1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 #include <linux/acpi.h>
30 #include <linux/pci.h>
31 #include <linux/slab.h>
32
33 #include <drm/drm_device.h>
34
35 #include "atom.h"
36 #include "radeon.h"
37 #include "radeon_reg.h"
38
39 /*
40 * BIOS.
41 */
42
43 /* If you boot an IGP board with a discrete card as the primary,
44 * the IGP rom is not accessible via the rom bar as the IGP rom is
45 * part of the system bios. On boot, the system bios puts a
46 * copy of the igp rom at the start of vram if a discrete card is
47 * present.
48 */
igp_read_bios_from_vram(struct radeon_device * rdev)49 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
50 {
51 uint8_t __iomem *bios;
52 uint8_t val1, val2;
53 resource_size_t vram_base;
54 resource_size_t size = 256 * 1024; /* ??? */
55
56 if (!(rdev->flags & RADEON_IS_IGP))
57 if (!radeon_card_posted(rdev))
58 return false;
59
60 rdev->bios = NULL;
61 vram_base = pci_resource_start(rdev->pdev, 0);
62 bios = ioremap(vram_base, size);
63 if (!bios) {
64 return false;
65 }
66
67 val1 = readb(&bios[0]);
68 val2 = readb(&bios[1]);
69
70 if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
71 iounmap(bios);
72 return false;
73 }
74 rdev->bios = kmalloc(size, GFP_KERNEL);
75 if (rdev->bios == NULL) {
76 iounmap(bios);
77 return false;
78 }
79 memcpy_fromio(rdev->bios, bios, size);
80 iounmap(bios);
81 return true;
82 }
83
radeon_read_bios(struct radeon_device * rdev)84 static bool radeon_read_bios(struct radeon_device *rdev)
85 {
86 uint8_t __iomem *bios, val1, val2;
87 size_t size;
88
89 rdev->bios = NULL;
90 /* XXX: some cards may return 0 for rom size? ddx has a workaround */
91 bios = pci_map_rom(rdev->pdev, &size);
92 if (!bios) {
93 return false;
94 }
95
96 val1 = readb(&bios[0]);
97 val2 = readb(&bios[1]);
98
99 if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
100 pci_unmap_rom(rdev->pdev, bios);
101 return false;
102 }
103 rdev->bios = kzalloc(size, GFP_KERNEL);
104 if (rdev->bios == NULL) {
105 pci_unmap_rom(rdev->pdev, bios);
106 return false;
107 }
108 memcpy_fromio(rdev->bios, bios, size);
109 pci_unmap_rom(rdev->pdev, bios);
110 return true;
111 }
112
radeon_read_platform_bios(struct radeon_device * rdev)113 static bool radeon_read_platform_bios(struct radeon_device *rdev)
114 {
115 phys_addr_t rom = rdev->pdev->rom;
116 size_t romlen = rdev->pdev->romlen;
117 void __iomem *bios;
118
119 rdev->bios = NULL;
120
121 if (!rom || romlen == 0)
122 return false;
123
124 rdev->bios = kzalloc(romlen, GFP_KERNEL);
125 if (!rdev->bios)
126 return false;
127
128 bios = ioremap(rom, romlen);
129 if (!bios)
130 goto free_bios;
131
132 memcpy_fromio(rdev->bios, bios, romlen);
133 iounmap(bios);
134
135 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa)
136 goto free_bios;
137
138 return true;
139 free_bios:
140 kfree(rdev->bios);
141 return false;
142 }
143
144 #ifdef CONFIG_ACPI
145 /* ATRM is used to get the BIOS on the discrete cards in
146 * dual-gpu systems.
147 */
148 /* retrieve the ROM in 4k blocks */
149 #define ATRM_BIOS_PAGE 4096
150 /**
151 * radeon_atrm_call - fetch a chunk of the vbios
152 *
153 * @atrm_handle: acpi ATRM handle
154 * @bios: vbios image pointer
155 * @offset: offset of vbios image data to fetch
156 * @len: length of vbios image data to fetch
157 *
158 * Executes ATRM to fetch a chunk of the discrete
159 * vbios image on PX systems (all asics).
160 * Returns the length of the buffer fetched.
161 */
radeon_atrm_call(acpi_handle atrm_handle,uint8_t * bios,int offset,int len)162 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
163 int offset, int len)
164 {
165 acpi_status status;
166 union acpi_object atrm_arg_elements[2], *obj;
167 struct acpi_object_list atrm_arg;
168 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
169
170 atrm_arg.count = 2;
171 atrm_arg.pointer = &atrm_arg_elements[0];
172
173 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
174 atrm_arg_elements[0].integer.value = offset;
175
176 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
177 atrm_arg_elements[1].integer.value = len;
178
179 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
180 if (ACPI_FAILURE(status)) {
181 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
182 return -ENODEV;
183 }
184
185 obj = (union acpi_object *)buffer.pointer;
186 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
187 len = obj->buffer.length;
188 kfree(buffer.pointer);
189 return len;
190 }
191
radeon_atrm_get_bios(struct radeon_device * rdev)192 static bool radeon_atrm_get_bios(struct radeon_device *rdev)
193 {
194 int ret;
195 int size = 256 * 1024;
196 int i;
197 struct pci_dev *pdev = NULL;
198 acpi_handle dhandle, atrm_handle;
199 acpi_status status;
200 bool found = false;
201
202 /* ATRM is for the discrete card only */
203 if (rdev->flags & RADEON_IS_IGP)
204 return false;
205
206 while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) {
207 if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) &&
208 (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8))
209 continue;
210
211 dhandle = ACPI_HANDLE(&pdev->dev);
212 if (!dhandle)
213 continue;
214
215 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
216 if (ACPI_SUCCESS(status)) {
217 found = true;
218 break;
219 }
220 }
221
222 if (!found)
223 return false;
224 pci_dev_put(pdev);
225
226 rdev->bios = kmalloc(size, GFP_KERNEL);
227 if (!rdev->bios) {
228 DRM_ERROR("Unable to allocate bios\n");
229 return false;
230 }
231
232 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
233 ret = radeon_atrm_call(atrm_handle,
234 rdev->bios,
235 (i * ATRM_BIOS_PAGE),
236 ATRM_BIOS_PAGE);
237 if (ret < ATRM_BIOS_PAGE)
238 break;
239 }
240
241 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
242 kfree(rdev->bios);
243 return false;
244 }
245 return true;
246 }
247 #else
radeon_atrm_get_bios(struct radeon_device * rdev)248 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
249 {
250 return false;
251 }
252 #endif
253
ni_read_disabled_bios(struct radeon_device * rdev)254 static bool ni_read_disabled_bios(struct radeon_device *rdev)
255 {
256 u32 bus_cntl;
257 u32 d1vga_control;
258 u32 d2vga_control;
259 u32 vga_render_control;
260 u32 rom_cntl;
261 bool r;
262
263 bus_cntl = RREG32(R600_BUS_CNTL);
264 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
265 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
266 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
267 rom_cntl = RREG32(R600_ROM_CNTL);
268
269 /* enable the rom */
270 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
271 if (!ASIC_IS_NODCE(rdev)) {
272 /* Disable VGA mode */
273 WREG32(AVIVO_D1VGA_CONTROL,
274 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
275 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
276 WREG32(AVIVO_D2VGA_CONTROL,
277 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
278 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
279 WREG32(AVIVO_VGA_RENDER_CONTROL,
280 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
281 }
282 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
283
284 r = radeon_read_bios(rdev);
285
286 /* restore regs */
287 WREG32(R600_BUS_CNTL, bus_cntl);
288 if (!ASIC_IS_NODCE(rdev)) {
289 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
290 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
291 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
292 }
293 WREG32(R600_ROM_CNTL, rom_cntl);
294 return r;
295 }
296
r700_read_disabled_bios(struct radeon_device * rdev)297 static bool r700_read_disabled_bios(struct radeon_device *rdev)
298 {
299 uint32_t viph_control;
300 uint32_t bus_cntl;
301 uint32_t d1vga_control;
302 uint32_t d2vga_control;
303 uint32_t vga_render_control;
304 uint32_t rom_cntl;
305 uint32_t cg_spll_func_cntl = 0;
306 uint32_t cg_spll_status;
307 bool r;
308
309 viph_control = RREG32(RADEON_VIPH_CONTROL);
310 bus_cntl = RREG32(R600_BUS_CNTL);
311 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
312 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
313 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
314 rom_cntl = RREG32(R600_ROM_CNTL);
315
316 /* disable VIP */
317 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
318 /* enable the rom */
319 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
320 /* Disable VGA mode */
321 WREG32(AVIVO_D1VGA_CONTROL,
322 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
323 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
324 WREG32(AVIVO_D2VGA_CONTROL,
325 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
326 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
327 WREG32(AVIVO_VGA_RENDER_CONTROL,
328 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
329
330 if (rdev->family == CHIP_RV730) {
331 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
332
333 /* enable bypass mode */
334 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
335 R600_SPLL_BYPASS_EN));
336
337 /* wait for SPLL_CHG_STATUS to change to 1 */
338 cg_spll_status = 0;
339 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
340 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
341
342 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
343 } else
344 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
345
346 r = radeon_read_bios(rdev);
347
348 /* restore regs */
349 if (rdev->family == CHIP_RV730) {
350 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
351
352 /* wait for SPLL_CHG_STATUS to change to 1 */
353 cg_spll_status = 0;
354 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
355 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
356 }
357 WREG32(RADEON_VIPH_CONTROL, viph_control);
358 WREG32(R600_BUS_CNTL, bus_cntl);
359 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
360 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
361 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
362 WREG32(R600_ROM_CNTL, rom_cntl);
363 return r;
364 }
365
r600_read_disabled_bios(struct radeon_device * rdev)366 static bool r600_read_disabled_bios(struct radeon_device *rdev)
367 {
368 uint32_t viph_control;
369 uint32_t bus_cntl;
370 uint32_t d1vga_control;
371 uint32_t d2vga_control;
372 uint32_t vga_render_control;
373 uint32_t rom_cntl;
374 uint32_t general_pwrmgt;
375 uint32_t low_vid_lower_gpio_cntl;
376 uint32_t medium_vid_lower_gpio_cntl;
377 uint32_t high_vid_lower_gpio_cntl;
378 uint32_t ctxsw_vid_lower_gpio_cntl;
379 uint32_t lower_gpio_enable;
380 bool r;
381
382 viph_control = RREG32(RADEON_VIPH_CONTROL);
383 bus_cntl = RREG32(R600_BUS_CNTL);
384 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
385 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
386 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
387 rom_cntl = RREG32(R600_ROM_CNTL);
388 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
389 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
390 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
391 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
392 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
393 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
394
395 /* disable VIP */
396 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
397 /* enable the rom */
398 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
399 /* Disable VGA mode */
400 WREG32(AVIVO_D1VGA_CONTROL,
401 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
402 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
403 WREG32(AVIVO_D2VGA_CONTROL,
404 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
405 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
406 WREG32(AVIVO_VGA_RENDER_CONTROL,
407 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
408
409 WREG32(R600_ROM_CNTL,
410 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
411 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
412 R600_SCK_OVERWRITE));
413
414 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
415 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
416 (low_vid_lower_gpio_cntl & ~0x400));
417 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
418 (medium_vid_lower_gpio_cntl & ~0x400));
419 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
420 (high_vid_lower_gpio_cntl & ~0x400));
421 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
422 (ctxsw_vid_lower_gpio_cntl & ~0x400));
423 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
424
425 r = radeon_read_bios(rdev);
426
427 /* restore regs */
428 WREG32(RADEON_VIPH_CONTROL, viph_control);
429 WREG32(R600_BUS_CNTL, bus_cntl);
430 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
431 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
432 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
433 WREG32(R600_ROM_CNTL, rom_cntl);
434 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
435 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
436 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
437 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
438 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
439 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
440 return r;
441 }
442
avivo_read_disabled_bios(struct radeon_device * rdev)443 static bool avivo_read_disabled_bios(struct radeon_device *rdev)
444 {
445 uint32_t seprom_cntl1;
446 uint32_t viph_control;
447 uint32_t bus_cntl;
448 uint32_t d1vga_control;
449 uint32_t d2vga_control;
450 uint32_t vga_render_control;
451 uint32_t gpiopad_a;
452 uint32_t gpiopad_en;
453 uint32_t gpiopad_mask;
454 bool r;
455
456 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
457 viph_control = RREG32(RADEON_VIPH_CONTROL);
458 bus_cntl = RREG32(RV370_BUS_CNTL);
459 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
460 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
461 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
462 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
463 gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
464 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
465
466 WREG32(RADEON_SEPROM_CNTL1,
467 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
468 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
469 WREG32(RADEON_GPIOPAD_A, 0);
470 WREG32(RADEON_GPIOPAD_EN, 0);
471 WREG32(RADEON_GPIOPAD_MASK, 0);
472
473 /* disable VIP */
474 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
475
476 /* enable the rom */
477 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
478
479 /* Disable VGA mode */
480 WREG32(AVIVO_D1VGA_CONTROL,
481 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
482 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
483 WREG32(AVIVO_D2VGA_CONTROL,
484 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
485 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
486 WREG32(AVIVO_VGA_RENDER_CONTROL,
487 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
488
489 r = radeon_read_bios(rdev);
490
491 /* restore regs */
492 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
493 WREG32(RADEON_VIPH_CONTROL, viph_control);
494 WREG32(RV370_BUS_CNTL, bus_cntl);
495 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
496 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
497 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
498 WREG32(RADEON_GPIOPAD_A, gpiopad_a);
499 WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
500 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
501 return r;
502 }
503
legacy_read_disabled_bios(struct radeon_device * rdev)504 static bool legacy_read_disabled_bios(struct radeon_device *rdev)
505 {
506 uint32_t seprom_cntl1;
507 uint32_t viph_control;
508 uint32_t bus_cntl;
509 uint32_t crtc_gen_cntl;
510 uint32_t crtc2_gen_cntl;
511 uint32_t crtc_ext_cntl;
512 uint32_t fp2_gen_cntl;
513 bool r;
514
515 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
516 viph_control = RREG32(RADEON_VIPH_CONTROL);
517 if (rdev->flags & RADEON_IS_PCIE)
518 bus_cntl = RREG32(RV370_BUS_CNTL);
519 else
520 bus_cntl = RREG32(RADEON_BUS_CNTL);
521 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
522 crtc2_gen_cntl = 0;
523 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
524 fp2_gen_cntl = 0;
525
526 if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
527 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
528 }
529
530 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
531 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
532 }
533
534 WREG32(RADEON_SEPROM_CNTL1,
535 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
536 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
537
538 /* disable VIP */
539 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
540
541 /* enable the rom */
542 if (rdev->flags & RADEON_IS_PCIE)
543 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
544 else
545 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
546
547 /* Turn off mem requests and CRTC for both controllers */
548 WREG32(RADEON_CRTC_GEN_CNTL,
549 ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
550 (RADEON_CRTC_DISP_REQ_EN_B |
551 RADEON_CRTC_EXT_DISP_EN)));
552 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
553 WREG32(RADEON_CRTC2_GEN_CNTL,
554 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
555 RADEON_CRTC2_DISP_REQ_EN_B));
556 }
557 /* Turn off CRTC */
558 WREG32(RADEON_CRTC_EXT_CNTL,
559 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
560 (RADEON_CRTC_SYNC_TRISTAT |
561 RADEON_CRTC_DISPLAY_DIS)));
562
563 if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
564 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
565 }
566
567 r = radeon_read_bios(rdev);
568
569 /* restore regs */
570 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
571 WREG32(RADEON_VIPH_CONTROL, viph_control);
572 if (rdev->flags & RADEON_IS_PCIE)
573 WREG32(RV370_BUS_CNTL, bus_cntl);
574 else
575 WREG32(RADEON_BUS_CNTL, bus_cntl);
576 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
577 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
578 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
579 }
580 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
581 if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
582 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
583 }
584 return r;
585 }
586
radeon_read_disabled_bios(struct radeon_device * rdev)587 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
588 {
589 if (rdev->flags & RADEON_IS_IGP)
590 return igp_read_bios_from_vram(rdev);
591 else if (rdev->family >= CHIP_BARTS)
592 return ni_read_disabled_bios(rdev);
593 else if (rdev->family >= CHIP_RV770)
594 return r700_read_disabled_bios(rdev);
595 else if (rdev->family >= CHIP_R600)
596 return r600_read_disabled_bios(rdev);
597 else if (rdev->family >= CHIP_RS600)
598 return avivo_read_disabled_bios(rdev);
599 else
600 return legacy_read_disabled_bios(rdev);
601 }
602
603 #ifdef CONFIG_ACPI
604 /**
605 * radeon_acpi_vfct_match() - Check if a VFCT entry matches the device
606 * @rdev: Radeon device
607 * @vhdr: VFCT image header to check
608 *
609 * VFCT entries contain the PCI bus number as recorded during BIOS POST.
610 * On systems where the kernel renumbers PCI buses (e.g. pci=realloc or
611 * resource conflicts), the runtime bus number may differ from the POST
612 * value. Match by device identity (vendor + device + function) and use
613 * the bus number as a preference: exact bus match is preferred, but when
614 * the bus numbers disagree we accept the entry if the device identity
615 * matches.
616 *
617 * Returns: 0 on match, -ENODEV on no match
618 */
radeon_acpi_vfct_match(struct radeon_device * rdev,VFCT_IMAGE_HEADER * vhdr)619 static int radeon_acpi_vfct_match(struct radeon_device *rdev,
620 VFCT_IMAGE_HEADER *vhdr)
621 {
622 /* Vendor and device IDs must always match */
623 if (vhdr->VendorID != rdev->pdev->vendor ||
624 vhdr->DeviceID != rdev->pdev->device)
625 return -ENODEV;
626
627 if (vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) ||
628 vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn))
629 return -ENODEV;
630
631 /* Exact bus number match - preferred */
632 if (vhdr->PCIBus == rdev->pdev->bus->number)
633 return 0;
634
635 /* Bus mismatch but device identity matches (PCI renumbering case) */
636 dev_notice(&rdev->pdev->dev,
637 "VFCT bus number mismatch: table %u != runtime %u, matching by device identity (vendor 0x%04x device 0x%04x)\n",
638 vhdr->PCIBus, rdev->pdev->bus->number,
639 rdev->pdev->vendor, rdev->pdev->device);
640 return 0;
641 }
642
radeon_acpi_vfct_bios(struct radeon_device * rdev)643 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
644 {
645 struct acpi_table_header *hdr;
646 acpi_size tbl_size;
647 UEFI_ACPI_VFCT *vfct;
648 unsigned int offset;
649 bool r = false;
650
651 if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr)))
652 return false;
653 tbl_size = hdr->length;
654 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
655 dev_warn(&rdev->pdev->dev, "ACPI VFCT table present but broken (too short #1),skipping\n");
656 goto out;
657 }
658
659 vfct = (UEFI_ACPI_VFCT *)hdr;
660 offset = vfct->VBIOSImageOffset;
661
662 while (offset < tbl_size) {
663 GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + offset);
664 VFCT_IMAGE_HEADER *vhdr = &vbios->VbiosHeader;
665
666 offset += sizeof(VFCT_IMAGE_HEADER);
667 if (offset > tbl_size) {
668 dev_warn(&rdev->pdev->dev, "ACPI VFCT image header truncated,skipping\n");
669 goto out;
670 }
671
672 offset += vhdr->ImageLength;
673 if (offset > tbl_size) {
674 dev_warn(&rdev->pdev->dev, "ACPI VFCT image truncated,skipping\n");
675 goto out;
676 }
677
678 if (vhdr->ImageLength &&
679 !radeon_acpi_vfct_match(rdev, vhdr)) {
680 rdev->bios = kmemdup(&vbios->VbiosContent,
681 vhdr->ImageLength,
682 GFP_KERNEL);
683
684 if (!rdev->bios ||
685 rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
686 kfree(rdev->bios);
687 rdev->bios = NULL;
688 goto out;
689 }
690 r = true;
691 goto out;
692 }
693 }
694
695 dev_warn(&rdev->pdev->dev, "ACPI VFCT table present but broken (too short #2),skipping\n");
696
697 out:
698 acpi_put_table(hdr);
699 return r;
700 }
701 #else
radeon_acpi_vfct_bios(struct radeon_device * rdev)702 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
703 {
704 return false;
705 }
706 #endif
707
radeon_get_bios(struct radeon_device * rdev)708 bool radeon_get_bios(struct radeon_device *rdev)
709 {
710 bool r;
711 uint16_t tmp;
712
713 r = radeon_atrm_get_bios(rdev);
714 if (!r)
715 r = radeon_acpi_vfct_bios(rdev);
716 if (!r)
717 r = igp_read_bios_from_vram(rdev);
718 if (!r)
719 r = radeon_read_bios(rdev);
720 if (!r)
721 r = radeon_read_disabled_bios(rdev);
722 if (!r)
723 r = radeon_read_platform_bios(rdev);
724 if (!r || rdev->bios == NULL) {
725 DRM_ERROR("Unable to locate a BIOS ROM\n");
726 rdev->bios = NULL;
727 return false;
728 }
729 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
730 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
731 goto free_bios;
732 }
733
734 tmp = RBIOS16(0x18);
735 if (RBIOS8(tmp + 0x14) != 0x0) {
736 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
737 goto free_bios;
738 }
739
740 rdev->bios_header_start = RBIOS16(0x48);
741 if (!rdev->bios_header_start) {
742 goto free_bios;
743 }
744 tmp = rdev->bios_header_start + 4;
745 if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
746 !memcmp(rdev->bios + tmp, "MOTA", 4)) {
747 rdev->is_atom_bios = true;
748 } else {
749 rdev->is_atom_bios = false;
750 }
751
752 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
753 return true;
754 free_bios:
755 kfree(rdev->bios);
756 rdev->bios = NULL;
757 return false;
758 }
759