1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * DRA7 ATL (Audio Tracking Logic) clock driver
4 *
5 * Copyright (C) 2013 Texas Instruments, Inc.
6 *
7 * Peter Ujfalusi <peter.ujfalusi@ti.com>
8 */
9
10 #include <linux/init.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/slab.h>
14 #include <linux/io.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/clk/ti.h>
20
21 #include "clock.h"
22
23 #define DRA7_ATL_INSTANCES 4
24
25 #define DRA7_ATL_PPMR_REG(id) (0x200 + (id * 0x80))
26 #define DRA7_ATL_BBSR_REG(id) (0x204 + (id * 0x80))
27 #define DRA7_ATL_ATLCR_REG(id) (0x208 + (id * 0x80))
28 #define DRA7_ATL_SWEN_REG(id) (0x210 + (id * 0x80))
29 #define DRA7_ATL_BWSMUX_REG(id) (0x214 + (id * 0x80))
30 #define DRA7_ATL_AWSMUX_REG(id) (0x218 + (id * 0x80))
31 #define DRA7_ATL_PCLKMUX_REG(id) (0x21c + (id * 0x80))
32
33 #define DRA7_ATL_SWEN BIT(0)
34 #define DRA7_ATL_DIVIDER_MASK (0x1f)
35 #define DRA7_ATL_PCLKMUX BIT(0)
36 struct dra7_atl_clock_info;
37
38 struct dra7_atl_desc {
39 struct clk *clk;
40 struct clk_hw hw;
41 struct dra7_atl_clock_info *cinfo;
42 int id;
43
44 bool probed; /* the driver for the IP has been loaded */
45 bool valid; /* configured */
46 bool enabled;
47 u32 bws; /* Baseband Word Select Mux */
48 u32 aws; /* Audio Word Select Mux */
49 u32 divider; /* Cached divider value */
50 };
51
52 struct dra7_atl_clock_info {
53 struct device *dev;
54 void __iomem *iobase;
55
56 struct dra7_atl_desc *cdesc;
57 };
58
59 #define to_atl_desc(_hw) container_of(_hw, struct dra7_atl_desc, hw)
60
atl_write(struct dra7_atl_clock_info * cinfo,u32 reg,u32 val)61 static inline void atl_write(struct dra7_atl_clock_info *cinfo, u32 reg,
62 u32 val)
63 {
64 __raw_writel(val, cinfo->iobase + reg);
65 }
66
atl_read(struct dra7_atl_clock_info * cinfo,u32 reg)67 static inline int atl_read(struct dra7_atl_clock_info *cinfo, u32 reg)
68 {
69 return __raw_readl(cinfo->iobase + reg);
70 }
71
atl_clk_enable(struct clk_hw * hw)72 static int atl_clk_enable(struct clk_hw *hw)
73 {
74 struct dra7_atl_desc *cdesc = to_atl_desc(hw);
75
76 if (!cdesc->probed)
77 goto out;
78
79 if (unlikely(!cdesc->valid))
80 dev_warn(cdesc->cinfo->dev, "atl%d has not been configured\n",
81 cdesc->id);
82 pm_runtime_get_sync(cdesc->cinfo->dev);
83
84 atl_write(cdesc->cinfo, DRA7_ATL_ATLCR_REG(cdesc->id),
85 cdesc->divider - 1);
86 atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), DRA7_ATL_SWEN);
87
88 out:
89 cdesc->enabled = true;
90
91 return 0;
92 }
93
atl_clk_disable(struct clk_hw * hw)94 static void atl_clk_disable(struct clk_hw *hw)
95 {
96 struct dra7_atl_desc *cdesc = to_atl_desc(hw);
97
98 if (!cdesc->probed)
99 goto out;
100
101 atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), 0);
102 pm_runtime_put_sync(cdesc->cinfo->dev);
103
104 out:
105 cdesc->enabled = false;
106 }
107
atl_clk_is_enabled(struct clk_hw * hw)108 static int atl_clk_is_enabled(struct clk_hw *hw)
109 {
110 struct dra7_atl_desc *cdesc = to_atl_desc(hw);
111
112 return cdesc->enabled;
113 }
114
atl_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)115 static unsigned long atl_clk_recalc_rate(struct clk_hw *hw,
116 unsigned long parent_rate)
117 {
118 struct dra7_atl_desc *cdesc = to_atl_desc(hw);
119
120 return parent_rate / cdesc->divider;
121 }
122
atl_clk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)123 static int atl_clk_determine_rate(struct clk_hw *hw,
124 struct clk_rate_request *req)
125 {
126 unsigned divider;
127
128 divider = (req->best_parent_rate + req->rate / 2) / req->rate;
129 if (divider > DRA7_ATL_DIVIDER_MASK + 1)
130 divider = DRA7_ATL_DIVIDER_MASK + 1;
131
132 req->rate = req->best_parent_rate / divider;
133
134 return 0;
135 }
136
atl_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)137 static int atl_clk_set_rate(struct clk_hw *hw, unsigned long rate,
138 unsigned long parent_rate)
139 {
140 struct dra7_atl_desc *cdesc;
141 u32 divider;
142
143 if (!hw || !rate)
144 return -EINVAL;
145
146 cdesc = to_atl_desc(hw);
147 divider = ((parent_rate + rate / 2) / rate) - 1;
148 if (divider > DRA7_ATL_DIVIDER_MASK)
149 divider = DRA7_ATL_DIVIDER_MASK;
150
151 cdesc->divider = divider + 1;
152
153 return 0;
154 }
155
156 static const struct clk_ops atl_clk_ops = {
157 .enable = atl_clk_enable,
158 .disable = atl_clk_disable,
159 .is_enabled = atl_clk_is_enabled,
160 .recalc_rate = atl_clk_recalc_rate,
161 .determine_rate = atl_clk_determine_rate,
162 .set_rate = atl_clk_set_rate,
163 };
164
of_dra7_atl_clock_setup(struct device_node * node)165 static void __init of_dra7_atl_clock_setup(struct device_node *node)
166 {
167 struct dra7_atl_desc *clk_hw = NULL;
168 struct clk_parent_data pdata = { .index = 0 };
169 struct clk_init_data init = { NULL };
170 const char *name;
171 struct clk *clk;
172
173 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
174 if (!clk_hw) {
175 pr_err("%s: could not allocate dra7_atl_desc\n", __func__);
176 return;
177 }
178
179 clk_hw->hw.init = &init;
180 clk_hw->divider = 1;
181 name = ti_dt_clk_name(node);
182 init.name = name;
183 init.ops = &atl_clk_ops;
184 init.flags = CLK_IGNORE_UNUSED;
185 init.num_parents = of_clk_get_parent_count(node);
186
187 if (init.num_parents != 1) {
188 pr_err("%s: atl clock %pOFn must have 1 parent\n", __func__,
189 node);
190 goto cleanup;
191 }
192
193 init.parent_data = &pdata;
194 clk = of_ti_clk_register(node, &clk_hw->hw, name);
195
196 if (!IS_ERR(clk)) {
197 of_clk_add_provider(node, of_clk_src_simple_get, clk);
198 return;
199 }
200 cleanup:
201 kfree(clk_hw);
202 }
203 CLK_OF_DECLARE(dra7_atl_clock, "ti,dra7-atl-clock", of_dra7_atl_clock_setup);
204
of_dra7_atl_clk_probe(struct platform_device * pdev)205 static int of_dra7_atl_clk_probe(struct platform_device *pdev)
206 {
207 struct device_node *node = pdev->dev.of_node;
208 struct dra7_atl_clock_info *cinfo;
209 int i;
210 int ret = 0;
211
212 if (!node)
213 return -ENODEV;
214
215 cinfo = devm_kzalloc(&pdev->dev, sizeof(*cinfo), GFP_KERNEL);
216 if (!cinfo)
217 return -ENOMEM;
218
219 cinfo->iobase = of_iomap(node, 0);
220 cinfo->dev = &pdev->dev;
221 pm_runtime_enable(cinfo->dev);
222
223 pm_runtime_get_sync(cinfo->dev);
224 atl_write(cinfo, DRA7_ATL_PCLKMUX_REG(0), DRA7_ATL_PCLKMUX);
225
226 for (i = 0; i < DRA7_ATL_INSTANCES; i++) {
227 struct device_node *cfg_node;
228 char prop[5];
229 struct dra7_atl_desc *cdesc;
230 struct of_phandle_args clkspec;
231 struct clk *clk;
232 int rc;
233
234 rc = of_parse_phandle_with_args(node, "ti,provided-clocks",
235 NULL, i, &clkspec);
236
237 if (rc) {
238 pr_err("%s: failed to lookup atl clock %d\n", __func__,
239 i);
240 ret = -EINVAL;
241 goto pm_put;
242 }
243
244 clk = of_clk_get_from_provider(&clkspec);
245 of_node_put(clkspec.np);
246 if (IS_ERR(clk)) {
247 pr_err("%s: failed to get atl clock %d from provider\n",
248 __func__, i);
249 ret = PTR_ERR(clk);
250 goto pm_put;
251 }
252
253 cdesc = to_atl_desc(__clk_get_hw(clk));
254 cdesc->cinfo = cinfo;
255 cdesc->id = i;
256
257 /* Get configuration for the ATL instances */
258 snprintf(prop, sizeof(prop), "atl%u", i);
259 cfg_node = of_get_child_by_name(node, prop);
260 if (cfg_node) {
261 ret = of_property_read_u32(cfg_node, "bws",
262 &cdesc->bws);
263 ret |= of_property_read_u32(cfg_node, "aws",
264 &cdesc->aws);
265 if (!ret) {
266 cdesc->valid = true;
267 atl_write(cinfo, DRA7_ATL_BWSMUX_REG(i),
268 cdesc->bws);
269 atl_write(cinfo, DRA7_ATL_AWSMUX_REG(i),
270 cdesc->aws);
271 }
272 of_node_put(cfg_node);
273 }
274
275 cdesc->probed = true;
276 /*
277 * Enable the clock if it has been asked prior to loading the
278 * hw driver
279 */
280 if (cdesc->enabled)
281 atl_clk_enable(__clk_get_hw(clk));
282 }
283
284 pm_put:
285 pm_runtime_put_sync(cinfo->dev);
286 return ret;
287 }
288
289 static const struct of_device_id of_dra7_atl_clk_match_tbl[] = {
290 { .compatible = "ti,dra7-atl", },
291 {},
292 };
293
294 static struct platform_driver dra7_atl_clk_driver = {
295 .driver = {
296 .name = "dra7-atl",
297 .suppress_bind_attrs = true,
298 .of_match_table = of_dra7_atl_clk_match_tbl,
299 },
300 .probe = of_dra7_atl_clk_probe,
301 };
302 builtin_platform_driver(dra7_atl_clk_driver);
303