1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
4 *
5 * Derived from Intel e1000 driver
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 */
8 #include <linux/pci.h>
9 #include <linux/delay.h>
10 #include <linux/mii.h>
11 #include <linux/crc32.h>
12
13 #include "atl1e.h"
14
15 /*
16 * check_eeprom_exist
17 * return 0 if eeprom exist
18 */
atl1e_check_eeprom_exist(struct atl1e_hw * hw)19 int atl1e_check_eeprom_exist(struct atl1e_hw *hw)
20 {
21 u32 value;
22
23 value = AT_READ_REG(hw, REG_SPI_FLASH_CTRL);
24 if (value & SPI_FLASH_CTRL_EN_VPD) {
25 value &= ~SPI_FLASH_CTRL_EN_VPD;
26 AT_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
27 }
28 value = AT_READ_REGW(hw, REG_PCIE_CAP_LIST);
29 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
30 }
31
atl1e_hw_set_mac_addr(struct atl1e_hw * hw)32 void atl1e_hw_set_mac_addr(struct atl1e_hw *hw)
33 {
34 u32 value;
35 /*
36 * 00-0B-6A-F6-00-DC
37 * 0: 6AF600DC 1: 000B
38 * low dword
39 */
40 value = (((u32)hw->mac_addr[2]) << 24) |
41 (((u32)hw->mac_addr[3]) << 16) |
42 (((u32)hw->mac_addr[4]) << 8) |
43 (((u32)hw->mac_addr[5])) ;
44 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
45 /* hight dword */
46 value = (((u32)hw->mac_addr[0]) << 8) |
47 (((u32)hw->mac_addr[1])) ;
48 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
49 }
50
51 /*
52 * atl1e_get_permanent_address
53 * return 0 if get valid mac address,
54 */
atl1e_get_permanent_address(struct atl1e_hw * hw)55 static int atl1e_get_permanent_address(struct atl1e_hw *hw)
56 {
57 u32 addr[2];
58 u32 i;
59 u32 twsi_ctrl_data;
60 u8 eth_addr[ETH_ALEN];
61
62 if (is_valid_ether_addr(hw->perm_mac_addr))
63 return 0;
64
65 /* init */
66 addr[0] = addr[1] = 0;
67
68 if (!atl1e_check_eeprom_exist(hw)) {
69 /* eeprom exist */
70 twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL);
71 twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART;
72 AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data);
73 for (i = 0; i < AT_TWSI_EEPROM_TIMEOUT; i++) {
74 msleep(10);
75 twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL);
76 if ((twsi_ctrl_data & TWSI_CTRL_SW_LDSTART) == 0)
77 break;
78 }
79 if (i >= AT_TWSI_EEPROM_TIMEOUT)
80 return AT_ERR_TIMEOUT;
81 }
82
83 /* maybe MAC-address is from BIOS */
84 addr[0] = AT_READ_REG(hw, REG_MAC_STA_ADDR);
85 addr[1] = AT_READ_REG(hw, REG_MAC_STA_ADDR + 4);
86 *(u32 *) ð_addr[2] = swab32(addr[0]);
87 *(u16 *) ð_addr[0] = swab16(*(u16 *)&addr[1]);
88
89 if (is_valid_ether_addr(eth_addr)) {
90 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
91 return 0;
92 }
93
94 return AT_ERR_EEPROM;
95 }
96
atl1e_write_eeprom(struct atl1e_hw * hw,u32 offset,u32 value)97 bool atl1e_write_eeprom(struct atl1e_hw *hw, u32 offset, u32 value)
98 {
99 return true;
100 }
101
atl1e_read_eeprom(struct atl1e_hw * hw,u32 offset,u32 * p_value)102 bool atl1e_read_eeprom(struct atl1e_hw *hw, u32 offset, u32 *p_value)
103 {
104 int i;
105 u32 control;
106
107 if (offset & 3)
108 return false; /* address do not align */
109
110 AT_WRITE_REG(hw, REG_VPD_DATA, 0);
111 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
112 AT_WRITE_REG(hw, REG_VPD_CAP, control);
113
114 for (i = 0; i < 10; i++) {
115 msleep(2);
116 control = AT_READ_REG(hw, REG_VPD_CAP);
117 if (control & VPD_CAP_VPD_FLAG)
118 break;
119 }
120 if (control & VPD_CAP_VPD_FLAG) {
121 *p_value = AT_READ_REG(hw, REG_VPD_DATA);
122 return true;
123 }
124 return false; /* timeout */
125 }
126
atl1e_force_ps(struct atl1e_hw * hw)127 void atl1e_force_ps(struct atl1e_hw *hw)
128 {
129 AT_WRITE_REGW(hw, REG_GPHY_CTRL,
130 GPHY_CTRL_PW_WOL_DIS | GPHY_CTRL_EXT_RESET);
131 }
132
133 /*
134 * Reads the adapter's MAC address from the EEPROM
135 *
136 * hw - Struct containing variables accessed by shared code
137 */
atl1e_read_mac_addr(struct atl1e_hw * hw)138 int atl1e_read_mac_addr(struct atl1e_hw *hw)
139 {
140 int err = 0;
141
142 err = atl1e_get_permanent_address(hw);
143 if (err)
144 return AT_ERR_EEPROM;
145 memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr));
146 return 0;
147 }
148
149 /*
150 * atl1e_hash_mc_addr
151 * purpose
152 * set hash value for a multicast address
153 */
atl1e_hash_mc_addr(struct atl1e_hw * hw,u8 * mc_addr)154 u32 atl1e_hash_mc_addr(struct atl1e_hw *hw, u8 *mc_addr)
155 {
156 u32 crc32;
157 u32 value = 0;
158 int i;
159
160 crc32 = ether_crc_le(6, mc_addr);
161 for (i = 0; i < 32; i++)
162 value |= (((crc32 >> i) & 1) << (31 - i));
163
164 return value;
165 }
166
167 /*
168 * Sets the bit in the multicast table corresponding to the hash value.
169 * hw - Struct containing variables accessed by shared code
170 * hash_value - Multicast address hash value
171 */
atl1e_hash_set(struct atl1e_hw * hw,u32 hash_value)172 void atl1e_hash_set(struct atl1e_hw *hw, u32 hash_value)
173 {
174 u32 hash_bit, hash_reg;
175 u32 mta;
176
177 /*
178 * The HASH Table is a register array of 2 32-bit registers.
179 * It is treated like an array of 64 bits. We want to set
180 * bit BitArray[hash_value]. So we figure out what register
181 * the bit is in, read it, OR in the new bit, then write
182 * back the new value. The register is determined by the
183 * upper 7 bits of the hash value and the bit within that
184 * register are determined by the lower 5 bits of the value.
185 */
186 hash_reg = (hash_value >> 31) & 0x1;
187 hash_bit = (hash_value >> 26) & 0x1F;
188
189 mta = AT_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
190
191 mta |= (1 << hash_bit);
192
193 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
194 }
195 /*
196 * Reads the value from a PHY register
197 * hw - Struct containing variables accessed by shared code
198 * reg_addr - address of the PHY register to read
199 */
atl1e_read_phy_reg(struct atl1e_hw * hw,u16 reg_addr,u16 * phy_data)200 int atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data)
201 {
202 u32 val;
203 int i;
204
205 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
206 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW |
207 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
208
209 AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
210
211 wmb();
212
213 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
214 udelay(2);
215 val = AT_READ_REG(hw, REG_MDIO_CTRL);
216 if (!(val & (MDIO_START | MDIO_BUSY)))
217 break;
218 wmb();
219 }
220 if (!(val & (MDIO_START | MDIO_BUSY))) {
221 *phy_data = (u16)val;
222 return 0;
223 }
224
225 return AT_ERR_PHY;
226 }
227
228 /*
229 * Writes a value to a PHY register
230 * hw - Struct containing variables accessed by shared code
231 * reg_addr - address of the PHY register to write
232 * data - data to write to the PHY
233 */
atl1e_write_phy_reg(struct atl1e_hw * hw,u32 reg_addr,u16 phy_data)234 int atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data)
235 {
236 int i;
237 u32 val;
238
239 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
240 (reg_addr&MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
241 MDIO_SUP_PREAMBLE |
242 MDIO_START |
243 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
244
245 AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
246 wmb();
247
248 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
249 udelay(2);
250 val = AT_READ_REG(hw, REG_MDIO_CTRL);
251 if (!(val & (MDIO_START | MDIO_BUSY)))
252 break;
253 wmb();
254 }
255
256 if (!(val & (MDIO_START | MDIO_BUSY)))
257 return 0;
258
259 return AT_ERR_PHY;
260 }
261
262 /*
263 * atl1e_init_pcie - init PCIE module
264 */
atl1e_init_pcie(struct atl1e_hw * hw)265 static void atl1e_init_pcie(struct atl1e_hw *hw)
266 {
267 u32 value;
268 /* comment 2lines below to save more power when sususpend
269 value = LTSSM_TEST_MODE_DEF;
270 AT_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
271 */
272
273 /* pcie flow control mode change */
274 value = AT_READ_REG(hw, 0x1008);
275 value |= 0x8000;
276 AT_WRITE_REG(hw, 0x1008, value);
277 }
278 /*
279 * Configures PHY autoneg and flow control advertisement settings
280 *
281 * hw - Struct containing variables accessed by shared code
282 */
atl1e_phy_setup_autoneg_adv(struct atl1e_hw * hw)283 static int atl1e_phy_setup_autoneg_adv(struct atl1e_hw *hw)
284 {
285 s32 ret_val;
286 u16 mii_autoneg_adv_reg;
287 u16 mii_1000t_ctrl_reg;
288
289 if (0 != hw->mii_autoneg_adv_reg)
290 return 0;
291 /* Read the MII Auto-Neg Advertisement Register (Address 4/9). */
292 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
293 mii_1000t_ctrl_reg = MII_AT001_CR_1000T_DEFAULT_CAP_MASK;
294
295 /*
296 * Need to parse autoneg_advertised and set up
297 * the appropriate PHY registers. First we will parse for
298 * autoneg_advertised software override. Since we can advertise
299 * a plethora of combinations, we need to check each bit
300 * individually.
301 */
302
303 /*
304 * First we clear all the 10/100 mb speed bits in the Auto-Neg
305 * Advertisement Register (Address 4) and the 1000 mb speed bits in
306 * the 1000Base-T control Register (Address 9).
307 */
308 mii_autoneg_adv_reg &= ~ADVERTISE_ALL;
309 mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK;
310
311 /*
312 * Need to parse MediaType and setup the
313 * appropriate PHY registers.
314 */
315 switch (hw->media_type) {
316 case MEDIA_TYPE_AUTO_SENSOR:
317 mii_autoneg_adv_reg |= ADVERTISE_ALL;
318 hw->autoneg_advertised = ADVERTISE_ALL;
319 if (hw->nic_type == athr_l1e) {
320 mii_1000t_ctrl_reg |= ADVERTISE_1000FULL;
321 hw->autoneg_advertised |= ADVERTISE_1000_FULL;
322 }
323 break;
324
325 case MEDIA_TYPE_100M_FULL:
326 mii_autoneg_adv_reg |= ADVERTISE_100FULL;
327 hw->autoneg_advertised = ADVERTISE_100_FULL;
328 break;
329
330 case MEDIA_TYPE_100M_HALF:
331 mii_autoneg_adv_reg |= ADVERTISE_100_HALF;
332 hw->autoneg_advertised = ADVERTISE_100_HALF;
333 break;
334
335 case MEDIA_TYPE_10M_FULL:
336 mii_autoneg_adv_reg |= ADVERTISE_10_FULL;
337 hw->autoneg_advertised = ADVERTISE_10_FULL;
338 break;
339
340 default:
341 mii_autoneg_adv_reg |= ADVERTISE_10_HALF;
342 hw->autoneg_advertised = ADVERTISE_10_HALF;
343 break;
344 }
345
346 /* flow control fixed to enable all */
347 mii_autoneg_adv_reg |= (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
348
349 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
350 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
351
352 ret_val = atl1e_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
353 if (ret_val)
354 return ret_val;
355
356 if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) {
357 ret_val = atl1e_write_phy_reg(hw, MII_CTRL1000,
358 mii_1000t_ctrl_reg);
359 if (ret_val)
360 return ret_val;
361 }
362
363 return 0;
364 }
365
366
367 /*
368 * Resets the PHY and make all config validate
369 *
370 * hw - Struct containing variables accessed by shared code
371 *
372 * Sets bit 15 and 12 of the MII control regiser (for F001 bug)
373 */
atl1e_phy_commit(struct atl1e_hw * hw)374 int atl1e_phy_commit(struct atl1e_hw *hw)
375 {
376 struct atl1e_adapter *adapter = hw->adapter;
377 int ret_val;
378 u16 phy_data;
379
380 phy_data = BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART;
381
382 ret_val = atl1e_write_phy_reg(hw, MII_BMCR, phy_data);
383 if (ret_val) {
384 u32 val;
385 int i;
386 /**************************************
387 * pcie serdes link may be down !
388 **************************************/
389 for (i = 0; i < 25; i++) {
390 msleep(1);
391 val = AT_READ_REG(hw, REG_MDIO_CTRL);
392 if (!(val & (MDIO_START | MDIO_BUSY)))
393 break;
394 }
395
396 if (0 != (val & (MDIO_START | MDIO_BUSY))) {
397 netdev_err(adapter->netdev,
398 "pcie linkdown at least for 25ms\n");
399 return ret_val;
400 }
401
402 netdev_err(adapter->netdev, "pcie linkup after %d ms\n", i);
403 }
404 return 0;
405 }
406
atl1e_phy_init(struct atl1e_hw * hw)407 int atl1e_phy_init(struct atl1e_hw *hw)
408 {
409 struct atl1e_adapter *adapter = hw->adapter;
410 s32 ret_val;
411 u16 phy_val;
412
413 if (hw->phy_configured) {
414 if (hw->re_autoneg) {
415 hw->re_autoneg = false;
416 return atl1e_restart_autoneg(hw);
417 }
418 return 0;
419 }
420
421 /* RESET GPHY Core */
422 AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT);
423 msleep(2);
424 AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT |
425 GPHY_CTRL_EXT_RESET);
426 msleep(2);
427
428 /* patches */
429 /* p1. eable hibernation mode */
430 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0xB);
431 if (ret_val)
432 return ret_val;
433 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0xBC00);
434 if (ret_val)
435 return ret_val;
436 /* p2. set Class A/B for all modes */
437 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0);
438 if (ret_val)
439 return ret_val;
440 phy_val = 0x02ef;
441 /* remove Class AB */
442 /* phy_val = hw->emi_ca ? 0x02ef : 0x02df; */
443 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, phy_val);
444 if (ret_val)
445 return ret_val;
446 /* p3. 10B ??? */
447 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x12);
448 if (ret_val)
449 return ret_val;
450 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x4C04);
451 if (ret_val)
452 return ret_val;
453 /* p4. 1000T power */
454 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x4);
455 if (ret_val)
456 return ret_val;
457 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x8BBB);
458 if (ret_val)
459 return ret_val;
460
461 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x5);
462 if (ret_val)
463 return ret_val;
464 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x2C46);
465 if (ret_val)
466 return ret_val;
467
468 msleep(1);
469
470 /*Enable PHY LinkChange Interrupt */
471 ret_val = atl1e_write_phy_reg(hw, MII_INT_CTRL, 0xC00);
472 if (ret_val) {
473 netdev_err(adapter->netdev,
474 "Error enable PHY linkChange Interrupt\n");
475 return ret_val;
476 }
477 /* setup AutoNeg parameters */
478 ret_val = atl1e_phy_setup_autoneg_adv(hw);
479 if (ret_val) {
480 netdev_err(adapter->netdev,
481 "Error Setting up Auto-Negotiation\n");
482 return ret_val;
483 }
484 /* SW.Reset & En-Auto-Neg to restart Auto-Neg*/
485 netdev_dbg(adapter->netdev, "Restarting Auto-Negotiation\n");
486 ret_val = atl1e_phy_commit(hw);
487 if (ret_val) {
488 netdev_err(adapter->netdev, "Error resetting the phy\n");
489 return ret_val;
490 }
491
492 hw->phy_configured = true;
493
494 return 0;
495 }
496
497 /*
498 * Reset the transmit and receive units; mask and clear all interrupts.
499 * hw - Struct containing variables accessed by shared code
500 * return : 0 or idle status (if error)
501 */
atl1e_reset_hw(struct atl1e_hw * hw)502 int atl1e_reset_hw(struct atl1e_hw *hw)
503 {
504 struct atl1e_adapter *adapter = hw->adapter;
505 struct pci_dev *pdev = adapter->pdev;
506
507 u32 idle_status_data = 0;
508 u16 pci_cfg_cmd_word = 0;
509 int timeout = 0;
510
511 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
512 pci_read_config_word(pdev, PCI_REG_COMMAND, &pci_cfg_cmd_word);
513 if ((pci_cfg_cmd_word & (CMD_IO_SPACE |
514 CMD_MEMORY_SPACE | CMD_BUS_MASTER))
515 != (CMD_IO_SPACE | CMD_MEMORY_SPACE | CMD_BUS_MASTER)) {
516 pci_cfg_cmd_word |= (CMD_IO_SPACE |
517 CMD_MEMORY_SPACE | CMD_BUS_MASTER);
518 pci_write_config_word(pdev, PCI_REG_COMMAND, pci_cfg_cmd_word);
519 }
520
521 /*
522 * Issue Soft Reset to the MAC. This will reset the chip's
523 * transmit, receive, DMA. It will not effect
524 * the current PCI configuration. The global reset bit is self-
525 * clearing, and should clear within a microsecond.
526 */
527 AT_WRITE_REG(hw, REG_MASTER_CTRL,
528 MASTER_CTRL_LED_MODE | MASTER_CTRL_SOFT_RST);
529 wmb();
530 msleep(1);
531
532 /* Wait at least 10ms for All module to be Idle */
533 for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
534 idle_status_data = AT_READ_REG(hw, REG_IDLE_STATUS);
535 if (idle_status_data == 0)
536 break;
537 msleep(1);
538 cpu_relax();
539 }
540
541 if (timeout >= AT_HW_MAX_IDLE_DELAY) {
542 netdev_err(adapter->netdev,
543 "MAC state machine can't be idle since disabled for 10ms second\n");
544 return AT_ERR_TIMEOUT;
545 }
546
547 return 0;
548 }
549
550
551 /*
552 * Performs basic configuration of the adapter.
553 *
554 * hw - Struct containing variables accessed by shared code
555 * Assumes that the controller has previously been reset and is in a
556 * post-reset uninitialized state. Initializes multicast table,
557 * and Calls routines to setup link
558 * Leaves the transmit and receive units disabled and uninitialized.
559 */
atl1e_init_hw(struct atl1e_hw * hw)560 int atl1e_init_hw(struct atl1e_hw *hw)
561 {
562 s32 ret_val = 0;
563
564 atl1e_init_pcie(hw);
565
566 /* Zero out the Multicast HASH table */
567 /* clear the old settings from the multicast hash table */
568 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
569 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
570
571 ret_val = atl1e_phy_init(hw);
572
573 return ret_val;
574 }
575
576 /*
577 * Detects the current speed and duplex settings of the hardware.
578 *
579 * hw - Struct containing variables accessed by shared code
580 * speed - Speed of the connection
581 * duplex - Duplex setting of the connection
582 */
atl1e_get_speed_and_duplex(struct atl1e_hw * hw,u16 * speed,u16 * duplex)583 int atl1e_get_speed_and_duplex(struct atl1e_hw *hw, u16 *speed, u16 *duplex)
584 {
585 int err;
586 u16 phy_data;
587
588 /* Read PHY Specific Status Register (17) */
589 err = atl1e_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
590 if (err)
591 return err;
592
593 if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED))
594 return AT_ERR_PHY_RES;
595
596 switch (phy_data & MII_AT001_PSSR_SPEED) {
597 case MII_AT001_PSSR_1000MBS:
598 *speed = SPEED_1000;
599 break;
600 case MII_AT001_PSSR_100MBS:
601 *speed = SPEED_100;
602 break;
603 case MII_AT001_PSSR_10MBS:
604 *speed = SPEED_10;
605 break;
606 default:
607 return AT_ERR_PHY_SPEED;
608 }
609
610 if (phy_data & MII_AT001_PSSR_DPLX)
611 *duplex = FULL_DUPLEX;
612 else
613 *duplex = HALF_DUPLEX;
614
615 return 0;
616 }
617
atl1e_restart_autoneg(struct atl1e_hw * hw)618 int atl1e_restart_autoneg(struct atl1e_hw *hw)
619 {
620 int err = 0;
621
622 err = atl1e_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
623 if (err)
624 return err;
625
626 if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) {
627 err = atl1e_write_phy_reg(hw, MII_CTRL1000,
628 hw->mii_1000t_ctrl_reg);
629 if (err)
630 return err;
631 }
632
633 err = atl1e_write_phy_reg(hw, MII_BMCR,
634 BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART);
635 return err;
636 }
637
638