1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ALSA driver for ATI IXP 150/200/250/300 AC97 controllers 4 * 5 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 6 */ 7 8 #include <linux/io.h> 9 #include <linux/delay.h> 10 #include <linux/interrupt.h> 11 #include <linux/init.h> 12 #include <linux/pci.h> 13 #include <linux/slab.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <sound/core.h> 17 #include <sound/pcm.h> 18 #include <sound/pcm_params.h> 19 #include <sound/info.h> 20 #include <sound/ac97_codec.h> 21 #include <sound/initval.h> 22 23 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>"); 24 MODULE_DESCRIPTION("ATI IXP AC97 controller"); 25 MODULE_LICENSE("GPL"); 26 27 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */ 28 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ 29 static int ac97_clock = 48000; 30 static char *ac97_quirk; 31 static bool spdif_aclink = 1; 32 static int ac97_codec = -1; 33 34 module_param(index, int, 0444); 35 MODULE_PARM_DESC(index, "Index value for ATI IXP controller."); 36 module_param(id, charp, 0444); 37 MODULE_PARM_DESC(id, "ID string for ATI IXP controller."); 38 module_param(ac97_clock, int, 0444); 39 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz)."); 40 module_param(ac97_quirk, charp, 0444); 41 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware."); 42 module_param(ac97_codec, int, 0444); 43 MODULE_PARM_DESC(ac97_codec, "Specify codec instead of probing."); 44 module_param(spdif_aclink, bool, 0444); 45 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link."); 46 47 /* just for backward compatibility */ 48 static bool enable; 49 module_param(enable, bool, 0444); 50 51 52 /* 53 */ 54 55 #define ATI_REG_ISR 0x00 /* interrupt source */ 56 #define ATI_REG_ISR_IN_XRUN (1U<<0) 57 #define ATI_REG_ISR_IN_STATUS (1U<<1) 58 #define ATI_REG_ISR_OUT_XRUN (1U<<2) 59 #define ATI_REG_ISR_OUT_STATUS (1U<<3) 60 #define ATI_REG_ISR_SPDF_XRUN (1U<<4) 61 #define ATI_REG_ISR_SPDF_STATUS (1U<<5) 62 #define ATI_REG_ISR_PHYS_INTR (1U<<8) 63 #define ATI_REG_ISR_PHYS_MISMATCH (1U<<9) 64 #define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10) 65 #define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11) 66 #define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12) 67 #define ATI_REG_ISR_NEW_FRAME (1U<<13) 68 69 #define ATI_REG_IER 0x04 /* interrupt enable */ 70 #define ATI_REG_IER_IN_XRUN_EN (1U<<0) 71 #define ATI_REG_IER_IO_STATUS_EN (1U<<1) 72 #define ATI_REG_IER_OUT_XRUN_EN (1U<<2) 73 #define ATI_REG_IER_OUT_XRUN_COND (1U<<3) 74 #define ATI_REG_IER_SPDF_XRUN_EN (1U<<4) 75 #define ATI_REG_IER_SPDF_STATUS_EN (1U<<5) 76 #define ATI_REG_IER_PHYS_INTR_EN (1U<<8) 77 #define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9) 78 #define ATI_REG_IER_CODEC0_INTR_EN (1U<<10) 79 #define ATI_REG_IER_CODEC1_INTR_EN (1U<<11) 80 #define ATI_REG_IER_CODEC2_INTR_EN (1U<<12) 81 #define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO */ 82 #define ATI_REG_IER_SET_BUS_BUSY (1U<<14) /* (WO) audio is running */ 83 84 #define ATI_REG_CMD 0x08 /* command */ 85 #define ATI_REG_CMD_POWERDOWN (1U<<0) 86 #define ATI_REG_CMD_RECEIVE_EN (1U<<1) 87 #define ATI_REG_CMD_SEND_EN (1U<<2) 88 #define ATI_REG_CMD_STATUS_MEM (1U<<3) 89 #define ATI_REG_CMD_SPDF_OUT_EN (1U<<4) 90 #define ATI_REG_CMD_SPDF_STATUS_MEM (1U<<5) 91 #define ATI_REG_CMD_SPDF_THRESHOLD (3U<<6) 92 #define ATI_REG_CMD_SPDF_THRESHOLD_SHIFT 6 93 #define ATI_REG_CMD_IN_DMA_EN (1U<<8) 94 #define ATI_REG_CMD_OUT_DMA_EN (1U<<9) 95 #define ATI_REG_CMD_SPDF_DMA_EN (1U<<10) 96 #define ATI_REG_CMD_SPDF_OUT_STOPPED (1U<<11) 97 #define ATI_REG_CMD_SPDF_CONFIG_MASK (7U<<12) 98 #define ATI_REG_CMD_SPDF_CONFIG_34 (1U<<12) 99 #define ATI_REG_CMD_SPDF_CONFIG_78 (2U<<12) 100 #define ATI_REG_CMD_SPDF_CONFIG_69 (3U<<12) 101 #define ATI_REG_CMD_SPDF_CONFIG_01 (4U<<12) 102 #define ATI_REG_CMD_INTERLEAVE_SPDF (1U<<16) 103 #define ATI_REG_CMD_AUDIO_PRESENT (1U<<20) 104 #define ATI_REG_CMD_INTERLEAVE_IN (1U<<21) 105 #define ATI_REG_CMD_INTERLEAVE_OUT (1U<<22) 106 #define ATI_REG_CMD_LOOPBACK_EN (1U<<23) 107 #define ATI_REG_CMD_PACKED_DIS (1U<<24) 108 #define ATI_REG_CMD_BURST_EN (1U<<25) 109 #define ATI_REG_CMD_PANIC_EN (1U<<26) 110 #define ATI_REG_CMD_MODEM_PRESENT (1U<<27) 111 #define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28) 112 #define ATI_REG_CMD_AC_SOFT_RESET (1U<<29) 113 #define ATI_REG_CMD_AC_SYNC (1U<<30) 114 #define ATI_REG_CMD_AC_RESET (1U<<31) 115 116 #define ATI_REG_PHYS_OUT_ADDR 0x0c 117 #define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0) 118 #define ATI_REG_PHYS_OUT_RW (1U<<2) 119 #define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8) 120 #define ATI_REG_PHYS_OUT_ADDR_SHIFT 9 121 #define ATI_REG_PHYS_OUT_DATA_SHIFT 16 122 123 #define ATI_REG_PHYS_IN_ADDR 0x10 124 #define ATI_REG_PHYS_IN_READ_FLAG (1U<<8) 125 #define ATI_REG_PHYS_IN_ADDR_SHIFT 9 126 #define ATI_REG_PHYS_IN_DATA_SHIFT 16 127 128 #define ATI_REG_SLOTREQ 0x14 129 130 #define ATI_REG_COUNTER 0x18 131 #define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */ 132 #define ATI_REG_COUNTER_BITCLOCK (31U<<8) 133 134 #define ATI_REG_IN_FIFO_THRESHOLD 0x1c 135 136 #define ATI_REG_IN_DMA_LINKPTR 0x20 137 #define ATI_REG_IN_DMA_DT_START 0x24 /* RO */ 138 #define ATI_REG_IN_DMA_DT_NEXT 0x28 /* RO */ 139 #define ATI_REG_IN_DMA_DT_CUR 0x2c /* RO */ 140 #define ATI_REG_IN_DMA_DT_SIZE 0x30 141 142 #define ATI_REG_OUT_DMA_SLOT 0x34 143 #define ATI_REG_OUT_DMA_SLOT_BIT(x) (1U << ((x) - 3)) 144 #define ATI_REG_OUT_DMA_SLOT_MASK 0x1ff 145 #define ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800 146 #define ATI_REG_OUT_DMA_THRESHOLD_SHIFT 11 147 148 #define ATI_REG_OUT_DMA_LINKPTR 0x38 149 #define ATI_REG_OUT_DMA_DT_START 0x3c /* RO */ 150 #define ATI_REG_OUT_DMA_DT_NEXT 0x40 /* RO */ 151 #define ATI_REG_OUT_DMA_DT_CUR 0x44 /* RO */ 152 #define ATI_REG_OUT_DMA_DT_SIZE 0x48 153 154 #define ATI_REG_SPDF_CMD 0x4c 155 #define ATI_REG_SPDF_CMD_LFSR (1U<<4) 156 #define ATI_REG_SPDF_CMD_SINGLE_CH (1U<<5) 157 #define ATI_REG_SPDF_CMD_LFSR_ACC (0xff<<8) /* RO */ 158 159 #define ATI_REG_SPDF_DMA_LINKPTR 0x50 160 #define ATI_REG_SPDF_DMA_DT_START 0x54 /* RO */ 161 #define ATI_REG_SPDF_DMA_DT_NEXT 0x58 /* RO */ 162 #define ATI_REG_SPDF_DMA_DT_CUR 0x5c /* RO */ 163 #define ATI_REG_SPDF_DMA_DT_SIZE 0x60 164 165 #define ATI_REG_MODEM_MIRROR 0x7c 166 #define ATI_REG_AUDIO_MIRROR 0x80 167 168 #define ATI_REG_6CH_REORDER 0x84 /* reorder slots for 6ch */ 169 #define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */ 170 171 #define ATI_REG_FIFO_FLUSH 0x88 172 #define ATI_REG_FIFO_OUT_FLUSH (1U<<0) 173 #define ATI_REG_FIFO_IN_FLUSH (1U<<1) 174 175 /* LINKPTR */ 176 #define ATI_REG_LINKPTR_EN (1U<<0) 177 178 /* [INT|OUT|SPDIF]_DMA_DT_SIZE */ 179 #define ATI_REG_DMA_DT_SIZE (0xffffU<<0) 180 #define ATI_REG_DMA_FIFO_USED (0x1fU<<16) 181 #define ATI_REG_DMA_FIFO_FREE (0x1fU<<21) 182 #define ATI_REG_DMA_STATE (7U<<26) 183 184 185 #define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */ 186 187 188 struct atiixp; 189 190 /* 191 * DMA packate descriptor 192 */ 193 194 struct atiixp_dma_desc { 195 __le32 addr; /* DMA buffer address */ 196 u16 status; /* status bits */ 197 u16 size; /* size of the packet in dwords */ 198 __le32 next; /* address of the next packet descriptor */ 199 }; 200 201 /* 202 * stream enum 203 */ 204 enum { ATI_DMA_PLAYBACK, ATI_DMA_CAPTURE, ATI_DMA_SPDIF, NUM_ATI_DMAS }; /* DMAs */ 205 enum { ATI_PCM_OUT, ATI_PCM_IN, ATI_PCM_SPDIF, NUM_ATI_PCMS }; /* AC97 pcm slots */ 206 enum { ATI_PCMDEV_ANALOG, ATI_PCMDEV_DIGITAL, NUM_ATI_PCMDEVS }; /* pcm devices */ 207 208 #define NUM_ATI_CODECS 3 209 210 211 /* 212 * constants and callbacks for each DMA type 213 */ 214 struct atiixp_dma_ops { 215 int type; /* ATI_DMA_XXX */ 216 unsigned int llp_offset; /* LINKPTR offset */ 217 unsigned int dt_cur; /* DT_CUR offset */ 218 /* called from open callback */ 219 void (*enable_dma)(struct atiixp *chip, int on); 220 /* called from trigger (START/STOP) */ 221 void (*enable_transfer)(struct atiixp *chip, int on); 222 /* called from trigger (STOP only) */ 223 void (*flush_dma)(struct atiixp *chip); 224 }; 225 226 /* 227 * DMA stream 228 */ 229 struct atiixp_dma { 230 const struct atiixp_dma_ops *ops; 231 struct snd_dma_buffer desc_buf; 232 struct snd_pcm_substream *substream; /* assigned PCM substream */ 233 unsigned int buf_addr, buf_bytes; /* DMA buffer address, bytes */ 234 unsigned int period_bytes, periods; 235 int opened; 236 int running; 237 int suspended; 238 int pcm_open_flag; 239 int ac97_pcm_type; /* index # of ac97_pcm to access, -1 = not used */ 240 unsigned int saved_curptr; 241 }; 242 243 /* 244 * ATI IXP chip 245 */ 246 struct atiixp { 247 struct snd_card *card; 248 struct pci_dev *pci; 249 250 unsigned long addr; 251 void __iomem *remap_addr; 252 int irq; 253 254 struct snd_ac97_bus *ac97_bus; 255 struct snd_ac97 *ac97[NUM_ATI_CODECS]; 256 257 spinlock_t reg_lock; 258 259 struct atiixp_dma dmas[NUM_ATI_DMAS]; 260 struct ac97_pcm *pcms[NUM_ATI_PCMS]; 261 struct snd_pcm *pcmdevs[NUM_ATI_PCMDEVS]; 262 263 int max_channels; /* max. channels for PCM out */ 264 265 unsigned int codec_not_ready_bits; /* for codec detection */ 266 267 int spdif_over_aclink; /* passed from the module option */ 268 struct mutex open_mutex; /* playback open mutex */ 269 }; 270 271 272 /* 273 */ 274 static const struct pci_device_id snd_atiixp_ids[] = { 275 { PCI_VDEVICE(ATI, 0x4341), 0 }, /* SB200 */ 276 { PCI_VDEVICE(ATI, 0x4361), 0 }, /* SB300 */ 277 { PCI_VDEVICE(ATI, 0x4370), 0 }, /* SB400 */ 278 { PCI_VDEVICE(ATI, 0x4382), 0 }, /* SB600 */ 279 { 0, } 280 }; 281 282 MODULE_DEVICE_TABLE(pci, snd_atiixp_ids); 283 284 static const struct snd_pci_quirk atiixp_quirks[] = { 285 SND_PCI_QUIRK(0x105b, 0x0c81, "Foxconn RC4107MA-RS2", 0), 286 SND_PCI_QUIRK(0x15bd, 0x3100, "DFI RS482", 0), 287 { } /* terminator */ 288 }; 289 290 /* 291 * lowlevel functions 292 */ 293 294 /* 295 * update the bits of the given register. 296 * return 1 if the bits changed. 297 */ 298 static int snd_atiixp_update_bits(struct atiixp *chip, unsigned int reg, 299 unsigned int mask, unsigned int value) 300 { 301 void __iomem *addr = chip->remap_addr + reg; 302 unsigned int data, old_data; 303 old_data = data = readl(addr); 304 data &= ~mask; 305 data |= value; 306 if (old_data == data) 307 return 0; 308 writel(data, addr); 309 return 1; 310 } 311 312 /* 313 * macros for easy use 314 */ 315 #define atiixp_write(chip,reg,value) \ 316 writel(value, chip->remap_addr + ATI_REG_##reg) 317 #define atiixp_read(chip,reg) \ 318 readl(chip->remap_addr + ATI_REG_##reg) 319 #define atiixp_update(chip,reg,mask,val) \ 320 snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val) 321 322 /* 323 * handling DMA packets 324 * 325 * we allocate a linear buffer for the DMA, and split it to each packet. 326 * in a future version, a scatter-gather buffer should be implemented. 327 */ 328 329 #define ATI_DESC_LIST_SIZE \ 330 PAGE_ALIGN(ATI_MAX_DESCRIPTORS * sizeof(struct atiixp_dma_desc)) 331 332 /* 333 * build packets ring for the given buffer size. 334 * 335 * IXP handles the buffer descriptors, which are connected as a linked 336 * list. although we can change the list dynamically, in this version, 337 * a static RING of buffer descriptors is used. 338 * 339 * the ring is built in this function, and is set up to the hardware. 340 */ 341 static int atiixp_build_dma_packets(struct atiixp *chip, struct atiixp_dma *dma, 342 struct snd_pcm_substream *substream, 343 unsigned int periods, 344 unsigned int period_bytes) 345 { 346 unsigned int i; 347 u32 addr, desc_addr; 348 349 if (periods > ATI_MAX_DESCRIPTORS) 350 return -ENOMEM; 351 352 if (dma->desc_buf.area == NULL) { 353 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 354 &chip->pci->dev, 355 ATI_DESC_LIST_SIZE, 356 &dma->desc_buf) < 0) 357 return -ENOMEM; 358 dma->period_bytes = dma->periods = 0; /* clear */ 359 } 360 361 if (dma->periods == periods && dma->period_bytes == period_bytes) 362 return 0; 363 364 /* reset DMA before changing the descriptor table */ 365 scoped_guard(spinlock_irqsave, &chip->reg_lock) { 366 writel(0, chip->remap_addr + dma->ops->llp_offset); 367 dma->ops->enable_dma(chip, 0); 368 dma->ops->enable_dma(chip, 1); 369 } 370 371 /* fill the entries */ 372 addr = (u32)substream->runtime->dma_addr; 373 desc_addr = (u32)dma->desc_buf.addr; 374 for (i = 0; i < periods; i++) { 375 struct atiixp_dma_desc *desc; 376 desc = &((struct atiixp_dma_desc *)dma->desc_buf.area)[i]; 377 desc->addr = cpu_to_le32(addr); 378 desc->status = 0; 379 desc->size = period_bytes >> 2; /* in dwords */ 380 desc_addr += sizeof(struct atiixp_dma_desc); 381 if (i == periods - 1) 382 desc->next = cpu_to_le32((u32)dma->desc_buf.addr); 383 else 384 desc->next = cpu_to_le32(desc_addr); 385 addr += period_bytes; 386 } 387 388 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN, 389 chip->remap_addr + dma->ops->llp_offset); 390 391 dma->period_bytes = period_bytes; 392 dma->periods = periods; 393 394 return 0; 395 } 396 397 /* 398 * remove the ring buffer and release it if assigned 399 */ 400 static void atiixp_clear_dma_packets(struct atiixp *chip, struct atiixp_dma *dma, 401 struct snd_pcm_substream *substream) 402 { 403 if (dma->desc_buf.area) { 404 writel(0, chip->remap_addr + dma->ops->llp_offset); 405 snd_dma_free_pages(&dma->desc_buf); 406 dma->desc_buf.area = NULL; 407 } 408 } 409 410 /* 411 * AC97 interface 412 */ 413 static int snd_atiixp_acquire_codec(struct atiixp *chip) 414 { 415 int timeout = 1000; 416 417 while (atiixp_read(chip, PHYS_OUT_ADDR) & ATI_REG_PHYS_OUT_ADDR_EN) { 418 if (! timeout--) { 419 dev_warn(chip->card->dev, "codec acquire timeout\n"); 420 return -EBUSY; 421 } 422 udelay(1); 423 } 424 return 0; 425 } 426 427 static unsigned short snd_atiixp_codec_read(struct atiixp *chip, unsigned short codec, unsigned short reg) 428 { 429 unsigned int data; 430 int timeout; 431 432 if (snd_atiixp_acquire_codec(chip) < 0) 433 return 0xffff; 434 data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | 435 ATI_REG_PHYS_OUT_ADDR_EN | 436 ATI_REG_PHYS_OUT_RW | 437 codec; 438 atiixp_write(chip, PHYS_OUT_ADDR, data); 439 if (snd_atiixp_acquire_codec(chip) < 0) 440 return 0xffff; 441 timeout = 1000; 442 do { 443 data = atiixp_read(chip, PHYS_IN_ADDR); 444 if (data & ATI_REG_PHYS_IN_READ_FLAG) 445 return data >> ATI_REG_PHYS_IN_DATA_SHIFT; 446 udelay(1); 447 } while (--timeout); 448 /* time out may happen during reset */ 449 if (reg < 0x7c) 450 dev_warn(chip->card->dev, "codec read timeout (reg %x)\n", reg); 451 return 0xffff; 452 } 453 454 455 static void snd_atiixp_codec_write(struct atiixp *chip, unsigned short codec, 456 unsigned short reg, unsigned short val) 457 { 458 unsigned int data; 459 460 if (snd_atiixp_acquire_codec(chip) < 0) 461 return; 462 data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) | 463 ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | 464 ATI_REG_PHYS_OUT_ADDR_EN | codec; 465 atiixp_write(chip, PHYS_OUT_ADDR, data); 466 } 467 468 469 static unsigned short snd_atiixp_ac97_read(struct snd_ac97 *ac97, 470 unsigned short reg) 471 { 472 struct atiixp *chip = ac97->private_data; 473 return snd_atiixp_codec_read(chip, ac97->num, reg); 474 475 } 476 477 static void snd_atiixp_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 478 unsigned short val) 479 { 480 struct atiixp *chip = ac97->private_data; 481 snd_atiixp_codec_write(chip, ac97->num, reg, val); 482 } 483 484 /* 485 * reset AC link 486 */ 487 static int snd_atiixp_aclink_reset(struct atiixp *chip) 488 { 489 int timeout; 490 491 /* reset powerdoewn */ 492 if (atiixp_update(chip, CMD, ATI_REG_CMD_POWERDOWN, 0)) 493 udelay(10); 494 495 /* perform a software reset */ 496 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, ATI_REG_CMD_AC_SOFT_RESET); 497 atiixp_read(chip, CMD); 498 udelay(10); 499 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, 0); 500 501 timeout = 10; 502 while (! (atiixp_read(chip, CMD) & ATI_REG_CMD_ACLINK_ACTIVE)) { 503 /* do a hard reset */ 504 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET, 505 ATI_REG_CMD_AC_SYNC); 506 atiixp_read(chip, CMD); 507 mdelay(1); 508 atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET); 509 if (!--timeout) { 510 dev_err(chip->card->dev, "codec reset timeout\n"); 511 break; 512 } 513 } 514 515 /* deassert RESET and assert SYNC to make sure */ 516 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET, 517 ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET); 518 519 return 0; 520 } 521 522 static int snd_atiixp_aclink_down(struct atiixp *chip) 523 { 524 // if (atiixp_read(chip, MODEM_MIRROR) & 0x1) /* modem running, too? */ 525 // return -EBUSY; 526 atiixp_update(chip, CMD, 527 ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET, 528 ATI_REG_CMD_POWERDOWN); 529 return 0; 530 } 531 532 /* 533 * auto-detection of codecs 534 * 535 * the IXP chip can generate interrupts for the non-existing codecs. 536 * NEW_FRAME interrupt is used to make sure that the interrupt is generated 537 * even if all three codecs are connected. 538 */ 539 540 #define ALL_CODEC_NOT_READY \ 541 (ATI_REG_ISR_CODEC0_NOT_READY |\ 542 ATI_REG_ISR_CODEC1_NOT_READY |\ 543 ATI_REG_ISR_CODEC2_NOT_READY) 544 #define CODEC_CHECK_BITS (ALL_CODEC_NOT_READY|ATI_REG_ISR_NEW_FRAME) 545 546 static int ac97_probing_bugs(struct pci_dev *pci) 547 { 548 const struct snd_pci_quirk *q; 549 550 q = snd_pci_quirk_lookup(pci, atiixp_quirks); 551 if (q) { 552 dev_dbg(&pci->dev, "atiixp quirk for %s. Forcing codec %d\n", 553 snd_pci_quirk_name(q), q->value); 554 return q->value; 555 } 556 /* this hardware doesn't need workarounds. Probe for codec */ 557 return -1; 558 } 559 560 static int snd_atiixp_codec_detect(struct atiixp *chip) 561 { 562 int timeout; 563 564 chip->codec_not_ready_bits = 0; 565 if (ac97_codec == -1) 566 ac97_codec = ac97_probing_bugs(chip->pci); 567 if (ac97_codec >= 0) { 568 chip->codec_not_ready_bits |= 569 CODEC_CHECK_BITS ^ (1 << (ac97_codec + 10)); 570 return 0; 571 } 572 573 atiixp_write(chip, IER, CODEC_CHECK_BITS); 574 /* wait for the interrupts */ 575 timeout = 50; 576 while (timeout-- > 0) { 577 mdelay(1); 578 if (chip->codec_not_ready_bits) 579 break; 580 } 581 atiixp_write(chip, IER, 0); /* disable irqs */ 582 583 if ((chip->codec_not_ready_bits & ALL_CODEC_NOT_READY) == ALL_CODEC_NOT_READY) { 584 dev_err(chip->card->dev, "no codec detected!\n"); 585 return -ENXIO; 586 } 587 return 0; 588 } 589 590 591 /* 592 * enable DMA and irqs 593 */ 594 static int snd_atiixp_chip_start(struct atiixp *chip) 595 { 596 unsigned int reg; 597 598 /* set up spdif, enable burst mode */ 599 reg = atiixp_read(chip, CMD); 600 reg |= 0x02 << ATI_REG_CMD_SPDF_THRESHOLD_SHIFT; 601 reg |= ATI_REG_CMD_BURST_EN; 602 atiixp_write(chip, CMD, reg); 603 604 reg = atiixp_read(chip, SPDF_CMD); 605 reg &= ~(ATI_REG_SPDF_CMD_LFSR|ATI_REG_SPDF_CMD_SINGLE_CH); 606 atiixp_write(chip, SPDF_CMD, reg); 607 608 /* clear all interrupt source */ 609 atiixp_write(chip, ISR, 0xffffffff); 610 /* enable irqs */ 611 atiixp_write(chip, IER, 612 ATI_REG_IER_IO_STATUS_EN | 613 ATI_REG_IER_IN_XRUN_EN | 614 ATI_REG_IER_OUT_XRUN_EN | 615 ATI_REG_IER_SPDF_XRUN_EN | 616 ATI_REG_IER_SPDF_STATUS_EN); 617 return 0; 618 } 619 620 621 /* 622 * disable DMA and IRQs 623 */ 624 static int snd_atiixp_chip_stop(struct atiixp *chip) 625 { 626 /* clear interrupt source */ 627 atiixp_write(chip, ISR, atiixp_read(chip, ISR)); 628 /* disable irqs */ 629 atiixp_write(chip, IER, 0); 630 return 0; 631 } 632 633 634 /* 635 * PCM section 636 */ 637 638 /* 639 * pointer callback simplly reads XXX_DMA_DT_CUR register as the current 640 * position. when SG-buffer is implemented, the offset must be calculated 641 * correctly... 642 */ 643 static snd_pcm_uframes_t snd_atiixp_pcm_pointer(struct snd_pcm_substream *substream) 644 { 645 struct atiixp *chip = snd_pcm_substream_chip(substream); 646 struct snd_pcm_runtime *runtime = substream->runtime; 647 struct atiixp_dma *dma = runtime->private_data; 648 unsigned int curptr; 649 int timeout = 1000; 650 651 while (timeout--) { 652 curptr = readl(chip->remap_addr + dma->ops->dt_cur); 653 if (curptr < dma->buf_addr) 654 continue; 655 curptr -= dma->buf_addr; 656 if (curptr >= dma->buf_bytes) 657 continue; 658 return bytes_to_frames(runtime, curptr); 659 } 660 dev_dbg(chip->card->dev, "invalid DMA pointer read 0x%x (buf=%x)\n", 661 readl(chip->remap_addr + dma->ops->dt_cur), dma->buf_addr); 662 return 0; 663 } 664 665 /* 666 * XRUN detected, and stop the PCM substream 667 */ 668 static void snd_atiixp_xrun_dma(struct atiixp *chip, struct atiixp_dma *dma) 669 { 670 if (! dma->substream || ! dma->running) 671 return; 672 dev_dbg(chip->card->dev, "XRUN detected (DMA %d)\n", dma->ops->type); 673 snd_pcm_stop_xrun(dma->substream); 674 } 675 676 /* 677 * the period ack. update the substream. 678 */ 679 static void snd_atiixp_update_dma(struct atiixp *chip, struct atiixp_dma *dma) 680 { 681 if (! dma->substream || ! dma->running) 682 return; 683 snd_pcm_period_elapsed(dma->substream); 684 } 685 686 /* set BUS_BUSY interrupt bit if any DMA is running */ 687 /* call with spinlock held */ 688 static void snd_atiixp_check_bus_busy(struct atiixp *chip) 689 { 690 unsigned int bus_busy; 691 if (atiixp_read(chip, CMD) & (ATI_REG_CMD_SEND_EN | 692 ATI_REG_CMD_RECEIVE_EN | 693 ATI_REG_CMD_SPDF_OUT_EN)) 694 bus_busy = ATI_REG_IER_SET_BUS_BUSY; 695 else 696 bus_busy = 0; 697 atiixp_update(chip, IER, ATI_REG_IER_SET_BUS_BUSY, bus_busy); 698 } 699 700 /* common trigger callback 701 * calling the lowlevel callbacks in it 702 */ 703 static int snd_atiixp_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 704 { 705 struct atiixp *chip = snd_pcm_substream_chip(substream); 706 struct atiixp_dma *dma = substream->runtime->private_data; 707 int err = 0; 708 709 if (snd_BUG_ON(!dma->ops->enable_transfer || 710 !dma->ops->flush_dma)) 711 return -EINVAL; 712 713 guard(spinlock)(&chip->reg_lock); 714 switch (cmd) { 715 case SNDRV_PCM_TRIGGER_START: 716 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 717 case SNDRV_PCM_TRIGGER_RESUME: 718 if (dma->running && dma->suspended && 719 cmd == SNDRV_PCM_TRIGGER_RESUME) 720 writel(dma->saved_curptr, chip->remap_addr + 721 dma->ops->dt_cur); 722 dma->ops->enable_transfer(chip, 1); 723 dma->running = 1; 724 dma->suspended = 0; 725 break; 726 case SNDRV_PCM_TRIGGER_STOP: 727 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 728 case SNDRV_PCM_TRIGGER_SUSPEND: 729 dma->suspended = cmd == SNDRV_PCM_TRIGGER_SUSPEND; 730 if (dma->running && dma->suspended) 731 dma->saved_curptr = readl(chip->remap_addr + 732 dma->ops->dt_cur); 733 dma->ops->enable_transfer(chip, 0); 734 dma->running = 0; 735 break; 736 default: 737 err = -EINVAL; 738 break; 739 } 740 if (! err) { 741 snd_atiixp_check_bus_busy(chip); 742 if (cmd == SNDRV_PCM_TRIGGER_STOP) { 743 dma->ops->flush_dma(chip); 744 snd_atiixp_check_bus_busy(chip); 745 } 746 } 747 return err; 748 } 749 750 751 /* 752 * lowlevel callbacks for each DMA type 753 * 754 * every callback is supposed to be called in chip->reg_lock spinlock 755 */ 756 757 /* flush FIFO of analog OUT DMA */ 758 static void atiixp_out_flush_dma(struct atiixp *chip) 759 { 760 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_OUT_FLUSH); 761 } 762 763 /* enable/disable analog OUT DMA */ 764 static void atiixp_out_enable_dma(struct atiixp *chip, int on) 765 { 766 unsigned int data; 767 data = atiixp_read(chip, CMD); 768 if (on) { 769 if (data & ATI_REG_CMD_OUT_DMA_EN) 770 return; 771 atiixp_out_flush_dma(chip); 772 data |= ATI_REG_CMD_OUT_DMA_EN; 773 } else 774 data &= ~ATI_REG_CMD_OUT_DMA_EN; 775 atiixp_write(chip, CMD, data); 776 } 777 778 /* start/stop transfer over OUT DMA */ 779 static void atiixp_out_enable_transfer(struct atiixp *chip, int on) 780 { 781 atiixp_update(chip, CMD, ATI_REG_CMD_SEND_EN, 782 on ? ATI_REG_CMD_SEND_EN : 0); 783 } 784 785 /* enable/disable analog IN DMA */ 786 static void atiixp_in_enable_dma(struct atiixp *chip, int on) 787 { 788 atiixp_update(chip, CMD, ATI_REG_CMD_IN_DMA_EN, 789 on ? ATI_REG_CMD_IN_DMA_EN : 0); 790 } 791 792 /* start/stop analog IN DMA */ 793 static void atiixp_in_enable_transfer(struct atiixp *chip, int on) 794 { 795 if (on) { 796 unsigned int data = atiixp_read(chip, CMD); 797 if (! (data & ATI_REG_CMD_RECEIVE_EN)) { 798 data |= ATI_REG_CMD_RECEIVE_EN; 799 #if 0 /* FIXME: this causes the endless loop */ 800 /* wait until slot 3/4 are finished */ 801 while ((atiixp_read(chip, COUNTER) & 802 ATI_REG_COUNTER_SLOT) != 5) 803 ; 804 #endif 805 atiixp_write(chip, CMD, data); 806 } 807 } else 808 atiixp_update(chip, CMD, ATI_REG_CMD_RECEIVE_EN, 0); 809 } 810 811 /* flush FIFO of analog IN DMA */ 812 static void atiixp_in_flush_dma(struct atiixp *chip) 813 { 814 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_IN_FLUSH); 815 } 816 817 /* enable/disable SPDIF OUT DMA */ 818 static void atiixp_spdif_enable_dma(struct atiixp *chip, int on) 819 { 820 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_DMA_EN, 821 on ? ATI_REG_CMD_SPDF_DMA_EN : 0); 822 } 823 824 /* start/stop SPDIF OUT DMA */ 825 static void atiixp_spdif_enable_transfer(struct atiixp *chip, int on) 826 { 827 unsigned int data; 828 data = atiixp_read(chip, CMD); 829 if (on) 830 data |= ATI_REG_CMD_SPDF_OUT_EN; 831 else 832 data &= ~ATI_REG_CMD_SPDF_OUT_EN; 833 atiixp_write(chip, CMD, data); 834 } 835 836 /* flush FIFO of SPDIF OUT DMA */ 837 static void atiixp_spdif_flush_dma(struct atiixp *chip) 838 { 839 int timeout; 840 841 /* DMA off, transfer on */ 842 atiixp_spdif_enable_dma(chip, 0); 843 atiixp_spdif_enable_transfer(chip, 1); 844 845 timeout = 100; 846 do { 847 if (! (atiixp_read(chip, SPDF_DMA_DT_SIZE) & ATI_REG_DMA_FIFO_USED)) 848 break; 849 udelay(1); 850 } while (timeout-- > 0); 851 852 atiixp_spdif_enable_transfer(chip, 0); 853 } 854 855 /* set up slots and formats for SPDIF OUT */ 856 static int snd_atiixp_spdif_prepare(struct snd_pcm_substream *substream) 857 { 858 struct atiixp *chip = snd_pcm_substream_chip(substream); 859 860 guard(spinlock_irq)(&chip->reg_lock); 861 if (chip->spdif_over_aclink) { 862 unsigned int data; 863 /* enable slots 10/11 */ 864 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, 865 ATI_REG_CMD_SPDF_CONFIG_01); 866 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK; 867 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) | 868 ATI_REG_OUT_DMA_SLOT_BIT(11); 869 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT; 870 atiixp_write(chip, OUT_DMA_SLOT, data); 871 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT, 872 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ? 873 ATI_REG_CMD_INTERLEAVE_OUT : 0); 874 } else { 875 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, 0); 876 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_SPDF, 0); 877 } 878 return 0; 879 } 880 881 /* set up slots and formats for analog OUT */ 882 static int snd_atiixp_playback_prepare(struct snd_pcm_substream *substream) 883 { 884 struct atiixp *chip = snd_pcm_substream_chip(substream); 885 unsigned int data; 886 887 guard(spinlock_irq)(&chip->reg_lock); 888 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK; 889 switch (substream->runtime->channels) { 890 case 8: 891 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) | 892 ATI_REG_OUT_DMA_SLOT_BIT(11); 893 fallthrough; 894 case 6: 895 data |= ATI_REG_OUT_DMA_SLOT_BIT(7) | 896 ATI_REG_OUT_DMA_SLOT_BIT(8); 897 fallthrough; 898 case 4: 899 data |= ATI_REG_OUT_DMA_SLOT_BIT(6) | 900 ATI_REG_OUT_DMA_SLOT_BIT(9); 901 fallthrough; 902 default: 903 data |= ATI_REG_OUT_DMA_SLOT_BIT(3) | 904 ATI_REG_OUT_DMA_SLOT_BIT(4); 905 break; 906 } 907 908 /* set output threshold */ 909 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT; 910 atiixp_write(chip, OUT_DMA_SLOT, data); 911 912 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT, 913 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ? 914 ATI_REG_CMD_INTERLEAVE_OUT : 0); 915 916 /* 917 * enable 6 channel re-ordering bit if needed 918 */ 919 atiixp_update(chip, 6CH_REORDER, ATI_REG_6CH_REORDER_EN, 920 substream->runtime->channels >= 6 ? ATI_REG_6CH_REORDER_EN: 0); 921 922 return 0; 923 } 924 925 /* set up slots and formats for analog IN */ 926 static int snd_atiixp_capture_prepare(struct snd_pcm_substream *substream) 927 { 928 struct atiixp *chip = snd_pcm_substream_chip(substream); 929 930 guard(spinlock_irq)(&chip->reg_lock); 931 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_IN, 932 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ? 933 ATI_REG_CMD_INTERLEAVE_IN : 0); 934 return 0; 935 } 936 937 /* 938 * hw_params - allocate the buffer and set up buffer descriptors 939 */ 940 static int snd_atiixp_pcm_hw_params(struct snd_pcm_substream *substream, 941 struct snd_pcm_hw_params *hw_params) 942 { 943 struct atiixp *chip = snd_pcm_substream_chip(substream); 944 struct atiixp_dma *dma = substream->runtime->private_data; 945 int err; 946 947 dma->buf_addr = substream->runtime->dma_addr; 948 dma->buf_bytes = params_buffer_bytes(hw_params); 949 950 err = atiixp_build_dma_packets(chip, dma, substream, 951 params_periods(hw_params), 952 params_period_bytes(hw_params)); 953 if (err < 0) 954 return err; 955 956 if (dma->ac97_pcm_type >= 0) { 957 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type]; 958 /* PCM is bound to AC97 codec(s) 959 * set up the AC97 codecs 960 */ 961 if (dma->pcm_open_flag) { 962 snd_ac97_pcm_close(pcm); 963 dma->pcm_open_flag = 0; 964 } 965 err = snd_ac97_pcm_open(pcm, params_rate(hw_params), 966 params_channels(hw_params), 967 pcm->r[0].slots); 968 if (err >= 0) 969 dma->pcm_open_flag = 1; 970 } 971 972 return err; 973 } 974 975 static int snd_atiixp_pcm_hw_free(struct snd_pcm_substream *substream) 976 { 977 struct atiixp *chip = snd_pcm_substream_chip(substream); 978 struct atiixp_dma *dma = substream->runtime->private_data; 979 980 if (dma->pcm_open_flag) { 981 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type]; 982 snd_ac97_pcm_close(pcm); 983 dma->pcm_open_flag = 0; 984 } 985 atiixp_clear_dma_packets(chip, dma, substream); 986 return 0; 987 } 988 989 990 /* 991 * pcm hardware definition, identical for all DMA types 992 */ 993 static const struct snd_pcm_hardware snd_atiixp_pcm_hw = 994 { 995 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 996 SNDRV_PCM_INFO_BLOCK_TRANSFER | 997 SNDRV_PCM_INFO_PAUSE | 998 SNDRV_PCM_INFO_RESUME | 999 SNDRV_PCM_INFO_MMAP_VALID), 1000 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, 1001 .rates = SNDRV_PCM_RATE_48000, 1002 .rate_min = 48000, 1003 .rate_max = 48000, 1004 .channels_min = 2, 1005 .channels_max = 2, 1006 .buffer_bytes_max = 256 * 1024, 1007 .period_bytes_min = 32, 1008 .period_bytes_max = 128 * 1024, 1009 .periods_min = 2, 1010 .periods_max = ATI_MAX_DESCRIPTORS, 1011 }; 1012 1013 static int snd_atiixp_pcm_open(struct snd_pcm_substream *substream, 1014 struct atiixp_dma *dma, int pcm_type) 1015 { 1016 struct atiixp *chip = snd_pcm_substream_chip(substream); 1017 struct snd_pcm_runtime *runtime = substream->runtime; 1018 int err; 1019 1020 if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma)) 1021 return -EINVAL; 1022 1023 if (dma->opened) 1024 return -EBUSY; 1025 dma->substream = substream; 1026 runtime->hw = snd_atiixp_pcm_hw; 1027 dma->ac97_pcm_type = pcm_type; 1028 if (pcm_type >= 0) { 1029 runtime->hw.rates = chip->pcms[pcm_type]->rates; 1030 snd_pcm_limit_hw_rates(runtime); 1031 } else { 1032 /* direct SPDIF */ 1033 runtime->hw.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE; 1034 } 1035 err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 1036 if (err < 0) 1037 return err; 1038 runtime->private_data = dma; 1039 1040 /* enable DMA bits */ 1041 scoped_guard(spinlock_irq, &chip->reg_lock) { 1042 dma->ops->enable_dma(chip, 1); 1043 } 1044 dma->opened = 1; 1045 1046 return 0; 1047 } 1048 1049 static int snd_atiixp_pcm_close(struct snd_pcm_substream *substream, 1050 struct atiixp_dma *dma) 1051 { 1052 struct atiixp *chip = snd_pcm_substream_chip(substream); 1053 /* disable DMA bits */ 1054 if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma)) 1055 return -EINVAL; 1056 scoped_guard(spinlock_irq, &chip->reg_lock) { 1057 dma->ops->enable_dma(chip, 0); 1058 } 1059 dma->substream = NULL; 1060 dma->opened = 0; 1061 return 0; 1062 } 1063 1064 /* 1065 */ 1066 static int snd_atiixp_playback_open(struct snd_pcm_substream *substream) 1067 { 1068 struct atiixp *chip = snd_pcm_substream_chip(substream); 1069 int err; 1070 1071 guard(mutex)(&chip->open_mutex); 1072 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 0); 1073 if (err < 0) 1074 return err; 1075 substream->runtime->hw.channels_max = chip->max_channels; 1076 if (chip->max_channels > 2) 1077 /* channels must be even */ 1078 snd_pcm_hw_constraint_step(substream->runtime, 0, 1079 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1080 return 0; 1081 } 1082 1083 static int snd_atiixp_playback_close(struct snd_pcm_substream *substream) 1084 { 1085 struct atiixp *chip = snd_pcm_substream_chip(substream); 1086 1087 guard(mutex)(&chip->open_mutex); 1088 return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]); 1089 } 1090 1091 static int snd_atiixp_capture_open(struct snd_pcm_substream *substream) 1092 { 1093 struct atiixp *chip = snd_pcm_substream_chip(substream); 1094 return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_CAPTURE], 1); 1095 } 1096 1097 static int snd_atiixp_capture_close(struct snd_pcm_substream *substream) 1098 { 1099 struct atiixp *chip = snd_pcm_substream_chip(substream); 1100 return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_CAPTURE]); 1101 } 1102 1103 static int snd_atiixp_spdif_open(struct snd_pcm_substream *substream) 1104 { 1105 struct atiixp *chip = snd_pcm_substream_chip(substream); 1106 1107 guard(mutex)(&chip->open_mutex); 1108 if (chip->spdif_over_aclink) /* share DMA_PLAYBACK */ 1109 return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 2); 1110 else 1111 return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_SPDIF], -1); 1112 } 1113 1114 static int snd_atiixp_spdif_close(struct snd_pcm_substream *substream) 1115 { 1116 struct atiixp *chip = snd_pcm_substream_chip(substream); 1117 1118 guard(mutex)(&chip->open_mutex); 1119 if (chip->spdif_over_aclink) 1120 return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]); 1121 else 1122 return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_SPDIF]); 1123 } 1124 1125 /* AC97 playback */ 1126 static const struct snd_pcm_ops snd_atiixp_playback_ops = { 1127 .open = snd_atiixp_playback_open, 1128 .close = snd_atiixp_playback_close, 1129 .hw_params = snd_atiixp_pcm_hw_params, 1130 .hw_free = snd_atiixp_pcm_hw_free, 1131 .prepare = snd_atiixp_playback_prepare, 1132 .trigger = snd_atiixp_pcm_trigger, 1133 .pointer = snd_atiixp_pcm_pointer, 1134 }; 1135 1136 /* AC97 capture */ 1137 static const struct snd_pcm_ops snd_atiixp_capture_ops = { 1138 .open = snd_atiixp_capture_open, 1139 .close = snd_atiixp_capture_close, 1140 .hw_params = snd_atiixp_pcm_hw_params, 1141 .hw_free = snd_atiixp_pcm_hw_free, 1142 .prepare = snd_atiixp_capture_prepare, 1143 .trigger = snd_atiixp_pcm_trigger, 1144 .pointer = snd_atiixp_pcm_pointer, 1145 }; 1146 1147 /* SPDIF playback */ 1148 static const struct snd_pcm_ops snd_atiixp_spdif_ops = { 1149 .open = snd_atiixp_spdif_open, 1150 .close = snd_atiixp_spdif_close, 1151 .hw_params = snd_atiixp_pcm_hw_params, 1152 .hw_free = snd_atiixp_pcm_hw_free, 1153 .prepare = snd_atiixp_spdif_prepare, 1154 .trigger = snd_atiixp_pcm_trigger, 1155 .pointer = snd_atiixp_pcm_pointer, 1156 }; 1157 1158 static const struct ac97_pcm atiixp_pcm_defs[] = { 1159 /* front PCM */ 1160 { 1161 .exclusive = 1, 1162 .r = { { 1163 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1164 (1 << AC97_SLOT_PCM_RIGHT) | 1165 (1 << AC97_SLOT_PCM_CENTER) | 1166 (1 << AC97_SLOT_PCM_SLEFT) | 1167 (1 << AC97_SLOT_PCM_SRIGHT) | 1168 (1 << AC97_SLOT_LFE) 1169 } 1170 } 1171 }, 1172 /* PCM IN #1 */ 1173 { 1174 .stream = 1, 1175 .exclusive = 1, 1176 .r = { { 1177 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1178 (1 << AC97_SLOT_PCM_RIGHT) 1179 } 1180 } 1181 }, 1182 /* S/PDIF OUT (optional) */ 1183 { 1184 .exclusive = 1, 1185 .spdif = 1, 1186 .r = { { 1187 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) | 1188 (1 << AC97_SLOT_SPDIF_RIGHT2) 1189 } 1190 } 1191 }, 1192 }; 1193 1194 static const struct atiixp_dma_ops snd_atiixp_playback_dma_ops = { 1195 .type = ATI_DMA_PLAYBACK, 1196 .llp_offset = ATI_REG_OUT_DMA_LINKPTR, 1197 .dt_cur = ATI_REG_OUT_DMA_DT_CUR, 1198 .enable_dma = atiixp_out_enable_dma, 1199 .enable_transfer = atiixp_out_enable_transfer, 1200 .flush_dma = atiixp_out_flush_dma, 1201 }; 1202 1203 static const struct atiixp_dma_ops snd_atiixp_capture_dma_ops = { 1204 .type = ATI_DMA_CAPTURE, 1205 .llp_offset = ATI_REG_IN_DMA_LINKPTR, 1206 .dt_cur = ATI_REG_IN_DMA_DT_CUR, 1207 .enable_dma = atiixp_in_enable_dma, 1208 .enable_transfer = atiixp_in_enable_transfer, 1209 .flush_dma = atiixp_in_flush_dma, 1210 }; 1211 1212 static const struct atiixp_dma_ops snd_atiixp_spdif_dma_ops = { 1213 .type = ATI_DMA_SPDIF, 1214 .llp_offset = ATI_REG_SPDF_DMA_LINKPTR, 1215 .dt_cur = ATI_REG_SPDF_DMA_DT_CUR, 1216 .enable_dma = atiixp_spdif_enable_dma, 1217 .enable_transfer = atiixp_spdif_enable_transfer, 1218 .flush_dma = atiixp_spdif_flush_dma, 1219 }; 1220 1221 1222 static int snd_atiixp_pcm_new(struct atiixp *chip) 1223 { 1224 struct snd_pcm *pcm; 1225 struct snd_pcm_chmap *chmap; 1226 struct snd_ac97_bus *pbus = chip->ac97_bus; 1227 int err, i, num_pcms; 1228 1229 /* initialize constants */ 1230 chip->dmas[ATI_DMA_PLAYBACK].ops = &snd_atiixp_playback_dma_ops; 1231 chip->dmas[ATI_DMA_CAPTURE].ops = &snd_atiixp_capture_dma_ops; 1232 if (! chip->spdif_over_aclink) 1233 chip->dmas[ATI_DMA_SPDIF].ops = &snd_atiixp_spdif_dma_ops; 1234 1235 /* assign AC97 pcm */ 1236 if (chip->spdif_over_aclink) 1237 num_pcms = 3; 1238 else 1239 num_pcms = 2; 1240 err = snd_ac97_pcm_assign(pbus, num_pcms, atiixp_pcm_defs); 1241 if (err < 0) 1242 return err; 1243 for (i = 0; i < num_pcms; i++) 1244 chip->pcms[i] = &pbus->pcms[i]; 1245 1246 chip->max_channels = 2; 1247 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) { 1248 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_LFE)) 1249 chip->max_channels = 6; 1250 else 1251 chip->max_channels = 4; 1252 } 1253 1254 /* PCM #0: analog I/O */ 1255 err = snd_pcm_new(chip->card, "ATI IXP AC97", 1256 ATI_PCMDEV_ANALOG, 1, 1, &pcm); 1257 if (err < 0) 1258 return err; 1259 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_playback_ops); 1260 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_atiixp_capture_ops); 1261 pcm->private_data = chip; 1262 strscpy(pcm->name, "ATI IXP AC97"); 1263 chip->pcmdevs[ATI_PCMDEV_ANALOG] = pcm; 1264 1265 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, 1266 &chip->pci->dev, 64*1024, 128*1024); 1267 1268 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, 1269 snd_pcm_alt_chmaps, chip->max_channels, 0, 1270 &chmap); 1271 if (err < 0) 1272 return err; 1273 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468; 1274 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap; 1275 1276 /* no SPDIF support on codec? */ 1277 if (chip->pcms[ATI_PCM_SPDIF] && ! chip->pcms[ATI_PCM_SPDIF]->rates) 1278 return 0; 1279 1280 /* FIXME: non-48k sample rate doesn't work on my test machine with AD1888 */ 1281 if (chip->pcms[ATI_PCM_SPDIF]) 1282 chip->pcms[ATI_PCM_SPDIF]->rates = SNDRV_PCM_RATE_48000; 1283 1284 /* PCM #1: spdif playback */ 1285 err = snd_pcm_new(chip->card, "ATI IXP IEC958", 1286 ATI_PCMDEV_DIGITAL, 1, 0, &pcm); 1287 if (err < 0) 1288 return err; 1289 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_spdif_ops); 1290 pcm->private_data = chip; 1291 if (chip->spdif_over_aclink) 1292 strscpy(pcm->name, "ATI IXP IEC958 (AC97)"); 1293 else 1294 strscpy(pcm->name, "ATI IXP IEC958 (Direct)"); 1295 chip->pcmdevs[ATI_PCMDEV_DIGITAL] = pcm; 1296 1297 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, 1298 &chip->pci->dev, 64*1024, 128*1024); 1299 1300 /* pre-select AC97 SPDIF slots 10/11 */ 1301 for (i = 0; i < NUM_ATI_CODECS; i++) { 1302 if (chip->ac97[i]) 1303 snd_ac97_update_bits(chip->ac97[i], 1304 AC97_EXTENDED_STATUS, 1305 0x03 << 4, 0x03 << 4); 1306 } 1307 1308 return 0; 1309 } 1310 1311 1312 1313 /* 1314 * interrupt handler 1315 */ 1316 static irqreturn_t snd_atiixp_interrupt(int irq, void *dev_id) 1317 { 1318 struct atiixp *chip = dev_id; 1319 unsigned int status; 1320 1321 status = atiixp_read(chip, ISR); 1322 1323 if (! status) 1324 return IRQ_NONE; 1325 1326 /* process audio DMA */ 1327 if (status & ATI_REG_ISR_OUT_XRUN) 1328 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]); 1329 else if (status & ATI_REG_ISR_OUT_STATUS) 1330 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]); 1331 if (status & ATI_REG_ISR_IN_XRUN) 1332 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]); 1333 else if (status & ATI_REG_ISR_IN_STATUS) 1334 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]); 1335 if (! chip->spdif_over_aclink) { 1336 if (status & ATI_REG_ISR_SPDF_XRUN) 1337 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_SPDIF]); 1338 else if (status & ATI_REG_ISR_SPDF_STATUS) 1339 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_SPDIF]); 1340 } 1341 1342 /* for codec detection */ 1343 if (status & CODEC_CHECK_BITS) { 1344 unsigned int detected; 1345 detected = status & CODEC_CHECK_BITS; 1346 guard(spinlock)(&chip->reg_lock); 1347 chip->codec_not_ready_bits |= detected; 1348 atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */ 1349 } 1350 1351 /* ack */ 1352 atiixp_write(chip, ISR, status); 1353 1354 return IRQ_HANDLED; 1355 } 1356 1357 1358 /* 1359 * ac97 mixer section 1360 */ 1361 1362 static const struct ac97_quirk ac97_quirks[] = { 1363 { 1364 .subvendor = 0x103c, 1365 .subdevice = 0x006b, 1366 .name = "HP Pavilion ZV5030US", 1367 .type = AC97_TUNE_MUTE_LED 1368 }, 1369 { 1370 .subvendor = 0x103c, 1371 .subdevice = 0x308b, 1372 .name = "HP nx6125", 1373 .type = AC97_TUNE_MUTE_LED 1374 }, 1375 { 1376 .subvendor = 0x103c, 1377 .subdevice = 0x3091, 1378 .name = "unknown HP", 1379 .type = AC97_TUNE_MUTE_LED 1380 }, 1381 { } /* terminator */ 1382 }; 1383 1384 static int snd_atiixp_mixer_new(struct atiixp *chip, int clock, 1385 const char *quirk_override) 1386 { 1387 struct snd_ac97_bus *pbus; 1388 struct snd_ac97_template ac97; 1389 int i, err; 1390 int codec_count; 1391 static const struct snd_ac97_bus_ops ops = { 1392 .write = snd_atiixp_ac97_write, 1393 .read = snd_atiixp_ac97_read, 1394 }; 1395 static const unsigned int codec_skip[NUM_ATI_CODECS] = { 1396 ATI_REG_ISR_CODEC0_NOT_READY, 1397 ATI_REG_ISR_CODEC1_NOT_READY, 1398 ATI_REG_ISR_CODEC2_NOT_READY, 1399 }; 1400 1401 if (snd_atiixp_codec_detect(chip) < 0) 1402 return -ENXIO; 1403 1404 err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus); 1405 if (err < 0) 1406 return err; 1407 pbus->clock = clock; 1408 chip->ac97_bus = pbus; 1409 1410 codec_count = 0; 1411 for (i = 0; i < NUM_ATI_CODECS; i++) { 1412 if (chip->codec_not_ready_bits & codec_skip[i]) 1413 continue; 1414 memset(&ac97, 0, sizeof(ac97)); 1415 ac97.private_data = chip; 1416 ac97.pci = chip->pci; 1417 ac97.num = i; 1418 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE; 1419 if (! chip->spdif_over_aclink) 1420 ac97.scaps |= AC97_SCAP_NO_SPDIF; 1421 err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i]); 1422 if (err < 0) { 1423 chip->ac97[i] = NULL; /* to be sure */ 1424 dev_dbg(chip->card->dev, 1425 "codec %d not available for audio\n", i); 1426 continue; 1427 } 1428 codec_count++; 1429 } 1430 1431 if (! codec_count) { 1432 dev_err(chip->card->dev, "no codec available\n"); 1433 return -ENODEV; 1434 } 1435 1436 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override); 1437 1438 return 0; 1439 } 1440 1441 1442 /* 1443 * power management 1444 */ 1445 static int snd_atiixp_suspend(struct device *dev) 1446 { 1447 struct snd_card *card = dev_get_drvdata(dev); 1448 struct atiixp *chip = card->private_data; 1449 int i; 1450 1451 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1452 for (i = 0; i < NUM_ATI_CODECS; i++) 1453 snd_ac97_suspend(chip->ac97[i]); 1454 snd_atiixp_aclink_down(chip); 1455 snd_atiixp_chip_stop(chip); 1456 return 0; 1457 } 1458 1459 static int snd_atiixp_resume(struct device *dev) 1460 { 1461 struct snd_card *card = dev_get_drvdata(dev); 1462 struct atiixp *chip = card->private_data; 1463 int i; 1464 1465 snd_atiixp_aclink_reset(chip); 1466 snd_atiixp_chip_start(chip); 1467 1468 for (i = 0; i < NUM_ATI_CODECS; i++) 1469 snd_ac97_resume(chip->ac97[i]); 1470 1471 for (i = 0; i < NUM_ATI_PCMDEVS; i++) 1472 if (chip->pcmdevs[i]) { 1473 struct atiixp_dma *dma = &chip->dmas[i]; 1474 if (dma->substream && dma->suspended) { 1475 dma->ops->enable_dma(chip, 1); 1476 dma->substream->ops->prepare(dma->substream); 1477 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN, 1478 chip->remap_addr + dma->ops->llp_offset); 1479 } 1480 } 1481 1482 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1483 return 0; 1484 } 1485 1486 static DEFINE_SIMPLE_DEV_PM_OPS(snd_atiixp_pm, snd_atiixp_suspend, snd_atiixp_resume); 1487 1488 /* 1489 * proc interface for register dump 1490 */ 1491 1492 static void snd_atiixp_proc_read(struct snd_info_entry *entry, 1493 struct snd_info_buffer *buffer) 1494 { 1495 struct atiixp *chip = entry->private_data; 1496 int i; 1497 1498 for (i = 0; i < 256; i += 4) 1499 snd_iprintf(buffer, "%02x: %08x\n", i, readl(chip->remap_addr + i)); 1500 } 1501 1502 static void snd_atiixp_proc_init(struct atiixp *chip) 1503 { 1504 snd_card_ro_proc_new(chip->card, "atiixp", chip, snd_atiixp_proc_read); 1505 } 1506 1507 1508 /* 1509 * destructor 1510 */ 1511 1512 static void snd_atiixp_free(struct snd_card *card) 1513 { 1514 snd_atiixp_chip_stop(card->private_data); 1515 } 1516 1517 /* 1518 * constructor for chip instance 1519 */ 1520 static int snd_atiixp_init(struct snd_card *card, struct pci_dev *pci) 1521 { 1522 struct atiixp *chip = card->private_data; 1523 int err; 1524 1525 err = pcim_enable_device(pci); 1526 if (err < 0) 1527 return err; 1528 1529 spin_lock_init(&chip->reg_lock); 1530 mutex_init(&chip->open_mutex); 1531 chip->card = card; 1532 chip->pci = pci; 1533 chip->irq = -1; 1534 chip->remap_addr = pcim_iomap_region(pci, 0, "ATI IXP AC97"); 1535 if (IS_ERR(chip->remap_addr)) 1536 return PTR_ERR(chip->remap_addr); 1537 chip->addr = pci_resource_start(pci, 0); 1538 1539 if (devm_request_irq(&pci->dev, pci->irq, snd_atiixp_interrupt, 1540 IRQF_SHARED, KBUILD_MODNAME, chip)) { 1541 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); 1542 return -EBUSY; 1543 } 1544 chip->irq = pci->irq; 1545 card->sync_irq = chip->irq; 1546 card->private_free = snd_atiixp_free; 1547 pci_set_master(pci); 1548 1549 return 0; 1550 } 1551 1552 1553 static int __snd_atiixp_probe(struct pci_dev *pci, 1554 const struct pci_device_id *pci_id) 1555 { 1556 struct snd_card *card; 1557 struct atiixp *chip; 1558 int err; 1559 1560 err = snd_devm_card_new(&pci->dev, index, id, THIS_MODULE, 1561 sizeof(*chip), &card); 1562 if (err < 0) 1563 return err; 1564 chip = card->private_data; 1565 1566 strscpy(card->driver, spdif_aclink ? "ATIIXP" : "ATIIXP-SPDMA"); 1567 strscpy(card->shortname, "ATI IXP"); 1568 err = snd_atiixp_init(card, pci); 1569 if (err < 0) 1570 return err; 1571 1572 err = snd_atiixp_aclink_reset(chip); 1573 if (err < 0) 1574 return err; 1575 1576 chip->spdif_over_aclink = spdif_aclink; 1577 1578 err = snd_atiixp_mixer_new(chip, ac97_clock, ac97_quirk); 1579 if (err < 0) 1580 return err; 1581 1582 err = snd_atiixp_pcm_new(chip); 1583 if (err < 0) 1584 return err; 1585 1586 snd_atiixp_proc_init(chip); 1587 1588 snd_atiixp_chip_start(chip); 1589 1590 snprintf(card->longname, sizeof(card->longname), 1591 "%s rev %x with %s at %#lx, irq %i", card->shortname, 1592 pci->revision, 1593 chip->ac97[0] ? snd_ac97_get_short_name(chip->ac97[0]) : "?", 1594 chip->addr, chip->irq); 1595 1596 err = snd_card_register(card); 1597 if (err < 0) 1598 return err; 1599 1600 pci_set_drvdata(pci, card); 1601 return 0; 1602 } 1603 1604 static int snd_atiixp_probe(struct pci_dev *pci, 1605 const struct pci_device_id *pci_id) 1606 { 1607 return snd_card_free_on_error(&pci->dev, __snd_atiixp_probe(pci, pci_id)); 1608 } 1609 1610 static struct pci_driver atiixp_driver = { 1611 .name = KBUILD_MODNAME, 1612 .id_table = snd_atiixp_ids, 1613 .probe = snd_atiixp_probe, 1614 .driver = { 1615 .pm = &snd_atiixp_pm, 1616 }, 1617 }; 1618 1619 module_pci_driver(atiixp_driver); 1620