1 /*
2 * Copyright (c) 2009-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 /*
18 * Module for common driver code between ath9k and ath9k_htc
19 */
20
21 #include <linux/export.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24
25 #include "common.h"
26
27 MODULE_AUTHOR("Atheros Communications");
28 MODULE_DESCRIPTION("Shared library for Atheros wireless 802.11n LAN cards.");
29 MODULE_LICENSE("Dual BSD/GPL");
30
31 /* Assumes you've already done the endian to CPU conversion */
ath9k_cmn_rx_accept(struct ath_common * common,struct ieee80211_hdr * hdr,struct ieee80211_rx_status * rxs,struct ath_rx_status * rx_stats,bool * decrypt_error,unsigned int rxfilter)32 bool ath9k_cmn_rx_accept(struct ath_common *common,
33 struct ieee80211_hdr *hdr,
34 struct ieee80211_rx_status *rxs,
35 struct ath_rx_status *rx_stats,
36 bool *decrypt_error,
37 unsigned int rxfilter)
38 {
39 struct ath_hw *ah = common->ah;
40 bool is_mc, is_valid_tkip, strip_mic, mic_error;
41 __le16 fc;
42
43 fc = hdr->frame_control;
44
45 is_mc = !!is_multicast_ether_addr(hdr->addr1);
46 is_valid_tkip = rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID &&
47 test_bit(rx_stats->rs_keyix, common->tkip_keymap);
48 strip_mic = is_valid_tkip && ieee80211_is_data(fc) &&
49 ieee80211_has_protected(fc) &&
50 !(rx_stats->rs_status &
51 (ATH9K_RXERR_DECRYPT | ATH9K_RXERR_CRC | ATH9K_RXERR_MIC |
52 ATH9K_RXERR_KEYMISS));
53
54 /*
55 * Key miss events are only relevant for pairwise keys where the
56 * descriptor does contain a valid key index. This has been observed
57 * mostly with CCMP encryption.
58 */
59 if (rx_stats->rs_keyix == ATH9K_RXKEYIX_INVALID ||
60 !test_bit(rx_stats->rs_keyix, common->ccmp_keymap))
61 rx_stats->rs_status &= ~ATH9K_RXERR_KEYMISS;
62
63 mic_error = is_valid_tkip && !ieee80211_is_ctl(fc) &&
64 !ieee80211_has_morefrags(fc) &&
65 !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
66 (rx_stats->rs_status & ATH9K_RXERR_MIC);
67
68 /*
69 * The rx_stats->rs_status will not be set until the end of the
70 * chained descriptors so it can be ignored if rs_more is set. The
71 * rs_more will be false at the last element of the chained
72 * descriptors.
73 */
74 if (rx_stats->rs_status != 0) {
75 u8 status_mask;
76
77 if (rx_stats->rs_status & ATH9K_RXERR_CRC) {
78 rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
79 mic_error = false;
80 }
81
82 if ((rx_stats->rs_status & ATH9K_RXERR_DECRYPT) ||
83 (!is_mc && (rx_stats->rs_status & ATH9K_RXERR_KEYMISS))) {
84 *decrypt_error = true;
85 mic_error = false;
86 }
87
88
89 /*
90 * Reject error frames with the exception of
91 * decryption and MIC failures. For monitor mode,
92 * we also ignore the CRC error.
93 */
94 status_mask = ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
95 ATH9K_RXERR_KEYMISS;
96
97 if (ah->is_monitoring && (rxfilter & FIF_FCSFAIL))
98 status_mask |= ATH9K_RXERR_CRC;
99
100 if (rx_stats->rs_status & ~status_mask)
101 return false;
102 }
103
104 /*
105 * For unicast frames the MIC error bit can have false positives,
106 * so all MIC error reports need to be validated in software.
107 * False negatives are not common, so skip software verification
108 * if the hardware considers the MIC valid.
109 */
110 if (strip_mic)
111 rxs->flag |= RX_FLAG_MMIC_STRIPPED;
112 else if (is_mc && mic_error)
113 rxs->flag |= RX_FLAG_MMIC_ERROR;
114
115 return true;
116 }
117 EXPORT_SYMBOL(ath9k_cmn_rx_accept);
118
ath9k_cmn_rx_skb_postprocess(struct ath_common * common,struct sk_buff * skb,struct ath_rx_status * rx_stats,struct ieee80211_rx_status * rxs,bool decrypt_error)119 void ath9k_cmn_rx_skb_postprocess(struct ath_common *common,
120 struct sk_buff *skb,
121 struct ath_rx_status *rx_stats,
122 struct ieee80211_rx_status *rxs,
123 bool decrypt_error)
124 {
125 struct ath_hw *ah = common->ah;
126 struct ieee80211_hdr *hdr;
127 int hdrlen, padpos, padsize;
128 u8 keyix;
129 __le16 fc;
130
131 /* see if any padding is done by the hw and remove it */
132 hdr = (struct ieee80211_hdr *) skb->data;
133 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
134 fc = hdr->frame_control;
135 padpos = ieee80211_hdrlen(fc);
136
137 /* The MAC header is padded to have 32-bit boundary if the
138 * packet payload is non-zero. The general calculation for
139 * padsize would take into account odd header lengths:
140 * padsize = (4 - padpos % 4) % 4; However, since only
141 * even-length headers are used, padding can only be 0 or 2
142 * bytes and we can optimize this a bit. In addition, we must
143 * not try to remove padding from short control frames that do
144 * not have payload. */
145 padsize = padpos & 3;
146 if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
147 memmove(skb->data + padsize, skb->data, padpos);
148 skb_pull(skb, padsize);
149 }
150
151 keyix = rx_stats->rs_keyix;
152
153 if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error &&
154 ieee80211_has_protected(fc)) {
155 rxs->flag |= RX_FLAG_DECRYPTED;
156 } else if (ieee80211_has_protected(fc)
157 && !decrypt_error && skb->len >= hdrlen + 4) {
158 keyix = skb->data[hdrlen + 3] >> 6;
159
160 if (test_bit(keyix, common->keymap))
161 rxs->flag |= RX_FLAG_DECRYPTED;
162 }
163 if (ah->sw_mgmt_crypto_rx &&
164 (rxs->flag & RX_FLAG_DECRYPTED) &&
165 ieee80211_is_mgmt(fc))
166 /* Use software decrypt for management frames. */
167 rxs->flag &= ~RX_FLAG_DECRYPTED;
168 }
169 EXPORT_SYMBOL(ath9k_cmn_rx_skb_postprocess);
170
ath9k_cmn_process_rate(struct ath_common * common,struct ieee80211_hw * hw,struct ath_rx_status * rx_stats,struct ieee80211_rx_status * rxs)171 int ath9k_cmn_process_rate(struct ath_common *common,
172 struct ieee80211_hw *hw,
173 struct ath_rx_status *rx_stats,
174 struct ieee80211_rx_status *rxs)
175 {
176 struct ieee80211_supported_band *sband;
177 enum nl80211_band band;
178 unsigned int i = 0;
179 struct ath_hw *ah = common->ah;
180
181 band = ah->curchan->chan->band;
182 sband = hw->wiphy->bands[band];
183
184 if (IS_CHAN_QUARTER_RATE(ah->curchan))
185 rxs->bw = RATE_INFO_BW_5;
186 else if (IS_CHAN_HALF_RATE(ah->curchan))
187 rxs->bw = RATE_INFO_BW_10;
188
189 if (rx_stats->rs_rate & 0x80) {
190 /* HT rate */
191 rxs->encoding = RX_ENC_HT;
192 rxs->enc_flags |= rx_stats->enc_flags;
193 rxs->bw = rx_stats->bw;
194 rxs->rate_idx = rx_stats->rs_rate & 0x7f;
195 return 0;
196 }
197
198 for (i = 0; i < sband->n_bitrates; i++) {
199 if (sband->bitrates[i].hw_value == rx_stats->rs_rate) {
200 rxs->rate_idx = i;
201 return 0;
202 }
203 if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
204 rxs->enc_flags |= RX_ENC_FLAG_SHORTPRE;
205 rxs->rate_idx = i;
206 return 0;
207 }
208 }
209
210 return -EINVAL;
211 }
212 EXPORT_SYMBOL(ath9k_cmn_process_rate);
213
ath9k_cmn_process_rssi(struct ath_common * common,struct ieee80211_hw * hw,struct ath_rx_status * rx_stats,struct ieee80211_rx_status * rxs)214 void ath9k_cmn_process_rssi(struct ath_common *common,
215 struct ieee80211_hw *hw,
216 struct ath_rx_status *rx_stats,
217 struct ieee80211_rx_status *rxs)
218 {
219 struct ath_hw *ah = common->ah;
220 int last_rssi;
221 int rssi = rx_stats->rs_rssi;
222 int i, j;
223
224 /*
225 * RSSI is not available for subframes in an A-MPDU.
226 */
227 if (rx_stats->rs_moreaggr) {
228 rxs->flag |= RX_FLAG_NO_SIGNAL_VAL;
229 return;
230 }
231
232 /*
233 * Check if the RSSI for the last subframe in an A-MPDU
234 * or an unaggregated frame is valid.
235 */
236 if (rx_stats->rs_rssi == ATH9K_RSSI_BAD) {
237 rxs->flag |= RX_FLAG_NO_SIGNAL_VAL;
238 return;
239 }
240
241 for (i = 0, j = 0; i < ARRAY_SIZE(rx_stats->rs_rssi_ctl); i++) {
242 s8 rssi;
243
244 if (!(ah->rxchainmask & BIT(i)))
245 continue;
246
247 rssi = rx_stats->rs_rssi_ctl[i];
248 if (rssi != ATH9K_RSSI_BAD) {
249 rxs->chains |= BIT(j);
250 rxs->chain_signal[j] = ah->noise + rssi;
251 }
252 j++;
253 }
254
255 /*
256 * Update Beacon RSSI, this is used by ANI.
257 */
258 if (rx_stats->is_mybeacon &&
259 ((ah->opmode == NL80211_IFTYPE_STATION) ||
260 (ah->opmode == NL80211_IFTYPE_ADHOC))) {
261 ATH_RSSI_LPF(common->last_rssi, rx_stats->rs_rssi);
262 last_rssi = common->last_rssi;
263
264 if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
265 rssi = ATH_EP_RND(last_rssi, ATH_RSSI_EP_MULTIPLIER);
266 if (rssi < 0)
267 rssi = 0;
268
269 ah->stats.avgbrssi = rssi;
270 }
271
272 rxs->signal = ah->noise + rx_stats->rs_rssi;
273 }
274 EXPORT_SYMBOL(ath9k_cmn_process_rssi);
275
ath9k_cmn_get_hw_crypto_keytype(struct sk_buff * skb)276 int ath9k_cmn_get_hw_crypto_keytype(struct sk_buff *skb)
277 {
278 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
279
280 if (tx_info->control.hw_key) {
281 switch (tx_info->control.hw_key->cipher) {
282 case WLAN_CIPHER_SUITE_WEP40:
283 case WLAN_CIPHER_SUITE_WEP104:
284 return ATH9K_KEY_TYPE_WEP;
285 case WLAN_CIPHER_SUITE_TKIP:
286 return ATH9K_KEY_TYPE_TKIP;
287 case WLAN_CIPHER_SUITE_CCMP:
288 return ATH9K_KEY_TYPE_AES;
289 default:
290 break;
291 }
292 }
293
294 return ATH9K_KEY_TYPE_CLEAR;
295 }
296 EXPORT_SYMBOL(ath9k_cmn_get_hw_crypto_keytype);
297
298 /*
299 * Update internal channel flags.
300 */
ath9k_cmn_update_ichannel(struct ath9k_channel * ichan,struct cfg80211_chan_def * chandef)301 static void ath9k_cmn_update_ichannel(struct ath9k_channel *ichan,
302 struct cfg80211_chan_def *chandef)
303 {
304 struct ieee80211_channel *chan = chandef->chan;
305 u16 flags = 0;
306
307 ichan->channel = chan->center_freq;
308 ichan->chan = chan;
309
310 if (chan->band == NL80211_BAND_5GHZ)
311 flags |= CHANNEL_5GHZ;
312
313 switch (chandef->width) {
314 case NL80211_CHAN_WIDTH_5:
315 flags |= CHANNEL_QUARTER;
316 break;
317 case NL80211_CHAN_WIDTH_10:
318 flags |= CHANNEL_HALF;
319 break;
320 case NL80211_CHAN_WIDTH_20_NOHT:
321 break;
322 case NL80211_CHAN_WIDTH_20:
323 flags |= CHANNEL_HT;
324 break;
325 case NL80211_CHAN_WIDTH_40:
326 if (chandef->center_freq1 > chandef->chan->center_freq)
327 flags |= CHANNEL_HT40PLUS | CHANNEL_HT;
328 else
329 flags |= CHANNEL_HT40MINUS | CHANNEL_HT;
330 break;
331 default:
332 WARN_ON(1);
333 }
334
335 ichan->channelFlags = flags;
336 }
337
338 /*
339 * Get the internal channel reference.
340 */
ath9k_cmn_get_channel(struct ieee80211_hw * hw,struct ath_hw * ah,struct cfg80211_chan_def * chandef)341 struct ath9k_channel *ath9k_cmn_get_channel(struct ieee80211_hw *hw,
342 struct ath_hw *ah,
343 struct cfg80211_chan_def *chandef)
344 {
345 struct ieee80211_channel *curchan = chandef->chan;
346 struct ath9k_channel *channel;
347
348 channel = &ah->channels[curchan->hw_value];
349 ath9k_cmn_update_ichannel(channel, chandef);
350
351 return channel;
352 }
353 EXPORT_SYMBOL(ath9k_cmn_get_channel);
354
ath9k_cmn_count_streams(unsigned int chainmask,int max)355 int ath9k_cmn_count_streams(unsigned int chainmask, int max)
356 {
357 int streams = 0;
358
359 do {
360 if (++streams == max)
361 break;
362 } while ((chainmask = chainmask & (chainmask - 1)));
363
364 return streams;
365 }
366 EXPORT_SYMBOL(ath9k_cmn_count_streams);
367
ath9k_cmn_update_txpow(struct ath_hw * ah,u16 cur_txpow,u16 new_txpow,u16 * txpower)368 void ath9k_cmn_update_txpow(struct ath_hw *ah, u16 cur_txpow,
369 u16 new_txpow, u16 *txpower)
370 {
371 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
372
373 if (ah->curchan && reg->power_limit != new_txpow)
374 ath9k_hw_set_txpowerlimit(ah, new_txpow, false);
375
376 /* read back in case value is clamped */
377 *txpower = reg->max_power_level;
378 }
379 EXPORT_SYMBOL(ath9k_cmn_update_txpow);
380
ath9k_cmn_init_crypto(struct ath_hw * ah)381 void ath9k_cmn_init_crypto(struct ath_hw *ah)
382 {
383 struct ath_common *common = ath9k_hw_common(ah);
384 int i = 0;
385
386 /* Get the hardware key cache size. */
387 common->keymax = AR_KEYTABLE_SIZE;
388
389 /*
390 * Check whether the separate key cache entries
391 * are required to handle both tx+rx MIC keys.
392 * With split mic keys the number of stations is limited
393 * to 27 otherwise 59.
394 */
395 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA)
396 common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
397
398 /*
399 * Reset the key cache since some parts do not
400 * reset the contents on initial power up.
401 */
402 for (i = 0; i < common->keymax; i++)
403 ath_hw_keyreset(common, (u16) i);
404 }
405 EXPORT_SYMBOL(ath9k_cmn_init_crypto);
406
ath9k_cmn_init(void)407 static int __init ath9k_cmn_init(void)
408 {
409 return 0;
410 }
411 module_init(ath9k_cmn_init);
412
ath9k_cmn_exit(void)413 static void __exit ath9k_cmn_exit(void)
414 {
415 return;
416 }
417 module_exit(ath9k_cmn_exit);
418