1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 #include <linux/skbuff.h> 7 #include <linux/ctype.h> 8 #include <net/mac80211.h> 9 #include <net/cfg80211.h> 10 #include <linux/completion.h> 11 #include <linux/if_ether.h> 12 #include <linux/types.h> 13 #include <linux/pci.h> 14 #include <linux/uuid.h> 15 #include <linux/time.h> 16 #include <linux/of.h> 17 #include <linux/cleanup.h> 18 #include <linux/percpu.h> 19 #include <linux/refcount.h> 20 #include "core.h" 21 #include "debugfs.h" 22 #include "debug.h" 23 #include "mac.h" 24 #include "hw.h" 25 #include "peer.h" 26 #include "p2p.h" 27 #include "testmode.h" 28 29 struct ath12k_wmi_svc_ready_parse { 30 bool wmi_svc_bitmap_done; 31 }; 32 33 struct wmi_tlv_fw_stats_parse { 34 const struct wmi_stats_event *ev; 35 struct ath12k_fw_stats *stats; 36 const struct wmi_per_chain_rssi_stat_params *rssi; 37 int rssi_num; 38 bool chain_rssi_done; 39 }; 40 41 struct ath12k_wmi_dma_ring_caps_parse { 42 struct ath12k_wmi_dma_ring_caps_params *dma_ring_caps; 43 u32 n_dma_ring_caps; 44 }; 45 46 struct ath12k_wmi_service_ext_arg { 47 u32 default_conc_scan_config_bits; 48 u32 default_fw_config_bits; 49 struct ath12k_wmi_ppe_threshold_arg ppet; 50 u32 he_cap_info; 51 u32 mpdu_density; 52 u32 max_bssid_rx_filters; 53 u32 num_hw_modes; 54 u32 num_phy; 55 }; 56 57 struct ath12k_wmi_svc_rdy_ext_parse { 58 struct ath12k_wmi_service_ext_arg arg; 59 const struct ath12k_wmi_soc_mac_phy_hw_mode_caps_params *hw_caps; 60 const struct ath12k_wmi_hw_mode_cap_params *hw_mode_caps; 61 u32 n_hw_mode_caps; 62 u32 tot_phy_id; 63 struct ath12k_wmi_hw_mode_cap_params pref_hw_mode_caps; 64 struct ath12k_wmi_mac_phy_caps_params *mac_phy_caps; 65 u32 n_mac_phy_caps; 66 const struct ath12k_wmi_soc_hal_reg_caps_params *soc_hal_reg_caps; 67 const struct ath12k_wmi_hal_reg_caps_ext_params *ext_hal_reg_caps; 68 u32 n_ext_hal_reg_caps; 69 struct ath12k_wmi_dma_ring_caps_parse dma_caps_parse; 70 bool hw_mode_done; 71 bool mac_phy_done; 72 bool ext_hal_reg_done; 73 bool mac_phy_chainmask_combo_done; 74 bool mac_phy_chainmask_cap_done; 75 bool oem_dma_ring_cap_done; 76 bool dma_ring_cap_done; 77 }; 78 79 struct ath12k_wmi_svc_rdy_ext2_arg { 80 u32 reg_db_version; 81 u32 hw_min_max_tx_power_2ghz; 82 u32 hw_min_max_tx_power_5ghz; 83 u32 chwidth_num_peer_caps; 84 u32 preamble_puncture_bw; 85 u32 max_user_per_ppdu_ofdma; 86 u32 max_user_per_ppdu_mumimo; 87 u32 target_cap_flags; 88 u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE]; 89 u32 max_num_linkview_peers; 90 u32 max_num_msduq_supported_per_tid; 91 u32 default_num_msduq_supported_per_tid; 92 }; 93 94 struct ath12k_wmi_svc_rdy_ext2_parse { 95 struct ath12k_wmi_svc_rdy_ext2_arg arg; 96 struct ath12k_wmi_dma_ring_caps_parse dma_caps_parse; 97 bool dma_ring_cap_done; 98 bool spectral_bin_scaling_done; 99 bool mac_phy_caps_ext_done; 100 bool hal_reg_caps_ext2_done; 101 bool scan_radio_caps_ext2_done; 102 bool twt_caps_done; 103 bool htt_msdu_idx_to_qtype_map_done; 104 bool dbs_or_sbs_cap_ext_done; 105 }; 106 107 struct ath12k_wmi_rdy_parse { 108 u32 num_extra_mac_addr; 109 }; 110 111 struct ath12k_wmi_dma_buf_release_arg { 112 struct ath12k_wmi_dma_buf_release_fixed_params fixed; 113 const struct ath12k_wmi_dma_buf_release_entry_params *buf_entry; 114 const struct ath12k_wmi_dma_buf_release_meta_data_params *meta_data; 115 u32 num_buf_entry; 116 u32 num_meta; 117 bool buf_entry_done; 118 bool meta_data_done; 119 }; 120 121 struct ath12k_wmi_tlv_policy { 122 size_t min_len; 123 }; 124 125 struct wmi_tlv_mgmt_rx_parse { 126 const struct ath12k_wmi_mgmt_rx_params *fixed; 127 const u8 *frame_buf; 128 bool frame_buf_done; 129 }; 130 131 struct wmi_pdev_set_obss_bitmap_arg { 132 u32 tlv_tag; 133 u32 pdev_id; 134 u32 cmd_id; 135 const u32 *bitmap; 136 const char *label; 137 }; 138 139 static DEFINE_MUTEX(ath12k_wmi_mutex); 140 static refcount_t ath12k_wmi_refcount; 141 static void __percpu *ath12k_wmi_tb; 142 143 static const struct ath12k_wmi_tlv_policy ath12k_wmi_tlv_policies[] = { 144 [WMI_TAG_ARRAY_BYTE] = { .min_len = 0 }, 145 [WMI_TAG_ARRAY_UINT32] = { .min_len = 0 }, 146 [WMI_TAG_SERVICE_READY_EVENT] = { 147 .min_len = sizeof(struct wmi_service_ready_event) }, 148 [WMI_TAG_SERVICE_READY_EXT_EVENT] = { 149 .min_len = sizeof(struct wmi_service_ready_ext_event) }, 150 [WMI_TAG_SOC_MAC_PHY_HW_MODE_CAPS] = { 151 .min_len = sizeof(struct ath12k_wmi_soc_mac_phy_hw_mode_caps_params) }, 152 [WMI_TAG_SOC_HAL_REG_CAPABILITIES] = { 153 .min_len = sizeof(struct ath12k_wmi_soc_hal_reg_caps_params) }, 154 [WMI_TAG_VDEV_START_RESPONSE_EVENT] = { 155 .min_len = sizeof(struct wmi_vdev_start_resp_event) }, 156 [WMI_TAG_PEER_DELETE_RESP_EVENT] = { 157 .min_len = sizeof(struct wmi_peer_delete_resp_event) }, 158 [WMI_TAG_OFFLOAD_BCN_TX_STATUS_EVENT] = { 159 .min_len = sizeof(struct wmi_bcn_tx_status_event) }, 160 [WMI_TAG_VDEV_STOPPED_EVENT] = { 161 .min_len = sizeof(struct wmi_vdev_stopped_event) }, 162 [WMI_TAG_REG_CHAN_LIST_CC_EXT_EVENT] = { 163 .min_len = sizeof(struct wmi_reg_chan_list_cc_ext_event) }, 164 [WMI_TAG_MGMT_RX_HDR] = { 165 .min_len = sizeof(struct ath12k_wmi_mgmt_rx_params) }, 166 [WMI_TAG_MGMT_TX_COMPL_EVENT] = { 167 .min_len = sizeof(struct wmi_mgmt_tx_compl_event) }, 168 [WMI_TAG_SCAN_EVENT] = { 169 .min_len = sizeof(struct wmi_scan_event) }, 170 [WMI_TAG_PEER_STA_KICKOUT_EVENT] = { 171 .min_len = sizeof(struct wmi_peer_sta_kickout_event) }, 172 [WMI_TAG_ROAM_EVENT] = { 173 .min_len = sizeof(struct wmi_roam_event) }, 174 [WMI_TAG_CHAN_INFO_EVENT] = { 175 .min_len = sizeof(struct wmi_chan_info_event) }, 176 [WMI_TAG_PDEV_BSS_CHAN_INFO_EVENT] = { 177 .min_len = sizeof(struct wmi_pdev_bss_chan_info_event) }, 178 [WMI_TAG_VDEV_INSTALL_KEY_COMPLETE_EVENT] = { 179 .min_len = sizeof(struct wmi_vdev_install_key_compl_event) }, 180 [WMI_TAG_READY_EVENT] = { 181 .min_len = sizeof(struct ath12k_wmi_ready_event_min_params) }, 182 [WMI_TAG_SERVICE_AVAILABLE_EVENT] = { 183 .min_len = sizeof(struct wmi_service_available_event) }, 184 [WMI_TAG_PEER_ASSOC_CONF_EVENT] = { 185 .min_len = sizeof(struct wmi_peer_assoc_conf_event) }, 186 [WMI_TAG_RFKILL_EVENT] = { 187 .min_len = sizeof(struct wmi_rfkill_state_change_event) }, 188 [WMI_TAG_PDEV_CTL_FAILSAFE_CHECK_EVENT] = { 189 .min_len = sizeof(struct wmi_pdev_ctl_failsafe_chk_event) }, 190 [WMI_TAG_HOST_SWFDA_EVENT] = { 191 .min_len = sizeof(struct wmi_fils_discovery_event) }, 192 [WMI_TAG_OFFLOAD_PRB_RSP_TX_STATUS_EVENT] = { 193 .min_len = sizeof(struct wmi_probe_resp_tx_status_event) }, 194 [WMI_TAG_VDEV_DELETE_RESP_EVENT] = { 195 .min_len = sizeof(struct wmi_vdev_delete_resp_event) }, 196 [WMI_TAG_TWT_ENABLE_COMPLETE_EVENT] = { 197 .min_len = sizeof(struct wmi_twt_enable_event) }, 198 [WMI_TAG_TWT_DISABLE_COMPLETE_EVENT] = { 199 .min_len = sizeof(struct wmi_twt_disable_event) }, 200 [WMI_TAG_P2P_NOA_INFO] = { 201 .min_len = sizeof(struct ath12k_wmi_p2p_noa_info) }, 202 [WMI_TAG_P2P_NOA_EVENT] = { 203 .min_len = sizeof(struct wmi_p2p_noa_event) }, 204 [WMI_TAG_11D_NEW_COUNTRY_EVENT] = { 205 .min_len = sizeof(struct wmi_11d_new_cc_event) }, 206 [WMI_TAG_PER_CHAIN_RSSI_STATS] = { 207 .min_len = sizeof(struct wmi_per_chain_rssi_stat_params) }, 208 [WMI_TAG_OBSS_COLOR_COLLISION_EVT] = { 209 .min_len = sizeof(struct wmi_obss_color_collision_event) }, 210 }; 211 212 __le32 ath12k_wmi_tlv_hdr(u32 cmd, u32 len) 213 { 214 return le32_encode_bits(cmd, WMI_TLV_TAG) | 215 le32_encode_bits(len, WMI_TLV_LEN); 216 } 217 218 static __le32 ath12k_wmi_tlv_cmd_hdr(u32 cmd, u32 len) 219 { 220 return ath12k_wmi_tlv_hdr(cmd, len - TLV_HDR_SIZE); 221 } 222 223 #define PRIMAP(_hw_mode_) \ 224 [_hw_mode_] = _hw_mode_##_PRI 225 226 static const int ath12k_hw_mode_pri_map[] = { 227 PRIMAP(WMI_HOST_HW_MODE_SINGLE), 228 PRIMAP(WMI_HOST_HW_MODE_DBS), 229 PRIMAP(WMI_HOST_HW_MODE_SBS_PASSIVE), 230 PRIMAP(WMI_HOST_HW_MODE_SBS), 231 PRIMAP(WMI_HOST_HW_MODE_DBS_SBS), 232 PRIMAP(WMI_HOST_HW_MODE_DBS_OR_SBS), 233 /* keep last */ 234 PRIMAP(WMI_HOST_HW_MODE_MAX), 235 }; 236 237 /* 238 * Interference bitmap transform maps used by 239 * ath12k_wmi_transform_interference_bitmap(). 240 * 241 * Firmware reports bitmap bits in a primary-based order where: 242 * - bit 0 is always the primary 20 MHz segment, 243 * - bit 1 is the adjacent 20 MHz in the same 40 MHz block, 244 * - bit 2 is the lower 20 MHz segment of the adjacent 40 MHz segment 245 * - bit 3 is the higher 20 MHz segment of the adjacent 40 MHz segment 246 * - remaining bits continue outward in 80/160/320 MHz groups. 247 * 248 * cfg80211 userspace notification expects absolute frequency order where: 249 * - bit 0 is the lowest-frequency 20 MHz segment in the current chandef, 250 * - bit N increases monotonically toward higher frequency. 251 * 252 * For each bandwidth-specific map: 253 * - row index = primary 20 MHz index in absolute (low->high) order, 254 * - column index = source bit position from firmware bitmap, 255 * - value = destination bit position in absolute order bitmap. 256 * 257 * Example for 80 MHz: if primary index is 2 (third 20 MHz chunk from low 258 * frequency), row intf_map_80[2] = { 2, 3, 0, 1 } means firmware bits {0,1,2,3} 259 * are remapped to destination bits {2,3,0,1} before notifying cfg80211. 260 */ 261 262 static const int intf_map_80[4][4] = { 263 { 0, 1, 2, 3 }, 264 { 1, 0, 2, 3 }, 265 { 2, 3, 0, 1 }, 266 { 3, 2, 0, 1 } 267 }; 268 269 static const int intf_map_160[8][8] = { 270 { 0, 1, 2, 3, 4, 5, 6, 7 }, 271 { 1, 0, 2, 3, 4, 5, 6, 7 }, 272 { 2, 3, 0, 1, 4, 5, 6, 7 }, 273 { 3, 2, 0, 1, 4, 5, 6, 7 }, 274 { 4, 5, 6, 7, 0, 1, 2, 3 }, 275 { 5, 4, 6, 7, 0, 1, 2, 3 }, 276 { 6, 7, 4, 5, 0, 1, 2, 3 }, 277 { 7, 6, 4, 5, 0, 1, 2, 3 } 278 }; 279 280 static const int intf_map_320[16][16] = { 281 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, 282 { 1, 0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, 283 { 2, 3, 0, 1, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, 284 { 3, 2, 0, 1, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, 285 { 4, 5, 6, 7, 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 14, 15 }, 286 { 5, 4, 6, 7, 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 14, 15 }, 287 { 6, 7, 4, 5, 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 14, 15 }, 288 { 7, 6, 4, 5, 0, 1, 2, 3, 8, 9, 10, 11, 12, 13, 14, 15 }, 289 { 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7 }, 290 { 9, 8, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7 }, 291 { 10, 11, 8, 9, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7 }, 292 { 11, 10, 8, 9, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7 }, 293 { 12, 13, 14, 15, 8, 9, 10, 11, 0, 1, 2, 3, 4, 5, 6, 7 }, 294 { 13, 12, 14, 15, 8, 9, 10, 11, 0, 1, 2, 3, 4, 5, 6, 7 }, 295 { 14, 15, 12, 13, 8, 9, 10, 11, 0, 1, 2, 3, 4, 5, 6, 7 }, 296 { 15, 14, 12, 13, 8, 9, 10, 11, 0, 1, 2, 3, 4, 5, 6, 7 } 297 }; 298 299 static int 300 ath12k_wmi_tlv_iter(struct ath12k_base *ab, const void *ptr, size_t len, 301 int (*iter)(struct ath12k_base *ab, u16 tag, u16 len, 302 const void *ptr, void *data), 303 void *data) 304 { 305 const void *begin = ptr; 306 const struct wmi_tlv *tlv; 307 u16 tlv_tag, tlv_len; 308 int ret; 309 310 while (len > 0) { 311 if (len < sizeof(*tlv)) { 312 ath12k_err(ab, "wmi tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n", 313 ptr - begin, len, sizeof(*tlv)); 314 return -EINVAL; 315 } 316 317 tlv = ptr; 318 tlv_tag = le32_get_bits(tlv->header, WMI_TLV_TAG); 319 tlv_len = le32_get_bits(tlv->header, WMI_TLV_LEN); 320 ptr += sizeof(*tlv); 321 len -= sizeof(*tlv); 322 323 if (tlv_len > len) { 324 ath12k_err(ab, "wmi tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n", 325 tlv_tag, ptr - begin, len, tlv_len); 326 return -EINVAL; 327 } 328 329 if (tlv_tag < ARRAY_SIZE(ath12k_wmi_tlv_policies) && 330 ath12k_wmi_tlv_policies[tlv_tag].min_len && 331 ath12k_wmi_tlv_policies[tlv_tag].min_len > tlv_len) { 332 ath12k_err(ab, "wmi tlv parse failure of tag %u at byte %zd (%u bytes is less than min length %zu)\n", 333 tlv_tag, ptr - begin, tlv_len, 334 ath12k_wmi_tlv_policies[tlv_tag].min_len); 335 return -EINVAL; 336 } 337 338 ret = iter(ab, tlv_tag, tlv_len, ptr, data); 339 if (ret) 340 return ret; 341 342 ptr += tlv_len; 343 len -= tlv_len; 344 } 345 346 return 0; 347 } 348 349 static int ath12k_wmi_tlv_iter_parse(struct ath12k_base *ab, u16 tag, u16 len, 350 const void *ptr, void *data) 351 { 352 const void **tb = data; 353 354 if (tag < WMI_TAG_MAX) 355 tb[tag] = ptr; 356 357 return 0; 358 } 359 360 static const void ** 361 ath12k_wmi_tlv_parse(struct ath12k_base *ab, struct sk_buff *skb) 362 { 363 const void **tb; 364 int ret; 365 366 tb = this_cpu_ptr(ath12k_wmi_tb); 367 memset(tb, 0, WMI_TAG_MAX * sizeof(*tb)); 368 369 ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, 370 ath12k_wmi_tlv_iter_parse, (void *)tb); 371 if (ret) 372 return ERR_PTR(ret); 373 374 return tb; 375 } 376 377 static int ath12k_wmi_cmd_send_nowait(struct ath12k_wmi_pdev *wmi, struct sk_buff *skb, 378 u32 cmd_id) 379 { 380 struct ath12k_skb_cb *skb_cb = ATH12K_SKB_CB(skb); 381 struct ath12k_base *ab = wmi->wmi_ab->ab; 382 struct wmi_cmd_hdr *cmd_hdr; 383 int ret; 384 385 if (!skb_push(skb, sizeof(struct wmi_cmd_hdr))) 386 return -ENOMEM; 387 388 cmd_hdr = (struct wmi_cmd_hdr *)skb->data; 389 cmd_hdr->cmd_id = le32_encode_bits(cmd_id, WMI_CMD_HDR_CMD_ID); 390 391 memset(skb_cb, 0, sizeof(*skb_cb)); 392 ret = ath12k_htc_send(&ab->htc, wmi->eid, skb); 393 394 if (ret) 395 goto err_pull; 396 397 return 0; 398 399 err_pull: 400 skb_pull(skb, sizeof(struct wmi_cmd_hdr)); 401 return ret; 402 } 403 404 int ath12k_wmi_cmd_send(struct ath12k_wmi_pdev *wmi, struct sk_buff *skb, 405 u32 cmd_id) 406 { 407 struct ath12k_wmi_base *wmi_ab = wmi->wmi_ab; 408 int ret = -EOPNOTSUPP; 409 410 might_sleep(); 411 412 wait_event_timeout(wmi_ab->tx_credits_wq, ({ 413 ret = ath12k_wmi_cmd_send_nowait(wmi, skb, cmd_id); 414 415 if (ret && test_bit(ATH12K_FLAG_CRASH_FLUSH, &wmi_ab->ab->dev_flags)) 416 ret = -ESHUTDOWN; 417 418 (ret != -EAGAIN); 419 }), WMI_SEND_TIMEOUT_HZ); 420 421 if (ret == -EAGAIN) 422 ath12k_warn(wmi_ab->ab, "wmi command %d timeout\n", cmd_id); 423 424 return ret; 425 } 426 427 static int ath12k_pull_svc_ready_ext(struct ath12k_wmi_pdev *wmi_handle, 428 const void *ptr, 429 struct ath12k_wmi_service_ext_arg *arg) 430 { 431 const struct wmi_service_ready_ext_event *ev = ptr; 432 int i; 433 434 if (!ev) 435 return -EINVAL; 436 437 /* Move this to host based bitmap */ 438 arg->default_conc_scan_config_bits = 439 le32_to_cpu(ev->default_conc_scan_config_bits); 440 arg->default_fw_config_bits = le32_to_cpu(ev->default_fw_config_bits); 441 arg->he_cap_info = le32_to_cpu(ev->he_cap_info); 442 arg->mpdu_density = le32_to_cpu(ev->mpdu_density); 443 arg->max_bssid_rx_filters = le32_to_cpu(ev->max_bssid_rx_filters); 444 arg->ppet.numss_m1 = le32_to_cpu(ev->ppet.numss_m1); 445 arg->ppet.ru_bit_mask = le32_to_cpu(ev->ppet.ru_info); 446 447 for (i = 0; i < WMI_MAX_NUM_SS; i++) 448 arg->ppet.ppet16_ppet8_ru3_ru0[i] = 449 le32_to_cpu(ev->ppet.ppet16_ppet8_ru3_ru0[i]); 450 451 return 0; 452 } 453 454 static int 455 ath12k_pull_mac_phy_cap_svc_ready_ext(struct ath12k_wmi_pdev *wmi_handle, 456 struct ath12k_wmi_svc_rdy_ext_parse *svc, 457 u8 hw_mode_id, u8 phy_id, 458 struct ath12k_pdev *pdev) 459 { 460 const struct ath12k_wmi_mac_phy_caps_params *mac_caps; 461 const struct ath12k_wmi_soc_mac_phy_hw_mode_caps_params *hw_caps = svc->hw_caps; 462 const struct ath12k_wmi_hw_mode_cap_params *wmi_hw_mode_caps = svc->hw_mode_caps; 463 const struct ath12k_wmi_mac_phy_caps_params *wmi_mac_phy_caps = svc->mac_phy_caps; 464 struct ath12k_base *ab = wmi_handle->wmi_ab->ab; 465 struct ath12k_band_cap *cap_band; 466 struct ath12k_pdev_cap *pdev_cap = &pdev->cap; 467 struct ath12k_fw_pdev *fw_pdev; 468 u32 supported_bands; 469 u32 phy_map; 470 u32 hw_idx, phy_idx = 0; 471 int i; 472 473 if (!hw_caps || !wmi_hw_mode_caps || !svc->soc_hal_reg_caps) 474 return -EINVAL; 475 476 for (hw_idx = 0; hw_idx < le32_to_cpu(hw_caps->num_hw_modes); hw_idx++) { 477 if (hw_mode_id == le32_to_cpu(wmi_hw_mode_caps[hw_idx].hw_mode_id)) 478 break; 479 480 phy_map = le32_to_cpu(wmi_hw_mode_caps[hw_idx].phy_id_map); 481 phy_idx = fls(phy_map); 482 } 483 484 if (hw_idx == le32_to_cpu(hw_caps->num_hw_modes)) 485 return -EINVAL; 486 487 phy_idx += phy_id; 488 if (phy_id >= le32_to_cpu(svc->soc_hal_reg_caps->num_phy)) 489 return -EINVAL; 490 491 mac_caps = wmi_mac_phy_caps + phy_idx; 492 supported_bands = le32_to_cpu(mac_caps->supported_bands); 493 494 if (!(supported_bands & WMI_HOST_WLAN_2GHZ_CAP) && 495 !(supported_bands & WMI_HOST_WLAN_5GHZ_CAP)) 496 return -EINVAL; 497 498 pdev->pdev_id = ath12k_wmi_mac_phy_get_pdev_id(mac_caps); 499 pdev->hw_link_id = ath12k_wmi_mac_phy_get_hw_link_id(mac_caps); 500 pdev_cap->supported_bands |= supported_bands; 501 pdev_cap->ampdu_density = le32_to_cpu(mac_caps->ampdu_density); 502 503 fw_pdev = &ab->fw_pdev[ab->fw_pdev_count]; 504 fw_pdev->supported_bands = supported_bands; 505 fw_pdev->pdev_id = ath12k_wmi_mac_phy_get_pdev_id(mac_caps); 506 fw_pdev->phy_id = le32_to_cpu(mac_caps->phy_id); 507 ab->fw_pdev_count++; 508 509 /* Take non-zero tx/rx chainmask. If tx/rx chainmask differs from 510 * band to band for a single radio, need to see how this should be 511 * handled. 512 */ 513 if (supported_bands & WMI_HOST_WLAN_2GHZ_CAP) { 514 pdev_cap->tx_chain_mask = le32_to_cpu(mac_caps->tx_chain_mask_2g); 515 pdev_cap->rx_chain_mask = le32_to_cpu(mac_caps->rx_chain_mask_2g); 516 } 517 518 if (supported_bands & WMI_HOST_WLAN_5GHZ_CAP) { 519 pdev_cap->vht_cap = le32_to_cpu(mac_caps->vht_cap_info_5g); 520 pdev_cap->vht_mcs = le32_to_cpu(mac_caps->vht_supp_mcs_5g); 521 pdev_cap->he_mcs = le32_to_cpu(mac_caps->he_supp_mcs_5g); 522 pdev_cap->tx_chain_mask = le32_to_cpu(mac_caps->tx_chain_mask_5g); 523 pdev_cap->rx_chain_mask = le32_to_cpu(mac_caps->rx_chain_mask_5g); 524 pdev_cap->nss_ratio_enabled = 525 WMI_NSS_RATIO_EN_DIS_GET(mac_caps->nss_ratio); 526 pdev_cap->nss_ratio_info = 527 WMI_NSS_RATIO_INFO_GET(mac_caps->nss_ratio); 528 } 529 530 /* tx/rx chainmask reported from fw depends on the actual hw chains used, 531 * For example, for 4x4 capable macphys, first 4 chains can be used for first 532 * mac and the remaining 4 chains can be used for the second mac or vice-versa. 533 * In this case, tx/rx chainmask 0xf will be advertised for first mac and 0xf0 534 * will be advertised for second mac or vice-versa. Compute the shift value 535 * for tx/rx chainmask which will be used to advertise supported ht/vht rates to 536 * mac80211. 537 */ 538 pdev_cap->tx_chain_mask_shift = 539 find_first_bit((unsigned long *)&pdev_cap->tx_chain_mask, 32); 540 pdev_cap->rx_chain_mask_shift = 541 find_first_bit((unsigned long *)&pdev_cap->rx_chain_mask, 32); 542 543 if (supported_bands & WMI_HOST_WLAN_2GHZ_CAP) { 544 cap_band = &pdev_cap->band[NL80211_BAND_2GHZ]; 545 cap_band->phy_id = le32_to_cpu(mac_caps->phy_id); 546 cap_band->max_bw_supported = le32_to_cpu(mac_caps->max_bw_supported_2g); 547 cap_band->ht_cap_info = le32_to_cpu(mac_caps->ht_cap_info_2g); 548 cap_band->he_cap_info[0] = le32_to_cpu(mac_caps->he_cap_info_2g); 549 cap_band->he_cap_info[1] = le32_to_cpu(mac_caps->he_cap_info_2g_ext); 550 cap_band->he_mcs = le32_to_cpu(mac_caps->he_supp_mcs_2g); 551 for (i = 0; i < WMI_MAX_HECAP_PHY_SIZE; i++) 552 cap_band->he_cap_phy_info[i] = 553 le32_to_cpu(mac_caps->he_cap_phy_info_2g[i]); 554 555 cap_band->he_ppet.numss_m1 = le32_to_cpu(mac_caps->he_ppet2g.numss_m1); 556 cap_band->he_ppet.ru_bit_mask = le32_to_cpu(mac_caps->he_ppet2g.ru_info); 557 558 for (i = 0; i < WMI_MAX_NUM_SS; i++) 559 cap_band->he_ppet.ppet16_ppet8_ru3_ru0[i] = 560 le32_to_cpu(mac_caps->he_ppet2g.ppet16_ppet8_ru3_ru0[i]); 561 } 562 563 if (supported_bands & WMI_HOST_WLAN_5GHZ_CAP) { 564 cap_band = &pdev_cap->band[NL80211_BAND_5GHZ]; 565 cap_band->phy_id = le32_to_cpu(mac_caps->phy_id); 566 cap_band->max_bw_supported = 567 le32_to_cpu(mac_caps->max_bw_supported_5g); 568 cap_band->ht_cap_info = le32_to_cpu(mac_caps->ht_cap_info_5g); 569 cap_band->he_cap_info[0] = le32_to_cpu(mac_caps->he_cap_info_5g); 570 cap_band->he_cap_info[1] = le32_to_cpu(mac_caps->he_cap_info_5g_ext); 571 cap_band->he_mcs = le32_to_cpu(mac_caps->he_supp_mcs_5g); 572 for (i = 0; i < WMI_MAX_HECAP_PHY_SIZE; i++) 573 cap_band->he_cap_phy_info[i] = 574 le32_to_cpu(mac_caps->he_cap_phy_info_5g[i]); 575 576 cap_band->he_ppet.numss_m1 = le32_to_cpu(mac_caps->he_ppet5g.numss_m1); 577 cap_band->he_ppet.ru_bit_mask = le32_to_cpu(mac_caps->he_ppet5g.ru_info); 578 579 for (i = 0; i < WMI_MAX_NUM_SS; i++) 580 cap_band->he_ppet.ppet16_ppet8_ru3_ru0[i] = 581 le32_to_cpu(mac_caps->he_ppet5g.ppet16_ppet8_ru3_ru0[i]); 582 583 cap_band = &pdev_cap->band[NL80211_BAND_6GHZ]; 584 cap_band->max_bw_supported = 585 le32_to_cpu(mac_caps->max_bw_supported_5g); 586 cap_band->ht_cap_info = le32_to_cpu(mac_caps->ht_cap_info_5g); 587 cap_band->he_cap_info[0] = le32_to_cpu(mac_caps->he_cap_info_5g); 588 cap_band->he_cap_info[1] = le32_to_cpu(mac_caps->he_cap_info_5g_ext); 589 cap_band->he_mcs = le32_to_cpu(mac_caps->he_supp_mcs_5g); 590 for (i = 0; i < WMI_MAX_HECAP_PHY_SIZE; i++) 591 cap_band->he_cap_phy_info[i] = 592 le32_to_cpu(mac_caps->he_cap_phy_info_5g[i]); 593 594 cap_band->he_ppet.numss_m1 = le32_to_cpu(mac_caps->he_ppet5g.numss_m1); 595 cap_band->he_ppet.ru_bit_mask = le32_to_cpu(mac_caps->he_ppet5g.ru_info); 596 597 for (i = 0; i < WMI_MAX_NUM_SS; i++) 598 cap_band->he_ppet.ppet16_ppet8_ru3_ru0[i] = 599 le32_to_cpu(mac_caps->he_ppet5g.ppet16_ppet8_ru3_ru0[i]); 600 } 601 602 return 0; 603 } 604 605 static int 606 ath12k_pull_reg_cap_svc_rdy_ext(struct ath12k_wmi_pdev *wmi_handle, 607 const struct ath12k_wmi_soc_hal_reg_caps_params *reg_caps, 608 const struct ath12k_wmi_hal_reg_caps_ext_params *ext_caps, 609 u8 phy_idx, 610 struct ath12k_wmi_hal_reg_capabilities_ext_arg *param) 611 { 612 const struct ath12k_wmi_hal_reg_caps_ext_params *ext_reg_cap; 613 614 if (!reg_caps || !ext_caps) 615 return -EINVAL; 616 617 if (phy_idx >= le32_to_cpu(reg_caps->num_phy)) 618 return -EINVAL; 619 620 ext_reg_cap = &ext_caps[phy_idx]; 621 622 param->phy_id = le32_to_cpu(ext_reg_cap->phy_id); 623 param->eeprom_reg_domain = le32_to_cpu(ext_reg_cap->eeprom_reg_domain); 624 param->eeprom_reg_domain_ext = 625 le32_to_cpu(ext_reg_cap->eeprom_reg_domain_ext); 626 param->regcap1 = le32_to_cpu(ext_reg_cap->regcap1); 627 param->regcap2 = le32_to_cpu(ext_reg_cap->regcap2); 628 /* check if param->wireless_mode is needed */ 629 param->low_2ghz_chan = le32_to_cpu(ext_reg_cap->low_2ghz_chan); 630 param->high_2ghz_chan = le32_to_cpu(ext_reg_cap->high_2ghz_chan); 631 param->low_5ghz_chan = le32_to_cpu(ext_reg_cap->low_5ghz_chan); 632 param->high_5ghz_chan = le32_to_cpu(ext_reg_cap->high_5ghz_chan); 633 634 return 0; 635 } 636 637 static int ath12k_pull_service_ready_tlv(struct ath12k_base *ab, 638 const void *evt_buf, 639 struct ath12k_wmi_target_cap_arg *cap) 640 { 641 const struct wmi_service_ready_event *ev = evt_buf; 642 643 if (!ev) { 644 ath12k_err(ab, "%s: failed by NULL param\n", 645 __func__); 646 return -EINVAL; 647 } 648 649 cap->phy_capability = le32_to_cpu(ev->phy_capability); 650 cap->max_frag_entry = le32_to_cpu(ev->max_frag_entry); 651 cap->num_rf_chains = le32_to_cpu(ev->num_rf_chains); 652 cap->ht_cap_info = le32_to_cpu(ev->ht_cap_info); 653 cap->vht_cap_info = le32_to_cpu(ev->vht_cap_info); 654 cap->vht_supp_mcs = le32_to_cpu(ev->vht_supp_mcs); 655 cap->hw_min_tx_power = le32_to_cpu(ev->hw_min_tx_power); 656 cap->hw_max_tx_power = le32_to_cpu(ev->hw_max_tx_power); 657 cap->sys_cap_info = le32_to_cpu(ev->sys_cap_info); 658 cap->min_pkt_size_enable = le32_to_cpu(ev->min_pkt_size_enable); 659 cap->max_bcn_ie_size = le32_to_cpu(ev->max_bcn_ie_size); 660 cap->max_num_scan_channels = le32_to_cpu(ev->max_num_scan_channels); 661 cap->max_supported_macs = le32_to_cpu(ev->max_supported_macs); 662 cap->wmi_fw_sub_feat_caps = le32_to_cpu(ev->wmi_fw_sub_feat_caps); 663 cap->txrx_chainmask = le32_to_cpu(ev->txrx_chainmask); 664 cap->default_dbs_hw_mode_index = le32_to_cpu(ev->default_dbs_hw_mode_index); 665 cap->num_msdu_desc = le32_to_cpu(ev->num_msdu_desc); 666 667 return 0; 668 } 669 670 /* Save the wmi_service_bitmap into a linear bitmap. The wmi_services in 671 * wmi_service ready event are advertised in b0-b3 (LSB 4-bits) of each 672 * 4-byte word. 673 */ 674 static void ath12k_wmi_service_bitmap_copy(struct ath12k_wmi_pdev *wmi, 675 const u32 *wmi_svc_bm) 676 { 677 int i, j; 678 679 for (i = 0, j = 0; i < WMI_SERVICE_BM_SIZE && j < WMI_MAX_SERVICE; i++) { 680 do { 681 if (wmi_svc_bm[i] & BIT(j % WMI_SERVICE_BITS_IN_SIZE32)) 682 set_bit(j, wmi->wmi_ab->svc_map); 683 } while (++j % WMI_SERVICE_BITS_IN_SIZE32); 684 } 685 } 686 687 static int ath12k_wmi_svc_rdy_parse(struct ath12k_base *ab, u16 tag, u16 len, 688 const void *ptr, void *data) 689 { 690 struct ath12k_wmi_svc_ready_parse *svc_ready = data; 691 struct ath12k_wmi_pdev *wmi_handle = &ab->wmi_ab.wmi[0]; 692 u16 expect_len; 693 694 switch (tag) { 695 case WMI_TAG_SERVICE_READY_EVENT: 696 if (ath12k_pull_service_ready_tlv(ab, ptr, &ab->target_caps)) 697 return -EINVAL; 698 break; 699 700 case WMI_TAG_ARRAY_UINT32: 701 if (!svc_ready->wmi_svc_bitmap_done) { 702 expect_len = WMI_SERVICE_BM_SIZE * sizeof(u32); 703 if (len < expect_len) { 704 ath12k_warn(ab, "invalid len %d for the tag 0x%x\n", 705 len, tag); 706 return -EINVAL; 707 } 708 709 ath12k_wmi_service_bitmap_copy(wmi_handle, ptr); 710 711 svc_ready->wmi_svc_bitmap_done = true; 712 } 713 break; 714 default: 715 break; 716 } 717 718 return 0; 719 } 720 721 static int ath12k_service_ready_event(struct ath12k_base *ab, struct sk_buff *skb) 722 { 723 struct ath12k_wmi_svc_ready_parse svc_ready = { }; 724 int ret; 725 726 ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, 727 ath12k_wmi_svc_rdy_parse, 728 &svc_ready); 729 if (ret) { 730 ath12k_warn(ab, "failed to parse tlv %d\n", ret); 731 return ret; 732 } 733 734 return 0; 735 } 736 737 static u32 ath12k_wmi_mgmt_get_freq(struct ath12k *ar, 738 struct ieee80211_tx_info *info) 739 { 740 struct ath12k_base *ab = ar->ab; 741 u32 freq = 0; 742 743 if (ab->hw_params->single_pdev_only && 744 ar->scan.is_roc && 745 (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)) 746 freq = ar->scan.roc_freq; 747 748 return freq; 749 } 750 751 struct sk_buff *ath12k_wmi_alloc_skb(struct ath12k_wmi_base *wmi_ab, u32 len) 752 { 753 struct sk_buff *skb; 754 struct ath12k_base *ab = wmi_ab->ab; 755 u32 round_len = roundup(len, 4); 756 757 skb = ath12k_htc_alloc_skb(ab, WMI_SKB_HEADROOM + round_len); 758 if (!skb) 759 return NULL; 760 761 skb_reserve(skb, WMI_SKB_HEADROOM); 762 if (!IS_ALIGNED((unsigned long)skb->data, 4)) 763 ath12k_warn(ab, "unaligned WMI skb data\n"); 764 765 skb_put(skb, round_len); 766 memset(skb->data, 0, round_len); 767 768 return skb; 769 } 770 771 int ath12k_wmi_mgmt_send(struct ath12k_link_vif *arvif, u32 buf_id, 772 struct sk_buff *frame) 773 { 774 struct ath12k *ar = arvif->ar; 775 struct ath12k_wmi_pdev *wmi = ar->wmi; 776 struct wmi_mgmt_send_cmd *cmd; 777 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(frame); 778 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)frame->data; 779 struct ieee80211_vif *vif = ath12k_ahvif_to_vif(arvif->ahvif); 780 int cmd_len = sizeof(struct ath12k_wmi_mgmt_send_tx_params); 781 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr; 782 struct ath12k_wmi_mlo_mgmt_send_params *ml_params; 783 struct ath12k_base *ab = ar->ab; 784 struct wmi_tlv *frame_tlv, *tlv; 785 struct ath12k_skb_cb *skb_cb; 786 u32 buf_len, buf_len_aligned; 787 u32 vdev_id = arvif->vdev_id; 788 bool link_agnostic = false; 789 struct sk_buff *skb; 790 int ret, len; 791 void *ptr; 792 793 buf_len = min_t(int, frame->len, WMI_MGMT_SEND_DOWNLD_LEN); 794 795 buf_len_aligned = roundup(buf_len, sizeof(u32)); 796 797 len = sizeof(*cmd) + sizeof(*frame_tlv) + buf_len_aligned; 798 799 if (ieee80211_vif_is_mld(vif)) { 800 skb_cb = ATH12K_SKB_CB(frame); 801 if ((skb_cb->flags & ATH12K_SKB_MLO_STA) && 802 ab->hw_params->hw_ops->is_frame_link_agnostic && 803 ab->hw_params->hw_ops->is_frame_link_agnostic(arvif, mgmt)) { 804 len += cmd_len + TLV_HDR_SIZE + sizeof(*ml_params); 805 ath12k_generic_dbg(ATH12K_DBG_MGMT, 806 "Sending Mgmt Frame fc 0x%0x as link agnostic", 807 mgmt->frame_control); 808 link_agnostic = true; 809 } 810 } 811 812 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 813 if (!skb) 814 return -ENOMEM; 815 816 cmd = (struct wmi_mgmt_send_cmd *)skb->data; 817 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_MGMT_TX_SEND_CMD, 818 sizeof(*cmd)); 819 cmd->vdev_id = cpu_to_le32(vdev_id); 820 cmd->desc_id = cpu_to_le32(buf_id); 821 cmd->chanfreq = cpu_to_le32(ath12k_wmi_mgmt_get_freq(ar, info)); 822 cmd->paddr_lo = cpu_to_le32(lower_32_bits(ATH12K_SKB_CB(frame)->paddr)); 823 cmd->paddr_hi = cpu_to_le32(upper_32_bits(ATH12K_SKB_CB(frame)->paddr)); 824 cmd->frame_len = cpu_to_le32(frame->len); 825 cmd->buf_len = cpu_to_le32(buf_len); 826 cmd->tx_params_valid = 0; 827 828 frame_tlv = (struct wmi_tlv *)(skb->data + sizeof(*cmd)); 829 frame_tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, buf_len_aligned); 830 831 memcpy(frame_tlv->value, frame->data, buf_len); 832 833 if (!link_agnostic) 834 goto send; 835 836 ptr = skb->data + sizeof(*cmd) + sizeof(*frame_tlv) + buf_len_aligned; 837 838 tlv = ptr; 839 840 /* Tx params not used currently */ 841 tlv->header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_TX_SEND_PARAMS, cmd_len); 842 ptr += cmd_len; 843 844 tlv = ptr; 845 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, sizeof(*ml_params)); 846 ptr += TLV_HDR_SIZE; 847 848 ml_params = ptr; 849 ml_params->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_MLO_TX_SEND_PARAMS, 850 sizeof(*ml_params)); 851 852 ml_params->hw_link_id = cpu_to_le32(WMI_MGMT_LINK_AGNOSTIC_ID); 853 854 send: 855 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_MGMT_TX_SEND_CMDID); 856 if (ret) { 857 ath12k_warn(ar->ab, 858 "failed to submit WMI_MGMT_TX_SEND_CMDID cmd\n"); 859 dev_kfree_skb(skb); 860 } 861 862 return ret; 863 } 864 865 int ath12k_wmi_send_stats_request_cmd(struct ath12k *ar, u32 stats_id, 866 u32 vdev_id, u32 pdev_id) 867 { 868 struct ath12k_wmi_pdev *wmi = ar->wmi; 869 struct wmi_request_stats_cmd *cmd; 870 struct sk_buff *skb; 871 int ret; 872 873 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 874 if (!skb) 875 return -ENOMEM; 876 877 cmd = (struct wmi_request_stats_cmd *)skb->data; 878 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_REQUEST_STATS_CMD, 879 sizeof(*cmd)); 880 881 cmd->stats_id = cpu_to_le32(stats_id); 882 cmd->vdev_id = cpu_to_le32(vdev_id); 883 cmd->pdev_id = cpu_to_le32(pdev_id); 884 885 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_REQUEST_STATS_CMDID); 886 if (ret) { 887 ath12k_warn(ar->ab, "failed to send WMI_REQUEST_STATS cmd\n"); 888 dev_kfree_skb(skb); 889 } 890 891 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 892 "WMI request stats 0x%x vdev id %d pdev id %d\n", 893 stats_id, vdev_id, pdev_id); 894 895 return ret; 896 } 897 898 int ath12k_wmi_vdev_create(struct ath12k *ar, u8 *macaddr, 899 struct ath12k_wmi_vdev_create_arg *args) 900 { 901 struct ath12k_wmi_pdev *wmi = ar->wmi; 902 struct wmi_vdev_create_cmd *cmd; 903 struct sk_buff *skb; 904 struct ath12k_wmi_vdev_txrx_streams_params *txrx_streams; 905 bool is_ml_vdev = is_valid_ether_addr(args->mld_addr); 906 struct wmi_vdev_create_mlo_params *ml_params; 907 struct wmi_tlv *tlv; 908 int ret, len; 909 void *ptr; 910 911 /* It can be optimized my sending tx/rx chain configuration 912 * only for supported bands instead of always sending it for 913 * both the bands. 914 */ 915 len = sizeof(*cmd) + TLV_HDR_SIZE + 916 (WMI_NUM_SUPPORTED_BAND_MAX * sizeof(*txrx_streams)) + 917 (is_ml_vdev ? TLV_HDR_SIZE + sizeof(*ml_params) : 0); 918 919 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 920 if (!skb) 921 return -ENOMEM; 922 923 cmd = (struct wmi_vdev_create_cmd *)skb->data; 924 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_CREATE_CMD, 925 sizeof(*cmd)); 926 927 cmd->vdev_id = cpu_to_le32(args->if_id); 928 cmd->vdev_type = cpu_to_le32(args->type); 929 cmd->vdev_subtype = cpu_to_le32(args->subtype); 930 cmd->num_cfg_txrx_streams = cpu_to_le32(WMI_NUM_SUPPORTED_BAND_MAX); 931 cmd->pdev_id = cpu_to_le32(args->pdev_id); 932 cmd->mbssid_flags = cpu_to_le32(args->mbssid_flags); 933 cmd->mbssid_tx_vdev_id = cpu_to_le32(args->mbssid_tx_vdev_id); 934 cmd->vdev_stats_id = cpu_to_le32(args->if_stats_id); 935 ether_addr_copy(cmd->vdev_macaddr.addr, macaddr); 936 937 if (args->if_stats_id != ATH12K_INVAL_VDEV_STATS_ID) 938 cmd->vdev_stats_id_valid = cpu_to_le32(BIT(0)); 939 940 ptr = skb->data + sizeof(*cmd); 941 len = WMI_NUM_SUPPORTED_BAND_MAX * sizeof(*txrx_streams); 942 943 tlv = ptr; 944 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, len); 945 946 ptr += TLV_HDR_SIZE; 947 txrx_streams = ptr; 948 len = sizeof(*txrx_streams); 949 txrx_streams->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_TXRX_STREAMS, 950 len); 951 txrx_streams->band = cpu_to_le32(WMI_TPC_CHAINMASK_CONFIG_BAND_2G); 952 txrx_streams->supported_tx_streams = 953 cpu_to_le32(args->chains[NL80211_BAND_2GHZ].tx); 954 txrx_streams->supported_rx_streams = 955 cpu_to_le32(args->chains[NL80211_BAND_2GHZ].rx); 956 957 txrx_streams++; 958 txrx_streams->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_TXRX_STREAMS, 959 len); 960 txrx_streams->band = cpu_to_le32(WMI_TPC_CHAINMASK_CONFIG_BAND_5G); 961 txrx_streams->supported_tx_streams = 962 cpu_to_le32(args->chains[NL80211_BAND_5GHZ].tx); 963 txrx_streams->supported_rx_streams = 964 cpu_to_le32(args->chains[NL80211_BAND_5GHZ].rx); 965 966 ptr += WMI_NUM_SUPPORTED_BAND_MAX * sizeof(*txrx_streams); 967 968 if (is_ml_vdev) { 969 tlv = ptr; 970 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, 971 sizeof(*ml_params)); 972 ptr += TLV_HDR_SIZE; 973 ml_params = ptr; 974 975 ml_params->tlv_header = 976 ath12k_wmi_tlv_cmd_hdr(WMI_TAG_MLO_VDEV_CREATE_PARAMS, 977 sizeof(*ml_params)); 978 ether_addr_copy(ml_params->mld_macaddr.addr, args->mld_addr); 979 } 980 981 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 982 "WMI vdev create: id %d type %d subtype %d macaddr %pM pdevid %d\n", 983 args->if_id, args->type, args->subtype, 984 macaddr, args->pdev_id); 985 986 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_VDEV_CREATE_CMDID); 987 if (ret) { 988 ath12k_warn(ar->ab, 989 "failed to submit WMI_VDEV_CREATE_CMDID\n"); 990 dev_kfree_skb(skb); 991 } 992 993 return ret; 994 } 995 996 int ath12k_wmi_vdev_delete(struct ath12k *ar, u8 vdev_id) 997 { 998 struct ath12k_wmi_pdev *wmi = ar->wmi; 999 struct wmi_vdev_delete_cmd *cmd; 1000 struct sk_buff *skb; 1001 int ret; 1002 1003 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 1004 if (!skb) 1005 return -ENOMEM; 1006 1007 cmd = (struct wmi_vdev_delete_cmd *)skb->data; 1008 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_DELETE_CMD, 1009 sizeof(*cmd)); 1010 cmd->vdev_id = cpu_to_le32(vdev_id); 1011 1012 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "WMI vdev delete id %d\n", vdev_id); 1013 1014 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_VDEV_DELETE_CMDID); 1015 if (ret) { 1016 ath12k_warn(ar->ab, "failed to submit WMI_VDEV_DELETE_CMDID\n"); 1017 dev_kfree_skb(skb); 1018 } 1019 1020 return ret; 1021 } 1022 1023 int ath12k_wmi_vdev_stop(struct ath12k *ar, u8 vdev_id) 1024 { 1025 struct ath12k_wmi_pdev *wmi = ar->wmi; 1026 struct wmi_vdev_stop_cmd *cmd; 1027 struct sk_buff *skb; 1028 int ret; 1029 1030 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 1031 if (!skb) 1032 return -ENOMEM; 1033 1034 cmd = (struct wmi_vdev_stop_cmd *)skb->data; 1035 1036 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_STOP_CMD, 1037 sizeof(*cmd)); 1038 cmd->vdev_id = cpu_to_le32(vdev_id); 1039 1040 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "WMI vdev stop id 0x%x\n", vdev_id); 1041 1042 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_VDEV_STOP_CMDID); 1043 if (ret) { 1044 ath12k_warn(ar->ab, "failed to submit WMI_VDEV_STOP cmd\n"); 1045 dev_kfree_skb(skb); 1046 } 1047 1048 return ret; 1049 } 1050 1051 int ath12k_wmi_vdev_down(struct ath12k *ar, u8 vdev_id) 1052 { 1053 struct ath12k_wmi_pdev *wmi = ar->wmi; 1054 struct wmi_vdev_down_cmd *cmd; 1055 struct sk_buff *skb; 1056 int ret; 1057 1058 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 1059 if (!skb) 1060 return -ENOMEM; 1061 1062 cmd = (struct wmi_vdev_down_cmd *)skb->data; 1063 1064 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_DOWN_CMD, 1065 sizeof(*cmd)); 1066 cmd->vdev_id = cpu_to_le32(vdev_id); 1067 1068 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "WMI vdev down id 0x%x\n", vdev_id); 1069 1070 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_VDEV_DOWN_CMDID); 1071 if (ret) { 1072 ath12k_warn(ar->ab, "failed to submit WMI_VDEV_DOWN cmd\n"); 1073 dev_kfree_skb(skb); 1074 } 1075 1076 return ret; 1077 } 1078 1079 static void ath12k_wmi_put_wmi_channel(struct ath12k_wmi_channel_params *chan, 1080 struct wmi_vdev_start_req_arg *arg) 1081 { 1082 u32 center_freq1 = arg->band_center_freq1; 1083 1084 memset(chan, 0, sizeof(*chan)); 1085 1086 chan->mhz = cpu_to_le32(arg->freq); 1087 chan->band_center_freq1 = cpu_to_le32(center_freq1); 1088 if (arg->mode == MODE_11BE_EHT320) { 1089 if (arg->freq > center_freq1) 1090 chan->band_center_freq1 = cpu_to_le32(center_freq1 + 80); 1091 else 1092 chan->band_center_freq1 = cpu_to_le32(center_freq1 - 80); 1093 1094 chan->band_center_freq2 = cpu_to_le32(center_freq1); 1095 1096 } else if (arg->mode == MODE_11BE_EHT160 || 1097 arg->mode == MODE_11AX_HE160) { 1098 if (arg->freq > center_freq1) 1099 chan->band_center_freq1 = cpu_to_le32(center_freq1 + 40); 1100 else 1101 chan->band_center_freq1 = cpu_to_le32(center_freq1 - 40); 1102 1103 chan->band_center_freq2 = cpu_to_le32(center_freq1); 1104 } else { 1105 chan->band_center_freq2 = 0; 1106 } 1107 1108 chan->info |= le32_encode_bits(arg->mode, WMI_CHAN_INFO_MODE); 1109 if (arg->passive) 1110 chan->info |= cpu_to_le32(WMI_CHAN_INFO_PASSIVE); 1111 if (arg->allow_ibss) 1112 chan->info |= cpu_to_le32(WMI_CHAN_INFO_ADHOC_ALLOWED); 1113 if (arg->allow_ht) 1114 chan->info |= cpu_to_le32(WMI_CHAN_INFO_ALLOW_HT); 1115 if (arg->allow_vht) 1116 chan->info |= cpu_to_le32(WMI_CHAN_INFO_ALLOW_VHT); 1117 if (arg->allow_he) 1118 chan->info |= cpu_to_le32(WMI_CHAN_INFO_ALLOW_HE); 1119 if (arg->ht40plus) 1120 chan->info |= cpu_to_le32(WMI_CHAN_INFO_HT40_PLUS); 1121 if (arg->chan_radar) 1122 chan->info |= cpu_to_le32(WMI_CHAN_INFO_DFS); 1123 if (arg->freq2_radar) 1124 chan->info |= cpu_to_le32(WMI_CHAN_INFO_DFS_FREQ2); 1125 1126 chan->reg_info_1 = le32_encode_bits(arg->max_power, 1127 WMI_CHAN_REG_INFO1_MAX_PWR) | 1128 le32_encode_bits(arg->max_reg_power, 1129 WMI_CHAN_REG_INFO1_MAX_REG_PWR); 1130 1131 chan->reg_info_2 = le32_encode_bits(arg->max_antenna_gain, 1132 WMI_CHAN_REG_INFO2_ANT_MAX) | 1133 le32_encode_bits(arg->max_power, WMI_CHAN_REG_INFO2_MAX_TX_PWR); 1134 } 1135 1136 int ath12k_wmi_vdev_start(struct ath12k *ar, struct wmi_vdev_start_req_arg *arg, 1137 bool restart) 1138 { 1139 struct wmi_vdev_start_mlo_params *ml_params; 1140 struct wmi_partner_link_info *partner_info; 1141 struct ath12k_wmi_pdev *wmi = ar->wmi; 1142 struct wmi_vdev_start_request_cmd *cmd; 1143 struct sk_buff *skb; 1144 struct ath12k_wmi_channel_params *chan; 1145 struct wmi_tlv *tlv; 1146 void *ptr; 1147 int ret, len, i, ml_arg_size = 0; 1148 1149 if (WARN_ON(arg->ssid_len > sizeof(cmd->ssid.ssid))) 1150 return -EINVAL; 1151 1152 len = sizeof(*cmd) + sizeof(*chan) + TLV_HDR_SIZE; 1153 1154 if (!restart && arg->ml.enabled) { 1155 ml_arg_size = TLV_HDR_SIZE + sizeof(*ml_params) + 1156 TLV_HDR_SIZE + (arg->ml.num_partner_links * 1157 sizeof(*partner_info)); 1158 len += ml_arg_size; 1159 } 1160 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 1161 if (!skb) 1162 return -ENOMEM; 1163 1164 cmd = (struct wmi_vdev_start_request_cmd *)skb->data; 1165 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_START_REQUEST_CMD, 1166 sizeof(*cmd)); 1167 cmd->vdev_id = cpu_to_le32(arg->vdev_id); 1168 cmd->beacon_interval = cpu_to_le32(arg->bcn_intval); 1169 cmd->bcn_tx_rate = cpu_to_le32(arg->bcn_tx_rate); 1170 cmd->dtim_period = cpu_to_le32(arg->dtim_period); 1171 cmd->num_noa_descriptors = cpu_to_le32(arg->num_noa_descriptors); 1172 cmd->preferred_rx_streams = cpu_to_le32(arg->pref_rx_streams); 1173 cmd->preferred_tx_streams = cpu_to_le32(arg->pref_tx_streams); 1174 cmd->cac_duration_ms = cpu_to_le32(arg->cac_duration_ms); 1175 cmd->regdomain = cpu_to_le32(arg->regdomain); 1176 cmd->he_ops = cpu_to_le32(arg->he_ops); 1177 cmd->punct_bitmap = cpu_to_le32(arg->punct_bitmap); 1178 cmd->mbssid_flags = cpu_to_le32(arg->mbssid_flags); 1179 cmd->mbssid_tx_vdev_id = cpu_to_le32(arg->mbssid_tx_vdev_id); 1180 1181 if (!restart) { 1182 if (arg->ssid) { 1183 cmd->ssid.ssid_len = cpu_to_le32(arg->ssid_len); 1184 memcpy(cmd->ssid.ssid, arg->ssid, arg->ssid_len); 1185 } 1186 if (arg->hidden_ssid) 1187 cmd->flags |= cpu_to_le32(WMI_VDEV_START_HIDDEN_SSID); 1188 if (arg->pmf_enabled) 1189 cmd->flags |= cpu_to_le32(WMI_VDEV_START_PMF_ENABLED); 1190 } 1191 1192 cmd->flags |= cpu_to_le32(WMI_VDEV_START_LDPC_RX_ENABLED); 1193 1194 ptr = skb->data + sizeof(*cmd); 1195 chan = ptr; 1196 1197 ath12k_wmi_put_wmi_channel(chan, arg); 1198 1199 chan->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_CHANNEL, 1200 sizeof(*chan)); 1201 ptr += sizeof(*chan); 1202 1203 tlv = ptr; 1204 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, 0); 1205 1206 /* Note: This is a nested TLV containing: 1207 * [wmi_tlv][ath12k_wmi_p2p_noa_descriptor][wmi_tlv].. 1208 */ 1209 1210 ptr += sizeof(*tlv); 1211 1212 if (ml_arg_size) { 1213 tlv = ptr; 1214 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, 1215 sizeof(*ml_params)); 1216 ptr += TLV_HDR_SIZE; 1217 1218 ml_params = ptr; 1219 1220 ml_params->tlv_header = 1221 ath12k_wmi_tlv_cmd_hdr(WMI_TAG_MLO_VDEV_START_PARAMS, 1222 sizeof(*ml_params)); 1223 1224 ml_params->flags = le32_encode_bits(arg->ml.enabled, 1225 ATH12K_WMI_FLAG_MLO_ENABLED) | 1226 le32_encode_bits(arg->ml.assoc_link, 1227 ATH12K_WMI_FLAG_MLO_ASSOC_LINK) | 1228 le32_encode_bits(arg->ml.mcast_link, 1229 ATH12K_WMI_FLAG_MLO_MCAST_VDEV) | 1230 le32_encode_bits(arg->ml.link_add, 1231 ATH12K_WMI_FLAG_MLO_LINK_ADD); 1232 1233 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "vdev %d start ml flags 0x%x\n", 1234 arg->vdev_id, ml_params->flags); 1235 1236 ptr += sizeof(*ml_params); 1237 1238 tlv = ptr; 1239 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, 1240 arg->ml.num_partner_links * 1241 sizeof(*partner_info)); 1242 ptr += TLV_HDR_SIZE; 1243 1244 partner_info = ptr; 1245 1246 for (i = 0; i < arg->ml.num_partner_links; i++) { 1247 partner_info->tlv_header = 1248 ath12k_wmi_tlv_cmd_hdr(WMI_TAG_MLO_PARTNER_LINK_PARAMS, 1249 sizeof(*partner_info)); 1250 partner_info->vdev_id = 1251 cpu_to_le32(arg->ml.partner_info[i].vdev_id); 1252 partner_info->hw_link_id = 1253 cpu_to_le32(arg->ml.partner_info[i].hw_link_id); 1254 ether_addr_copy(partner_info->vdev_addr.addr, 1255 arg->ml.partner_info[i].addr); 1256 1257 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "partner vdev %d hw_link_id %d macaddr%pM\n", 1258 partner_info->vdev_id, partner_info->hw_link_id, 1259 partner_info->vdev_addr.addr); 1260 1261 partner_info++; 1262 } 1263 1264 ptr = partner_info; 1265 } 1266 1267 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "vdev %s id 0x%x freq 0x%x mode 0x%x\n", 1268 restart ? "restart" : "start", arg->vdev_id, 1269 arg->freq, arg->mode); 1270 1271 if (restart) 1272 ret = ath12k_wmi_cmd_send(wmi, skb, 1273 WMI_VDEV_RESTART_REQUEST_CMDID); 1274 else 1275 ret = ath12k_wmi_cmd_send(wmi, skb, 1276 WMI_VDEV_START_REQUEST_CMDID); 1277 if (ret) { 1278 ath12k_warn(ar->ab, "failed to submit vdev_%s cmd\n", 1279 restart ? "restart" : "start"); 1280 dev_kfree_skb(skb); 1281 } 1282 1283 return ret; 1284 } 1285 1286 int ath12k_wmi_vdev_up(struct ath12k *ar, struct ath12k_wmi_vdev_up_params *params) 1287 { 1288 struct ath12k_wmi_pdev *wmi = ar->wmi; 1289 struct wmi_vdev_up_cmd *cmd; 1290 struct sk_buff *skb; 1291 int ret; 1292 1293 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 1294 if (!skb) 1295 return -ENOMEM; 1296 1297 cmd = (struct wmi_vdev_up_cmd *)skb->data; 1298 1299 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_UP_CMD, 1300 sizeof(*cmd)); 1301 cmd->vdev_id = cpu_to_le32(params->vdev_id); 1302 cmd->vdev_assoc_id = cpu_to_le32(params->aid); 1303 1304 ether_addr_copy(cmd->vdev_bssid.addr, params->bssid); 1305 1306 if (params->tx_bssid) { 1307 ether_addr_copy(cmd->tx_vdev_bssid.addr, params->tx_bssid); 1308 cmd->nontx_profile_idx = cpu_to_le32(params->nontx_profile_idx); 1309 cmd->nontx_profile_cnt = cpu_to_le32(params->nontx_profile_cnt); 1310 } 1311 1312 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 1313 "WMI mgmt vdev up id 0x%x assoc id %d bssid %pM\n", 1314 params->vdev_id, params->aid, params->bssid); 1315 1316 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_VDEV_UP_CMDID); 1317 if (ret) { 1318 ath12k_warn(ar->ab, "failed to submit WMI_VDEV_UP cmd\n"); 1319 dev_kfree_skb(skb); 1320 } 1321 1322 return ret; 1323 } 1324 1325 int ath12k_wmi_send_peer_create_cmd(struct ath12k *ar, 1326 struct ath12k_wmi_peer_create_arg *arg) 1327 { 1328 struct ath12k_wmi_pdev *wmi = ar->wmi; 1329 struct wmi_peer_create_cmd *cmd; 1330 struct sk_buff *skb; 1331 int ret, len; 1332 struct wmi_peer_create_mlo_params *ml_param; 1333 void *ptr; 1334 struct wmi_tlv *tlv; 1335 1336 len = sizeof(*cmd) + TLV_HDR_SIZE + sizeof(*ml_param); 1337 1338 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 1339 if (!skb) 1340 return -ENOMEM; 1341 1342 cmd = (struct wmi_peer_create_cmd *)skb->data; 1343 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PEER_CREATE_CMD, 1344 sizeof(*cmd)); 1345 1346 ether_addr_copy(cmd->peer_macaddr.addr, arg->peer_addr); 1347 cmd->peer_type = cpu_to_le32(arg->peer_type); 1348 cmd->vdev_id = cpu_to_le32(arg->vdev_id); 1349 1350 ptr = skb->data + sizeof(*cmd); 1351 tlv = ptr; 1352 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, 1353 sizeof(*ml_param)); 1354 ptr += TLV_HDR_SIZE; 1355 ml_param = ptr; 1356 ml_param->tlv_header = 1357 ath12k_wmi_tlv_cmd_hdr(WMI_TAG_MLO_PEER_CREATE_PARAMS, 1358 sizeof(*ml_param)); 1359 if (arg->ml_enabled) 1360 ml_param->flags = cpu_to_le32(ATH12K_WMI_FLAG_MLO_ENABLED); 1361 1362 ptr += sizeof(*ml_param); 1363 1364 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 1365 "WMI peer create vdev_id %d peer_addr %pM ml_flags 0x%x\n", 1366 arg->vdev_id, arg->peer_addr, ml_param->flags); 1367 1368 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PEER_CREATE_CMDID); 1369 if (ret) { 1370 ath12k_warn(ar->ab, "failed to submit WMI_PEER_CREATE cmd\n"); 1371 dev_kfree_skb(skb); 1372 } 1373 1374 return ret; 1375 } 1376 1377 int ath12k_wmi_send_peer_delete_cmd(struct ath12k *ar, 1378 const u8 *peer_addr, u8 vdev_id) 1379 { 1380 struct ath12k_wmi_pdev *wmi = ar->wmi; 1381 struct wmi_peer_delete_cmd *cmd; 1382 struct sk_buff *skb; 1383 int ret; 1384 1385 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 1386 if (!skb) 1387 return -ENOMEM; 1388 1389 cmd = (struct wmi_peer_delete_cmd *)skb->data; 1390 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PEER_DELETE_CMD, 1391 sizeof(*cmd)); 1392 1393 ether_addr_copy(cmd->peer_macaddr.addr, peer_addr); 1394 cmd->vdev_id = cpu_to_le32(vdev_id); 1395 1396 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 1397 "WMI peer delete vdev_id %d peer_addr %pM\n", 1398 vdev_id, peer_addr); 1399 1400 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PEER_DELETE_CMDID); 1401 if (ret) { 1402 ath12k_warn(ar->ab, "failed to send WMI_PEER_DELETE cmd\n"); 1403 dev_kfree_skb(skb); 1404 } 1405 1406 return ret; 1407 } 1408 1409 int ath12k_wmi_send_pdev_set_regdomain(struct ath12k *ar, 1410 struct ath12k_wmi_pdev_set_regdomain_arg *arg) 1411 { 1412 struct ath12k_wmi_pdev *wmi = ar->wmi; 1413 struct wmi_pdev_set_regdomain_cmd *cmd; 1414 struct sk_buff *skb; 1415 int ret; 1416 1417 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 1418 if (!skb) 1419 return -ENOMEM; 1420 1421 cmd = (struct wmi_pdev_set_regdomain_cmd *)skb->data; 1422 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_SET_REGDOMAIN_CMD, 1423 sizeof(*cmd)); 1424 1425 cmd->reg_domain = cpu_to_le32(arg->current_rd_in_use); 1426 cmd->reg_domain_2g = cpu_to_le32(arg->current_rd_2g); 1427 cmd->reg_domain_5g = cpu_to_le32(arg->current_rd_5g); 1428 cmd->conformance_test_limit_2g = cpu_to_le32(arg->ctl_2g); 1429 cmd->conformance_test_limit_5g = cpu_to_le32(arg->ctl_5g); 1430 cmd->dfs_domain = cpu_to_le32(arg->dfs_domain); 1431 cmd->pdev_id = cpu_to_le32(arg->pdev_id); 1432 1433 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 1434 "WMI pdev regd rd %d rd2g %d rd5g %d domain %d pdev id %d\n", 1435 arg->current_rd_in_use, arg->current_rd_2g, 1436 arg->current_rd_5g, arg->dfs_domain, arg->pdev_id); 1437 1438 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PDEV_SET_REGDOMAIN_CMDID); 1439 if (ret) { 1440 ath12k_warn(ar->ab, 1441 "failed to send WMI_PDEV_SET_REGDOMAIN cmd\n"); 1442 dev_kfree_skb(skb); 1443 } 1444 1445 return ret; 1446 } 1447 1448 int ath12k_wmi_set_peer_param(struct ath12k *ar, const u8 *peer_addr, 1449 u32 vdev_id, u32 param_id, u32 param_val) 1450 { 1451 struct ath12k_wmi_pdev *wmi = ar->wmi; 1452 struct wmi_peer_set_param_cmd *cmd; 1453 struct sk_buff *skb; 1454 int ret; 1455 1456 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 1457 if (!skb) 1458 return -ENOMEM; 1459 1460 cmd = (struct wmi_peer_set_param_cmd *)skb->data; 1461 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PEER_SET_PARAM_CMD, 1462 sizeof(*cmd)); 1463 ether_addr_copy(cmd->peer_macaddr.addr, peer_addr); 1464 cmd->vdev_id = cpu_to_le32(vdev_id); 1465 cmd->param_id = cpu_to_le32(param_id); 1466 cmd->param_value = cpu_to_le32(param_val); 1467 1468 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 1469 "WMI vdev %d peer 0x%pM set param %d value %d\n", 1470 vdev_id, peer_addr, param_id, param_val); 1471 1472 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PEER_SET_PARAM_CMDID); 1473 if (ret) { 1474 ath12k_warn(ar->ab, "failed to send WMI_PEER_SET_PARAM cmd\n"); 1475 dev_kfree_skb(skb); 1476 } 1477 1478 return ret; 1479 } 1480 1481 int ath12k_wmi_send_peer_flush_tids_cmd(struct ath12k *ar, 1482 u8 peer_addr[ETH_ALEN], 1483 u32 peer_tid_bitmap, 1484 u8 vdev_id) 1485 { 1486 struct ath12k_wmi_pdev *wmi = ar->wmi; 1487 struct wmi_peer_flush_tids_cmd *cmd; 1488 struct sk_buff *skb; 1489 int ret; 1490 1491 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 1492 if (!skb) 1493 return -ENOMEM; 1494 1495 cmd = (struct wmi_peer_flush_tids_cmd *)skb->data; 1496 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PEER_FLUSH_TIDS_CMD, 1497 sizeof(*cmd)); 1498 1499 ether_addr_copy(cmd->peer_macaddr.addr, peer_addr); 1500 cmd->peer_tid_bitmap = cpu_to_le32(peer_tid_bitmap); 1501 cmd->vdev_id = cpu_to_le32(vdev_id); 1502 1503 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 1504 "WMI peer flush vdev_id %d peer_addr %pM tids %08x\n", 1505 vdev_id, peer_addr, peer_tid_bitmap); 1506 1507 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PEER_FLUSH_TIDS_CMDID); 1508 if (ret) { 1509 ath12k_warn(ar->ab, 1510 "failed to send WMI_PEER_FLUSH_TIDS cmd\n"); 1511 dev_kfree_skb(skb); 1512 } 1513 1514 return ret; 1515 } 1516 1517 int ath12k_wmi_peer_rx_reorder_queue_setup(struct ath12k *ar, 1518 int vdev_id, const u8 *addr, 1519 dma_addr_t paddr, u8 tid, 1520 u8 ba_window_size_valid, 1521 u32 ba_window_size) 1522 { 1523 struct wmi_peer_reorder_queue_setup_cmd *cmd; 1524 struct sk_buff *skb; 1525 int ret; 1526 1527 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, sizeof(*cmd)); 1528 if (!skb) 1529 return -ENOMEM; 1530 1531 cmd = (struct wmi_peer_reorder_queue_setup_cmd *)skb->data; 1532 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_REORDER_QUEUE_SETUP_CMD, 1533 sizeof(*cmd)); 1534 1535 ether_addr_copy(cmd->peer_macaddr.addr, addr); 1536 cmd->vdev_id = cpu_to_le32(vdev_id); 1537 cmd->tid = cpu_to_le32(tid); 1538 cmd->queue_ptr_lo = cpu_to_le32(lower_32_bits(paddr)); 1539 cmd->queue_ptr_hi = cpu_to_le32(upper_32_bits(paddr)); 1540 cmd->queue_no = cpu_to_le32(tid); 1541 cmd->ba_window_size_valid = cpu_to_le32(ba_window_size_valid); 1542 cmd->ba_window_size = cpu_to_le32(ba_window_size); 1543 1544 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 1545 "wmi rx reorder queue setup addr %pM vdev_id %d tid %d\n", 1546 addr, vdev_id, tid); 1547 1548 ret = ath12k_wmi_cmd_send(ar->wmi, skb, 1549 WMI_PEER_REORDER_QUEUE_SETUP_CMDID); 1550 if (ret) { 1551 ath12k_warn(ar->ab, 1552 "failed to send WMI_PEER_REORDER_QUEUE_SETUP\n"); 1553 dev_kfree_skb(skb); 1554 } 1555 1556 return ret; 1557 } 1558 1559 int 1560 ath12k_wmi_rx_reord_queue_remove(struct ath12k *ar, 1561 struct ath12k_wmi_rx_reorder_queue_remove_arg *arg) 1562 { 1563 struct ath12k_wmi_pdev *wmi = ar->wmi; 1564 struct wmi_peer_reorder_queue_remove_cmd *cmd; 1565 struct sk_buff *skb; 1566 int ret; 1567 1568 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 1569 if (!skb) 1570 return -ENOMEM; 1571 1572 cmd = (struct wmi_peer_reorder_queue_remove_cmd *)skb->data; 1573 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_REORDER_QUEUE_REMOVE_CMD, 1574 sizeof(*cmd)); 1575 1576 ether_addr_copy(cmd->peer_macaddr.addr, arg->peer_macaddr); 1577 cmd->vdev_id = cpu_to_le32(arg->vdev_id); 1578 cmd->tid_mask = cpu_to_le32(arg->peer_tid_bitmap); 1579 1580 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 1581 "%s: peer_macaddr %pM vdev_id %d, tid_map %d", __func__, 1582 arg->peer_macaddr, arg->vdev_id, arg->peer_tid_bitmap); 1583 1584 ret = ath12k_wmi_cmd_send(wmi, skb, 1585 WMI_PEER_REORDER_QUEUE_REMOVE_CMDID); 1586 if (ret) { 1587 ath12k_warn(ar->ab, 1588 "failed to send WMI_PEER_REORDER_QUEUE_REMOVE_CMDID"); 1589 dev_kfree_skb(skb); 1590 } 1591 1592 return ret; 1593 } 1594 1595 int ath12k_wmi_pdev_set_param(struct ath12k *ar, u32 param_id, 1596 u32 param_value, u8 pdev_id) 1597 { 1598 struct ath12k_wmi_pdev *wmi = ar->wmi; 1599 struct wmi_pdev_set_param_cmd *cmd; 1600 struct sk_buff *skb; 1601 int ret; 1602 1603 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 1604 if (!skb) 1605 return -ENOMEM; 1606 1607 cmd = (struct wmi_pdev_set_param_cmd *)skb->data; 1608 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_SET_PARAM_CMD, 1609 sizeof(*cmd)); 1610 cmd->pdev_id = cpu_to_le32(pdev_id); 1611 cmd->param_id = cpu_to_le32(param_id); 1612 cmd->param_value = cpu_to_le32(param_value); 1613 1614 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 1615 "WMI pdev set param %d pdev id %d value %d\n", 1616 param_id, pdev_id, param_value); 1617 1618 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PDEV_SET_PARAM_CMDID); 1619 if (ret) { 1620 ath12k_warn(ar->ab, "failed to send WMI_PDEV_SET_PARAM cmd\n"); 1621 dev_kfree_skb(skb); 1622 } 1623 1624 return ret; 1625 } 1626 1627 int ath12k_wmi_pdev_set_ps_mode(struct ath12k *ar, int vdev_id, u32 enable) 1628 { 1629 struct ath12k_wmi_pdev *wmi = ar->wmi; 1630 struct wmi_pdev_set_ps_mode_cmd *cmd; 1631 struct sk_buff *skb; 1632 int ret; 1633 1634 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 1635 if (!skb) 1636 return -ENOMEM; 1637 1638 cmd = (struct wmi_pdev_set_ps_mode_cmd *)skb->data; 1639 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_STA_POWERSAVE_MODE_CMD, 1640 sizeof(*cmd)); 1641 cmd->vdev_id = cpu_to_le32(vdev_id); 1642 cmd->sta_ps_mode = cpu_to_le32(enable); 1643 1644 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 1645 "WMI vdev set psmode %d vdev id %d\n", 1646 enable, vdev_id); 1647 1648 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_STA_POWERSAVE_MODE_CMDID); 1649 if (ret) { 1650 ath12k_warn(ar->ab, "failed to send WMI_PDEV_SET_PARAM cmd\n"); 1651 dev_kfree_skb(skb); 1652 } 1653 1654 return ret; 1655 } 1656 1657 int ath12k_wmi_pdev_suspend(struct ath12k *ar, u32 suspend_opt, 1658 u32 pdev_id) 1659 { 1660 struct ath12k_wmi_pdev *wmi = ar->wmi; 1661 struct wmi_pdev_suspend_cmd *cmd; 1662 struct sk_buff *skb; 1663 int ret; 1664 1665 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 1666 if (!skb) 1667 return -ENOMEM; 1668 1669 cmd = (struct wmi_pdev_suspend_cmd *)skb->data; 1670 1671 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_SUSPEND_CMD, 1672 sizeof(*cmd)); 1673 1674 cmd->suspend_opt = cpu_to_le32(suspend_opt); 1675 cmd->pdev_id = cpu_to_le32(pdev_id); 1676 1677 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 1678 "WMI pdev suspend pdev_id %d\n", pdev_id); 1679 1680 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PDEV_SUSPEND_CMDID); 1681 if (ret) { 1682 ath12k_warn(ar->ab, "failed to send WMI_PDEV_SUSPEND cmd\n"); 1683 dev_kfree_skb(skb); 1684 } 1685 1686 return ret; 1687 } 1688 1689 int ath12k_wmi_pdev_resume(struct ath12k *ar, u32 pdev_id) 1690 { 1691 struct ath12k_wmi_pdev *wmi = ar->wmi; 1692 struct wmi_pdev_resume_cmd *cmd; 1693 struct sk_buff *skb; 1694 int ret; 1695 1696 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 1697 if (!skb) 1698 return -ENOMEM; 1699 1700 cmd = (struct wmi_pdev_resume_cmd *)skb->data; 1701 1702 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_RESUME_CMD, 1703 sizeof(*cmd)); 1704 cmd->pdev_id = cpu_to_le32(pdev_id); 1705 1706 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 1707 "WMI pdev resume pdev id %d\n", pdev_id); 1708 1709 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PDEV_RESUME_CMDID); 1710 if (ret) { 1711 ath12k_warn(ar->ab, "failed to send WMI_PDEV_RESUME cmd\n"); 1712 dev_kfree_skb(skb); 1713 } 1714 1715 return ret; 1716 } 1717 1718 /* TODO FW Support for the cmd is not available yet. 1719 * Can be tested once the command and corresponding 1720 * event is implemented in FW 1721 */ 1722 int ath12k_wmi_pdev_bss_chan_info_request(struct ath12k *ar, 1723 enum wmi_bss_chan_info_req_type type) 1724 { 1725 struct ath12k_wmi_pdev *wmi = ar->wmi; 1726 struct wmi_pdev_bss_chan_info_req_cmd *cmd; 1727 struct sk_buff *skb; 1728 int ret; 1729 1730 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 1731 if (!skb) 1732 return -ENOMEM; 1733 1734 cmd = (struct wmi_pdev_bss_chan_info_req_cmd *)skb->data; 1735 1736 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_BSS_CHAN_INFO_REQUEST, 1737 sizeof(*cmd)); 1738 cmd->req_type = cpu_to_le32(type); 1739 cmd->pdev_id = cpu_to_le32(ar->pdev->pdev_id); 1740 1741 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 1742 "WMI bss chan info req type %d\n", type); 1743 1744 ret = ath12k_wmi_cmd_send(wmi, skb, 1745 WMI_PDEV_BSS_CHAN_INFO_REQUEST_CMDID); 1746 if (ret) { 1747 ath12k_warn(ar->ab, 1748 "failed to send WMI_PDEV_BSS_CHAN_INFO_REQUEST cmd\n"); 1749 dev_kfree_skb(skb); 1750 } 1751 1752 return ret; 1753 } 1754 1755 int ath12k_wmi_send_set_ap_ps_param_cmd(struct ath12k *ar, u8 *peer_addr, 1756 struct ath12k_wmi_ap_ps_arg *arg) 1757 { 1758 struct ath12k_wmi_pdev *wmi = ar->wmi; 1759 struct wmi_ap_ps_peer_cmd *cmd; 1760 struct sk_buff *skb; 1761 int ret; 1762 1763 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 1764 if (!skb) 1765 return -ENOMEM; 1766 1767 cmd = (struct wmi_ap_ps_peer_cmd *)skb->data; 1768 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_AP_PS_PEER_CMD, 1769 sizeof(*cmd)); 1770 1771 cmd->vdev_id = cpu_to_le32(arg->vdev_id); 1772 ether_addr_copy(cmd->peer_macaddr.addr, peer_addr); 1773 cmd->param = cpu_to_le32(arg->param); 1774 cmd->value = cpu_to_le32(arg->value); 1775 1776 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 1777 "WMI set ap ps vdev id %d peer %pM param %d value %d\n", 1778 arg->vdev_id, peer_addr, arg->param, arg->value); 1779 1780 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_AP_PS_PEER_PARAM_CMDID); 1781 if (ret) { 1782 ath12k_warn(ar->ab, 1783 "failed to send WMI_AP_PS_PEER_PARAM_CMDID\n"); 1784 dev_kfree_skb(skb); 1785 } 1786 1787 return ret; 1788 } 1789 1790 int ath12k_wmi_set_sta_ps_param(struct ath12k *ar, u32 vdev_id, 1791 u32 param, u32 param_value) 1792 { 1793 struct ath12k_wmi_pdev *wmi = ar->wmi; 1794 struct wmi_sta_powersave_param_cmd *cmd; 1795 struct sk_buff *skb; 1796 int ret; 1797 1798 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 1799 if (!skb) 1800 return -ENOMEM; 1801 1802 cmd = (struct wmi_sta_powersave_param_cmd *)skb->data; 1803 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_STA_POWERSAVE_PARAM_CMD, 1804 sizeof(*cmd)); 1805 1806 cmd->vdev_id = cpu_to_le32(vdev_id); 1807 cmd->param = cpu_to_le32(param); 1808 cmd->value = cpu_to_le32(param_value); 1809 1810 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 1811 "WMI set sta ps vdev_id %d param %d value %d\n", 1812 vdev_id, param, param_value); 1813 1814 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_STA_POWERSAVE_PARAM_CMDID); 1815 if (ret) { 1816 ath12k_warn(ar->ab, "failed to send WMI_STA_POWERSAVE_PARAM_CMDID"); 1817 dev_kfree_skb(skb); 1818 } 1819 1820 return ret; 1821 } 1822 1823 int ath12k_wmi_force_fw_hang_cmd(struct ath12k *ar, u32 type, u32 delay_time_ms) 1824 { 1825 struct ath12k_wmi_pdev *wmi = ar->wmi; 1826 struct wmi_force_fw_hang_cmd *cmd; 1827 struct sk_buff *skb; 1828 int ret, len; 1829 1830 len = sizeof(*cmd); 1831 1832 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 1833 if (!skb) 1834 return -ENOMEM; 1835 1836 cmd = (struct wmi_force_fw_hang_cmd *)skb->data; 1837 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_FORCE_FW_HANG_CMD, 1838 len); 1839 1840 cmd->type = cpu_to_le32(type); 1841 cmd->delay_time_ms = cpu_to_le32(delay_time_ms); 1842 1843 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_FORCE_FW_HANG_CMDID); 1844 1845 if (ret) { 1846 ath12k_warn(ar->ab, "Failed to send WMI_FORCE_FW_HANG_CMDID"); 1847 dev_kfree_skb(skb); 1848 } 1849 return ret; 1850 } 1851 1852 int ath12k_wmi_vdev_set_param_cmd(struct ath12k *ar, u32 vdev_id, 1853 u32 param_id, u32 param_value) 1854 { 1855 struct ath12k_wmi_pdev *wmi = ar->wmi; 1856 struct wmi_vdev_set_param_cmd *cmd; 1857 struct sk_buff *skb; 1858 int ret; 1859 1860 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 1861 if (!skb) 1862 return -ENOMEM; 1863 1864 cmd = (struct wmi_vdev_set_param_cmd *)skb->data; 1865 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_SET_PARAM_CMD, 1866 sizeof(*cmd)); 1867 1868 cmd->vdev_id = cpu_to_le32(vdev_id); 1869 cmd->param_id = cpu_to_le32(param_id); 1870 cmd->param_value = cpu_to_le32(param_value); 1871 1872 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 1873 "WMI vdev id 0x%x set param %d value %d\n", 1874 vdev_id, param_id, param_value); 1875 1876 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_VDEV_SET_PARAM_CMDID); 1877 if (ret) { 1878 ath12k_warn(ar->ab, 1879 "failed to send WMI_VDEV_SET_PARAM_CMDID\n"); 1880 dev_kfree_skb(skb); 1881 } 1882 1883 return ret; 1884 } 1885 1886 int ath12k_wmi_send_pdev_temperature_cmd(struct ath12k *ar) 1887 { 1888 struct ath12k_wmi_pdev *wmi = ar->wmi; 1889 struct wmi_get_pdev_temperature_cmd *cmd; 1890 struct sk_buff *skb; 1891 int ret; 1892 1893 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 1894 if (!skb) 1895 return -ENOMEM; 1896 1897 cmd = (struct wmi_get_pdev_temperature_cmd *)skb->data; 1898 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_GET_TEMPERATURE_CMD, 1899 sizeof(*cmd)); 1900 cmd->pdev_id = cpu_to_le32(ar->pdev->pdev_id); 1901 1902 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 1903 "WMI pdev get temperature for pdev_id %d\n", ar->pdev->pdev_id); 1904 1905 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PDEV_GET_TEMPERATURE_CMDID); 1906 if (ret) { 1907 ath12k_warn(ar->ab, "failed to send WMI_PDEV_GET_TEMPERATURE cmd\n"); 1908 dev_kfree_skb(skb); 1909 } 1910 1911 return ret; 1912 } 1913 1914 int ath12k_wmi_send_bcn_offload_control_cmd(struct ath12k *ar, 1915 u32 vdev_id, u32 bcn_ctrl_op) 1916 { 1917 struct ath12k_wmi_pdev *wmi = ar->wmi; 1918 struct wmi_bcn_offload_ctrl_cmd *cmd; 1919 struct sk_buff *skb; 1920 int ret; 1921 1922 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 1923 if (!skb) 1924 return -ENOMEM; 1925 1926 cmd = (struct wmi_bcn_offload_ctrl_cmd *)skb->data; 1927 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_BCN_OFFLOAD_CTRL_CMD, 1928 sizeof(*cmd)); 1929 1930 cmd->vdev_id = cpu_to_le32(vdev_id); 1931 cmd->bcn_ctrl_op = cpu_to_le32(bcn_ctrl_op); 1932 1933 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 1934 "WMI bcn ctrl offload vdev id %d ctrl_op %d\n", 1935 vdev_id, bcn_ctrl_op); 1936 1937 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_BCN_OFFLOAD_CTRL_CMDID); 1938 if (ret) { 1939 ath12k_warn(ar->ab, 1940 "failed to send WMI_BCN_OFFLOAD_CTRL_CMDID\n"); 1941 dev_kfree_skb(skb); 1942 } 1943 1944 return ret; 1945 } 1946 1947 int ath12k_wmi_p2p_go_bcn_ie(struct ath12k *ar, u32 vdev_id, 1948 const u8 *p2p_ie) 1949 { 1950 struct ath12k_wmi_pdev *wmi = ar->wmi; 1951 struct wmi_p2p_go_set_beacon_ie_cmd *cmd; 1952 size_t p2p_ie_len, aligned_len; 1953 struct wmi_tlv *tlv; 1954 struct sk_buff *skb; 1955 void *ptr; 1956 int ret, len; 1957 1958 p2p_ie_len = p2p_ie[1] + 2; 1959 aligned_len = roundup(p2p_ie_len, sizeof(u32)); 1960 1961 len = sizeof(*cmd) + TLV_HDR_SIZE + aligned_len; 1962 1963 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 1964 if (!skb) 1965 return -ENOMEM; 1966 1967 ptr = skb->data; 1968 cmd = ptr; 1969 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_P2P_GO_SET_BEACON_IE, 1970 sizeof(*cmd)); 1971 cmd->vdev_id = cpu_to_le32(vdev_id); 1972 cmd->ie_buf_len = cpu_to_le32(p2p_ie_len); 1973 1974 ptr += sizeof(*cmd); 1975 tlv = ptr; 1976 tlv->header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_ARRAY_BYTE, 1977 aligned_len); 1978 memcpy(tlv->value, p2p_ie, p2p_ie_len); 1979 1980 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_P2P_GO_SET_BEACON_IE); 1981 if (ret) { 1982 ath12k_warn(ar->ab, "failed to send WMI_P2P_GO_SET_BEACON_IE\n"); 1983 dev_kfree_skb(skb); 1984 } 1985 1986 return ret; 1987 } 1988 1989 int ath12k_wmi_bcn_tmpl(struct ath12k_link_vif *arvif, 1990 struct ieee80211_mutable_offsets *offs, 1991 struct sk_buff *bcn, 1992 struct ath12k_wmi_bcn_tmpl_ema_arg *ema_args) 1993 { 1994 struct ath12k *ar = arvif->ar; 1995 struct ath12k_wmi_pdev *wmi = ar->wmi; 1996 struct ath12k_base *ab = ar->ab; 1997 struct wmi_bcn_tmpl_cmd *cmd; 1998 struct ath12k_wmi_bcn_prb_info_params *bcn_prb_info; 1999 struct ath12k_vif *ahvif = arvif->ahvif; 2000 struct ieee80211_bss_conf *conf; 2001 u32 vdev_id = arvif->vdev_id; 2002 struct wmi_tlv *tlv; 2003 struct sk_buff *skb; 2004 u32 ema_params = 0; 2005 void *ptr; 2006 int ret, len; 2007 size_t aligned_len = roundup(bcn->len, 4); 2008 2009 conf = ath12k_mac_get_link_bss_conf(arvif); 2010 if (!conf) { 2011 ath12k_warn(ab, 2012 "unable to access bss link conf in beacon template command for vif %pM link %u\n", 2013 ahvif->vif->addr, arvif->link_id); 2014 return -EINVAL; 2015 } 2016 2017 len = sizeof(*cmd) + sizeof(*bcn_prb_info) + TLV_HDR_SIZE + aligned_len; 2018 2019 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 2020 if (!skb) 2021 return -ENOMEM; 2022 2023 cmd = (struct wmi_bcn_tmpl_cmd *)skb->data; 2024 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_BCN_TMPL_CMD, 2025 sizeof(*cmd)); 2026 cmd->vdev_id = cpu_to_le32(vdev_id); 2027 cmd->tim_ie_offset = cpu_to_le32(offs->tim_offset); 2028 2029 if (conf->csa_active) { 2030 cmd->csa_switch_count_offset = 2031 cpu_to_le32(offs->cntdwn_counter_offs[0]); 2032 cmd->ext_csa_switch_count_offset = 2033 cpu_to_le32(offs->cntdwn_counter_offs[1]); 2034 cmd->csa_event_bitmap = cpu_to_le32(0xFFFFFFFF); 2035 arvif->current_cntdown_counter = bcn->data[offs->cntdwn_counter_offs[0]]; 2036 } 2037 2038 cmd->buf_len = cpu_to_le32(bcn->len); 2039 cmd->mbssid_ie_offset = cpu_to_le32(offs->mbssid_off); 2040 if (ema_args) { 2041 u32p_replace_bits(&ema_params, ema_args->bcn_cnt, WMI_EMA_BEACON_CNT); 2042 u32p_replace_bits(&ema_params, ema_args->bcn_index, WMI_EMA_BEACON_IDX); 2043 if (ema_args->bcn_index == 0) 2044 u32p_replace_bits(&ema_params, 1, WMI_EMA_BEACON_FIRST); 2045 if (ema_args->bcn_index + 1 == ema_args->bcn_cnt) 2046 u32p_replace_bits(&ema_params, 1, WMI_EMA_BEACON_LAST); 2047 cmd->ema_params = cpu_to_le32(ema_params); 2048 } 2049 cmd->feature_enable_bitmap = 2050 cpu_to_le32(u32_encode_bits(arvif->beacon_prot, 2051 WMI_BEACON_PROTECTION_EN_BIT)); 2052 2053 ptr = skb->data + sizeof(*cmd); 2054 2055 bcn_prb_info = ptr; 2056 len = sizeof(*bcn_prb_info); 2057 bcn_prb_info->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_BCN_PRB_INFO, 2058 len); 2059 bcn_prb_info->caps = 0; 2060 bcn_prb_info->erp = 0; 2061 2062 ptr += sizeof(*bcn_prb_info); 2063 2064 tlv = ptr; 2065 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, aligned_len); 2066 memcpy(tlv->value, bcn->data, bcn->len); 2067 2068 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_BCN_TMPL_CMDID); 2069 if (ret) { 2070 ath12k_warn(ab, "failed to send WMI_BCN_TMPL_CMDID\n"); 2071 dev_kfree_skb(skb); 2072 } 2073 2074 return ret; 2075 } 2076 2077 int ath12k_wmi_vdev_install_key(struct ath12k *ar, 2078 struct wmi_vdev_install_key_arg *arg) 2079 { 2080 struct ath12k_wmi_pdev *wmi = ar->wmi; 2081 struct wmi_vdev_install_key_cmd *cmd; 2082 struct wmi_tlv *tlv; 2083 struct sk_buff *skb; 2084 int ret, len, key_len_aligned; 2085 2086 /* WMI_TAG_ARRAY_BYTE needs to be aligned with 4, the actual key 2087 * length is specified in cmd->key_len. 2088 */ 2089 key_len_aligned = roundup(arg->key_len, 4); 2090 2091 len = sizeof(*cmd) + TLV_HDR_SIZE + key_len_aligned; 2092 2093 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 2094 if (!skb) 2095 return -ENOMEM; 2096 2097 cmd = (struct wmi_vdev_install_key_cmd *)skb->data; 2098 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_INSTALL_KEY_CMD, 2099 sizeof(*cmd)); 2100 cmd->vdev_id = cpu_to_le32(arg->vdev_id); 2101 ether_addr_copy(cmd->peer_macaddr.addr, arg->macaddr); 2102 cmd->key_idx = cpu_to_le32(arg->key_idx); 2103 cmd->key_flags = cpu_to_le32(arg->key_flags); 2104 cmd->key_cipher = cpu_to_le32(arg->key_cipher); 2105 cmd->key_len = cpu_to_le32(arg->key_len); 2106 cmd->key_txmic_len = cpu_to_le32(arg->key_txmic_len); 2107 cmd->key_rxmic_len = cpu_to_le32(arg->key_rxmic_len); 2108 2109 if (arg->key_rsc_counter) 2110 cmd->key_rsc_counter = cpu_to_le64(arg->key_rsc_counter); 2111 2112 tlv = (struct wmi_tlv *)(skb->data + sizeof(*cmd)); 2113 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, key_len_aligned); 2114 memcpy(tlv->value, arg->key_data, arg->key_len); 2115 2116 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 2117 "WMI vdev install key idx %d cipher %d len %d\n", 2118 arg->key_idx, arg->key_cipher, arg->key_len); 2119 2120 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_VDEV_INSTALL_KEY_CMDID); 2121 if (ret) { 2122 ath12k_warn(ar->ab, 2123 "failed to send WMI_VDEV_INSTALL_KEY cmd\n"); 2124 dev_kfree_skb(skb); 2125 } 2126 2127 return ret; 2128 } 2129 2130 static void ath12k_wmi_copy_peer_flags(struct wmi_peer_assoc_complete_cmd *cmd, 2131 struct ath12k_wmi_peer_assoc_arg *arg, 2132 bool hw_crypto_disabled) 2133 { 2134 cmd->peer_flags = 0; 2135 cmd->peer_flags_ext = 0; 2136 2137 if (arg->is_wme_set) { 2138 if (arg->qos_flag) 2139 cmd->peer_flags |= cpu_to_le32(WMI_PEER_QOS); 2140 if (arg->apsd_flag) 2141 cmd->peer_flags |= cpu_to_le32(WMI_PEER_APSD); 2142 if (arg->ht_flag) 2143 cmd->peer_flags |= cpu_to_le32(WMI_PEER_HT); 2144 if (arg->bw_40) 2145 cmd->peer_flags |= cpu_to_le32(WMI_PEER_40MHZ); 2146 if (arg->bw_80) 2147 cmd->peer_flags |= cpu_to_le32(WMI_PEER_80MHZ); 2148 if (arg->bw_160) 2149 cmd->peer_flags |= cpu_to_le32(WMI_PEER_160MHZ); 2150 if (arg->bw_320) 2151 cmd->peer_flags_ext |= cpu_to_le32(WMI_PEER_EXT_320MHZ); 2152 2153 /* Typically if STBC is enabled for VHT it should be enabled 2154 * for HT as well 2155 **/ 2156 if (arg->stbc_flag) 2157 cmd->peer_flags |= cpu_to_le32(WMI_PEER_STBC); 2158 2159 /* Typically if LDPC is enabled for VHT it should be enabled 2160 * for HT as well 2161 **/ 2162 if (arg->ldpc_flag) 2163 cmd->peer_flags |= cpu_to_le32(WMI_PEER_LDPC); 2164 2165 if (arg->static_mimops_flag) 2166 cmd->peer_flags |= cpu_to_le32(WMI_PEER_STATIC_MIMOPS); 2167 if (arg->dynamic_mimops_flag) 2168 cmd->peer_flags |= cpu_to_le32(WMI_PEER_DYN_MIMOPS); 2169 if (arg->spatial_mux_flag) 2170 cmd->peer_flags |= cpu_to_le32(WMI_PEER_SPATIAL_MUX); 2171 if (arg->vht_flag) 2172 cmd->peer_flags |= cpu_to_le32(WMI_PEER_VHT); 2173 if (arg->he_flag) 2174 cmd->peer_flags |= cpu_to_le32(WMI_PEER_HE); 2175 if (arg->twt_requester) 2176 cmd->peer_flags |= cpu_to_le32(WMI_PEER_TWT_REQ); 2177 if (arg->twt_responder) 2178 cmd->peer_flags |= cpu_to_le32(WMI_PEER_TWT_RESP); 2179 if (arg->eht_flag) 2180 cmd->peer_flags_ext |= cpu_to_le32(WMI_PEER_EXT_EHT); 2181 } 2182 2183 /* Suppress authorization for all AUTH modes that need 4-way handshake 2184 * (during re-association). 2185 * Authorization will be done for these modes on key installation. 2186 */ 2187 if (arg->auth_flag) 2188 cmd->peer_flags |= cpu_to_le32(WMI_PEER_AUTH); 2189 if (arg->need_ptk_4_way) { 2190 cmd->peer_flags |= cpu_to_le32(WMI_PEER_NEED_PTK_4_WAY); 2191 if (!hw_crypto_disabled && arg->is_assoc) 2192 cmd->peer_flags &= cpu_to_le32(~WMI_PEER_AUTH); 2193 } 2194 if (arg->need_gtk_2_way) 2195 cmd->peer_flags |= cpu_to_le32(WMI_PEER_NEED_GTK_2_WAY); 2196 /* safe mode bypass the 4-way handshake */ 2197 if (arg->safe_mode_enabled) 2198 cmd->peer_flags &= cpu_to_le32(~(WMI_PEER_NEED_PTK_4_WAY | 2199 WMI_PEER_NEED_GTK_2_WAY)); 2200 2201 if (arg->is_pmf_enabled) 2202 cmd->peer_flags |= cpu_to_le32(WMI_PEER_PMF); 2203 2204 /* Disable AMSDU for station transmit, if user configures it */ 2205 /* Disable AMSDU for AP transmit to 11n Stations, if user configures 2206 * it 2207 * if (arg->amsdu_disable) Add after FW support 2208 **/ 2209 2210 /* Target asserts if node is marked HT and all MCS is set to 0. 2211 * Mark the node as non-HT if all the mcs rates are disabled through 2212 * iwpriv 2213 **/ 2214 if (arg->peer_ht_rates.num_rates == 0) 2215 cmd->peer_flags &= cpu_to_le32(~WMI_PEER_HT); 2216 } 2217 2218 int ath12k_wmi_send_peer_assoc_cmd(struct ath12k *ar, 2219 struct ath12k_wmi_peer_assoc_arg *arg) 2220 { 2221 struct ath12k_wmi_pdev *wmi = ar->wmi; 2222 struct wmi_peer_assoc_complete_cmd *cmd; 2223 struct ath12k_wmi_vht_rate_set_params *mcs; 2224 struct ath12k_wmi_he_rate_set_params *he_mcs; 2225 struct ath12k_wmi_eht_rate_set_params *eht_mcs; 2226 struct wmi_peer_assoc_mlo_params *ml_params; 2227 struct wmi_peer_assoc_mlo_partner_info_params *partner_info; 2228 struct sk_buff *skb; 2229 struct wmi_tlv *tlv; 2230 void *ptr; 2231 u32 peer_legacy_rates_align, eml_pad_delay, eml_trans_delay; 2232 u32 peer_ht_rates_align, eml_trans_timeout; 2233 int i, ret, len; 2234 u16 eml_cap; 2235 __le32 v; 2236 2237 peer_legacy_rates_align = roundup(arg->peer_legacy_rates.num_rates, 2238 sizeof(u32)); 2239 peer_ht_rates_align = roundup(arg->peer_ht_rates.num_rates, 2240 sizeof(u32)); 2241 2242 len = sizeof(*cmd) + 2243 TLV_HDR_SIZE + (peer_legacy_rates_align * sizeof(u8)) + 2244 TLV_HDR_SIZE + (peer_ht_rates_align * sizeof(u8)) + 2245 sizeof(*mcs) + TLV_HDR_SIZE + 2246 (sizeof(*he_mcs) * arg->peer_he_mcs_count) + 2247 TLV_HDR_SIZE + (sizeof(*eht_mcs) * arg->peer_eht_mcs_count); 2248 2249 if (arg->ml.enabled) 2250 len += TLV_HDR_SIZE + sizeof(*ml_params) + 2251 TLV_HDR_SIZE + (arg->ml.num_partner_links * sizeof(*partner_info)); 2252 else 2253 len += (2 * TLV_HDR_SIZE); 2254 2255 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 2256 if (!skb) 2257 return -ENOMEM; 2258 2259 ptr = skb->data; 2260 2261 cmd = ptr; 2262 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PEER_ASSOC_COMPLETE_CMD, 2263 sizeof(*cmd)); 2264 2265 cmd->vdev_id = cpu_to_le32(arg->vdev_id); 2266 2267 cmd->peer_new_assoc = cpu_to_le32(arg->peer_new_assoc); 2268 cmd->peer_associd = cpu_to_le32(arg->peer_associd); 2269 cmd->punct_bitmap = cpu_to_le32(arg->punct_bitmap); 2270 2271 ath12k_wmi_copy_peer_flags(cmd, arg, 2272 test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, 2273 &ar->ab->dev_flags)); 2274 2275 ether_addr_copy(cmd->peer_macaddr.addr, arg->peer_mac); 2276 2277 cmd->peer_rate_caps = cpu_to_le32(arg->peer_rate_caps); 2278 cmd->peer_caps = cpu_to_le32(arg->peer_caps); 2279 cmd->peer_listen_intval = cpu_to_le32(arg->peer_listen_intval); 2280 cmd->peer_ht_caps = cpu_to_le32(arg->peer_ht_caps); 2281 cmd->peer_max_mpdu = cpu_to_le32(arg->peer_max_mpdu); 2282 cmd->peer_mpdu_density = cpu_to_le32(arg->peer_mpdu_density); 2283 cmd->peer_vht_caps = cpu_to_le32(arg->peer_vht_caps); 2284 cmd->peer_phymode = cpu_to_le32(arg->peer_phymode); 2285 2286 /* Update 11ax capabilities */ 2287 cmd->peer_he_cap_info = cpu_to_le32(arg->peer_he_cap_macinfo[0]); 2288 cmd->peer_he_cap_info_ext = cpu_to_le32(arg->peer_he_cap_macinfo[1]); 2289 cmd->peer_he_cap_info_internal = cpu_to_le32(arg->peer_he_cap_macinfo_internal); 2290 cmd->peer_he_caps_6ghz = cpu_to_le32(arg->peer_he_caps_6ghz); 2291 cmd->peer_he_ops = cpu_to_le32(arg->peer_he_ops); 2292 for (i = 0; i < WMI_MAX_HECAP_PHY_SIZE; i++) 2293 cmd->peer_he_cap_phy[i] = 2294 cpu_to_le32(arg->peer_he_cap_phyinfo[i]); 2295 cmd->peer_ppet.numss_m1 = cpu_to_le32(arg->peer_ppet.numss_m1); 2296 cmd->peer_ppet.ru_info = cpu_to_le32(arg->peer_ppet.ru_bit_mask); 2297 for (i = 0; i < WMI_MAX_NUM_SS; i++) 2298 cmd->peer_ppet.ppet16_ppet8_ru3_ru0[i] = 2299 cpu_to_le32(arg->peer_ppet.ppet16_ppet8_ru3_ru0[i]); 2300 2301 /* Update 11be capabilities */ 2302 memcpy_and_pad(cmd->peer_eht_cap_mac, sizeof(cmd->peer_eht_cap_mac), 2303 arg->peer_eht_cap_mac, sizeof(arg->peer_eht_cap_mac), 2304 0); 2305 memcpy_and_pad(cmd->peer_eht_cap_phy, sizeof(cmd->peer_eht_cap_phy), 2306 arg->peer_eht_cap_phy, sizeof(arg->peer_eht_cap_phy), 2307 0); 2308 memcpy_and_pad(&cmd->peer_eht_ppet, sizeof(cmd->peer_eht_ppet), 2309 &arg->peer_eht_ppet, sizeof(arg->peer_eht_ppet), 0); 2310 2311 /* Update peer legacy rate information */ 2312 ptr += sizeof(*cmd); 2313 2314 tlv = ptr; 2315 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, peer_legacy_rates_align); 2316 2317 ptr += TLV_HDR_SIZE; 2318 2319 cmd->num_peer_legacy_rates = cpu_to_le32(arg->peer_legacy_rates.num_rates); 2320 memcpy(ptr, arg->peer_legacy_rates.rates, 2321 arg->peer_legacy_rates.num_rates); 2322 2323 /* Update peer HT rate information */ 2324 ptr += peer_legacy_rates_align; 2325 2326 tlv = ptr; 2327 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, peer_ht_rates_align); 2328 ptr += TLV_HDR_SIZE; 2329 cmd->num_peer_ht_rates = cpu_to_le32(arg->peer_ht_rates.num_rates); 2330 memcpy(ptr, arg->peer_ht_rates.rates, 2331 arg->peer_ht_rates.num_rates); 2332 2333 /* VHT Rates */ 2334 ptr += peer_ht_rates_align; 2335 2336 mcs = ptr; 2337 2338 mcs->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VHT_RATE_SET, 2339 sizeof(*mcs)); 2340 2341 cmd->peer_nss = cpu_to_le32(arg->peer_nss); 2342 2343 /* Update bandwidth-NSS mapping */ 2344 cmd->peer_bw_rxnss_override = 0; 2345 cmd->peer_bw_rxnss_override |= cpu_to_le32(arg->peer_bw_rxnss_override); 2346 2347 if (arg->vht_capable) { 2348 /* Firmware interprets mcs->tx_mcs_set field as peer's 2349 * RX capability 2350 */ 2351 mcs->rx_max_rate = cpu_to_le32(arg->tx_max_rate); 2352 mcs->rx_mcs_set = cpu_to_le32(arg->tx_mcs_set); 2353 mcs->tx_max_rate = cpu_to_le32(arg->rx_max_rate); 2354 mcs->tx_mcs_set = cpu_to_le32(arg->rx_mcs_set); 2355 } 2356 2357 /* HE Rates */ 2358 cmd->peer_he_mcs = cpu_to_le32(arg->peer_he_mcs_count); 2359 cmd->min_data_rate = cpu_to_le32(arg->min_data_rate); 2360 2361 ptr += sizeof(*mcs); 2362 2363 len = arg->peer_he_mcs_count * sizeof(*he_mcs); 2364 2365 tlv = ptr; 2366 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, len); 2367 ptr += TLV_HDR_SIZE; 2368 2369 /* Loop through the HE rate set */ 2370 for (i = 0; i < arg->peer_he_mcs_count; i++) { 2371 he_mcs = ptr; 2372 he_mcs->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_HE_RATE_SET, 2373 sizeof(*he_mcs)); 2374 2375 he_mcs->rx_mcs_set = cpu_to_le32(arg->peer_he_rx_mcs_set[i]); 2376 he_mcs->tx_mcs_set = cpu_to_le32(arg->peer_he_tx_mcs_set[i]); 2377 ptr += sizeof(*he_mcs); 2378 } 2379 2380 tlv = ptr; 2381 len = arg->ml.enabled ? sizeof(*ml_params) : 0; 2382 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, len); 2383 ptr += TLV_HDR_SIZE; 2384 if (!len) 2385 goto skip_ml_params; 2386 2387 ml_params = ptr; 2388 ml_params->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_MLO_PEER_ASSOC_PARAMS, 2389 len); 2390 ml_params->flags = cpu_to_le32(ATH12K_WMI_FLAG_MLO_ENABLED); 2391 2392 if (arg->ml.assoc_link) 2393 ml_params->flags |= cpu_to_le32(ATH12K_WMI_FLAG_MLO_ASSOC_LINK); 2394 2395 if (arg->ml.primary_umac) 2396 ml_params->flags |= cpu_to_le32(ATH12K_WMI_FLAG_MLO_PRIMARY_UMAC); 2397 2398 if (arg->ml.logical_link_idx_valid) 2399 ml_params->flags |= 2400 cpu_to_le32(ATH12K_WMI_FLAG_MLO_LOGICAL_LINK_IDX_VALID); 2401 2402 if (arg->ml.peer_id_valid) 2403 ml_params->flags |= cpu_to_le32(ATH12K_WMI_FLAG_MLO_PEER_ID_VALID); 2404 2405 ether_addr_copy(ml_params->mld_addr.addr, arg->ml.mld_addr); 2406 ml_params->logical_link_idx = cpu_to_le32(arg->ml.logical_link_idx); 2407 ml_params->ml_peer_id = cpu_to_le32(arg->ml.ml_peer_id); 2408 ml_params->ieee_link_id = cpu_to_le32(arg->ml.ieee_link_id); 2409 2410 eml_cap = arg->ml.eml_cap; 2411 if (u16_get_bits(eml_cap, IEEE80211_EML_CAP_EMLSR_SUPP)) { 2412 ml_params->flags |= cpu_to_le32(ATH12K_WMI_FLAG_MLO_EMLSR_SUPPORT); 2413 /* Padding delay */ 2414 eml_pad_delay = ieee80211_emlsr_pad_delay_in_us(eml_cap); 2415 ml_params->emlsr_padding_delay_us = cpu_to_le32(eml_pad_delay); 2416 /* Transition delay */ 2417 eml_trans_delay = ieee80211_emlsr_trans_delay_in_us(eml_cap); 2418 ml_params->emlsr_trans_delay_us = cpu_to_le32(eml_trans_delay); 2419 /* Transition timeout */ 2420 eml_trans_timeout = ieee80211_eml_trans_timeout_in_us(eml_cap); 2421 ml_params->emlsr_trans_timeout_us = 2422 cpu_to_le32(eml_trans_timeout); 2423 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "wmi peer %pM emlsr padding delay %u, trans delay %u trans timeout %u", 2424 arg->peer_mac, eml_pad_delay, eml_trans_delay, 2425 eml_trans_timeout); 2426 } 2427 2428 ptr += sizeof(*ml_params); 2429 2430 skip_ml_params: 2431 /* Loop through the EHT rate set */ 2432 len = arg->peer_eht_mcs_count * sizeof(*eht_mcs); 2433 tlv = ptr; 2434 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, len); 2435 ptr += TLV_HDR_SIZE; 2436 2437 for (i = 0; i < arg->peer_eht_mcs_count; i++) { 2438 eht_mcs = ptr; 2439 eht_mcs->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_EHT_RATE_SET, 2440 sizeof(*eht_mcs)); 2441 2442 eht_mcs->rx_mcs_set = cpu_to_le32(arg->peer_eht_rx_mcs_set[i]); 2443 eht_mcs->tx_mcs_set = cpu_to_le32(arg->peer_eht_tx_mcs_set[i]); 2444 ptr += sizeof(*eht_mcs); 2445 } 2446 2447 /* Update MCS15 capability */ 2448 if (arg->eht_disable_mcs15) 2449 cmd->peer_eht_ops = cpu_to_le32(IEEE80211_EHT_OPER_MCS15_DISABLE); 2450 2451 tlv = ptr; 2452 len = arg->ml.enabled ? arg->ml.num_partner_links * sizeof(*partner_info) : 0; 2453 /* fill ML Partner links */ 2454 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, len); 2455 ptr += TLV_HDR_SIZE; 2456 2457 if (len == 0) 2458 goto send; 2459 2460 for (i = 0; i < arg->ml.num_partner_links; i++) { 2461 u32 cmd = WMI_TAG_MLO_PARTNER_LINK_PARAMS_PEER_ASSOC; 2462 2463 partner_info = ptr; 2464 partner_info->tlv_header = ath12k_wmi_tlv_cmd_hdr(cmd, 2465 sizeof(*partner_info)); 2466 partner_info->vdev_id = cpu_to_le32(arg->ml.partner_info[i].vdev_id); 2467 partner_info->hw_link_id = 2468 cpu_to_le32(arg->ml.partner_info[i].hw_link_id); 2469 partner_info->flags = cpu_to_le32(ATH12K_WMI_FLAG_MLO_ENABLED); 2470 2471 if (arg->ml.partner_info[i].assoc_link) 2472 partner_info->flags |= 2473 cpu_to_le32(ATH12K_WMI_FLAG_MLO_ASSOC_LINK); 2474 2475 if (arg->ml.partner_info[i].primary_umac) 2476 partner_info->flags |= 2477 cpu_to_le32(ATH12K_WMI_FLAG_MLO_PRIMARY_UMAC); 2478 2479 if (arg->ml.partner_info[i].logical_link_idx_valid) { 2480 v = cpu_to_le32(ATH12K_WMI_FLAG_MLO_LINK_ID_VALID); 2481 partner_info->flags |= v; 2482 } 2483 2484 partner_info->logical_link_idx = 2485 cpu_to_le32(arg->ml.partner_info[i].logical_link_idx); 2486 ptr += sizeof(*partner_info); 2487 } 2488 2489 send: 2490 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 2491 "wmi peer assoc vdev id %d assoc id %d peer mac %pM peer_flags %x rate_caps %x peer_caps %x listen_intval %d ht_caps %x max_mpdu %d nss %d phymode %d peer_mpdu_density %d vht_caps %x he cap_info %x he ops %x he cap_info_ext %x he phy %x %x %x peer_bw_rxnss_override %x peer_flags_ext %x eht mac_cap %x %x eht phy_cap %x %x %x peer_eht_ops %x\n", 2492 cmd->vdev_id, cmd->peer_associd, arg->peer_mac, 2493 cmd->peer_flags, cmd->peer_rate_caps, cmd->peer_caps, 2494 cmd->peer_listen_intval, cmd->peer_ht_caps, 2495 cmd->peer_max_mpdu, cmd->peer_nss, cmd->peer_phymode, 2496 cmd->peer_mpdu_density, 2497 cmd->peer_vht_caps, cmd->peer_he_cap_info, 2498 cmd->peer_he_ops, cmd->peer_he_cap_info_ext, 2499 cmd->peer_he_cap_phy[0], cmd->peer_he_cap_phy[1], 2500 cmd->peer_he_cap_phy[2], 2501 cmd->peer_bw_rxnss_override, cmd->peer_flags_ext, 2502 cmd->peer_eht_cap_mac[0], cmd->peer_eht_cap_mac[1], 2503 cmd->peer_eht_cap_phy[0], cmd->peer_eht_cap_phy[1], 2504 cmd->peer_eht_cap_phy[2], cmd->peer_eht_ops); 2505 2506 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PEER_ASSOC_CMDID); 2507 if (ret) { 2508 ath12k_warn(ar->ab, 2509 "failed to send WMI_PEER_ASSOC_CMDID\n"); 2510 dev_kfree_skb(skb); 2511 } 2512 2513 return ret; 2514 } 2515 2516 void ath12k_wmi_start_scan_init(struct ath12k *ar, 2517 struct ath12k_wmi_scan_req_arg *arg) 2518 { 2519 /* setup commonly used values */ 2520 arg->scan_req_id = 1; 2521 arg->scan_priority = WMI_SCAN_PRIORITY_LOW; 2522 arg->dwell_time_active = 50; 2523 arg->dwell_time_active_2g = 0; 2524 arg->dwell_time_passive = 150; 2525 arg->dwell_time_active_6g = 70; 2526 arg->dwell_time_passive_6g = 70; 2527 arg->min_rest_time = 50; 2528 arg->max_rest_time = 500; 2529 arg->repeat_probe_time = 0; 2530 arg->probe_spacing_time = 0; 2531 arg->idle_time = 0; 2532 arg->max_scan_time = 20000; 2533 arg->probe_delay = 5; 2534 arg->notify_scan_events = WMI_SCAN_EVENT_STARTED | 2535 WMI_SCAN_EVENT_COMPLETED | 2536 WMI_SCAN_EVENT_BSS_CHANNEL | 2537 WMI_SCAN_EVENT_FOREIGN_CHAN | 2538 WMI_SCAN_EVENT_DEQUEUED; 2539 arg->scan_f_chan_stat_evnt = 1; 2540 arg->num_bssid = 1; 2541 2542 /* fill bssid_list[0] with 0xff, otherwise bssid and RA will be 2543 * ZEROs in probe request 2544 */ 2545 eth_broadcast_addr(arg->bssid_list[0].addr); 2546 } 2547 2548 static void ath12k_wmi_copy_scan_event_cntrl_flags(struct wmi_start_scan_cmd *cmd, 2549 struct ath12k_wmi_scan_req_arg *arg) 2550 { 2551 /* Scan events subscription */ 2552 if (arg->scan_ev_started) 2553 cmd->notify_scan_events |= cpu_to_le32(WMI_SCAN_EVENT_STARTED); 2554 if (arg->scan_ev_completed) 2555 cmd->notify_scan_events |= cpu_to_le32(WMI_SCAN_EVENT_COMPLETED); 2556 if (arg->scan_ev_bss_chan) 2557 cmd->notify_scan_events |= cpu_to_le32(WMI_SCAN_EVENT_BSS_CHANNEL); 2558 if (arg->scan_ev_foreign_chan) 2559 cmd->notify_scan_events |= cpu_to_le32(WMI_SCAN_EVENT_FOREIGN_CHAN); 2560 if (arg->scan_ev_dequeued) 2561 cmd->notify_scan_events |= cpu_to_le32(WMI_SCAN_EVENT_DEQUEUED); 2562 if (arg->scan_ev_preempted) 2563 cmd->notify_scan_events |= cpu_to_le32(WMI_SCAN_EVENT_PREEMPTED); 2564 if (arg->scan_ev_start_failed) 2565 cmd->notify_scan_events |= cpu_to_le32(WMI_SCAN_EVENT_START_FAILED); 2566 if (arg->scan_ev_restarted) 2567 cmd->notify_scan_events |= cpu_to_le32(WMI_SCAN_EVENT_RESTARTED); 2568 if (arg->scan_ev_foreign_chn_exit) 2569 cmd->notify_scan_events |= cpu_to_le32(WMI_SCAN_EVENT_FOREIGN_CHAN_EXIT); 2570 if (arg->scan_ev_suspended) 2571 cmd->notify_scan_events |= cpu_to_le32(WMI_SCAN_EVENT_SUSPENDED); 2572 if (arg->scan_ev_resumed) 2573 cmd->notify_scan_events |= cpu_to_le32(WMI_SCAN_EVENT_RESUMED); 2574 2575 /** Set scan control flags */ 2576 cmd->scan_ctrl_flags = 0; 2577 if (arg->scan_f_passive) 2578 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_FLAG_PASSIVE); 2579 if (arg->scan_f_strict_passive_pch) 2580 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_FLAG_STRICT_PASSIVE_ON_PCHN); 2581 if (arg->scan_f_promisc_mode) 2582 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_FILTER_PROMISCUOS); 2583 if (arg->scan_f_capture_phy_err) 2584 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_CAPTURE_PHY_ERROR); 2585 if (arg->scan_f_half_rate) 2586 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_FLAG_HALF_RATE_SUPPORT); 2587 if (arg->scan_f_quarter_rate) 2588 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_FLAG_QUARTER_RATE_SUPPORT); 2589 if (arg->scan_f_cck_rates) 2590 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_ADD_CCK_RATES); 2591 if (arg->scan_f_ofdm_rates) 2592 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_ADD_OFDM_RATES); 2593 if (arg->scan_f_chan_stat_evnt) 2594 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_CHAN_STAT_EVENT); 2595 if (arg->scan_f_filter_prb_req) 2596 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_FILTER_PROBE_REQ); 2597 if (arg->scan_f_bcast_probe) 2598 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_ADD_BCAST_PROBE_REQ); 2599 if (arg->scan_f_offchan_mgmt_tx) 2600 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_OFFCHAN_MGMT_TX); 2601 if (arg->scan_f_offchan_data_tx) 2602 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_OFFCHAN_DATA_TX); 2603 if (arg->scan_f_force_active_dfs_chn) 2604 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_FLAG_FORCE_ACTIVE_ON_DFS); 2605 if (arg->scan_f_add_tpc_ie_in_probe) 2606 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_ADD_TPC_IE_IN_PROBE_REQ); 2607 if (arg->scan_f_add_ds_ie_in_probe) 2608 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_ADD_DS_IE_IN_PROBE_REQ); 2609 if (arg->scan_f_add_spoofed_mac_in_probe) 2610 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_ADD_SPOOF_MAC_IN_PROBE_REQ); 2611 if (arg->scan_f_add_rand_seq_in_probe) 2612 cmd->scan_ctrl_flags |= cpu_to_le32(WMI_SCAN_RANDOM_SEQ_NO_IN_PROBE_REQ); 2613 if (arg->scan_f_en_ie_whitelist_in_probe) 2614 cmd->scan_ctrl_flags |= 2615 cpu_to_le32(WMI_SCAN_ENABLE_IE_WHTELIST_IN_PROBE_REQ); 2616 2617 cmd->scan_ctrl_flags |= le32_encode_bits(arg->adaptive_dwell_time_mode, 2618 WMI_SCAN_DWELL_MODE_MASK); 2619 } 2620 2621 int ath12k_wmi_send_scan_start_cmd(struct ath12k *ar, 2622 struct ath12k_wmi_scan_req_arg *arg) 2623 { 2624 struct ath12k_wmi_pdev *wmi = ar->wmi; 2625 struct wmi_start_scan_cmd *cmd; 2626 struct ath12k_wmi_ssid_params *ssid = NULL; 2627 struct ath12k_wmi_mac_addr_params *bssid; 2628 struct sk_buff *skb; 2629 struct wmi_tlv *tlv; 2630 void *ptr; 2631 int i, ret, len; 2632 u32 *tmp_ptr, extraie_len_with_pad = 0; 2633 struct ath12k_wmi_hint_short_ssid_arg *s_ssid = NULL; 2634 struct ath12k_wmi_hint_bssid_arg *hint_bssid = NULL; 2635 2636 len = sizeof(*cmd); 2637 2638 len += TLV_HDR_SIZE; 2639 if (arg->num_chan) 2640 len += arg->num_chan * sizeof(u32); 2641 2642 len += TLV_HDR_SIZE; 2643 if (arg->num_ssids) 2644 len += arg->num_ssids * sizeof(*ssid); 2645 2646 len += TLV_HDR_SIZE; 2647 if (arg->num_bssid) 2648 len += sizeof(*bssid) * arg->num_bssid; 2649 2650 if (arg->num_hint_bssid) 2651 len += TLV_HDR_SIZE + 2652 arg->num_hint_bssid * sizeof(*hint_bssid); 2653 2654 if (arg->num_hint_s_ssid) 2655 len += TLV_HDR_SIZE + 2656 arg->num_hint_s_ssid * sizeof(*s_ssid); 2657 2658 len += TLV_HDR_SIZE; 2659 if (arg->extraie.len) 2660 extraie_len_with_pad = 2661 roundup(arg->extraie.len, sizeof(u32)); 2662 if (extraie_len_with_pad <= (wmi->wmi_ab->max_msg_len[ar->pdev_idx] - len)) { 2663 len += extraie_len_with_pad; 2664 } else { 2665 ath12k_warn(ar->ab, "discard large size %d bytes extraie for scan start\n", 2666 arg->extraie.len); 2667 extraie_len_with_pad = 0; 2668 } 2669 2670 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 2671 if (!skb) 2672 return -ENOMEM; 2673 2674 ptr = skb->data; 2675 2676 cmd = ptr; 2677 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_START_SCAN_CMD, 2678 sizeof(*cmd)); 2679 2680 cmd->scan_id = cpu_to_le32(arg->scan_id); 2681 cmd->scan_req_id = cpu_to_le32(arg->scan_req_id); 2682 cmd->vdev_id = cpu_to_le32(arg->vdev_id); 2683 if (ar->state_11d == ATH12K_11D_PREPARING) 2684 arg->scan_priority = WMI_SCAN_PRIORITY_MEDIUM; 2685 else 2686 arg->scan_priority = WMI_SCAN_PRIORITY_LOW; 2687 cmd->notify_scan_events = cpu_to_le32(arg->notify_scan_events); 2688 2689 ath12k_wmi_copy_scan_event_cntrl_flags(cmd, arg); 2690 2691 cmd->dwell_time_active = cpu_to_le32(arg->dwell_time_active); 2692 cmd->dwell_time_active_2g = cpu_to_le32(arg->dwell_time_active_2g); 2693 cmd->dwell_time_passive = cpu_to_le32(arg->dwell_time_passive); 2694 cmd->dwell_time_active_6g = cpu_to_le32(arg->dwell_time_active_6g); 2695 cmd->dwell_time_passive_6g = cpu_to_le32(arg->dwell_time_passive_6g); 2696 cmd->min_rest_time = cpu_to_le32(arg->min_rest_time); 2697 cmd->max_rest_time = cpu_to_le32(arg->max_rest_time); 2698 cmd->repeat_probe_time = cpu_to_le32(arg->repeat_probe_time); 2699 cmd->probe_spacing_time = cpu_to_le32(arg->probe_spacing_time); 2700 cmd->idle_time = cpu_to_le32(arg->idle_time); 2701 cmd->max_scan_time = cpu_to_le32(arg->max_scan_time); 2702 cmd->probe_delay = cpu_to_le32(arg->probe_delay); 2703 cmd->burst_duration = cpu_to_le32(arg->burst_duration); 2704 cmd->num_chan = cpu_to_le32(arg->num_chan); 2705 cmd->num_bssid = cpu_to_le32(arg->num_bssid); 2706 cmd->num_ssids = cpu_to_le32(arg->num_ssids); 2707 cmd->ie_len = cpu_to_le32(arg->extraie.len); 2708 cmd->n_probes = cpu_to_le32(arg->n_probes); 2709 2710 ptr += sizeof(*cmd); 2711 2712 len = arg->num_chan * sizeof(u32); 2713 2714 tlv = ptr; 2715 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_UINT32, len); 2716 ptr += TLV_HDR_SIZE; 2717 tmp_ptr = (u32 *)ptr; 2718 2719 memcpy(tmp_ptr, arg->chan_list, arg->num_chan * 4); 2720 2721 ptr += len; 2722 2723 len = arg->num_ssids * sizeof(*ssid); 2724 tlv = ptr; 2725 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_FIXED_STRUCT, len); 2726 2727 ptr += TLV_HDR_SIZE; 2728 2729 if (arg->num_ssids) { 2730 ssid = ptr; 2731 for (i = 0; i < arg->num_ssids; ++i) { 2732 ssid->ssid_len = cpu_to_le32(arg->ssid[i].ssid_len); 2733 memcpy(ssid->ssid, arg->ssid[i].ssid, 2734 arg->ssid[i].ssid_len); 2735 ssid++; 2736 } 2737 } 2738 2739 ptr += (arg->num_ssids * sizeof(*ssid)); 2740 len = arg->num_bssid * sizeof(*bssid); 2741 tlv = ptr; 2742 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_FIXED_STRUCT, len); 2743 2744 ptr += TLV_HDR_SIZE; 2745 bssid = ptr; 2746 2747 if (arg->num_bssid) { 2748 for (i = 0; i < arg->num_bssid; ++i) { 2749 ether_addr_copy(bssid->addr, 2750 arg->bssid_list[i].addr); 2751 bssid++; 2752 } 2753 } 2754 2755 ptr += arg->num_bssid * sizeof(*bssid); 2756 2757 len = extraie_len_with_pad; 2758 tlv = ptr; 2759 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, len); 2760 ptr += TLV_HDR_SIZE; 2761 2762 if (extraie_len_with_pad) 2763 memcpy(ptr, arg->extraie.ptr, 2764 arg->extraie.len); 2765 2766 ptr += extraie_len_with_pad; 2767 2768 if (arg->num_hint_s_ssid) { 2769 len = arg->num_hint_s_ssid * sizeof(*s_ssid); 2770 tlv = ptr; 2771 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_FIXED_STRUCT, len); 2772 ptr += TLV_HDR_SIZE; 2773 s_ssid = ptr; 2774 for (i = 0; i < arg->num_hint_s_ssid; ++i) { 2775 s_ssid->freq_flags = arg->hint_s_ssid[i].freq_flags; 2776 s_ssid->short_ssid = arg->hint_s_ssid[i].short_ssid; 2777 s_ssid++; 2778 } 2779 ptr += len; 2780 } 2781 2782 if (arg->num_hint_bssid) { 2783 len = arg->num_hint_bssid * sizeof(struct ath12k_wmi_hint_bssid_arg); 2784 tlv = ptr; 2785 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_FIXED_STRUCT, len); 2786 ptr += TLV_HDR_SIZE; 2787 hint_bssid = ptr; 2788 for (i = 0; i < arg->num_hint_bssid; ++i) { 2789 hint_bssid->freq_flags = 2790 arg->hint_bssid[i].freq_flags; 2791 ether_addr_copy(&arg->hint_bssid[i].bssid.addr[0], 2792 &hint_bssid->bssid.addr[0]); 2793 hint_bssid++; 2794 } 2795 } 2796 2797 ret = ath12k_wmi_cmd_send(wmi, skb, 2798 WMI_START_SCAN_CMDID); 2799 if (ret) { 2800 ath12k_warn(ar->ab, "failed to send WMI_START_SCAN_CMDID\n"); 2801 dev_kfree_skb(skb); 2802 } 2803 2804 return ret; 2805 } 2806 2807 int ath12k_wmi_send_scan_stop_cmd(struct ath12k *ar, 2808 struct ath12k_wmi_scan_cancel_arg *arg) 2809 { 2810 struct ath12k_wmi_pdev *wmi = ar->wmi; 2811 struct wmi_stop_scan_cmd *cmd; 2812 struct sk_buff *skb; 2813 int ret; 2814 2815 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 2816 if (!skb) 2817 return -ENOMEM; 2818 2819 cmd = (struct wmi_stop_scan_cmd *)skb->data; 2820 2821 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_STOP_SCAN_CMD, 2822 sizeof(*cmd)); 2823 2824 cmd->vdev_id = cpu_to_le32(arg->vdev_id); 2825 cmd->requestor = cpu_to_le32(arg->requester); 2826 cmd->scan_id = cpu_to_le32(arg->scan_id); 2827 cmd->pdev_id = cpu_to_le32(arg->pdev_id); 2828 /* stop the scan with the corresponding scan_id */ 2829 if (arg->req_type == WLAN_SCAN_CANCEL_PDEV_ALL) { 2830 /* Cancelling all scans */ 2831 cmd->req_type = cpu_to_le32(WMI_SCAN_STOP_ALL); 2832 } else if (arg->req_type == WLAN_SCAN_CANCEL_VDEV_ALL) { 2833 /* Cancelling VAP scans */ 2834 cmd->req_type = cpu_to_le32(WMI_SCAN_STOP_VAP_ALL); 2835 } else if (arg->req_type == WLAN_SCAN_CANCEL_SINGLE) { 2836 /* Cancelling specific scan */ 2837 cmd->req_type = WMI_SCAN_STOP_ONE; 2838 } else { 2839 ath12k_warn(ar->ab, "invalid scan cancel req_type %d", 2840 arg->req_type); 2841 dev_kfree_skb(skb); 2842 return -EINVAL; 2843 } 2844 2845 ret = ath12k_wmi_cmd_send(wmi, skb, 2846 WMI_STOP_SCAN_CMDID); 2847 if (ret) { 2848 ath12k_warn(ar->ab, "failed to send WMI_STOP_SCAN_CMDID\n"); 2849 dev_kfree_skb(skb); 2850 } 2851 2852 return ret; 2853 } 2854 2855 int ath12k_wmi_send_scan_chan_list_cmd(struct ath12k *ar, 2856 struct ath12k_wmi_scan_chan_list_arg *arg) 2857 { 2858 struct ath12k_wmi_pdev *wmi = ar->wmi; 2859 struct wmi_scan_chan_list_cmd *cmd; 2860 struct sk_buff *skb; 2861 struct ath12k_wmi_channel_params *chan_info; 2862 struct ath12k_wmi_channel_arg *channel_arg; 2863 struct wmi_tlv *tlv; 2864 void *ptr; 2865 int i, ret, len; 2866 u16 num_send_chans, num_sends = 0, max_chan_limit = 0; 2867 __le32 *reg1, *reg2; 2868 2869 channel_arg = &arg->channel[0]; 2870 while (arg->nallchans) { 2871 len = sizeof(*cmd) + TLV_HDR_SIZE; 2872 max_chan_limit = (wmi->wmi_ab->max_msg_len[ar->pdev_idx] - len) / 2873 sizeof(*chan_info); 2874 2875 num_send_chans = min3(arg->nallchans, max_chan_limit, 2876 ATH12K_WMI_MAX_NUM_CHAN_PER_CMD); 2877 2878 arg->nallchans -= num_send_chans; 2879 len += sizeof(*chan_info) * num_send_chans; 2880 2881 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 2882 if (!skb) 2883 return -ENOMEM; 2884 2885 cmd = (struct wmi_scan_chan_list_cmd *)skb->data; 2886 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_SCAN_CHAN_LIST_CMD, 2887 sizeof(*cmd)); 2888 cmd->pdev_id = cpu_to_le32(arg->pdev_id); 2889 cmd->num_scan_chans = cpu_to_le32(num_send_chans); 2890 if (num_sends) 2891 cmd->flags |= cpu_to_le32(WMI_APPEND_TO_EXISTING_CHAN_LIST_FLAG); 2892 2893 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 2894 "WMI no.of chan = %d len = %d pdev_id = %d num_sends = %d\n", 2895 num_send_chans, len, cmd->pdev_id, num_sends); 2896 2897 ptr = skb->data + sizeof(*cmd); 2898 2899 len = sizeof(*chan_info) * num_send_chans; 2900 tlv = ptr; 2901 tlv->header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_ARRAY_STRUCT, 2902 len); 2903 ptr += TLV_HDR_SIZE; 2904 2905 for (i = 0; i < num_send_chans; ++i) { 2906 chan_info = ptr; 2907 memset(chan_info, 0, sizeof(*chan_info)); 2908 len = sizeof(*chan_info); 2909 chan_info->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_CHANNEL, 2910 len); 2911 2912 reg1 = &chan_info->reg_info_1; 2913 reg2 = &chan_info->reg_info_2; 2914 chan_info->mhz = cpu_to_le32(channel_arg->mhz); 2915 chan_info->band_center_freq1 = cpu_to_le32(channel_arg->cfreq1); 2916 chan_info->band_center_freq2 = cpu_to_le32(channel_arg->cfreq2); 2917 2918 if (channel_arg->is_chan_passive) 2919 chan_info->info |= cpu_to_le32(WMI_CHAN_INFO_PASSIVE); 2920 if (channel_arg->allow_he) 2921 chan_info->info |= cpu_to_le32(WMI_CHAN_INFO_ALLOW_HE); 2922 else if (channel_arg->allow_vht) 2923 chan_info->info |= cpu_to_le32(WMI_CHAN_INFO_ALLOW_VHT); 2924 else if (channel_arg->allow_ht) 2925 chan_info->info |= cpu_to_le32(WMI_CHAN_INFO_ALLOW_HT); 2926 if (channel_arg->half_rate) 2927 chan_info->info |= cpu_to_le32(WMI_CHAN_INFO_HALF_RATE); 2928 if (channel_arg->quarter_rate) 2929 chan_info->info |= 2930 cpu_to_le32(WMI_CHAN_INFO_QUARTER_RATE); 2931 2932 if (channel_arg->psc_channel) 2933 chan_info->info |= cpu_to_le32(WMI_CHAN_INFO_PSC); 2934 2935 if (channel_arg->dfs_set) 2936 chan_info->info |= cpu_to_le32(WMI_CHAN_INFO_DFS); 2937 2938 chan_info->info |= le32_encode_bits(channel_arg->phy_mode, 2939 WMI_CHAN_INFO_MODE); 2940 *reg1 |= le32_encode_bits(channel_arg->minpower, 2941 WMI_CHAN_REG_INFO1_MIN_PWR); 2942 *reg1 |= le32_encode_bits(channel_arg->maxpower, 2943 WMI_CHAN_REG_INFO1_MAX_PWR); 2944 *reg1 |= le32_encode_bits(channel_arg->maxregpower, 2945 WMI_CHAN_REG_INFO1_MAX_REG_PWR); 2946 *reg1 |= le32_encode_bits(channel_arg->reg_class_id, 2947 WMI_CHAN_REG_INFO1_REG_CLS); 2948 *reg2 |= le32_encode_bits(channel_arg->antennamax, 2949 WMI_CHAN_REG_INFO2_ANT_MAX); 2950 *reg2 |= le32_encode_bits(channel_arg->maxregpower, 2951 WMI_CHAN_REG_INFO2_MAX_TX_PWR); 2952 2953 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 2954 "WMI chan scan list chan[%d] = %u, chan_info->info %8x\n", 2955 i, chan_info->mhz, chan_info->info); 2956 2957 ptr += sizeof(*chan_info); 2958 2959 channel_arg++; 2960 } 2961 2962 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_SCAN_CHAN_LIST_CMDID); 2963 if (ret) { 2964 ath12k_warn(ar->ab, "failed to send WMI_SCAN_CHAN_LIST cmd\n"); 2965 dev_kfree_skb(skb); 2966 return ret; 2967 } 2968 2969 num_sends++; 2970 } 2971 2972 return 0; 2973 } 2974 2975 int ath12k_wmi_send_wmm_update_cmd(struct ath12k *ar, u32 vdev_id, 2976 struct wmi_wmm_params_all_arg *param) 2977 { 2978 struct ath12k_wmi_pdev *wmi = ar->wmi; 2979 struct wmi_vdev_set_wmm_params_cmd *cmd; 2980 struct wmi_wmm_params *wmm_param; 2981 struct wmi_wmm_params_arg *wmi_wmm_arg; 2982 struct sk_buff *skb; 2983 int ret, ac; 2984 2985 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 2986 if (!skb) 2987 return -ENOMEM; 2988 2989 cmd = (struct wmi_vdev_set_wmm_params_cmd *)skb->data; 2990 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_SET_WMM_PARAMS_CMD, 2991 sizeof(*cmd)); 2992 2993 cmd->vdev_id = cpu_to_le32(vdev_id); 2994 cmd->wmm_param_type = 0; 2995 2996 for (ac = 0; ac < WME_NUM_AC; ac++) { 2997 switch (ac) { 2998 case WME_AC_BE: 2999 wmi_wmm_arg = ¶m->ac_be; 3000 break; 3001 case WME_AC_BK: 3002 wmi_wmm_arg = ¶m->ac_bk; 3003 break; 3004 case WME_AC_VI: 3005 wmi_wmm_arg = ¶m->ac_vi; 3006 break; 3007 case WME_AC_VO: 3008 wmi_wmm_arg = ¶m->ac_vo; 3009 break; 3010 } 3011 3012 wmm_param = (struct wmi_wmm_params *)&cmd->wmm_params[ac]; 3013 wmm_param->tlv_header = 3014 ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_SET_WMM_PARAMS_CMD, 3015 sizeof(*wmm_param)); 3016 3017 wmm_param->aifs = cpu_to_le32(wmi_wmm_arg->aifs); 3018 wmm_param->cwmin = cpu_to_le32(wmi_wmm_arg->cwmin); 3019 wmm_param->cwmax = cpu_to_le32(wmi_wmm_arg->cwmax); 3020 wmm_param->txoplimit = cpu_to_le32(wmi_wmm_arg->txop); 3021 wmm_param->acm = cpu_to_le32(wmi_wmm_arg->acm); 3022 wmm_param->no_ack = cpu_to_le32(wmi_wmm_arg->no_ack); 3023 3024 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 3025 "wmi wmm set ac %d aifs %d cwmin %d cwmax %d txop %d acm %d no_ack %d\n", 3026 ac, wmm_param->aifs, wmm_param->cwmin, 3027 wmm_param->cwmax, wmm_param->txoplimit, 3028 wmm_param->acm, wmm_param->no_ack); 3029 } 3030 ret = ath12k_wmi_cmd_send(wmi, skb, 3031 WMI_VDEV_SET_WMM_PARAMS_CMDID); 3032 if (ret) { 3033 ath12k_warn(ar->ab, 3034 "failed to send WMI_VDEV_SET_WMM_PARAMS_CMDID"); 3035 dev_kfree_skb(skb); 3036 } 3037 3038 return ret; 3039 } 3040 3041 int ath12k_wmi_send_dfs_phyerr_offload_enable_cmd(struct ath12k *ar, 3042 u32 pdev_id) 3043 { 3044 struct ath12k_wmi_pdev *wmi = ar->wmi; 3045 struct wmi_dfs_phyerr_offload_cmd *cmd; 3046 struct sk_buff *skb; 3047 int ret; 3048 3049 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 3050 if (!skb) 3051 return -ENOMEM; 3052 3053 cmd = (struct wmi_dfs_phyerr_offload_cmd *)skb->data; 3054 cmd->tlv_header = 3055 ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMD, 3056 sizeof(*cmd)); 3057 3058 cmd->pdev_id = cpu_to_le32(pdev_id); 3059 3060 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 3061 "WMI dfs phy err offload enable pdev id %d\n", pdev_id); 3062 3063 ret = ath12k_wmi_cmd_send(wmi, skb, 3064 WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMDID); 3065 if (ret) { 3066 ath12k_warn(ar->ab, 3067 "failed to send WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE cmd\n"); 3068 dev_kfree_skb(skb); 3069 } 3070 3071 return ret; 3072 } 3073 3074 int ath12k_wmi_set_bios_cmd(struct ath12k_base *ab, u32 param_id, 3075 const u8 *buf, size_t buf_len) 3076 { 3077 struct ath12k_wmi_base *wmi_ab = &ab->wmi_ab; 3078 struct wmi_pdev_set_bios_interface_cmd *cmd; 3079 struct wmi_tlv *tlv; 3080 struct sk_buff *skb; 3081 u8 *ptr; 3082 u32 len, len_aligned; 3083 int ret; 3084 3085 len_aligned = roundup(buf_len, sizeof(u32)); 3086 len = sizeof(*cmd) + TLV_HDR_SIZE + len_aligned; 3087 3088 skb = ath12k_wmi_alloc_skb(wmi_ab, len); 3089 if (!skb) 3090 return -ENOMEM; 3091 3092 cmd = (struct wmi_pdev_set_bios_interface_cmd *)skb->data; 3093 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_SET_BIOS_INTERFACE_CMD, 3094 sizeof(*cmd)); 3095 cmd->pdev_id = cpu_to_le32(WMI_PDEV_ID_SOC); 3096 cmd->param_type_id = cpu_to_le32(param_id); 3097 cmd->length = cpu_to_le32(buf_len); 3098 3099 ptr = skb->data + sizeof(*cmd); 3100 tlv = (struct wmi_tlv *)ptr; 3101 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, len_aligned); 3102 ptr += TLV_HDR_SIZE; 3103 memcpy(ptr, buf, buf_len); 3104 3105 ret = ath12k_wmi_cmd_send(&wmi_ab->wmi[0], 3106 skb, 3107 WMI_PDEV_SET_BIOS_INTERFACE_CMDID); 3108 if (ret) { 3109 ath12k_warn(ab, 3110 "failed to send WMI_PDEV_SET_BIOS_INTERFACE_CMDID parameter id %d: %d\n", 3111 param_id, ret); 3112 dev_kfree_skb(skb); 3113 } 3114 3115 return 0; 3116 } 3117 3118 int ath12k_wmi_set_bios_sar_cmd(struct ath12k_base *ab, const u8 *psar_table) 3119 { 3120 struct ath12k_wmi_base *wmi_ab = &ab->wmi_ab; 3121 struct wmi_pdev_set_bios_sar_table_cmd *cmd; 3122 struct wmi_tlv *tlv; 3123 struct sk_buff *skb; 3124 int ret; 3125 u8 *buf_ptr; 3126 u32 len, sar_table_len_aligned, sar_dbs_backoff_len_aligned; 3127 const u8 *psar_value = psar_table + ATH12K_ACPI_POWER_LIMIT_DATA_OFFSET; 3128 const u8 *pdbs_value = psar_table + ATH12K_ACPI_DBS_BACKOFF_DATA_OFFSET; 3129 3130 sar_table_len_aligned = roundup(ATH12K_ACPI_BIOS_SAR_TABLE_LEN, sizeof(u32)); 3131 sar_dbs_backoff_len_aligned = roundup(ATH12K_ACPI_BIOS_SAR_DBS_BACKOFF_LEN, 3132 sizeof(u32)); 3133 len = sizeof(*cmd) + TLV_HDR_SIZE + sar_table_len_aligned + 3134 TLV_HDR_SIZE + sar_dbs_backoff_len_aligned; 3135 3136 skb = ath12k_wmi_alloc_skb(wmi_ab, len); 3137 if (!skb) 3138 return -ENOMEM; 3139 3140 cmd = (struct wmi_pdev_set_bios_sar_table_cmd *)skb->data; 3141 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_SET_BIOS_SAR_TABLE_CMD, 3142 sizeof(*cmd)); 3143 cmd->pdev_id = cpu_to_le32(WMI_PDEV_ID_SOC); 3144 cmd->sar_len = cpu_to_le32(ATH12K_ACPI_BIOS_SAR_TABLE_LEN); 3145 cmd->dbs_backoff_len = cpu_to_le32(ATH12K_ACPI_BIOS_SAR_DBS_BACKOFF_LEN); 3146 3147 buf_ptr = skb->data + sizeof(*cmd); 3148 tlv = (struct wmi_tlv *)buf_ptr; 3149 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, 3150 sar_table_len_aligned); 3151 buf_ptr += TLV_HDR_SIZE; 3152 memcpy(buf_ptr, psar_value, ATH12K_ACPI_BIOS_SAR_TABLE_LEN); 3153 3154 buf_ptr += sar_table_len_aligned; 3155 tlv = (struct wmi_tlv *)buf_ptr; 3156 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, 3157 sar_dbs_backoff_len_aligned); 3158 buf_ptr += TLV_HDR_SIZE; 3159 memcpy(buf_ptr, pdbs_value, ATH12K_ACPI_BIOS_SAR_DBS_BACKOFF_LEN); 3160 3161 ret = ath12k_wmi_cmd_send(&wmi_ab->wmi[0], 3162 skb, 3163 WMI_PDEV_SET_BIOS_SAR_TABLE_CMDID); 3164 if (ret) { 3165 ath12k_warn(ab, 3166 "failed to send WMI_PDEV_SET_BIOS_INTERFACE_CMDID %d\n", 3167 ret); 3168 dev_kfree_skb(skb); 3169 } 3170 3171 return ret; 3172 } 3173 3174 int ath12k_wmi_set_bios_geo_cmd(struct ath12k_base *ab, const u8 *pgeo_table) 3175 { 3176 struct ath12k_wmi_base *wmi_ab = &ab->wmi_ab; 3177 struct wmi_pdev_set_bios_geo_table_cmd *cmd; 3178 struct wmi_tlv *tlv; 3179 struct sk_buff *skb; 3180 int ret; 3181 u8 *buf_ptr; 3182 u32 len, sar_geo_len_aligned; 3183 const u8 *pgeo_value = pgeo_table + ATH12K_ACPI_GEO_OFFSET_DATA_OFFSET; 3184 3185 sar_geo_len_aligned = roundup(ATH12K_ACPI_BIOS_SAR_GEO_OFFSET_LEN, sizeof(u32)); 3186 len = sizeof(*cmd) + TLV_HDR_SIZE + sar_geo_len_aligned; 3187 3188 skb = ath12k_wmi_alloc_skb(wmi_ab, len); 3189 if (!skb) 3190 return -ENOMEM; 3191 3192 cmd = (struct wmi_pdev_set_bios_geo_table_cmd *)skb->data; 3193 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_SET_BIOS_GEO_TABLE_CMD, 3194 sizeof(*cmd)); 3195 cmd->pdev_id = cpu_to_le32(WMI_PDEV_ID_SOC); 3196 cmd->geo_len = cpu_to_le32(ATH12K_ACPI_BIOS_SAR_GEO_OFFSET_LEN); 3197 3198 buf_ptr = skb->data + sizeof(*cmd); 3199 tlv = (struct wmi_tlv *)buf_ptr; 3200 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, sar_geo_len_aligned); 3201 buf_ptr += TLV_HDR_SIZE; 3202 memcpy(buf_ptr, pgeo_value, ATH12K_ACPI_BIOS_SAR_GEO_OFFSET_LEN); 3203 3204 ret = ath12k_wmi_cmd_send(&wmi_ab->wmi[0], 3205 skb, 3206 WMI_PDEV_SET_BIOS_GEO_TABLE_CMDID); 3207 if (ret) { 3208 ath12k_warn(ab, 3209 "failed to send WMI_PDEV_SET_BIOS_GEO_TABLE_CMDID %d\n", 3210 ret); 3211 dev_kfree_skb(skb); 3212 } 3213 3214 return ret; 3215 } 3216 3217 int ath12k_wmi_delba_send(struct ath12k *ar, u32 vdev_id, const u8 *mac, 3218 u32 tid, u32 initiator, u32 reason) 3219 { 3220 struct ath12k_wmi_pdev *wmi = ar->wmi; 3221 struct wmi_delba_send_cmd *cmd; 3222 struct sk_buff *skb; 3223 int ret; 3224 3225 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 3226 if (!skb) 3227 return -ENOMEM; 3228 3229 cmd = (struct wmi_delba_send_cmd *)skb->data; 3230 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_DELBA_SEND_CMD, 3231 sizeof(*cmd)); 3232 cmd->vdev_id = cpu_to_le32(vdev_id); 3233 ether_addr_copy(cmd->peer_macaddr.addr, mac); 3234 cmd->tid = cpu_to_le32(tid); 3235 cmd->initiator = cpu_to_le32(initiator); 3236 cmd->reasoncode = cpu_to_le32(reason); 3237 3238 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 3239 "wmi delba send vdev_id 0x%X mac_addr %pM tid %u initiator %u reason %u\n", 3240 vdev_id, mac, tid, initiator, reason); 3241 3242 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_DELBA_SEND_CMDID); 3243 3244 if (ret) { 3245 ath12k_warn(ar->ab, 3246 "failed to send WMI_DELBA_SEND_CMDID cmd\n"); 3247 dev_kfree_skb(skb); 3248 } 3249 3250 return ret; 3251 } 3252 3253 int ath12k_wmi_addba_set_resp(struct ath12k *ar, u32 vdev_id, const u8 *mac, 3254 u32 tid, u32 status) 3255 { 3256 struct ath12k_wmi_pdev *wmi = ar->wmi; 3257 struct wmi_addba_setresponse_cmd *cmd; 3258 struct sk_buff *skb; 3259 int ret; 3260 3261 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 3262 if (!skb) 3263 return -ENOMEM; 3264 3265 cmd = (struct wmi_addba_setresponse_cmd *)skb->data; 3266 cmd->tlv_header = 3267 ath12k_wmi_tlv_cmd_hdr(WMI_TAG_ADDBA_SETRESPONSE_CMD, 3268 sizeof(*cmd)); 3269 cmd->vdev_id = cpu_to_le32(vdev_id); 3270 ether_addr_copy(cmd->peer_macaddr.addr, mac); 3271 cmd->tid = cpu_to_le32(tid); 3272 cmd->statuscode = cpu_to_le32(status); 3273 3274 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 3275 "wmi addba set resp vdev_id 0x%X mac_addr %pM tid %u status %u\n", 3276 vdev_id, mac, tid, status); 3277 3278 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_ADDBA_SET_RESP_CMDID); 3279 3280 if (ret) { 3281 ath12k_warn(ar->ab, 3282 "failed to send WMI_ADDBA_SET_RESP_CMDID cmd\n"); 3283 dev_kfree_skb(skb); 3284 } 3285 3286 return ret; 3287 } 3288 3289 int ath12k_wmi_addba_send(struct ath12k *ar, u32 vdev_id, const u8 *mac, 3290 u32 tid, u32 buf_size) 3291 { 3292 struct ath12k_wmi_pdev *wmi = ar->wmi; 3293 struct wmi_addba_send_cmd *cmd; 3294 struct sk_buff *skb; 3295 int ret; 3296 3297 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 3298 if (!skb) 3299 return -ENOMEM; 3300 3301 cmd = (struct wmi_addba_send_cmd *)skb->data; 3302 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_ADDBA_SEND_CMD, 3303 sizeof(*cmd)); 3304 cmd->vdev_id = cpu_to_le32(vdev_id); 3305 ether_addr_copy(cmd->peer_macaddr.addr, mac); 3306 cmd->tid = cpu_to_le32(tid); 3307 cmd->buffersize = cpu_to_le32(buf_size); 3308 3309 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 3310 "wmi addba send vdev_id 0x%X mac_addr %pM tid %u bufsize %u\n", 3311 vdev_id, mac, tid, buf_size); 3312 3313 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_ADDBA_SEND_CMDID); 3314 3315 if (ret) { 3316 ath12k_warn(ar->ab, 3317 "failed to send WMI_ADDBA_SEND_CMDID cmd\n"); 3318 dev_kfree_skb(skb); 3319 } 3320 3321 return ret; 3322 } 3323 3324 int ath12k_wmi_addba_clear_resp(struct ath12k *ar, u32 vdev_id, const u8 *mac) 3325 { 3326 struct ath12k_wmi_pdev *wmi = ar->wmi; 3327 struct wmi_addba_clear_resp_cmd *cmd; 3328 struct sk_buff *skb; 3329 int ret; 3330 3331 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 3332 if (!skb) 3333 return -ENOMEM; 3334 3335 cmd = (struct wmi_addba_clear_resp_cmd *)skb->data; 3336 cmd->tlv_header = 3337 ath12k_wmi_tlv_cmd_hdr(WMI_TAG_ADDBA_CLEAR_RESP_CMD, 3338 sizeof(*cmd)); 3339 cmd->vdev_id = cpu_to_le32(vdev_id); 3340 ether_addr_copy(cmd->peer_macaddr.addr, mac); 3341 3342 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 3343 "wmi addba clear resp vdev_id 0x%X mac_addr %pM\n", 3344 vdev_id, mac); 3345 3346 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_ADDBA_CLEAR_RESP_CMDID); 3347 3348 if (ret) { 3349 ath12k_warn(ar->ab, 3350 "failed to send WMI_ADDBA_CLEAR_RESP_CMDID cmd\n"); 3351 dev_kfree_skb(skb); 3352 } 3353 3354 return ret; 3355 } 3356 3357 int ath12k_wmi_send_init_country_cmd(struct ath12k *ar, 3358 struct ath12k_wmi_init_country_arg *arg) 3359 { 3360 struct ath12k_wmi_pdev *wmi = ar->wmi; 3361 struct wmi_init_country_cmd *cmd; 3362 struct sk_buff *skb; 3363 int ret; 3364 3365 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 3366 if (!skb) 3367 return -ENOMEM; 3368 3369 cmd = (struct wmi_init_country_cmd *)skb->data; 3370 cmd->tlv_header = 3371 ath12k_wmi_tlv_cmd_hdr(WMI_TAG_SET_INIT_COUNTRY_CMD, 3372 sizeof(*cmd)); 3373 3374 cmd->pdev_id = cpu_to_le32(ar->pdev->pdev_id); 3375 3376 switch (arg->flags) { 3377 case ALPHA_IS_SET: 3378 cmd->init_cc_type = WMI_COUNTRY_INFO_TYPE_ALPHA; 3379 memcpy(&cmd->cc_info.alpha2, arg->cc_info.alpha2, 3); 3380 break; 3381 case CC_IS_SET: 3382 cmd->init_cc_type = cpu_to_le32(WMI_COUNTRY_INFO_TYPE_COUNTRY_CODE); 3383 cmd->cc_info.country_code = 3384 cpu_to_le32(arg->cc_info.country_code); 3385 break; 3386 case REGDMN_IS_SET: 3387 cmd->init_cc_type = cpu_to_le32(WMI_COUNTRY_INFO_TYPE_REGDOMAIN); 3388 cmd->cc_info.regdom_id = cpu_to_le32(arg->cc_info.regdom_id); 3389 break; 3390 default: 3391 ret = -EINVAL; 3392 goto out; 3393 } 3394 3395 ret = ath12k_wmi_cmd_send(wmi, skb, 3396 WMI_SET_INIT_COUNTRY_CMDID); 3397 3398 out: 3399 if (ret) { 3400 ath12k_warn(ar->ab, 3401 "failed to send WMI_SET_INIT_COUNTRY CMD :%d\n", 3402 ret); 3403 dev_kfree_skb(skb); 3404 } 3405 3406 return ret; 3407 } 3408 3409 int ath12k_wmi_send_set_current_country_cmd(struct ath12k *ar, 3410 struct wmi_set_current_country_arg *arg) 3411 { 3412 struct ath12k_wmi_pdev *wmi = ar->wmi; 3413 struct wmi_set_current_country_cmd *cmd; 3414 struct sk_buff *skb; 3415 int ret; 3416 3417 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 3418 if (!skb) 3419 return -ENOMEM; 3420 3421 cmd = (struct wmi_set_current_country_cmd *)skb->data; 3422 cmd->tlv_header = 3423 ath12k_wmi_tlv_cmd_hdr(WMI_TAG_SET_CURRENT_COUNTRY_CMD, 3424 sizeof(*cmd)); 3425 3426 cmd->pdev_id = cpu_to_le32(ar->pdev->pdev_id); 3427 memcpy(&cmd->new_alpha2, &arg->alpha2, sizeof(arg->alpha2)); 3428 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_SET_CURRENT_COUNTRY_CMDID); 3429 3430 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 3431 "set current country pdev id %d alpha2 %c%c\n", 3432 ar->pdev->pdev_id, 3433 arg->alpha2[0], 3434 arg->alpha2[1]); 3435 3436 if (ret) { 3437 ath12k_warn(ar->ab, 3438 "failed to send WMI_SET_CURRENT_COUNTRY_CMDID: %d\n", ret); 3439 dev_kfree_skb(skb); 3440 } 3441 3442 return ret; 3443 } 3444 3445 int 3446 ath12k_wmi_send_thermal_mitigation_cmd(struct ath12k *ar, 3447 struct ath12k_wmi_thermal_mitigation_arg *arg) 3448 { 3449 struct ath12k_wmi_therm_throt_level_config_param *lvl_conf; 3450 struct ath12k_wmi_therm_throt_config_request_cmd *cmd; 3451 struct ath12k_wmi_pdev *wmi = ar->wmi; 3452 struct wmi_tlv *tlv; 3453 struct sk_buff *skb; 3454 int i, ret, len; 3455 3456 len = sizeof(*cmd) + TLV_HDR_SIZE + (arg->num_levels * sizeof(*lvl_conf)); 3457 3458 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 3459 if (!skb) 3460 return -ENOMEM; 3461 3462 cmd = (struct ath12k_wmi_therm_throt_config_request_cmd *)skb->data; 3463 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_THERM_THROT_CONFIG_REQUEST, 3464 sizeof(*cmd)); 3465 cmd->pdev_id = cpu_to_le32(ar->pdev->pdev_id); 3466 cmd->enable = cpu_to_le32(1); 3467 cmd->dc = cpu_to_le32(100); 3468 cmd->dc_per_event = cpu_to_le32(0xffffffff); 3469 cmd->therm_throt_levels = cpu_to_le32(arg->num_levels); 3470 3471 tlv = (struct wmi_tlv *)(skb->data + sizeof(*cmd)); 3472 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, 3473 arg->num_levels * sizeof(*lvl_conf)); 3474 3475 lvl_conf = (struct ath12k_wmi_therm_throt_level_config_param *)tlv->value; 3476 3477 for (i = 0; i < arg->num_levels; i++) { 3478 lvl_conf->tlv_header = 3479 ath12k_wmi_tlv_cmd_hdr(WMI_TAG_THERM_THROT_LEVEL_CONFIG_INFO, 3480 sizeof(*lvl_conf)); 3481 3482 lvl_conf->temp_lwm = a_cpu_to_sle32(arg->levelconf[i].tmplwm); 3483 lvl_conf->temp_hwm = a_cpu_to_sle32(arg->levelconf[i].tmphwm); 3484 lvl_conf->dc_off_percent = cpu_to_le32(arg->levelconf[i].dcoffpercent); 3485 3486 if (test_bit(WMI_TLV_SERVICE_THERM_THROT_POUT_REDUCTION, 3487 ar->ab->wmi_ab.svc_map)) 3488 lvl_conf->pout_reduction_25db = 3489 cpu_to_le32(arg->levelconf[i].pout_reduction_db); 3490 3491 if (test_bit(WMI_TLV_SERVICE_THERM_THROT_TX_CHAIN_MASK, 3492 ar->ab->wmi_ab.svc_map)) 3493 lvl_conf->tx_chain_mask = cpu_to_le32(ar->cfg_tx_chainmask); 3494 3495 lvl_conf->duty_cycle = cpu_to_le32(ATH12K_THERMAL_DEFAULT_DUTY_CYCLE); 3496 lvl_conf++; 3497 } 3498 3499 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 3500 "WMI vdev set thermal throt pdev_id %u enable dc 100 dc_per_event 0xffffffff levels %d\n", 3501 ar->pdev->pdev_id, arg->num_levels); 3502 3503 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_THERM_THROT_SET_CONF_CMDID); 3504 if (ret) { 3505 ath12k_warn(ar->ab, 3506 "failed to send WMI_THERM_THROT_SET_CONF cmd: %d\n", 3507 ret); 3508 dev_kfree_skb(skb); 3509 } 3510 3511 return ret; 3512 } 3513 3514 int ath12k_wmi_send_11d_scan_start_cmd(struct ath12k *ar, 3515 struct wmi_11d_scan_start_arg *arg) 3516 { 3517 struct ath12k_wmi_pdev *wmi = ar->wmi; 3518 struct wmi_11d_scan_start_cmd *cmd; 3519 struct sk_buff *skb; 3520 int ret; 3521 3522 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 3523 if (!skb) 3524 return -ENOMEM; 3525 3526 cmd = (struct wmi_11d_scan_start_cmd *)skb->data; 3527 cmd->tlv_header = 3528 ath12k_wmi_tlv_cmd_hdr(WMI_TAG_11D_SCAN_START_CMD, 3529 sizeof(*cmd)); 3530 3531 cmd->vdev_id = cpu_to_le32(arg->vdev_id); 3532 cmd->scan_period_msec = cpu_to_le32(arg->scan_period_msec); 3533 cmd->start_interval_msec = cpu_to_le32(arg->start_interval_msec); 3534 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_11D_SCAN_START_CMDID); 3535 3536 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 3537 "send 11d scan start vdev id %d period %d ms internal %d ms\n", 3538 arg->vdev_id, arg->scan_period_msec, 3539 arg->start_interval_msec); 3540 3541 if (ret) { 3542 ath12k_warn(ar->ab, 3543 "failed to send WMI_11D_SCAN_START_CMDID: %d\n", ret); 3544 dev_kfree_skb(skb); 3545 } 3546 3547 return ret; 3548 } 3549 3550 int ath12k_wmi_send_11d_scan_stop_cmd(struct ath12k *ar, u32 vdev_id) 3551 { 3552 struct ath12k_wmi_pdev *wmi = ar->wmi; 3553 struct wmi_11d_scan_stop_cmd *cmd; 3554 struct sk_buff *skb; 3555 int ret; 3556 3557 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); 3558 if (!skb) 3559 return -ENOMEM; 3560 3561 cmd = (struct wmi_11d_scan_stop_cmd *)skb->data; 3562 cmd->tlv_header = 3563 ath12k_wmi_tlv_cmd_hdr(WMI_TAG_11D_SCAN_STOP_CMD, 3564 sizeof(*cmd)); 3565 3566 cmd->vdev_id = cpu_to_le32(vdev_id); 3567 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_11D_SCAN_STOP_CMDID); 3568 3569 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 3570 "send 11d scan stop vdev id %d\n", 3571 cmd->vdev_id); 3572 3573 if (ret) { 3574 ath12k_warn(ar->ab, 3575 "failed to send WMI_11D_SCAN_STOP_CMDID: %d\n", ret); 3576 dev_kfree_skb(skb); 3577 } 3578 3579 return ret; 3580 } 3581 3582 int 3583 ath12k_wmi_send_twt_enable_cmd(struct ath12k *ar, u32 pdev_id) 3584 { 3585 struct ath12k_wmi_pdev *wmi = ar->wmi; 3586 struct ath12k_base *ab = wmi->wmi_ab->ab; 3587 struct wmi_twt_enable_params_cmd *cmd; 3588 struct sk_buff *skb; 3589 int ret, len; 3590 3591 len = sizeof(*cmd); 3592 3593 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 3594 if (!skb) 3595 return -ENOMEM; 3596 3597 cmd = (struct wmi_twt_enable_params_cmd *)skb->data; 3598 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_TWT_ENABLE_CMD, 3599 len); 3600 cmd->pdev_id = cpu_to_le32(pdev_id); 3601 cmd->sta_cong_timer_ms = cpu_to_le32(ATH12K_TWT_DEF_STA_CONG_TIMER_MS); 3602 cmd->default_slot_size = cpu_to_le32(ATH12K_TWT_DEF_DEFAULT_SLOT_SIZE); 3603 cmd->congestion_thresh_setup = 3604 cpu_to_le32(ATH12K_TWT_DEF_CONGESTION_THRESH_SETUP); 3605 cmd->congestion_thresh_teardown = 3606 cpu_to_le32(ATH12K_TWT_DEF_CONGESTION_THRESH_TEARDOWN); 3607 cmd->congestion_thresh_critical = 3608 cpu_to_le32(ATH12K_TWT_DEF_CONGESTION_THRESH_CRITICAL); 3609 cmd->interference_thresh_teardown = 3610 cpu_to_le32(ATH12K_TWT_DEF_INTERFERENCE_THRESH_TEARDOWN); 3611 cmd->interference_thresh_setup = 3612 cpu_to_le32(ATH12K_TWT_DEF_INTERFERENCE_THRESH_SETUP); 3613 cmd->min_no_sta_setup = cpu_to_le32(ATH12K_TWT_DEF_MIN_NO_STA_SETUP); 3614 cmd->min_no_sta_teardown = cpu_to_le32(ATH12K_TWT_DEF_MIN_NO_STA_TEARDOWN); 3615 cmd->no_of_bcast_mcast_slots = 3616 cpu_to_le32(ATH12K_TWT_DEF_NO_OF_BCAST_MCAST_SLOTS); 3617 cmd->min_no_twt_slots = cpu_to_le32(ATH12K_TWT_DEF_MIN_NO_TWT_SLOTS); 3618 cmd->max_no_sta_twt = cpu_to_le32(ATH12K_TWT_DEF_MAX_NO_STA_TWT); 3619 cmd->mode_check_interval = cpu_to_le32(ATH12K_TWT_DEF_MODE_CHECK_INTERVAL); 3620 cmd->add_sta_slot_interval = cpu_to_le32(ATH12K_TWT_DEF_ADD_STA_SLOT_INTERVAL); 3621 cmd->remove_sta_slot_interval = 3622 cpu_to_le32(ATH12K_TWT_DEF_REMOVE_STA_SLOT_INTERVAL); 3623 /* TODO add MBSSID support */ 3624 cmd->mbss_support = 0; 3625 3626 ret = ath12k_wmi_cmd_send(wmi, skb, 3627 WMI_TWT_ENABLE_CMDID); 3628 if (ret) { 3629 ath12k_warn(ab, "Failed to send WMI_TWT_ENABLE_CMDID"); 3630 dev_kfree_skb(skb); 3631 } 3632 return ret; 3633 } 3634 3635 int 3636 ath12k_wmi_send_twt_disable_cmd(struct ath12k *ar, u32 pdev_id) 3637 { 3638 struct ath12k_wmi_pdev *wmi = ar->wmi; 3639 struct ath12k_base *ab = wmi->wmi_ab->ab; 3640 struct wmi_twt_disable_params_cmd *cmd; 3641 struct sk_buff *skb; 3642 int ret, len; 3643 3644 len = sizeof(*cmd); 3645 3646 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 3647 if (!skb) 3648 return -ENOMEM; 3649 3650 cmd = (struct wmi_twt_disable_params_cmd *)skb->data; 3651 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_TWT_DISABLE_CMD, 3652 len); 3653 cmd->pdev_id = cpu_to_le32(pdev_id); 3654 3655 ret = ath12k_wmi_cmd_send(wmi, skb, 3656 WMI_TWT_DISABLE_CMDID); 3657 if (ret) { 3658 ath12k_warn(ab, "Failed to send WMI_TWT_DISABLE_CMDID"); 3659 dev_kfree_skb(skb); 3660 } 3661 return ret; 3662 } 3663 3664 int 3665 ath12k_wmi_send_obss_spr_cmd(struct ath12k *ar, u32 vdev_id, 3666 struct ieee80211_he_obss_pd *he_obss_pd) 3667 { 3668 struct ath12k_wmi_pdev *wmi = ar->wmi; 3669 struct ath12k_base *ab = wmi->wmi_ab->ab; 3670 struct wmi_obss_spatial_reuse_params_cmd *cmd; 3671 struct sk_buff *skb; 3672 int ret, len; 3673 3674 len = sizeof(*cmd); 3675 3676 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 3677 if (!skb) 3678 return -ENOMEM; 3679 3680 cmd = (struct wmi_obss_spatial_reuse_params_cmd *)skb->data; 3681 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_OBSS_SPATIAL_REUSE_SET_CMD, 3682 len); 3683 cmd->vdev_id = cpu_to_le32(vdev_id); 3684 cmd->enable = cpu_to_le32(he_obss_pd->enable); 3685 cmd->obss_min = a_cpu_to_sle32(he_obss_pd->min_offset); 3686 cmd->obss_max = a_cpu_to_sle32(he_obss_pd->max_offset); 3687 3688 ret = ath12k_wmi_cmd_send(wmi, skb, 3689 WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID); 3690 if (ret) { 3691 ath12k_warn(ab, 3692 "Failed to send WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID"); 3693 dev_kfree_skb(skb); 3694 } 3695 return ret; 3696 } 3697 3698 u32 ath12k_wmi_build_obss_pd(const struct ath12k_wmi_obss_pd_arg *arg) 3699 { 3700 u32 param_val = 0; 3701 3702 param_val |= u32_encode_bits((u8)arg->srg_th, GENMASK(15, 8)); 3703 param_val |= u32_encode_bits((u8)arg->non_srg_th, GENMASK(7, 0)); 3704 3705 if (arg->srp_support) 3706 param_val |= ATH12K_OBSS_PD_THRESHOLD_IN_DBM; 3707 3708 if (arg->srg_enabled && arg->srp_support) 3709 param_val |= ATH12K_OBSS_PD_SRG_EN; 3710 3711 if (arg->non_srg_enabled) 3712 param_val |= ATH12K_OBSS_PD_NON_SRG_EN; 3713 3714 return param_val; 3715 } 3716 3717 static int ath12k_wmi_pdev_set_obss_bitmap(struct ath12k *ar, 3718 const struct wmi_pdev_set_obss_bitmap_arg *arg) 3719 { 3720 struct wmi_pdev_obss_pd_bitmap_cmd *cmd; 3721 struct ath12k_wmi_pdev *wmi = ar->wmi; 3722 const int len = sizeof(*cmd); 3723 struct sk_buff *skb; 3724 int ret; 3725 3726 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 3727 if (!skb) 3728 return -ENOMEM; 3729 3730 cmd = (struct wmi_pdev_obss_pd_bitmap_cmd *)skb->data; 3731 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(arg->tlv_tag, len); 3732 cmd->pdev_id = cpu_to_le32(arg->pdev_id); 3733 memcpy(cmd->bitmap, arg->bitmap, sizeof(cmd->bitmap)); 3734 3735 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 3736 "wmi set pdev %u %s %08x %08x\n", 3737 arg->pdev_id, arg->label, arg->bitmap[0], arg->bitmap[1]); 3738 3739 ret = ath12k_wmi_cmd_send(wmi, skb, arg->cmd_id); 3740 if (ret) { 3741 ath12k_warn(ar->ab, "failed to send %s: %d\n", arg->label, ret); 3742 dev_kfree_skb(skb); 3743 } 3744 3745 return ret; 3746 } 3747 3748 int ath12k_wmi_pdev_set_srg_bss_color_bitmap(struct ath12k *ar, 3749 u32 pdev_id, const u32 *bitmap) 3750 { 3751 struct wmi_pdev_set_obss_bitmap_arg arg = { 3752 .tlv_tag = WMI_TAG_PDEV_SRG_BSS_COLOR_BITMAP_CMD, 3753 .pdev_id = pdev_id, 3754 .cmd_id = WMI_PDEV_SET_SRG_BSS_COLOR_BITMAP_CMDID, 3755 .bitmap = bitmap, 3756 .label = "SRG bss color bitmap", 3757 }; 3758 3759 return ath12k_wmi_pdev_set_obss_bitmap(ar, &arg); 3760 } 3761 3762 int ath12k_wmi_pdev_set_srg_partial_bssid_bitmap(struct ath12k *ar, 3763 u32 pdev_id, const u32 *bitmap) 3764 { 3765 struct wmi_pdev_set_obss_bitmap_arg arg = { 3766 .tlv_tag = WMI_TAG_PDEV_SRG_PARTIAL_BSSID_BITMAP_CMD, 3767 .pdev_id = pdev_id, 3768 .cmd_id = WMI_PDEV_SET_SRG_PARTIAL_BSSID_BITMAP_CMDID, 3769 .bitmap = bitmap, 3770 .label = "SRG partial bssid bitmap", 3771 }; 3772 3773 return ath12k_wmi_pdev_set_obss_bitmap(ar, &arg); 3774 } 3775 3776 int ath12k_wmi_pdev_srg_obss_color_enable_bitmap(struct ath12k *ar, 3777 u32 pdev_id, const u32 *bitmap) 3778 { 3779 struct wmi_pdev_set_obss_bitmap_arg arg = { 3780 .tlv_tag = WMI_TAG_PDEV_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD, 3781 .pdev_id = pdev_id, 3782 .cmd_id = WMI_PDEV_SET_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID, 3783 .bitmap = bitmap, 3784 .label = "SRG obss color enable bitmap", 3785 }; 3786 3787 return ath12k_wmi_pdev_set_obss_bitmap(ar, &arg); 3788 } 3789 3790 int ath12k_wmi_pdev_srg_obss_bssid_enable_bitmap(struct ath12k *ar, 3791 u32 pdev_id, const u32 *bitmap) 3792 { 3793 struct wmi_pdev_set_obss_bitmap_arg arg = { 3794 .tlv_tag = WMI_TAG_PDEV_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD, 3795 .pdev_id = pdev_id, 3796 .cmd_id = WMI_PDEV_SET_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID, 3797 .bitmap = bitmap, 3798 .label = "SRG obss bssid enable bitmap", 3799 }; 3800 3801 return ath12k_wmi_pdev_set_obss_bitmap(ar, &arg); 3802 } 3803 3804 int ath12k_wmi_pdev_non_srg_obss_color_enable_bitmap(struct ath12k *ar, 3805 u32 pdev_id, const u32 *bitmap) 3806 { 3807 struct wmi_pdev_set_obss_bitmap_arg arg = { 3808 .tlv_tag = WMI_TAG_PDEV_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD, 3809 .pdev_id = pdev_id, 3810 .cmd_id = WMI_PDEV_SET_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID, 3811 .bitmap = bitmap, 3812 .label = "non SRG obss color enable bitmap", 3813 }; 3814 3815 return ath12k_wmi_pdev_set_obss_bitmap(ar, &arg); 3816 } 3817 3818 int ath12k_wmi_pdev_non_srg_obss_bssid_enable_bitmap(struct ath12k *ar, 3819 u32 pdev_id, const u32 *bitmap) 3820 { 3821 struct wmi_pdev_set_obss_bitmap_arg arg = { 3822 .tlv_tag = WMI_TAG_PDEV_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD, 3823 .pdev_id = pdev_id, 3824 .cmd_id = WMI_PDEV_SET_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID, 3825 .bitmap = bitmap, 3826 .label = "non SRG obss bssid enable bitmap", 3827 }; 3828 3829 return ath12k_wmi_pdev_set_obss_bitmap(ar, &arg); 3830 } 3831 3832 int ath12k_wmi_obss_color_cfg_cmd(struct ath12k *ar, u32 vdev_id, 3833 u8 bss_color, u32 period, 3834 bool enable) 3835 { 3836 struct ath12k_wmi_pdev *wmi = ar->wmi; 3837 struct ath12k_base *ab = wmi->wmi_ab->ab; 3838 struct wmi_obss_color_collision_cfg_params_cmd *cmd; 3839 struct sk_buff *skb; 3840 int ret, len; 3841 3842 len = sizeof(*cmd); 3843 3844 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 3845 if (!skb) 3846 return -ENOMEM; 3847 3848 cmd = (struct wmi_obss_color_collision_cfg_params_cmd *)skb->data; 3849 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_OBSS_COLOR_COLLISION_DET_CONFIG, 3850 len); 3851 cmd->vdev_id = cpu_to_le32(vdev_id); 3852 cmd->evt_type = enable ? cpu_to_le32(ATH12K_OBSS_COLOR_COLLISION_DETECTION) : 3853 cpu_to_le32(ATH12K_OBSS_COLOR_COLLISION_DETECTION_DISABLE); 3854 cmd->current_bss_color = cpu_to_le32(bss_color); 3855 cmd->detection_period_ms = cpu_to_le32(period); 3856 cmd->scan_period_ms = cpu_to_le32(ATH12K_BSS_COLOR_COLLISION_SCAN_PERIOD_MS); 3857 cmd->free_slot_expiry_time_ms = 0; 3858 cmd->flags = 0; 3859 3860 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 3861 "wmi_send_obss_color_collision_cfg id %d type %d bss_color %d detect_period %d scan_period %d\n", 3862 cmd->vdev_id, cmd->evt_type, cmd->current_bss_color, 3863 cmd->detection_period_ms, cmd->scan_period_ms); 3864 3865 ret = ath12k_wmi_cmd_send(wmi, skb, 3866 WMI_OBSS_COLOR_COLLISION_DET_CONFIG_CMDID); 3867 if (ret) { 3868 ath12k_warn(ab, "Failed to send WMI_OBSS_COLOR_COLLISION_DET_CONFIG_CMDID"); 3869 dev_kfree_skb(skb); 3870 } 3871 return ret; 3872 } 3873 3874 int ath12k_wmi_send_bss_color_change_enable_cmd(struct ath12k *ar, u32 vdev_id, 3875 bool enable) 3876 { 3877 struct ath12k_wmi_pdev *wmi = ar->wmi; 3878 struct ath12k_base *ab = wmi->wmi_ab->ab; 3879 struct wmi_bss_color_change_enable_params_cmd *cmd; 3880 struct sk_buff *skb; 3881 int ret, len; 3882 3883 len = sizeof(*cmd); 3884 3885 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 3886 if (!skb) 3887 return -ENOMEM; 3888 3889 cmd = (struct wmi_bss_color_change_enable_params_cmd *)skb->data; 3890 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_BSS_COLOR_CHANGE_ENABLE, 3891 len); 3892 cmd->vdev_id = cpu_to_le32(vdev_id); 3893 cmd->enable = enable ? cpu_to_le32(1) : 0; 3894 3895 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 3896 "wmi_send_bss_color_change_enable id %d enable %d\n", 3897 cmd->vdev_id, cmd->enable); 3898 3899 ret = ath12k_wmi_cmd_send(wmi, skb, 3900 WMI_BSS_COLOR_CHANGE_ENABLE_CMDID); 3901 if (ret) { 3902 ath12k_warn(ab, "Failed to send WMI_BSS_COLOR_CHANGE_ENABLE_CMDID"); 3903 dev_kfree_skb(skb); 3904 } 3905 return ret; 3906 } 3907 3908 int ath12k_wmi_fils_discovery_tmpl(struct ath12k *ar, u32 vdev_id, 3909 struct sk_buff *tmpl) 3910 { 3911 struct wmi_tlv *tlv; 3912 struct sk_buff *skb; 3913 void *ptr; 3914 int ret, len; 3915 size_t aligned_len; 3916 struct wmi_fils_discovery_tmpl_cmd *cmd; 3917 3918 aligned_len = roundup(tmpl->len, 4); 3919 len = sizeof(*cmd) + TLV_HDR_SIZE + aligned_len; 3920 3921 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 3922 "WMI vdev %i set FILS discovery template\n", vdev_id); 3923 3924 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, len); 3925 if (!skb) 3926 return -ENOMEM; 3927 3928 cmd = (struct wmi_fils_discovery_tmpl_cmd *)skb->data; 3929 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_FILS_DISCOVERY_TMPL_CMD, 3930 sizeof(*cmd)); 3931 cmd->vdev_id = cpu_to_le32(vdev_id); 3932 cmd->buf_len = cpu_to_le32(tmpl->len); 3933 ptr = skb->data + sizeof(*cmd); 3934 3935 tlv = ptr; 3936 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, aligned_len); 3937 memcpy(tlv->value, tmpl->data, tmpl->len); 3938 3939 ret = ath12k_wmi_cmd_send(ar->wmi, skb, WMI_FILS_DISCOVERY_TMPL_CMDID); 3940 if (ret) { 3941 ath12k_warn(ar->ab, 3942 "WMI vdev %i failed to send FILS discovery template command\n", 3943 vdev_id); 3944 dev_kfree_skb(skb); 3945 } 3946 return ret; 3947 } 3948 3949 int ath12k_wmi_probe_resp_tmpl(struct ath12k *ar, u32 vdev_id, 3950 struct sk_buff *tmpl) 3951 { 3952 struct wmi_probe_tmpl_cmd *cmd; 3953 struct ath12k_wmi_bcn_prb_info_params *probe_info; 3954 struct wmi_tlv *tlv; 3955 struct sk_buff *skb; 3956 void *ptr; 3957 int ret, len; 3958 size_t aligned_len = roundup(tmpl->len, 4); 3959 3960 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 3961 "WMI vdev %i set probe response template\n", vdev_id); 3962 3963 len = sizeof(*cmd) + sizeof(*probe_info) + TLV_HDR_SIZE + aligned_len; 3964 3965 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, len); 3966 if (!skb) 3967 return -ENOMEM; 3968 3969 cmd = (struct wmi_probe_tmpl_cmd *)skb->data; 3970 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PRB_TMPL_CMD, 3971 sizeof(*cmd)); 3972 cmd->vdev_id = cpu_to_le32(vdev_id); 3973 cmd->buf_len = cpu_to_le32(tmpl->len); 3974 3975 ptr = skb->data + sizeof(*cmd); 3976 3977 probe_info = ptr; 3978 len = sizeof(*probe_info); 3979 probe_info->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_BCN_PRB_INFO, 3980 len); 3981 probe_info->caps = 0; 3982 probe_info->erp = 0; 3983 3984 ptr += sizeof(*probe_info); 3985 3986 tlv = ptr; 3987 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, aligned_len); 3988 memcpy(tlv->value, tmpl->data, tmpl->len); 3989 3990 ret = ath12k_wmi_cmd_send(ar->wmi, skb, WMI_PRB_TMPL_CMDID); 3991 if (ret) { 3992 ath12k_warn(ar->ab, 3993 "WMI vdev %i failed to send probe response template command\n", 3994 vdev_id); 3995 dev_kfree_skb(skb); 3996 } 3997 return ret; 3998 } 3999 4000 int ath12k_wmi_fils_discovery(struct ath12k *ar, u32 vdev_id, u32 interval, 4001 bool unsol_bcast_probe_resp_enabled) 4002 { 4003 struct sk_buff *skb; 4004 int ret, len; 4005 struct wmi_fils_discovery_cmd *cmd; 4006 4007 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 4008 "WMI vdev %i set %s interval to %u TU\n", 4009 vdev_id, unsol_bcast_probe_resp_enabled ? 4010 "unsolicited broadcast probe response" : "FILS discovery", 4011 interval); 4012 4013 len = sizeof(*cmd); 4014 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, len); 4015 if (!skb) 4016 return -ENOMEM; 4017 4018 cmd = (struct wmi_fils_discovery_cmd *)skb->data; 4019 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_ENABLE_FILS_CMD, 4020 len); 4021 cmd->vdev_id = cpu_to_le32(vdev_id); 4022 cmd->interval = cpu_to_le32(interval); 4023 cmd->config = cpu_to_le32(unsol_bcast_probe_resp_enabled); 4024 4025 ret = ath12k_wmi_cmd_send(ar->wmi, skb, WMI_ENABLE_FILS_CMDID); 4026 if (ret) { 4027 ath12k_warn(ar->ab, 4028 "WMI vdev %i failed to send FILS discovery enable/disable command\n", 4029 vdev_id); 4030 dev_kfree_skb(skb); 4031 } 4032 return ret; 4033 } 4034 4035 static void 4036 ath12k_wmi_obss_color_collision_event(struct ath12k_base *ab, struct sk_buff *skb) 4037 { 4038 const struct wmi_obss_color_collision_event *ev; 4039 struct ath12k_link_vif *arvif; 4040 u32 vdev_id, evt_type; 4041 const void **tb; 4042 u64 bitmap; 4043 4044 tb = ath12k_wmi_tlv_parse(ab, skb); 4045 if (IS_ERR(tb)) { 4046 ath12k_warn(ab, "failed to parse OBSS color collision tlv %ld\n", 4047 PTR_ERR(tb)); 4048 return; 4049 } 4050 4051 ev = tb[WMI_TAG_OBSS_COLOR_COLLISION_EVT]; 4052 if (!ev) { 4053 ath12k_warn(ab, "failed to fetch OBSS color collision event\n"); 4054 return; 4055 } 4056 4057 vdev_id = le32_to_cpu(ev->vdev_id); 4058 evt_type = le32_to_cpu(ev->evt_type); 4059 bitmap = le64_to_cpu(ev->obss_color_bitmap); 4060 4061 guard(rcu)(); 4062 4063 arvif = ath12k_mac_get_arvif_by_vdev_id(ab, vdev_id); 4064 if (!arvif) { 4065 ath12k_warn(ab, "no arvif found for vdev %u in OBSS color collision event\n", 4066 vdev_id); 4067 return; 4068 } 4069 4070 switch (evt_type) { 4071 case WMI_BSS_COLOR_COLLISION_DETECTION: 4072 ieee80211_obss_color_collision_notify(arvif->ahvif->vif, 4073 bitmap, 4074 arvif->link_id); 4075 ath12k_dbg(ab, ATH12K_DBG_WMI, 4076 "obss color collision detected vdev %u event %d bitmap %016llx\n", 4077 vdev_id, evt_type, bitmap); 4078 break; 4079 case WMI_BSS_COLOR_COLLISION_DISABLE: 4080 case WMI_BSS_COLOR_FREE_SLOT_TIMER_EXPIRY: 4081 case WMI_BSS_COLOR_FREE_SLOT_AVAILABLE: 4082 break; 4083 default: 4084 ath12k_warn(ab, "unknown OBSS color collision event type %d\n", evt_type); 4085 } 4086 } 4087 4088 static void 4089 ath12k_fill_band_to_mac_param(struct ath12k_base *soc, 4090 struct ath12k_wmi_pdev_band_arg *arg) 4091 { 4092 u8 i; 4093 struct ath12k_wmi_hal_reg_capabilities_ext_arg *hal_reg_cap; 4094 struct ath12k_pdev *pdev; 4095 4096 for (i = 0; i < soc->num_radios; i++) { 4097 pdev = &soc->pdevs[i]; 4098 hal_reg_cap = &soc->hal_reg_cap[i]; 4099 arg[i].pdev_id = pdev->pdev_id; 4100 4101 switch (pdev->cap.supported_bands) { 4102 case WMI_HOST_WLAN_2GHZ_5GHZ_CAP: 4103 arg[i].start_freq = hal_reg_cap->low_2ghz_chan; 4104 arg[i].end_freq = hal_reg_cap->high_5ghz_chan; 4105 break; 4106 case WMI_HOST_WLAN_2GHZ_CAP: 4107 arg[i].start_freq = hal_reg_cap->low_2ghz_chan; 4108 arg[i].end_freq = hal_reg_cap->high_2ghz_chan; 4109 break; 4110 case WMI_HOST_WLAN_5GHZ_CAP: 4111 arg[i].start_freq = hal_reg_cap->low_5ghz_chan; 4112 arg[i].end_freq = hal_reg_cap->high_5ghz_chan; 4113 break; 4114 default: 4115 break; 4116 } 4117 } 4118 } 4119 4120 static void 4121 ath12k_wmi_copy_resource_config(struct ath12k_base *ab, 4122 struct ath12k_wmi_resource_config_params *wmi_cfg, 4123 struct ath12k_wmi_resource_config_arg *tg_cfg) 4124 { 4125 wmi_cfg->num_vdevs = cpu_to_le32(tg_cfg->num_vdevs); 4126 wmi_cfg->num_peers = cpu_to_le32(tg_cfg->num_peers); 4127 wmi_cfg->num_offload_peers = cpu_to_le32(tg_cfg->num_offload_peers); 4128 wmi_cfg->num_offload_reorder_buffs = 4129 cpu_to_le32(tg_cfg->num_offload_reorder_buffs); 4130 wmi_cfg->num_peer_keys = cpu_to_le32(tg_cfg->num_peer_keys); 4131 wmi_cfg->num_tids = cpu_to_le32(tg_cfg->num_tids); 4132 wmi_cfg->ast_skid_limit = cpu_to_le32(tg_cfg->ast_skid_limit); 4133 wmi_cfg->tx_chain_mask = cpu_to_le32(tg_cfg->tx_chain_mask); 4134 wmi_cfg->rx_chain_mask = cpu_to_le32(tg_cfg->rx_chain_mask); 4135 wmi_cfg->rx_timeout_pri[0] = cpu_to_le32(tg_cfg->rx_timeout_pri[0]); 4136 wmi_cfg->rx_timeout_pri[1] = cpu_to_le32(tg_cfg->rx_timeout_pri[1]); 4137 wmi_cfg->rx_timeout_pri[2] = cpu_to_le32(tg_cfg->rx_timeout_pri[2]); 4138 wmi_cfg->rx_timeout_pri[3] = cpu_to_le32(tg_cfg->rx_timeout_pri[3]); 4139 wmi_cfg->rx_decap_mode = cpu_to_le32(tg_cfg->rx_decap_mode); 4140 wmi_cfg->scan_max_pending_req = cpu_to_le32(tg_cfg->scan_max_pending_req); 4141 wmi_cfg->bmiss_offload_max_vdev = cpu_to_le32(tg_cfg->bmiss_offload_max_vdev); 4142 wmi_cfg->roam_offload_max_vdev = cpu_to_le32(tg_cfg->roam_offload_max_vdev); 4143 wmi_cfg->roam_offload_max_ap_profiles = 4144 cpu_to_le32(tg_cfg->roam_offload_max_ap_profiles); 4145 wmi_cfg->num_mcast_groups = cpu_to_le32(tg_cfg->num_mcast_groups); 4146 wmi_cfg->num_mcast_table_elems = cpu_to_le32(tg_cfg->num_mcast_table_elems); 4147 wmi_cfg->mcast2ucast_mode = cpu_to_le32(tg_cfg->mcast2ucast_mode); 4148 wmi_cfg->tx_dbg_log_size = cpu_to_le32(tg_cfg->tx_dbg_log_size); 4149 wmi_cfg->num_wds_entries = cpu_to_le32(tg_cfg->num_wds_entries); 4150 wmi_cfg->dma_burst_size = cpu_to_le32(tg_cfg->dma_burst_size); 4151 wmi_cfg->mac_aggr_delim = cpu_to_le32(tg_cfg->mac_aggr_delim); 4152 wmi_cfg->rx_skip_defrag_timeout_dup_detection_check = 4153 cpu_to_le32(tg_cfg->rx_skip_defrag_timeout_dup_detection_check); 4154 wmi_cfg->vow_config = cpu_to_le32(tg_cfg->vow_config); 4155 wmi_cfg->gtk_offload_max_vdev = cpu_to_le32(tg_cfg->gtk_offload_max_vdev); 4156 wmi_cfg->num_msdu_desc = cpu_to_le32(tg_cfg->num_msdu_desc); 4157 wmi_cfg->max_frag_entries = cpu_to_le32(tg_cfg->max_frag_entries); 4158 wmi_cfg->num_tdls_vdevs = cpu_to_le32(tg_cfg->num_tdls_vdevs); 4159 wmi_cfg->num_tdls_conn_table_entries = 4160 cpu_to_le32(tg_cfg->num_tdls_conn_table_entries); 4161 wmi_cfg->beacon_tx_offload_max_vdev = 4162 cpu_to_le32(tg_cfg->beacon_tx_offload_max_vdev); 4163 wmi_cfg->num_multicast_filter_entries = 4164 cpu_to_le32(tg_cfg->num_multicast_filter_entries); 4165 wmi_cfg->num_wow_filters = cpu_to_le32(tg_cfg->num_wow_filters); 4166 wmi_cfg->num_keep_alive_pattern = cpu_to_le32(tg_cfg->num_keep_alive_pattern); 4167 wmi_cfg->keep_alive_pattern_size = cpu_to_le32(tg_cfg->keep_alive_pattern_size); 4168 wmi_cfg->max_tdls_concurrent_sleep_sta = 4169 cpu_to_le32(tg_cfg->max_tdls_concurrent_sleep_sta); 4170 wmi_cfg->max_tdls_concurrent_buffer_sta = 4171 cpu_to_le32(tg_cfg->max_tdls_concurrent_buffer_sta); 4172 wmi_cfg->wmi_send_separate = cpu_to_le32(tg_cfg->wmi_send_separate); 4173 wmi_cfg->num_ocb_vdevs = cpu_to_le32(tg_cfg->num_ocb_vdevs); 4174 wmi_cfg->num_ocb_channels = cpu_to_le32(tg_cfg->num_ocb_channels); 4175 wmi_cfg->num_ocb_schedules = cpu_to_le32(tg_cfg->num_ocb_schedules); 4176 wmi_cfg->bpf_instruction_size = cpu_to_le32(tg_cfg->bpf_instruction_size); 4177 wmi_cfg->max_bssid_rx_filters = cpu_to_le32(tg_cfg->max_bssid_rx_filters); 4178 wmi_cfg->use_pdev_id = cpu_to_le32(tg_cfg->use_pdev_id); 4179 wmi_cfg->flag1 = cpu_to_le32(tg_cfg->atf_config | 4180 WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64 | 4181 WMI_RSRC_CFG_FLAG1_ACK_RSSI); 4182 wmi_cfg->peer_map_unmap_version = cpu_to_le32(tg_cfg->peer_map_unmap_version); 4183 wmi_cfg->sched_params = cpu_to_le32(tg_cfg->sched_params); 4184 wmi_cfg->twt_ap_pdev_count = cpu_to_le32(tg_cfg->twt_ap_pdev_count); 4185 wmi_cfg->twt_ap_sta_count = cpu_to_le32(tg_cfg->twt_ap_sta_count); 4186 wmi_cfg->flags2 = le32_encode_bits(tg_cfg->peer_metadata_ver, 4187 WMI_RSRC_CFG_FLAGS2_RX_PEER_METADATA_VERSION); 4188 wmi_cfg->host_service_flags = cpu_to_le32(tg_cfg->is_reg_cc_ext_event_supported << 4189 WMI_RSRC_CFG_HOST_SVC_FLAG_REG_CC_EXT_SUPPORT_BIT); 4190 if (ab->hw_params->reoq_lut_support) 4191 wmi_cfg->host_service_flags |= 4192 cpu_to_le32(1 << WMI_RSRC_CFG_HOST_SVC_FLAG_REO_QREF_SUPPORT_BIT); 4193 wmi_cfg->ema_max_vap_cnt = cpu_to_le32(tg_cfg->ema_max_vap_cnt); 4194 wmi_cfg->ema_max_profile_period = cpu_to_le32(tg_cfg->ema_max_profile_period); 4195 wmi_cfg->flags2 |= cpu_to_le32(WMI_RSRC_CFG_FLAGS2_CALC_NEXT_DTIM_COUNT_SET | 4196 WMI_RSRC_CFG_FLAGS2_FW_AST_INDICATION_DISABLE); 4197 4198 if (tg_cfg->is_wds_null_frame_supported) 4199 wmi_cfg->flags2 |= 4200 cpu_to_le32(WMI_RSRC_CFG_FLAGS2_WDS_NULL_FRAME_SUPPORT); 4201 } 4202 4203 static int ath12k_init_cmd_send(struct ath12k_wmi_pdev *wmi, 4204 struct ath12k_wmi_init_cmd_arg *arg) 4205 { 4206 struct ath12k_base *ab = wmi->wmi_ab->ab; 4207 struct sk_buff *skb; 4208 struct wmi_init_cmd *cmd; 4209 struct ath12k_wmi_resource_config_params *cfg; 4210 struct ath12k_wmi_pdev_set_hw_mode_cmd *hw_mode; 4211 struct ath12k_wmi_pdev_band_to_mac_params *band_to_mac; 4212 struct ath12k_wmi_host_mem_chunk_params *host_mem_chunks; 4213 struct wmi_tlv *tlv; 4214 size_t ret, len; 4215 void *ptr; 4216 u32 hw_mode_len = 0; 4217 u16 idx; 4218 4219 if (arg->hw_mode_id != WMI_HOST_HW_MODE_MAX) 4220 hw_mode_len = sizeof(*hw_mode) + TLV_HDR_SIZE + 4221 (arg->num_band_to_mac * sizeof(*band_to_mac)); 4222 4223 len = sizeof(*cmd) + TLV_HDR_SIZE + sizeof(*cfg) + hw_mode_len + 4224 (arg->num_mem_chunks ? (sizeof(*host_mem_chunks) * WMI_MAX_MEM_REQS) : 0); 4225 4226 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 4227 if (!skb) 4228 return -ENOMEM; 4229 4230 cmd = (struct wmi_init_cmd *)skb->data; 4231 4232 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_INIT_CMD, 4233 sizeof(*cmd)); 4234 4235 ptr = skb->data + sizeof(*cmd); 4236 cfg = ptr; 4237 4238 ath12k_wmi_copy_resource_config(ab, cfg, &arg->res_cfg); 4239 4240 cfg->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_RESOURCE_CONFIG, 4241 sizeof(*cfg)); 4242 4243 ptr += sizeof(*cfg); 4244 host_mem_chunks = ptr + TLV_HDR_SIZE; 4245 len = sizeof(struct ath12k_wmi_host_mem_chunk_params); 4246 4247 for (idx = 0; idx < arg->num_mem_chunks; ++idx) { 4248 host_mem_chunks[idx].tlv_header = 4249 ath12k_wmi_tlv_hdr(WMI_TAG_WLAN_HOST_MEMORY_CHUNK, 4250 len); 4251 4252 host_mem_chunks[idx].ptr = cpu_to_le32(arg->mem_chunks[idx].paddr); 4253 host_mem_chunks[idx].size = cpu_to_le32(arg->mem_chunks[idx].len); 4254 host_mem_chunks[idx].req_id = cpu_to_le32(arg->mem_chunks[idx].req_id); 4255 4256 ath12k_dbg(ab, ATH12K_DBG_WMI, 4257 "WMI host mem chunk req_id %d paddr 0x%llx len %d\n", 4258 arg->mem_chunks[idx].req_id, 4259 (u64)arg->mem_chunks[idx].paddr, 4260 arg->mem_chunks[idx].len); 4261 } 4262 cmd->num_host_mem_chunks = cpu_to_le32(arg->num_mem_chunks); 4263 len = sizeof(struct ath12k_wmi_host_mem_chunk_params) * arg->num_mem_chunks; 4264 4265 /* num_mem_chunks is zero */ 4266 tlv = ptr; 4267 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, len); 4268 ptr += TLV_HDR_SIZE + len; 4269 4270 if (arg->hw_mode_id != WMI_HOST_HW_MODE_MAX) { 4271 hw_mode = (struct ath12k_wmi_pdev_set_hw_mode_cmd *)ptr; 4272 hw_mode->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_SET_HW_MODE_CMD, 4273 sizeof(*hw_mode)); 4274 4275 hw_mode->hw_mode_index = cpu_to_le32(arg->hw_mode_id); 4276 hw_mode->num_band_to_mac = cpu_to_le32(arg->num_band_to_mac); 4277 4278 ptr += sizeof(*hw_mode); 4279 4280 len = arg->num_band_to_mac * sizeof(*band_to_mac); 4281 tlv = ptr; 4282 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, len); 4283 4284 ptr += TLV_HDR_SIZE; 4285 len = sizeof(*band_to_mac); 4286 4287 for (idx = 0; idx < arg->num_band_to_mac; idx++) { 4288 band_to_mac = (void *)ptr; 4289 4290 band_to_mac->tlv_header = 4291 ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_BAND_TO_MAC, 4292 len); 4293 band_to_mac->pdev_id = cpu_to_le32(arg->band_to_mac[idx].pdev_id); 4294 band_to_mac->start_freq = 4295 cpu_to_le32(arg->band_to_mac[idx].start_freq); 4296 band_to_mac->end_freq = 4297 cpu_to_le32(arg->band_to_mac[idx].end_freq); 4298 ptr += sizeof(*band_to_mac); 4299 } 4300 } 4301 4302 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_INIT_CMDID); 4303 if (ret) { 4304 ath12k_warn(ab, "failed to send WMI_INIT_CMDID\n"); 4305 dev_kfree_skb(skb); 4306 } 4307 4308 return ret; 4309 } 4310 4311 int ath12k_wmi_pdev_lro_cfg(struct ath12k *ar, 4312 int pdev_id) 4313 { 4314 struct ath12k_wmi_pdev_lro_config_cmd *cmd; 4315 struct sk_buff *skb; 4316 int ret; 4317 4318 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, sizeof(*cmd)); 4319 if (!skb) 4320 return -ENOMEM; 4321 4322 cmd = (struct ath12k_wmi_pdev_lro_config_cmd *)skb->data; 4323 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_LRO_INFO_CMD, 4324 sizeof(*cmd)); 4325 4326 get_random_bytes(cmd->th_4, sizeof(cmd->th_4)); 4327 get_random_bytes(cmd->th_6, sizeof(cmd->th_6)); 4328 4329 cmd->pdev_id = cpu_to_le32(pdev_id); 4330 4331 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 4332 "WMI lro cfg cmd pdev_id 0x%x\n", pdev_id); 4333 4334 ret = ath12k_wmi_cmd_send(ar->wmi, skb, WMI_LRO_CONFIG_CMDID); 4335 if (ret) { 4336 ath12k_warn(ar->ab, 4337 "failed to send lro cfg req wmi cmd\n"); 4338 dev_kfree_skb(skb); 4339 } 4340 4341 return ret; 4342 } 4343 4344 int ath12k_wmi_wait_for_service_ready(struct ath12k_base *ab) 4345 { 4346 unsigned long time_left; 4347 4348 time_left = wait_for_completion_timeout(&ab->wmi_ab.service_ready, 4349 WMI_SERVICE_READY_TIMEOUT_HZ); 4350 if (!time_left) 4351 return -ETIMEDOUT; 4352 4353 return 0; 4354 } 4355 4356 int ath12k_wmi_wait_for_unified_ready(struct ath12k_base *ab) 4357 { 4358 unsigned long time_left; 4359 4360 time_left = wait_for_completion_timeout(&ab->wmi_ab.unified_ready, 4361 WMI_SERVICE_READY_TIMEOUT_HZ); 4362 if (!time_left) 4363 return -ETIMEDOUT; 4364 4365 return 0; 4366 } 4367 4368 int ath12k_wmi_set_hw_mode(struct ath12k_base *ab, 4369 enum wmi_host_hw_mode_config_type mode) 4370 { 4371 struct ath12k_wmi_pdev_set_hw_mode_cmd *cmd; 4372 struct sk_buff *skb; 4373 struct ath12k_wmi_base *wmi_ab = &ab->wmi_ab; 4374 int len; 4375 int ret; 4376 4377 len = sizeof(*cmd); 4378 4379 skb = ath12k_wmi_alloc_skb(wmi_ab, len); 4380 if (!skb) 4381 return -ENOMEM; 4382 4383 cmd = (struct ath12k_wmi_pdev_set_hw_mode_cmd *)skb->data; 4384 4385 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_SET_HW_MODE_CMD, 4386 sizeof(*cmd)); 4387 4388 cmd->pdev_id = WMI_PDEV_ID_SOC; 4389 cmd->hw_mode_index = cpu_to_le32(mode); 4390 4391 ret = ath12k_wmi_cmd_send(&wmi_ab->wmi[0], skb, WMI_PDEV_SET_HW_MODE_CMDID); 4392 if (ret) { 4393 ath12k_warn(ab, "failed to send WMI_PDEV_SET_HW_MODE_CMDID\n"); 4394 dev_kfree_skb(skb); 4395 } 4396 4397 return ret; 4398 } 4399 4400 int ath12k_wmi_cmd_init(struct ath12k_base *ab) 4401 { 4402 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 4403 struct ath12k_wmi_base *wmi_ab = &ab->wmi_ab; 4404 struct ath12k_wmi_init_cmd_arg arg = {}; 4405 4406 if (test_bit(WMI_TLV_SERVICE_REG_CC_EXT_EVENT_SUPPORT, 4407 ab->wmi_ab.svc_map)) 4408 arg.res_cfg.is_reg_cc_ext_event_supported = true; 4409 4410 if (test_bit(WMI_TLV_SERVICE_WDS_NULL_FRAME_SUPPORT, ab->wmi_ab.svc_map)) 4411 arg.res_cfg.is_wds_null_frame_supported = true; 4412 4413 ab->hw_params->wmi_init(ab, &arg.res_cfg); 4414 ab->wow.wmi_conf_rx_decap_mode = arg.res_cfg.rx_decap_mode; 4415 4416 arg.num_mem_chunks = wmi_ab->num_mem_chunks; 4417 arg.hw_mode_id = wmi_ab->preferred_hw_mode; 4418 arg.mem_chunks = wmi_ab->mem_chunks; 4419 4420 if (ab->hw_params->single_pdev_only) 4421 arg.hw_mode_id = WMI_HOST_HW_MODE_MAX; 4422 4423 arg.num_band_to_mac = ab->num_radios; 4424 ath12k_fill_band_to_mac_param(ab, arg.band_to_mac); 4425 4426 dp->peer_metadata_ver = arg.res_cfg.peer_metadata_ver; 4427 4428 return ath12k_init_cmd_send(&wmi_ab->wmi[0], &arg); 4429 } 4430 4431 int ath12k_wmi_vdev_spectral_conf(struct ath12k *ar, 4432 struct ath12k_wmi_vdev_spectral_conf_arg *arg) 4433 { 4434 struct ath12k_wmi_vdev_spectral_conf_cmd *cmd; 4435 struct sk_buff *skb; 4436 int ret; 4437 4438 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, sizeof(*cmd)); 4439 if (!skb) 4440 return -ENOMEM; 4441 4442 cmd = (struct ath12k_wmi_vdev_spectral_conf_cmd *)skb->data; 4443 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_SPECTRAL_CONFIGURE_CMD, 4444 sizeof(*cmd)); 4445 cmd->vdev_id = cpu_to_le32(arg->vdev_id); 4446 cmd->scan_count = cpu_to_le32(arg->scan_count); 4447 cmd->scan_period = cpu_to_le32(arg->scan_period); 4448 cmd->scan_priority = cpu_to_le32(arg->scan_priority); 4449 cmd->scan_fft_size = cpu_to_le32(arg->scan_fft_size); 4450 cmd->scan_gc_ena = cpu_to_le32(arg->scan_gc_ena); 4451 cmd->scan_restart_ena = cpu_to_le32(arg->scan_restart_ena); 4452 cmd->scan_noise_floor_ref = cpu_to_le32(arg->scan_noise_floor_ref); 4453 cmd->scan_init_delay = cpu_to_le32(arg->scan_init_delay); 4454 cmd->scan_nb_tone_thr = cpu_to_le32(arg->scan_nb_tone_thr); 4455 cmd->scan_str_bin_thr = cpu_to_le32(arg->scan_str_bin_thr); 4456 cmd->scan_wb_rpt_mode = cpu_to_le32(arg->scan_wb_rpt_mode); 4457 cmd->scan_rssi_rpt_mode = cpu_to_le32(arg->scan_rssi_rpt_mode); 4458 cmd->scan_rssi_thr = cpu_to_le32(arg->scan_rssi_thr); 4459 cmd->scan_pwr_format = cpu_to_le32(arg->scan_pwr_format); 4460 cmd->scan_rpt_mode = cpu_to_le32(arg->scan_rpt_mode); 4461 cmd->scan_bin_scale = cpu_to_le32(arg->scan_bin_scale); 4462 cmd->scan_dbm_adj = cpu_to_le32(arg->scan_dbm_adj); 4463 cmd->scan_chn_mask = cpu_to_le32(arg->scan_chn_mask); 4464 4465 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 4466 "WMI spectral scan config cmd vdev_id 0x%x\n", 4467 arg->vdev_id); 4468 4469 ret = ath12k_wmi_cmd_send(ar->wmi, skb, 4470 WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID); 4471 if (ret) { 4472 ath12k_warn(ar->ab, 4473 "failed to send spectral scan config wmi cmd\n"); 4474 dev_kfree_skb(skb); 4475 } 4476 4477 return ret; 4478 } 4479 4480 int ath12k_wmi_vdev_spectral_enable(struct ath12k *ar, u32 vdev_id, 4481 u32 trigger, u32 enable) 4482 { 4483 struct ath12k_wmi_vdev_spectral_enable_cmd *cmd; 4484 struct sk_buff *skb; 4485 int ret; 4486 4487 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, sizeof(*cmd)); 4488 if (!skb) 4489 return -ENOMEM; 4490 4491 cmd = (struct ath12k_wmi_vdev_spectral_enable_cmd *)skb->data; 4492 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_SPECTRAL_ENABLE_CMD, 4493 sizeof(*cmd)); 4494 4495 cmd->vdev_id = cpu_to_le32(vdev_id); 4496 cmd->trigger_cmd = cpu_to_le32(trigger); 4497 cmd->enable_cmd = cpu_to_le32(enable); 4498 4499 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 4500 "WMI spectral enable cmd vdev id 0x%x\n", 4501 vdev_id); 4502 4503 ret = ath12k_wmi_cmd_send(ar->wmi, skb, 4504 WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID); 4505 if (ret) { 4506 ath12k_warn(ar->ab, 4507 "failed to send spectral enable wmi cmd\n"); 4508 dev_kfree_skb(skb); 4509 } 4510 4511 return ret; 4512 } 4513 4514 int ath12k_wmi_pdev_dma_ring_cfg(struct ath12k *ar, 4515 struct ath12k_wmi_pdev_dma_ring_cfg_arg *arg) 4516 { 4517 struct ath12k_wmi_pdev_dma_ring_cfg_req_cmd *cmd; 4518 struct sk_buff *skb; 4519 int ret; 4520 4521 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, sizeof(*cmd)); 4522 if (!skb) 4523 return -ENOMEM; 4524 4525 cmd = (struct ath12k_wmi_pdev_dma_ring_cfg_req_cmd *)skb->data; 4526 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_DMA_RING_CFG_REQ, 4527 sizeof(*cmd)); 4528 4529 cmd->pdev_id = cpu_to_le32(arg->pdev_id); 4530 cmd->module_id = cpu_to_le32(arg->module_id); 4531 cmd->base_paddr_lo = cpu_to_le32(arg->base_paddr_lo); 4532 cmd->base_paddr_hi = cpu_to_le32(arg->base_paddr_hi); 4533 cmd->head_idx_paddr_lo = cpu_to_le32(arg->head_idx_paddr_lo); 4534 cmd->head_idx_paddr_hi = cpu_to_le32(arg->head_idx_paddr_hi); 4535 cmd->tail_idx_paddr_lo = cpu_to_le32(arg->tail_idx_paddr_lo); 4536 cmd->tail_idx_paddr_hi = cpu_to_le32(arg->tail_idx_paddr_hi); 4537 cmd->num_elems = cpu_to_le32(arg->num_elems); 4538 cmd->buf_size = cpu_to_le32(arg->buf_size); 4539 cmd->num_resp_per_event = cpu_to_le32(arg->num_resp_per_event); 4540 cmd->event_timeout_ms = cpu_to_le32(arg->event_timeout_ms); 4541 4542 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 4543 "WMI DMA ring cfg req cmd pdev_id 0x%x\n", 4544 arg->pdev_id); 4545 4546 ret = ath12k_wmi_cmd_send(ar->wmi, skb, 4547 WMI_PDEV_DMA_RING_CFG_REQ_CMDID); 4548 if (ret) { 4549 ath12k_warn(ar->ab, 4550 "failed to send dma ring cfg req wmi cmd\n"); 4551 dev_kfree_skb(skb); 4552 } 4553 4554 return ret; 4555 } 4556 4557 static int ath12k_wmi_dma_buf_entry_parse(struct ath12k_base *soc, 4558 u16 tag, u16 len, 4559 const void *ptr, void *data) 4560 { 4561 struct ath12k_wmi_dma_buf_release_arg *arg = data; 4562 4563 if (tag != WMI_TAG_DMA_BUF_RELEASE_ENTRY) 4564 return -EPROTO; 4565 4566 if (arg->num_buf_entry >= le32_to_cpu(arg->fixed.num_buf_release_entry)) 4567 return -ENOBUFS; 4568 4569 arg->num_buf_entry++; 4570 return 0; 4571 } 4572 4573 static int ath12k_wmi_dma_buf_meta_parse(struct ath12k_base *soc, 4574 u16 tag, u16 len, 4575 const void *ptr, void *data) 4576 { 4577 struct ath12k_wmi_dma_buf_release_arg *arg = data; 4578 4579 if (tag != WMI_TAG_DMA_BUF_RELEASE_SPECTRAL_META_DATA) 4580 return -EPROTO; 4581 4582 if (arg->num_meta >= le32_to_cpu(arg->fixed.num_meta_data_entry)) 4583 return -ENOBUFS; 4584 4585 arg->num_meta++; 4586 4587 return 0; 4588 } 4589 4590 static int ath12k_wmi_dma_buf_parse(struct ath12k_base *ab, 4591 u16 tag, u16 len, 4592 const void *ptr, void *data) 4593 { 4594 struct ath12k_wmi_dma_buf_release_arg *arg = data; 4595 const struct ath12k_wmi_dma_buf_release_fixed_params *fixed; 4596 u32 pdev_id; 4597 int ret; 4598 4599 switch (tag) { 4600 case WMI_TAG_DMA_BUF_RELEASE: 4601 fixed = ptr; 4602 arg->fixed = *fixed; 4603 pdev_id = DP_HW2SW_MACID(le32_to_cpu(fixed->pdev_id)); 4604 arg->fixed.pdev_id = cpu_to_le32(pdev_id); 4605 break; 4606 case WMI_TAG_ARRAY_STRUCT: 4607 if (!arg->buf_entry_done) { 4608 arg->num_buf_entry = 0; 4609 arg->buf_entry = ptr; 4610 4611 ret = ath12k_wmi_tlv_iter(ab, ptr, len, 4612 ath12k_wmi_dma_buf_entry_parse, 4613 arg); 4614 if (ret) { 4615 ath12k_warn(ab, "failed to parse dma buf entry tlv %d\n", 4616 ret); 4617 return ret; 4618 } 4619 4620 arg->buf_entry_done = true; 4621 } else if (!arg->meta_data_done) { 4622 arg->num_meta = 0; 4623 arg->meta_data = ptr; 4624 4625 ret = ath12k_wmi_tlv_iter(ab, ptr, len, 4626 ath12k_wmi_dma_buf_meta_parse, 4627 arg); 4628 if (ret) { 4629 ath12k_warn(ab, "failed to parse dma buf meta tlv %d\n", 4630 ret); 4631 return ret; 4632 } 4633 4634 arg->meta_data_done = true; 4635 } 4636 break; 4637 default: 4638 break; 4639 } 4640 return 0; 4641 } 4642 4643 static void ath12k_wmi_pdev_dma_ring_buf_release_event(struct ath12k_base *ab, 4644 struct sk_buff *skb) 4645 { 4646 struct ath12k_wmi_dma_buf_release_arg arg = {}; 4647 struct ath12k_dbring_buf_release_event param; 4648 int ret; 4649 4650 ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, 4651 ath12k_wmi_dma_buf_parse, 4652 &arg); 4653 if (ret) { 4654 ath12k_warn(ab, "failed to parse dma buf release tlv %d\n", ret); 4655 return; 4656 } 4657 4658 param.fixed = arg.fixed; 4659 param.buf_entry = arg.buf_entry; 4660 param.num_buf_entry = arg.num_buf_entry; 4661 param.meta_data = arg.meta_data; 4662 param.num_meta = arg.num_meta; 4663 4664 ret = ath12k_dbring_buffer_release_event(ab, ¶m); 4665 if (ret) { 4666 ath12k_warn(ab, "failed to handle dma buf release event %d\n", ret); 4667 return; 4668 } 4669 } 4670 4671 static int ath12k_wmi_hw_mode_caps_parse(struct ath12k_base *soc, 4672 u16 tag, u16 len, 4673 const void *ptr, void *data) 4674 { 4675 struct ath12k_wmi_svc_rdy_ext_parse *svc_rdy_ext = data; 4676 struct ath12k_wmi_hw_mode_cap_params *hw_mode_cap; 4677 u32 phy_map = 0; 4678 4679 if (tag != WMI_TAG_HW_MODE_CAPABILITIES) 4680 return -EPROTO; 4681 4682 if (svc_rdy_ext->n_hw_mode_caps >= svc_rdy_ext->arg.num_hw_modes) 4683 return -ENOBUFS; 4684 4685 hw_mode_cap = container_of(ptr, struct ath12k_wmi_hw_mode_cap_params, 4686 hw_mode_id); 4687 svc_rdy_ext->n_hw_mode_caps++; 4688 4689 phy_map = le32_to_cpu(hw_mode_cap->phy_id_map); 4690 svc_rdy_ext->tot_phy_id += fls(phy_map); 4691 4692 return 0; 4693 } 4694 4695 static int ath12k_wmi_hw_mode_caps(struct ath12k_base *soc, 4696 u16 len, const void *ptr, void *data) 4697 { 4698 struct ath12k_svc_ext_info *svc_ext_info = &soc->wmi_ab.svc_ext_info; 4699 struct ath12k_wmi_svc_rdy_ext_parse *svc_rdy_ext = data; 4700 const struct ath12k_wmi_hw_mode_cap_params *hw_mode_caps; 4701 enum wmi_host_hw_mode_config_type mode, pref; 4702 u32 i; 4703 int ret; 4704 4705 svc_rdy_ext->n_hw_mode_caps = 0; 4706 svc_rdy_ext->hw_mode_caps = ptr; 4707 4708 ret = ath12k_wmi_tlv_iter(soc, ptr, len, 4709 ath12k_wmi_hw_mode_caps_parse, 4710 svc_rdy_ext); 4711 if (ret) { 4712 ath12k_warn(soc, "failed to parse tlv %d\n", ret); 4713 return ret; 4714 } 4715 4716 for (i = 0 ; i < svc_rdy_ext->n_hw_mode_caps; i++) { 4717 hw_mode_caps = &svc_rdy_ext->hw_mode_caps[i]; 4718 mode = le32_to_cpu(hw_mode_caps->hw_mode_id); 4719 4720 if (mode >= WMI_HOST_HW_MODE_MAX) 4721 continue; 4722 4723 pref = soc->wmi_ab.preferred_hw_mode; 4724 4725 if (ath12k_hw_mode_pri_map[mode] <= ath12k_hw_mode_pri_map[pref]) { 4726 svc_rdy_ext->pref_hw_mode_caps = *hw_mode_caps; 4727 soc->wmi_ab.preferred_hw_mode = mode; 4728 } 4729 } 4730 4731 svc_ext_info->num_hw_modes = svc_rdy_ext->n_hw_mode_caps; 4732 4733 ath12k_dbg(soc, ATH12K_DBG_WMI, "num hw modes %u preferred_hw_mode %d\n", 4734 svc_ext_info->num_hw_modes, soc->wmi_ab.preferred_hw_mode); 4735 4736 if (soc->wmi_ab.preferred_hw_mode == WMI_HOST_HW_MODE_MAX) 4737 return -EINVAL; 4738 4739 return 0; 4740 } 4741 4742 static int ath12k_wmi_mac_phy_caps_parse(struct ath12k_base *soc, 4743 u16 tag, u16 len, 4744 const void *ptr, void *data) 4745 { 4746 struct ath12k_wmi_svc_rdy_ext_parse *svc_rdy_ext = data; 4747 4748 if (tag != WMI_TAG_MAC_PHY_CAPABILITIES) 4749 return -EPROTO; 4750 4751 if (svc_rdy_ext->n_mac_phy_caps >= svc_rdy_ext->tot_phy_id) 4752 return -ENOBUFS; 4753 4754 len = min_t(u16, len, sizeof(struct ath12k_wmi_mac_phy_caps_params)); 4755 if (!svc_rdy_ext->n_mac_phy_caps) { 4756 svc_rdy_ext->mac_phy_caps = kzalloc((svc_rdy_ext->tot_phy_id) * len, 4757 GFP_ATOMIC); 4758 if (!svc_rdy_ext->mac_phy_caps) 4759 return -ENOMEM; 4760 } 4761 4762 memcpy(svc_rdy_ext->mac_phy_caps + svc_rdy_ext->n_mac_phy_caps, ptr, len); 4763 svc_rdy_ext->n_mac_phy_caps++; 4764 return 0; 4765 } 4766 4767 static int ath12k_wmi_ext_hal_reg_caps_parse(struct ath12k_base *soc, 4768 u16 tag, u16 len, 4769 const void *ptr, void *data) 4770 { 4771 struct ath12k_wmi_svc_rdy_ext_parse *svc_rdy_ext = data; 4772 4773 if (tag != WMI_TAG_HAL_REG_CAPABILITIES_EXT) 4774 return -EPROTO; 4775 4776 if (svc_rdy_ext->n_ext_hal_reg_caps >= svc_rdy_ext->arg.num_phy) 4777 return -ENOBUFS; 4778 4779 svc_rdy_ext->n_ext_hal_reg_caps++; 4780 return 0; 4781 } 4782 4783 static int ath12k_wmi_ext_hal_reg_caps(struct ath12k_base *soc, 4784 u16 len, const void *ptr, void *data) 4785 { 4786 struct ath12k_wmi_pdev *wmi_handle = &soc->wmi_ab.wmi[0]; 4787 struct ath12k_wmi_svc_rdy_ext_parse *svc_rdy_ext = data; 4788 struct ath12k_wmi_hal_reg_capabilities_ext_arg reg_cap; 4789 int ret; 4790 u32 i; 4791 4792 svc_rdy_ext->n_ext_hal_reg_caps = 0; 4793 svc_rdy_ext->ext_hal_reg_caps = ptr; 4794 ret = ath12k_wmi_tlv_iter(soc, ptr, len, 4795 ath12k_wmi_ext_hal_reg_caps_parse, 4796 svc_rdy_ext); 4797 if (ret) { 4798 ath12k_warn(soc, "failed to parse tlv %d\n", ret); 4799 return ret; 4800 } 4801 4802 for (i = 0; i < svc_rdy_ext->arg.num_phy; i++) { 4803 ret = ath12k_pull_reg_cap_svc_rdy_ext(wmi_handle, 4804 svc_rdy_ext->soc_hal_reg_caps, 4805 svc_rdy_ext->ext_hal_reg_caps, i, 4806 ®_cap); 4807 if (ret) { 4808 ath12k_warn(soc, "failed to extract reg cap %d\n", i); 4809 return ret; 4810 } 4811 4812 if (reg_cap.phy_id >= MAX_RADIOS) { 4813 ath12k_warn(soc, "unexpected phy id %u\n", reg_cap.phy_id); 4814 return -EINVAL; 4815 } 4816 4817 soc->hal_reg_cap[reg_cap.phy_id] = reg_cap; 4818 } 4819 return 0; 4820 } 4821 4822 static int ath12k_wmi_ext_soc_hal_reg_caps_parse(struct ath12k_base *soc, 4823 u16 len, const void *ptr, 4824 void *data) 4825 { 4826 struct ath12k_wmi_pdev *wmi_handle = &soc->wmi_ab.wmi[0]; 4827 struct ath12k_wmi_svc_rdy_ext_parse *svc_rdy_ext = data; 4828 u8 hw_mode_id = le32_to_cpu(svc_rdy_ext->pref_hw_mode_caps.hw_mode_id); 4829 u32 phy_id_map; 4830 int pdev_index = 0; 4831 int ret; 4832 4833 svc_rdy_ext->soc_hal_reg_caps = ptr; 4834 svc_rdy_ext->arg.num_phy = le32_to_cpu(svc_rdy_ext->soc_hal_reg_caps->num_phy); 4835 4836 soc->num_radios = 0; 4837 phy_id_map = le32_to_cpu(svc_rdy_ext->pref_hw_mode_caps.phy_id_map); 4838 soc->fw_pdev_count = 0; 4839 4840 while (phy_id_map && soc->num_radios < MAX_RADIOS) { 4841 ret = ath12k_pull_mac_phy_cap_svc_ready_ext(wmi_handle, 4842 svc_rdy_ext, 4843 hw_mode_id, soc->num_radios, 4844 &soc->pdevs[pdev_index]); 4845 if (ret) { 4846 ath12k_warn(soc, "failed to extract mac caps, idx :%d\n", 4847 soc->num_radios); 4848 return ret; 4849 } 4850 4851 soc->num_radios++; 4852 4853 /* For single_pdev_only targets, 4854 * save mac_phy capability in the same pdev 4855 */ 4856 if (soc->hw_params->single_pdev_only) 4857 pdev_index = 0; 4858 else 4859 pdev_index = soc->num_radios; 4860 4861 /* TODO: mac_phy_cap prints */ 4862 phy_id_map >>= 1; 4863 } 4864 4865 if (soc->hw_params->single_pdev_only) { 4866 soc->num_radios = 1; 4867 soc->pdevs[0].pdev_id = 0; 4868 } 4869 4870 return 0; 4871 } 4872 4873 static int ath12k_wmi_dma_ring_caps_parse(struct ath12k_base *soc, 4874 u16 tag, u16 len, 4875 const void *ptr, void *data) 4876 { 4877 struct ath12k_wmi_dma_ring_caps_parse *parse = data; 4878 4879 if (tag != WMI_TAG_DMA_RING_CAPABILITIES) 4880 return -EPROTO; 4881 4882 parse->n_dma_ring_caps++; 4883 return 0; 4884 } 4885 4886 static int ath12k_wmi_alloc_dbring_caps(struct ath12k_base *ab, 4887 u32 num_cap) 4888 { 4889 size_t sz; 4890 void *ptr; 4891 4892 sz = num_cap * sizeof(struct ath12k_dbring_cap); 4893 ptr = kzalloc(sz, GFP_ATOMIC); 4894 if (!ptr) 4895 return -ENOMEM; 4896 4897 ab->db_caps = ptr; 4898 ab->num_db_cap = num_cap; 4899 4900 return 0; 4901 } 4902 4903 static void ath12k_wmi_free_dbring_caps(struct ath12k_base *ab) 4904 { 4905 kfree(ab->db_caps); 4906 ab->db_caps = NULL; 4907 ab->num_db_cap = 0; 4908 } 4909 4910 static int ath12k_wmi_dma_ring_caps(struct ath12k_base *ab, 4911 u16 len, const void *ptr, void *data) 4912 { 4913 struct ath12k_wmi_dma_ring_caps_parse *dma_caps_parse = data; 4914 struct ath12k_wmi_dma_ring_caps_params *dma_caps; 4915 struct ath12k_dbring_cap *dir_buff_caps; 4916 int ret; 4917 u32 i; 4918 4919 dma_caps_parse->n_dma_ring_caps = 0; 4920 dma_caps = (struct ath12k_wmi_dma_ring_caps_params *)ptr; 4921 ret = ath12k_wmi_tlv_iter(ab, ptr, len, 4922 ath12k_wmi_dma_ring_caps_parse, 4923 dma_caps_parse); 4924 if (ret) { 4925 ath12k_warn(ab, "failed to parse dma ring caps tlv %d\n", ret); 4926 return ret; 4927 } 4928 4929 if (!dma_caps_parse->n_dma_ring_caps) 4930 return 0; 4931 4932 if (ab->num_db_cap) { 4933 ath12k_warn(ab, "Already processed, so ignoring dma ring caps\n"); 4934 return 0; 4935 } 4936 4937 ret = ath12k_wmi_alloc_dbring_caps(ab, dma_caps_parse->n_dma_ring_caps); 4938 if (ret) 4939 return ret; 4940 4941 dir_buff_caps = ab->db_caps; 4942 for (i = 0; i < dma_caps_parse->n_dma_ring_caps; i++) { 4943 if (le32_to_cpu(dma_caps[i].module_id) >= WMI_DIRECT_BUF_MAX) { 4944 ath12k_warn(ab, "Invalid module id %d\n", 4945 le32_to_cpu(dma_caps[i].module_id)); 4946 ret = -EINVAL; 4947 goto free_dir_buff; 4948 } 4949 4950 dir_buff_caps[i].id = le32_to_cpu(dma_caps[i].module_id); 4951 dir_buff_caps[i].pdev_id = 4952 DP_HW2SW_MACID(le32_to_cpu(dma_caps[i].pdev_id)); 4953 dir_buff_caps[i].min_elem = le32_to_cpu(dma_caps[i].min_elem); 4954 dir_buff_caps[i].min_buf_sz = le32_to_cpu(dma_caps[i].min_buf_sz); 4955 dir_buff_caps[i].min_buf_align = le32_to_cpu(dma_caps[i].min_buf_align); 4956 } 4957 4958 return 0; 4959 4960 free_dir_buff: 4961 ath12k_wmi_free_dbring_caps(ab); 4962 return ret; 4963 } 4964 4965 static void 4966 ath12k_wmi_save_mac_phy_info(struct ath12k_base *ab, 4967 const struct ath12k_wmi_mac_phy_caps_params *mac_phy_cap, 4968 struct ath12k_svc_ext_mac_phy_info *mac_phy_info) 4969 { 4970 mac_phy_info->phy_id = __le32_to_cpu(mac_phy_cap->phy_id); 4971 mac_phy_info->supported_bands = __le32_to_cpu(mac_phy_cap->supported_bands); 4972 mac_phy_info->hw_freq_range.low_2ghz_freq = 4973 __le32_to_cpu(mac_phy_cap->low_2ghz_chan_freq); 4974 mac_phy_info->hw_freq_range.high_2ghz_freq = 4975 __le32_to_cpu(mac_phy_cap->high_2ghz_chan_freq); 4976 mac_phy_info->hw_freq_range.low_5ghz_freq = 4977 __le32_to_cpu(mac_phy_cap->low_5ghz_chan_freq); 4978 mac_phy_info->hw_freq_range.high_5ghz_freq = 4979 __le32_to_cpu(mac_phy_cap->high_5ghz_chan_freq); 4980 } 4981 4982 static void 4983 ath12k_wmi_save_all_mac_phy_info(struct ath12k_base *ab, 4984 struct ath12k_wmi_svc_rdy_ext_parse *svc_rdy_ext) 4985 { 4986 struct ath12k_svc_ext_info *svc_ext_info = &ab->wmi_ab.svc_ext_info; 4987 const struct ath12k_wmi_mac_phy_caps_params *mac_phy_cap; 4988 const struct ath12k_wmi_hw_mode_cap_params *hw_mode_cap; 4989 struct ath12k_svc_ext_mac_phy_info *mac_phy_info; 4990 u32 hw_mode_id, phy_bit_map; 4991 u8 hw_idx; 4992 4993 mac_phy_info = &svc_ext_info->mac_phy_info[0]; 4994 mac_phy_cap = svc_rdy_ext->mac_phy_caps; 4995 4996 for (hw_idx = 0; hw_idx < svc_ext_info->num_hw_modes; hw_idx++) { 4997 hw_mode_cap = &svc_rdy_ext->hw_mode_caps[hw_idx]; 4998 hw_mode_id = __le32_to_cpu(hw_mode_cap->hw_mode_id); 4999 phy_bit_map = __le32_to_cpu(hw_mode_cap->phy_id_map); 5000 5001 while (phy_bit_map) { 5002 ath12k_wmi_save_mac_phy_info(ab, mac_phy_cap, mac_phy_info); 5003 mac_phy_info->hw_mode_config_type = 5004 le32_get_bits(hw_mode_cap->hw_mode_config_type, 5005 WMI_HW_MODE_CAP_CFG_TYPE); 5006 ath12k_dbg(ab, ATH12K_DBG_WMI, 5007 "hw_idx %u hw_mode_id %u hw_mode_config_type %u supported_bands %u phy_id %u 2 GHz [%u - %u] 5 GHz [%u - %u]\n", 5008 hw_idx, hw_mode_id, 5009 mac_phy_info->hw_mode_config_type, 5010 mac_phy_info->supported_bands, mac_phy_info->phy_id, 5011 mac_phy_info->hw_freq_range.low_2ghz_freq, 5012 mac_phy_info->hw_freq_range.high_2ghz_freq, 5013 mac_phy_info->hw_freq_range.low_5ghz_freq, 5014 mac_phy_info->hw_freq_range.high_5ghz_freq); 5015 5016 mac_phy_cap++; 5017 mac_phy_info++; 5018 5019 phy_bit_map >>= 1; 5020 } 5021 } 5022 } 5023 5024 static int ath12k_wmi_svc_rdy_ext_parse(struct ath12k_base *ab, 5025 u16 tag, u16 len, 5026 const void *ptr, void *data) 5027 { 5028 struct ath12k_wmi_pdev *wmi_handle = &ab->wmi_ab.wmi[0]; 5029 struct ath12k_wmi_svc_rdy_ext_parse *svc_rdy_ext = data; 5030 int ret; 5031 5032 switch (tag) { 5033 case WMI_TAG_SERVICE_READY_EXT_EVENT: 5034 ret = ath12k_pull_svc_ready_ext(wmi_handle, ptr, 5035 &svc_rdy_ext->arg); 5036 if (ret) { 5037 ath12k_warn(ab, "unable to extract ext params\n"); 5038 return ret; 5039 } 5040 break; 5041 5042 case WMI_TAG_SOC_MAC_PHY_HW_MODE_CAPS: 5043 svc_rdy_ext->hw_caps = ptr; 5044 svc_rdy_ext->arg.num_hw_modes = 5045 le32_to_cpu(svc_rdy_ext->hw_caps->num_hw_modes); 5046 break; 5047 5048 case WMI_TAG_SOC_HAL_REG_CAPABILITIES: 5049 ret = ath12k_wmi_ext_soc_hal_reg_caps_parse(ab, len, ptr, 5050 svc_rdy_ext); 5051 if (ret) 5052 return ret; 5053 break; 5054 5055 case WMI_TAG_ARRAY_STRUCT: 5056 if (!svc_rdy_ext->hw_mode_done) { 5057 ret = ath12k_wmi_hw_mode_caps(ab, len, ptr, svc_rdy_ext); 5058 if (ret) 5059 return ret; 5060 5061 svc_rdy_ext->hw_mode_done = true; 5062 } else if (!svc_rdy_ext->mac_phy_done) { 5063 svc_rdy_ext->n_mac_phy_caps = 0; 5064 ret = ath12k_wmi_tlv_iter(ab, ptr, len, 5065 ath12k_wmi_mac_phy_caps_parse, 5066 svc_rdy_ext); 5067 if (ret) { 5068 ath12k_warn(ab, "failed to parse tlv %d\n", ret); 5069 return ret; 5070 } 5071 5072 ath12k_wmi_save_all_mac_phy_info(ab, svc_rdy_ext); 5073 5074 svc_rdy_ext->mac_phy_done = true; 5075 } else if (!svc_rdy_ext->ext_hal_reg_done) { 5076 ret = ath12k_wmi_ext_hal_reg_caps(ab, len, ptr, svc_rdy_ext); 5077 if (ret) 5078 return ret; 5079 5080 svc_rdy_ext->ext_hal_reg_done = true; 5081 } else if (!svc_rdy_ext->mac_phy_chainmask_combo_done) { 5082 svc_rdy_ext->mac_phy_chainmask_combo_done = true; 5083 } else if (!svc_rdy_ext->mac_phy_chainmask_cap_done) { 5084 svc_rdy_ext->mac_phy_chainmask_cap_done = true; 5085 } else if (!svc_rdy_ext->oem_dma_ring_cap_done) { 5086 svc_rdy_ext->oem_dma_ring_cap_done = true; 5087 } else if (!svc_rdy_ext->dma_ring_cap_done) { 5088 ret = ath12k_wmi_dma_ring_caps(ab, len, ptr, 5089 &svc_rdy_ext->dma_caps_parse); 5090 if (ret) 5091 return ret; 5092 5093 svc_rdy_ext->dma_ring_cap_done = true; 5094 } 5095 break; 5096 5097 default: 5098 break; 5099 } 5100 return 0; 5101 } 5102 5103 static int ath12k_service_ready_ext_event(struct ath12k_base *ab, 5104 struct sk_buff *skb) 5105 { 5106 struct ath12k_wmi_svc_rdy_ext_parse svc_rdy_ext = { }; 5107 int ret; 5108 5109 ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, 5110 ath12k_wmi_svc_rdy_ext_parse, 5111 &svc_rdy_ext); 5112 if (ret) { 5113 ath12k_warn(ab, "failed to parse tlv %d\n", ret); 5114 goto err; 5115 } 5116 5117 if (!test_bit(WMI_TLV_SERVICE_EXT2_MSG, ab->wmi_ab.svc_map)) 5118 complete(&ab->wmi_ab.service_ready); 5119 5120 kfree(svc_rdy_ext.mac_phy_caps); 5121 return 0; 5122 5123 err: 5124 kfree(svc_rdy_ext.mac_phy_caps); 5125 ath12k_wmi_free_dbring_caps(ab); 5126 return ret; 5127 } 5128 5129 static int ath12k_pull_svc_ready_ext2(struct ath12k_wmi_pdev *wmi_handle, 5130 const void *ptr, 5131 struct ath12k_wmi_svc_rdy_ext2_arg *arg) 5132 { 5133 const struct wmi_service_ready_ext2_event *ev = ptr; 5134 5135 if (!ev) 5136 return -EINVAL; 5137 5138 arg->reg_db_version = le32_to_cpu(ev->reg_db_version); 5139 arg->hw_min_max_tx_power_2ghz = le32_to_cpu(ev->hw_min_max_tx_power_2ghz); 5140 arg->hw_min_max_tx_power_5ghz = le32_to_cpu(ev->hw_min_max_tx_power_5ghz); 5141 arg->chwidth_num_peer_caps = le32_to_cpu(ev->chwidth_num_peer_caps); 5142 arg->preamble_puncture_bw = le32_to_cpu(ev->preamble_puncture_bw); 5143 arg->max_user_per_ppdu_ofdma = le32_to_cpu(ev->max_user_per_ppdu_ofdma); 5144 arg->max_user_per_ppdu_mumimo = le32_to_cpu(ev->max_user_per_ppdu_mumimo); 5145 arg->target_cap_flags = le32_to_cpu(ev->target_cap_flags); 5146 return 0; 5147 } 5148 5149 static void ath12k_wmi_eht_caps_parse(struct ath12k_pdev *pdev, u32 band, 5150 const __le32 cap_mac_info[], 5151 const __le32 cap_phy_info[], 5152 const __le32 supp_mcs[], 5153 const struct ath12k_wmi_ppe_threshold_params *ppet, 5154 __le32 cap_info_internal) 5155 { 5156 struct ath12k_band_cap *cap_band = &pdev->cap.band[band]; 5157 u32 support_320mhz; 5158 u8 i; 5159 5160 if (band == NL80211_BAND_6GHZ) 5161 support_320mhz = cap_band->eht_cap_phy_info[0] & 5162 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 5163 5164 for (i = 0; i < WMI_MAX_EHTCAP_MAC_SIZE; i++) 5165 cap_band->eht_cap_mac_info[i] = le32_to_cpu(cap_mac_info[i]); 5166 5167 for (i = 0; i < WMI_MAX_EHTCAP_PHY_SIZE; i++) 5168 cap_band->eht_cap_phy_info[i] = le32_to_cpu(cap_phy_info[i]); 5169 5170 if (band == NL80211_BAND_6GHZ) 5171 cap_band->eht_cap_phy_info[0] |= support_320mhz; 5172 5173 cap_band->eht_mcs_20_only = le32_to_cpu(supp_mcs[0]); 5174 cap_band->eht_mcs_80 = le32_to_cpu(supp_mcs[1]); 5175 if (band != NL80211_BAND_2GHZ) { 5176 cap_band->eht_mcs_160 = le32_to_cpu(supp_mcs[2]); 5177 cap_band->eht_mcs_320 = le32_to_cpu(supp_mcs[3]); 5178 } 5179 5180 cap_band->eht_ppet.numss_m1 = le32_to_cpu(ppet->numss_m1); 5181 cap_band->eht_ppet.ru_bit_mask = le32_to_cpu(ppet->ru_info); 5182 for (i = 0; i < WMI_MAX_NUM_SS; i++) 5183 cap_band->eht_ppet.ppet16_ppet8_ru3_ru0[i] = 5184 le32_to_cpu(ppet->ppet16_ppet8_ru3_ru0[i]); 5185 5186 cap_band->eht_cap_info_internal = le32_to_cpu(cap_info_internal); 5187 } 5188 5189 static int 5190 ath12k_wmi_tlv_mac_phy_caps_ext_parse(struct ath12k_base *ab, 5191 const struct ath12k_wmi_caps_ext_params *caps, 5192 struct ath12k_pdev *pdev) 5193 { 5194 u32 bands; 5195 int i; 5196 5197 if (ab->hw_params->single_pdev_only) { 5198 for (i = 0; i < ab->fw_pdev_count; i++) { 5199 struct ath12k_fw_pdev *fw_pdev = &ab->fw_pdev[i]; 5200 5201 if (fw_pdev->pdev_id == ath12k_wmi_caps_ext_get_pdev_id(caps) && 5202 fw_pdev->phy_id == le32_to_cpu(caps->phy_id)) { 5203 bands = fw_pdev->supported_bands; 5204 break; 5205 } 5206 } 5207 5208 if (i == ab->fw_pdev_count) 5209 return -EINVAL; 5210 } else { 5211 bands = pdev->cap.supported_bands; 5212 } 5213 5214 if (bands & WMI_HOST_WLAN_2GHZ_CAP) { 5215 ath12k_wmi_eht_caps_parse(pdev, NL80211_BAND_2GHZ, 5216 caps->eht_cap_mac_info_2ghz, 5217 caps->eht_cap_phy_info_2ghz, 5218 caps->eht_supp_mcs_ext_2ghz, 5219 &caps->eht_ppet_2ghz, 5220 caps->eht_cap_info_internal); 5221 } 5222 5223 if (bands & WMI_HOST_WLAN_5GHZ_CAP) { 5224 ath12k_wmi_eht_caps_parse(pdev, NL80211_BAND_5GHZ, 5225 caps->eht_cap_mac_info_5ghz, 5226 caps->eht_cap_phy_info_5ghz, 5227 caps->eht_supp_mcs_ext_5ghz, 5228 &caps->eht_ppet_5ghz, 5229 caps->eht_cap_info_internal); 5230 5231 ath12k_wmi_eht_caps_parse(pdev, NL80211_BAND_6GHZ, 5232 caps->eht_cap_mac_info_5ghz, 5233 caps->eht_cap_phy_info_5ghz, 5234 caps->eht_supp_mcs_ext_5ghz, 5235 &caps->eht_ppet_5ghz, 5236 caps->eht_cap_info_internal); 5237 } 5238 5239 pdev->cap.eml_cap = le32_to_cpu(caps->eml_capability); 5240 pdev->cap.mld_cap = le32_to_cpu(caps->mld_capability); 5241 5242 return 0; 5243 } 5244 5245 static int ath12k_wmi_tlv_mac_phy_caps_ext(struct ath12k_base *ab, u16 tag, 5246 u16 len, const void *ptr, 5247 void *data) 5248 { 5249 const struct ath12k_wmi_caps_ext_params *caps = ptr; 5250 struct ath12k_band_cap *cap_band; 5251 u32 support_320mhz; 5252 int i = 0, ret; 5253 5254 if (tag != WMI_TAG_MAC_PHY_CAPABILITIES_EXT) 5255 return -EPROTO; 5256 5257 if (ab->hw_params->single_pdev_only) { 5258 if (caps->hw_mode_id == WMI_HOST_HW_MODE_SINGLE) { 5259 support_320mhz = le32_to_cpu(caps->eht_cap_phy_info_5ghz[0]) & 5260 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 5261 cap_band = &ab->pdevs[0].cap.band[NL80211_BAND_6GHZ]; 5262 cap_band->eht_cap_phy_info[0] |= support_320mhz; 5263 } 5264 5265 if (ab->wmi_ab.preferred_hw_mode != le32_to_cpu(caps->hw_mode_id)) 5266 return 0; 5267 } else { 5268 for (i = 0; i < ab->num_radios; i++) { 5269 if (ab->pdevs[i].pdev_id == 5270 ath12k_wmi_caps_ext_get_pdev_id(caps)) 5271 break; 5272 } 5273 5274 if (i == ab->num_radios) 5275 return -EINVAL; 5276 } 5277 5278 ret = ath12k_wmi_tlv_mac_phy_caps_ext_parse(ab, caps, &ab->pdevs[i]); 5279 if (ret) { 5280 ath12k_warn(ab, 5281 "failed to parse extended MAC PHY capabilities for pdev %d: %d\n", 5282 ret, ab->pdevs[i].pdev_id); 5283 return ret; 5284 } 5285 5286 return 0; 5287 } 5288 5289 static void 5290 ath12k_wmi_update_freq_info(struct ath12k_base *ab, 5291 struct ath12k_svc_ext_mac_phy_info *mac_cap, 5292 enum ath12k_hw_mode mode, 5293 u32 phy_id) 5294 { 5295 struct ath12k_hw_mode_info *hw_mode_info = &ab->wmi_ab.hw_mode_info; 5296 struct ath12k_hw_mode_freq_range_arg *mac_range; 5297 5298 mac_range = &hw_mode_info->freq_range_caps[mode][phy_id]; 5299 5300 if (mac_cap->supported_bands & WMI_HOST_WLAN_2GHZ_CAP) { 5301 mac_range->low_2ghz_freq = max_t(u32, 5302 mac_cap->hw_freq_range.low_2ghz_freq, 5303 ATH12K_MIN_2GHZ_FREQ); 5304 mac_range->high_2ghz_freq = mac_cap->hw_freq_range.high_2ghz_freq ? 5305 min_t(u32, 5306 mac_cap->hw_freq_range.high_2ghz_freq, 5307 ATH12K_MAX_2GHZ_FREQ) : 5308 ATH12K_MAX_2GHZ_FREQ; 5309 } 5310 5311 if (mac_cap->supported_bands & WMI_HOST_WLAN_5GHZ_CAP) { 5312 mac_range->low_5ghz_freq = max_t(u32, 5313 mac_cap->hw_freq_range.low_5ghz_freq, 5314 ATH12K_MIN_5GHZ_FREQ); 5315 mac_range->high_5ghz_freq = mac_cap->hw_freq_range.high_5ghz_freq ? 5316 min_t(u32, 5317 mac_cap->hw_freq_range.high_5ghz_freq, 5318 ATH12K_MAX_6GHZ_FREQ) : 5319 ATH12K_MAX_6GHZ_FREQ; 5320 } 5321 } 5322 5323 static bool 5324 ath12k_wmi_all_phy_range_updated(struct ath12k_base *ab, 5325 enum ath12k_hw_mode hwmode) 5326 { 5327 struct ath12k_hw_mode_info *hw_mode_info = &ab->wmi_ab.hw_mode_info; 5328 struct ath12k_hw_mode_freq_range_arg *mac_range; 5329 u8 phy_id; 5330 5331 for (phy_id = 0; phy_id < MAX_RADIOS; phy_id++) { 5332 mac_range = &hw_mode_info->freq_range_caps[hwmode][phy_id]; 5333 /* modify SBS/DBS range only when both phy for DBS are filled */ 5334 if (!mac_range->low_2ghz_freq && !mac_range->low_5ghz_freq) 5335 return false; 5336 } 5337 5338 return true; 5339 } 5340 5341 static void ath12k_wmi_update_dbs_freq_info(struct ath12k_base *ab) 5342 { 5343 struct ath12k_hw_mode_info *hw_mode_info = &ab->wmi_ab.hw_mode_info; 5344 struct ath12k_hw_mode_freq_range_arg *mac_range; 5345 u8 phy_id; 5346 5347 mac_range = hw_mode_info->freq_range_caps[ATH12K_HW_MODE_DBS]; 5348 /* Reset 5 GHz range for shared mac for DBS */ 5349 for (phy_id = 0; phy_id < MAX_RADIOS; phy_id++) { 5350 if (mac_range[phy_id].low_2ghz_freq && 5351 mac_range[phy_id].low_5ghz_freq) { 5352 mac_range[phy_id].low_5ghz_freq = 0; 5353 mac_range[phy_id].high_5ghz_freq = 0; 5354 } 5355 } 5356 } 5357 5358 static u32 5359 ath12k_wmi_get_highest_5ghz_freq_from_range(struct ath12k_hw_mode_freq_range_arg *range) 5360 { 5361 u32 highest_freq = 0; 5362 u8 phy_id; 5363 5364 for (phy_id = 0; phy_id < MAX_RADIOS; phy_id++) { 5365 if (range[phy_id].high_5ghz_freq > highest_freq) 5366 highest_freq = range[phy_id].high_5ghz_freq; 5367 } 5368 5369 return highest_freq ? highest_freq : ATH12K_MAX_6GHZ_FREQ; 5370 } 5371 5372 static u32 5373 ath12k_wmi_get_lowest_5ghz_freq_from_range(struct ath12k_hw_mode_freq_range_arg *range) 5374 { 5375 u32 lowest_freq = 0; 5376 u8 phy_id; 5377 5378 for (phy_id = 0; phy_id < MAX_RADIOS; phy_id++) { 5379 if ((!lowest_freq && range[phy_id].low_5ghz_freq) || 5380 range[phy_id].low_5ghz_freq < lowest_freq) 5381 lowest_freq = range[phy_id].low_5ghz_freq; 5382 } 5383 5384 return lowest_freq ? lowest_freq : ATH12K_MIN_5GHZ_FREQ; 5385 } 5386 5387 static void 5388 ath12k_wmi_fill_upper_share_sbs_freq(struct ath12k_base *ab, 5389 u16 sbs_range_sep, 5390 struct ath12k_hw_mode_freq_range_arg *ref_freq) 5391 { 5392 struct ath12k_hw_mode_info *hw_mode_info = &ab->wmi_ab.hw_mode_info; 5393 struct ath12k_hw_mode_freq_range_arg *upper_sbs_freq_range; 5394 u8 phy_id; 5395 5396 upper_sbs_freq_range = 5397 hw_mode_info->freq_range_caps[ATH12K_HW_MODE_SBS_UPPER_SHARE]; 5398 5399 for (phy_id = 0; phy_id < MAX_RADIOS; phy_id++) { 5400 upper_sbs_freq_range[phy_id].low_2ghz_freq = 5401 ref_freq[phy_id].low_2ghz_freq; 5402 upper_sbs_freq_range[phy_id].high_2ghz_freq = 5403 ref_freq[phy_id].high_2ghz_freq; 5404 5405 /* update for shared mac */ 5406 if (upper_sbs_freq_range[phy_id].low_2ghz_freq) { 5407 upper_sbs_freq_range[phy_id].low_5ghz_freq = sbs_range_sep + 10; 5408 upper_sbs_freq_range[phy_id].high_5ghz_freq = 5409 ath12k_wmi_get_highest_5ghz_freq_from_range(ref_freq); 5410 } else { 5411 upper_sbs_freq_range[phy_id].low_5ghz_freq = 5412 ath12k_wmi_get_lowest_5ghz_freq_from_range(ref_freq); 5413 upper_sbs_freq_range[phy_id].high_5ghz_freq = sbs_range_sep; 5414 } 5415 } 5416 } 5417 5418 static void 5419 ath12k_wmi_fill_lower_share_sbs_freq(struct ath12k_base *ab, 5420 u16 sbs_range_sep, 5421 struct ath12k_hw_mode_freq_range_arg *ref_freq) 5422 { 5423 struct ath12k_hw_mode_info *hw_mode_info = &ab->wmi_ab.hw_mode_info; 5424 struct ath12k_hw_mode_freq_range_arg *lower_sbs_freq_range; 5425 u8 phy_id; 5426 5427 lower_sbs_freq_range = 5428 hw_mode_info->freq_range_caps[ATH12K_HW_MODE_SBS_LOWER_SHARE]; 5429 5430 for (phy_id = 0; phy_id < MAX_RADIOS; phy_id++) { 5431 lower_sbs_freq_range[phy_id].low_2ghz_freq = 5432 ref_freq[phy_id].low_2ghz_freq; 5433 lower_sbs_freq_range[phy_id].high_2ghz_freq = 5434 ref_freq[phy_id].high_2ghz_freq; 5435 5436 /* update for shared mac */ 5437 if (lower_sbs_freq_range[phy_id].low_2ghz_freq) { 5438 lower_sbs_freq_range[phy_id].low_5ghz_freq = 5439 ath12k_wmi_get_lowest_5ghz_freq_from_range(ref_freq); 5440 lower_sbs_freq_range[phy_id].high_5ghz_freq = sbs_range_sep; 5441 } else { 5442 lower_sbs_freq_range[phy_id].low_5ghz_freq = sbs_range_sep + 10; 5443 lower_sbs_freq_range[phy_id].high_5ghz_freq = 5444 ath12k_wmi_get_highest_5ghz_freq_from_range(ref_freq); 5445 } 5446 } 5447 } 5448 5449 static const char *ath12k_wmi_hw_mode_to_str(enum ath12k_hw_mode hw_mode) 5450 { 5451 static const char * const mode_str[] = { 5452 [ATH12K_HW_MODE_SMM] = "SMM", 5453 [ATH12K_HW_MODE_DBS] = "DBS", 5454 [ATH12K_HW_MODE_SBS] = "SBS", 5455 [ATH12K_HW_MODE_SBS_UPPER_SHARE] = "SBS_UPPER_SHARE", 5456 [ATH12K_HW_MODE_SBS_LOWER_SHARE] = "SBS_LOWER_SHARE", 5457 }; 5458 5459 if (hw_mode >= ARRAY_SIZE(mode_str)) 5460 return "Unknown"; 5461 5462 return mode_str[hw_mode]; 5463 } 5464 5465 static void 5466 ath12k_wmi_dump_freq_range_per_mac(struct ath12k_base *ab, 5467 struct ath12k_hw_mode_freq_range_arg *freq_range, 5468 enum ath12k_hw_mode hw_mode) 5469 { 5470 u8 i; 5471 5472 for (i = 0; i < MAX_RADIOS; i++) 5473 if (freq_range[i].low_2ghz_freq || freq_range[i].low_5ghz_freq) 5474 ath12k_dbg(ab, ATH12K_DBG_WMI, 5475 "frequency range: %s(%d) mac %d 2 GHz [%d - %d] 5 GHz [%d - %d]", 5476 ath12k_wmi_hw_mode_to_str(hw_mode), 5477 hw_mode, i, 5478 freq_range[i].low_2ghz_freq, 5479 freq_range[i].high_2ghz_freq, 5480 freq_range[i].low_5ghz_freq, 5481 freq_range[i].high_5ghz_freq); 5482 } 5483 5484 static void ath12k_wmi_dump_freq_range(struct ath12k_base *ab) 5485 { 5486 struct ath12k_hw_mode_freq_range_arg *freq_range; 5487 u8 i; 5488 5489 for (i = ATH12K_HW_MODE_SMM; i < ATH12K_HW_MODE_MAX; i++) { 5490 freq_range = ab->wmi_ab.hw_mode_info.freq_range_caps[i]; 5491 ath12k_wmi_dump_freq_range_per_mac(ab, freq_range, i); 5492 } 5493 } 5494 5495 static int ath12k_wmi_modify_sbs_freq(struct ath12k_base *ab, u8 phy_id) 5496 { 5497 struct ath12k_hw_mode_info *hw_mode_info = &ab->wmi_ab.hw_mode_info; 5498 struct ath12k_hw_mode_freq_range_arg *sbs_mac_range, *shared_mac_range; 5499 struct ath12k_hw_mode_freq_range_arg *non_shared_range; 5500 u8 shared_phy_id; 5501 5502 sbs_mac_range = &hw_mode_info->freq_range_caps[ATH12K_HW_MODE_SBS][phy_id]; 5503 5504 /* if SBS mac range has both 2.4 and 5 GHz ranges, i.e. shared phy_id 5505 * keep the range as it is in SBS 5506 */ 5507 if (sbs_mac_range->low_2ghz_freq && sbs_mac_range->low_5ghz_freq) 5508 return 0; 5509 5510 if (sbs_mac_range->low_2ghz_freq && !sbs_mac_range->low_5ghz_freq) { 5511 ath12k_err(ab, "Invalid DBS/SBS mode with only 2.4Ghz"); 5512 ath12k_wmi_dump_freq_range_per_mac(ab, sbs_mac_range, ATH12K_HW_MODE_SBS); 5513 return -EINVAL; 5514 } 5515 5516 non_shared_range = sbs_mac_range; 5517 /* if SBS mac range has only 5 GHz then it's the non-shared phy, so 5518 * modify the range as per the shared mac. 5519 */ 5520 shared_phy_id = phy_id ? 0 : 1; 5521 shared_mac_range = 5522 &hw_mode_info->freq_range_caps[ATH12K_HW_MODE_SBS][shared_phy_id]; 5523 5524 if (shared_mac_range->low_5ghz_freq > non_shared_range->low_5ghz_freq) { 5525 ath12k_dbg(ab, ATH12K_DBG_WMI, "high 5 GHz shared"); 5526 /* If the shared mac lower 5 GHz frequency is greater than 5527 * non-shared mac lower 5 GHz frequency then the shared mac has 5528 * high 5 GHz shared with 2.4 GHz. So non-shared mac's 5 GHz high 5529 * freq should be less than the shared mac's low 5 GHz freq. 5530 */ 5531 if (non_shared_range->high_5ghz_freq >= 5532 shared_mac_range->low_5ghz_freq) 5533 non_shared_range->high_5ghz_freq = 5534 max_t(u32, shared_mac_range->low_5ghz_freq - 10, 5535 non_shared_range->low_5ghz_freq); 5536 } else if (shared_mac_range->high_5ghz_freq < 5537 non_shared_range->high_5ghz_freq) { 5538 ath12k_dbg(ab, ATH12K_DBG_WMI, "low 5 GHz shared"); 5539 /* If the shared mac high 5 GHz frequency is less than 5540 * non-shared mac high 5 GHz frequency then the shared mac has 5541 * low 5 GHz shared with 2.4 GHz. So non-shared mac's 5 GHz low 5542 * freq should be greater than the shared mac's high 5 GHz freq. 5543 */ 5544 if (shared_mac_range->high_5ghz_freq >= 5545 non_shared_range->low_5ghz_freq) 5546 non_shared_range->low_5ghz_freq = 5547 min_t(u32, shared_mac_range->high_5ghz_freq + 10, 5548 non_shared_range->high_5ghz_freq); 5549 } else { 5550 ath12k_warn(ab, "invalid SBS range with all 5 GHz shared"); 5551 return -EINVAL; 5552 } 5553 5554 return 0; 5555 } 5556 5557 static void ath12k_wmi_update_sbs_freq_info(struct ath12k_base *ab) 5558 { 5559 struct ath12k_hw_mode_info *hw_mode_info = &ab->wmi_ab.hw_mode_info; 5560 struct ath12k_hw_mode_freq_range_arg *mac_range; 5561 u16 sbs_range_sep; 5562 u8 phy_id; 5563 int ret; 5564 5565 mac_range = hw_mode_info->freq_range_caps[ATH12K_HW_MODE_SBS]; 5566 5567 /* If sbs_lower_band_end_freq has a value, then the frequency range 5568 * will be split using that value. 5569 */ 5570 sbs_range_sep = ab->wmi_ab.sbs_lower_band_end_freq; 5571 if (sbs_range_sep) { 5572 ath12k_wmi_fill_upper_share_sbs_freq(ab, sbs_range_sep, 5573 mac_range); 5574 ath12k_wmi_fill_lower_share_sbs_freq(ab, sbs_range_sep, 5575 mac_range); 5576 /* Hardware specifies the range boundary with sbs_range_sep, 5577 * (i.e. the boundary between 5 GHz high and 5 GHz low), 5578 * reset the original one to make sure it will not get used. 5579 */ 5580 memset(mac_range, 0, sizeof(*mac_range) * MAX_RADIOS); 5581 return; 5582 } 5583 5584 /* If sbs_lower_band_end_freq is not set that means firmware will send one 5585 * shared mac range and one non-shared mac range. so update that freq. 5586 */ 5587 for (phy_id = 0; phy_id < MAX_RADIOS; phy_id++) { 5588 ret = ath12k_wmi_modify_sbs_freq(ab, phy_id); 5589 if (ret) { 5590 memset(mac_range, 0, sizeof(*mac_range) * MAX_RADIOS); 5591 break; 5592 } 5593 } 5594 } 5595 5596 static void 5597 ath12k_wmi_update_mac_freq_info(struct ath12k_base *ab, 5598 enum wmi_host_hw_mode_config_type hw_config_type, 5599 u32 phy_id, 5600 struct ath12k_svc_ext_mac_phy_info *mac_cap) 5601 { 5602 if (phy_id >= MAX_RADIOS) { 5603 ath12k_err(ab, "mac more than two not supported: %d", phy_id); 5604 return; 5605 } 5606 5607 ath12k_dbg(ab, ATH12K_DBG_WMI, 5608 "hw_mode_cfg %d mac %d band 0x%x SBS cutoff freq %d 2 GHz [%d - %d] 5 GHz [%d - %d]", 5609 hw_config_type, phy_id, mac_cap->supported_bands, 5610 ab->wmi_ab.sbs_lower_band_end_freq, 5611 mac_cap->hw_freq_range.low_2ghz_freq, 5612 mac_cap->hw_freq_range.high_2ghz_freq, 5613 mac_cap->hw_freq_range.low_5ghz_freq, 5614 mac_cap->hw_freq_range.high_5ghz_freq); 5615 5616 switch (hw_config_type) { 5617 case WMI_HOST_HW_MODE_SINGLE: 5618 if (phy_id) { 5619 ath12k_dbg(ab, ATH12K_DBG_WMI, "mac phy 1 is not supported"); 5620 break; 5621 } 5622 ath12k_wmi_update_freq_info(ab, mac_cap, ATH12K_HW_MODE_SMM, phy_id); 5623 break; 5624 5625 case WMI_HOST_HW_MODE_DBS: 5626 if (!ath12k_wmi_all_phy_range_updated(ab, ATH12K_HW_MODE_DBS)) 5627 ath12k_wmi_update_freq_info(ab, mac_cap, 5628 ATH12K_HW_MODE_DBS, phy_id); 5629 break; 5630 case WMI_HOST_HW_MODE_DBS_SBS: 5631 case WMI_HOST_HW_MODE_DBS_OR_SBS: 5632 ath12k_wmi_update_freq_info(ab, mac_cap, ATH12K_HW_MODE_DBS, phy_id); 5633 if (ab->wmi_ab.sbs_lower_band_end_freq || 5634 mac_cap->hw_freq_range.low_5ghz_freq || 5635 mac_cap->hw_freq_range.low_2ghz_freq) 5636 ath12k_wmi_update_freq_info(ab, mac_cap, ATH12K_HW_MODE_SBS, 5637 phy_id); 5638 5639 if (ath12k_wmi_all_phy_range_updated(ab, ATH12K_HW_MODE_DBS)) 5640 ath12k_wmi_update_dbs_freq_info(ab); 5641 if (ath12k_wmi_all_phy_range_updated(ab, ATH12K_HW_MODE_SBS)) 5642 ath12k_wmi_update_sbs_freq_info(ab); 5643 break; 5644 case WMI_HOST_HW_MODE_SBS: 5645 case WMI_HOST_HW_MODE_SBS_PASSIVE: 5646 ath12k_wmi_update_freq_info(ab, mac_cap, ATH12K_HW_MODE_SBS, phy_id); 5647 if (ath12k_wmi_all_phy_range_updated(ab, ATH12K_HW_MODE_SBS)) 5648 ath12k_wmi_update_sbs_freq_info(ab); 5649 5650 break; 5651 default: 5652 break; 5653 } 5654 } 5655 5656 static bool ath12k_wmi_sbs_range_present(struct ath12k_base *ab) 5657 { 5658 if (ath12k_wmi_all_phy_range_updated(ab, ATH12K_HW_MODE_SBS) || 5659 (ab->wmi_ab.sbs_lower_band_end_freq && 5660 ath12k_wmi_all_phy_range_updated(ab, ATH12K_HW_MODE_SBS_LOWER_SHARE) && 5661 ath12k_wmi_all_phy_range_updated(ab, ATH12K_HW_MODE_SBS_UPPER_SHARE))) 5662 return true; 5663 5664 return false; 5665 } 5666 5667 static int ath12k_wmi_update_hw_mode_list(struct ath12k_base *ab) 5668 { 5669 struct ath12k_svc_ext_info *svc_ext_info = &ab->wmi_ab.svc_ext_info; 5670 struct ath12k_hw_mode_info *info = &ab->wmi_ab.hw_mode_info; 5671 enum wmi_host_hw_mode_config_type hw_config_type; 5672 struct ath12k_svc_ext_mac_phy_info *tmp; 5673 bool dbs_mode = false, sbs_mode = false; 5674 u32 i, j = 0; 5675 5676 if (!svc_ext_info->num_hw_modes) { 5677 ath12k_err(ab, "invalid number of hw modes"); 5678 return -EINVAL; 5679 } 5680 5681 ath12k_dbg(ab, ATH12K_DBG_WMI, "updated HW mode list: num modes %d", 5682 svc_ext_info->num_hw_modes); 5683 5684 memset(info->freq_range_caps, 0, sizeof(info->freq_range_caps)); 5685 5686 for (i = 0; i < svc_ext_info->num_hw_modes; i++) { 5687 if (j >= ATH12K_MAX_MAC_PHY_CAP) 5688 return -EINVAL; 5689 5690 /* Update for MAC0 */ 5691 tmp = &svc_ext_info->mac_phy_info[j++]; 5692 hw_config_type = tmp->hw_mode_config_type; 5693 ath12k_wmi_update_mac_freq_info(ab, hw_config_type, tmp->phy_id, tmp); 5694 5695 /* SBS and DBS have dual MAC. Up to 2 MACs are considered. */ 5696 if (hw_config_type == WMI_HOST_HW_MODE_DBS || 5697 hw_config_type == WMI_HOST_HW_MODE_SBS_PASSIVE || 5698 hw_config_type == WMI_HOST_HW_MODE_SBS || 5699 hw_config_type == WMI_HOST_HW_MODE_DBS_OR_SBS) { 5700 if (j >= ATH12K_MAX_MAC_PHY_CAP) 5701 return -EINVAL; 5702 /* Update for MAC1 */ 5703 tmp = &svc_ext_info->mac_phy_info[j++]; 5704 ath12k_wmi_update_mac_freq_info(ab, hw_config_type, 5705 tmp->phy_id, tmp); 5706 5707 if (hw_config_type == WMI_HOST_HW_MODE_DBS || 5708 hw_config_type == WMI_HOST_HW_MODE_DBS_OR_SBS) 5709 dbs_mode = true; 5710 5711 if (ath12k_wmi_sbs_range_present(ab) && 5712 (hw_config_type == WMI_HOST_HW_MODE_SBS_PASSIVE || 5713 hw_config_type == WMI_HOST_HW_MODE_SBS || 5714 hw_config_type == WMI_HOST_HW_MODE_DBS_OR_SBS)) 5715 sbs_mode = true; 5716 } 5717 } 5718 5719 info->support_dbs = dbs_mode; 5720 info->support_sbs = sbs_mode; 5721 5722 ath12k_wmi_dump_freq_range(ab); 5723 5724 return 0; 5725 } 5726 5727 static int ath12k_wmi_svc_rdy_ext2_parse(struct ath12k_base *ab, 5728 u16 tag, u16 len, 5729 const void *ptr, void *data) 5730 { 5731 const struct ath12k_wmi_dbs_or_sbs_cap_params *dbs_or_sbs_caps; 5732 struct ath12k_wmi_pdev *wmi_handle = &ab->wmi_ab.wmi[0]; 5733 struct ath12k_wmi_svc_rdy_ext2_parse *parse = data; 5734 int ret; 5735 5736 switch (tag) { 5737 case WMI_TAG_SERVICE_READY_EXT2_EVENT: 5738 ret = ath12k_pull_svc_ready_ext2(wmi_handle, ptr, 5739 &parse->arg); 5740 if (ret) { 5741 ath12k_warn(ab, 5742 "failed to extract wmi service ready ext2 parameters: %d\n", 5743 ret); 5744 return ret; 5745 } 5746 5747 ab->wmi_ab.dp_peer_meta_data_ver = 5748 u32_get_bits(parse->arg.target_cap_flags, 5749 WMI_TARGET_CAP_FLAGS_RX_PEER_METADATA_VERSION); 5750 break; 5751 5752 case WMI_TAG_ARRAY_STRUCT: 5753 if (!parse->dma_ring_cap_done) { 5754 ret = ath12k_wmi_dma_ring_caps(ab, len, ptr, 5755 &parse->dma_caps_parse); 5756 if (ret) 5757 return ret; 5758 5759 parse->dma_ring_cap_done = true; 5760 } else if (!parse->spectral_bin_scaling_done) { 5761 /* TODO: This is a place-holder as WMI tag for 5762 * spectral scaling is before 5763 * WMI_TAG_MAC_PHY_CAPABILITIES_EXT 5764 */ 5765 parse->spectral_bin_scaling_done = true; 5766 } else if (!parse->mac_phy_caps_ext_done) { 5767 ret = ath12k_wmi_tlv_iter(ab, ptr, len, 5768 ath12k_wmi_tlv_mac_phy_caps_ext, 5769 parse); 5770 if (ret) { 5771 ath12k_warn(ab, "failed to parse extended MAC PHY capabilities WMI TLV: %d\n", 5772 ret); 5773 return ret; 5774 } 5775 5776 parse->mac_phy_caps_ext_done = true; 5777 } else if (!parse->hal_reg_caps_ext2_done) { 5778 parse->hal_reg_caps_ext2_done = true; 5779 } else if (!parse->scan_radio_caps_ext2_done) { 5780 parse->scan_radio_caps_ext2_done = true; 5781 } else if (!parse->twt_caps_done) { 5782 parse->twt_caps_done = true; 5783 } else if (!parse->htt_msdu_idx_to_qtype_map_done) { 5784 parse->htt_msdu_idx_to_qtype_map_done = true; 5785 } else if (!parse->dbs_or_sbs_cap_ext_done) { 5786 dbs_or_sbs_caps = ptr; 5787 ab->wmi_ab.sbs_lower_band_end_freq = 5788 __le32_to_cpu(dbs_or_sbs_caps->sbs_lower_band_end_freq); 5789 5790 ath12k_dbg(ab, ATH12K_DBG_WMI, "sbs_lower_band_end_freq %u\n", 5791 ab->wmi_ab.sbs_lower_band_end_freq); 5792 5793 ret = ath12k_wmi_update_hw_mode_list(ab); 5794 if (ret) { 5795 ath12k_warn(ab, "failed to update hw mode list: %d\n", 5796 ret); 5797 return ret; 5798 } 5799 5800 parse->dbs_or_sbs_cap_ext_done = true; 5801 } 5802 5803 break; 5804 default: 5805 break; 5806 } 5807 5808 return 0; 5809 } 5810 5811 static int ath12k_service_ready_ext2_event(struct ath12k_base *ab, 5812 struct sk_buff *skb) 5813 { 5814 struct ath12k_wmi_svc_rdy_ext2_parse svc_rdy_ext2 = { }; 5815 int ret; 5816 5817 ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, 5818 ath12k_wmi_svc_rdy_ext2_parse, 5819 &svc_rdy_ext2); 5820 if (ret) { 5821 ath12k_warn(ab, "failed to parse ext2 event tlv %d\n", ret); 5822 goto err; 5823 } 5824 5825 complete(&ab->wmi_ab.service_ready); 5826 5827 return 0; 5828 5829 err: 5830 ath12k_wmi_free_dbring_caps(ab); 5831 return ret; 5832 } 5833 5834 static int ath12k_pull_vdev_start_resp_tlv(struct ath12k_base *ab, struct sk_buff *skb, 5835 struct wmi_vdev_start_resp_event *vdev_rsp) 5836 { 5837 const void **tb; 5838 const struct wmi_vdev_start_resp_event *ev; 5839 int ret; 5840 5841 tb = ath12k_wmi_tlv_parse(ab, skb); 5842 if (IS_ERR(tb)) { 5843 ret = PTR_ERR(tb); 5844 ath12k_warn(ab, "failed to parse tlv: %d\n", ret); 5845 return ret; 5846 } 5847 5848 ev = tb[WMI_TAG_VDEV_START_RESPONSE_EVENT]; 5849 if (!ev) { 5850 ath12k_warn(ab, "failed to fetch vdev start resp ev"); 5851 return -EPROTO; 5852 } 5853 5854 *vdev_rsp = *ev; 5855 5856 return 0; 5857 } 5858 5859 static struct ath12k_reg_rule 5860 *create_ext_reg_rules_from_wmi(u32 num_reg_rules, 5861 struct ath12k_wmi_reg_rule_ext_params *wmi_reg_rule) 5862 { 5863 struct ath12k_reg_rule *reg_rule_ptr; 5864 u32 count; 5865 5866 reg_rule_ptr = kzalloc((num_reg_rules * sizeof(*reg_rule_ptr)), 5867 GFP_ATOMIC); 5868 5869 if (!reg_rule_ptr) 5870 return NULL; 5871 5872 for (count = 0; count < num_reg_rules; count++) { 5873 reg_rule_ptr[count].start_freq = 5874 le32_get_bits(wmi_reg_rule[count].freq_info, 5875 REG_RULE_START_FREQ); 5876 reg_rule_ptr[count].end_freq = 5877 le32_get_bits(wmi_reg_rule[count].freq_info, 5878 REG_RULE_END_FREQ); 5879 reg_rule_ptr[count].max_bw = 5880 le32_get_bits(wmi_reg_rule[count].bw_pwr_info, 5881 REG_RULE_MAX_BW); 5882 reg_rule_ptr[count].reg_power = 5883 le32_get_bits(wmi_reg_rule[count].bw_pwr_info, 5884 REG_RULE_REG_PWR); 5885 reg_rule_ptr[count].ant_gain = 5886 le32_get_bits(wmi_reg_rule[count].bw_pwr_info, 5887 REG_RULE_ANT_GAIN); 5888 reg_rule_ptr[count].flags = 5889 le32_get_bits(wmi_reg_rule[count].flag_info, 5890 REG_RULE_FLAGS); 5891 reg_rule_ptr[count].psd_flag = 5892 le32_get_bits(wmi_reg_rule[count].psd_power_info, 5893 REG_RULE_PSD_INFO); 5894 reg_rule_ptr[count].psd_eirp = 5895 le32_get_bits(wmi_reg_rule[count].psd_power_info, 5896 REG_RULE_PSD_EIRP); 5897 } 5898 5899 return reg_rule_ptr; 5900 } 5901 5902 static u8 ath12k_wmi_ignore_num_extra_rules(struct ath12k_wmi_reg_rule_ext_params *rule, 5903 u32 num_reg_rules) 5904 { 5905 u8 num_invalid_5ghz_rules = 0; 5906 u32 count, start_freq; 5907 5908 for (count = 0; count < num_reg_rules; count++) { 5909 start_freq = le32_get_bits(rule[count].freq_info, REG_RULE_START_FREQ); 5910 5911 if (start_freq >= ATH12K_MIN_6GHZ_FREQ) 5912 num_invalid_5ghz_rules++; 5913 } 5914 5915 return num_invalid_5ghz_rules; 5916 } 5917 5918 static int ath12k_pull_reg_chan_list_ext_update_ev(struct ath12k_base *ab, 5919 struct sk_buff *skb, 5920 struct ath12k_reg_info *reg_info) 5921 { 5922 const void **tb; 5923 const struct wmi_reg_chan_list_cc_ext_event *ev; 5924 struct ath12k_wmi_reg_rule_ext_params *ext_wmi_reg_rule; 5925 u32 num_2g_reg_rules, num_5g_reg_rules; 5926 u32 num_6g_reg_rules_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 5927 u32 num_6g_reg_rules_cl[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 5928 u8 num_invalid_5ghz_ext_rules; 5929 u32 total_reg_rules = 0; 5930 int ret, i, j; 5931 5932 ath12k_dbg(ab, ATH12K_DBG_WMI, "processing regulatory ext channel list\n"); 5933 5934 tb = ath12k_wmi_tlv_parse(ab, skb); 5935 if (IS_ERR(tb)) { 5936 ret = PTR_ERR(tb); 5937 ath12k_warn(ab, "failed to parse tlv: %d\n", ret); 5938 return ret; 5939 } 5940 5941 ev = tb[WMI_TAG_REG_CHAN_LIST_CC_EXT_EVENT]; 5942 if (!ev) { 5943 ath12k_warn(ab, "failed to fetch reg chan list ext update ev\n"); 5944 return -EPROTO; 5945 } 5946 5947 reg_info->num_2g_reg_rules = le32_to_cpu(ev->num_2g_reg_rules); 5948 reg_info->num_5g_reg_rules = le32_to_cpu(ev->num_5g_reg_rules); 5949 reg_info->num_6g_reg_rules_ap[WMI_REG_INDOOR_AP] = 5950 le32_to_cpu(ev->num_6g_reg_rules_ap_lpi); 5951 reg_info->num_6g_reg_rules_ap[WMI_REG_STD_POWER_AP] = 5952 le32_to_cpu(ev->num_6g_reg_rules_ap_sp); 5953 reg_info->num_6g_reg_rules_ap[WMI_REG_VLP_AP] = 5954 le32_to_cpu(ev->num_6g_reg_rules_ap_vlp); 5955 5956 for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) { 5957 reg_info->num_6g_reg_rules_cl[WMI_REG_INDOOR_AP][i] = 5958 le32_to_cpu(ev->num_6g_reg_rules_cl_lpi[i]); 5959 reg_info->num_6g_reg_rules_cl[WMI_REG_STD_POWER_AP][i] = 5960 le32_to_cpu(ev->num_6g_reg_rules_cl_sp[i]); 5961 reg_info->num_6g_reg_rules_cl[WMI_REG_VLP_AP][i] = 5962 le32_to_cpu(ev->num_6g_reg_rules_cl_vlp[i]); 5963 } 5964 5965 num_2g_reg_rules = reg_info->num_2g_reg_rules; 5966 total_reg_rules += num_2g_reg_rules; 5967 num_5g_reg_rules = reg_info->num_5g_reg_rules; 5968 total_reg_rules += num_5g_reg_rules; 5969 5970 if (num_2g_reg_rules > MAX_REG_RULES || num_5g_reg_rules > MAX_REG_RULES) { 5971 ath12k_warn(ab, "Num reg rules for 2G/5G exceeds max limit (num_2g_reg_rules: %d num_5g_reg_rules: %d max_rules: %d)\n", 5972 num_2g_reg_rules, num_5g_reg_rules, MAX_REG_RULES); 5973 return -EINVAL; 5974 } 5975 5976 for (i = 0; i < WMI_REG_CURRENT_MAX_AP_TYPE; i++) { 5977 num_6g_reg_rules_ap[i] = reg_info->num_6g_reg_rules_ap[i]; 5978 5979 if (num_6g_reg_rules_ap[i] > MAX_6GHZ_REG_RULES) { 5980 ath12k_warn(ab, "Num 6G reg rules for AP mode(%d) exceeds max limit (num_6g_reg_rules_ap: %d, max_rules: %d)\n", 5981 i, num_6g_reg_rules_ap[i], MAX_6GHZ_REG_RULES); 5982 return -EINVAL; 5983 } 5984 5985 total_reg_rules += num_6g_reg_rules_ap[i]; 5986 } 5987 5988 for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) { 5989 num_6g_reg_rules_cl[WMI_REG_INDOOR_AP][i] = 5990 reg_info->num_6g_reg_rules_cl[WMI_REG_INDOOR_AP][i]; 5991 total_reg_rules += num_6g_reg_rules_cl[WMI_REG_INDOOR_AP][i]; 5992 5993 num_6g_reg_rules_cl[WMI_REG_STD_POWER_AP][i] = 5994 reg_info->num_6g_reg_rules_cl[WMI_REG_STD_POWER_AP][i]; 5995 total_reg_rules += num_6g_reg_rules_cl[WMI_REG_STD_POWER_AP][i]; 5996 5997 num_6g_reg_rules_cl[WMI_REG_VLP_AP][i] = 5998 reg_info->num_6g_reg_rules_cl[WMI_REG_VLP_AP][i]; 5999 total_reg_rules += num_6g_reg_rules_cl[WMI_REG_VLP_AP][i]; 6000 6001 if (num_6g_reg_rules_cl[WMI_REG_INDOOR_AP][i] > MAX_6GHZ_REG_RULES || 6002 num_6g_reg_rules_cl[WMI_REG_STD_POWER_AP][i] > MAX_6GHZ_REG_RULES || 6003 num_6g_reg_rules_cl[WMI_REG_VLP_AP][i] > MAX_6GHZ_REG_RULES) { 6004 ath12k_warn(ab, "Num 6g client reg rules exceeds max limit, for client(type: %d)\n", 6005 i); 6006 return -EINVAL; 6007 } 6008 } 6009 6010 if (!total_reg_rules) { 6011 ath12k_warn(ab, "No reg rules available\n"); 6012 return -EINVAL; 6013 } 6014 6015 memcpy(reg_info->alpha2, &ev->alpha2, REG_ALPHA2_LEN); 6016 6017 reg_info->dfs_region = le32_to_cpu(ev->dfs_region); 6018 reg_info->phybitmap = le32_to_cpu(ev->phybitmap); 6019 reg_info->num_phy = le32_to_cpu(ev->num_phy); 6020 reg_info->phy_id = le32_to_cpu(ev->phy_id); 6021 reg_info->ctry_code = le32_to_cpu(ev->country_id); 6022 reg_info->reg_dmn_pair = le32_to_cpu(ev->domain_code); 6023 6024 switch (le32_to_cpu(ev->status_code)) { 6025 case WMI_REG_SET_CC_STATUS_PASS: 6026 reg_info->status_code = REG_SET_CC_STATUS_PASS; 6027 break; 6028 case WMI_REG_CURRENT_ALPHA2_NOT_FOUND: 6029 reg_info->status_code = REG_CURRENT_ALPHA2_NOT_FOUND; 6030 break; 6031 case WMI_REG_INIT_ALPHA2_NOT_FOUND: 6032 reg_info->status_code = REG_INIT_ALPHA2_NOT_FOUND; 6033 break; 6034 case WMI_REG_SET_CC_CHANGE_NOT_ALLOWED: 6035 reg_info->status_code = REG_SET_CC_CHANGE_NOT_ALLOWED; 6036 break; 6037 case WMI_REG_SET_CC_STATUS_NO_MEMORY: 6038 reg_info->status_code = REG_SET_CC_STATUS_NO_MEMORY; 6039 break; 6040 case WMI_REG_SET_CC_STATUS_FAIL: 6041 reg_info->status_code = REG_SET_CC_STATUS_FAIL; 6042 break; 6043 } 6044 6045 reg_info->is_ext_reg_event = true; 6046 6047 reg_info->min_bw_2g = le32_to_cpu(ev->min_bw_2g); 6048 reg_info->max_bw_2g = le32_to_cpu(ev->max_bw_2g); 6049 reg_info->min_bw_5g = le32_to_cpu(ev->min_bw_5g); 6050 reg_info->max_bw_5g = le32_to_cpu(ev->max_bw_5g); 6051 reg_info->min_bw_6g_ap[WMI_REG_INDOOR_AP] = le32_to_cpu(ev->min_bw_6g_ap_lpi); 6052 reg_info->max_bw_6g_ap[WMI_REG_INDOOR_AP] = le32_to_cpu(ev->max_bw_6g_ap_lpi); 6053 reg_info->min_bw_6g_ap[WMI_REG_STD_POWER_AP] = le32_to_cpu(ev->min_bw_6g_ap_sp); 6054 reg_info->max_bw_6g_ap[WMI_REG_STD_POWER_AP] = le32_to_cpu(ev->max_bw_6g_ap_sp); 6055 reg_info->min_bw_6g_ap[WMI_REG_VLP_AP] = le32_to_cpu(ev->min_bw_6g_ap_vlp); 6056 reg_info->max_bw_6g_ap[WMI_REG_VLP_AP] = le32_to_cpu(ev->max_bw_6g_ap_vlp); 6057 6058 for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) { 6059 reg_info->min_bw_6g_client[WMI_REG_INDOOR_AP][i] = 6060 le32_to_cpu(ev->min_bw_6g_client_lpi[i]); 6061 reg_info->max_bw_6g_client[WMI_REG_INDOOR_AP][i] = 6062 le32_to_cpu(ev->max_bw_6g_client_lpi[i]); 6063 reg_info->min_bw_6g_client[WMI_REG_STD_POWER_AP][i] = 6064 le32_to_cpu(ev->min_bw_6g_client_sp[i]); 6065 reg_info->max_bw_6g_client[WMI_REG_STD_POWER_AP][i] = 6066 le32_to_cpu(ev->max_bw_6g_client_sp[i]); 6067 reg_info->min_bw_6g_client[WMI_REG_VLP_AP][i] = 6068 le32_to_cpu(ev->min_bw_6g_client_vlp[i]); 6069 reg_info->max_bw_6g_client[WMI_REG_VLP_AP][i] = 6070 le32_to_cpu(ev->max_bw_6g_client_vlp[i]); 6071 } 6072 6073 ath12k_dbg(ab, ATH12K_DBG_WMI, 6074 "%s:cc_ext %s dfs %d BW: min_2g %d max_2g %d min_5g %d max_5g %d phy_bitmap 0x%x", 6075 __func__, reg_info->alpha2, reg_info->dfs_region, 6076 reg_info->min_bw_2g, reg_info->max_bw_2g, 6077 reg_info->min_bw_5g, reg_info->max_bw_5g, 6078 reg_info->phybitmap); 6079 6080 ath12k_dbg(ab, ATH12K_DBG_WMI, 6081 "num_2g_reg_rules %d num_5g_reg_rules %d", 6082 num_2g_reg_rules, num_5g_reg_rules); 6083 6084 ath12k_dbg(ab, ATH12K_DBG_WMI, 6085 "num_6g_reg_rules_ap_lpi: %d num_6g_reg_rules_ap_sp: %d num_6g_reg_rules_ap_vlp: %d", 6086 num_6g_reg_rules_ap[WMI_REG_INDOOR_AP], 6087 num_6g_reg_rules_ap[WMI_REG_STD_POWER_AP], 6088 num_6g_reg_rules_ap[WMI_REG_VLP_AP]); 6089 6090 ath12k_dbg(ab, ATH12K_DBG_WMI, 6091 "6g Regular client: num_6g_reg_rules_lpi: %d num_6g_reg_rules_sp: %d num_6g_reg_rules_vlp: %d", 6092 num_6g_reg_rules_cl[WMI_REG_INDOOR_AP][WMI_REG_DEFAULT_CLIENT], 6093 num_6g_reg_rules_cl[WMI_REG_STD_POWER_AP][WMI_REG_DEFAULT_CLIENT], 6094 num_6g_reg_rules_cl[WMI_REG_VLP_AP][WMI_REG_DEFAULT_CLIENT]); 6095 6096 ath12k_dbg(ab, ATH12K_DBG_WMI, 6097 "6g Subordinate client: num_6g_reg_rules_lpi: %d num_6g_reg_rules_sp: %d num_6g_reg_rules_vlp: %d", 6098 num_6g_reg_rules_cl[WMI_REG_INDOOR_AP][WMI_REG_SUBORDINATE_CLIENT], 6099 num_6g_reg_rules_cl[WMI_REG_STD_POWER_AP][WMI_REG_SUBORDINATE_CLIENT], 6100 num_6g_reg_rules_cl[WMI_REG_VLP_AP][WMI_REG_SUBORDINATE_CLIENT]); 6101 6102 ext_wmi_reg_rule = 6103 (struct ath12k_wmi_reg_rule_ext_params *)((u8 *)ev 6104 + sizeof(*ev) 6105 + sizeof(struct wmi_tlv)); 6106 6107 if (num_2g_reg_rules) { 6108 reg_info->reg_rules_2g_ptr = 6109 create_ext_reg_rules_from_wmi(num_2g_reg_rules, 6110 ext_wmi_reg_rule); 6111 6112 if (!reg_info->reg_rules_2g_ptr) { 6113 ath12k_warn(ab, "Unable to Allocate memory for 2g rules\n"); 6114 return -ENOMEM; 6115 } 6116 } 6117 6118 ext_wmi_reg_rule += num_2g_reg_rules; 6119 6120 /* Firmware might include 6 GHz reg rule in 5 GHz rule list 6121 * for few countries along with separate 6 GHz rule. 6122 * Having same 6 GHz reg rule in 5 GHz and 6 GHz rules list 6123 * causes intersect check to be true, and same rules will be 6124 * shown multiple times in iw cmd. 6125 * Hence, avoid parsing 6 GHz rule from 5 GHz reg rule list 6126 */ 6127 num_invalid_5ghz_ext_rules = ath12k_wmi_ignore_num_extra_rules(ext_wmi_reg_rule, 6128 num_5g_reg_rules); 6129 6130 if (num_invalid_5ghz_ext_rules) { 6131 ath12k_dbg(ab, ATH12K_DBG_WMI, 6132 "CC: %s 5 GHz reg rules number %d from fw, %d number of invalid 5 GHz rules", 6133 reg_info->alpha2, reg_info->num_5g_reg_rules, 6134 num_invalid_5ghz_ext_rules); 6135 6136 num_5g_reg_rules = num_5g_reg_rules - num_invalid_5ghz_ext_rules; 6137 reg_info->num_5g_reg_rules = num_5g_reg_rules; 6138 } 6139 6140 if (num_5g_reg_rules) { 6141 reg_info->reg_rules_5g_ptr = 6142 create_ext_reg_rules_from_wmi(num_5g_reg_rules, 6143 ext_wmi_reg_rule); 6144 6145 if (!reg_info->reg_rules_5g_ptr) { 6146 ath12k_warn(ab, "Unable to Allocate memory for 5g rules\n"); 6147 return -ENOMEM; 6148 } 6149 } 6150 6151 /* We have adjusted the number of 5 GHz reg rules above. But still those 6152 * many rules needs to be adjusted in ext_wmi_reg_rule. 6153 * 6154 * NOTE: num_invalid_5ghz_ext_rules will be 0 for rest other cases. 6155 */ 6156 ext_wmi_reg_rule += (num_5g_reg_rules + num_invalid_5ghz_ext_rules); 6157 6158 for (i = 0; i < WMI_REG_CURRENT_MAX_AP_TYPE; i++) { 6159 reg_info->reg_rules_6g_ap_ptr[i] = 6160 create_ext_reg_rules_from_wmi(num_6g_reg_rules_ap[i], 6161 ext_wmi_reg_rule); 6162 6163 if (!reg_info->reg_rules_6g_ap_ptr[i]) { 6164 ath12k_warn(ab, "Unable to Allocate memory for 6g ap rules\n"); 6165 return -ENOMEM; 6166 } 6167 6168 ext_wmi_reg_rule += num_6g_reg_rules_ap[i]; 6169 } 6170 6171 for (j = 0; j < WMI_REG_CURRENT_MAX_AP_TYPE; j++) { 6172 for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) { 6173 reg_info->reg_rules_6g_client_ptr[j][i] = 6174 create_ext_reg_rules_from_wmi(num_6g_reg_rules_cl[j][i], 6175 ext_wmi_reg_rule); 6176 6177 if (!reg_info->reg_rules_6g_client_ptr[j][i]) { 6178 ath12k_warn(ab, "Unable to Allocate memory for 6g client rules\n"); 6179 return -ENOMEM; 6180 } 6181 6182 ext_wmi_reg_rule += num_6g_reg_rules_cl[j][i]; 6183 } 6184 } 6185 6186 reg_info->client_type = le32_to_cpu(ev->client_type); 6187 reg_info->rnr_tpe_usable = ev->rnr_tpe_usable; 6188 reg_info->unspecified_ap_usable = ev->unspecified_ap_usable; 6189 reg_info->domain_code_6g_ap[WMI_REG_INDOOR_AP] = 6190 le32_to_cpu(ev->domain_code_6g_ap_lpi); 6191 reg_info->domain_code_6g_ap[WMI_REG_STD_POWER_AP] = 6192 le32_to_cpu(ev->domain_code_6g_ap_sp); 6193 reg_info->domain_code_6g_ap[WMI_REG_VLP_AP] = 6194 le32_to_cpu(ev->domain_code_6g_ap_vlp); 6195 6196 for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) { 6197 reg_info->domain_code_6g_client[WMI_REG_INDOOR_AP][i] = 6198 le32_to_cpu(ev->domain_code_6g_client_lpi[i]); 6199 reg_info->domain_code_6g_client[WMI_REG_STD_POWER_AP][i] = 6200 le32_to_cpu(ev->domain_code_6g_client_sp[i]); 6201 reg_info->domain_code_6g_client[WMI_REG_VLP_AP][i] = 6202 le32_to_cpu(ev->domain_code_6g_client_vlp[i]); 6203 } 6204 6205 reg_info->domain_code_6g_super_id = le32_to_cpu(ev->domain_code_6g_super_id); 6206 6207 ath12k_dbg(ab, ATH12K_DBG_WMI, "6g client_type: %d domain_code_6g_super_id: %d", 6208 reg_info->client_type, reg_info->domain_code_6g_super_id); 6209 6210 ath12k_dbg(ab, ATH12K_DBG_WMI, "processed regulatory ext channel list\n"); 6211 6212 return 0; 6213 } 6214 6215 static int ath12k_pull_peer_del_resp_ev(struct ath12k_base *ab, struct sk_buff *skb, 6216 struct wmi_peer_delete_resp_event *peer_del_resp) 6217 { 6218 const void **tb; 6219 const struct wmi_peer_delete_resp_event *ev; 6220 int ret; 6221 6222 tb = ath12k_wmi_tlv_parse(ab, skb); 6223 if (IS_ERR(tb)) { 6224 ret = PTR_ERR(tb); 6225 ath12k_warn(ab, "failed to parse tlv: %d\n", ret); 6226 return ret; 6227 } 6228 6229 ev = tb[WMI_TAG_PEER_DELETE_RESP_EVENT]; 6230 if (!ev) { 6231 ath12k_warn(ab, "failed to fetch peer delete resp ev"); 6232 return -EPROTO; 6233 } 6234 6235 memset(peer_del_resp, 0, sizeof(*peer_del_resp)); 6236 6237 peer_del_resp->vdev_id = ev->vdev_id; 6238 ether_addr_copy(peer_del_resp->peer_macaddr.addr, 6239 ev->peer_macaddr.addr); 6240 6241 return 0; 6242 } 6243 6244 static int ath12k_pull_vdev_del_resp_ev(struct ath12k_base *ab, 6245 struct sk_buff *skb, 6246 u32 *vdev_id) 6247 { 6248 const void **tb; 6249 const struct wmi_vdev_delete_resp_event *ev; 6250 int ret; 6251 6252 tb = ath12k_wmi_tlv_parse(ab, skb); 6253 if (IS_ERR(tb)) { 6254 ret = PTR_ERR(tb); 6255 ath12k_warn(ab, "failed to parse tlv: %d\n", ret); 6256 return ret; 6257 } 6258 6259 ev = tb[WMI_TAG_VDEV_DELETE_RESP_EVENT]; 6260 if (!ev) { 6261 ath12k_warn(ab, "failed to fetch vdev delete resp ev"); 6262 return -EPROTO; 6263 } 6264 6265 *vdev_id = le32_to_cpu(ev->vdev_id); 6266 6267 return 0; 6268 } 6269 6270 static int ath12k_pull_bcn_tx_status_ev(struct ath12k_base *ab, 6271 struct sk_buff *skb, 6272 u32 *vdev_id, u32 *tx_status) 6273 { 6274 const void **tb; 6275 const struct wmi_bcn_tx_status_event *ev; 6276 int ret; 6277 6278 tb = ath12k_wmi_tlv_parse(ab, skb); 6279 if (IS_ERR(tb)) { 6280 ret = PTR_ERR(tb); 6281 ath12k_warn(ab, "failed to parse tlv: %d\n", ret); 6282 return ret; 6283 } 6284 6285 ev = tb[WMI_TAG_OFFLOAD_BCN_TX_STATUS_EVENT]; 6286 if (!ev) { 6287 ath12k_warn(ab, "failed to fetch bcn tx status ev"); 6288 return -EPROTO; 6289 } 6290 6291 *vdev_id = le32_to_cpu(ev->vdev_id); 6292 *tx_status = le32_to_cpu(ev->tx_status); 6293 6294 return 0; 6295 } 6296 6297 static int ath12k_pull_vdev_stopped_param_tlv(struct ath12k_base *ab, struct sk_buff *skb, 6298 u32 *vdev_id) 6299 { 6300 const void **tb; 6301 const struct wmi_vdev_stopped_event *ev; 6302 int ret; 6303 6304 tb = ath12k_wmi_tlv_parse(ab, skb); 6305 if (IS_ERR(tb)) { 6306 ret = PTR_ERR(tb); 6307 ath12k_warn(ab, "failed to parse tlv: %d\n", ret); 6308 return ret; 6309 } 6310 6311 ev = tb[WMI_TAG_VDEV_STOPPED_EVENT]; 6312 if (!ev) { 6313 ath12k_warn(ab, "failed to fetch vdev stop ev"); 6314 return -EPROTO; 6315 } 6316 6317 *vdev_id = le32_to_cpu(ev->vdev_id); 6318 6319 return 0; 6320 } 6321 6322 static int ath12k_wmi_tlv_mgmt_rx_parse(struct ath12k_base *ab, 6323 u16 tag, u16 len, 6324 const void *ptr, void *data) 6325 { 6326 struct wmi_tlv_mgmt_rx_parse *parse = data; 6327 6328 switch (tag) { 6329 case WMI_TAG_MGMT_RX_HDR: 6330 parse->fixed = ptr; 6331 break; 6332 case WMI_TAG_ARRAY_BYTE: 6333 if (!parse->frame_buf_done) { 6334 parse->frame_buf = ptr; 6335 parse->frame_buf_done = true; 6336 } 6337 break; 6338 } 6339 return 0; 6340 } 6341 6342 static int ath12k_pull_mgmt_rx_params_tlv(struct ath12k_base *ab, 6343 struct sk_buff *skb, 6344 struct ath12k_wmi_mgmt_rx_arg *hdr) 6345 { 6346 struct wmi_tlv_mgmt_rx_parse parse = { }; 6347 const struct ath12k_wmi_mgmt_rx_params *ev; 6348 const u8 *frame; 6349 int i, ret; 6350 6351 ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, 6352 ath12k_wmi_tlv_mgmt_rx_parse, 6353 &parse); 6354 if (ret) { 6355 ath12k_warn(ab, "failed to parse mgmt rx tlv %d\n", ret); 6356 return ret; 6357 } 6358 6359 ev = parse.fixed; 6360 frame = parse.frame_buf; 6361 6362 if (!ev || !frame) { 6363 ath12k_warn(ab, "failed to fetch mgmt rx hdr"); 6364 return -EPROTO; 6365 } 6366 6367 hdr->pdev_id = le32_to_cpu(ev->pdev_id); 6368 hdr->chan_freq = le32_to_cpu(ev->chan_freq); 6369 hdr->channel = le32_to_cpu(ev->channel); 6370 hdr->snr = le32_to_cpu(ev->snr); 6371 hdr->rate = le32_to_cpu(ev->rate); 6372 hdr->phy_mode = le32_to_cpu(ev->phy_mode); 6373 hdr->buf_len = le32_to_cpu(ev->buf_len); 6374 hdr->status = le32_to_cpu(ev->status); 6375 hdr->flags = le32_to_cpu(ev->flags); 6376 hdr->rssi = a_sle32_to_cpu(ev->rssi); 6377 hdr->tsf_delta = le32_to_cpu(ev->tsf_delta); 6378 6379 for (i = 0; i < ATH_MAX_ANTENNA; i++) 6380 hdr->rssi_ctl[i] = le32_to_cpu(ev->rssi_ctl[i]); 6381 6382 if (skb->len < (frame - skb->data) + hdr->buf_len) { 6383 ath12k_warn(ab, "invalid length in mgmt rx hdr ev"); 6384 return -EPROTO; 6385 } 6386 6387 /* shift the sk_buff to point to `frame` */ 6388 skb_trim(skb, 0); 6389 skb_put(skb, frame - skb->data); 6390 skb_pull(skb, frame - skb->data); 6391 skb_put(skb, hdr->buf_len); 6392 6393 return 0; 6394 } 6395 6396 static int wmi_process_mgmt_tx_comp(struct ath12k *ar, u32 desc_id, 6397 u32 status, u32 ack_rssi) 6398 { 6399 struct sk_buff *msdu; 6400 struct ieee80211_tx_info *info; 6401 struct ath12k_skb_cb *skb_cb; 6402 int num_mgmt; 6403 6404 spin_lock_bh(&ar->txmgmt_idr_lock); 6405 msdu = idr_find(&ar->txmgmt_idr, desc_id); 6406 6407 if (!msdu) { 6408 ath12k_warn(ar->ab, "received mgmt tx compl for invalid msdu_id: %d\n", 6409 desc_id); 6410 spin_unlock_bh(&ar->txmgmt_idr_lock); 6411 return -ENOENT; 6412 } 6413 6414 idr_remove(&ar->txmgmt_idr, desc_id); 6415 spin_unlock_bh(&ar->txmgmt_idr_lock); 6416 6417 skb_cb = ATH12K_SKB_CB(msdu); 6418 dma_unmap_single(ar->ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 6419 6420 info = IEEE80211_SKB_CB(msdu); 6421 memset(&info->status, 0, sizeof(info->status)); 6422 6423 /* skip tx rate update from ieee80211_status*/ 6424 info->status.rates[0].idx = -1; 6425 6426 if ((!(info->flags & IEEE80211_TX_CTL_NO_ACK)) && !status) { 6427 info->flags |= IEEE80211_TX_STAT_ACK; 6428 info->status.ack_signal = ack_rssi; 6429 info->status.flags |= IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; 6430 } 6431 6432 if ((info->flags & IEEE80211_TX_CTL_NO_ACK) && !status) 6433 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 6434 6435 ieee80211_tx_status_irqsafe(ath12k_ar_to_hw(ar), msdu); 6436 6437 num_mgmt = atomic_dec_if_positive(&ar->num_pending_mgmt_tx); 6438 6439 /* WARN when we received this event without doing any mgmt tx */ 6440 if (num_mgmt < 0) 6441 WARN_ON_ONCE(1); 6442 6443 if (!num_mgmt) 6444 wake_up(&ar->txmgmt_empty_waitq); 6445 6446 return 0; 6447 } 6448 6449 static int ath12k_pull_mgmt_tx_compl_param_tlv(struct ath12k_base *ab, 6450 struct sk_buff *skb, 6451 struct wmi_mgmt_tx_compl_event *param) 6452 { 6453 const void **tb; 6454 const struct wmi_mgmt_tx_compl_event *ev; 6455 int ret; 6456 6457 tb = ath12k_wmi_tlv_parse(ab, skb); 6458 if (IS_ERR(tb)) { 6459 ret = PTR_ERR(tb); 6460 ath12k_warn(ab, "failed to parse tlv: %d\n", ret); 6461 return ret; 6462 } 6463 6464 ev = tb[WMI_TAG_MGMT_TX_COMPL_EVENT]; 6465 if (!ev) { 6466 ath12k_warn(ab, "failed to fetch mgmt tx compl ev"); 6467 return -EPROTO; 6468 } 6469 6470 param->pdev_id = ev->pdev_id; 6471 param->desc_id = ev->desc_id; 6472 param->status = ev->status; 6473 param->ppdu_id = ev->ppdu_id; 6474 param->ack_rssi = ev->ack_rssi; 6475 6476 return 0; 6477 } 6478 6479 static void ath12k_wmi_event_scan_started(struct ath12k *ar) 6480 { 6481 lockdep_assert_held(&ar->data_lock); 6482 6483 switch (ar->scan.state) { 6484 case ATH12K_SCAN_IDLE: 6485 case ATH12K_SCAN_RUNNING: 6486 case ATH12K_SCAN_ABORTING: 6487 ath12k_warn(ar->ab, "received scan started event in an invalid scan state: %s (%d)\n", 6488 ath12k_scan_state_str(ar->scan.state), 6489 ar->scan.state); 6490 break; 6491 case ATH12K_SCAN_STARTING: 6492 ar->scan.state = ATH12K_SCAN_RUNNING; 6493 6494 if (ar->scan.is_roc) 6495 ieee80211_ready_on_channel(ath12k_ar_to_hw(ar)); 6496 6497 complete(&ar->scan.started); 6498 break; 6499 } 6500 } 6501 6502 static void ath12k_wmi_event_scan_start_failed(struct ath12k *ar) 6503 { 6504 lockdep_assert_held(&ar->data_lock); 6505 6506 switch (ar->scan.state) { 6507 case ATH12K_SCAN_IDLE: 6508 case ATH12K_SCAN_RUNNING: 6509 case ATH12K_SCAN_ABORTING: 6510 ath12k_warn(ar->ab, "received scan start failed event in an invalid scan state: %s (%d)\n", 6511 ath12k_scan_state_str(ar->scan.state), 6512 ar->scan.state); 6513 break; 6514 case ATH12K_SCAN_STARTING: 6515 complete(&ar->scan.started); 6516 __ath12k_mac_scan_finish(ar); 6517 break; 6518 } 6519 } 6520 6521 static void ath12k_wmi_event_scan_completed(struct ath12k *ar) 6522 { 6523 lockdep_assert_held(&ar->data_lock); 6524 6525 switch (ar->scan.state) { 6526 case ATH12K_SCAN_IDLE: 6527 case ATH12K_SCAN_STARTING: 6528 /* One suspected reason scan can be completed while starting is 6529 * if firmware fails to deliver all scan events to the host, 6530 * e.g. when transport pipe is full. This has been observed 6531 * with spectral scan phyerr events starving wmi transport 6532 * pipe. In such case the "scan completed" event should be (and 6533 * is) ignored by the host as it may be just firmware's scan 6534 * state machine recovering. 6535 */ 6536 ath12k_warn(ar->ab, "received scan completed event in an invalid scan state: %s (%d)\n", 6537 ath12k_scan_state_str(ar->scan.state), 6538 ar->scan.state); 6539 break; 6540 case ATH12K_SCAN_RUNNING: 6541 case ATH12K_SCAN_ABORTING: 6542 __ath12k_mac_scan_finish(ar); 6543 break; 6544 } 6545 } 6546 6547 static void ath12k_wmi_event_scan_bss_chan(struct ath12k *ar) 6548 { 6549 lockdep_assert_held(&ar->data_lock); 6550 6551 switch (ar->scan.state) { 6552 case ATH12K_SCAN_IDLE: 6553 case ATH12K_SCAN_STARTING: 6554 ath12k_warn(ar->ab, "received scan bss chan event in an invalid scan state: %s (%d)\n", 6555 ath12k_scan_state_str(ar->scan.state), 6556 ar->scan.state); 6557 break; 6558 case ATH12K_SCAN_RUNNING: 6559 case ATH12K_SCAN_ABORTING: 6560 ar->scan_channel = NULL; 6561 break; 6562 } 6563 } 6564 6565 static void ath12k_wmi_event_scan_foreign_chan(struct ath12k *ar, u32 freq) 6566 { 6567 struct ieee80211_hw *hw = ath12k_ar_to_hw(ar); 6568 6569 lockdep_assert_held(&ar->data_lock); 6570 6571 switch (ar->scan.state) { 6572 case ATH12K_SCAN_IDLE: 6573 case ATH12K_SCAN_STARTING: 6574 ath12k_warn(ar->ab, "received scan foreign chan event in an invalid scan state: %s (%d)\n", 6575 ath12k_scan_state_str(ar->scan.state), 6576 ar->scan.state); 6577 break; 6578 case ATH12K_SCAN_RUNNING: 6579 case ATH12K_SCAN_ABORTING: 6580 ar->scan_channel = ieee80211_get_channel(hw->wiphy, freq); 6581 6582 if (ar->scan.is_roc && ar->scan.roc_freq == freq) 6583 complete(&ar->scan.on_channel); 6584 6585 break; 6586 } 6587 } 6588 6589 static const char * 6590 ath12k_wmi_event_scan_type_str(enum wmi_scan_event_type type, 6591 enum wmi_scan_completion_reason reason) 6592 { 6593 switch (type) { 6594 case WMI_SCAN_EVENT_STARTED: 6595 return "started"; 6596 case WMI_SCAN_EVENT_COMPLETED: 6597 switch (reason) { 6598 case WMI_SCAN_REASON_COMPLETED: 6599 return "completed"; 6600 case WMI_SCAN_REASON_CANCELLED: 6601 return "completed [cancelled]"; 6602 case WMI_SCAN_REASON_PREEMPTED: 6603 return "completed [preempted]"; 6604 case WMI_SCAN_REASON_TIMEDOUT: 6605 return "completed [timedout]"; 6606 case WMI_SCAN_REASON_INTERNAL_FAILURE: 6607 return "completed [internal err]"; 6608 case WMI_SCAN_REASON_MAX: 6609 break; 6610 } 6611 return "completed [unknown]"; 6612 case WMI_SCAN_EVENT_BSS_CHANNEL: 6613 return "bss channel"; 6614 case WMI_SCAN_EVENT_FOREIGN_CHAN: 6615 return "foreign channel"; 6616 case WMI_SCAN_EVENT_DEQUEUED: 6617 return "dequeued"; 6618 case WMI_SCAN_EVENT_PREEMPTED: 6619 return "preempted"; 6620 case WMI_SCAN_EVENT_START_FAILED: 6621 return "start failed"; 6622 case WMI_SCAN_EVENT_RESTARTED: 6623 return "restarted"; 6624 case WMI_SCAN_EVENT_FOREIGN_CHAN_EXIT: 6625 return "foreign channel exit"; 6626 default: 6627 return "unknown"; 6628 } 6629 } 6630 6631 static int ath12k_pull_scan_ev(struct ath12k_base *ab, struct sk_buff *skb, 6632 struct wmi_scan_event *scan_evt_param) 6633 { 6634 const void **tb; 6635 const struct wmi_scan_event *ev; 6636 int ret; 6637 6638 tb = ath12k_wmi_tlv_parse(ab, skb); 6639 if (IS_ERR(tb)) { 6640 ret = PTR_ERR(tb); 6641 ath12k_warn(ab, "failed to parse tlv: %d\n", ret); 6642 return ret; 6643 } 6644 6645 ev = tb[WMI_TAG_SCAN_EVENT]; 6646 if (!ev) { 6647 ath12k_warn(ab, "failed to fetch scan ev"); 6648 return -EPROTO; 6649 } 6650 6651 scan_evt_param->event_type = ev->event_type; 6652 scan_evt_param->reason = ev->reason; 6653 scan_evt_param->channel_freq = ev->channel_freq; 6654 scan_evt_param->scan_req_id = ev->scan_req_id; 6655 scan_evt_param->scan_id = ev->scan_id; 6656 scan_evt_param->vdev_id = ev->vdev_id; 6657 scan_evt_param->tsf_timestamp = ev->tsf_timestamp; 6658 6659 return 0; 6660 } 6661 6662 static int ath12k_pull_peer_sta_kickout_ev(struct ath12k_base *ab, struct sk_buff *skb, 6663 struct wmi_peer_sta_kickout_arg *arg) 6664 { 6665 const void **tb; 6666 const struct wmi_peer_sta_kickout_event *ev; 6667 int ret; 6668 6669 tb = ath12k_wmi_tlv_parse(ab, skb); 6670 if (IS_ERR(tb)) { 6671 ret = PTR_ERR(tb); 6672 ath12k_warn(ab, "failed to parse tlv: %d\n", ret); 6673 return ret; 6674 } 6675 6676 ev = tb[WMI_TAG_PEER_STA_KICKOUT_EVENT]; 6677 if (!ev) { 6678 ath12k_warn(ab, "failed to fetch peer sta kickout ev"); 6679 return -EPROTO; 6680 } 6681 6682 arg->mac_addr = ev->peer_macaddr.addr; 6683 arg->reason = le32_to_cpu(ev->reason); 6684 arg->rssi = le32_to_cpu(ev->rssi); 6685 6686 return 0; 6687 } 6688 6689 static int ath12k_pull_roam_ev(struct ath12k_base *ab, struct sk_buff *skb, 6690 struct wmi_roam_event *roam_ev) 6691 { 6692 const void **tb; 6693 const struct wmi_roam_event *ev; 6694 int ret; 6695 6696 tb = ath12k_wmi_tlv_parse(ab, skb); 6697 if (IS_ERR(tb)) { 6698 ret = PTR_ERR(tb); 6699 ath12k_warn(ab, "failed to parse tlv: %d\n", ret); 6700 return ret; 6701 } 6702 6703 ev = tb[WMI_TAG_ROAM_EVENT]; 6704 if (!ev) { 6705 ath12k_warn(ab, "failed to fetch roam ev"); 6706 return -EPROTO; 6707 } 6708 6709 roam_ev->vdev_id = ev->vdev_id; 6710 roam_ev->reason = ev->reason; 6711 roam_ev->rssi = ev->rssi; 6712 6713 return 0; 6714 } 6715 6716 static int freq_to_idx(struct ath12k *ar, int freq) 6717 { 6718 struct ieee80211_supported_band *sband; 6719 struct ieee80211_hw *hw = ath12k_ar_to_hw(ar); 6720 int band, ch, idx = 0; 6721 6722 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 6723 if (!ar->mac.sbands[band].channels) 6724 continue; 6725 6726 sband = hw->wiphy->bands[band]; 6727 if (!sband) 6728 continue; 6729 6730 for (ch = 0; ch < sband->n_channels; ch++, idx++) 6731 if (sband->channels[ch].center_freq == freq) 6732 goto exit; 6733 } 6734 6735 exit: 6736 return idx; 6737 } 6738 6739 static int ath12k_pull_chan_info_ev(struct ath12k_base *ab, struct sk_buff *skb, 6740 struct wmi_chan_info_event *ch_info_ev) 6741 { 6742 const void **tb; 6743 const struct wmi_chan_info_event *ev; 6744 int ret; 6745 6746 tb = ath12k_wmi_tlv_parse(ab, skb); 6747 if (IS_ERR(tb)) { 6748 ret = PTR_ERR(tb); 6749 ath12k_warn(ab, "failed to parse tlv: %d\n", ret); 6750 return ret; 6751 } 6752 6753 ev = tb[WMI_TAG_CHAN_INFO_EVENT]; 6754 if (!ev) { 6755 ath12k_warn(ab, "failed to fetch chan info ev"); 6756 return -EPROTO; 6757 } 6758 6759 ch_info_ev->err_code = ev->err_code; 6760 ch_info_ev->freq = ev->freq; 6761 ch_info_ev->cmd_flags = ev->cmd_flags; 6762 ch_info_ev->noise_floor = ev->noise_floor; 6763 ch_info_ev->rx_clear_count = ev->rx_clear_count; 6764 ch_info_ev->cycle_count = ev->cycle_count; 6765 ch_info_ev->chan_tx_pwr_range = ev->chan_tx_pwr_range; 6766 ch_info_ev->chan_tx_pwr_tp = ev->chan_tx_pwr_tp; 6767 ch_info_ev->rx_frame_count = ev->rx_frame_count; 6768 ch_info_ev->tx_frame_cnt = ev->tx_frame_cnt; 6769 ch_info_ev->mac_clk_mhz = ev->mac_clk_mhz; 6770 ch_info_ev->vdev_id = ev->vdev_id; 6771 6772 return 0; 6773 } 6774 6775 static int 6776 ath12k_pull_pdev_bss_chan_info_ev(struct ath12k_base *ab, struct sk_buff *skb, 6777 struct wmi_pdev_bss_chan_info_event *bss_ch_info_ev) 6778 { 6779 const void **tb; 6780 const struct wmi_pdev_bss_chan_info_event *ev; 6781 int ret; 6782 6783 tb = ath12k_wmi_tlv_parse(ab, skb); 6784 if (IS_ERR(tb)) { 6785 ret = PTR_ERR(tb); 6786 ath12k_warn(ab, "failed to parse tlv: %d\n", ret); 6787 return ret; 6788 } 6789 6790 ev = tb[WMI_TAG_PDEV_BSS_CHAN_INFO_EVENT]; 6791 if (!ev) { 6792 ath12k_warn(ab, "failed to fetch pdev bss chan info ev"); 6793 return -EPROTO; 6794 } 6795 6796 bss_ch_info_ev->pdev_id = ev->pdev_id; 6797 bss_ch_info_ev->freq = ev->freq; 6798 bss_ch_info_ev->noise_floor = ev->noise_floor; 6799 bss_ch_info_ev->rx_clear_count_low = ev->rx_clear_count_low; 6800 bss_ch_info_ev->rx_clear_count_high = ev->rx_clear_count_high; 6801 bss_ch_info_ev->cycle_count_low = ev->cycle_count_low; 6802 bss_ch_info_ev->cycle_count_high = ev->cycle_count_high; 6803 bss_ch_info_ev->tx_cycle_count_low = ev->tx_cycle_count_low; 6804 bss_ch_info_ev->tx_cycle_count_high = ev->tx_cycle_count_high; 6805 bss_ch_info_ev->rx_cycle_count_low = ev->rx_cycle_count_low; 6806 bss_ch_info_ev->rx_cycle_count_high = ev->rx_cycle_count_high; 6807 bss_ch_info_ev->rx_bss_cycle_count_low = ev->rx_bss_cycle_count_low; 6808 bss_ch_info_ev->rx_bss_cycle_count_high = ev->rx_bss_cycle_count_high; 6809 6810 return 0; 6811 } 6812 6813 static int 6814 ath12k_pull_vdev_install_key_compl_ev(struct ath12k_base *ab, struct sk_buff *skb, 6815 struct wmi_vdev_install_key_complete_arg *arg) 6816 { 6817 const void **tb; 6818 const struct wmi_vdev_install_key_compl_event *ev; 6819 int ret; 6820 6821 tb = ath12k_wmi_tlv_parse(ab, skb); 6822 if (IS_ERR(tb)) { 6823 ret = PTR_ERR(tb); 6824 ath12k_warn(ab, "failed to parse tlv: %d\n", ret); 6825 return ret; 6826 } 6827 6828 ev = tb[WMI_TAG_VDEV_INSTALL_KEY_COMPLETE_EVENT]; 6829 if (!ev) { 6830 ath12k_warn(ab, "failed to fetch vdev install key compl ev"); 6831 return -EPROTO; 6832 } 6833 6834 arg->vdev_id = le32_to_cpu(ev->vdev_id); 6835 arg->macaddr = ev->peer_macaddr.addr; 6836 arg->key_idx = le32_to_cpu(ev->key_idx); 6837 arg->key_flags = le32_to_cpu(ev->key_flags); 6838 arg->status = le32_to_cpu(ev->status); 6839 6840 return 0; 6841 } 6842 6843 static int ath12k_pull_peer_assoc_conf_ev(struct ath12k_base *ab, struct sk_buff *skb, 6844 struct wmi_peer_assoc_conf_arg *peer_assoc_conf) 6845 { 6846 const void **tb; 6847 const struct wmi_peer_assoc_conf_event *ev; 6848 int ret; 6849 6850 tb = ath12k_wmi_tlv_parse(ab, skb); 6851 if (IS_ERR(tb)) { 6852 ret = PTR_ERR(tb); 6853 ath12k_warn(ab, "failed to parse tlv: %d\n", ret); 6854 return ret; 6855 } 6856 6857 ev = tb[WMI_TAG_PEER_ASSOC_CONF_EVENT]; 6858 if (!ev) { 6859 ath12k_warn(ab, "failed to fetch peer assoc conf ev"); 6860 return -EPROTO; 6861 } 6862 6863 peer_assoc_conf->vdev_id = le32_to_cpu(ev->vdev_id); 6864 peer_assoc_conf->macaddr = ev->peer_macaddr.addr; 6865 6866 return 0; 6867 } 6868 6869 static void ath12k_wmi_op_ep_tx_credits(struct ath12k_base *ab) 6870 { 6871 /* try to send pending beacons first. they take priority */ 6872 wake_up(&ab->wmi_ab.tx_credits_wq); 6873 } 6874 6875 static int ath12k_reg_11d_new_cc_event(struct ath12k_base *ab, struct sk_buff *skb) 6876 { 6877 const struct wmi_11d_new_cc_event *ev; 6878 struct ath12k *ar; 6879 struct ath12k_pdev *pdev; 6880 const void **tb; 6881 int ret, i; 6882 6883 tb = ath12k_wmi_tlv_parse(ab, skb); 6884 if (IS_ERR(tb)) { 6885 ret = PTR_ERR(tb); 6886 ath12k_warn(ab, "failed to parse tlv: %d\n", ret); 6887 return ret; 6888 } 6889 6890 ev = tb[WMI_TAG_11D_NEW_COUNTRY_EVENT]; 6891 if (!ev) { 6892 ath12k_warn(ab, "failed to fetch 11d new cc ev"); 6893 return -EPROTO; 6894 } 6895 6896 spin_lock_bh(&ab->base_lock); 6897 memcpy(&ab->new_alpha2, &ev->new_alpha2, REG_ALPHA2_LEN); 6898 spin_unlock_bh(&ab->base_lock); 6899 6900 ath12k_dbg(ab, ATH12K_DBG_WMI, "wmi 11d new cc %c%c\n", 6901 ab->new_alpha2[0], 6902 ab->new_alpha2[1]); 6903 6904 for (i = 0; i < ab->num_radios; i++) { 6905 pdev = &ab->pdevs[i]; 6906 ar = pdev->ar; 6907 ar->state_11d = ATH12K_11D_IDLE; 6908 ar->ah->regd_updated = false; 6909 complete(&ar->completed_11d_scan); 6910 } 6911 6912 queue_work(ab->workqueue, &ab->update_11d_work); 6913 6914 return 0; 6915 } 6916 6917 static void ath12k_wmi_htc_tx_complete(struct ath12k_base *ab, 6918 struct sk_buff *skb) 6919 { 6920 dev_kfree_skb(skb); 6921 } 6922 6923 static int ath12k_reg_chan_list_event(struct ath12k_base *ab, struct sk_buff *skb) 6924 { 6925 struct ath12k_reg_info *reg_info; 6926 struct ath12k *ar = NULL; 6927 u8 pdev_idx = 255; 6928 int ret; 6929 6930 reg_info = kzalloc_obj(*reg_info, GFP_ATOMIC); 6931 if (!reg_info) { 6932 ret = -ENOMEM; 6933 goto fallback; 6934 } 6935 6936 ret = ath12k_pull_reg_chan_list_ext_update_ev(ab, skb, reg_info); 6937 if (ret) { 6938 ath12k_warn(ab, "failed to extract regulatory info from received event\n"); 6939 goto mem_free; 6940 } 6941 6942 ret = ath12k_reg_validate_reg_info(ab, reg_info); 6943 if (ret == ATH12K_REG_STATUS_FALLBACK) { 6944 ath12k_warn(ab, "failed to validate reg info %d\n", ret); 6945 /* firmware has successfully switches to new regd but host can not 6946 * continue, so free reginfo and fallback to old regd 6947 */ 6948 goto mem_free; 6949 } else if (ret == ATH12K_REG_STATUS_DROP) { 6950 /* reg info is valid but we will not store it and 6951 * not going to create new regd for it 6952 */ 6953 ret = ATH12K_REG_STATUS_VALID; 6954 goto mem_free; 6955 } 6956 6957 /* free old reg_info if it exist */ 6958 pdev_idx = reg_info->phy_id; 6959 if (ab->reg_info[pdev_idx]) { 6960 ath12k_reg_reset_reg_info(ab->reg_info[pdev_idx]); 6961 kfree(ab->reg_info[pdev_idx]); 6962 } 6963 /* reg_info is valid, we store it for later use 6964 * even below regd build failed 6965 */ 6966 ab->reg_info[pdev_idx] = reg_info; 6967 6968 ret = ath12k_reg_handle_chan_list(ab, reg_info, WMI_VDEV_TYPE_UNSPEC, 6969 IEEE80211_REG_UNSET_AP); 6970 if (ret) { 6971 ath12k_warn(ab, "failed to handle chan list %d\n", ret); 6972 goto fallback; 6973 } 6974 6975 goto out; 6976 6977 mem_free: 6978 ath12k_reg_reset_reg_info(reg_info); 6979 kfree(reg_info); 6980 6981 if (ret == ATH12K_REG_STATUS_VALID) 6982 goto out; 6983 6984 fallback: 6985 /* Fallback to older reg (by sending previous country setting 6986 * again if fw has succeeded and we failed to process here. 6987 * The Regdomain should be uniform across driver and fw. Since the 6988 * FW has processed the command and sent a success status, we expect 6989 * this function to succeed as well. If it doesn't, CTRY needs to be 6990 * reverted at the fw and the old SCAN_CHAN_LIST cmd needs to be sent. 6991 */ 6992 /* TODO: This is rare, but still should also be handled */ 6993 WARN_ON(1); 6994 6995 out: 6996 /* In some error cases, even a valid pdev_idx might not be available */ 6997 if (pdev_idx != 255) 6998 ar = ab->pdevs[pdev_idx].ar; 6999 7000 /* During the boot-time update, 'ar' might not be allocated, 7001 * so the completion cannot be marked at that point. 7002 * This boot-time update is handled in ath12k_mac_hw_register() 7003 * before registering the hardware. 7004 */ 7005 if (ar) 7006 complete_all(&ar->regd_update_completed); 7007 7008 return ret; 7009 } 7010 7011 static int ath12k_wmi_rdy_parse(struct ath12k_base *ab, u16 tag, u16 len, 7012 const void *ptr, void *data) 7013 { 7014 struct ath12k_wmi_rdy_parse *rdy_parse = data; 7015 struct wmi_ready_event fixed_param; 7016 struct ath12k_wmi_mac_addr_params *addr_list; 7017 struct ath12k_pdev *pdev; 7018 u32 num_mac_addr; 7019 int i; 7020 7021 switch (tag) { 7022 case WMI_TAG_READY_EVENT: 7023 memset(&fixed_param, 0, sizeof(fixed_param)); 7024 memcpy(&fixed_param, (struct wmi_ready_event *)ptr, 7025 min_t(u16, sizeof(fixed_param), len)); 7026 ab->wlan_init_status = le32_to_cpu(fixed_param.ready_event_min.status); 7027 rdy_parse->num_extra_mac_addr = 7028 le32_to_cpu(fixed_param.ready_event_min.num_extra_mac_addr); 7029 7030 ether_addr_copy(ab->mac_addr, 7031 fixed_param.ready_event_min.mac_addr.addr); 7032 ab->pktlog_defs_checksum = le32_to_cpu(fixed_param.pktlog_defs_checksum); 7033 ab->wmi_ready = true; 7034 break; 7035 case WMI_TAG_ARRAY_FIXED_STRUCT: 7036 addr_list = (struct ath12k_wmi_mac_addr_params *)ptr; 7037 num_mac_addr = rdy_parse->num_extra_mac_addr; 7038 7039 if (!(ab->num_radios > 1 && num_mac_addr >= ab->num_radios)) 7040 break; 7041 7042 for (i = 0; i < ab->num_radios; i++) { 7043 pdev = &ab->pdevs[i]; 7044 ether_addr_copy(pdev->mac_addr, addr_list[i].addr); 7045 } 7046 ab->pdevs_macaddr_valid = true; 7047 break; 7048 default: 7049 break; 7050 } 7051 7052 return 0; 7053 } 7054 7055 static int ath12k_ready_event(struct ath12k_base *ab, struct sk_buff *skb) 7056 { 7057 struct ath12k_wmi_rdy_parse rdy_parse = { }; 7058 int ret; 7059 7060 ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, 7061 ath12k_wmi_rdy_parse, &rdy_parse); 7062 if (ret) { 7063 ath12k_warn(ab, "failed to parse tlv %d\n", ret); 7064 return ret; 7065 } 7066 7067 complete(&ab->wmi_ab.unified_ready); 7068 return 0; 7069 } 7070 7071 static void ath12k_peer_delete_resp_event(struct ath12k_base *ab, struct sk_buff *skb) 7072 { 7073 struct wmi_peer_delete_resp_event peer_del_resp; 7074 struct ath12k *ar; 7075 7076 if (ath12k_pull_peer_del_resp_ev(ab, skb, &peer_del_resp) != 0) { 7077 ath12k_warn(ab, "failed to extract peer delete resp"); 7078 return; 7079 } 7080 7081 rcu_read_lock(); 7082 ar = ath12k_mac_get_ar_by_vdev_id(ab, le32_to_cpu(peer_del_resp.vdev_id)); 7083 if (!ar) { 7084 ath12k_warn(ab, "invalid vdev id in peer delete resp ev %d", 7085 peer_del_resp.vdev_id); 7086 rcu_read_unlock(); 7087 return; 7088 } 7089 7090 complete(&ar->peer_delete_done); 7091 rcu_read_unlock(); 7092 ath12k_dbg(ab, ATH12K_DBG_WMI, "peer delete resp for vdev id %d addr %pM\n", 7093 peer_del_resp.vdev_id, peer_del_resp.peer_macaddr.addr); 7094 } 7095 7096 static void ath12k_vdev_delete_resp_event(struct ath12k_base *ab, 7097 struct sk_buff *skb) 7098 { 7099 struct ath12k *ar; 7100 u32 vdev_id = 0; 7101 7102 if (ath12k_pull_vdev_del_resp_ev(ab, skb, &vdev_id) != 0) { 7103 ath12k_warn(ab, "failed to extract vdev delete resp"); 7104 return; 7105 } 7106 7107 rcu_read_lock(); 7108 ar = ath12k_mac_get_ar_by_vdev_id(ab, vdev_id); 7109 if (!ar) { 7110 ath12k_warn(ab, "invalid vdev id in vdev delete resp ev %d", 7111 vdev_id); 7112 rcu_read_unlock(); 7113 return; 7114 } 7115 7116 complete(&ar->vdev_delete_done); 7117 7118 rcu_read_unlock(); 7119 7120 ath12k_dbg(ab, ATH12K_DBG_WMI, "vdev delete resp for vdev id %d\n", 7121 vdev_id); 7122 } 7123 7124 static const char *ath12k_wmi_vdev_resp_print(u32 vdev_resp_status) 7125 { 7126 switch (vdev_resp_status) { 7127 case WMI_VDEV_START_RESPONSE_INVALID_VDEVID: 7128 return "invalid vdev id"; 7129 case WMI_VDEV_START_RESPONSE_NOT_SUPPORTED: 7130 return "not supported"; 7131 case WMI_VDEV_START_RESPONSE_DFS_VIOLATION: 7132 return "dfs violation"; 7133 case WMI_VDEV_START_RESPONSE_INVALID_REGDOMAIN: 7134 return "invalid regdomain"; 7135 default: 7136 return "unknown"; 7137 } 7138 } 7139 7140 static void ath12k_vdev_start_resp_event(struct ath12k_base *ab, struct sk_buff *skb) 7141 { 7142 struct wmi_vdev_start_resp_event vdev_start_resp; 7143 struct ath12k *ar; 7144 u32 status; 7145 7146 if (ath12k_pull_vdev_start_resp_tlv(ab, skb, &vdev_start_resp) != 0) { 7147 ath12k_warn(ab, "failed to extract vdev start resp"); 7148 return; 7149 } 7150 7151 rcu_read_lock(); 7152 ar = ath12k_mac_get_ar_by_vdev_id(ab, le32_to_cpu(vdev_start_resp.vdev_id)); 7153 if (!ar) { 7154 ath12k_warn(ab, "invalid vdev id in vdev start resp ev %d", 7155 vdev_start_resp.vdev_id); 7156 rcu_read_unlock(); 7157 return; 7158 } 7159 7160 ar->last_wmi_vdev_start_status = 0; 7161 7162 status = le32_to_cpu(vdev_start_resp.status); 7163 if (WARN_ON_ONCE(status)) { 7164 ath12k_warn(ab, "vdev start resp error status %d (%s)\n", 7165 status, ath12k_wmi_vdev_resp_print(status)); 7166 ar->last_wmi_vdev_start_status = status; 7167 } 7168 7169 ar->max_allowed_tx_power = (s8)le32_to_cpu(vdev_start_resp.max_allowed_tx_power); 7170 7171 complete(&ar->vdev_setup_done); 7172 7173 rcu_read_unlock(); 7174 7175 ath12k_dbg(ab, ATH12K_DBG_WMI, "vdev start resp for vdev id %d", 7176 vdev_start_resp.vdev_id); 7177 } 7178 7179 static void ath12k_bcn_tx_status_event(struct ath12k_base *ab, struct sk_buff *skb) 7180 { 7181 struct ath12k_link_vif *arvif; 7182 struct ath12k *ar; 7183 u32 vdev_id, tx_status; 7184 7185 if (ath12k_pull_bcn_tx_status_ev(ab, skb, &vdev_id, &tx_status) != 0) { 7186 ath12k_warn(ab, "failed to extract bcn tx status"); 7187 return; 7188 } 7189 7190 guard(rcu)(); 7191 7192 arvif = ath12k_mac_get_arvif_by_vdev_id(ab, vdev_id); 7193 if (!arvif) { 7194 ath12k_warn(ab, "invalid vdev %u in bcn tx status\n", 7195 vdev_id); 7196 return; 7197 } 7198 7199 ar = arvif->ar; 7200 wiphy_work_queue(ath12k_ar_to_hw(ar)->wiphy, &arvif->bcn_tx_work); 7201 } 7202 7203 static void ath12k_vdev_stopped_event(struct ath12k_base *ab, struct sk_buff *skb) 7204 { 7205 struct ath12k *ar; 7206 u32 vdev_id = 0; 7207 7208 if (ath12k_pull_vdev_stopped_param_tlv(ab, skb, &vdev_id) != 0) { 7209 ath12k_warn(ab, "failed to extract vdev stopped event"); 7210 return; 7211 } 7212 7213 rcu_read_lock(); 7214 ar = ath12k_mac_get_ar_by_vdev_id(ab, vdev_id); 7215 if (!ar) { 7216 ath12k_warn(ab, "invalid vdev id in vdev stopped ev %d", 7217 vdev_id); 7218 rcu_read_unlock(); 7219 return; 7220 } 7221 7222 complete(&ar->vdev_setup_done); 7223 7224 rcu_read_unlock(); 7225 7226 ath12k_dbg(ab, ATH12K_DBG_WMI, "vdev stopped for vdev id %d", vdev_id); 7227 } 7228 7229 static void ath12k_mgmt_rx_event(struct ath12k_base *ab, struct sk_buff *skb) 7230 { 7231 struct ath12k_wmi_mgmt_rx_arg rx_ev = {}; 7232 struct ath12k *ar; 7233 struct ieee80211_rx_status *status = IEEE80211_SKB_RXCB(skb); 7234 struct ieee80211_sta *pubsta = NULL; 7235 struct ath12k_dp_link_peer *peer; 7236 struct ieee80211_hdr *hdr; 7237 bool is_4addr_null_pkt; 7238 struct ath12k_dp *dp; 7239 u16 fc; 7240 struct ieee80211_supported_band *sband; 7241 s32 noise_floor; 7242 7243 if (ath12k_pull_mgmt_rx_params_tlv(ab, skb, &rx_ev) != 0) { 7244 ath12k_warn(ab, "failed to extract mgmt rx event"); 7245 dev_kfree_skb(skb); 7246 return; 7247 } 7248 7249 memset(status, 0, sizeof(*status)); 7250 7251 ath12k_dbg(ab, ATH12K_DBG_MGMT, "mgmt rx event status %08x\n", 7252 rx_ev.status); 7253 7254 rcu_read_lock(); 7255 ar = ath12k_mac_get_ar_by_pdev_id(ab, rx_ev.pdev_id); 7256 7257 if (!ar) { 7258 ath12k_warn(ab, "invalid pdev_id %d in mgmt_rx_event\n", 7259 rx_ev.pdev_id); 7260 dev_kfree_skb(skb); 7261 goto exit; 7262 } 7263 7264 if ((test_bit(ATH12K_FLAG_CAC_RUNNING, &ar->dev_flags)) || 7265 (rx_ev.status & (WMI_RX_STATUS_ERR_DECRYPT | 7266 WMI_RX_STATUS_ERR_KEY_CACHE_MISS | 7267 WMI_RX_STATUS_ERR_CRC))) { 7268 dev_kfree_skb(skb); 7269 goto exit; 7270 } 7271 7272 if (rx_ev.status & WMI_RX_STATUS_ERR_MIC) 7273 status->flag |= RX_FLAG_MMIC_ERROR; 7274 7275 if (rx_ev.chan_freq >= ATH12K_MIN_6GHZ_FREQ && 7276 rx_ev.chan_freq <= ATH12K_MAX_6GHZ_FREQ) { 7277 status->band = NL80211_BAND_6GHZ; 7278 status->freq = rx_ev.chan_freq; 7279 } else if (rx_ev.channel >= 1 && rx_ev.channel <= 14) { 7280 status->band = NL80211_BAND_2GHZ; 7281 } else if (rx_ev.channel >= 36 && rx_ev.channel <= ATH12K_MAX_5GHZ_CHAN) { 7282 status->band = NL80211_BAND_5GHZ; 7283 } else { 7284 /* Shouldn't happen unless list of advertised channels to 7285 * mac80211 has been changed. 7286 */ 7287 WARN_ON_ONCE(1); 7288 dev_kfree_skb(skb); 7289 goto exit; 7290 } 7291 7292 if (rx_ev.phy_mode == MODE_11B && 7293 (status->band == NL80211_BAND_5GHZ || status->band == NL80211_BAND_6GHZ)) 7294 ath12k_dbg(ab, ATH12K_DBG_WMI, 7295 "wmi mgmt rx 11b (CCK) on 5/6GHz, band = %d\n", status->band); 7296 7297 sband = &ar->mac.sbands[status->band]; 7298 7299 if (status->band != NL80211_BAND_6GHZ) 7300 status->freq = ieee80211_channel_to_frequency(rx_ev.channel, 7301 status->band); 7302 7303 spin_lock_bh(&ar->data_lock); 7304 noise_floor = ath12k_pdev_get_noise_floor(ar); 7305 spin_unlock_bh(&ar->data_lock); 7306 7307 status->signal = rx_ev.snr + noise_floor; 7308 status->rate_idx = ath12k_mac_bitrate_to_idx(sband, rx_ev.rate / 100); 7309 7310 hdr = (struct ieee80211_hdr *)skb->data; 7311 fc = le16_to_cpu(hdr->frame_control); 7312 7313 is_4addr_null_pkt = (ieee80211_is_nullfunc(hdr->frame_control) || 7314 ieee80211_is_qos_nullfunc(hdr->frame_control)) && 7315 ieee80211_has_a4(hdr->frame_control); 7316 7317 /* 7318 * Add check to drop frames other than 4-address NULL frame. Since 7319 * firmware sends all NULL frames in this path (3-address and 4-address) 7320 */ 7321 if (ieee80211_is_data(hdr->frame_control) && !is_4addr_null_pkt) { 7322 dev_kfree_skb(skb); 7323 goto exit; 7324 } 7325 7326 if (is_4addr_null_pkt) { 7327 dp = ath12k_ab_to_dp(ar->ab); 7328 spin_lock_bh(&dp->dp_lock); 7329 peer = ath12k_dp_link_peer_find_by_pdev_and_addr(dp, ar->pdev_idx, 7330 hdr->addr2); 7331 if (!peer) { 7332 spin_unlock_bh(&dp->dp_lock); 7333 dev_kfree_skb(skb); 7334 goto exit; 7335 } 7336 pubsta = peer->sta; 7337 if (pubsta && pubsta->valid_links) { 7338 status->link_valid = 1; 7339 status->link_id = peer->link_id; 7340 } 7341 spin_unlock_bh(&dp->dp_lock); 7342 goto send_rx; 7343 } 7344 7345 /* Firmware is guaranteed to report all essential management frames via 7346 * WMI while it can deliver some extra via HTT. Since there can be 7347 * duplicates split the reporting wrt monitor/sniffing. 7348 */ 7349 status->flag |= RX_FLAG_SKIP_MONITOR; 7350 7351 /* In case of PMF, FW delivers decrypted frames with Protected Bit set 7352 * including group privacy action frames. 7353 */ 7354 if (ieee80211_has_protected(hdr->frame_control)) { 7355 status->flag |= RX_FLAG_DECRYPTED; 7356 7357 if (!ieee80211_is_robust_mgmt_frame(skb)) { 7358 status->flag |= RX_FLAG_IV_STRIPPED | 7359 RX_FLAG_MMIC_STRIPPED; 7360 hdr->frame_control = __cpu_to_le16(fc & 7361 ~IEEE80211_FCTL_PROTECTED); 7362 } 7363 } 7364 7365 if (ieee80211_is_beacon(hdr->frame_control)) 7366 ath12k_mac_handle_beacon(ar, skb); 7367 7368 send_rx: 7369 ath12k_dbg(ab, ATH12K_DBG_MGMT, 7370 "event mgmt rx skb %p len %d ftype %02x stype %02x\n", 7371 skb, skb->len, 7372 fc & IEEE80211_FCTL_FTYPE, fc & IEEE80211_FCTL_STYPE); 7373 7374 ath12k_dbg(ab, ATH12K_DBG_MGMT, 7375 "event mgmt rx freq %d band %d snr %d, rate_idx %d\n", 7376 status->freq, status->band, status->signal, 7377 status->rate_idx); 7378 7379 ieee80211_rx_ni(ath12k_ar_to_hw(ar), skb); 7380 7381 exit: 7382 rcu_read_unlock(); 7383 } 7384 7385 static void ath12k_mgmt_tx_compl_event(struct ath12k_base *ab, struct sk_buff *skb) 7386 { 7387 struct wmi_mgmt_tx_compl_event tx_compl_param = {}; 7388 struct ath12k *ar; 7389 7390 if (ath12k_pull_mgmt_tx_compl_param_tlv(ab, skb, &tx_compl_param) != 0) { 7391 ath12k_warn(ab, "failed to extract mgmt tx compl event"); 7392 return; 7393 } 7394 7395 rcu_read_lock(); 7396 ar = ath12k_mac_get_ar_by_pdev_id(ab, le32_to_cpu(tx_compl_param.pdev_id)); 7397 if (!ar) { 7398 ath12k_warn(ab, "invalid pdev id %d in mgmt_tx_compl_event\n", 7399 tx_compl_param.pdev_id); 7400 goto exit; 7401 } 7402 7403 wmi_process_mgmt_tx_comp(ar, le32_to_cpu(tx_compl_param.desc_id), 7404 le32_to_cpu(tx_compl_param.status), 7405 le32_to_cpu(tx_compl_param.ack_rssi)); 7406 7407 ath12k_dbg(ab, ATH12K_DBG_MGMT, 7408 "mgmt tx compl ev pdev_id %d, desc_id %d, status %d", 7409 tx_compl_param.pdev_id, tx_compl_param.desc_id, 7410 tx_compl_param.status); 7411 7412 exit: 7413 rcu_read_unlock(); 7414 } 7415 7416 static struct ath12k *ath12k_get_ar_on_scan_state(struct ath12k_base *ab, 7417 u32 vdev_id, 7418 enum ath12k_scan_state state) 7419 { 7420 int i; 7421 struct ath12k_pdev *pdev; 7422 struct ath12k *ar; 7423 7424 for (i = 0; i < ab->num_radios; i++) { 7425 pdev = rcu_dereference(ab->pdevs_active[i]); 7426 if (pdev && pdev->ar) { 7427 ar = pdev->ar; 7428 7429 spin_lock_bh(&ar->data_lock); 7430 if (ar->scan.state == state && 7431 ar->scan.arvif && 7432 ar->scan.arvif->vdev_id == vdev_id) { 7433 spin_unlock_bh(&ar->data_lock); 7434 return ar; 7435 } 7436 spin_unlock_bh(&ar->data_lock); 7437 } 7438 } 7439 return NULL; 7440 } 7441 7442 static void ath12k_scan_event(struct ath12k_base *ab, struct sk_buff *skb) 7443 { 7444 struct ath12k *ar; 7445 struct wmi_scan_event scan_ev = {}; 7446 7447 if (ath12k_pull_scan_ev(ab, skb, &scan_ev) != 0) { 7448 ath12k_warn(ab, "failed to extract scan event"); 7449 return; 7450 } 7451 7452 rcu_read_lock(); 7453 7454 /* In case the scan was cancelled, ex. during interface teardown, 7455 * the interface will not be found in active interfaces. 7456 * Rather, in such scenarios, iterate over the active pdev's to 7457 * search 'ar' if the corresponding 'ar' scan is ABORTING and the 7458 * aborting scan's vdev id matches this event info. 7459 */ 7460 if (le32_to_cpu(scan_ev.event_type) == WMI_SCAN_EVENT_COMPLETED && 7461 le32_to_cpu(scan_ev.reason) == WMI_SCAN_REASON_CANCELLED) { 7462 ar = ath12k_get_ar_on_scan_state(ab, le32_to_cpu(scan_ev.vdev_id), 7463 ATH12K_SCAN_ABORTING); 7464 if (!ar) 7465 ar = ath12k_get_ar_on_scan_state(ab, le32_to_cpu(scan_ev.vdev_id), 7466 ATH12K_SCAN_RUNNING); 7467 } else { 7468 ar = ath12k_mac_get_ar_by_vdev_id(ab, le32_to_cpu(scan_ev.vdev_id)); 7469 } 7470 7471 if (!ar) { 7472 ath12k_warn(ab, "Received scan event for unknown vdev"); 7473 rcu_read_unlock(); 7474 return; 7475 } 7476 7477 spin_lock_bh(&ar->data_lock); 7478 7479 ath12k_dbg(ab, ATH12K_DBG_WMI, 7480 "scan event %s type %d reason %d freq %d req_id %d scan_id %d vdev_id %d state %s (%d)\n", 7481 ath12k_wmi_event_scan_type_str(le32_to_cpu(scan_ev.event_type), 7482 le32_to_cpu(scan_ev.reason)), 7483 le32_to_cpu(scan_ev.event_type), 7484 le32_to_cpu(scan_ev.reason), 7485 le32_to_cpu(scan_ev.channel_freq), 7486 le32_to_cpu(scan_ev.scan_req_id), 7487 le32_to_cpu(scan_ev.scan_id), 7488 le32_to_cpu(scan_ev.vdev_id), 7489 ath12k_scan_state_str(ar->scan.state), ar->scan.state); 7490 7491 switch (le32_to_cpu(scan_ev.event_type)) { 7492 case WMI_SCAN_EVENT_STARTED: 7493 ath12k_wmi_event_scan_started(ar); 7494 break; 7495 case WMI_SCAN_EVENT_COMPLETED: 7496 ath12k_wmi_event_scan_completed(ar); 7497 break; 7498 case WMI_SCAN_EVENT_BSS_CHANNEL: 7499 ath12k_wmi_event_scan_bss_chan(ar); 7500 break; 7501 case WMI_SCAN_EVENT_FOREIGN_CHAN: 7502 ath12k_wmi_event_scan_foreign_chan(ar, le32_to_cpu(scan_ev.channel_freq)); 7503 break; 7504 case WMI_SCAN_EVENT_START_FAILED: 7505 ath12k_warn(ab, "received scan start failure event\n"); 7506 ath12k_wmi_event_scan_start_failed(ar); 7507 break; 7508 case WMI_SCAN_EVENT_DEQUEUED: 7509 __ath12k_mac_scan_finish(ar); 7510 break; 7511 case WMI_SCAN_EVENT_PREEMPTED: 7512 case WMI_SCAN_EVENT_RESTARTED: 7513 case WMI_SCAN_EVENT_FOREIGN_CHAN_EXIT: 7514 default: 7515 break; 7516 } 7517 7518 spin_unlock_bh(&ar->data_lock); 7519 7520 rcu_read_unlock(); 7521 } 7522 7523 static void ath12k_peer_sta_kickout_event(struct ath12k_base *ab, struct sk_buff *skb) 7524 { 7525 struct wmi_peer_sta_kickout_arg arg = {}; 7526 struct ath12k_link_vif *arvif; 7527 struct ieee80211_sta *sta; 7528 struct ath12k_sta *ahsta; 7529 struct ath12k_link_sta *arsta; 7530 struct ath12k *ar; 7531 7532 if (ath12k_pull_peer_sta_kickout_ev(ab, skb, &arg) != 0) { 7533 ath12k_warn(ab, "failed to extract peer sta kickout event"); 7534 return; 7535 } 7536 7537 rcu_read_lock(); 7538 7539 spin_lock_bh(&ab->base_lock); 7540 7541 arsta = ath12k_link_sta_find_by_addr(ab, arg.mac_addr); 7542 7543 if (!arsta) { 7544 ath12k_warn(ab, "arsta not found %pM\n", 7545 arg.mac_addr); 7546 goto exit; 7547 } 7548 7549 arvif = arsta->arvif; 7550 if (!arvif) { 7551 ath12k_warn(ab, "invalid arvif in peer sta kickout ev for STA %pM", 7552 arg.mac_addr); 7553 goto exit; 7554 } 7555 7556 ar = arvif->ar; 7557 ahsta = arsta->ahsta; 7558 sta = ath12k_ahsta_to_sta(ahsta); 7559 7560 ath12k_dbg(ab, ATH12K_DBG_WMI, 7561 "peer sta kickout event %pM reason: %d rssi: %d\n", 7562 arg.mac_addr, arg.reason, arg.rssi); 7563 7564 switch (arg.reason) { 7565 case WMI_PEER_STA_KICKOUT_REASON_INACTIVITY: 7566 if (arvif->ahvif->vif->type == NL80211_IFTYPE_STATION) { 7567 ath12k_mac_handle_beacon_miss(ar, arvif); 7568 break; 7569 } 7570 fallthrough; 7571 default: 7572 ieee80211_report_low_ack(sta, 10); 7573 } 7574 7575 exit: 7576 spin_unlock_bh(&ab->base_lock); 7577 rcu_read_unlock(); 7578 } 7579 7580 static void ath12k_roam_event(struct ath12k_base *ab, struct sk_buff *skb) 7581 { 7582 struct ath12k_link_vif *arvif; 7583 struct wmi_roam_event roam_ev = {}; 7584 struct ath12k *ar; 7585 u32 vdev_id; 7586 u8 roam_reason; 7587 7588 if (ath12k_pull_roam_ev(ab, skb, &roam_ev) != 0) { 7589 ath12k_warn(ab, "failed to extract roam event"); 7590 return; 7591 } 7592 7593 vdev_id = le32_to_cpu(roam_ev.vdev_id); 7594 roam_reason = u32_get_bits(le32_to_cpu(roam_ev.reason), 7595 WMI_ROAM_REASON_MASK); 7596 7597 ath12k_dbg(ab, ATH12K_DBG_WMI, 7598 "wmi roam event vdev %u reason %d rssi %d\n", 7599 vdev_id, roam_reason, roam_ev.rssi); 7600 7601 guard(rcu)(); 7602 arvif = ath12k_mac_get_arvif_by_vdev_id(ab, vdev_id); 7603 if (!arvif) { 7604 ath12k_warn(ab, "invalid vdev id in roam ev %d", vdev_id); 7605 return; 7606 } 7607 7608 ar = arvif->ar; 7609 7610 if (roam_reason >= WMI_ROAM_REASON_MAX) 7611 ath12k_warn(ab, "ignoring unknown roam event reason %d on vdev %i\n", 7612 roam_reason, vdev_id); 7613 7614 switch (roam_reason) { 7615 case WMI_ROAM_REASON_BEACON_MISS: 7616 ath12k_mac_handle_beacon_miss(ar, arvif); 7617 break; 7618 case WMI_ROAM_REASON_BETTER_AP: 7619 case WMI_ROAM_REASON_LOW_RSSI: 7620 case WMI_ROAM_REASON_SUITABLE_AP_FOUND: 7621 case WMI_ROAM_REASON_HO_FAILED: 7622 ath12k_warn(ab, "ignoring not implemented roam event reason %d on vdev %i\n", 7623 roam_reason, vdev_id); 7624 break; 7625 } 7626 } 7627 7628 static void ath12k_chan_info_event(struct ath12k_base *ab, struct sk_buff *skb) 7629 { 7630 struct wmi_chan_info_event ch_info_ev = {}; 7631 struct ath12k *ar; 7632 struct survey_info *survey; 7633 int idx; 7634 /* HW channel counters frequency value in hertz */ 7635 u32 cc_freq_hz = ab->cc_freq_hz; 7636 7637 if (ath12k_pull_chan_info_ev(ab, skb, &ch_info_ev) != 0) { 7638 ath12k_warn(ab, "failed to extract chan info event"); 7639 return; 7640 } 7641 7642 ath12k_dbg(ab, ATH12K_DBG_WMI, 7643 "chan info vdev_id %d err_code %d freq %d cmd_flags %d noise_floor %d rx_clear_count %d cycle_count %d mac_clk_mhz %d\n", 7644 ch_info_ev.vdev_id, ch_info_ev.err_code, ch_info_ev.freq, 7645 ch_info_ev.cmd_flags, ch_info_ev.noise_floor, 7646 ch_info_ev.rx_clear_count, ch_info_ev.cycle_count, 7647 ch_info_ev.mac_clk_mhz); 7648 7649 if (le32_to_cpu(ch_info_ev.cmd_flags) == WMI_CHAN_INFO_END_RESP) { 7650 ath12k_dbg(ab, ATH12K_DBG_WMI, "chan info report completed\n"); 7651 return; 7652 } 7653 7654 rcu_read_lock(); 7655 ar = ath12k_mac_get_ar_by_vdev_id(ab, le32_to_cpu(ch_info_ev.vdev_id)); 7656 if (!ar) { 7657 ath12k_warn(ab, "invalid vdev id in chan info ev %d", 7658 ch_info_ev.vdev_id); 7659 rcu_read_unlock(); 7660 return; 7661 } 7662 spin_lock_bh(&ar->data_lock); 7663 7664 switch (ar->scan.state) { 7665 case ATH12K_SCAN_IDLE: 7666 case ATH12K_SCAN_STARTING: 7667 ath12k_warn(ab, "received chan info event without a scan request, ignoring\n"); 7668 goto exit; 7669 case ATH12K_SCAN_RUNNING: 7670 case ATH12K_SCAN_ABORTING: 7671 break; 7672 } 7673 7674 idx = freq_to_idx(ar, le32_to_cpu(ch_info_ev.freq)); 7675 if (idx >= ARRAY_SIZE(ar->survey)) { 7676 ath12k_warn(ab, "chan info: invalid frequency %d (idx %d out of bounds)\n", 7677 ch_info_ev.freq, idx); 7678 goto exit; 7679 } 7680 7681 /* If FW provides MAC clock frequency in Mhz, overriding the initialized 7682 * HW channel counters frequency value 7683 */ 7684 if (ch_info_ev.mac_clk_mhz) 7685 cc_freq_hz = (le32_to_cpu(ch_info_ev.mac_clk_mhz) * 1000); 7686 7687 if (ch_info_ev.cmd_flags == WMI_CHAN_INFO_START_RESP) { 7688 survey = &ar->survey[idx]; 7689 memset(survey, 0, sizeof(*survey)); 7690 survey->noise = le32_to_cpu(ch_info_ev.noise_floor); 7691 survey->filled = SURVEY_INFO_NOISE_DBM | SURVEY_INFO_TIME | 7692 SURVEY_INFO_TIME_BUSY; 7693 survey->time = div_u64(le32_to_cpu(ch_info_ev.cycle_count), cc_freq_hz); 7694 survey->time_busy = div_u64(le32_to_cpu(ch_info_ev.rx_clear_count), 7695 cc_freq_hz); 7696 } 7697 exit: 7698 spin_unlock_bh(&ar->data_lock); 7699 rcu_read_unlock(); 7700 } 7701 7702 static void 7703 ath12k_pdev_bss_chan_info_event(struct ath12k_base *ab, struct sk_buff *skb) 7704 { 7705 struct wmi_pdev_bss_chan_info_event bss_ch_info_ev = {}; 7706 struct survey_info *survey; 7707 struct ath12k *ar; 7708 u32 cc_freq_hz = ab->cc_freq_hz; 7709 u64 busy, total, tx, rx, rx_bss; 7710 int idx; 7711 7712 if (ath12k_pull_pdev_bss_chan_info_ev(ab, skb, &bss_ch_info_ev) != 0) { 7713 ath12k_warn(ab, "failed to extract pdev bss chan info event"); 7714 return; 7715 } 7716 7717 busy = (u64)(le32_to_cpu(bss_ch_info_ev.rx_clear_count_high)) << 32 | 7718 le32_to_cpu(bss_ch_info_ev.rx_clear_count_low); 7719 7720 total = (u64)(le32_to_cpu(bss_ch_info_ev.cycle_count_high)) << 32 | 7721 le32_to_cpu(bss_ch_info_ev.cycle_count_low); 7722 7723 tx = (u64)(le32_to_cpu(bss_ch_info_ev.tx_cycle_count_high)) << 32 | 7724 le32_to_cpu(bss_ch_info_ev.tx_cycle_count_low); 7725 7726 rx = (u64)(le32_to_cpu(bss_ch_info_ev.rx_cycle_count_high)) << 32 | 7727 le32_to_cpu(bss_ch_info_ev.rx_cycle_count_low); 7728 7729 rx_bss = (u64)(le32_to_cpu(bss_ch_info_ev.rx_bss_cycle_count_high)) << 32 | 7730 le32_to_cpu(bss_ch_info_ev.rx_bss_cycle_count_low); 7731 7732 ath12k_dbg(ab, ATH12K_DBG_WMI, 7733 "pdev bss chan info:\n pdev_id: %d freq: %d noise: %d cycle: busy %llu total %llu tx %llu rx %llu rx_bss %llu\n", 7734 bss_ch_info_ev.pdev_id, bss_ch_info_ev.freq, 7735 bss_ch_info_ev.noise_floor, busy, total, 7736 tx, rx, rx_bss); 7737 7738 rcu_read_lock(); 7739 ar = ath12k_mac_get_ar_by_pdev_id(ab, le32_to_cpu(bss_ch_info_ev.pdev_id)); 7740 7741 if (!ar) { 7742 ath12k_warn(ab, "invalid pdev id %d in bss_chan_info event\n", 7743 bss_ch_info_ev.pdev_id); 7744 rcu_read_unlock(); 7745 return; 7746 } 7747 7748 spin_lock_bh(&ar->data_lock); 7749 idx = freq_to_idx(ar, le32_to_cpu(bss_ch_info_ev.freq)); 7750 if (idx >= ARRAY_SIZE(ar->survey)) { 7751 ath12k_warn(ab, "bss chan info: invalid frequency %d (idx %d out of bounds)\n", 7752 bss_ch_info_ev.freq, idx); 7753 goto exit; 7754 } 7755 7756 survey = &ar->survey[idx]; 7757 7758 survey->noise = le32_to_cpu(bss_ch_info_ev.noise_floor); 7759 survey->time = div_u64(total, cc_freq_hz); 7760 survey->time_busy = div_u64(busy, cc_freq_hz); 7761 survey->time_rx = div_u64(rx_bss, cc_freq_hz); 7762 survey->time_tx = div_u64(tx, cc_freq_hz); 7763 survey->filled |= (SURVEY_INFO_NOISE_DBM | 7764 SURVEY_INFO_TIME | 7765 SURVEY_INFO_TIME_BUSY | 7766 SURVEY_INFO_TIME_RX | 7767 SURVEY_INFO_TIME_TX); 7768 exit: 7769 spin_unlock_bh(&ar->data_lock); 7770 complete(&ar->bss_survey_done); 7771 7772 rcu_read_unlock(); 7773 } 7774 7775 static void ath12k_vdev_install_key_compl_event(struct ath12k_base *ab, 7776 struct sk_buff *skb) 7777 { 7778 struct wmi_vdev_install_key_complete_arg install_key_compl = {}; 7779 struct ath12k *ar; 7780 7781 if (ath12k_pull_vdev_install_key_compl_ev(ab, skb, &install_key_compl) != 0) { 7782 ath12k_warn(ab, "failed to extract install key compl event"); 7783 return; 7784 } 7785 7786 ath12k_dbg(ab, ATH12K_DBG_WMI, 7787 "vdev install key ev idx %d flags %08x macaddr %pM status %d\n", 7788 install_key_compl.key_idx, install_key_compl.key_flags, 7789 install_key_compl.macaddr, install_key_compl.status); 7790 7791 rcu_read_lock(); 7792 ar = ath12k_mac_get_ar_by_vdev_id(ab, install_key_compl.vdev_id); 7793 if (!ar) { 7794 ath12k_warn(ab, "invalid vdev id in install key compl ev %d", 7795 install_key_compl.vdev_id); 7796 rcu_read_unlock(); 7797 return; 7798 } 7799 7800 ar->install_key_status = 0; 7801 7802 if (install_key_compl.status != WMI_VDEV_INSTALL_KEY_COMPL_STATUS_SUCCESS) { 7803 ath12k_warn(ab, "install key failed for %pM status %d\n", 7804 install_key_compl.macaddr, install_key_compl.status); 7805 ar->install_key_status = install_key_compl.status; 7806 } 7807 7808 complete(&ar->install_key_done); 7809 rcu_read_unlock(); 7810 } 7811 7812 static int ath12k_wmi_tlv_services_parser(struct ath12k_base *ab, 7813 u16 tag, u16 len, 7814 const void *ptr, 7815 void *data) 7816 { 7817 const struct wmi_service_available_event *ev; 7818 u16 wmi_ext2_service_words; 7819 __le32 *wmi_ext2_service_bitmap; 7820 int i, j; 7821 u16 expected_len; 7822 7823 expected_len = WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(u32); 7824 if (len < expected_len) { 7825 ath12k_warn(ab, "invalid length %d for the WMI services available tag 0x%x\n", 7826 len, tag); 7827 return -EINVAL; 7828 } 7829 7830 switch (tag) { 7831 case WMI_TAG_SERVICE_AVAILABLE_EVENT: 7832 ev = (struct wmi_service_available_event *)ptr; 7833 for (i = 0, j = WMI_MAX_SERVICE; 7834 i < WMI_SERVICE_SEGMENT_BM_SIZE32 && j < WMI_MAX_EXT_SERVICE; 7835 i++) { 7836 do { 7837 if (le32_to_cpu(ev->wmi_service_segment_bitmap[i]) & 7838 BIT(j % WMI_AVAIL_SERVICE_BITS_IN_SIZE32)) 7839 set_bit(j, ab->wmi_ab.svc_map); 7840 } while (++j % WMI_AVAIL_SERVICE_BITS_IN_SIZE32); 7841 } 7842 7843 ath12k_dbg(ab, ATH12K_DBG_WMI, 7844 "wmi_ext_service_bitmap 0x%x 0x%x 0x%x 0x%x", 7845 ev->wmi_service_segment_bitmap[0], 7846 ev->wmi_service_segment_bitmap[1], 7847 ev->wmi_service_segment_bitmap[2], 7848 ev->wmi_service_segment_bitmap[3]); 7849 break; 7850 case WMI_TAG_ARRAY_UINT32: 7851 wmi_ext2_service_bitmap = (__le32 *)ptr; 7852 wmi_ext2_service_words = len / sizeof(u32); 7853 for (i = 0, j = WMI_MAX_EXT_SERVICE; 7854 i < wmi_ext2_service_words && j < WMI_MAX_EXT2_SERVICE; 7855 i++) { 7856 do { 7857 if (__le32_to_cpu(wmi_ext2_service_bitmap[i]) & 7858 BIT(j % WMI_AVAIL_SERVICE_BITS_IN_SIZE32)) 7859 set_bit(j, ab->wmi_ab.svc_map); 7860 } while (++j % WMI_AVAIL_SERVICE_BITS_IN_SIZE32); 7861 ath12k_dbg(ab, ATH12K_DBG_WMI, 7862 "wmi_ext2_service bitmap 0x%08x\n", 7863 __le32_to_cpu(wmi_ext2_service_bitmap[i])); 7864 } 7865 7866 break; 7867 } 7868 return 0; 7869 } 7870 7871 static int ath12k_service_available_event(struct ath12k_base *ab, struct sk_buff *skb) 7872 { 7873 int ret; 7874 7875 ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, 7876 ath12k_wmi_tlv_services_parser, 7877 NULL); 7878 return ret; 7879 } 7880 7881 static void ath12k_peer_assoc_conf_event(struct ath12k_base *ab, struct sk_buff *skb) 7882 { 7883 struct wmi_peer_assoc_conf_arg peer_assoc_conf = {}; 7884 struct ath12k *ar; 7885 7886 if (ath12k_pull_peer_assoc_conf_ev(ab, skb, &peer_assoc_conf) != 0) { 7887 ath12k_warn(ab, "failed to extract peer assoc conf event"); 7888 return; 7889 } 7890 7891 ath12k_dbg(ab, ATH12K_DBG_WMI, 7892 "peer assoc conf ev vdev id %d macaddr %pM\n", 7893 peer_assoc_conf.vdev_id, peer_assoc_conf.macaddr); 7894 7895 rcu_read_lock(); 7896 ar = ath12k_mac_get_ar_by_vdev_id(ab, peer_assoc_conf.vdev_id); 7897 7898 if (!ar) { 7899 ath12k_warn(ab, "invalid vdev id in peer assoc conf ev %d", 7900 peer_assoc_conf.vdev_id); 7901 rcu_read_unlock(); 7902 return; 7903 } 7904 7905 complete(&ar->peer_assoc_done); 7906 rcu_read_unlock(); 7907 } 7908 7909 static void 7910 ath12k_wmi_fw_vdev_stats_dump(struct ath12k *ar, 7911 struct ath12k_fw_stats *fw_stats, 7912 char *buf, u32 *length) 7913 { 7914 const struct ath12k_fw_stats_vdev *vdev; 7915 u32 buf_len = ATH12K_FW_STATS_BUF_SIZE; 7916 struct ath12k_link_vif *arvif; 7917 u32 len = *length; 7918 u8 *vif_macaddr; 7919 int i; 7920 7921 len += scnprintf(buf + len, buf_len - len, "\n"); 7922 len += scnprintf(buf + len, buf_len - len, "%30s\n", 7923 "ath12k VDEV stats"); 7924 len += scnprintf(buf + len, buf_len - len, "%30s\n\n", 7925 "================="); 7926 7927 list_for_each_entry(vdev, &fw_stats->vdevs, list) { 7928 arvif = ath12k_mac_get_arvif(ar, vdev->vdev_id); 7929 if (!arvif) 7930 continue; 7931 vif_macaddr = arvif->ahvif->vif->addr; 7932 7933 len += scnprintf(buf + len, buf_len - len, "%30s %u\n", 7934 "VDEV ID", vdev->vdev_id); 7935 len += scnprintf(buf + len, buf_len - len, "%30s %pM\n", 7936 "VDEV MAC address", vif_macaddr); 7937 len += scnprintf(buf + len, buf_len - len, "%30s %u\n", 7938 "beacon snr", vdev->beacon_snr); 7939 len += scnprintf(buf + len, buf_len - len, "%30s %u\n", 7940 "data snr", vdev->data_snr); 7941 len += scnprintf(buf + len, buf_len - len, "%30s %u\n", 7942 "num rx frames", vdev->num_rx_frames); 7943 len += scnprintf(buf + len, buf_len - len, "%30s %u\n", 7944 "num rts fail", vdev->num_rts_fail); 7945 len += scnprintf(buf + len, buf_len - len, "%30s %u\n", 7946 "num rts success", vdev->num_rts_success); 7947 len += scnprintf(buf + len, buf_len - len, "%30s %u\n", 7948 "num rx err", vdev->num_rx_err); 7949 len += scnprintf(buf + len, buf_len - len, "%30s %u\n", 7950 "num rx discard", vdev->num_rx_discard); 7951 len += scnprintf(buf + len, buf_len - len, "%30s %u\n", 7952 "num tx not acked", vdev->num_tx_not_acked); 7953 7954 for (i = 0 ; i < WLAN_MAX_AC; i++) 7955 len += scnprintf(buf + len, buf_len - len, 7956 "%25s [%02d] %u\n", 7957 "num tx frames", i, 7958 vdev->num_tx_frames[i]); 7959 7960 for (i = 0 ; i < WLAN_MAX_AC; i++) 7961 len += scnprintf(buf + len, buf_len - len, 7962 "%25s [%02d] %u\n", 7963 "num tx frames retries", i, 7964 vdev->num_tx_frames_retries[i]); 7965 7966 for (i = 0 ; i < WLAN_MAX_AC; i++) 7967 len += scnprintf(buf + len, buf_len - len, 7968 "%25s [%02d] %u\n", 7969 "num tx frames failures", i, 7970 vdev->num_tx_frames_failures[i]); 7971 7972 for (i = 0 ; i < MAX_TX_RATE_VALUES; i++) 7973 len += scnprintf(buf + len, buf_len - len, 7974 "%25s [%02d] 0x%08x\n", 7975 "tx rate history", i, 7976 vdev->tx_rate_history[i]); 7977 for (i = 0 ; i < MAX_TX_RATE_VALUES; i++) 7978 len += scnprintf(buf + len, buf_len - len, 7979 "%25s [%02d] %u\n", 7980 "beacon rssi history", i, 7981 vdev->beacon_rssi_history[i]); 7982 7983 len += scnprintf(buf + len, buf_len - len, "\n"); 7984 *length = len; 7985 } 7986 } 7987 7988 static void 7989 ath12k_wmi_fw_bcn_stats_dump(struct ath12k *ar, 7990 struct ath12k_fw_stats *fw_stats, 7991 char *buf, u32 *length) 7992 { 7993 const struct ath12k_fw_stats_bcn *bcn; 7994 u32 buf_len = ATH12K_FW_STATS_BUF_SIZE; 7995 struct ath12k_link_vif *arvif; 7996 u32 len = *length; 7997 size_t num_bcn; 7998 7999 num_bcn = list_count_nodes(&fw_stats->bcn); 8000 8001 len += scnprintf(buf + len, buf_len - len, "\n"); 8002 len += scnprintf(buf + len, buf_len - len, "%30s (%zu)\n", 8003 "ath12k Beacon stats", num_bcn); 8004 len += scnprintf(buf + len, buf_len - len, "%30s\n\n", 8005 "==================="); 8006 8007 list_for_each_entry(bcn, &fw_stats->bcn, list) { 8008 arvif = ath12k_mac_get_arvif(ar, bcn->vdev_id); 8009 if (!arvif) 8010 continue; 8011 len += scnprintf(buf + len, buf_len - len, "%30s %u\n", 8012 "VDEV ID", bcn->vdev_id); 8013 len += scnprintf(buf + len, buf_len - len, "%30s %pM\n", 8014 "VDEV MAC address", arvif->ahvif->vif->addr); 8015 len += scnprintf(buf + len, buf_len - len, "%30s\n\n", 8016 "================"); 8017 len += scnprintf(buf + len, buf_len - len, "%30s %u\n", 8018 "Num of beacon tx success", bcn->tx_bcn_succ_cnt); 8019 len += scnprintf(buf + len, buf_len - len, "%30s %u\n", 8020 "Num of beacon tx failures", bcn->tx_bcn_outage_cnt); 8021 8022 len += scnprintf(buf + len, buf_len - len, "\n"); 8023 *length = len; 8024 } 8025 } 8026 8027 static void 8028 ath12k_wmi_fw_pdev_base_stats_dump(const struct ath12k_fw_stats_pdev *pdev, 8029 char *buf, u32 *length, u64 fw_soc_drop_cnt) 8030 { 8031 u32 len = *length; 8032 u32 buf_len = ATH12K_FW_STATS_BUF_SIZE; 8033 8034 len = scnprintf(buf + len, buf_len - len, "\n"); 8035 len += scnprintf(buf + len, buf_len - len, "%30s\n", 8036 "ath12k PDEV stats"); 8037 len += scnprintf(buf + len, buf_len - len, "%30s\n\n", 8038 "================="); 8039 8040 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8041 "Channel noise floor", pdev->ch_noise_floor); 8042 len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", 8043 "Channel TX power", pdev->chan_tx_power); 8044 len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", 8045 "TX frame count", pdev->tx_frame_count); 8046 len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", 8047 "RX frame count", pdev->rx_frame_count); 8048 len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", 8049 "RX clear count", pdev->rx_clear_count); 8050 len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", 8051 "Cycle count", pdev->cycle_count); 8052 len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", 8053 "PHY error count", pdev->phy_err_count); 8054 len += scnprintf(buf + len, buf_len - len, "%30s %10llu\n", 8055 "soc drop count", fw_soc_drop_cnt); 8056 8057 *length = len; 8058 } 8059 8060 static void 8061 ath12k_wmi_fw_pdev_tx_stats_dump(const struct ath12k_fw_stats_pdev *pdev, 8062 char *buf, u32 *length) 8063 { 8064 u32 len = *length; 8065 u32 buf_len = ATH12K_FW_STATS_BUF_SIZE; 8066 8067 len += scnprintf(buf + len, buf_len - len, "\n%30s\n", 8068 "ath12k PDEV TX stats"); 8069 len += scnprintf(buf + len, buf_len - len, "%30s\n\n", 8070 "===================="); 8071 8072 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8073 "HTT cookies queued", pdev->comp_queued); 8074 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8075 "HTT cookies disp.", pdev->comp_delivered); 8076 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8077 "MSDU queued", pdev->msdu_enqued); 8078 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8079 "MPDU queued", pdev->mpdu_enqued); 8080 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8081 "MSDUs dropped", pdev->wmm_drop); 8082 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8083 "Local enqued", pdev->local_enqued); 8084 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8085 "Local freed", pdev->local_freed); 8086 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8087 "HW queued", pdev->hw_queued); 8088 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8089 "PPDUs reaped", pdev->hw_reaped); 8090 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8091 "Num underruns", pdev->underrun); 8092 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8093 "PPDUs cleaned", pdev->tx_abort); 8094 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8095 "MPDUs requeued", pdev->mpdus_requed); 8096 len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", 8097 "Excessive retries", pdev->tx_ko); 8098 len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", 8099 "HW rate", pdev->data_rc); 8100 len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", 8101 "Sched self triggers", pdev->self_triggers); 8102 len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", 8103 "Dropped due to SW retries", 8104 pdev->sw_retry_failure); 8105 len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", 8106 "Illegal rate phy errors", 8107 pdev->illgl_rate_phy_err); 8108 len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", 8109 "PDEV continuous xretry", pdev->pdev_cont_xretry); 8110 len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", 8111 "TX timeout", pdev->pdev_tx_timeout); 8112 len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", 8113 "PDEV resets", pdev->pdev_resets); 8114 len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", 8115 "Stateless TIDs alloc failures", 8116 pdev->stateless_tid_alloc_failure); 8117 len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", 8118 "PHY underrun", pdev->phy_underrun); 8119 len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", 8120 "MPDU is more than txop limit", pdev->txop_ovf); 8121 *length = len; 8122 } 8123 8124 static void 8125 ath12k_wmi_fw_pdev_rx_stats_dump(const struct ath12k_fw_stats_pdev *pdev, 8126 char *buf, u32 *length) 8127 { 8128 u32 len = *length; 8129 u32 buf_len = ATH12K_FW_STATS_BUF_SIZE; 8130 8131 len += scnprintf(buf + len, buf_len - len, "\n%30s\n", 8132 "ath12k PDEV RX stats"); 8133 len += scnprintf(buf + len, buf_len - len, "%30s\n\n", 8134 "===================="); 8135 8136 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8137 "Mid PPDU route change", 8138 pdev->mid_ppdu_route_change); 8139 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8140 "Tot. number of statuses", pdev->status_rcvd); 8141 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8142 "Extra frags on rings 0", pdev->r0_frags); 8143 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8144 "Extra frags on rings 1", pdev->r1_frags); 8145 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8146 "Extra frags on rings 2", pdev->r2_frags); 8147 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8148 "Extra frags on rings 3", pdev->r3_frags); 8149 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8150 "MSDUs delivered to HTT", pdev->htt_msdus); 8151 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8152 "MPDUs delivered to HTT", pdev->htt_mpdus); 8153 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8154 "MSDUs delivered to stack", pdev->loc_msdus); 8155 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8156 "MPDUs delivered to stack", pdev->loc_mpdus); 8157 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8158 "Oversized AMSUs", pdev->oversize_amsdu); 8159 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8160 "PHY errors", pdev->phy_errs); 8161 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8162 "PHY errors drops", pdev->phy_err_drop); 8163 len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", 8164 "MPDU errors (FCS, MIC, ENC)", pdev->mpdu_errs); 8165 *length = len; 8166 } 8167 8168 static void 8169 ath12k_wmi_fw_pdev_stats_dump(struct ath12k *ar, 8170 struct ath12k_fw_stats *fw_stats, 8171 char *buf, u32 *length) 8172 { 8173 const struct ath12k_fw_stats_pdev *pdev; 8174 u32 len = *length; 8175 8176 pdev = list_first_entry_or_null(&fw_stats->pdevs, 8177 struct ath12k_fw_stats_pdev, list); 8178 if (!pdev) { 8179 ath12k_warn(ar->ab, "failed to get pdev stats\n"); 8180 return; 8181 } 8182 8183 ath12k_wmi_fw_pdev_base_stats_dump(pdev, buf, &len, 8184 ar->ab->fw_soc_drop_count); 8185 ath12k_wmi_fw_pdev_tx_stats_dump(pdev, buf, &len); 8186 ath12k_wmi_fw_pdev_rx_stats_dump(pdev, buf, &len); 8187 8188 *length = len; 8189 } 8190 8191 void ath12k_wmi_fw_stats_dump(struct ath12k *ar, 8192 struct ath12k_fw_stats *fw_stats, 8193 u32 stats_id, char *buf) 8194 { 8195 u32 len = 0; 8196 u32 buf_len = ATH12K_FW_STATS_BUF_SIZE; 8197 8198 spin_lock_bh(&ar->data_lock); 8199 8200 switch (stats_id) { 8201 case WMI_REQUEST_VDEV_STAT: 8202 ath12k_wmi_fw_vdev_stats_dump(ar, fw_stats, buf, &len); 8203 break; 8204 case WMI_REQUEST_BCN_STAT: 8205 ath12k_wmi_fw_bcn_stats_dump(ar, fw_stats, buf, &len); 8206 break; 8207 case WMI_REQUEST_PDEV_STAT: 8208 ath12k_wmi_fw_pdev_stats_dump(ar, fw_stats, buf, &len); 8209 break; 8210 default: 8211 break; 8212 } 8213 8214 spin_unlock_bh(&ar->data_lock); 8215 8216 if (len >= buf_len) 8217 buf[len - 1] = 0; 8218 else 8219 buf[len] = 0; 8220 } 8221 8222 static void 8223 ath12k_wmi_pull_vdev_stats(const struct wmi_vdev_stats_params *src, 8224 struct ath12k_fw_stats_vdev *dst) 8225 { 8226 int i; 8227 8228 dst->vdev_id = le32_to_cpu(src->vdev_id); 8229 dst->beacon_snr = le32_to_cpu(src->beacon_snr); 8230 dst->data_snr = le32_to_cpu(src->data_snr); 8231 dst->num_rx_frames = le32_to_cpu(src->num_rx_frames); 8232 dst->num_rts_fail = le32_to_cpu(src->num_rts_fail); 8233 dst->num_rts_success = le32_to_cpu(src->num_rts_success); 8234 dst->num_rx_err = le32_to_cpu(src->num_rx_err); 8235 dst->num_rx_discard = le32_to_cpu(src->num_rx_discard); 8236 dst->num_tx_not_acked = le32_to_cpu(src->num_tx_not_acked); 8237 8238 for (i = 0; i < WLAN_MAX_AC; i++) 8239 dst->num_tx_frames[i] = 8240 le32_to_cpu(src->num_tx_frames[i]); 8241 8242 for (i = 0; i < WLAN_MAX_AC; i++) 8243 dst->num_tx_frames_retries[i] = 8244 le32_to_cpu(src->num_tx_frames_retries[i]); 8245 8246 for (i = 0; i < WLAN_MAX_AC; i++) 8247 dst->num_tx_frames_failures[i] = 8248 le32_to_cpu(src->num_tx_frames_failures[i]); 8249 8250 for (i = 0; i < MAX_TX_RATE_VALUES; i++) 8251 dst->tx_rate_history[i] = 8252 le32_to_cpu(src->tx_rate_history[i]); 8253 8254 for (i = 0; i < MAX_TX_RATE_VALUES; i++) 8255 dst->beacon_rssi_history[i] = 8256 le32_to_cpu(src->beacon_rssi_history[i]); 8257 } 8258 8259 static void 8260 ath12k_wmi_pull_bcn_stats(const struct ath12k_wmi_bcn_stats_params *src, 8261 struct ath12k_fw_stats_bcn *dst) 8262 { 8263 dst->vdev_id = le32_to_cpu(src->vdev_id); 8264 dst->tx_bcn_succ_cnt = le32_to_cpu(src->tx_bcn_succ_cnt); 8265 dst->tx_bcn_outage_cnt = le32_to_cpu(src->tx_bcn_outage_cnt); 8266 } 8267 8268 static void 8269 ath12k_wmi_pull_pdev_stats_base(const struct ath12k_wmi_pdev_base_stats_params *src, 8270 struct ath12k_fw_stats_pdev *dst) 8271 { 8272 dst->ch_noise_floor = a_sle32_to_cpu(src->chan_nf); 8273 dst->tx_frame_count = __le32_to_cpu(src->tx_frame_count); 8274 dst->rx_frame_count = __le32_to_cpu(src->rx_frame_count); 8275 dst->rx_clear_count = __le32_to_cpu(src->rx_clear_count); 8276 dst->cycle_count = __le32_to_cpu(src->cycle_count); 8277 dst->phy_err_count = __le32_to_cpu(src->phy_err_count); 8278 dst->chan_tx_power = __le32_to_cpu(src->chan_tx_pwr); 8279 } 8280 8281 static void 8282 ath12k_wmi_pull_pdev_stats_tx(const struct ath12k_wmi_pdev_tx_stats_params *src, 8283 struct ath12k_fw_stats_pdev *dst) 8284 { 8285 dst->comp_queued = a_sle32_to_cpu(src->comp_queued); 8286 dst->comp_delivered = a_sle32_to_cpu(src->comp_delivered); 8287 dst->msdu_enqued = a_sle32_to_cpu(src->msdu_enqued); 8288 dst->mpdu_enqued = a_sle32_to_cpu(src->mpdu_enqued); 8289 dst->wmm_drop = a_sle32_to_cpu(src->wmm_drop); 8290 dst->local_enqued = a_sle32_to_cpu(src->local_enqued); 8291 dst->local_freed = a_sle32_to_cpu(src->local_freed); 8292 dst->hw_queued = a_sle32_to_cpu(src->hw_queued); 8293 dst->hw_reaped = a_sle32_to_cpu(src->hw_reaped); 8294 dst->underrun = a_sle32_to_cpu(src->underrun); 8295 dst->tx_abort = a_sle32_to_cpu(src->tx_abort); 8296 dst->mpdus_requed = a_sle32_to_cpu(src->mpdus_requed); 8297 dst->tx_ko = __le32_to_cpu(src->tx_ko); 8298 dst->data_rc = __le32_to_cpu(src->data_rc); 8299 dst->self_triggers = __le32_to_cpu(src->self_triggers); 8300 dst->sw_retry_failure = __le32_to_cpu(src->sw_retry_failure); 8301 dst->illgl_rate_phy_err = __le32_to_cpu(src->illgl_rate_phy_err); 8302 dst->pdev_cont_xretry = __le32_to_cpu(src->pdev_cont_xretry); 8303 dst->pdev_tx_timeout = __le32_to_cpu(src->pdev_tx_timeout); 8304 dst->pdev_resets = __le32_to_cpu(src->pdev_resets); 8305 dst->stateless_tid_alloc_failure = 8306 __le32_to_cpu(src->stateless_tid_alloc_failure); 8307 dst->phy_underrun = __le32_to_cpu(src->phy_underrun); 8308 dst->txop_ovf = __le32_to_cpu(src->txop_ovf); 8309 } 8310 8311 static void 8312 ath12k_wmi_pull_pdev_stats_rx(const struct ath12k_wmi_pdev_rx_stats_params *src, 8313 struct ath12k_fw_stats_pdev *dst) 8314 { 8315 dst->mid_ppdu_route_change = 8316 a_sle32_to_cpu(src->mid_ppdu_route_change); 8317 dst->status_rcvd = a_sle32_to_cpu(src->status_rcvd); 8318 dst->r0_frags = a_sle32_to_cpu(src->r0_frags); 8319 dst->r1_frags = a_sle32_to_cpu(src->r1_frags); 8320 dst->r2_frags = a_sle32_to_cpu(src->r2_frags); 8321 dst->r3_frags = a_sle32_to_cpu(src->r3_frags); 8322 dst->htt_msdus = a_sle32_to_cpu(src->htt_msdus); 8323 dst->htt_mpdus = a_sle32_to_cpu(src->htt_mpdus); 8324 dst->loc_msdus = a_sle32_to_cpu(src->loc_msdus); 8325 dst->loc_mpdus = a_sle32_to_cpu(src->loc_mpdus); 8326 dst->oversize_amsdu = a_sle32_to_cpu(src->oversize_amsdu); 8327 dst->phy_errs = a_sle32_to_cpu(src->phy_errs); 8328 dst->phy_err_drop = a_sle32_to_cpu(src->phy_err_drop); 8329 dst->mpdu_errs = a_sle32_to_cpu(src->mpdu_errs); 8330 } 8331 8332 static int ath12k_wmi_tlv_fw_stats_data_parse(struct ath12k_base *ab, 8333 struct wmi_tlv_fw_stats_parse *parse, 8334 const void *ptr, 8335 u16 len) 8336 { 8337 const struct wmi_stats_event *ev = parse->ev; 8338 struct ath12k_fw_stats *stats = parse->stats; 8339 struct ath12k *ar; 8340 struct ath12k_link_vif *arvif; 8341 struct ath12k_link_sta *arsta; 8342 int i, ret = 0; 8343 const void *data = ptr; 8344 8345 if (!ev) { 8346 ath12k_warn(ab, "failed to fetch update stats ev"); 8347 return -EPROTO; 8348 } 8349 8350 if (!stats) 8351 return -EINVAL; 8352 8353 rcu_read_lock(); 8354 8355 stats->pdev_id = le32_to_cpu(ev->pdev_id); 8356 ar = ath12k_mac_get_ar_by_pdev_id(ab, stats->pdev_id); 8357 if (!ar) { 8358 ath12k_warn(ab, "invalid pdev id %d in update stats event\n", 8359 le32_to_cpu(ev->pdev_id)); 8360 ret = -EPROTO; 8361 goto exit; 8362 } 8363 8364 for (i = 0; i < le32_to_cpu(ev->num_vdev_stats); i++) { 8365 const struct wmi_vdev_stats_params *src; 8366 struct ath12k_fw_stats_vdev *dst; 8367 8368 src = data; 8369 if (len < sizeof(*src)) { 8370 ret = -EPROTO; 8371 goto exit; 8372 } 8373 8374 arvif = ath12k_mac_get_arvif(ar, le32_to_cpu(src->vdev_id)); 8375 if (arvif) { 8376 spin_lock_bh(&ab->base_lock); 8377 arsta = ath12k_link_sta_find_by_addr(ab, arvif->bssid); 8378 if (arsta) { 8379 arsta->rssi_beacon = le32_to_cpu(src->beacon_snr); 8380 ath12k_dbg(ab, ATH12K_DBG_WMI, 8381 "wmi stats vdev id %d snr %d\n", 8382 src->vdev_id, src->beacon_snr); 8383 } else { 8384 ath12k_warn(ab, 8385 "not found link sta with bssid %pM for vdev stat\n", 8386 arvif->bssid); 8387 } 8388 spin_unlock_bh(&ab->base_lock); 8389 } 8390 8391 data += sizeof(*src); 8392 len -= sizeof(*src); 8393 dst = kzalloc_obj(*dst, GFP_ATOMIC); 8394 if (!dst) 8395 continue; 8396 ath12k_wmi_pull_vdev_stats(src, dst); 8397 stats->stats_id = WMI_REQUEST_VDEV_STAT; 8398 list_add_tail(&dst->list, &stats->vdevs); 8399 } 8400 for (i = 0; i < le32_to_cpu(ev->num_bcn_stats); i++) { 8401 const struct ath12k_wmi_bcn_stats_params *src; 8402 struct ath12k_fw_stats_bcn *dst; 8403 8404 src = data; 8405 if (len < sizeof(*src)) { 8406 ret = -EPROTO; 8407 goto exit; 8408 } 8409 8410 data += sizeof(*src); 8411 len -= sizeof(*src); 8412 dst = kzalloc_obj(*dst, GFP_ATOMIC); 8413 if (!dst) 8414 continue; 8415 ath12k_wmi_pull_bcn_stats(src, dst); 8416 stats->stats_id = WMI_REQUEST_BCN_STAT; 8417 list_add_tail(&dst->list, &stats->bcn); 8418 } 8419 for (i = 0; i < le32_to_cpu(ev->num_pdev_stats); i++) { 8420 const struct ath12k_wmi_pdev_stats_params *src; 8421 struct ath12k_fw_stats_pdev *dst; 8422 8423 src = data; 8424 if (len < sizeof(*src)) { 8425 ret = -EPROTO; 8426 goto exit; 8427 } 8428 8429 stats->stats_id = WMI_REQUEST_PDEV_STAT; 8430 8431 data += sizeof(*src); 8432 len -= sizeof(*src); 8433 8434 dst = kzalloc_obj(*dst, GFP_ATOMIC); 8435 if (!dst) 8436 continue; 8437 8438 ath12k_wmi_pull_pdev_stats_base(&src->base, dst); 8439 ath12k_wmi_pull_pdev_stats_tx(&src->tx, dst); 8440 ath12k_wmi_pull_pdev_stats_rx(&src->rx, dst); 8441 list_add_tail(&dst->list, &stats->pdevs); 8442 } 8443 8444 exit: 8445 rcu_read_unlock(); 8446 return ret; 8447 } 8448 8449 static int ath12k_wmi_tlv_rssi_chain_parse(struct ath12k_base *ab, 8450 u16 tag, u16 len, 8451 const void *ptr, void *data) 8452 { 8453 const struct wmi_rssi_stat_params *stats_rssi = ptr; 8454 struct wmi_tlv_fw_stats_parse *parse = data; 8455 const struct wmi_stats_event *ev = parse->ev; 8456 struct ath12k_fw_stats *stats = parse->stats; 8457 struct ath12k_link_vif *arvif; 8458 struct ath12k_link_sta *arsta; 8459 struct ath12k *ar; 8460 int vdev_id; 8461 int j; 8462 8463 if (!ev) { 8464 ath12k_warn(ab, "failed to fetch update stats ev"); 8465 return -EPROTO; 8466 } 8467 8468 if (tag != WMI_TAG_RSSI_STATS) 8469 return -EPROTO; 8470 8471 if (!stats) 8472 return -EINVAL; 8473 8474 stats->pdev_id = le32_to_cpu(ev->pdev_id); 8475 vdev_id = le32_to_cpu(stats_rssi->vdev_id); 8476 guard(rcu)(); 8477 ar = ath12k_mac_get_ar_by_pdev_id(ab, stats->pdev_id); 8478 if (!ar) { 8479 ath12k_warn(ab, "invalid pdev id %d in rssi chain parse\n", 8480 stats->pdev_id); 8481 return -EPROTO; 8482 } 8483 8484 arvif = ath12k_mac_get_arvif(ar, vdev_id); 8485 if (!arvif) { 8486 ath12k_warn(ab, "not found vif for vdev id %d\n", vdev_id); 8487 return -EPROTO; 8488 } 8489 8490 ath12k_dbg(ab, ATH12K_DBG_WMI, 8491 "stats bssid %pM vif %p\n", 8492 arvif->bssid, arvif->ahvif->vif); 8493 8494 guard(spinlock_bh)(&ab->base_lock); 8495 arsta = ath12k_link_sta_find_by_addr(ab, arvif->bssid); 8496 if (!arsta) { 8497 ath12k_warn(ab, 8498 "not found link sta with bssid %pM for rssi chain\n", 8499 arvif->bssid); 8500 return -EPROTO; 8501 } 8502 8503 BUILD_BUG_ON(ARRAY_SIZE(arsta->chain_signal) > 8504 ARRAY_SIZE(stats_rssi->rssi_avg_beacon)); 8505 8506 for (j = 0; j < ARRAY_SIZE(arsta->chain_signal); j++) 8507 arsta->chain_signal[j] = le32_to_cpu(stats_rssi->rssi_avg_beacon[j]); 8508 8509 stats->stats_id = WMI_REQUEST_RSSI_PER_CHAIN_STAT; 8510 8511 return 0; 8512 } 8513 8514 static int ath12k_wmi_tlv_fw_stats_parse(struct ath12k_base *ab, 8515 u16 tag, u16 len, 8516 const void *ptr, void *data) 8517 { 8518 struct wmi_tlv_fw_stats_parse *parse = data; 8519 int ret = 0; 8520 8521 switch (tag) { 8522 case WMI_TAG_STATS_EVENT: 8523 parse->ev = ptr; 8524 break; 8525 case WMI_TAG_ARRAY_BYTE: 8526 ret = ath12k_wmi_tlv_fw_stats_data_parse(ab, parse, ptr, len); 8527 break; 8528 case WMI_TAG_PER_CHAIN_RSSI_STATS: 8529 parse->rssi = ptr; 8530 if (le32_to_cpu(parse->ev->stats_id) & WMI_REQUEST_RSSI_PER_CHAIN_STAT) 8531 parse->rssi_num = le32_to_cpu(parse->rssi->num_per_chain_rssi); 8532 break; 8533 case WMI_TAG_ARRAY_STRUCT: 8534 if (parse->rssi_num && !parse->chain_rssi_done) { 8535 ret = ath12k_wmi_tlv_iter(ab, ptr, len, 8536 ath12k_wmi_tlv_rssi_chain_parse, 8537 parse); 8538 if (ret) 8539 return ret; 8540 8541 parse->chain_rssi_done = true; 8542 } 8543 break; 8544 default: 8545 break; 8546 } 8547 return ret; 8548 } 8549 8550 static int ath12k_wmi_pull_fw_stats(struct ath12k_base *ab, struct sk_buff *skb, 8551 struct ath12k_fw_stats *stats) 8552 { 8553 struct wmi_tlv_fw_stats_parse parse = {}; 8554 8555 stats->stats_id = 0; 8556 parse.stats = stats; 8557 8558 return ath12k_wmi_tlv_iter(ab, skb->data, skb->len, 8559 ath12k_wmi_tlv_fw_stats_parse, 8560 &parse); 8561 } 8562 8563 static void ath12k_wmi_fw_stats_process(struct ath12k *ar, 8564 struct ath12k_fw_stats *stats) 8565 { 8566 struct ath12k_base *ab = ar->ab; 8567 struct ath12k_pdev *pdev; 8568 bool is_end = true; 8569 size_t total_vdevs_started = 0; 8570 int i; 8571 8572 if (stats->stats_id == WMI_REQUEST_VDEV_STAT) { 8573 if (list_empty(&stats->vdevs)) { 8574 ath12k_warn(ab, "empty vdev stats"); 8575 return; 8576 } 8577 /* FW sends all the active VDEV stats irrespective of PDEV, 8578 * hence limit until the count of all VDEVs started 8579 */ 8580 rcu_read_lock(); 8581 for (i = 0; i < ab->num_radios; i++) { 8582 pdev = rcu_dereference(ab->pdevs_active[i]); 8583 if (pdev && pdev->ar) 8584 total_vdevs_started += pdev->ar->num_started_vdevs; 8585 } 8586 rcu_read_unlock(); 8587 8588 if (total_vdevs_started) 8589 is_end = ((++ar->fw_stats.num_vdev_recvd) == 8590 total_vdevs_started); 8591 8592 list_splice_tail_init(&stats->vdevs, 8593 &ar->fw_stats.vdevs); 8594 8595 if (is_end) 8596 complete(&ar->fw_stats_done); 8597 8598 return; 8599 } 8600 8601 if (stats->stats_id == WMI_REQUEST_BCN_STAT) { 8602 if (list_empty(&stats->bcn)) { 8603 ath12k_warn(ab, "empty beacon stats"); 8604 return; 8605 } 8606 8607 list_splice_tail_init(&stats->bcn, 8608 &ar->fw_stats.bcn); 8609 complete(&ar->fw_stats_done); 8610 } 8611 } 8612 8613 static void ath12k_update_stats_event(struct ath12k_base *ab, struct sk_buff *skb) 8614 { 8615 struct ath12k_fw_stats stats = {}; 8616 struct ath12k *ar; 8617 int ret; 8618 8619 INIT_LIST_HEAD(&stats.pdevs); 8620 INIT_LIST_HEAD(&stats.vdevs); 8621 INIT_LIST_HEAD(&stats.bcn); 8622 8623 ret = ath12k_wmi_pull_fw_stats(ab, skb, &stats); 8624 if (ret) { 8625 ath12k_warn(ab, "failed to pull fw stats: %d\n", ret); 8626 goto free; 8627 } 8628 8629 ath12k_dbg(ab, ATH12K_DBG_WMI, "event update stats"); 8630 8631 rcu_read_lock(); 8632 ar = ath12k_mac_get_ar_by_pdev_id(ab, stats.pdev_id); 8633 if (!ar) { 8634 rcu_read_unlock(); 8635 ath12k_warn(ab, "failed to get ar for pdev_id %d: %d\n", 8636 stats.pdev_id, ret); 8637 goto free; 8638 } 8639 8640 spin_lock_bh(&ar->data_lock); 8641 8642 /* Handle WMI_REQUEST_PDEV_STAT status update */ 8643 if (stats.stats_id == WMI_REQUEST_PDEV_STAT) { 8644 list_splice_tail_init(&stats.pdevs, &ar->fw_stats.pdevs); 8645 complete(&ar->fw_stats_done); 8646 goto complete; 8647 } 8648 8649 /* Handle WMI_REQUEST_RSSI_PER_CHAIN_STAT status update */ 8650 if (stats.stats_id == WMI_REQUEST_RSSI_PER_CHAIN_STAT) { 8651 complete(&ar->fw_stats_done); 8652 goto complete; 8653 } 8654 8655 /* Handle WMI_REQUEST_VDEV_STAT and WMI_REQUEST_BCN_STAT updates. */ 8656 ath12k_wmi_fw_stats_process(ar, &stats); 8657 8658 complete: 8659 complete(&ar->fw_stats_complete); 8660 spin_unlock_bh(&ar->data_lock); 8661 rcu_read_unlock(); 8662 8663 /* Since the stats's pdev, vdev and beacon list are spliced and reinitialised 8664 * at this point, no need to free the individual list. 8665 */ 8666 return; 8667 8668 free: 8669 ath12k_fw_stats_free(&stats); 8670 } 8671 8672 /* PDEV_CTL_FAILSAFE_CHECK_EVENT is received from FW when the frequency scanned 8673 * is not part of BDF CTL(Conformance test limits) table entries. 8674 */ 8675 static void ath12k_pdev_ctl_failsafe_check_event(struct ath12k_base *ab, 8676 struct sk_buff *skb) 8677 { 8678 const void **tb; 8679 const struct wmi_pdev_ctl_failsafe_chk_event *ev; 8680 int ret; 8681 8682 tb = ath12k_wmi_tlv_parse(ab, skb); 8683 if (IS_ERR(tb)) { 8684 ret = PTR_ERR(tb); 8685 ath12k_warn(ab, "failed to parse tlv: %d\n", ret); 8686 return; 8687 } 8688 8689 ev = tb[WMI_TAG_PDEV_CTL_FAILSAFE_CHECK_EVENT]; 8690 if (!ev) { 8691 ath12k_warn(ab, "failed to fetch pdev ctl failsafe check ev"); 8692 return; 8693 } 8694 8695 ath12k_dbg(ab, ATH12K_DBG_WMI, 8696 "pdev ctl failsafe check ev status %d\n", 8697 ev->ctl_failsafe_status); 8698 8699 /* If ctl_failsafe_status is set to 1 FW will max out the Transmit power 8700 * to 10 dBm else the CTL power entry in the BDF would be picked up. 8701 */ 8702 if (ev->ctl_failsafe_status != 0) 8703 ath12k_warn(ab, "pdev ctl failsafe failure status %d", 8704 ev->ctl_failsafe_status); 8705 } 8706 8707 static int 8708 ath12k_wmi_incumbent_signal_interference_subtlv_parser(struct ath12k_base *ab, 8709 u16 tag, u16 len, 8710 const void *ptr, 8711 void *data) 8712 { 8713 const struct ath12k_wmi_incumbent_signal_interference_params *info; 8714 struct ath12k_wmi_incumbent_signal_interference_arg *arg = data; 8715 8716 switch (tag) { 8717 case WMI_TAG_DCS_INCUMBENT_SIGNAL_INTERFERENCE_TYPE: 8718 if (len < sizeof(*info)) { 8719 ath12k_warn(ab, 8720 "DCS incumbent signal interference subtlv 0x%x invalid len %u\n", 8721 tag, len); 8722 return -EINVAL; 8723 } 8724 8725 info = ptr; 8726 8727 arg->chan_width = le32_to_cpu(info->chan_width); 8728 arg->chan_freq = le32_to_cpu(info->chan_freq); 8729 arg->center_freq0 = le32_to_cpu(info->center_freq0); 8730 arg->center_freq1 = le32_to_cpu(info->center_freq1); 8731 arg->chan_bw_interference_bitmap = 8732 le32_to_cpu(info->chan_bw_interference_bitmap); 8733 8734 ath12k_dbg(ab, ATH12K_DBG_WMI, 8735 "incumbent signal interference chan width %u freq %u center_freq0 %u center_freq1 %u bitmap 0x%x\n", 8736 arg->chan_width, arg->chan_freq, 8737 arg->center_freq0, arg->center_freq1, 8738 arg->chan_bw_interference_bitmap); 8739 break; 8740 default: 8741 ath12k_warn(ab, "Received invalid tag 0x%x for WMI DCS interference in subtlvs\n", 8742 tag); 8743 return -EINVAL; 8744 } 8745 8746 return 0; 8747 } 8748 8749 static int ath12k_wmi_dcs_interference_event_parser(struct ath12k_base *ab, 8750 u16 tag, u16 len, 8751 const void *ptr, void *data) 8752 { 8753 int ret = 0; 8754 8755 switch (tag) { 8756 case WMI_TAG_DCS_INTERFERENCE_EVENT: 8757 /* Fixed param should already be processed */ 8758 break; 8759 case WMI_TAG_ARRAY_STRUCT: 8760 ret = ath12k_wmi_tlv_iter(ab, ptr, len, 8761 ath12k_wmi_incumbent_signal_interference_subtlv_parser, 8762 data); 8763 break; 8764 default: 8765 ath12k_warn(ab, "Received invalid tag 0x%x for WMI DCS interference event\n", 8766 tag); 8767 ret = -EINVAL; 8768 break; 8769 } 8770 8771 return ret; 8772 } 8773 8774 static bool 8775 ath12k_wmi_validate_interference_info(struct ath12k *ar, 8776 struct ath12k_wmi_incumbent_signal_interference_arg *info) 8777 { 8778 switch (info->chan_width) { 8779 case WMI_CHAN_WIDTH_20: 8780 if (info->chan_bw_interference_bitmap > ATH12K_WMI_DCS_SEG_PRI20) { 8781 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 8782 "DCS interference event received with wrong chan width bmap 0x%x for 20 MHz", 8783 info->chan_bw_interference_bitmap); 8784 return false; 8785 } 8786 break; 8787 case WMI_CHAN_WIDTH_40: 8788 if (info->chan_bw_interference_bitmap > (ATH12K_WMI_DCS_SEG_PRI20 | 8789 ATH12K_WMI_DCS_SEG_SEC20)) { 8790 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 8791 "DCS interference event received with wrong chan width bmap 0x%x for 40 MHz", 8792 info->chan_bw_interference_bitmap); 8793 return false; 8794 } 8795 break; 8796 case WMI_CHAN_WIDTH_80: 8797 if (info->chan_bw_interference_bitmap > (ATH12K_WMI_DCS_SEG_PRI20 | 8798 ATH12K_WMI_DCS_SEG_SEC20 | 8799 ATH12K_WMI_DCS_SEG_SEC40)) { 8800 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 8801 "DCS interference event received with wrong chan width bmap 0x%x for 80 MHz", 8802 info->chan_bw_interference_bitmap); 8803 return false; 8804 } 8805 break; 8806 case WMI_CHAN_WIDTH_160: 8807 if (info->chan_bw_interference_bitmap > (ATH12K_WMI_DCS_SEG_PRI20 | 8808 ATH12K_WMI_DCS_SEG_SEC20 | 8809 ATH12K_WMI_DCS_SEG_SEC40 | 8810 ATH12K_WMI_DCS_SEG_SEC80)) { 8811 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 8812 "DCS interference event received with wrong chan width bmap 0x%x for 160 MHz", 8813 info->chan_bw_interference_bitmap); 8814 return false; 8815 } 8816 break; 8817 case WMI_CHAN_WIDTH_320: 8818 if (info->chan_bw_interference_bitmap > (ATH12K_WMI_DCS_SEG_PRI20 | 8819 ATH12K_WMI_DCS_SEG_SEC20 | 8820 ATH12K_WMI_DCS_SEG_SEC40 | 8821 ATH12K_WMI_DCS_SEG_SEC80 | 8822 ATH12K_WMI_DCS_SEG_SEC160)) { 8823 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 8824 "DCS interference event received with wrong chan width bmap 0x%x for 320 MHz", 8825 info->chan_bw_interference_bitmap); 8826 return false; 8827 } 8828 break; 8829 default: 8830 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 8831 "DCS interference event received with unknown channel width %u", 8832 info->chan_width); 8833 return false; 8834 } 8835 return true; 8836 } 8837 8838 static u32 8839 ath12k_wmi_transform_interference_bitmap(int input_bitmap, 8840 struct cfg80211_chan_def *chandef) 8841 { 8842 u16 output_bits[ATH12K_MAX_20MHZ_SEGMENTS] = {}; 8843 u16 input_bits[ATH12K_MAX_20MHZ_SEGMENTS] = {}; 8844 u32 start_freq, segment_freq; 8845 int primary_index = -1; 8846 u32 output_bitmap = 0; 8847 u16 num_sub_chans; 8848 int bandwidth; 8849 8850 bandwidth = nl80211_chan_width_to_mhz(chandef->width); 8851 if (bandwidth < 0) 8852 return 0; 8853 8854 /* 8855 * Firmware reports bit 0 as primary 20 MHz irrespective of absolute 8856 * frequency position. Convert to standardized lowest-to-highest 20 MHz 8857 * ordering expected by cfg80211/mac80211 userspace consumers. 8858 */ 8859 num_sub_chans = bandwidth / 20; 8860 start_freq = (chandef->center_freq1 - bandwidth / 2) + 10; 8861 8862 for (int i = 0; i < ATH12K_MAX_20MHZ_SEGMENTS; i++) { 8863 segment_freq = start_freq + (i * 20); 8864 if (segment_freq == chandef->chan->center_freq) { 8865 primary_index = i; 8866 break; 8867 } 8868 } 8869 if (primary_index == -1) 8870 return 0; 8871 8872 for (int i = 0; i < ATH12K_MAX_20MHZ_SEGMENTS; ++i) 8873 input_bits[i] = BIT(i) & input_bitmap; 8874 8875 for (int i = 0; i < num_sub_chans; ++i) { 8876 int src = i, dst = i; 8877 8878 switch (bandwidth) { 8879 case 40: 8880 if (primary_index == 1) 8881 dst = 1 - i; 8882 break; 8883 case 80: 8884 dst = intf_map_80[primary_index][i]; 8885 break; 8886 case 160: 8887 dst = intf_map_160[primary_index][i]; 8888 break; 8889 case 320: 8890 dst = intf_map_320[primary_index][i]; 8891 break; 8892 } 8893 output_bits[dst] = input_bits[src]; 8894 } 8895 8896 for (int i = 0; i < ATH12K_MAX_20MHZ_SEGMENTS; ++i) 8897 output_bitmap |= output_bits[i] ? BIT(i) : 0; 8898 8899 return output_bitmap; 8900 } 8901 8902 static void 8903 ath12k_wmi_process_incumbent_signal_interference_evt(struct ath12k_base *ab, 8904 struct sk_buff *skb, 8905 const struct ath12k_wmi_intf_arg *intf_arg) 8906 { 8907 struct ath12k_wmi_incumbent_signal_interference_arg info = {}; 8908 struct ath12k_incumbent_signal_interference *incumbent; 8909 struct ath12k_mac_get_any_chanctx_conf_arg arg; 8910 u32 transformed_intf_bitmap; 8911 struct ieee80211_hw *hw; 8912 struct ath12k *ar; 8913 int ret; 8914 8915 guard(rcu)(); 8916 8917 ar = ath12k_mac_get_ar_by_pdev_id(ab, intf_arg->pdev_id); 8918 if (!ar) { 8919 ath12k_warn(ab, "incumbent signal interference detected on invalid pdev %d\n", 8920 intf_arg->pdev_id); 8921 return; 8922 } 8923 if (!ar->supports_6ghz) { 8924 ath12k_warn(ab, "pdev does not support 6 GHz, dropping DCS interference event\n"); 8925 return; 8926 } 8927 8928 incumbent = &ar->incumbent_signal_interference; 8929 spin_lock_bh(&ar->data_lock); 8930 if (incumbent->handling_in_progress) { 8931 spin_unlock_bh(&ar->data_lock); 8932 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 8933 "incumbent signal interference handling ongoing, dropping DCS interference event"); 8934 return; 8935 } 8936 spin_unlock_bh(&ar->data_lock); 8937 8938 ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, 8939 ath12k_wmi_dcs_interference_event_parser, 8940 &info); 8941 if (ret) { 8942 ath12k_warn(ab, 8943 "failed to parse incumbent signal interference TLV. Error %d\n", 8944 ret); 8945 return; 8946 } 8947 8948 if (!ath12k_wmi_validate_interference_info(ar, &info)) { 8949 ath12k_warn(ab, "invalid DCS incumbent signal interference TLV - Skipping event"); 8950 return; 8951 } 8952 8953 arg.ar = ar; 8954 arg.chanctx_conf = NULL; 8955 hw = ath12k_ar_to_hw(ar); 8956 ieee80211_iter_chan_contexts_atomic(hw, 8957 ath12k_mac_get_any_chanctx_conf_iter, 8958 &arg); 8959 if (!arg.chanctx_conf) { 8960 ath12k_warn(ab, "failed to find valid chanctx_conf in incumbent signal intf detected event\n"); 8961 return; 8962 } 8963 8964 if (info.chan_freq != arg.chanctx_conf->def.chan->center_freq) { 8965 ath12k_dbg(ab, ATH12K_DBG_WMI, 8966 "dcs interference event received with wrong channel %d (ctx freq %d)", 8967 info.chan_freq, arg.chanctx_conf->def.chan->center_freq); 8968 return; 8969 } 8970 8971 spin_lock_bh(&ar->data_lock); 8972 incumbent->center_freq = arg.chanctx_conf->def.chan->center_freq; 8973 incumbent->width = arg.chanctx_conf->def.width; 8974 incumbent->chan_bw_interference_bitmap = info.chan_bw_interference_bitmap; 8975 incumbent->handling_in_progress = true; 8976 spin_unlock_bh(&ar->data_lock); 8977 transformed_intf_bitmap = 8978 ath12k_wmi_transform_interference_bitmap(info.chan_bw_interference_bitmap, 8979 &arg.chanctx_conf->def); 8980 ath12k_dbg(ab, ATH12K_DBG_WMI, 8981 "incumbent signal interference bitmap 0x%x (transformed 0x%x)\n", 8982 info.chan_bw_interference_bitmap, transformed_intf_bitmap); 8983 cfg80211_incumbent_signal_notify(hw->wiphy, 8984 &arg.chanctx_conf->def, 8985 transformed_intf_bitmap, 8986 GFP_ATOMIC); 8987 } 8988 8989 static void 8990 ath12k_wmi_dcs_interference_event(struct ath12k_base *ab, 8991 struct sk_buff *skb) 8992 { 8993 const struct ath12k_wmi_dcs_interference_ev_fixed_params *dcs_intf_ev; 8994 struct ath12k_wmi_intf_arg dcs_intf_arg; 8995 const struct wmi_tlv *tlv; 8996 u16 tlv_tag; 8997 u8 *ptr; 8998 8999 if (skb->len < (sizeof(*dcs_intf_ev) + TLV_HDR_SIZE)) { 9000 ath12k_warn(ab, "DCS interference event is of incorrect length\n"); 9001 return; 9002 } 9003 9004 ptr = skb->data; 9005 tlv = (struct wmi_tlv *)ptr; 9006 tlv_tag = le32_get_bits(tlv->header, WMI_TLV_TAG); 9007 ptr += sizeof(*tlv); 9008 9009 if (tlv_tag != WMI_TAG_DCS_INTERFERENCE_EVENT) { 9010 ath12k_warn(ab, "DCS interference event received with wrong tag\n"); 9011 return; 9012 } 9013 9014 dcs_intf_ev = (struct ath12k_wmi_dcs_interference_ev_fixed_params *)ptr; 9015 9016 dcs_intf_arg.interference_type = 9017 le32_to_cpu(dcs_intf_ev->interference_type); 9018 dcs_intf_arg.pdev_id = le32_to_cpu(dcs_intf_ev->pdev_id); 9019 9020 if (dcs_intf_arg.interference_type == 9021 ATH12K_WMI_DCS_INCUMBENT_SIGNAL_INTERFERENCE) { 9022 ath12k_dbg(ab, ATH12K_DBG_WMI, 9023 "incumbent signal interference (Type %u) detected on pdev %u.", 9024 dcs_intf_arg.interference_type, 9025 dcs_intf_arg.pdev_id); 9026 ath12k_wmi_process_incumbent_signal_interference_evt(ab, skb, 9027 &dcs_intf_arg); 9028 } 9029 } 9030 9031 static void 9032 ath12k_wmi_process_csa_switch_count_event(struct ath12k_base *ab, 9033 const struct ath12k_wmi_pdev_csa_event *ev, 9034 const u32 *vdev_ids) 9035 { 9036 u32 current_switch_count = le32_to_cpu(ev->current_switch_count); 9037 u32 num_vdevs = le32_to_cpu(ev->num_vdevs); 9038 struct ieee80211_bss_conf *conf; 9039 struct ath12k_link_vif *arvif; 9040 struct ath12k_vif *ahvif; 9041 int i; 9042 9043 rcu_read_lock(); 9044 for (i = 0; i < num_vdevs; i++) { 9045 arvif = ath12k_mac_get_arvif_by_vdev_id(ab, vdev_ids[i]); 9046 9047 if (!arvif) { 9048 ath12k_warn(ab, "Recvd csa status for unknown vdev %d", 9049 vdev_ids[i]); 9050 continue; 9051 } 9052 ahvif = arvif->ahvif; 9053 9054 if (arvif->link_id >= IEEE80211_MLD_MAX_NUM_LINKS) { 9055 ath12k_warn(ab, "Invalid CSA switch count even link id: %d\n", 9056 arvif->link_id); 9057 continue; 9058 } 9059 9060 conf = rcu_dereference(ahvif->vif->link_conf[arvif->link_id]); 9061 if (!conf) { 9062 ath12k_warn(ab, "unable to access bss link conf in process csa for vif %pM link %u\n", 9063 ahvif->vif->addr, arvif->link_id); 9064 continue; 9065 } 9066 9067 if (!arvif->is_up || !conf->csa_active) 9068 continue; 9069 9070 /* Finish CSA when counter reaches zero */ 9071 if (!current_switch_count) { 9072 ieee80211_csa_finish(ahvif->vif, arvif->link_id); 9073 arvif->current_cntdown_counter = 0; 9074 } else if (current_switch_count > 1) { 9075 /* If the count in event is not what we expect, don't update the 9076 * mac80211 count. Since during beacon Tx failure, count in the 9077 * firmware will not decrement and this event will come with the 9078 * previous count value again 9079 */ 9080 if (current_switch_count != arvif->current_cntdown_counter) 9081 continue; 9082 9083 arvif->current_cntdown_counter = 9084 ieee80211_beacon_update_cntdwn(ahvif->vif, 9085 arvif->link_id); 9086 } 9087 } 9088 rcu_read_unlock(); 9089 } 9090 9091 static void 9092 ath12k_wmi_pdev_csa_switch_count_status_event(struct ath12k_base *ab, 9093 struct sk_buff *skb) 9094 { 9095 const void **tb; 9096 const struct ath12k_wmi_pdev_csa_event *ev; 9097 const u32 *vdev_ids; 9098 int ret; 9099 9100 tb = ath12k_wmi_tlv_parse(ab, skb); 9101 if (IS_ERR(tb)) { 9102 ret = PTR_ERR(tb); 9103 ath12k_warn(ab, "failed to parse tlv: %d\n", ret); 9104 return; 9105 } 9106 9107 ev = tb[WMI_TAG_PDEV_CSA_SWITCH_COUNT_STATUS_EVENT]; 9108 vdev_ids = tb[WMI_TAG_ARRAY_UINT32]; 9109 9110 if (!ev || !vdev_ids) { 9111 ath12k_warn(ab, "failed to fetch pdev csa switch count ev"); 9112 return; 9113 } 9114 9115 ath12k_dbg(ab, ATH12K_DBG_WMI, 9116 "pdev csa switch count %d for pdev %d, num_vdevs %d", 9117 ev->current_switch_count, ev->pdev_id, 9118 ev->num_vdevs); 9119 9120 ath12k_wmi_process_csa_switch_count_event(ab, ev, vdev_ids); 9121 } 9122 9123 static void 9124 ath12k_wmi_pdev_dfs_radar_detected_event(struct ath12k_base *ab, struct sk_buff *skb) 9125 { 9126 const void **tb; 9127 struct ath12k_mac_get_any_chanctx_conf_arg arg; 9128 const struct ath12k_wmi_pdev_radar_event *ev; 9129 struct ath12k *ar; 9130 int ret; 9131 9132 tb = ath12k_wmi_tlv_parse(ab, skb); 9133 if (IS_ERR(tb)) { 9134 ret = PTR_ERR(tb); 9135 ath12k_warn(ab, "failed to parse tlv: %d\n", ret); 9136 return; 9137 } 9138 9139 ev = tb[WMI_TAG_PDEV_DFS_RADAR_DETECTION_EVENT]; 9140 9141 if (!ev) { 9142 ath12k_warn(ab, "failed to fetch pdev dfs radar detected ev"); 9143 return; 9144 } 9145 9146 ath12k_dbg(ab, ATH12K_DBG_WMI, 9147 "pdev dfs radar detected on pdev %d, detection mode %d, chan freq %d, chan_width %d, detector id %d, seg id %d, timestamp %d, chirp %d, freq offset %d, sidx %d", 9148 ev->pdev_id, ev->detection_mode, ev->chan_freq, ev->chan_width, 9149 ev->detector_id, ev->segment_id, ev->timestamp, ev->is_chirp, 9150 ev->freq_offset, ev->sidx); 9151 9152 rcu_read_lock(); 9153 9154 ar = ath12k_mac_get_ar_by_pdev_id(ab, le32_to_cpu(ev->pdev_id)); 9155 9156 if (!ar) { 9157 ath12k_warn(ab, "radar detected in invalid pdev %d\n", 9158 ev->pdev_id); 9159 goto exit; 9160 } 9161 9162 arg.ar = ar; 9163 arg.chanctx_conf = NULL; 9164 ieee80211_iter_chan_contexts_atomic(ath12k_ar_to_hw(ar), 9165 ath12k_mac_get_any_chanctx_conf_iter, &arg); 9166 if (!arg.chanctx_conf) { 9167 ath12k_warn(ab, "failed to find valid chanctx_conf in radar detected event\n"); 9168 goto exit; 9169 } 9170 9171 ath12k_dbg(ar->ab, ATH12K_DBG_REG, "DFS Radar Detected in pdev %d\n", 9172 ev->pdev_id); 9173 9174 if (ar->dfs_block_radar_events) 9175 ath12k_info(ab, "DFS Radar detected, but ignored as requested\n"); 9176 else 9177 ieee80211_radar_detected(ath12k_ar_to_hw(ar), arg.chanctx_conf); 9178 9179 exit: 9180 rcu_read_unlock(); 9181 } 9182 9183 static void ath12k_tm_wmi_event_segmented(struct ath12k_base *ab, u32 cmd_id, 9184 struct sk_buff *skb) 9185 { 9186 const struct ath12k_wmi_ftm_event *ev; 9187 const void **tb; 9188 int ret; 9189 u16 length; 9190 9191 tb = ath12k_wmi_tlv_parse(ab, skb); 9192 9193 if (IS_ERR(tb)) { 9194 ret = PTR_ERR(tb); 9195 ath12k_warn(ab, "failed to parse ftm event tlv: %d\n", ret); 9196 return; 9197 } 9198 9199 ev = tb[WMI_TAG_ARRAY_BYTE]; 9200 if (!ev) { 9201 ath12k_warn(ab, "failed to fetch ftm msg\n"); 9202 return; 9203 } 9204 9205 length = skb->len - TLV_HDR_SIZE; 9206 ath12k_tm_process_event(ab, cmd_id, ev, length); 9207 } 9208 9209 static void 9210 ath12k_wmi_pdev_temperature_event(struct ath12k_base *ab, 9211 struct sk_buff *skb) 9212 { 9213 const struct wmi_pdev_temperature_event *ev; 9214 struct ath12k *ar; 9215 const void **tb; 9216 int temp; 9217 u32 pdev_id; 9218 9219 tb = ath12k_wmi_tlv_parse(ab, skb); 9220 if (IS_ERR(tb)) { 9221 ath12k_warn(ab, "failed to parse tlv: %ld\n", PTR_ERR(tb)); 9222 return; 9223 } 9224 9225 ev = tb[WMI_TAG_PDEV_TEMPERATURE_EVENT]; 9226 if (!ev) { 9227 ath12k_warn(ab, "failed to fetch pdev temp ev\n"); 9228 return; 9229 } 9230 9231 temp = a_sle32_to_cpu(ev->temp); 9232 pdev_id = le32_to_cpu(ev->pdev_id); 9233 9234 ath12k_dbg(ab, ATH12K_DBG_WMI, 9235 "pdev temperature ev temp %d pdev_id %u\n", 9236 temp, pdev_id); 9237 9238 rcu_read_lock(); 9239 9240 ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id); 9241 if (!ar) { 9242 ath12k_warn(ab, "invalid pdev id %u in pdev temperature ev\n", 9243 pdev_id); 9244 goto exit; 9245 } 9246 9247 ath12k_thermal_event_temperature(ar, temp); 9248 9249 exit: 9250 rcu_read_unlock(); 9251 } 9252 9253 static void ath12k_wmi_thermal_throt_stats_event(struct ath12k_base *ab, 9254 struct sk_buff *skb) 9255 { 9256 const struct wmi_therm_throt_stats_event *ev; 9257 struct ath12k *ar; 9258 const void **tb; 9259 9260 tb = ath12k_wmi_tlv_parse(ab, skb); 9261 if (IS_ERR(tb)) { 9262 ath12k_err(ab, "failed to parse thermal throttling stats tlv: %ld\n", 9263 PTR_ERR(tb)); 9264 return; 9265 } 9266 9267 ev = tb[WMI_TAG_THERM_THROT_STATS_EVENT]; 9268 if (!ev) { 9269 ath12k_err(ab, "failed to fetch thermal throt stats ev\n"); 9270 return; 9271 } 9272 9273 rcu_read_lock(); 9274 ar = ath12k_mac_get_ar_by_pdev_id(ab, le32_to_cpu(ev->pdev_id)); 9275 if (!ar) { 9276 ath12k_warn(ab, "received thermal_throt_stats in invalid pdev %u\n", 9277 le32_to_cpu(ev->pdev_id)); 9278 rcu_read_unlock(); 9279 return; 9280 } 9281 rcu_read_unlock(); 9282 9283 ath12k_dbg(ab, ATH12K_DBG_WMI, 9284 "thermal stats ev level %u pdev_id %u temp %u throt_levels %u\n", 9285 le32_to_cpu(ev->level), le32_to_cpu(ev->pdev_id), 9286 le32_to_cpu(ev->temp), le32_to_cpu(ev->therm_throt_levels)); 9287 } 9288 9289 static void ath12k_fils_discovery_event(struct ath12k_base *ab, 9290 struct sk_buff *skb) 9291 { 9292 const void **tb; 9293 const struct wmi_fils_discovery_event *ev; 9294 int ret; 9295 9296 tb = ath12k_wmi_tlv_parse(ab, skb); 9297 if (IS_ERR(tb)) { 9298 ret = PTR_ERR(tb); 9299 ath12k_warn(ab, 9300 "failed to parse FILS discovery event tlv %d\n", 9301 ret); 9302 return; 9303 } 9304 9305 ev = tb[WMI_TAG_HOST_SWFDA_EVENT]; 9306 if (!ev) { 9307 ath12k_warn(ab, "failed to fetch FILS discovery event\n"); 9308 return; 9309 } 9310 9311 ath12k_warn(ab, 9312 "FILS discovery frame expected from host for vdev_id: %u, transmission scheduled at %u, next TBTT: %u\n", 9313 ev->vdev_id, ev->fils_tt, ev->tbtt); 9314 } 9315 9316 static void ath12k_probe_resp_tx_status_event(struct ath12k_base *ab, 9317 struct sk_buff *skb) 9318 { 9319 const void **tb; 9320 const struct wmi_probe_resp_tx_status_event *ev; 9321 int ret; 9322 9323 tb = ath12k_wmi_tlv_parse(ab, skb); 9324 if (IS_ERR(tb)) { 9325 ret = PTR_ERR(tb); 9326 ath12k_warn(ab, 9327 "failed to parse probe response transmission status event tlv: %d\n", 9328 ret); 9329 return; 9330 } 9331 9332 ev = tb[WMI_TAG_OFFLOAD_PRB_RSP_TX_STATUS_EVENT]; 9333 if (!ev) { 9334 ath12k_warn(ab, 9335 "failed to fetch probe response transmission status event"); 9336 return; 9337 } 9338 9339 if (ev->tx_status) 9340 ath12k_warn(ab, 9341 "Probe response transmission failed for vdev_id %u, status %u\n", 9342 ev->vdev_id, ev->tx_status); 9343 } 9344 9345 static int ath12k_wmi_p2p_noa_event(struct ath12k_base *ab, 9346 struct sk_buff *skb) 9347 { 9348 const void **tb; 9349 const struct wmi_p2p_noa_event *ev; 9350 const struct ath12k_wmi_p2p_noa_info *noa; 9351 struct ath12k *ar; 9352 int ret, vdev_id; 9353 9354 tb = ath12k_wmi_tlv_parse(ab, skb); 9355 if (IS_ERR(tb)) { 9356 ret = PTR_ERR(tb); 9357 ath12k_warn(ab, "failed to parse P2P NoA TLV: %d\n", ret); 9358 return ret; 9359 } 9360 9361 ev = tb[WMI_TAG_P2P_NOA_EVENT]; 9362 noa = tb[WMI_TAG_P2P_NOA_INFO]; 9363 9364 if (!ev || !noa) 9365 return -EPROTO; 9366 9367 vdev_id = __le32_to_cpu(ev->vdev_id); 9368 9369 ath12k_dbg(ab, ATH12K_DBG_WMI, 9370 "wmi tlv p2p noa vdev_id %i descriptors %u\n", 9371 vdev_id, le32_get_bits(noa->noa_attr, WMI_P2P_NOA_INFO_DESC_NUM)); 9372 9373 rcu_read_lock(); 9374 ar = ath12k_mac_get_ar_by_vdev_id(ab, vdev_id); 9375 if (!ar) { 9376 ath12k_warn(ab, "invalid vdev id %d in P2P NoA event\n", 9377 vdev_id); 9378 ret = -EINVAL; 9379 goto unlock; 9380 } 9381 9382 ath12k_p2p_noa_update_by_vdev_id(ar, vdev_id, noa); 9383 9384 ret = 0; 9385 9386 unlock: 9387 rcu_read_unlock(); 9388 return ret; 9389 } 9390 9391 static void ath12k_rfkill_state_change_event(struct ath12k_base *ab, 9392 struct sk_buff *skb) 9393 { 9394 const struct wmi_rfkill_state_change_event *ev; 9395 const void **tb; 9396 int ret; 9397 9398 tb = ath12k_wmi_tlv_parse(ab, skb); 9399 if (IS_ERR(tb)) { 9400 ret = PTR_ERR(tb); 9401 ath12k_warn(ab, "failed to parse tlv: %d\n", ret); 9402 return; 9403 } 9404 9405 ev = tb[WMI_TAG_RFKILL_EVENT]; 9406 if (!ev) 9407 return; 9408 9409 ath12k_dbg(ab, ATH12K_DBG_MAC, 9410 "wmi tlv rfkill state change gpio %d type %d radio_state %d\n", 9411 le32_to_cpu(ev->gpio_pin_num), 9412 le32_to_cpu(ev->int_type), 9413 le32_to_cpu(ev->radio_state)); 9414 9415 spin_lock_bh(&ab->base_lock); 9416 ab->rfkill_radio_on = (ev->radio_state == cpu_to_le32(WMI_RFKILL_RADIO_STATE_ON)); 9417 spin_unlock_bh(&ab->base_lock); 9418 9419 queue_work(ab->workqueue, &ab->rfkill_work); 9420 } 9421 9422 static void 9423 ath12k_wmi_diag_event(struct ath12k_base *ab, struct sk_buff *skb) 9424 { 9425 trace_ath12k_wmi_diag(ab, skb->data, skb->len); 9426 } 9427 9428 static void ath12k_wmi_twt_enable_event(struct ath12k_base *ab, 9429 struct sk_buff *skb) 9430 { 9431 const void **tb; 9432 const struct wmi_twt_enable_event *ev; 9433 int ret; 9434 9435 tb = ath12k_wmi_tlv_parse(ab, skb); 9436 if (IS_ERR(tb)) { 9437 ret = PTR_ERR(tb); 9438 ath12k_warn(ab, "failed to parse wmi twt enable status event tlv: %d\n", 9439 ret); 9440 return; 9441 } 9442 9443 ev = tb[WMI_TAG_TWT_ENABLE_COMPLETE_EVENT]; 9444 if (!ev) { 9445 ath12k_warn(ab, "failed to fetch twt enable wmi event\n"); 9446 return; 9447 } 9448 9449 ath12k_dbg(ab, ATH12K_DBG_MAC, "wmi twt enable event pdev id %u status %u\n", 9450 le32_to_cpu(ev->pdev_id), 9451 le32_to_cpu(ev->status)); 9452 } 9453 9454 static void ath12k_wmi_twt_disable_event(struct ath12k_base *ab, 9455 struct sk_buff *skb) 9456 { 9457 const void **tb; 9458 const struct wmi_twt_disable_event *ev; 9459 int ret; 9460 9461 tb = ath12k_wmi_tlv_parse(ab, skb); 9462 if (IS_ERR(tb)) { 9463 ret = PTR_ERR(tb); 9464 ath12k_warn(ab, "failed to parse wmi twt disable status event tlv: %d\n", 9465 ret); 9466 return; 9467 } 9468 9469 ev = tb[WMI_TAG_TWT_DISABLE_COMPLETE_EVENT]; 9470 if (!ev) { 9471 ath12k_warn(ab, "failed to fetch twt disable wmi event\n"); 9472 return; 9473 } 9474 9475 ath12k_dbg(ab, ATH12K_DBG_MAC, "wmi twt disable event pdev id %d status %u\n", 9476 le32_to_cpu(ev->pdev_id), 9477 le32_to_cpu(ev->status)); 9478 } 9479 9480 static int ath12k_wmi_wow_wakeup_host_parse(struct ath12k_base *ab, 9481 u16 tag, u16 len, 9482 const void *ptr, void *data) 9483 { 9484 const struct wmi_wow_ev_pg_fault_param *pf_param; 9485 const struct wmi_wow_ev_param *param; 9486 struct wmi_wow_ev_arg *arg = data; 9487 int pf_len; 9488 9489 switch (tag) { 9490 case WMI_TAG_WOW_EVENT_INFO: 9491 param = ptr; 9492 arg->wake_reason = le32_to_cpu(param->wake_reason); 9493 ath12k_dbg(ab, ATH12K_DBG_WMI, "wow wakeup host reason %d %s\n", 9494 arg->wake_reason, wow_reason(arg->wake_reason)); 9495 break; 9496 9497 case WMI_TAG_ARRAY_BYTE: 9498 if (arg && arg->wake_reason == WOW_REASON_PAGE_FAULT) { 9499 pf_param = ptr; 9500 pf_len = le32_to_cpu(pf_param->len); 9501 if (pf_len > len - sizeof(pf_len) || 9502 pf_len < 0) { 9503 ath12k_warn(ab, "invalid wo reason page fault buffer len %d\n", 9504 pf_len); 9505 return -EINVAL; 9506 } 9507 ath12k_dbg(ab, ATH12K_DBG_WMI, "wow_reason_page_fault len %d\n", 9508 pf_len); 9509 ath12k_dbg_dump(ab, ATH12K_DBG_WMI, 9510 "wow_reason_page_fault packet present", 9511 "wow_pg_fault ", 9512 pf_param->data, 9513 pf_len); 9514 } 9515 break; 9516 default: 9517 break; 9518 } 9519 9520 return 0; 9521 } 9522 9523 static void ath12k_wmi_event_wow_wakeup_host(struct ath12k_base *ab, struct sk_buff *skb) 9524 { 9525 struct wmi_wow_ev_arg arg = { }; 9526 int ret; 9527 9528 ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, 9529 ath12k_wmi_wow_wakeup_host_parse, 9530 &arg); 9531 if (ret) { 9532 ath12k_warn(ab, "failed to parse wmi wow wakeup host event tlv: %d\n", 9533 ret); 9534 return; 9535 } 9536 9537 complete(&ab->wow.wakeup_completed); 9538 } 9539 9540 static void ath12k_wmi_gtk_offload_status_event(struct ath12k_base *ab, 9541 struct sk_buff *skb) 9542 { 9543 const struct wmi_gtk_offload_status_event *ev; 9544 struct ath12k_link_vif *arvif; 9545 __be64 replay_ctr_be; 9546 u64 replay_ctr; 9547 const void **tb; 9548 int ret; 9549 9550 tb = ath12k_wmi_tlv_parse(ab, skb); 9551 if (IS_ERR(tb)) { 9552 ret = PTR_ERR(tb); 9553 ath12k_warn(ab, "failed to parse tlv: %d\n", ret); 9554 return; 9555 } 9556 9557 ev = tb[WMI_TAG_GTK_OFFLOAD_STATUS_EVENT]; 9558 if (!ev) { 9559 ath12k_warn(ab, "failed to fetch gtk offload status ev"); 9560 return; 9561 } 9562 9563 rcu_read_lock(); 9564 arvif = ath12k_mac_get_arvif_by_vdev_id(ab, le32_to_cpu(ev->vdev_id)); 9565 if (!arvif) { 9566 rcu_read_unlock(); 9567 ath12k_warn(ab, "failed to get arvif for vdev_id:%d\n", 9568 le32_to_cpu(ev->vdev_id)); 9569 return; 9570 } 9571 9572 replay_ctr = le64_to_cpu(ev->replay_ctr); 9573 arvif->rekey_data.replay_ctr = replay_ctr; 9574 ath12k_dbg(ab, ATH12K_DBG_WMI, "wmi gtk offload event refresh_cnt %d replay_ctr %llu\n", 9575 le32_to_cpu(ev->refresh_cnt), replay_ctr); 9576 9577 /* supplicant expects big-endian replay counter */ 9578 replay_ctr_be = cpu_to_be64(replay_ctr); 9579 9580 ieee80211_gtk_rekey_notify(arvif->ahvif->vif, arvif->bssid, 9581 (void *)&replay_ctr_be, GFP_ATOMIC); 9582 9583 rcu_read_unlock(); 9584 } 9585 9586 static void ath12k_wmi_event_mlo_setup_complete(struct ath12k_base *ab, 9587 struct sk_buff *skb) 9588 { 9589 const struct wmi_mlo_setup_complete_event *ev; 9590 struct ath12k *ar = NULL; 9591 struct ath12k_pdev *pdev; 9592 const void **tb; 9593 int ret, i; 9594 9595 tb = ath12k_wmi_tlv_parse(ab, skb); 9596 if (IS_ERR(tb)) { 9597 ret = PTR_ERR(tb); 9598 ath12k_warn(ab, "failed to parse mlo setup complete event tlv: %d\n", 9599 ret); 9600 return; 9601 } 9602 9603 ev = tb[WMI_TAG_MLO_SETUP_COMPLETE_EVENT]; 9604 if (!ev) { 9605 ath12k_warn(ab, "failed to fetch mlo setup complete event\n"); 9606 return; 9607 } 9608 9609 if (le32_to_cpu(ev->pdev_id) > ab->num_radios) 9610 goto skip_lookup; 9611 9612 for (i = 0; i < ab->num_radios; i++) { 9613 pdev = &ab->pdevs[i]; 9614 if (pdev && pdev->pdev_id == le32_to_cpu(ev->pdev_id)) { 9615 ar = pdev->ar; 9616 break; 9617 } 9618 } 9619 9620 skip_lookup: 9621 if (!ar) { 9622 ath12k_warn(ab, "invalid pdev_id %d status %u in setup complete event\n", 9623 ev->pdev_id, ev->status); 9624 return; 9625 } 9626 9627 ar->mlo_setup_status = le32_to_cpu(ev->status); 9628 complete(&ar->mlo_setup_done); 9629 } 9630 9631 static void ath12k_wmi_event_teardown_complete(struct ath12k_base *ab, 9632 struct sk_buff *skb) 9633 { 9634 const struct wmi_mlo_teardown_complete_event *ev; 9635 const void **tb; 9636 int ret; 9637 9638 tb = ath12k_wmi_tlv_parse(ab, skb); 9639 if (IS_ERR(tb)) { 9640 ret = PTR_ERR(tb); 9641 ath12k_warn(ab, "failed to parse teardown complete event tlv: %d\n", ret); 9642 return; 9643 } 9644 9645 ev = tb[WMI_TAG_MLO_TEARDOWN_COMPLETE]; 9646 if (!ev) 9647 ath12k_warn(ab, "failed to fetch teardown complete event\n"); 9648 } 9649 9650 #ifdef CONFIG_ATH12K_DEBUGFS 9651 static int ath12k_wmi_tpc_stats_copy_buffer(struct ath12k_base *ab, 9652 const void *ptr, u16 tag, u16 len, 9653 struct wmi_tpc_stats_arg *tpc_stats) 9654 { 9655 u32 len1, len2, len3, len4; 9656 s16 *dst_ptr; 9657 s8 *dst_ptr_ctl; 9658 9659 len1 = le32_to_cpu(tpc_stats->max_reg_allowed_power.tpc_reg_pwr.reg_array_len); 9660 len2 = le32_to_cpu(tpc_stats->rates_array1.tpc_rates_array.rate_array_len); 9661 len3 = le32_to_cpu(tpc_stats->rates_array2.tpc_rates_array.rate_array_len); 9662 len4 = le32_to_cpu(tpc_stats->ctl_array.tpc_ctl_pwr.ctl_array_len); 9663 9664 switch (tpc_stats->event_count) { 9665 case ATH12K_TPC_STATS_CONFIG_REG_PWR_EVENT: 9666 if (len1 > len) 9667 return -ENOBUFS; 9668 9669 if (tpc_stats->tlvs_rcvd & WMI_TPC_REG_PWR_ALLOWED) { 9670 dst_ptr = tpc_stats->max_reg_allowed_power.reg_pwr_array; 9671 memcpy(dst_ptr, ptr, len1); 9672 } 9673 break; 9674 case ATH12K_TPC_STATS_RATES_EVENT1: 9675 if (len2 > len) 9676 return -ENOBUFS; 9677 9678 if (tpc_stats->tlvs_rcvd & WMI_TPC_RATES_ARRAY1) { 9679 dst_ptr = tpc_stats->rates_array1.rate_array; 9680 memcpy(dst_ptr, ptr, len2); 9681 } 9682 break; 9683 case ATH12K_TPC_STATS_RATES_EVENT2: 9684 if (len3 > len) 9685 return -ENOBUFS; 9686 9687 if (tpc_stats->tlvs_rcvd & WMI_TPC_RATES_ARRAY2) { 9688 dst_ptr = tpc_stats->rates_array2.rate_array; 9689 memcpy(dst_ptr, ptr, len3); 9690 } 9691 break; 9692 case ATH12K_TPC_STATS_CTL_TABLE_EVENT: 9693 if (len4 > len) 9694 return -ENOBUFS; 9695 9696 if (tpc_stats->tlvs_rcvd & WMI_TPC_CTL_PWR_ARRAY) { 9697 dst_ptr_ctl = tpc_stats->ctl_array.ctl_pwr_table; 9698 memcpy(dst_ptr_ctl, ptr, len4); 9699 } 9700 break; 9701 } 9702 return 0; 9703 } 9704 9705 static int ath12k_tpc_get_reg_pwr(struct ath12k_base *ab, 9706 struct wmi_tpc_stats_arg *tpc_stats, 9707 struct wmi_max_reg_power_fixed_params *ev) 9708 { 9709 struct wmi_max_reg_power_allowed_arg *reg_pwr; 9710 u32 total_size; 9711 9712 ath12k_dbg(ab, ATH12K_DBG_WMI, 9713 "Received reg power array type %d length %d for tpc stats\n", 9714 ev->reg_power_type, ev->reg_array_len); 9715 9716 switch (le32_to_cpu(ev->reg_power_type)) { 9717 case TPC_STATS_REG_PWR_ALLOWED_TYPE: 9718 reg_pwr = &tpc_stats->max_reg_allowed_power; 9719 break; 9720 default: 9721 return -EINVAL; 9722 } 9723 9724 /* Each entry is 2 byte hence multiplying the indices with 2 */ 9725 total_size = le32_to_cpu(ev->d1) * le32_to_cpu(ev->d2) * 9726 le32_to_cpu(ev->d3) * le32_to_cpu(ev->d4) * 2; 9727 if (le32_to_cpu(ev->reg_array_len) != total_size) { 9728 ath12k_warn(ab, 9729 "Total size and reg_array_len doesn't match for tpc stats\n"); 9730 return -EINVAL; 9731 } 9732 9733 memcpy(®_pwr->tpc_reg_pwr, ev, sizeof(struct wmi_max_reg_power_fixed_params)); 9734 9735 reg_pwr->reg_pwr_array = kzalloc(le32_to_cpu(reg_pwr->tpc_reg_pwr.reg_array_len), 9736 GFP_ATOMIC); 9737 if (!reg_pwr->reg_pwr_array) 9738 return -ENOMEM; 9739 9740 tpc_stats->tlvs_rcvd |= WMI_TPC_REG_PWR_ALLOWED; 9741 9742 return 0; 9743 } 9744 9745 static int ath12k_tpc_get_rate_array(struct ath12k_base *ab, 9746 struct wmi_tpc_stats_arg *tpc_stats, 9747 struct wmi_tpc_rates_array_fixed_params *ev) 9748 { 9749 struct wmi_tpc_rates_array_arg *rates_array; 9750 u32 flag = 0, rate_array_len; 9751 9752 ath12k_dbg(ab, ATH12K_DBG_WMI, 9753 "Received rates array type %d length %d for tpc stats\n", 9754 ev->rate_array_type, ev->rate_array_len); 9755 9756 switch (le32_to_cpu(ev->rate_array_type)) { 9757 case ATH12K_TPC_STATS_RATES_ARRAY1: 9758 rates_array = &tpc_stats->rates_array1; 9759 flag = WMI_TPC_RATES_ARRAY1; 9760 break; 9761 case ATH12K_TPC_STATS_RATES_ARRAY2: 9762 rates_array = &tpc_stats->rates_array2; 9763 flag = WMI_TPC_RATES_ARRAY2; 9764 break; 9765 default: 9766 ath12k_warn(ab, 9767 "Received invalid type of rates array for tpc stats\n"); 9768 return -EINVAL; 9769 } 9770 memcpy(&rates_array->tpc_rates_array, ev, 9771 sizeof(struct wmi_tpc_rates_array_fixed_params)); 9772 rate_array_len = le32_to_cpu(rates_array->tpc_rates_array.rate_array_len); 9773 rates_array->rate_array = kzalloc(rate_array_len, GFP_ATOMIC); 9774 if (!rates_array->rate_array) 9775 return -ENOMEM; 9776 9777 tpc_stats->tlvs_rcvd |= flag; 9778 return 0; 9779 } 9780 9781 static int ath12k_tpc_get_ctl_pwr_tbl(struct ath12k_base *ab, 9782 struct wmi_tpc_stats_arg *tpc_stats, 9783 struct wmi_tpc_ctl_pwr_fixed_params *ev) 9784 { 9785 struct wmi_tpc_ctl_pwr_table_arg *ctl_array; 9786 u32 total_size, ctl_array_len, flag = 0; 9787 9788 ath12k_dbg(ab, ATH12K_DBG_WMI, 9789 "Received ctl array type %d length %d for tpc stats\n", 9790 ev->ctl_array_type, ev->ctl_array_len); 9791 9792 switch (le32_to_cpu(ev->ctl_array_type)) { 9793 case ATH12K_TPC_STATS_CTL_ARRAY: 9794 ctl_array = &tpc_stats->ctl_array; 9795 flag = WMI_TPC_CTL_PWR_ARRAY; 9796 break; 9797 default: 9798 ath12k_warn(ab, 9799 "Received invalid type of ctl pwr table for tpc stats\n"); 9800 return -EINVAL; 9801 } 9802 9803 total_size = le32_to_cpu(ev->d1) * le32_to_cpu(ev->d2) * 9804 le32_to_cpu(ev->d3) * le32_to_cpu(ev->d4); 9805 if (le32_to_cpu(ev->ctl_array_len) != total_size) { 9806 ath12k_warn(ab, 9807 "Total size and ctl_array_len doesn't match for tpc stats\n"); 9808 return -EINVAL; 9809 } 9810 9811 memcpy(&ctl_array->tpc_ctl_pwr, ev, sizeof(struct wmi_tpc_ctl_pwr_fixed_params)); 9812 ctl_array_len = le32_to_cpu(ctl_array->tpc_ctl_pwr.ctl_array_len); 9813 ctl_array->ctl_pwr_table = kzalloc(ctl_array_len, GFP_ATOMIC); 9814 if (!ctl_array->ctl_pwr_table) 9815 return -ENOMEM; 9816 9817 tpc_stats->tlvs_rcvd |= flag; 9818 return 0; 9819 } 9820 9821 static int ath12k_wmi_tpc_stats_subtlv_parser(struct ath12k_base *ab, 9822 u16 tag, u16 len, 9823 const void *ptr, void *data) 9824 { 9825 struct wmi_tpc_rates_array_fixed_params *tpc_rates_array; 9826 struct wmi_max_reg_power_fixed_params *tpc_reg_pwr; 9827 struct wmi_tpc_ctl_pwr_fixed_params *tpc_ctl_pwr; 9828 struct wmi_tpc_stats_arg *tpc_stats = data; 9829 struct wmi_tpc_config_params *tpc_config; 9830 int ret = 0; 9831 9832 if (!tpc_stats) { 9833 ath12k_warn(ab, "tpc stats memory unavailable\n"); 9834 return -EINVAL; 9835 } 9836 9837 switch (tag) { 9838 case WMI_TAG_TPC_STATS_CONFIG_EVENT: 9839 tpc_config = (struct wmi_tpc_config_params *)ptr; 9840 memcpy(&tpc_stats->tpc_config, tpc_config, 9841 sizeof(struct wmi_tpc_config_params)); 9842 break; 9843 case WMI_TAG_TPC_STATS_REG_PWR_ALLOWED: 9844 tpc_reg_pwr = (struct wmi_max_reg_power_fixed_params *)ptr; 9845 ret = ath12k_tpc_get_reg_pwr(ab, tpc_stats, tpc_reg_pwr); 9846 break; 9847 case WMI_TAG_TPC_STATS_RATES_ARRAY: 9848 tpc_rates_array = (struct wmi_tpc_rates_array_fixed_params *)ptr; 9849 ret = ath12k_tpc_get_rate_array(ab, tpc_stats, tpc_rates_array); 9850 break; 9851 case WMI_TAG_TPC_STATS_CTL_PWR_TABLE_EVENT: 9852 tpc_ctl_pwr = (struct wmi_tpc_ctl_pwr_fixed_params *)ptr; 9853 ret = ath12k_tpc_get_ctl_pwr_tbl(ab, tpc_stats, tpc_ctl_pwr); 9854 break; 9855 default: 9856 ath12k_warn(ab, 9857 "Received invalid tag for tpc stats in subtlvs\n"); 9858 return -EINVAL; 9859 } 9860 return ret; 9861 } 9862 9863 static int ath12k_wmi_tpc_stats_event_parser(struct ath12k_base *ab, 9864 u16 tag, u16 len, 9865 const void *ptr, void *data) 9866 { 9867 struct wmi_tpc_stats_arg *tpc_stats = (struct wmi_tpc_stats_arg *)data; 9868 int ret; 9869 9870 switch (tag) { 9871 case WMI_TAG_HALPHY_CTRL_PATH_EVENT_FIXED_PARAM: 9872 ret = 0; 9873 /* Fixed param is already processed*/ 9874 break; 9875 case WMI_TAG_ARRAY_STRUCT: 9876 /* len 0 is expected for array of struct when there 9877 * is no content of that type to pack inside that tlv 9878 */ 9879 if (len == 0) 9880 return 0; 9881 ret = ath12k_wmi_tlv_iter(ab, ptr, len, 9882 ath12k_wmi_tpc_stats_subtlv_parser, 9883 tpc_stats); 9884 break; 9885 case WMI_TAG_ARRAY_INT16: 9886 if (len == 0) 9887 return 0; 9888 ret = ath12k_wmi_tpc_stats_copy_buffer(ab, ptr, 9889 WMI_TAG_ARRAY_INT16, 9890 len, tpc_stats); 9891 break; 9892 case WMI_TAG_ARRAY_BYTE: 9893 if (len == 0) 9894 return 0; 9895 ret = ath12k_wmi_tpc_stats_copy_buffer(ab, ptr, 9896 WMI_TAG_ARRAY_BYTE, 9897 len, tpc_stats); 9898 break; 9899 default: 9900 ath12k_warn(ab, "Received invalid tag for tpc stats\n"); 9901 ret = -EINVAL; 9902 break; 9903 } 9904 return ret; 9905 } 9906 9907 void ath12k_wmi_free_tpc_stats_mem(struct ath12k *ar) 9908 { 9909 struct wmi_tpc_stats_arg *tpc_stats = ar->debug.tpc_stats; 9910 9911 lockdep_assert_held(&ar->data_lock); 9912 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "tpc stats mem free\n"); 9913 if (tpc_stats) { 9914 kfree(tpc_stats->max_reg_allowed_power.reg_pwr_array); 9915 kfree(tpc_stats->rates_array1.rate_array); 9916 kfree(tpc_stats->rates_array2.rate_array); 9917 kfree(tpc_stats->ctl_array.ctl_pwr_table); 9918 kfree(tpc_stats); 9919 ar->debug.tpc_stats = NULL; 9920 } 9921 } 9922 9923 static void ath12k_wmi_process_tpc_stats(struct ath12k_base *ab, 9924 struct sk_buff *skb) 9925 { 9926 struct ath12k_wmi_pdev_tpc_stats_event_fixed_params *fixed_param; 9927 struct wmi_tpc_stats_arg *tpc_stats; 9928 const struct wmi_tlv *tlv; 9929 void *ptr = skb->data; 9930 struct ath12k *ar; 9931 u16 tlv_tag; 9932 u32 event_count; 9933 int ret; 9934 9935 if (!skb->data) { 9936 ath12k_warn(ab, "No data present in tpc stats event\n"); 9937 return; 9938 } 9939 9940 if (skb->len < (sizeof(*fixed_param) + TLV_HDR_SIZE)) { 9941 ath12k_warn(ab, "TPC stats event size invalid\n"); 9942 return; 9943 } 9944 9945 tlv = (struct wmi_tlv *)ptr; 9946 tlv_tag = le32_get_bits(tlv->header, WMI_TLV_TAG); 9947 ptr += sizeof(*tlv); 9948 9949 if (tlv_tag != WMI_TAG_HALPHY_CTRL_PATH_EVENT_FIXED_PARAM) { 9950 ath12k_warn(ab, "TPC stats without fixed param tlv at start\n"); 9951 return; 9952 } 9953 9954 fixed_param = (struct ath12k_wmi_pdev_tpc_stats_event_fixed_params *)ptr; 9955 rcu_read_lock(); 9956 ar = ath12k_mac_get_ar_by_pdev_id(ab, le32_to_cpu(fixed_param->pdev_id) + 1); 9957 if (!ar) { 9958 ath12k_warn(ab, "Failed to get ar for tpc stats\n"); 9959 rcu_read_unlock(); 9960 return; 9961 } 9962 spin_lock_bh(&ar->data_lock); 9963 if (!ar->debug.tpc_request) { 9964 /* Event is received either without request or the 9965 * timeout, if memory is already allocated free it 9966 */ 9967 if (ar->debug.tpc_stats) { 9968 ath12k_warn(ab, "Freeing memory for tpc_stats\n"); 9969 ath12k_wmi_free_tpc_stats_mem(ar); 9970 } 9971 goto unlock; 9972 } 9973 9974 event_count = le32_to_cpu(fixed_param->event_count); 9975 if (event_count == 0) { 9976 if (ar->debug.tpc_stats) { 9977 ath12k_warn(ab, 9978 "Invalid tpc memory present\n"); 9979 goto unlock; 9980 } 9981 ar->debug.tpc_stats = 9982 kzalloc_obj(struct wmi_tpc_stats_arg, GFP_ATOMIC); 9983 if (!ar->debug.tpc_stats) { 9984 ath12k_warn(ab, 9985 "Failed to allocate memory for tpc stats\n"); 9986 goto unlock; 9987 } 9988 } 9989 9990 tpc_stats = ar->debug.tpc_stats; 9991 if (!tpc_stats) { 9992 ath12k_warn(ab, "tpc stats memory unavailable\n"); 9993 goto unlock; 9994 } 9995 9996 if (!(event_count == 0)) { 9997 if (event_count != tpc_stats->event_count + 1) { 9998 ath12k_warn(ab, 9999 "Invalid tpc event received\n"); 10000 goto unlock; 10001 } 10002 } 10003 tpc_stats->pdev_id = le32_to_cpu(fixed_param->pdev_id); 10004 tpc_stats->end_of_event = le32_to_cpu(fixed_param->end_of_event); 10005 tpc_stats->event_count = le32_to_cpu(fixed_param->event_count); 10006 ath12k_dbg(ab, ATH12K_DBG_WMI, 10007 "tpc stats event_count %d\n", 10008 tpc_stats->event_count); 10009 ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, 10010 ath12k_wmi_tpc_stats_event_parser, 10011 tpc_stats); 10012 if (ret) { 10013 ath12k_wmi_free_tpc_stats_mem(ar); 10014 ath12k_warn(ab, "failed to parse tpc_stats tlv: %d\n", ret); 10015 goto unlock; 10016 } 10017 10018 if (tpc_stats->end_of_event) 10019 complete(&ar->debug.tpc_complete); 10020 10021 unlock: 10022 spin_unlock_bh(&ar->data_lock); 10023 rcu_read_unlock(); 10024 } 10025 #else 10026 static void ath12k_wmi_process_tpc_stats(struct ath12k_base *ab, 10027 struct sk_buff *skb) 10028 { 10029 } 10030 #endif 10031 10032 static int 10033 ath12k_wmi_rssi_dbm_conv_info_evt_subtlv_parser(struct ath12k_base *ab, 10034 u16 tag, u16 len, 10035 const void *ptr, void *data) 10036 { 10037 const struct ath12k_wmi_rssi_dbm_conv_temp_info_params *temp_info; 10038 const struct ath12k_wmi_rssi_dbm_conv_info_params *param_info; 10039 struct ath12k_wmi_rssi_dbm_conv_info_arg *rssi_info = data; 10040 struct ath12k_wmi_rssi_dbm_conv_param_arg param_arg; 10041 s32 nf_hw_dbm[ATH12K_MAX_NUM_NF_HW_DBM]; 10042 u8 num_20mhz_segments; 10043 s8 min_nf, *nf_ptr; 10044 int i, j; 10045 10046 switch (tag) { 10047 case WMI_TAG_RSSI_DBM_CONVERSION_PARAMS_INFO: 10048 if (len < sizeof(*param_info)) { 10049 ath12k_warn(ab, 10050 "RSSI dbm conv subtlv 0x%x invalid len %d rcvd", 10051 tag, len); 10052 return -EINVAL; 10053 } 10054 10055 param_info = ptr; 10056 10057 param_arg.curr_bw = le32_to_cpu(param_info->curr_bw); 10058 param_arg.curr_rx_chainmask = le32_to_cpu(param_info->curr_rx_chainmask); 10059 10060 /* The received array is actually a 2D byte-array for per chain, 10061 * per 20MHz subband. Convert to 2D byte-array 10062 */ 10063 nf_ptr = ¶m_arg.nf_hw_dbm[0][0]; 10064 10065 for (i = 0; i < ATH12K_MAX_NUM_NF_HW_DBM; i++) { 10066 nf_hw_dbm[i] = a_sle32_to_cpu(param_info->nf_hw_dbm[i]); 10067 10068 for (j = 0; j < 4; j++) { 10069 *nf_ptr = (nf_hw_dbm[i] >> (j * 8)) & 0xFF; 10070 nf_ptr++; 10071 } 10072 } 10073 10074 switch (param_arg.curr_bw) { 10075 case WMI_CHAN_WIDTH_20: 10076 num_20mhz_segments = 1; 10077 break; 10078 case WMI_CHAN_WIDTH_40: 10079 num_20mhz_segments = 2; 10080 break; 10081 case WMI_CHAN_WIDTH_80: 10082 num_20mhz_segments = 4; 10083 break; 10084 case WMI_CHAN_WIDTH_160: 10085 num_20mhz_segments = 8; 10086 break; 10087 case WMI_CHAN_WIDTH_320: 10088 num_20mhz_segments = 16; 10089 break; 10090 default: 10091 ath12k_warn(ab, "Invalid current bandwidth %d in RSSI dbm event", 10092 param_arg.curr_bw); 10093 /* In error case, still consider the primary 20 MHz segment since 10094 * that would be much better than instead of dropping the whole 10095 * event 10096 */ 10097 num_20mhz_segments = 1; 10098 } 10099 10100 min_nf = ATH12K_DEFAULT_NOISE_FLOOR; 10101 10102 for (i = 0; i < ATH12K_MAX_NUM_ANTENNA; i++) { 10103 if (!(param_arg.curr_rx_chainmask & BIT(i))) 10104 continue; 10105 10106 for (j = 0; j < num_20mhz_segments; j++) { 10107 if (param_arg.nf_hw_dbm[i][j] < min_nf) 10108 min_nf = param_arg.nf_hw_dbm[i][j]; 10109 } 10110 } 10111 10112 rssi_info->min_nf_dbm = min_nf; 10113 rssi_info->nf_dbm_present = true; 10114 break; 10115 case WMI_TAG_RSSI_DBM_CONVERSION_TEMP_OFFSET_INFO: 10116 if (len < sizeof(*temp_info)) { 10117 ath12k_warn(ab, 10118 "RSSI dbm conv subtlv 0x%x invalid len %d rcvd", 10119 tag, len); 10120 return -EINVAL; 10121 } 10122 10123 temp_info = ptr; 10124 rssi_info->temp_offset = a_sle32_to_cpu(temp_info->offset); 10125 rssi_info->temp_offset_present = true; 10126 break; 10127 default: 10128 ath12k_dbg(ab, ATH12K_DBG_WMI, 10129 "Unknown subtlv 0x%x in RSSI dbm conversion event\n", tag); 10130 } 10131 10132 return 0; 10133 } 10134 10135 static int 10136 ath12k_wmi_rssi_dbm_conv_info_event_parser(struct ath12k_base *ab, 10137 u16 tag, u16 len, 10138 const void *ptr, void *data) 10139 { 10140 int ret = 0; 10141 10142 switch (tag) { 10143 case WMI_TAG_RSSI_DBM_CONVERSION_PARAMS_INFO_FIXED_PARAM: 10144 /* Fixed param is already processed*/ 10145 break; 10146 case WMI_TAG_ARRAY_STRUCT: 10147 /* len 0 is expected for array of struct when there 10148 * is no content of that type inside that tlv 10149 */ 10150 if (len == 0) 10151 return 0; 10152 10153 ret = ath12k_wmi_tlv_iter(ab, ptr, len, 10154 ath12k_wmi_rssi_dbm_conv_info_evt_subtlv_parser, 10155 data); 10156 break; 10157 default: 10158 ath12k_dbg(ab, ATH12K_DBG_WMI, 10159 "Received invalid tag 0x%x for RSSI dbm conv info event\n", 10160 tag); 10161 break; 10162 } 10163 10164 return ret; 10165 } 10166 10167 static int 10168 ath12k_wmi_rssi_dbm_conv_info_process_fixed_param(struct ath12k_base *ab, u8 *ptr, 10169 size_t len, int *pdev_id) 10170 { 10171 struct ath12k_wmi_rssi_dbm_conv_info_fixed_params *fixed_param; 10172 const struct wmi_tlv *tlv; 10173 u16 tlv_tag; 10174 10175 if (len < (sizeof(*fixed_param) + TLV_HDR_SIZE)) { 10176 ath12k_warn(ab, "invalid RSSI dbm conv event size %zu\n", len); 10177 return -EINVAL; 10178 } 10179 10180 tlv = (struct wmi_tlv *)ptr; 10181 tlv_tag = le32_get_bits(tlv->header, WMI_TLV_TAG); 10182 ptr += sizeof(*tlv); 10183 10184 if (tlv_tag != WMI_TAG_RSSI_DBM_CONVERSION_PARAMS_INFO_FIXED_PARAM) { 10185 ath12k_warn(ab, "RSSI dbm conv event received without fixed param tlv\n"); 10186 return -EINVAL; 10187 } 10188 10189 fixed_param = (struct ath12k_wmi_rssi_dbm_conv_info_fixed_params *)ptr; 10190 *pdev_id = le32_to_cpu(fixed_param->pdev_id); 10191 10192 return 0; 10193 } 10194 10195 static void 10196 ath12k_wmi_update_rssi_offsets(struct ath12k *ar, 10197 struct ath12k_wmi_rssi_dbm_conv_info_arg *rssi_info) 10198 { 10199 struct ath12k_pdev_rssi_offsets *info = &ar->rssi_info; 10200 10201 lockdep_assert_held(&ar->data_lock); 10202 10203 if (rssi_info->temp_offset_present) 10204 info->temp_offset = rssi_info->temp_offset; 10205 10206 if (rssi_info->nf_dbm_present) 10207 info->min_nf_dbm = rssi_info->min_nf_dbm; 10208 10209 info->noise_floor = info->min_nf_dbm + info->temp_offset; 10210 } 10211 10212 static void 10213 ath12k_wmi_rssi_dbm_conversion_params_info_event(struct ath12k_base *ab, 10214 struct sk_buff *skb) 10215 { 10216 struct ath12k_wmi_rssi_dbm_conv_info_arg rssi_info = {}; 10217 struct ath12k *ar; 10218 s32 noise_floor; 10219 u32 pdev_id; 10220 int ret; 10221 10222 ret = ath12k_wmi_rssi_dbm_conv_info_process_fixed_param(ab, skb->data, skb->len, 10223 &pdev_id); 10224 if (ret) { 10225 ath12k_warn(ab, "failed to parse fixed param in RSSI dbm conv event: %d\n", 10226 ret); 10227 return; 10228 } 10229 10230 rcu_read_lock(); 10231 ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id); 10232 /* If pdev is not active, ignore the event */ 10233 if (!ar) 10234 goto out_unlock; 10235 10236 ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, 10237 ath12k_wmi_rssi_dbm_conv_info_event_parser, 10238 &rssi_info); 10239 if (ret) { 10240 ath12k_warn(ab, "unable to parse RSSI dbm conversion event\n"); 10241 goto out_unlock; 10242 } 10243 10244 spin_lock_bh(&ar->data_lock); 10245 ath12k_wmi_update_rssi_offsets(ar, &rssi_info); 10246 noise_floor = ath12k_pdev_get_noise_floor(ar); 10247 spin_unlock_bh(&ar->data_lock); 10248 10249 ath12k_dbg(ab, ATH12K_DBG_WMI, 10250 "RSSI noise floor updated, new value is %d dbm\n", noise_floor); 10251 out_unlock: 10252 rcu_read_unlock(); 10253 } 10254 10255 static void ath12k_wmi_op_rx(struct ath12k_base *ab, struct sk_buff *skb) 10256 { 10257 struct wmi_cmd_hdr *cmd_hdr; 10258 enum wmi_tlv_event_id id; 10259 10260 cmd_hdr = (struct wmi_cmd_hdr *)skb->data; 10261 id = le32_get_bits(cmd_hdr->cmd_id, WMI_CMD_HDR_CMD_ID); 10262 10263 if (!skb_pull(skb, sizeof(struct wmi_cmd_hdr))) 10264 goto out; 10265 10266 switch (id) { 10267 /* Process all the WMI events here */ 10268 case WMI_SERVICE_READY_EVENTID: 10269 ath12k_service_ready_event(ab, skb); 10270 break; 10271 case WMI_SERVICE_READY_EXT_EVENTID: 10272 ath12k_service_ready_ext_event(ab, skb); 10273 break; 10274 case WMI_SERVICE_READY_EXT2_EVENTID: 10275 ath12k_service_ready_ext2_event(ab, skb); 10276 break; 10277 case WMI_REG_CHAN_LIST_CC_EXT_EVENTID: 10278 ath12k_reg_chan_list_event(ab, skb); 10279 break; 10280 case WMI_READY_EVENTID: 10281 ath12k_ready_event(ab, skb); 10282 break; 10283 case WMI_PEER_DELETE_RESP_EVENTID: 10284 ath12k_peer_delete_resp_event(ab, skb); 10285 break; 10286 case WMI_VDEV_START_RESP_EVENTID: 10287 ath12k_vdev_start_resp_event(ab, skb); 10288 break; 10289 case WMI_OFFLOAD_BCN_TX_STATUS_EVENTID: 10290 ath12k_bcn_tx_status_event(ab, skb); 10291 break; 10292 case WMI_VDEV_STOPPED_EVENTID: 10293 ath12k_vdev_stopped_event(ab, skb); 10294 break; 10295 case WMI_MGMT_RX_EVENTID: 10296 ath12k_mgmt_rx_event(ab, skb); 10297 /* mgmt_rx_event() owns the skb now! */ 10298 return; 10299 case WMI_MGMT_TX_COMPLETION_EVENTID: 10300 ath12k_mgmt_tx_compl_event(ab, skb); 10301 break; 10302 case WMI_SCAN_EVENTID: 10303 ath12k_scan_event(ab, skb); 10304 break; 10305 case WMI_PEER_STA_KICKOUT_EVENTID: 10306 ath12k_peer_sta_kickout_event(ab, skb); 10307 break; 10308 case WMI_ROAM_EVENTID: 10309 ath12k_roam_event(ab, skb); 10310 break; 10311 case WMI_CHAN_INFO_EVENTID: 10312 ath12k_chan_info_event(ab, skb); 10313 break; 10314 case WMI_PDEV_BSS_CHAN_INFO_EVENTID: 10315 ath12k_pdev_bss_chan_info_event(ab, skb); 10316 break; 10317 case WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID: 10318 ath12k_vdev_install_key_compl_event(ab, skb); 10319 break; 10320 case WMI_SERVICE_AVAILABLE_EVENTID: 10321 ath12k_service_available_event(ab, skb); 10322 break; 10323 case WMI_PEER_ASSOC_CONF_EVENTID: 10324 ath12k_peer_assoc_conf_event(ab, skb); 10325 break; 10326 case WMI_UPDATE_STATS_EVENTID: 10327 ath12k_update_stats_event(ab, skb); 10328 break; 10329 case WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID: 10330 ath12k_pdev_ctl_failsafe_check_event(ab, skb); 10331 break; 10332 case WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID: 10333 ath12k_wmi_pdev_csa_switch_count_status_event(ab, skb); 10334 break; 10335 case WMI_PDEV_TEMPERATURE_EVENTID: 10336 ath12k_wmi_pdev_temperature_event(ab, skb); 10337 break; 10338 case WMI_THERM_THROT_STATS_EVENTID: 10339 ath12k_wmi_thermal_throt_stats_event(ab, skb); 10340 break; 10341 case WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID: 10342 ath12k_wmi_pdev_dma_ring_buf_release_event(ab, skb); 10343 break; 10344 case WMI_HOST_FILS_DISCOVERY_EVENTID: 10345 ath12k_fils_discovery_event(ab, skb); 10346 break; 10347 case WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID: 10348 ath12k_probe_resp_tx_status_event(ab, skb); 10349 break; 10350 case WMI_RFKILL_STATE_CHANGE_EVENTID: 10351 ath12k_rfkill_state_change_event(ab, skb); 10352 break; 10353 case WMI_TWT_ENABLE_EVENTID: 10354 ath12k_wmi_twt_enable_event(ab, skb); 10355 break; 10356 case WMI_TWT_DISABLE_EVENTID: 10357 ath12k_wmi_twt_disable_event(ab, skb); 10358 break; 10359 case WMI_P2P_NOA_EVENTID: 10360 ath12k_wmi_p2p_noa_event(ab, skb); 10361 break; 10362 case WMI_PDEV_DFS_RADAR_DETECTION_EVENTID: 10363 ath12k_wmi_pdev_dfs_radar_detected_event(ab, skb); 10364 break; 10365 case WMI_VDEV_DELETE_RESP_EVENTID: 10366 ath12k_vdev_delete_resp_event(ab, skb); 10367 break; 10368 case WMI_DIAG_EVENTID: 10369 ath12k_wmi_diag_event(ab, skb); 10370 break; 10371 case WMI_WOW_WAKEUP_HOST_EVENTID: 10372 ath12k_wmi_event_wow_wakeup_host(ab, skb); 10373 break; 10374 case WMI_GTK_OFFLOAD_STATUS_EVENTID: 10375 ath12k_wmi_gtk_offload_status_event(ab, skb); 10376 break; 10377 case WMI_MLO_SETUP_COMPLETE_EVENTID: 10378 ath12k_wmi_event_mlo_setup_complete(ab, skb); 10379 break; 10380 case WMI_MLO_TEARDOWN_COMPLETE_EVENTID: 10381 ath12k_wmi_event_teardown_complete(ab, skb); 10382 break; 10383 case WMI_HALPHY_STATS_CTRL_PATH_EVENTID: 10384 ath12k_wmi_process_tpc_stats(ab, skb); 10385 break; 10386 case WMI_11D_NEW_COUNTRY_EVENTID: 10387 ath12k_reg_11d_new_cc_event(ab, skb); 10388 break; 10389 case WMI_PDEV_RSSI_DBM_CONVERSION_PARAMS_INFO_EVENTID: 10390 ath12k_wmi_rssi_dbm_conversion_params_info_event(ab, skb); 10391 break; 10392 case WMI_OBSS_COLOR_COLLISION_DETECTION_EVENTID: 10393 ath12k_wmi_obss_color_collision_event(ab, skb); 10394 break; 10395 case WMI_DCS_INTERFERENCE_EVENTID: 10396 ath12k_wmi_dcs_interference_event(ab, skb); 10397 break; 10398 /* add Unsupported events (rare) here */ 10399 case WMI_TBTTOFFSET_EXT_UPDATE_EVENTID: 10400 case WMI_PEER_OPER_MODE_CHANGE_EVENTID: 10401 case WMI_PDEV_DMA_RING_CFG_RSP_EVENTID: 10402 ath12k_dbg(ab, ATH12K_DBG_WMI, 10403 "ignoring unsupported event 0x%x\n", id); 10404 break; 10405 /* add Unsupported events (frequent) here */ 10406 case WMI_PDEV_GET_HALPHY_CAL_STATUS_EVENTID: 10407 case WMI_MGMT_RX_FW_CONSUMED_EVENTID: 10408 /* debug might flood hence silently ignore (no-op) */ 10409 break; 10410 case WMI_PDEV_UTF_EVENTID: 10411 if (test_bit(ATH12K_FLAG_FTM_SEGMENTED, &ab->dev_flags)) 10412 ath12k_tm_wmi_event_segmented(ab, id, skb); 10413 else 10414 ath12k_tm_wmi_event_unsegmented(ab, id, skb); 10415 break; 10416 default: 10417 ath12k_dbg(ab, ATH12K_DBG_WMI, "Unknown eventid: 0x%x\n", id); 10418 break; 10419 } 10420 10421 out: 10422 dev_kfree_skb(skb); 10423 } 10424 10425 static int ath12k_connect_pdev_htc_service(struct ath12k_base *ab, 10426 u32 pdev_idx) 10427 { 10428 int status; 10429 static const u32 svc_id[] = { 10430 ATH12K_HTC_SVC_ID_WMI_CONTROL, 10431 ATH12K_HTC_SVC_ID_WMI_CONTROL_MAC1, 10432 ATH12K_HTC_SVC_ID_WMI_CONTROL_MAC2 10433 }; 10434 struct ath12k_htc_svc_conn_req conn_req = {}; 10435 struct ath12k_htc_svc_conn_resp conn_resp = {}; 10436 10437 /* these fields are the same for all service endpoints */ 10438 conn_req.ep_ops.ep_tx_complete = ath12k_wmi_htc_tx_complete; 10439 conn_req.ep_ops.ep_rx_complete = ath12k_wmi_op_rx; 10440 conn_req.ep_ops.ep_tx_credits = ath12k_wmi_op_ep_tx_credits; 10441 10442 /* connect to control service */ 10443 conn_req.service_id = svc_id[pdev_idx]; 10444 10445 status = ath12k_htc_connect_service(&ab->htc, &conn_req, &conn_resp); 10446 if (status) { 10447 ath12k_warn(ab, "failed to connect to WMI CONTROL service status: %d\n", 10448 status); 10449 return status; 10450 } 10451 10452 ab->wmi_ab.wmi_endpoint_id[pdev_idx] = conn_resp.eid; 10453 ab->wmi_ab.wmi[pdev_idx].eid = conn_resp.eid; 10454 ab->wmi_ab.max_msg_len[pdev_idx] = conn_resp.max_msg_len; 10455 10456 return 0; 10457 } 10458 10459 static int 10460 ath12k_wmi_send_unit_test_cmd(struct ath12k *ar, 10461 const struct wmi_unit_test_arg *ut) 10462 { 10463 struct ath12k_wmi_pdev *wmi = ar->wmi; 10464 struct wmi_unit_test_cmd *cmd; 10465 int buf_len, arg_len; 10466 struct sk_buff *skb; 10467 struct wmi_tlv *tlv; 10468 __le32 *ut_cmd_args; 10469 void *ptr; 10470 int ret; 10471 int i; 10472 10473 arg_len = sizeof(*ut_cmd_args) * ut->num_args; 10474 buf_len = sizeof(*cmd) + arg_len + TLV_HDR_SIZE; 10475 10476 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, buf_len); 10477 if (!skb) 10478 return -ENOMEM; 10479 10480 ptr = skb->data; 10481 cmd = ptr; 10482 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_UNIT_TEST_CMD, 10483 sizeof(*cmd)); 10484 cmd->vdev_id = cpu_to_le32(ut->vdev_id); 10485 cmd->module_id = cpu_to_le32(ut->module_id); 10486 cmd->num_args = cpu_to_le32(ut->num_args); 10487 cmd->diag_token = cpu_to_le32(ut->diag_token); 10488 10489 ptr += sizeof(*cmd); 10490 tlv = ptr; 10491 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_UINT32, arg_len); 10492 10493 ptr += TLV_HDR_SIZE; 10494 ut_cmd_args = ptr; 10495 for (i = 0; i < ut->num_args; i++) 10496 ut_cmd_args[i] = cpu_to_le32(ut->args[i]); 10497 10498 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 10499 "WMI unit test : module %d vdev %d n_args %d token %d\n", 10500 ut->module_id, ut->vdev_id, ut->num_args, ut->diag_token); 10501 10502 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_UNIT_TEST_CMDID); 10503 10504 if (ret) { 10505 ath12k_warn(ar->ab, "failed to send WMI_UNIT_TEST CMD :%d\n", 10506 ret); 10507 dev_kfree_skb(skb); 10508 } 10509 10510 return ret; 10511 } 10512 10513 int ath12k_wmi_simulate_radar(struct ath12k *ar) 10514 { 10515 struct ath12k_link_vif *arvif; 10516 struct wmi_unit_test_arg wmi_ut = {}; 10517 bool arvif_found = false; 10518 10519 list_for_each_entry(arvif, &ar->arvifs, list) { 10520 if (arvif->is_started && arvif->ahvif->vdev_type == WMI_VDEV_TYPE_AP) { 10521 arvif_found = true; 10522 break; 10523 } 10524 } 10525 10526 if (!arvif_found) 10527 return -EINVAL; 10528 10529 wmi_ut.args[DFS_TEST_CMDID] = 0; 10530 wmi_ut.args[DFS_TEST_PDEV_ID] = ar->pdev->pdev_id; 10531 /* 10532 * Currently we could pass segment_id(b0 - b1), chirp(b2) 10533 * freq offset (b3 - b10) to unit test. For simulation 10534 * purpose this can be set to 0 which is valid. 10535 */ 10536 wmi_ut.args[DFS_TEST_RADAR_PARAM] = 0; 10537 10538 wmi_ut.vdev_id = arvif->vdev_id; 10539 wmi_ut.module_id = DFS_UNIT_TEST_MODULE; 10540 wmi_ut.num_args = DFS_MAX_TEST_ARGS; 10541 wmi_ut.diag_token = DFS_UNIT_TEST_TOKEN; 10542 10543 ath12k_dbg(ar->ab, ATH12K_DBG_REG, "Triggering Radar Simulation\n"); 10544 10545 return ath12k_wmi_send_unit_test_cmd(ar, &wmi_ut); 10546 } 10547 10548 int ath12k_wmi_send_tpc_stats_request(struct ath12k *ar, 10549 enum wmi_halphy_ctrl_path_stats_id tpc_stats_type) 10550 { 10551 struct wmi_request_halphy_ctrl_path_stats_cmd_fixed_params *cmd; 10552 struct ath12k_wmi_pdev *wmi = ar->wmi; 10553 struct sk_buff *skb; 10554 struct wmi_tlv *tlv; 10555 __le32 *pdev_id; 10556 u32 buf_len; 10557 void *ptr; 10558 int ret; 10559 10560 buf_len = sizeof(*cmd) + TLV_HDR_SIZE + sizeof(u32) + TLV_HDR_SIZE + TLV_HDR_SIZE; 10561 10562 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, buf_len); 10563 if (!skb) 10564 return -ENOMEM; 10565 cmd = (struct wmi_request_halphy_ctrl_path_stats_cmd_fixed_params *)skb->data; 10566 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_HALPHY_CTRL_PATH_CMD_FIXED_PARAM, 10567 sizeof(*cmd)); 10568 10569 cmd->stats_id_mask = cpu_to_le32(WMI_REQ_CTRL_PATH_PDEV_TX_STAT); 10570 cmd->action = cpu_to_le32(WMI_REQUEST_CTRL_PATH_STAT_GET); 10571 cmd->subid = cpu_to_le32(tpc_stats_type); 10572 10573 ptr = skb->data + sizeof(*cmd); 10574 10575 /* The below TLV arrays optionally follow this fixed param TLV structure 10576 * 1. ARRAY_UINT32 pdev_ids[] 10577 * If this array is present and non-zero length, stats should only 10578 * be provided from the pdevs identified in the array. 10579 * 2. ARRAY_UNIT32 vdev_ids[] 10580 * If this array is present and non-zero length, stats should only 10581 * be provided from the vdevs identified in the array. 10582 * 3. ath12k_wmi_mac_addr_params peer_macaddr[]; 10583 * If this array is present and non-zero length, stats should only 10584 * be provided from the peers with the MAC addresses specified 10585 * in the array 10586 */ 10587 tlv = ptr; 10588 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_UINT32, sizeof(u32)); 10589 ptr += TLV_HDR_SIZE; 10590 10591 pdev_id = ptr; 10592 *pdev_id = cpu_to_le32(ath12k_mac_get_target_pdev_id(ar)); 10593 ptr += sizeof(*pdev_id); 10594 10595 tlv = ptr; 10596 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_UINT32, 0); 10597 ptr += TLV_HDR_SIZE; 10598 10599 tlv = ptr; 10600 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_FIXED_STRUCT, 0); 10601 ptr += TLV_HDR_SIZE; 10602 10603 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_REQUEST_HALPHY_CTRL_PATH_STATS_CMDID); 10604 if (ret) { 10605 ath12k_warn(ar->ab, 10606 "failed to submit WMI_REQUEST_STATS_CTRL_PATH_CMDID\n"); 10607 dev_kfree_skb(skb); 10608 return ret; 10609 } 10610 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "WMI get TPC STATS sent on pdev %d\n", 10611 ar->pdev->pdev_id); 10612 10613 return ret; 10614 } 10615 10616 int ath12k_wmi_simulate_incumbent_signal_interference(struct ath12k *ar, 10617 u32 chan_bw_interference_bitmap) 10618 { 10619 struct wmi_unit_test_arg wmi_ut = {}; 10620 struct ath12k_link_vif *arvif; 10621 struct ath12k_vif *ahvif; 10622 bool arvif_found = false; 10623 10624 list_for_each_entry(arvif, &ar->arvifs, list) { 10625 ahvif = arvif->ahvif; 10626 if (arvif->is_started && ahvif->vdev_type == WMI_VDEV_TYPE_AP) { 10627 arvif_found = true; 10628 break; 10629 } 10630 } 10631 10632 if (!arvif_found) 10633 return -EINVAL; 10634 10635 wmi_ut.args[ATH12K_WMI_INCUMBENT_SIGNAL_TEST_INTF] = 10636 ATH12K_WMI_UNIT_TEST_INCUMBENT_SIGNAL_INTF_TYPE; 10637 wmi_ut.args[ATH12K_WMI_INCUMBENT_SIGNAL_TEST_BITMAP] = 10638 chan_bw_interference_bitmap; 10639 10640 wmi_ut.vdev_id = arvif->vdev_id; 10641 wmi_ut.module_id = ATH12K_WMI_INCUMBENT_SIGNAL_UNIT_TEST_MODULE; 10642 wmi_ut.num_args = ATH12K_WMI_INCUMBENT_SIGNAL_MAX_TEST_ARGS; 10643 wmi_ut.diag_token = ATH12K_WMI_INCUMBENT_SIGNAL_UNIT_TEST_TOKEN; 10644 10645 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 10646 "Triggering incumbent signal interference simulation, interference bitmap: 0x%x\n", 10647 chan_bw_interference_bitmap); 10648 10649 return ath12k_wmi_send_unit_test_cmd(ar, &wmi_ut); 10650 } 10651 10652 int ath12k_wmi_connect(struct ath12k_base *ab) 10653 { 10654 u32 i; 10655 u8 wmi_ep_count; 10656 10657 wmi_ep_count = ab->htc.wmi_ep_count; 10658 if (wmi_ep_count > ab->hw_params->max_radios) 10659 return -1; 10660 10661 for (i = 0; i < wmi_ep_count; i++) 10662 ath12k_connect_pdev_htc_service(ab, i); 10663 10664 return 0; 10665 } 10666 10667 static void ath12k_wmi_pdev_detach(struct ath12k_base *ab, u8 pdev_id) 10668 { 10669 if (WARN_ON(pdev_id >= MAX_RADIOS)) 10670 return; 10671 10672 /* TODO: Deinit any pdev specific wmi resource */ 10673 } 10674 10675 int ath12k_wmi_pdev_attach(struct ath12k_base *ab, 10676 u8 pdev_id) 10677 { 10678 struct ath12k_wmi_pdev *wmi_handle; 10679 10680 if (pdev_id >= ab->hw_params->max_radios) 10681 return -EINVAL; 10682 10683 wmi_handle = &ab->wmi_ab.wmi[pdev_id]; 10684 10685 wmi_handle->wmi_ab = &ab->wmi_ab; 10686 10687 ab->wmi_ab.ab = ab; 10688 /* TODO: Init remaining resource specific to pdev */ 10689 10690 return 0; 10691 } 10692 10693 int ath12k_wmi_attach(struct ath12k_base *ab) 10694 { 10695 int ret; 10696 10697 ret = ath12k_wmi_pdev_attach(ab, 0); 10698 if (ret) 10699 return ret; 10700 10701 ab->wmi_ab.ab = ab; 10702 ab->wmi_ab.preferred_hw_mode = WMI_HOST_HW_MODE_MAX; 10703 10704 /* It's overwritten when service_ext_ready is handled */ 10705 if (ab->hw_params->single_pdev_only) 10706 ab->wmi_ab.preferred_hw_mode = WMI_HOST_HW_MODE_SINGLE; 10707 10708 /* TODO: Init remaining wmi soc resources required */ 10709 init_completion(&ab->wmi_ab.service_ready); 10710 init_completion(&ab->wmi_ab.unified_ready); 10711 10712 return 0; 10713 } 10714 10715 void ath12k_wmi_detach(struct ath12k_base *ab) 10716 { 10717 int i; 10718 10719 /* TODO: Deinit wmi resource specific to SOC as required */ 10720 10721 for (i = 0; i < ab->htc.wmi_ep_count; i++) 10722 ath12k_wmi_pdev_detach(ab, i); 10723 10724 ath12k_wmi_free_dbring_caps(ab); 10725 } 10726 10727 int ath12k_wmi_hw_data_filter_cmd(struct ath12k *ar, struct wmi_hw_data_filter_arg *arg) 10728 { 10729 struct wmi_hw_data_filter_cmd *cmd; 10730 struct sk_buff *skb; 10731 int ret, len; 10732 10733 len = sizeof(*cmd); 10734 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, len); 10735 10736 if (!skb) 10737 return -ENOMEM; 10738 10739 cmd = (struct wmi_hw_data_filter_cmd *)skb->data; 10740 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_HW_DATA_FILTER_CMD, 10741 sizeof(*cmd)); 10742 cmd->vdev_id = cpu_to_le32(arg->vdev_id); 10743 cmd->enable = cpu_to_le32(arg->enable ? 1 : 0); 10744 10745 /* Set all modes in case of disable */ 10746 if (arg->enable) 10747 cmd->hw_filter_bitmap = cpu_to_le32(arg->hw_filter_bitmap); 10748 else 10749 cmd->hw_filter_bitmap = cpu_to_le32((u32)~0U); 10750 10751 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 10752 "wmi hw data filter enable %d filter_bitmap 0x%x\n", 10753 arg->enable, arg->hw_filter_bitmap); 10754 10755 ret = ath12k_wmi_cmd_send(ar->wmi, skb, WMI_HW_DATA_FILTER_CMDID); 10756 if (ret) { 10757 ath12k_warn(ar->ab, "failed to send WMI_HW_DATA_FILTER_CMDID\n"); 10758 dev_kfree_skb(skb); 10759 } 10760 10761 return ret; 10762 } 10763 10764 int ath12k_wmi_wow_host_wakeup_ind(struct ath12k *ar) 10765 { 10766 struct wmi_wow_host_wakeup_cmd *cmd; 10767 struct sk_buff *skb; 10768 size_t len; 10769 int ret; 10770 10771 len = sizeof(*cmd); 10772 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, len); 10773 if (!skb) 10774 return -ENOMEM; 10775 10776 cmd = (struct wmi_wow_host_wakeup_cmd *)skb->data; 10777 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_WOW_HOSTWAKEUP_FROM_SLEEP_CMD, 10778 sizeof(*cmd)); 10779 10780 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "wmi tlv wow host wakeup ind\n"); 10781 10782 ret = ath12k_wmi_cmd_send(ar->wmi, skb, WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID); 10783 if (ret) { 10784 ath12k_warn(ar->ab, "failed to send WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID\n"); 10785 dev_kfree_skb(skb); 10786 } 10787 10788 return ret; 10789 } 10790 10791 int ath12k_wmi_wow_enable(struct ath12k *ar) 10792 { 10793 struct wmi_wow_enable_cmd *cmd; 10794 struct sk_buff *skb; 10795 int ret, len; 10796 10797 len = sizeof(*cmd); 10798 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, len); 10799 if (!skb) 10800 return -ENOMEM; 10801 10802 cmd = (struct wmi_wow_enable_cmd *)skb->data; 10803 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_WOW_ENABLE_CMD, 10804 sizeof(*cmd)); 10805 10806 cmd->enable = cpu_to_le32(1); 10807 cmd->pause_iface_config = cpu_to_le32(WOW_IFACE_PAUSE_ENABLED); 10808 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "wmi tlv wow enable\n"); 10809 10810 ret = ath12k_wmi_cmd_send(ar->wmi, skb, WMI_WOW_ENABLE_CMDID); 10811 if (ret) { 10812 ath12k_warn(ar->ab, "failed to send WMI_WOW_ENABLE_CMDID\n"); 10813 dev_kfree_skb(skb); 10814 } 10815 10816 return ret; 10817 } 10818 10819 int ath12k_wmi_wow_add_wakeup_event(struct ath12k *ar, u32 vdev_id, 10820 enum wmi_wow_wakeup_event event, 10821 u32 enable) 10822 { 10823 struct wmi_wow_add_del_event_cmd *cmd; 10824 struct sk_buff *skb; 10825 size_t len; 10826 int ret; 10827 10828 len = sizeof(*cmd); 10829 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, len); 10830 if (!skb) 10831 return -ENOMEM; 10832 10833 cmd = (struct wmi_wow_add_del_event_cmd *)skb->data; 10834 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_WOW_ADD_DEL_EVT_CMD, 10835 sizeof(*cmd)); 10836 cmd->vdev_id = cpu_to_le32(vdev_id); 10837 cmd->is_add = cpu_to_le32(enable); 10838 cmd->event_bitmap = cpu_to_le32((1 << event)); 10839 10840 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "wmi tlv wow add wakeup event %s enable %d vdev_id %d\n", 10841 wow_wakeup_event(event), enable, vdev_id); 10842 10843 ret = ath12k_wmi_cmd_send(ar->wmi, skb, WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID); 10844 if (ret) { 10845 ath12k_warn(ar->ab, "failed to send WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID\n"); 10846 dev_kfree_skb(skb); 10847 } 10848 10849 return ret; 10850 } 10851 10852 int ath12k_wmi_wow_add_pattern(struct ath12k *ar, u32 vdev_id, u32 pattern_id, 10853 const u8 *pattern, const u8 *mask, 10854 int pattern_len, int pattern_offset) 10855 { 10856 struct wmi_wow_add_pattern_cmd *cmd; 10857 struct wmi_wow_bitmap_pattern_params *bitmap; 10858 struct wmi_tlv *tlv; 10859 struct sk_buff *skb; 10860 void *ptr; 10861 size_t len; 10862 int ret; 10863 10864 len = sizeof(*cmd) + 10865 sizeof(*tlv) + /* array struct */ 10866 sizeof(*bitmap) + /* bitmap */ 10867 sizeof(*tlv) + /* empty ipv4 sync */ 10868 sizeof(*tlv) + /* empty ipv6 sync */ 10869 sizeof(*tlv) + /* empty magic */ 10870 sizeof(*tlv) + /* empty info timeout */ 10871 sizeof(*tlv) + sizeof(u32); /* ratelimit interval */ 10872 10873 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, len); 10874 if (!skb) 10875 return -ENOMEM; 10876 10877 /* cmd */ 10878 ptr = skb->data; 10879 cmd = ptr; 10880 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_WOW_ADD_PATTERN_CMD, 10881 sizeof(*cmd)); 10882 cmd->vdev_id = cpu_to_le32(vdev_id); 10883 cmd->pattern_id = cpu_to_le32(pattern_id); 10884 cmd->pattern_type = cpu_to_le32(WOW_BITMAP_PATTERN); 10885 10886 ptr += sizeof(*cmd); 10887 10888 /* bitmap */ 10889 tlv = ptr; 10890 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, sizeof(*bitmap)); 10891 10892 ptr += sizeof(*tlv); 10893 10894 bitmap = ptr; 10895 bitmap->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_WOW_BITMAP_PATTERN_T, 10896 sizeof(*bitmap)); 10897 memcpy(bitmap->patternbuf, pattern, pattern_len); 10898 memcpy(bitmap->bitmaskbuf, mask, pattern_len); 10899 bitmap->pattern_offset = cpu_to_le32(pattern_offset); 10900 bitmap->pattern_len = cpu_to_le32(pattern_len); 10901 bitmap->bitmask_len = cpu_to_le32(pattern_len); 10902 bitmap->pattern_id = cpu_to_le32(pattern_id); 10903 10904 ptr += sizeof(*bitmap); 10905 10906 /* ipv4 sync */ 10907 tlv = ptr; 10908 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, 0); 10909 10910 ptr += sizeof(*tlv); 10911 10912 /* ipv6 sync */ 10913 tlv = ptr; 10914 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, 0); 10915 10916 ptr += sizeof(*tlv); 10917 10918 /* magic */ 10919 tlv = ptr; 10920 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, 0); 10921 10922 ptr += sizeof(*tlv); 10923 10924 /* pattern info timeout */ 10925 tlv = ptr; 10926 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_UINT32, 0); 10927 10928 ptr += sizeof(*tlv); 10929 10930 /* ratelimit interval */ 10931 tlv = ptr; 10932 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_UINT32, sizeof(u32)); 10933 10934 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "wmi tlv wow add pattern vdev_id %d pattern_id %d pattern_offset %d pattern_len %d\n", 10935 vdev_id, pattern_id, pattern_offset, pattern_len); 10936 10937 ath12k_dbg_dump(ar->ab, ATH12K_DBG_WMI, NULL, "wow pattern: ", 10938 bitmap->patternbuf, pattern_len); 10939 ath12k_dbg_dump(ar->ab, ATH12K_DBG_WMI, NULL, "wow bitmask: ", 10940 bitmap->bitmaskbuf, pattern_len); 10941 10942 ret = ath12k_wmi_cmd_send(ar->wmi, skb, WMI_WOW_ADD_WAKE_PATTERN_CMDID); 10943 if (ret) { 10944 ath12k_warn(ar->ab, "failed to send WMI_WOW_ADD_WAKE_PATTERN_CMDID\n"); 10945 dev_kfree_skb(skb); 10946 } 10947 10948 return ret; 10949 } 10950 10951 int ath12k_wmi_wow_del_pattern(struct ath12k *ar, u32 vdev_id, u32 pattern_id) 10952 { 10953 struct wmi_wow_del_pattern_cmd *cmd; 10954 struct sk_buff *skb; 10955 size_t len; 10956 int ret; 10957 10958 len = sizeof(*cmd); 10959 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, len); 10960 if (!skb) 10961 return -ENOMEM; 10962 10963 cmd = (struct wmi_wow_del_pattern_cmd *)skb->data; 10964 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_WOW_DEL_PATTERN_CMD, 10965 sizeof(*cmd)); 10966 cmd->vdev_id = cpu_to_le32(vdev_id); 10967 cmd->pattern_id = cpu_to_le32(pattern_id); 10968 cmd->pattern_type = cpu_to_le32(WOW_BITMAP_PATTERN); 10969 10970 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "wmi tlv wow del pattern vdev_id %d pattern_id %d\n", 10971 vdev_id, pattern_id); 10972 10973 ret = ath12k_wmi_cmd_send(ar->wmi, skb, WMI_WOW_DEL_WAKE_PATTERN_CMDID); 10974 if (ret) { 10975 ath12k_warn(ar->ab, "failed to send WMI_WOW_DEL_WAKE_PATTERN_CMDID\n"); 10976 dev_kfree_skb(skb); 10977 } 10978 10979 return ret; 10980 } 10981 10982 static struct sk_buff * 10983 ath12k_wmi_op_gen_config_pno_start(struct ath12k *ar, u32 vdev_id, 10984 struct wmi_pno_scan_req_arg *pno) 10985 { 10986 struct nlo_configured_params *nlo_list; 10987 size_t len, nlo_list_len, channel_list_len; 10988 struct wmi_wow_nlo_config_cmd *cmd; 10989 __le32 *channel_list; 10990 struct wmi_tlv *tlv; 10991 struct sk_buff *skb; 10992 void *ptr; 10993 u32 i; 10994 10995 len = sizeof(*cmd) + 10996 sizeof(*tlv) + 10997 /* TLV place holder for array of structures 10998 * nlo_configured_params(nlo_list) 10999 */ 11000 sizeof(*tlv); 11001 /* TLV place holder for array of uint32 channel_list */ 11002 11003 channel_list_len = sizeof(u32) * pno->a_networks[0].channel_count; 11004 len += channel_list_len; 11005 11006 nlo_list_len = sizeof(*nlo_list) * pno->uc_networks_count; 11007 len += nlo_list_len; 11008 11009 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, len); 11010 if (!skb) 11011 return ERR_PTR(-ENOMEM); 11012 11013 ptr = skb->data; 11014 cmd = ptr; 11015 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_NLO_CONFIG_CMD, sizeof(*cmd)); 11016 11017 cmd->vdev_id = cpu_to_le32(pno->vdev_id); 11018 cmd->flags = cpu_to_le32(WMI_NLO_CONFIG_START | WMI_NLO_CONFIG_SSID_HIDE_EN); 11019 11020 /* current FW does not support min-max range for dwell time */ 11021 cmd->active_dwell_time = cpu_to_le32(pno->active_max_time); 11022 cmd->passive_dwell_time = cpu_to_le32(pno->passive_max_time); 11023 11024 if (pno->do_passive_scan) 11025 cmd->flags |= cpu_to_le32(WMI_NLO_CONFIG_SCAN_PASSIVE); 11026 11027 cmd->fast_scan_period = cpu_to_le32(pno->fast_scan_period); 11028 cmd->slow_scan_period = cpu_to_le32(pno->slow_scan_period); 11029 cmd->fast_scan_max_cycles = cpu_to_le32(pno->fast_scan_max_cycles); 11030 cmd->delay_start_time = cpu_to_le32(pno->delay_start_time); 11031 11032 if (pno->enable_pno_scan_randomization) { 11033 cmd->flags |= cpu_to_le32(WMI_NLO_CONFIG_SPOOFED_MAC_IN_PROBE_REQ | 11034 WMI_NLO_CONFIG_RANDOM_SEQ_NO_IN_PROBE_REQ); 11035 ether_addr_copy(cmd->mac_addr.addr, pno->mac_addr); 11036 ether_addr_copy(cmd->mac_mask.addr, pno->mac_addr_mask); 11037 } 11038 11039 ptr += sizeof(*cmd); 11040 11041 /* nlo_configured_params(nlo_list) */ 11042 cmd->no_of_ssids = cpu_to_le32(pno->uc_networks_count); 11043 tlv = ptr; 11044 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, nlo_list_len); 11045 11046 ptr += sizeof(*tlv); 11047 nlo_list = ptr; 11048 for (i = 0; i < pno->uc_networks_count; i++) { 11049 tlv = (struct wmi_tlv *)(&nlo_list[i].tlv_header); 11050 tlv->header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_ARRAY_BYTE, 11051 sizeof(*nlo_list)); 11052 11053 nlo_list[i].ssid.valid = cpu_to_le32(1); 11054 nlo_list[i].ssid.ssid.ssid_len = 11055 cpu_to_le32(pno->a_networks[i].ssid.ssid_len); 11056 memcpy(nlo_list[i].ssid.ssid.ssid, 11057 pno->a_networks[i].ssid.ssid, 11058 le32_to_cpu(nlo_list[i].ssid.ssid.ssid_len)); 11059 11060 if (pno->a_networks[i].rssi_threshold && 11061 pno->a_networks[i].rssi_threshold > -300) { 11062 nlo_list[i].rssi_cond.valid = cpu_to_le32(1); 11063 nlo_list[i].rssi_cond.rssi = 11064 cpu_to_le32(pno->a_networks[i].rssi_threshold); 11065 } 11066 11067 nlo_list[i].bcast_nw_type.valid = cpu_to_le32(1); 11068 nlo_list[i].bcast_nw_type.bcast_nw_type = 11069 cpu_to_le32(pno->a_networks[i].bcast_nw_type); 11070 } 11071 11072 ptr += nlo_list_len; 11073 cmd->num_of_channels = cpu_to_le32(pno->a_networks[0].channel_count); 11074 tlv = ptr; 11075 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_UINT32, channel_list_len); 11076 ptr += sizeof(*tlv); 11077 channel_list = ptr; 11078 11079 for (i = 0; i < pno->a_networks[0].channel_count; i++) 11080 channel_list[i] = cpu_to_le32(pno->a_networks[0].channels[i]); 11081 11082 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "wmi tlv start pno config vdev_id %d\n", 11083 vdev_id); 11084 11085 return skb; 11086 } 11087 11088 static struct sk_buff *ath12k_wmi_op_gen_config_pno_stop(struct ath12k *ar, 11089 u32 vdev_id) 11090 { 11091 struct wmi_wow_nlo_config_cmd *cmd; 11092 struct sk_buff *skb; 11093 size_t len; 11094 11095 len = sizeof(*cmd); 11096 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, len); 11097 if (!skb) 11098 return ERR_PTR(-ENOMEM); 11099 11100 cmd = (struct wmi_wow_nlo_config_cmd *)skb->data; 11101 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_NLO_CONFIG_CMD, len); 11102 11103 cmd->vdev_id = cpu_to_le32(vdev_id); 11104 cmd->flags = cpu_to_le32(WMI_NLO_CONFIG_STOP); 11105 11106 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 11107 "wmi tlv stop pno config vdev_id %d\n", vdev_id); 11108 return skb; 11109 } 11110 11111 int ath12k_wmi_wow_config_pno(struct ath12k *ar, u32 vdev_id, 11112 struct wmi_pno_scan_req_arg *pno_scan) 11113 { 11114 struct sk_buff *skb; 11115 int ret; 11116 11117 if (pno_scan->enable) 11118 skb = ath12k_wmi_op_gen_config_pno_start(ar, vdev_id, pno_scan); 11119 else 11120 skb = ath12k_wmi_op_gen_config_pno_stop(ar, vdev_id); 11121 11122 if (IS_ERR_OR_NULL(skb)) 11123 return -ENOMEM; 11124 11125 ret = ath12k_wmi_cmd_send(ar->wmi, skb, WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID); 11126 if (ret) { 11127 ath12k_warn(ar->ab, "failed to send WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID\n"); 11128 dev_kfree_skb(skb); 11129 } 11130 11131 return ret; 11132 } 11133 11134 static void ath12k_wmi_fill_ns_offload(struct ath12k *ar, 11135 struct wmi_arp_ns_offload_arg *offload, 11136 void **ptr, 11137 bool enable, 11138 bool ext) 11139 { 11140 struct wmi_ns_offload_params *ns; 11141 struct wmi_tlv *tlv; 11142 void *buf_ptr = *ptr; 11143 u32 ns_cnt, ns_ext_tuples; 11144 int i, max_offloads; 11145 11146 ns_cnt = offload->ipv6_count; 11147 11148 tlv = buf_ptr; 11149 11150 if (ext) { 11151 ns_ext_tuples = offload->ipv6_count - WMI_MAX_NS_OFFLOADS; 11152 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, 11153 ns_ext_tuples * sizeof(*ns)); 11154 i = WMI_MAX_NS_OFFLOADS; 11155 max_offloads = offload->ipv6_count; 11156 } else { 11157 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, 11158 WMI_MAX_NS_OFFLOADS * sizeof(*ns)); 11159 i = 0; 11160 max_offloads = WMI_MAX_NS_OFFLOADS; 11161 } 11162 11163 buf_ptr += sizeof(*tlv); 11164 11165 for (; i < max_offloads; i++) { 11166 ns = buf_ptr; 11167 ns->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_NS_OFFLOAD_TUPLE, 11168 sizeof(*ns)); 11169 11170 if (enable) { 11171 if (i < ns_cnt) 11172 ns->flags |= cpu_to_le32(WMI_NSOL_FLAGS_VALID); 11173 11174 memcpy(ns->target_ipaddr[0], offload->ipv6_addr[i], 16); 11175 memcpy(ns->solicitation_ipaddr, offload->self_ipv6_addr[i], 16); 11176 11177 if (offload->ipv6_type[i]) 11178 ns->flags |= cpu_to_le32(WMI_NSOL_FLAGS_IS_IPV6_ANYCAST); 11179 11180 memcpy(ns->target_mac.addr, offload->mac_addr, ETH_ALEN); 11181 11182 if (!is_zero_ether_addr(ns->target_mac.addr)) 11183 ns->flags |= cpu_to_le32(WMI_NSOL_FLAGS_MAC_VALID); 11184 11185 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 11186 "wmi index %d ns_solicited %pI6 target %pI6", 11187 i, ns->solicitation_ipaddr, 11188 ns->target_ipaddr[0]); 11189 } 11190 11191 buf_ptr += sizeof(*ns); 11192 } 11193 11194 *ptr = buf_ptr; 11195 } 11196 11197 static void ath12k_wmi_fill_arp_offload(struct ath12k *ar, 11198 struct wmi_arp_ns_offload_arg *offload, 11199 void **ptr, 11200 bool enable) 11201 { 11202 struct wmi_arp_offload_params *arp; 11203 struct wmi_tlv *tlv; 11204 void *buf_ptr = *ptr; 11205 int i; 11206 11207 /* fill arp tuple */ 11208 tlv = buf_ptr; 11209 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, 11210 WMI_MAX_ARP_OFFLOADS * sizeof(*arp)); 11211 buf_ptr += sizeof(*tlv); 11212 11213 for (i = 0; i < WMI_MAX_ARP_OFFLOADS; i++) { 11214 arp = buf_ptr; 11215 arp->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_ARP_OFFLOAD_TUPLE, 11216 sizeof(*arp)); 11217 11218 if (enable && i < offload->ipv4_count) { 11219 /* Copy the target ip addr and flags */ 11220 arp->flags = cpu_to_le32(WMI_ARPOL_FLAGS_VALID); 11221 memcpy(arp->target_ipaddr, offload->ipv4_addr[i], 4); 11222 11223 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "wmi arp offload address %pI4", 11224 arp->target_ipaddr); 11225 } 11226 11227 buf_ptr += sizeof(*arp); 11228 } 11229 11230 *ptr = buf_ptr; 11231 } 11232 11233 int ath12k_wmi_arp_ns_offload(struct ath12k *ar, 11234 struct ath12k_link_vif *arvif, 11235 struct wmi_arp_ns_offload_arg *offload, 11236 bool enable) 11237 { 11238 struct wmi_set_arp_ns_offload_cmd *cmd; 11239 struct wmi_tlv *tlv; 11240 struct sk_buff *skb; 11241 void *buf_ptr; 11242 size_t len; 11243 u8 ns_cnt, ns_ext_tuples = 0; 11244 int ret; 11245 11246 ns_cnt = offload->ipv6_count; 11247 11248 len = sizeof(*cmd) + 11249 sizeof(*tlv) + 11250 WMI_MAX_NS_OFFLOADS * sizeof(struct wmi_ns_offload_params) + 11251 sizeof(*tlv) + 11252 WMI_MAX_ARP_OFFLOADS * sizeof(struct wmi_arp_offload_params); 11253 11254 if (ns_cnt > WMI_MAX_NS_OFFLOADS) { 11255 ns_ext_tuples = ns_cnt - WMI_MAX_NS_OFFLOADS; 11256 len += sizeof(*tlv) + 11257 ns_ext_tuples * sizeof(struct wmi_ns_offload_params); 11258 } 11259 11260 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, len); 11261 if (!skb) 11262 return -ENOMEM; 11263 11264 buf_ptr = skb->data; 11265 cmd = buf_ptr; 11266 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_SET_ARP_NS_OFFLOAD_CMD, 11267 sizeof(*cmd)); 11268 cmd->flags = cpu_to_le32(0); 11269 cmd->vdev_id = cpu_to_le32(arvif->vdev_id); 11270 cmd->num_ns_ext_tuples = cpu_to_le32(ns_ext_tuples); 11271 11272 buf_ptr += sizeof(*cmd); 11273 11274 ath12k_wmi_fill_ns_offload(ar, offload, &buf_ptr, enable, 0); 11275 ath12k_wmi_fill_arp_offload(ar, offload, &buf_ptr, enable); 11276 11277 if (ns_ext_tuples) 11278 ath12k_wmi_fill_ns_offload(ar, offload, &buf_ptr, enable, 1); 11279 11280 ret = ath12k_wmi_cmd_send(ar->wmi, skb, WMI_SET_ARP_NS_OFFLOAD_CMDID); 11281 if (ret) { 11282 ath12k_warn(ar->ab, "failed to send WMI_SET_ARP_NS_OFFLOAD_CMDID\n"); 11283 dev_kfree_skb(skb); 11284 } 11285 11286 return ret; 11287 } 11288 11289 int ath12k_wmi_gtk_rekey_offload(struct ath12k *ar, 11290 struct ath12k_link_vif *arvif, bool enable) 11291 { 11292 struct ath12k_rekey_data *rekey_data = &arvif->rekey_data; 11293 struct wmi_gtk_rekey_offload_cmd *cmd; 11294 struct sk_buff *skb; 11295 __le64 replay_ctr; 11296 int ret, len; 11297 11298 len = sizeof(*cmd); 11299 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, len); 11300 if (!skb) 11301 return -ENOMEM; 11302 11303 cmd = (struct wmi_gtk_rekey_offload_cmd *)skb->data; 11304 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_GTK_OFFLOAD_CMD, sizeof(*cmd)); 11305 cmd->vdev_id = cpu_to_le32(arvif->vdev_id); 11306 11307 if (enable) { 11308 cmd->flags = cpu_to_le32(GTK_OFFLOAD_ENABLE_OPCODE); 11309 11310 /* the length in rekey_data and cmd is equal */ 11311 memcpy(cmd->kck, rekey_data->kck, sizeof(cmd->kck)); 11312 memcpy(cmd->kek, rekey_data->kek, sizeof(cmd->kek)); 11313 11314 replay_ctr = cpu_to_le64(rekey_data->replay_ctr); 11315 memcpy(cmd->replay_ctr, &replay_ctr, 11316 sizeof(replay_ctr)); 11317 } else { 11318 cmd->flags = cpu_to_le32(GTK_OFFLOAD_DISABLE_OPCODE); 11319 } 11320 11321 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "offload gtk rekey vdev: %d %d\n", 11322 arvif->vdev_id, enable); 11323 ret = ath12k_wmi_cmd_send(ar->wmi, skb, WMI_GTK_OFFLOAD_CMDID); 11324 if (ret) { 11325 ath12k_warn(ar->ab, "failed to send WMI_GTK_OFFLOAD_CMDID offload\n"); 11326 dev_kfree_skb(skb); 11327 } 11328 11329 return ret; 11330 } 11331 11332 int ath12k_wmi_gtk_rekey_getinfo(struct ath12k *ar, 11333 struct ath12k_link_vif *arvif) 11334 { 11335 struct wmi_gtk_rekey_offload_cmd *cmd; 11336 struct sk_buff *skb; 11337 int ret, len; 11338 11339 len = sizeof(*cmd); 11340 skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, len); 11341 if (!skb) 11342 return -ENOMEM; 11343 11344 cmd = (struct wmi_gtk_rekey_offload_cmd *)skb->data; 11345 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_GTK_OFFLOAD_CMD, sizeof(*cmd)); 11346 cmd->vdev_id = cpu_to_le32(arvif->vdev_id); 11347 cmd->flags = cpu_to_le32(GTK_OFFLOAD_REQUEST_STATUS_OPCODE); 11348 11349 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "get gtk rekey vdev_id: %d\n", 11350 arvif->vdev_id); 11351 ret = ath12k_wmi_cmd_send(ar->wmi, skb, WMI_GTK_OFFLOAD_CMDID); 11352 if (ret) { 11353 ath12k_warn(ar->ab, "failed to send WMI_GTK_OFFLOAD_CMDID getinfo\n"); 11354 dev_kfree_skb(skb); 11355 } 11356 11357 return ret; 11358 } 11359 11360 int ath12k_wmi_sta_keepalive(struct ath12k *ar, 11361 const struct wmi_sta_keepalive_arg *arg) 11362 { 11363 struct wmi_sta_keepalive_arp_resp_params *arp; 11364 struct ath12k_wmi_pdev *wmi = ar->wmi; 11365 struct wmi_sta_keepalive_cmd *cmd; 11366 struct sk_buff *skb; 11367 size_t len; 11368 int ret; 11369 11370 len = sizeof(*cmd) + sizeof(*arp); 11371 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 11372 if (!skb) 11373 return -ENOMEM; 11374 11375 cmd = (struct wmi_sta_keepalive_cmd *)skb->data; 11376 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_STA_KEEPALIVE_CMD, sizeof(*cmd)); 11377 cmd->vdev_id = cpu_to_le32(arg->vdev_id); 11378 cmd->enabled = cpu_to_le32(arg->enabled); 11379 cmd->interval = cpu_to_le32(arg->interval); 11380 cmd->method = cpu_to_le32(arg->method); 11381 11382 arp = (struct wmi_sta_keepalive_arp_resp_params *)(cmd + 1); 11383 arp->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_STA_KEEPALVE_ARP_RESPONSE, 11384 sizeof(*arp)); 11385 if (arg->method == WMI_STA_KEEPALIVE_METHOD_UNSOLICITED_ARP_RESPONSE || 11386 arg->method == WMI_STA_KEEPALIVE_METHOD_GRATUITOUS_ARP_REQUEST) { 11387 arp->src_ip4_addr = cpu_to_le32(arg->src_ip4_addr); 11388 arp->dest_ip4_addr = cpu_to_le32(arg->dest_ip4_addr); 11389 ether_addr_copy(arp->dest_mac_addr.addr, arg->dest_mac_addr); 11390 } 11391 11392 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 11393 "wmi sta keepalive vdev %d enabled %d method %d interval %d\n", 11394 arg->vdev_id, arg->enabled, arg->method, arg->interval); 11395 11396 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_STA_KEEPALIVE_CMDID); 11397 if (ret) { 11398 ath12k_warn(ar->ab, "failed to send WMI_STA_KEEPALIVE_CMDID\n"); 11399 dev_kfree_skb(skb); 11400 } 11401 11402 return ret; 11403 } 11404 11405 int ath12k_wmi_mlo_setup(struct ath12k *ar, struct wmi_mlo_setup_arg *mlo_params) 11406 { 11407 struct wmi_mlo_setup_cmd *cmd; 11408 struct ath12k_wmi_pdev *wmi = ar->wmi; 11409 u32 *partner_links, num_links; 11410 int i, ret, buf_len, arg_len; 11411 struct sk_buff *skb; 11412 struct wmi_tlv *tlv; 11413 void *ptr; 11414 11415 num_links = mlo_params->num_partner_links; 11416 arg_len = num_links * sizeof(u32); 11417 buf_len = sizeof(*cmd) + TLV_HDR_SIZE + arg_len; 11418 11419 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, buf_len); 11420 if (!skb) 11421 return -ENOMEM; 11422 11423 cmd = (struct wmi_mlo_setup_cmd *)skb->data; 11424 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_MLO_SETUP_CMD, 11425 sizeof(*cmd)); 11426 cmd->mld_group_id = mlo_params->group_id; 11427 cmd->pdev_id = cpu_to_le32(ar->pdev->pdev_id); 11428 ptr = skb->data + sizeof(*cmd); 11429 11430 tlv = ptr; 11431 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_UINT32, arg_len); 11432 ptr += TLV_HDR_SIZE; 11433 11434 partner_links = ptr; 11435 for (i = 0; i < num_links; i++) 11436 partner_links[i] = mlo_params->partner_link_id[i]; 11437 11438 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_MLO_SETUP_CMDID); 11439 if (ret) { 11440 ath12k_warn(ar->ab, "failed to submit WMI_MLO_SETUP_CMDID command: %d\n", 11441 ret); 11442 dev_kfree_skb(skb); 11443 } 11444 11445 return ret; 11446 } 11447 11448 int ath12k_wmi_mlo_ready(struct ath12k *ar) 11449 { 11450 struct wmi_mlo_ready_cmd *cmd; 11451 struct ath12k_wmi_pdev *wmi = ar->wmi; 11452 struct sk_buff *skb; 11453 int ret, len; 11454 11455 len = sizeof(*cmd); 11456 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 11457 if (!skb) 11458 return -ENOMEM; 11459 11460 cmd = (struct wmi_mlo_ready_cmd *)skb->data; 11461 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_MLO_READY_CMD, 11462 sizeof(*cmd)); 11463 cmd->pdev_id = cpu_to_le32(ar->pdev->pdev_id); 11464 11465 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_MLO_READY_CMDID); 11466 if (ret) { 11467 ath12k_warn(ar->ab, "failed to submit WMI_MLO_READY_CMDID command: %d\n", 11468 ret); 11469 dev_kfree_skb(skb); 11470 } 11471 11472 return ret; 11473 } 11474 11475 int ath12k_wmi_mlo_teardown(struct ath12k *ar) 11476 { 11477 struct wmi_mlo_teardown_cmd *cmd; 11478 struct ath12k_wmi_pdev *wmi = ar->wmi; 11479 struct sk_buff *skb; 11480 int ret, len; 11481 11482 len = sizeof(*cmd); 11483 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 11484 if (!skb) 11485 return -ENOMEM; 11486 11487 cmd = (struct wmi_mlo_teardown_cmd *)skb->data; 11488 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_MLO_TEARDOWN_CMD, 11489 sizeof(*cmd)); 11490 cmd->pdev_id = cpu_to_le32(ar->pdev->pdev_id); 11491 cmd->reason_code = WMI_MLO_TEARDOWN_SSR_REASON; 11492 11493 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_MLO_TEARDOWN_CMDID); 11494 if (ret) { 11495 ath12k_warn(ar->ab, "failed to submit WMI MLO teardown command: %d\n", 11496 ret); 11497 dev_kfree_skb(skb); 11498 } 11499 11500 return ret; 11501 } 11502 11503 bool ath12k_wmi_supports_6ghz_cc_ext(struct ath12k *ar) 11504 { 11505 return test_bit(WMI_TLV_SERVICE_REG_CC_EXT_EVENT_SUPPORT, 11506 ar->ab->wmi_ab.svc_map) && ar->supports_6ghz; 11507 } 11508 11509 int ath12k_wmi_send_vdev_set_tpc_power(struct ath12k *ar, 11510 u32 vdev_id, 11511 struct ath12k_reg_tpc_power_info *param) 11512 { 11513 struct wmi_vdev_set_tpc_power_cmd *cmd; 11514 struct ath12k_wmi_pdev *wmi = ar->wmi; 11515 struct wmi_vdev_ch_power_params *ch; 11516 int i, ret, len, array_len; 11517 struct sk_buff *skb; 11518 struct wmi_tlv *tlv; 11519 u8 *ptr; 11520 11521 array_len = sizeof(*ch) * param->num_pwr_levels; 11522 len = sizeof(*cmd) + TLV_HDR_SIZE + array_len; 11523 11524 skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); 11525 if (!skb) 11526 return -ENOMEM; 11527 11528 ptr = skb->data; 11529 11530 cmd = (struct wmi_vdev_set_tpc_power_cmd *)ptr; 11531 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_SET_TPC_POWER_CMD, 11532 sizeof(*cmd)); 11533 cmd->vdev_id = cpu_to_le32(vdev_id); 11534 cmd->psd_power = cpu_to_le32(param->is_psd_power); 11535 cmd->eirp_power = cpu_to_le32(param->eirp_power); 11536 cmd->power_type_6ghz = cpu_to_le32(param->ap_power_type); 11537 11538 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, 11539 "tpc vdev id %d is psd power %d eirp power %d 6 ghz power type %d\n", 11540 vdev_id, param->is_psd_power, param->eirp_power, param->ap_power_type); 11541 11542 ptr += sizeof(*cmd); 11543 tlv = (struct wmi_tlv *)ptr; 11544 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, array_len); 11545 11546 ptr += TLV_HDR_SIZE; 11547 ch = (struct wmi_vdev_ch_power_params *)ptr; 11548 11549 for (i = 0; i < param->num_pwr_levels; i++, ch++) { 11550 ch->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_CH_POWER_INFO, 11551 sizeof(*ch)); 11552 ch->chan_cfreq = cpu_to_le32(param->chan_power_info[i].chan_cfreq); 11553 ch->tx_power = cpu_to_le32(param->chan_power_info[i].tx_power); 11554 11555 ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "tpc chan freq %d TX power %d\n", 11556 ch->chan_cfreq, ch->tx_power); 11557 } 11558 11559 ret = ath12k_wmi_cmd_send(wmi, skb, WMI_VDEV_SET_TPC_POWER_CMDID); 11560 if (ret) { 11561 ath12k_warn(ar->ab, "failed to send WMI_VDEV_SET_TPC_POWER_CMDID\n"); 11562 dev_kfree_skb(skb); 11563 } 11564 11565 return ret; 11566 } 11567 11568 static int 11569 ath12k_wmi_fill_disallowed_bmap(struct ath12k_base *ab, 11570 struct wmi_disallowed_mlo_mode_bitmap_params *dislw_bmap, 11571 struct wmi_mlo_link_set_active_arg *arg) 11572 { 11573 struct wmi_ml_disallow_mode_bmap_arg *dislw_bmap_arg; 11574 u8 i; 11575 11576 if (arg->num_disallow_mode_comb > 11577 ARRAY_SIZE(arg->disallow_bmap)) { 11578 ath12k_warn(ab, "invalid num_disallow_mode_comb: %d", 11579 arg->num_disallow_mode_comb); 11580 return -EINVAL; 11581 } 11582 11583 dislw_bmap_arg = &arg->disallow_bmap[0]; 11584 for (i = 0; i < arg->num_disallow_mode_comb; i++) { 11585 dislw_bmap->tlv_header = 11586 ath12k_wmi_tlv_cmd_hdr(0, sizeof(*dislw_bmap)); 11587 dislw_bmap->disallowed_mode_bitmap = 11588 cpu_to_le32(dislw_bmap_arg->disallowed_mode); 11589 dislw_bmap->ieee_link_id_comb = 11590 le32_encode_bits(dislw_bmap_arg->ieee_link_id[0], 11591 WMI_DISALW_MLO_MODE_BMAP_IEEE_LINK_ID_COMB_1) | 11592 le32_encode_bits(dislw_bmap_arg->ieee_link_id[1], 11593 WMI_DISALW_MLO_MODE_BMAP_IEEE_LINK_ID_COMB_2) | 11594 le32_encode_bits(dislw_bmap_arg->ieee_link_id[2], 11595 WMI_DISALW_MLO_MODE_BMAP_IEEE_LINK_ID_COMB_3) | 11596 le32_encode_bits(dislw_bmap_arg->ieee_link_id[3], 11597 WMI_DISALW_MLO_MODE_BMAP_IEEE_LINK_ID_COMB_4); 11598 11599 ath12k_dbg(ab, ATH12K_DBG_WMI, 11600 "entry %d disallowed_mode %d ieee_link_id_comb 0x%x", 11601 i, dislw_bmap_arg->disallowed_mode, 11602 dislw_bmap_arg->ieee_link_id_comb); 11603 dislw_bmap++; 11604 dislw_bmap_arg++; 11605 } 11606 11607 return 0; 11608 } 11609 11610 int ath12k_wmi_send_mlo_link_set_active_cmd(struct ath12k_base *ab, 11611 struct wmi_mlo_link_set_active_arg *arg) 11612 { 11613 struct wmi_disallowed_mlo_mode_bitmap_params *disallowed_mode_bmap; 11614 struct wmi_mlo_set_active_link_number_params *link_num_param; 11615 u32 num_link_num_param = 0, num_vdev_bitmap = 0; 11616 struct ath12k_wmi_base *wmi_ab = &ab->wmi_ab; 11617 struct wmi_mlo_link_set_active_cmd *cmd; 11618 u32 num_inactive_vdev_bitmap = 0; 11619 u32 num_disallow_mode_comb = 0; 11620 struct wmi_tlv *tlv; 11621 struct sk_buff *skb; 11622 __le32 *vdev_bitmap; 11623 void *buf_ptr; 11624 int i, ret; 11625 u32 len; 11626 11627 if (!arg->num_vdev_bitmap && !arg->num_link_entry) { 11628 ath12k_warn(ab, "Invalid num_vdev_bitmap and num_link_entry"); 11629 return -EINVAL; 11630 } 11631 11632 switch (arg->force_mode) { 11633 case WMI_MLO_LINK_FORCE_MODE_ACTIVE_LINK_NUM: 11634 case WMI_MLO_LINK_FORCE_MODE_INACTIVE_LINK_NUM: 11635 num_link_num_param = arg->num_link_entry; 11636 fallthrough; 11637 case WMI_MLO_LINK_FORCE_MODE_ACTIVE: 11638 case WMI_MLO_LINK_FORCE_MODE_INACTIVE: 11639 case WMI_MLO_LINK_FORCE_MODE_NO_FORCE: 11640 num_vdev_bitmap = arg->num_vdev_bitmap; 11641 break; 11642 case WMI_MLO_LINK_FORCE_MODE_ACTIVE_INACTIVE: 11643 num_vdev_bitmap = arg->num_vdev_bitmap; 11644 num_inactive_vdev_bitmap = arg->num_inactive_vdev_bitmap; 11645 break; 11646 default: 11647 ath12k_warn(ab, "Invalid force mode: %u", arg->force_mode); 11648 return -EINVAL; 11649 } 11650 11651 num_disallow_mode_comb = arg->num_disallow_mode_comb; 11652 len = sizeof(*cmd) + 11653 TLV_HDR_SIZE + sizeof(*link_num_param) * num_link_num_param + 11654 TLV_HDR_SIZE + sizeof(*vdev_bitmap) * num_vdev_bitmap + 11655 TLV_HDR_SIZE + TLV_HDR_SIZE + TLV_HDR_SIZE + 11656 TLV_HDR_SIZE + sizeof(*disallowed_mode_bmap) * num_disallow_mode_comb; 11657 if (arg->force_mode == WMI_MLO_LINK_FORCE_MODE_ACTIVE_INACTIVE) 11658 len += sizeof(*vdev_bitmap) * num_inactive_vdev_bitmap; 11659 11660 skb = ath12k_wmi_alloc_skb(wmi_ab, len); 11661 if (!skb) 11662 return -ENOMEM; 11663 11664 cmd = (struct wmi_mlo_link_set_active_cmd *)skb->data; 11665 cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_MLO_LINK_SET_ACTIVE_CMD, 11666 sizeof(*cmd)); 11667 cmd->force_mode = cpu_to_le32(arg->force_mode); 11668 cmd->reason = cpu_to_le32(arg->reason); 11669 ath12k_dbg(ab, ATH12K_DBG_WMI, 11670 "mode %d reason %d num_link_num_param %d num_vdev_bitmap %d inactive %d num_disallow_mode_comb %d", 11671 arg->force_mode, arg->reason, num_link_num_param, 11672 num_vdev_bitmap, num_inactive_vdev_bitmap, 11673 num_disallow_mode_comb); 11674 11675 buf_ptr = skb->data + sizeof(*cmd); 11676 tlv = buf_ptr; 11677 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, 11678 sizeof(*link_num_param) * num_link_num_param); 11679 buf_ptr += TLV_HDR_SIZE; 11680 11681 if (num_link_num_param) { 11682 cmd->ctrl_flags = 11683 le32_encode_bits(arg->ctrl_flags.dync_force_link_num ? 1 : 0, 11684 CRTL_F_DYNC_FORCE_LINK_NUM); 11685 11686 link_num_param = buf_ptr; 11687 for (i = 0; i < num_link_num_param; i++) { 11688 link_num_param->tlv_header = 11689 ath12k_wmi_tlv_cmd_hdr(0, sizeof(*link_num_param)); 11690 link_num_param->num_of_link = 11691 cpu_to_le32(arg->link_num[i].num_of_link); 11692 link_num_param->vdev_type = 11693 cpu_to_le32(arg->link_num[i].vdev_type); 11694 link_num_param->vdev_subtype = 11695 cpu_to_le32(arg->link_num[i].vdev_subtype); 11696 link_num_param->home_freq = 11697 cpu_to_le32(arg->link_num[i].home_freq); 11698 ath12k_dbg(ab, ATH12K_DBG_WMI, 11699 "entry %d num_of_link %d vdev type %d subtype %d freq %d control_flags %d", 11700 i, arg->link_num[i].num_of_link, 11701 arg->link_num[i].vdev_type, 11702 arg->link_num[i].vdev_subtype, 11703 arg->link_num[i].home_freq, 11704 __le32_to_cpu(cmd->ctrl_flags)); 11705 link_num_param++; 11706 } 11707 11708 buf_ptr += sizeof(*link_num_param) * num_link_num_param; 11709 } 11710 11711 tlv = buf_ptr; 11712 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_UINT32, 11713 sizeof(*vdev_bitmap) * num_vdev_bitmap); 11714 buf_ptr += TLV_HDR_SIZE; 11715 11716 if (num_vdev_bitmap) { 11717 vdev_bitmap = buf_ptr; 11718 for (i = 0; i < num_vdev_bitmap; i++) { 11719 vdev_bitmap[i] = cpu_to_le32(arg->vdev_bitmap[i]); 11720 ath12k_dbg(ab, ATH12K_DBG_WMI, "entry %d vdev_id_bitmap 0x%x", 11721 i, arg->vdev_bitmap[i]); 11722 } 11723 11724 buf_ptr += sizeof(*vdev_bitmap) * num_vdev_bitmap; 11725 } 11726 11727 if (arg->force_mode == WMI_MLO_LINK_FORCE_MODE_ACTIVE_INACTIVE) { 11728 tlv = buf_ptr; 11729 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_UINT32, 11730 sizeof(*vdev_bitmap) * 11731 num_inactive_vdev_bitmap); 11732 buf_ptr += TLV_HDR_SIZE; 11733 11734 if (num_inactive_vdev_bitmap) { 11735 vdev_bitmap = buf_ptr; 11736 for (i = 0; i < num_inactive_vdev_bitmap; i++) { 11737 vdev_bitmap[i] = 11738 cpu_to_le32(arg->inactive_vdev_bitmap[i]); 11739 ath12k_dbg(ab, ATH12K_DBG_WMI, 11740 "entry %d inactive_vdev_id_bitmap 0x%x", 11741 i, arg->inactive_vdev_bitmap[i]); 11742 } 11743 11744 buf_ptr += sizeof(*vdev_bitmap) * num_inactive_vdev_bitmap; 11745 } 11746 } else { 11747 /* add empty vdev bitmap2 tlv */ 11748 tlv = buf_ptr; 11749 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_UINT32, 0); 11750 buf_ptr += TLV_HDR_SIZE; 11751 } 11752 11753 /* add empty ieee_link_id_bitmap tlv */ 11754 tlv = buf_ptr; 11755 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_UINT32, 0); 11756 buf_ptr += TLV_HDR_SIZE; 11757 11758 /* add empty ieee_link_id_bitmap2 tlv */ 11759 tlv = buf_ptr; 11760 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_UINT32, 0); 11761 buf_ptr += TLV_HDR_SIZE; 11762 11763 tlv = buf_ptr; 11764 tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, 11765 sizeof(*disallowed_mode_bmap) * 11766 arg->num_disallow_mode_comb); 11767 buf_ptr += TLV_HDR_SIZE; 11768 11769 ret = ath12k_wmi_fill_disallowed_bmap(ab, buf_ptr, arg); 11770 if (ret) 11771 goto free_skb; 11772 11773 ret = ath12k_wmi_cmd_send(&wmi_ab->wmi[0], skb, WMI_MLO_LINK_SET_ACTIVE_CMDID); 11774 if (ret) { 11775 ath12k_warn(ab, 11776 "failed to send WMI_MLO_LINK_SET_ACTIVE_CMDID: %d\n", ret); 11777 goto free_skb; 11778 } 11779 11780 ath12k_dbg(ab, ATH12K_DBG_WMI, "WMI mlo link set active cmd"); 11781 11782 return ret; 11783 11784 free_skb: 11785 dev_kfree_skb(skb); 11786 return ret; 11787 } 11788 11789 int ath12k_wmi_alloc(void) 11790 { 11791 guard(mutex)(&ath12k_wmi_mutex); 11792 11793 if (!ath12k_wmi_tb) { 11794 ath12k_wmi_tb = __alloc_percpu(WMI_TAG_MAX * sizeof(void *), 11795 __alignof__(void *)); 11796 if (!ath12k_wmi_tb) 11797 return -ENOMEM; 11798 11799 refcount_set(&ath12k_wmi_refcount, 1); 11800 } else { 11801 refcount_inc(&ath12k_wmi_refcount); 11802 } 11803 11804 return 0; 11805 } 11806 11807 void ath12k_wmi_free(void) 11808 { 11809 guard(mutex)(&ath12k_wmi_mutex); 11810 11811 if (refcount_dec_and_test(&ath12k_wmi_refcount)) { 11812 free_percpu(ath12k_wmi_tb); 11813 ath12k_wmi_tb = NULL; 11814 } 11815 } 11816