1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/types.h>
8 #include <linux/bitops.h>
9 #include <linux/bitfield.h>
10
11 #include "debug.h"
12 #include "core.h"
13 #include "ce.h"
14 #include "hw.h"
15 #include "mhi.h"
16 #include "dp_rx.h"
17
18 static const guid_t wcn7850_uuid = GUID_INIT(0xf634f534, 0x6147, 0x11ec,
19 0x90, 0xd6, 0x02, 0x42,
20 0xac, 0x12, 0x00, 0x03);
21
ath12k_hw_qcn9274_mac_from_pdev_id(int pdev_idx)22 static u8 ath12k_hw_qcn9274_mac_from_pdev_id(int pdev_idx)
23 {
24 return pdev_idx;
25 }
26
ath12k_hw_mac_id_to_pdev_id_qcn9274(const struct ath12k_hw_params * hw,int mac_id)27 static int ath12k_hw_mac_id_to_pdev_id_qcn9274(const struct ath12k_hw_params *hw,
28 int mac_id)
29 {
30 return mac_id;
31 }
32
ath12k_hw_mac_id_to_srng_id_qcn9274(const struct ath12k_hw_params * hw,int mac_id)33 static int ath12k_hw_mac_id_to_srng_id_qcn9274(const struct ath12k_hw_params *hw,
34 int mac_id)
35 {
36 return 0;
37 }
38
ath12k_hw_get_ring_selector_qcn9274(struct sk_buff * skb)39 static u8 ath12k_hw_get_ring_selector_qcn9274(struct sk_buff *skb)
40 {
41 return smp_processor_id();
42 }
43
ath12k_dp_srng_is_comp_ring_qcn9274(int ring_num)44 static bool ath12k_dp_srng_is_comp_ring_qcn9274(int ring_num)
45 {
46 if (ring_num < 3 || ring_num == 4)
47 return true;
48
49 return false;
50 }
51
ath12k_hw_mac_id_to_pdev_id_wcn7850(const struct ath12k_hw_params * hw,int mac_id)52 static int ath12k_hw_mac_id_to_pdev_id_wcn7850(const struct ath12k_hw_params *hw,
53 int mac_id)
54 {
55 return 0;
56 }
57
ath12k_hw_mac_id_to_srng_id_wcn7850(const struct ath12k_hw_params * hw,int mac_id)58 static int ath12k_hw_mac_id_to_srng_id_wcn7850(const struct ath12k_hw_params *hw,
59 int mac_id)
60 {
61 return mac_id;
62 }
63
ath12k_hw_get_ring_selector_wcn7850(struct sk_buff * skb)64 static u8 ath12k_hw_get_ring_selector_wcn7850(struct sk_buff *skb)
65 {
66 return skb_get_queue_mapping(skb);
67 }
68
ath12k_dp_srng_is_comp_ring_wcn7850(int ring_num)69 static bool ath12k_dp_srng_is_comp_ring_wcn7850(int ring_num)
70 {
71 if (ring_num == 0 || ring_num == 2 || ring_num == 4)
72 return true;
73
74 return false;
75 }
76
77 static const struct ath12k_hw_ops qcn9274_ops = {
78 .get_hw_mac_from_pdev_id = ath12k_hw_qcn9274_mac_from_pdev_id,
79 .mac_id_to_pdev_id = ath12k_hw_mac_id_to_pdev_id_qcn9274,
80 .mac_id_to_srng_id = ath12k_hw_mac_id_to_srng_id_qcn9274,
81 .rxdma_ring_sel_config = ath12k_dp_rxdma_ring_sel_config_qcn9274,
82 .get_ring_selector = ath12k_hw_get_ring_selector_qcn9274,
83 .dp_srng_is_tx_comp_ring = ath12k_dp_srng_is_comp_ring_qcn9274,
84 };
85
86 static const struct ath12k_hw_ops wcn7850_ops = {
87 .get_hw_mac_from_pdev_id = ath12k_hw_qcn9274_mac_from_pdev_id,
88 .mac_id_to_pdev_id = ath12k_hw_mac_id_to_pdev_id_wcn7850,
89 .mac_id_to_srng_id = ath12k_hw_mac_id_to_srng_id_wcn7850,
90 .rxdma_ring_sel_config = ath12k_dp_rxdma_ring_sel_config_wcn7850,
91 .get_ring_selector = ath12k_hw_get_ring_selector_wcn7850,
92 .dp_srng_is_tx_comp_ring = ath12k_dp_srng_is_comp_ring_wcn7850,
93 };
94
95 #define ATH12K_TX_RING_MASK_0 0x1
96 #define ATH12K_TX_RING_MASK_1 0x2
97 #define ATH12K_TX_RING_MASK_2 0x4
98 #define ATH12K_TX_RING_MASK_3 0x8
99 #define ATH12K_TX_RING_MASK_4 0x10
100
101 #define ATH12K_RX_RING_MASK_0 0x1
102 #define ATH12K_RX_RING_MASK_1 0x2
103 #define ATH12K_RX_RING_MASK_2 0x4
104 #define ATH12K_RX_RING_MASK_3 0x8
105
106 #define ATH12K_RX_ERR_RING_MASK_0 0x1
107
108 #define ATH12K_RX_WBM_REL_RING_MASK_0 0x1
109
110 #define ATH12K_REO_STATUS_RING_MASK_0 0x1
111
112 #define ATH12K_HOST2RXDMA_RING_MASK_0 0x1
113
114 #define ATH12K_RX_MON_RING_MASK_0 0x1
115 #define ATH12K_RX_MON_RING_MASK_1 0x2
116 #define ATH12K_RX_MON_RING_MASK_2 0x4
117
118 #define ATH12K_TX_MON_RING_MASK_0 0x1
119 #define ATH12K_TX_MON_RING_MASK_1 0x2
120
121 #define ATH12K_RX_MON_STATUS_RING_MASK_0 0x1
122 #define ATH12K_RX_MON_STATUS_RING_MASK_1 0x2
123 #define ATH12K_RX_MON_STATUS_RING_MASK_2 0x4
124
125 /* Target firmware's Copy Engine configuration. */
126 static const struct ce_pipe_config ath12k_target_ce_config_wlan_qcn9274[] = {
127 /* CE0: host->target HTC control and raw streams */
128 {
129 .pipenum = __cpu_to_le32(0),
130 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
131 .nentries = __cpu_to_le32(32),
132 .nbytes_max = __cpu_to_le32(2048),
133 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
134 .reserved = __cpu_to_le32(0),
135 },
136
137 /* CE1: target->host HTT + HTC control */
138 {
139 .pipenum = __cpu_to_le32(1),
140 .pipedir = __cpu_to_le32(PIPEDIR_IN),
141 .nentries = __cpu_to_le32(32),
142 .nbytes_max = __cpu_to_le32(2048),
143 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
144 .reserved = __cpu_to_le32(0),
145 },
146
147 /* CE2: target->host WMI */
148 {
149 .pipenum = __cpu_to_le32(2),
150 .pipedir = __cpu_to_le32(PIPEDIR_IN),
151 .nentries = __cpu_to_le32(32),
152 .nbytes_max = __cpu_to_le32(2048),
153 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
154 .reserved = __cpu_to_le32(0),
155 },
156
157 /* CE3: host->target WMI (mac0) */
158 {
159 .pipenum = __cpu_to_le32(3),
160 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
161 .nentries = __cpu_to_le32(32),
162 .nbytes_max = __cpu_to_le32(2048),
163 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
164 .reserved = __cpu_to_le32(0),
165 },
166
167 /* CE4: host->target HTT */
168 {
169 .pipenum = __cpu_to_le32(4),
170 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
171 .nentries = __cpu_to_le32(256),
172 .nbytes_max = __cpu_to_le32(256),
173 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
174 .reserved = __cpu_to_le32(0),
175 },
176
177 /* CE5: target->host Pktlog */
178 {
179 .pipenum = __cpu_to_le32(5),
180 .pipedir = __cpu_to_le32(PIPEDIR_IN),
181 .nentries = __cpu_to_le32(32),
182 .nbytes_max = __cpu_to_le32(2048),
183 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
184 .reserved = __cpu_to_le32(0),
185 },
186
187 /* CE6: Reserved for target autonomous hif_memcpy */
188 {
189 .pipenum = __cpu_to_le32(6),
190 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
191 .nentries = __cpu_to_le32(32),
192 .nbytes_max = __cpu_to_le32(16384),
193 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
194 .reserved = __cpu_to_le32(0),
195 },
196
197 /* CE7: host->target WMI (mac1) */
198 {
199 .pipenum = __cpu_to_le32(7),
200 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
201 .nentries = __cpu_to_le32(32),
202 .nbytes_max = __cpu_to_le32(2048),
203 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
204 .reserved = __cpu_to_le32(0),
205 },
206
207 /* CE8: Reserved for target autonomous hif_memcpy */
208 {
209 .pipenum = __cpu_to_le32(8),
210 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
211 .nentries = __cpu_to_le32(32),
212 .nbytes_max = __cpu_to_le32(16384),
213 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
214 .reserved = __cpu_to_le32(0),
215 },
216
217 /* CE9, 10 and 11: Reserved for MHI */
218
219 /* CE12: Target CV prefetch */
220 {
221 .pipenum = __cpu_to_le32(12),
222 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
223 .nentries = __cpu_to_le32(32),
224 .nbytes_max = __cpu_to_le32(2048),
225 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
226 .reserved = __cpu_to_le32(0),
227 },
228
229 /* CE13: Target CV prefetch */
230 {
231 .pipenum = __cpu_to_le32(13),
232 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
233 .nentries = __cpu_to_le32(32),
234 .nbytes_max = __cpu_to_le32(2048),
235 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
236 .reserved = __cpu_to_le32(0),
237 },
238
239 /* CE14: WMI logging/CFR/Spectral/Radar */
240 {
241 .pipenum = __cpu_to_le32(14),
242 .pipedir = __cpu_to_le32(PIPEDIR_IN),
243 .nentries = __cpu_to_le32(32),
244 .nbytes_max = __cpu_to_le32(2048),
245 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
246 .reserved = __cpu_to_le32(0),
247 },
248
249 /* CE15: Reserved */
250 };
251
252 /* Target firmware's Copy Engine configuration. */
253 static const struct ce_pipe_config ath12k_target_ce_config_wlan_wcn7850[] = {
254 /* CE0: host->target HTC control and raw streams */
255 {
256 .pipenum = __cpu_to_le32(0),
257 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
258 .nentries = __cpu_to_le32(32),
259 .nbytes_max = __cpu_to_le32(2048),
260 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
261 .reserved = __cpu_to_le32(0),
262 },
263
264 /* CE1: target->host HTT + HTC control */
265 {
266 .pipenum = __cpu_to_le32(1),
267 .pipedir = __cpu_to_le32(PIPEDIR_IN),
268 .nentries = __cpu_to_le32(32),
269 .nbytes_max = __cpu_to_le32(2048),
270 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
271 .reserved = __cpu_to_le32(0),
272 },
273
274 /* CE2: target->host WMI */
275 {
276 .pipenum = __cpu_to_le32(2),
277 .pipedir = __cpu_to_le32(PIPEDIR_IN),
278 .nentries = __cpu_to_le32(32),
279 .nbytes_max = __cpu_to_le32(2048),
280 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
281 .reserved = __cpu_to_le32(0),
282 },
283
284 /* CE3: host->target WMI */
285 {
286 .pipenum = __cpu_to_le32(3),
287 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
288 .nentries = __cpu_to_le32(32),
289 .nbytes_max = __cpu_to_le32(2048),
290 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
291 .reserved = __cpu_to_le32(0),
292 },
293
294 /* CE4: host->target HTT */
295 {
296 .pipenum = __cpu_to_le32(4),
297 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
298 .nentries = __cpu_to_le32(256),
299 .nbytes_max = __cpu_to_le32(256),
300 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
301 .reserved = __cpu_to_le32(0),
302 },
303
304 /* CE5: target->host Pktlog */
305 {
306 .pipenum = __cpu_to_le32(5),
307 .pipedir = __cpu_to_le32(PIPEDIR_IN),
308 .nentries = __cpu_to_le32(32),
309 .nbytes_max = __cpu_to_le32(2048),
310 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
311 .reserved = __cpu_to_le32(0),
312 },
313
314 /* CE6: Reserved for target autonomous hif_memcpy */
315 {
316 .pipenum = __cpu_to_le32(6),
317 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
318 .nentries = __cpu_to_le32(32),
319 .nbytes_max = __cpu_to_le32(16384),
320 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
321 .reserved = __cpu_to_le32(0),
322 },
323
324 /* CE7 used only by Host */
325 {
326 .pipenum = __cpu_to_le32(7),
327 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H),
328 .nentries = __cpu_to_le32(0),
329 .nbytes_max = __cpu_to_le32(0),
330 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
331 .reserved = __cpu_to_le32(0),
332 },
333
334 /* CE8 target->host used only by IPA */
335 {
336 .pipenum = __cpu_to_le32(8),
337 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
338 .nentries = __cpu_to_le32(32),
339 .nbytes_max = __cpu_to_le32(16384),
340 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
341 .reserved = __cpu_to_le32(0),
342 },
343 /* CE 9, 10, 11 are used by MHI driver */
344 };
345
346 /* Map from service/endpoint to Copy Engine.
347 * This table is derived from the CE_PCI TABLE, above.
348 * It is passed to the Target at startup for use by firmware.
349 */
350 static const struct service_to_pipe ath12k_target_service_to_ce_map_wlan_qcn9274[] = {
351 {
352 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO),
353 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
354 __cpu_to_le32(3),
355 },
356 {
357 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO),
358 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
359 __cpu_to_le32(2),
360 },
361 {
362 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK),
363 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
364 __cpu_to_le32(3),
365 },
366 {
367 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK),
368 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
369 __cpu_to_le32(2),
370 },
371 {
372 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE),
373 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
374 __cpu_to_le32(3),
375 },
376 {
377 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE),
378 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
379 __cpu_to_le32(2),
380 },
381 {
382 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI),
383 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
384 __cpu_to_le32(3),
385 },
386 {
387 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI),
388 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
389 __cpu_to_le32(2),
390 },
391 {
392 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL),
393 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
394 __cpu_to_le32(3),
395 },
396 {
397 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL),
398 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
399 __cpu_to_le32(2),
400 },
401 {
402 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL),
403 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
404 __cpu_to_le32(0),
405 },
406 {
407 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL),
408 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
409 __cpu_to_le32(1),
410 },
411 {
412 __cpu_to_le32(ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS),
413 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
414 __cpu_to_le32(0),
415 },
416 {
417 __cpu_to_le32(ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS),
418 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
419 __cpu_to_le32(1),
420 },
421 {
422 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG),
423 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
424 __cpu_to_le32(4),
425 },
426 {
427 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG),
428 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
429 __cpu_to_le32(1),
430 },
431 {
432 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_MAC1),
433 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
434 __cpu_to_le32(7),
435 },
436 {
437 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_MAC1),
438 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
439 __cpu_to_le32(2),
440 },
441 {
442 __cpu_to_le32(ATH12K_HTC_SVC_ID_PKT_LOG),
443 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
444 __cpu_to_le32(5),
445 },
446 {
447 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_DIAG),
448 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
449 __cpu_to_le32(14),
450 },
451
452 /* (Additions here) */
453
454 { /* must be last */
455 __cpu_to_le32(0),
456 __cpu_to_le32(0),
457 __cpu_to_le32(0),
458 },
459 };
460
461 static const struct service_to_pipe ath12k_target_service_to_ce_map_wlan_wcn7850[] = {
462 {
463 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO),
464 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
465 __cpu_to_le32(3),
466 },
467 {
468 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO),
469 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
470 __cpu_to_le32(2),
471 },
472 {
473 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK),
474 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
475 __cpu_to_le32(3),
476 },
477 {
478 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK),
479 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
480 __cpu_to_le32(2),
481 },
482 {
483 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE),
484 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
485 __cpu_to_le32(3),
486 },
487 {
488 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE),
489 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
490 __cpu_to_le32(2),
491 },
492 {
493 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI),
494 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
495 __cpu_to_le32(3),
496 },
497 {
498 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI),
499 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
500 __cpu_to_le32(2),
501 },
502 {
503 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL),
504 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
505 __cpu_to_le32(3),
506 },
507 {
508 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL),
509 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
510 __cpu_to_le32(2),
511 },
512 {
513 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL),
514 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
515 __cpu_to_le32(0),
516 },
517 {
518 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL),
519 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
520 __cpu_to_le32(2),
521 },
522 {
523 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG),
524 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
525 __cpu_to_le32(4),
526 },
527 {
528 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG),
529 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
530 __cpu_to_le32(1),
531 },
532
533 /* (Additions here) */
534
535 { /* must be last */
536 __cpu_to_le32(0),
537 __cpu_to_le32(0),
538 __cpu_to_le32(0),
539 },
540 };
541
542 static const struct ce_pipe_config ath12k_target_ce_config_wlan_ipq5332[] = {
543 /* host->target HTC control and raw streams */
544 {
545 .pipenum = __cpu_to_le32(0),
546 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
547 .nentries = __cpu_to_le32(32),
548 .nbytes_max = __cpu_to_le32(2048),
549 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
550 .reserved = __cpu_to_le32(0),
551 },
552 /* target->host HTT */
553 {
554 .pipenum = __cpu_to_le32(1),
555 .pipedir = __cpu_to_le32(PIPEDIR_IN),
556 .nentries = __cpu_to_le32(32),
557 .nbytes_max = __cpu_to_le32(2048),
558 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
559 .reserved = __cpu_to_le32(0),
560 },
561 /* target->host WMI + HTC control */
562 {
563 .pipenum = __cpu_to_le32(2),
564 .pipedir = __cpu_to_le32(PIPEDIR_IN),
565 .nentries = __cpu_to_le32(32),
566 .nbytes_max = __cpu_to_le32(2048),
567 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
568 .reserved = __cpu_to_le32(0),
569 },
570 /* host->target WMI */
571 {
572 .pipenum = __cpu_to_le32(3),
573 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
574 .nentries = __cpu_to_le32(32),
575 .nbytes_max = __cpu_to_le32(2048),
576 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
577 .reserved = __cpu_to_le32(0),
578 },
579 /* host->target HTT */
580 {
581 .pipenum = __cpu_to_le32(4),
582 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
583 .nentries = __cpu_to_le32(256),
584 .nbytes_max = __cpu_to_le32(256),
585 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
586 .reserved = __cpu_to_le32(0),
587 },
588 /* Target -> host PKTLOG */
589 {
590 .pipenum = __cpu_to_le32(5),
591 .pipedir = __cpu_to_le32(PIPEDIR_IN),
592 .nentries = __cpu_to_le32(32),
593 .nbytes_max = __cpu_to_le32(2048),
594 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
595 .reserved = __cpu_to_le32(0),
596 },
597 /* Reserved for target autonomous HIF_memcpy */
598 {
599 .pipenum = __cpu_to_le32(6),
600 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
601 .nentries = __cpu_to_le32(32),
602 .nbytes_max = __cpu_to_le32(16384),
603 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
604 .reserved = __cpu_to_le32(0),
605 },
606 /* CE7 Reserved for CV Prefetch */
607 {
608 .pipenum = __cpu_to_le32(7),
609 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
610 .nentries = __cpu_to_le32(32),
611 .nbytes_max = __cpu_to_le32(2048),
612 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
613 .reserved = __cpu_to_le32(0),
614 },
615 /* CE8 Reserved for target generic HIF memcpy */
616 {
617 .pipenum = __cpu_to_le32(8),
618 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
619 .nentries = __cpu_to_le32(32),
620 .nbytes_max = __cpu_to_le32(16384),
621 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
622 .reserved = __cpu_to_le32(0),
623 },
624 /* CE9 WMI logging/CFR/Spectral/Radar/ */
625 {
626 .pipenum = __cpu_to_le32(9),
627 .pipedir = __cpu_to_le32(PIPEDIR_IN),
628 .nentries = __cpu_to_le32(32),
629 .nbytes_max = __cpu_to_le32(2048),
630 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
631 .reserved = __cpu_to_le32(0),
632 },
633 /* Unused TBD */
634 {
635 .pipenum = __cpu_to_le32(10),
636 .pipedir = __cpu_to_le32(PIPEDIR_NONE),
637 .nentries = __cpu_to_le32(0),
638 .nbytes_max = __cpu_to_le32(0),
639 .flags = __cpu_to_le32(0),
640 .reserved = __cpu_to_le32(0),
641 },
642 /* Unused TBD */
643 {
644 .pipenum = __cpu_to_le32(11),
645 .pipedir = __cpu_to_le32(PIPEDIR_NONE),
646 .nentries = __cpu_to_le32(0),
647 .nbytes_max = __cpu_to_le32(0),
648 .flags = __cpu_to_le32(0),
649 .reserved = __cpu_to_le32(0),
650 },
651 };
652
653 static const struct service_to_pipe ath12k_target_service_to_ce_map_wlan_ipq5332[] = {
654 {
655 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO),
656 __cpu_to_le32(PIPEDIR_OUT),
657 __cpu_to_le32(3),
658 },
659 {
660 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO),
661 __cpu_to_le32(PIPEDIR_IN),
662 __cpu_to_le32(2),
663 },
664 {
665 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK),
666 __cpu_to_le32(PIPEDIR_OUT),
667 __cpu_to_le32(3),
668 },
669 {
670 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK),
671 __cpu_to_le32(PIPEDIR_IN),
672 __cpu_to_le32(2),
673 },
674 {
675 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE),
676 __cpu_to_le32(PIPEDIR_OUT),
677 __cpu_to_le32(3),
678 },
679 {
680 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE),
681 __cpu_to_le32(PIPEDIR_IN),
682 __cpu_to_le32(2),
683 },
684 {
685 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI),
686 __cpu_to_le32(PIPEDIR_OUT),
687 __cpu_to_le32(3),
688 },
689 {
690 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI),
691 __cpu_to_le32(PIPEDIR_IN),
692 __cpu_to_le32(2),
693 },
694 {
695 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL),
696 __cpu_to_le32(PIPEDIR_OUT),
697 __cpu_to_le32(3),
698 },
699 {
700 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL),
701 __cpu_to_le32(PIPEDIR_IN),
702 __cpu_to_le32(2),
703 },
704 {
705 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL),
706 __cpu_to_le32(PIPEDIR_OUT),
707 __cpu_to_le32(0),
708 },
709 {
710 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL),
711 __cpu_to_le32(PIPEDIR_IN),
712 __cpu_to_le32(1),
713 },
714 {
715 __cpu_to_le32(ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS),
716 __cpu_to_le32(PIPEDIR_OUT),
717 __cpu_to_le32(0),
718 },
719 {
720 __cpu_to_le32(ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS),
721 __cpu_to_le32(PIPEDIR_IN),
722 __cpu_to_le32(1),
723 },
724 {
725 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG),
726 __cpu_to_le32(PIPEDIR_OUT),
727 __cpu_to_le32(4),
728 },
729 {
730 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG),
731 __cpu_to_le32(PIPEDIR_IN),
732 __cpu_to_le32(1),
733 },
734 {
735 __cpu_to_le32(ATH12K_HTC_SVC_ID_PKT_LOG),
736 __cpu_to_le32(PIPEDIR_IN),
737 __cpu_to_le32(5),
738 },
739 {
740 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_DIAG),
741 __cpu_to_le32(PIPEDIR_IN),
742 __cpu_to_le32(9),
743 },
744 /* (Additions here) */
745
746 { /* must be last */
747 __cpu_to_le32(0),
748 __cpu_to_le32(0),
749 __cpu_to_le32(0),
750 },
751 };
752
753 static const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_qcn9274 = {
754 .tx = {
755 ATH12K_TX_RING_MASK_0,
756 ATH12K_TX_RING_MASK_1,
757 ATH12K_TX_RING_MASK_2,
758 ATH12K_TX_RING_MASK_3,
759 },
760 .rx_mon_dest = {
761 0, 0, 0, 0,
762 0, 0, 0, 0,
763 ATH12K_RX_MON_RING_MASK_0,
764 ATH12K_RX_MON_RING_MASK_1,
765 ATH12K_RX_MON_RING_MASK_2,
766 },
767 .rx = {
768 0, 0, 0, 0,
769 ATH12K_RX_RING_MASK_0,
770 ATH12K_RX_RING_MASK_1,
771 ATH12K_RX_RING_MASK_2,
772 ATH12K_RX_RING_MASK_3,
773 },
774 .rx_err = {
775 0, 0, 0,
776 ATH12K_RX_ERR_RING_MASK_0,
777 },
778 .rx_wbm_rel = {
779 0, 0, 0,
780 ATH12K_RX_WBM_REL_RING_MASK_0,
781 },
782 .reo_status = {
783 0, 0, 0,
784 ATH12K_REO_STATUS_RING_MASK_0,
785 },
786 .host2rxdma = {
787 0, 0, 0,
788 ATH12K_HOST2RXDMA_RING_MASK_0,
789 },
790 .tx_mon_dest = {
791 0, 0, 0,
792 },
793 };
794
795 static const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_ipq5332 = {
796 .tx = {
797 ATH12K_TX_RING_MASK_0,
798 ATH12K_TX_RING_MASK_1,
799 ATH12K_TX_RING_MASK_2,
800 ATH12K_TX_RING_MASK_3,
801 },
802 .rx_mon_dest = {
803 0, 0, 0, 0, 0, 0, 0, 0,
804 ATH12K_RX_MON_RING_MASK_0,
805 },
806 .rx = {
807 0, 0, 0, 0,
808 ATH12K_RX_RING_MASK_0,
809 ATH12K_RX_RING_MASK_1,
810 ATH12K_RX_RING_MASK_2,
811 ATH12K_RX_RING_MASK_3,
812 },
813 .rx_err = {
814 0, 0, 0,
815 ATH12K_RX_ERR_RING_MASK_0,
816 },
817 .rx_wbm_rel = {
818 0, 0, 0,
819 ATH12K_RX_WBM_REL_RING_MASK_0,
820 },
821 .reo_status = {
822 0, 0, 0,
823 ATH12K_REO_STATUS_RING_MASK_0,
824 },
825 .host2rxdma = {
826 0, 0, 0,
827 ATH12K_HOST2RXDMA_RING_MASK_0,
828 },
829 .tx_mon_dest = {
830 ATH12K_TX_MON_RING_MASK_0,
831 ATH12K_TX_MON_RING_MASK_1,
832 },
833 };
834
835 static const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_wcn7850 = {
836 .tx = {
837 ATH12K_TX_RING_MASK_0,
838 ATH12K_TX_RING_MASK_1,
839 ATH12K_TX_RING_MASK_2,
840 },
841 .rx_mon_dest = {
842 },
843 .rx_mon_status = {
844 0, 0, 0, 0,
845 ATH12K_RX_MON_STATUS_RING_MASK_0,
846 ATH12K_RX_MON_STATUS_RING_MASK_1,
847 ATH12K_RX_MON_STATUS_RING_MASK_2,
848 },
849 .rx = {
850 0, 0, 0,
851 ATH12K_RX_RING_MASK_0,
852 ATH12K_RX_RING_MASK_1,
853 ATH12K_RX_RING_MASK_2,
854 ATH12K_RX_RING_MASK_3,
855 },
856 .rx_err = {
857 ATH12K_RX_ERR_RING_MASK_0,
858 },
859 .rx_wbm_rel = {
860 ATH12K_RX_WBM_REL_RING_MASK_0,
861 },
862 .reo_status = {
863 ATH12K_REO_STATUS_RING_MASK_0,
864 },
865 .host2rxdma = {
866 },
867 .tx_mon_dest = {
868 },
869 };
870
871 static const struct ath12k_hw_regs qcn9274_v1_regs = {
872 /* SW2TCL(x) R0 ring configuration address */
873 .hal_tcl1_ring_id = 0x00000908,
874 .hal_tcl1_ring_misc = 0x00000910,
875 .hal_tcl1_ring_tp_addr_lsb = 0x0000091c,
876 .hal_tcl1_ring_tp_addr_msb = 0x00000920,
877 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930,
878 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934,
879 .hal_tcl1_ring_msi1_base_lsb = 0x00000948,
880 .hal_tcl1_ring_msi1_base_msb = 0x0000094c,
881 .hal_tcl1_ring_msi1_data = 0x00000950,
882 .hal_tcl_ring_base_lsb = 0x00000b58,
883 .hal_tcl1_ring_base_lsb = 0x00000900,
884 .hal_tcl1_ring_base_msb = 0x00000904,
885 .hal_tcl2_ring_base_lsb = 0x00000978,
886
887 /* TCL STATUS ring address */
888 .hal_tcl_status_ring_base_lsb = 0x00000d38,
889
890 .hal_wbm_idle_ring_base_lsb = 0x00000d0c,
891 .hal_wbm_idle_ring_misc_addr = 0x00000d1c,
892 .hal_wbm_r0_idle_list_cntl_addr = 0x00000210,
893 .hal_wbm_r0_idle_list_size_addr = 0x00000214,
894 .hal_wbm_scattered_ring_base_lsb = 0x00000220,
895 .hal_wbm_scattered_ring_base_msb = 0x00000224,
896 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000230,
897 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000234,
898 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000240,
899 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000244,
900 .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000024c,
901
902 .hal_wbm_sw_release_ring_base_lsb = 0x0000034c,
903 .hal_wbm_sw1_release_ring_base_lsb = 0x000003c4,
904 .hal_wbm0_release_ring_base_lsb = 0x00000dd8,
905 .hal_wbm1_release_ring_base_lsb = 0x00000e50,
906
907 /* PCIe base address */
908 .pcie_qserdes_sysclk_en_sel = 0x01e0c0a8,
909 .pcie_pcs_osc_dtct_config_base = 0x01e0d45c,
910
911 /* PPE release ring address */
912 .hal_ppe_rel_ring_base = 0x0000043c,
913
914 /* REO DEST ring address */
915 .hal_reo2_ring_base = 0x0000055c,
916 .hal_reo1_misc_ctrl_addr = 0x00000b7c,
917 .hal_reo1_sw_cookie_cfg0 = 0x00000050,
918 .hal_reo1_sw_cookie_cfg1 = 0x00000054,
919 .hal_reo1_qdesc_lut_base0 = 0x00000058,
920 .hal_reo1_qdesc_lut_base1 = 0x0000005c,
921 .hal_reo1_ring_base_lsb = 0x000004e4,
922 .hal_reo1_ring_base_msb = 0x000004e8,
923 .hal_reo1_ring_id = 0x000004ec,
924 .hal_reo1_ring_misc = 0x000004f4,
925 .hal_reo1_ring_hp_addr_lsb = 0x000004f8,
926 .hal_reo1_ring_hp_addr_msb = 0x000004fc,
927 .hal_reo1_ring_producer_int_setup = 0x00000508,
928 .hal_reo1_ring_msi1_base_lsb = 0x0000052C,
929 .hal_reo1_ring_msi1_base_msb = 0x00000530,
930 .hal_reo1_ring_msi1_data = 0x00000534,
931 .hal_reo1_aging_thres_ix0 = 0x00000b08,
932 .hal_reo1_aging_thres_ix1 = 0x00000b0c,
933 .hal_reo1_aging_thres_ix2 = 0x00000b10,
934 .hal_reo1_aging_thres_ix3 = 0x00000b14,
935
936 /* REO Exception ring address */
937 .hal_reo2_sw0_ring_base = 0x000008a4,
938
939 /* REO Reinject ring address */
940 .hal_sw2reo_ring_base = 0x00000304,
941 .hal_sw2reo1_ring_base = 0x0000037c,
942
943 /* REO cmd ring address */
944 .hal_reo_cmd_ring_base = 0x0000028c,
945
946 /* REO status ring address */
947 .hal_reo_status_ring_base = 0x00000a84,
948
949 /* CE base address */
950 .hal_umac_ce0_src_reg_base = 0x01b80000,
951 .hal_umac_ce0_dest_reg_base = 0x01b81000,
952 .hal_umac_ce1_src_reg_base = 0x01b82000,
953 .hal_umac_ce1_dest_reg_base = 0x01b83000,
954
955 .gcc_gcc_pcie_hot_rst = 0x1e38338,
956 };
957
958 static const struct ath12k_hw_regs qcn9274_v2_regs = {
959 /* SW2TCL(x) R0 ring configuration address */
960 .hal_tcl1_ring_id = 0x00000908,
961 .hal_tcl1_ring_misc = 0x00000910,
962 .hal_tcl1_ring_tp_addr_lsb = 0x0000091c,
963 .hal_tcl1_ring_tp_addr_msb = 0x00000920,
964 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930,
965 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934,
966 .hal_tcl1_ring_msi1_base_lsb = 0x00000948,
967 .hal_tcl1_ring_msi1_base_msb = 0x0000094c,
968 .hal_tcl1_ring_msi1_data = 0x00000950,
969 .hal_tcl_ring_base_lsb = 0x00000b58,
970 .hal_tcl1_ring_base_lsb = 0x00000900,
971 .hal_tcl1_ring_base_msb = 0x00000904,
972 .hal_tcl2_ring_base_lsb = 0x00000978,
973
974 /* TCL STATUS ring address */
975 .hal_tcl_status_ring_base_lsb = 0x00000d38,
976
977 /* WBM idle link ring address */
978 .hal_wbm_idle_ring_base_lsb = 0x00000d3c,
979 .hal_wbm_idle_ring_misc_addr = 0x00000d4c,
980 .hal_wbm_r0_idle_list_cntl_addr = 0x00000240,
981 .hal_wbm_r0_idle_list_size_addr = 0x00000244,
982 .hal_wbm_scattered_ring_base_lsb = 0x00000250,
983 .hal_wbm_scattered_ring_base_msb = 0x00000254,
984 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000260,
985 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000264,
986 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000270,
987 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000274,
988 .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000027c,
989
990 /* SW2WBM release ring address */
991 .hal_wbm_sw_release_ring_base_lsb = 0x0000037c,
992 .hal_wbm_sw1_release_ring_base_lsb = 0x000003f4,
993
994 /* WBM2SW release ring address */
995 .hal_wbm0_release_ring_base_lsb = 0x00000e08,
996 .hal_wbm1_release_ring_base_lsb = 0x00000e80,
997
998 /* PCIe base address */
999 .pcie_qserdes_sysclk_en_sel = 0x01e0c0a8,
1000 .pcie_pcs_osc_dtct_config_base = 0x01e0d45c,
1001
1002 /* PPE release ring address */
1003 .hal_ppe_rel_ring_base = 0x0000046c,
1004
1005 /* REO DEST ring address */
1006 .hal_reo2_ring_base = 0x00000578,
1007 .hal_reo1_misc_ctrl_addr = 0x00000b9c,
1008 .hal_reo1_sw_cookie_cfg0 = 0x0000006c,
1009 .hal_reo1_sw_cookie_cfg1 = 0x00000070,
1010 .hal_reo1_qdesc_lut_base0 = 0x00000074,
1011 .hal_reo1_qdesc_lut_base1 = 0x00000078,
1012 .hal_reo1_qdesc_addr = 0x0000007c,
1013 .hal_reo1_qdesc_max_peerid = 0x00000088,
1014 .hal_reo1_ring_base_lsb = 0x00000500,
1015 .hal_reo1_ring_base_msb = 0x00000504,
1016 .hal_reo1_ring_id = 0x00000508,
1017 .hal_reo1_ring_misc = 0x00000510,
1018 .hal_reo1_ring_hp_addr_lsb = 0x00000514,
1019 .hal_reo1_ring_hp_addr_msb = 0x00000518,
1020 .hal_reo1_ring_producer_int_setup = 0x00000524,
1021 .hal_reo1_ring_msi1_base_lsb = 0x00000548,
1022 .hal_reo1_ring_msi1_base_msb = 0x0000054C,
1023 .hal_reo1_ring_msi1_data = 0x00000550,
1024 .hal_reo1_aging_thres_ix0 = 0x00000B28,
1025 .hal_reo1_aging_thres_ix1 = 0x00000B2C,
1026 .hal_reo1_aging_thres_ix2 = 0x00000B30,
1027 .hal_reo1_aging_thres_ix3 = 0x00000B34,
1028
1029 /* REO Exception ring address */
1030 .hal_reo2_sw0_ring_base = 0x000008c0,
1031
1032 /* REO Reinject ring address */
1033 .hal_sw2reo_ring_base = 0x00000320,
1034 .hal_sw2reo1_ring_base = 0x00000398,
1035
1036 /* REO cmd ring address */
1037 .hal_reo_cmd_ring_base = 0x000002A8,
1038
1039 /* REO status ring address */
1040 .hal_reo_status_ring_base = 0x00000aa0,
1041
1042 /* CE base address */
1043 .hal_umac_ce0_src_reg_base = 0x01b80000,
1044 .hal_umac_ce0_dest_reg_base = 0x01b81000,
1045 .hal_umac_ce1_src_reg_base = 0x01b82000,
1046 .hal_umac_ce1_dest_reg_base = 0x01b83000,
1047
1048 .gcc_gcc_pcie_hot_rst = 0x1e38338,
1049 };
1050
1051 static const struct ath12k_hw_regs ipq5332_regs = {
1052 /* SW2TCL(x) R0 ring configuration address */
1053 .hal_tcl1_ring_id = 0x00000918,
1054 .hal_tcl1_ring_misc = 0x00000920,
1055 .hal_tcl1_ring_tp_addr_lsb = 0x0000092c,
1056 .hal_tcl1_ring_tp_addr_msb = 0x00000930,
1057 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000940,
1058 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000944,
1059 .hal_tcl1_ring_msi1_base_lsb = 0x00000958,
1060 .hal_tcl1_ring_msi1_base_msb = 0x0000095c,
1061 .hal_tcl1_ring_base_lsb = 0x00000910,
1062 .hal_tcl1_ring_base_msb = 0x00000914,
1063 .hal_tcl1_ring_msi1_data = 0x00000960,
1064 .hal_tcl2_ring_base_lsb = 0x00000988,
1065 .hal_tcl_ring_base_lsb = 0x00000b68,
1066
1067 /* TCL STATUS ring address */
1068 .hal_tcl_status_ring_base_lsb = 0x00000d48,
1069
1070 /* REO DEST ring address */
1071 .hal_reo2_ring_base = 0x00000578,
1072 .hal_reo1_misc_ctrl_addr = 0x00000b9c,
1073 .hal_reo1_sw_cookie_cfg0 = 0x0000006c,
1074 .hal_reo1_sw_cookie_cfg1 = 0x00000070,
1075 .hal_reo1_qdesc_lut_base0 = 0x00000074,
1076 .hal_reo1_qdesc_lut_base1 = 0x00000078,
1077 .hal_reo1_ring_base_lsb = 0x00000500,
1078 .hal_reo1_ring_base_msb = 0x00000504,
1079 .hal_reo1_ring_id = 0x00000508,
1080 .hal_reo1_ring_misc = 0x00000510,
1081 .hal_reo1_ring_hp_addr_lsb = 0x00000514,
1082 .hal_reo1_ring_hp_addr_msb = 0x00000518,
1083 .hal_reo1_ring_producer_int_setup = 0x00000524,
1084 .hal_reo1_ring_msi1_base_lsb = 0x00000548,
1085 .hal_reo1_ring_msi1_base_msb = 0x0000054C,
1086 .hal_reo1_ring_msi1_data = 0x00000550,
1087 .hal_reo1_aging_thres_ix0 = 0x00000B28,
1088 .hal_reo1_aging_thres_ix1 = 0x00000B2C,
1089 .hal_reo1_aging_thres_ix2 = 0x00000B30,
1090 .hal_reo1_aging_thres_ix3 = 0x00000B34,
1091
1092 /* REO Exception ring address */
1093 .hal_reo2_sw0_ring_base = 0x000008c0,
1094
1095 /* REO Reinject ring address */
1096 .hal_sw2reo_ring_base = 0x00000320,
1097 .hal_sw2reo1_ring_base = 0x00000398,
1098
1099 /* REO cmd ring address */
1100 .hal_reo_cmd_ring_base = 0x000002A8,
1101
1102 /* REO status ring address */
1103 .hal_reo_status_ring_base = 0x00000aa0,
1104
1105 /* WBM idle link ring address */
1106 .hal_wbm_idle_ring_base_lsb = 0x00000d3c,
1107 .hal_wbm_idle_ring_misc_addr = 0x00000d4c,
1108 .hal_wbm_r0_idle_list_cntl_addr = 0x00000240,
1109 .hal_wbm_r0_idle_list_size_addr = 0x00000244,
1110 .hal_wbm_scattered_ring_base_lsb = 0x00000250,
1111 .hal_wbm_scattered_ring_base_msb = 0x00000254,
1112 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000260,
1113 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000264,
1114 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000270,
1115 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000274,
1116 .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000027c,
1117
1118 /* SW2WBM release ring address */
1119 .hal_wbm_sw_release_ring_base_lsb = 0x0000037c,
1120
1121 /* WBM2SW release ring address */
1122 .hal_wbm0_release_ring_base_lsb = 0x00000e08,
1123 .hal_wbm1_release_ring_base_lsb = 0x00000e80,
1124
1125 /* PPE release ring address */
1126 .hal_ppe_rel_ring_base = 0x0000046c,
1127
1128 /* CE address */
1129 .hal_umac_ce0_src_reg_base = 0x00740000 -
1130 HAL_IPQ5332_CE_WFSS_REG_BASE,
1131 .hal_umac_ce0_dest_reg_base = 0x00741000 -
1132 HAL_IPQ5332_CE_WFSS_REG_BASE,
1133 .hal_umac_ce1_src_reg_base = 0x00742000 -
1134 HAL_IPQ5332_CE_WFSS_REG_BASE,
1135 .hal_umac_ce1_dest_reg_base = 0x00743000 -
1136 HAL_IPQ5332_CE_WFSS_REG_BASE,
1137 };
1138
1139 static const struct ath12k_hw_regs wcn7850_regs = {
1140 /* SW2TCL(x) R0 ring configuration address */
1141 .hal_tcl1_ring_id = 0x00000908,
1142 .hal_tcl1_ring_misc = 0x00000910,
1143 .hal_tcl1_ring_tp_addr_lsb = 0x0000091c,
1144 .hal_tcl1_ring_tp_addr_msb = 0x00000920,
1145 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930,
1146 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934,
1147 .hal_tcl1_ring_msi1_base_lsb = 0x00000948,
1148 .hal_tcl1_ring_msi1_base_msb = 0x0000094c,
1149 .hal_tcl1_ring_msi1_data = 0x00000950,
1150 .hal_tcl_ring_base_lsb = 0x00000b58,
1151 .hal_tcl1_ring_base_lsb = 0x00000900,
1152 .hal_tcl1_ring_base_msb = 0x00000904,
1153 .hal_tcl2_ring_base_lsb = 0x00000978,
1154
1155 /* TCL STATUS ring address */
1156 .hal_tcl_status_ring_base_lsb = 0x00000d38,
1157
1158 .hal_wbm_idle_ring_base_lsb = 0x00000d3c,
1159 .hal_wbm_idle_ring_misc_addr = 0x00000d4c,
1160 .hal_wbm_r0_idle_list_cntl_addr = 0x00000240,
1161 .hal_wbm_r0_idle_list_size_addr = 0x00000244,
1162 .hal_wbm_scattered_ring_base_lsb = 0x00000250,
1163 .hal_wbm_scattered_ring_base_msb = 0x00000254,
1164 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000260,
1165 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000264,
1166 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000270,
1167 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000274,
1168 .hal_wbm_scattered_desc_ptr_hp_addr = 0x00000027c,
1169
1170 .hal_wbm_sw_release_ring_base_lsb = 0x0000037c,
1171 .hal_wbm_sw1_release_ring_base_lsb = 0x00000284,
1172 .hal_wbm0_release_ring_base_lsb = 0x00000e08,
1173 .hal_wbm1_release_ring_base_lsb = 0x00000e80,
1174
1175 /* PCIe base address */
1176 .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8,
1177 .pcie_pcs_osc_dtct_config_base = 0x01e0f45c,
1178
1179 /* PPE release ring address */
1180 .hal_ppe_rel_ring_base = 0x0000043c,
1181
1182 /* REO DEST ring address */
1183 .hal_reo2_ring_base = 0x0000055c,
1184 .hal_reo1_misc_ctrl_addr = 0x00000b7c,
1185 .hal_reo1_sw_cookie_cfg0 = 0x00000050,
1186 .hal_reo1_sw_cookie_cfg1 = 0x00000054,
1187 .hal_reo1_qdesc_lut_base0 = 0x00000058,
1188 .hal_reo1_qdesc_lut_base1 = 0x0000005c,
1189 .hal_reo1_ring_base_lsb = 0x000004e4,
1190 .hal_reo1_ring_base_msb = 0x000004e8,
1191 .hal_reo1_ring_id = 0x000004ec,
1192 .hal_reo1_ring_misc = 0x000004f4,
1193 .hal_reo1_ring_hp_addr_lsb = 0x000004f8,
1194 .hal_reo1_ring_hp_addr_msb = 0x000004fc,
1195 .hal_reo1_ring_producer_int_setup = 0x00000508,
1196 .hal_reo1_ring_msi1_base_lsb = 0x0000052C,
1197 .hal_reo1_ring_msi1_base_msb = 0x00000530,
1198 .hal_reo1_ring_msi1_data = 0x00000534,
1199 .hal_reo1_aging_thres_ix0 = 0x00000b08,
1200 .hal_reo1_aging_thres_ix1 = 0x00000b0c,
1201 .hal_reo1_aging_thres_ix2 = 0x00000b10,
1202 .hal_reo1_aging_thres_ix3 = 0x00000b14,
1203
1204 /* REO Exception ring address */
1205 .hal_reo2_sw0_ring_base = 0x000008a4,
1206
1207 /* REO Reinject ring address */
1208 .hal_sw2reo_ring_base = 0x00000304,
1209 .hal_sw2reo1_ring_base = 0x0000037c,
1210
1211 /* REO cmd ring address */
1212 .hal_reo_cmd_ring_base = 0x0000028c,
1213
1214 /* REO status ring address */
1215 .hal_reo_status_ring_base = 0x00000a84,
1216
1217 /* CE base address */
1218 .hal_umac_ce0_src_reg_base = 0x01b80000,
1219 .hal_umac_ce0_dest_reg_base = 0x01b81000,
1220 .hal_umac_ce1_src_reg_base = 0x01b82000,
1221 .hal_umac_ce1_dest_reg_base = 0x01b83000,
1222
1223 .gcc_gcc_pcie_hot_rst = 0x1e40304,
1224 };
1225
1226 static const struct ath12k_hw_hal_params ath12k_hw_hal_params_qcn9274 = {
1227 .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM,
1228 .wbm2sw_cc_enable = HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN |
1229 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN |
1230 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN |
1231 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN |
1232 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN,
1233 };
1234
1235 static const struct ath12k_hw_hal_params ath12k_hw_hal_params_wcn7850 = {
1236 .rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM,
1237 .wbm2sw_cc_enable = HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN |
1238 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN |
1239 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN |
1240 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN,
1241 };
1242
1243 static const struct ath12k_hw_hal_params ath12k_hw_hal_params_ipq5332 = {
1244 .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM,
1245 .wbm2sw_cc_enable = HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN |
1246 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN |
1247 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN |
1248 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN |
1249 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN,
1250 };
1251
1252 static const struct ce_ie_addr ath12k_ce_ie_addr_ipq5332 = {
1253 .ie1_reg_addr = CE_HOST_IE_ADDRESS - HAL_IPQ5332_CE_WFSS_REG_BASE,
1254 .ie2_reg_addr = CE_HOST_IE_2_ADDRESS - HAL_IPQ5332_CE_WFSS_REG_BASE,
1255 .ie3_reg_addr = CE_HOST_IE_3_ADDRESS - HAL_IPQ5332_CE_WFSS_REG_BASE,
1256 };
1257
1258 static const struct ce_remap ath12k_ce_remap_ipq5332 = {
1259 .base = HAL_IPQ5332_CE_WFSS_REG_BASE,
1260 .size = HAL_IPQ5332_CE_SIZE,
1261 };
1262
1263 static const struct ath12k_hw_params ath12k_hw_params[] = {
1264 {
1265 .name = "qcn9274 hw1.0",
1266 .hw_rev = ATH12K_HW_QCN9274_HW10,
1267 .fw = {
1268 .dir = "QCN9274/hw1.0",
1269 .board_size = 256 * 1024,
1270 .cal_offset = 128 * 1024,
1271 .m3_loader = ath12k_m3_fw_loader_driver,
1272 },
1273 .max_radios = 1,
1274 .single_pdev_only = false,
1275 .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274,
1276 .internal_sleep_clock = false,
1277
1278 .hw_ops = &qcn9274_ops,
1279 .ring_mask = &ath12k_hw_ring_mask_qcn9274,
1280 .regs = &qcn9274_v1_regs,
1281
1282 .host_ce_config = ath12k_host_ce_config_qcn9274,
1283 .ce_count = 16,
1284 .target_ce_config = ath12k_target_ce_config_wlan_qcn9274,
1285 .target_ce_count = 12,
1286 .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_qcn9274,
1287 .svc_to_ce_map_len = 18,
1288
1289 .hal_params = &ath12k_hw_hal_params_qcn9274,
1290
1291 .rxdma1_enable = false,
1292 .num_rxdma_per_pdev = 1,
1293 .num_rxdma_dst_ring = 0,
1294 .rx_mac_buf_ring = false,
1295 .vdev_start_delay = false,
1296
1297 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
1298 BIT(NL80211_IFTYPE_AP) |
1299 BIT(NL80211_IFTYPE_MESH_POINT) |
1300 BIT(NL80211_IFTYPE_AP_VLAN),
1301 .supports_monitor = false,
1302
1303 .idle_ps = false,
1304 .download_calib = true,
1305 .supports_suspend = false,
1306 .tcl_ring_retry = true,
1307 .reoq_lut_support = true,
1308 .supports_shadow_regs = false,
1309
1310 .num_tcl_banks = 48,
1311 .max_tx_ring = 4,
1312
1313 .mhi_config = &ath12k_mhi_config_qcn9274,
1314
1315 .wmi_init = ath12k_wmi_init_qcn9274,
1316
1317 .hal_ops = &hal_qcn9274_ops,
1318
1319 .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01),
1320
1321 .rfkill_pin = 0,
1322 .rfkill_cfg = 0,
1323 .rfkill_on_level = 0,
1324
1325 .rddm_size = 0x600000,
1326
1327 .def_num_link = 0,
1328 .max_mlo_peer = 256,
1329
1330 .otp_board_id_register = QCN9274_QFPROM_RAW_RFA_PDET_ROW13_LSB,
1331
1332 .supports_sta_ps = false,
1333
1334 .acpi_guid = NULL,
1335 .supports_dynamic_smps_6ghz = true,
1336
1337 .iova_mask = 0,
1338
1339 .supports_aspm = false,
1340
1341 .ce_ie_addr = NULL,
1342 .ce_remap = NULL,
1343 .bdf_addr_offset = 0,
1344
1345 .current_cc_support = false,
1346
1347 .dp_primary_link_only = true,
1348 },
1349 {
1350 .name = "wcn7850 hw2.0",
1351 .hw_rev = ATH12K_HW_WCN7850_HW20,
1352
1353 .fw = {
1354 .dir = "WCN7850/hw2.0",
1355 .board_size = 256 * 1024,
1356 .cal_offset = 256 * 1024,
1357 .m3_loader = ath12k_m3_fw_loader_driver,
1358 },
1359
1360 .max_radios = 1,
1361 .single_pdev_only = true,
1362 .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850,
1363 .internal_sleep_clock = true,
1364
1365 .hw_ops = &wcn7850_ops,
1366 .ring_mask = &ath12k_hw_ring_mask_wcn7850,
1367 .regs = &wcn7850_regs,
1368
1369 .host_ce_config = ath12k_host_ce_config_wcn7850,
1370 .ce_count = 9,
1371 .target_ce_config = ath12k_target_ce_config_wlan_wcn7850,
1372 .target_ce_count = 9,
1373 .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_wcn7850,
1374 .svc_to_ce_map_len = 14,
1375
1376 .hal_params = &ath12k_hw_hal_params_wcn7850,
1377
1378 .rxdma1_enable = false,
1379 .num_rxdma_per_pdev = 2,
1380 .num_rxdma_dst_ring = 1,
1381 .rx_mac_buf_ring = true,
1382 .vdev_start_delay = true,
1383
1384 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
1385 BIT(NL80211_IFTYPE_AP) |
1386 BIT(NL80211_IFTYPE_P2P_DEVICE) |
1387 BIT(NL80211_IFTYPE_P2P_CLIENT) |
1388 BIT(NL80211_IFTYPE_P2P_GO),
1389 .supports_monitor = true,
1390
1391 .idle_ps = true,
1392 .download_calib = false,
1393 .supports_suspend = true,
1394 .tcl_ring_retry = false,
1395 .reoq_lut_support = false,
1396 .supports_shadow_regs = true,
1397
1398 .num_tcl_banks = 7,
1399 .max_tx_ring = 3,
1400
1401 .mhi_config = &ath12k_mhi_config_wcn7850,
1402
1403 .wmi_init = ath12k_wmi_init_wcn7850,
1404
1405 .hal_ops = &hal_wcn7850_ops,
1406
1407 .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01) |
1408 BIT(CNSS_PCIE_PERST_NO_PULL_V01),
1409
1410 .rfkill_pin = 48,
1411 .rfkill_cfg = 0,
1412 .rfkill_on_level = 1,
1413
1414 .rddm_size = 0x780000,
1415
1416 .def_num_link = 2,
1417 .max_mlo_peer = 32,
1418
1419 .otp_board_id_register = 0,
1420
1421 .supports_sta_ps = true,
1422
1423 .acpi_guid = &wcn7850_uuid,
1424 .supports_dynamic_smps_6ghz = false,
1425
1426 .iova_mask = ATH12K_PCIE_MAX_PAYLOAD_SIZE - 1,
1427
1428 .supports_aspm = true,
1429
1430 .ce_ie_addr = NULL,
1431 .ce_remap = NULL,
1432 .bdf_addr_offset = 0,
1433
1434 .current_cc_support = true,
1435
1436 .dp_primary_link_only = false,
1437 },
1438 {
1439 .name = "qcn9274 hw2.0",
1440 .hw_rev = ATH12K_HW_QCN9274_HW20,
1441 .fw = {
1442 .dir = "QCN9274/hw2.0",
1443 .board_size = 256 * 1024,
1444 .cal_offset = 128 * 1024,
1445 .m3_loader = ath12k_m3_fw_loader_driver,
1446 },
1447 .max_radios = 2,
1448 .single_pdev_only = false,
1449 .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274,
1450 .internal_sleep_clock = false,
1451
1452 .hw_ops = &qcn9274_ops,
1453 .ring_mask = &ath12k_hw_ring_mask_qcn9274,
1454 .regs = &qcn9274_v2_regs,
1455
1456 .host_ce_config = ath12k_host_ce_config_qcn9274,
1457 .ce_count = 16,
1458 .target_ce_config = ath12k_target_ce_config_wlan_qcn9274,
1459 .target_ce_count = 12,
1460 .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_qcn9274,
1461 .svc_to_ce_map_len = 18,
1462
1463 .hal_params = &ath12k_hw_hal_params_qcn9274,
1464
1465 .rxdma1_enable = true,
1466 .num_rxdma_per_pdev = 1,
1467 .num_rxdma_dst_ring = 0,
1468 .rx_mac_buf_ring = false,
1469 .vdev_start_delay = false,
1470
1471 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
1472 BIT(NL80211_IFTYPE_AP) |
1473 BIT(NL80211_IFTYPE_MESH_POINT) |
1474 BIT(NL80211_IFTYPE_AP_VLAN),
1475 .supports_monitor = true,
1476
1477 .idle_ps = false,
1478 .download_calib = true,
1479 .supports_suspend = false,
1480 .tcl_ring_retry = true,
1481 .reoq_lut_support = false,
1482 .supports_shadow_regs = false,
1483
1484 .num_tcl_banks = 48,
1485 .max_tx_ring = 4,
1486
1487 .mhi_config = &ath12k_mhi_config_qcn9274,
1488
1489 .wmi_init = ath12k_wmi_init_qcn9274,
1490
1491 .hal_ops = &hal_qcn9274_ops,
1492
1493 .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01),
1494
1495 .rfkill_pin = 0,
1496 .rfkill_cfg = 0,
1497 .rfkill_on_level = 0,
1498
1499 .rddm_size = 0x600000,
1500
1501 .def_num_link = 0,
1502 .max_mlo_peer = 256,
1503
1504 .otp_board_id_register = QCN9274_QFPROM_RAW_RFA_PDET_ROW13_LSB,
1505
1506 .supports_sta_ps = false,
1507
1508 .acpi_guid = NULL,
1509 .supports_dynamic_smps_6ghz = true,
1510
1511 .iova_mask = 0,
1512
1513 .supports_aspm = false,
1514
1515 .ce_ie_addr = NULL,
1516 .ce_remap = NULL,
1517 .bdf_addr_offset = 0,
1518
1519 .current_cc_support = false,
1520
1521 .dp_primary_link_only = true,
1522 },
1523 {
1524 .name = "ipq5332 hw1.0",
1525 .hw_rev = ATH12K_HW_IPQ5332_HW10,
1526 .fw = {
1527 .dir = "IPQ5332/hw1.0",
1528 .board_size = 256 * 1024,
1529 .cal_offset = 128 * 1024,
1530 .m3_loader = ath12k_m3_fw_loader_remoteproc,
1531 },
1532 .max_radios = 1,
1533 .single_pdev_only = false,
1534 .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ5332,
1535 .internal_sleep_clock = false,
1536
1537 .hw_ops = &qcn9274_ops,
1538 .regs = &ipq5332_regs,
1539 .ring_mask = &ath12k_hw_ring_mask_ipq5332,
1540
1541 .host_ce_config = ath12k_host_ce_config_ipq5332,
1542 .ce_count = 12,
1543 .target_ce_config = ath12k_target_ce_config_wlan_ipq5332,
1544 .target_ce_count = 12,
1545 .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_ipq5332,
1546 .svc_to_ce_map_len = 18,
1547
1548 .hal_params = &ath12k_hw_hal_params_ipq5332,
1549
1550 .rxdma1_enable = false,
1551 .num_rxdma_per_pdev = 1,
1552 .num_rxdma_dst_ring = 0,
1553 .rx_mac_buf_ring = false,
1554 .vdev_start_delay = false,
1555
1556 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
1557 BIT(NL80211_IFTYPE_AP) |
1558 BIT(NL80211_IFTYPE_MESH_POINT),
1559 .supports_monitor = false,
1560
1561 .idle_ps = false,
1562 .download_calib = true,
1563 .supports_suspend = false,
1564 .tcl_ring_retry = true,
1565 .reoq_lut_support = false,
1566 .supports_shadow_regs = false,
1567
1568 .num_tcl_banks = 48,
1569 .max_tx_ring = 4,
1570
1571 .wmi_init = &ath12k_wmi_init_qcn9274,
1572
1573 .hal_ops = &hal_qcn9274_ops,
1574
1575 .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01),
1576
1577 .rfkill_pin = 0,
1578 .rfkill_cfg = 0,
1579 .rfkill_on_level = 0,
1580
1581 .rddm_size = 0,
1582
1583 .def_num_link = 0,
1584 .max_mlo_peer = 256,
1585
1586 .otp_board_id_register = 0,
1587
1588 .supports_sta_ps = false,
1589
1590 .acpi_guid = NULL,
1591 .supports_dynamic_smps_6ghz = false,
1592 .iova_mask = 0,
1593 .supports_aspm = false,
1594
1595 .ce_ie_addr = &ath12k_ce_ie_addr_ipq5332,
1596 .ce_remap = &ath12k_ce_remap_ipq5332,
1597 .bdf_addr_offset = 0xC00000,
1598
1599 .dp_primary_link_only = true,
1600 },
1601 };
1602
ath12k_hw_init(struct ath12k_base * ab)1603 int ath12k_hw_init(struct ath12k_base *ab)
1604 {
1605 const struct ath12k_hw_params *hw_params = NULL;
1606 int i;
1607
1608 for (i = 0; i < ARRAY_SIZE(ath12k_hw_params); i++) {
1609 hw_params = &ath12k_hw_params[i];
1610
1611 if (hw_params->hw_rev == ab->hw_rev)
1612 break;
1613 }
1614
1615 if (i == ARRAY_SIZE(ath12k_hw_params)) {
1616 ath12k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev);
1617 return -EINVAL;
1618 }
1619
1620 ab->hw_params = hw_params;
1621
1622 ath12k_info(ab, "Hardware name: %s\n", ab->hw_params->name);
1623
1624 return 0;
1625 }
1626