1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include "core.h"
8 #include "dp_tx.h"
9 #include "debug.h"
10 #include "hw.h"
11 #include "peer.h"
12 #include "mac.h"
13
14 static enum hal_tcl_encap_type
ath12k_dp_tx_get_encap_type(struct ath12k_link_vif * arvif,struct sk_buff * skb)15 ath12k_dp_tx_get_encap_type(struct ath12k_link_vif *arvif, struct sk_buff *skb)
16 {
17 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
18 struct ath12k_base *ab = arvif->ar->ab;
19
20 if (test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags))
21 return HAL_TCL_ENCAP_TYPE_RAW;
22
23 if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP)
24 return HAL_TCL_ENCAP_TYPE_ETHERNET;
25
26 return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI;
27 }
28
ath12k_dp_tx_encap_nwifi(struct sk_buff * skb)29 static void ath12k_dp_tx_encap_nwifi(struct sk_buff *skb)
30 {
31 struct ieee80211_hdr *hdr = (void *)skb->data;
32 u8 *qos_ctl;
33
34 if (!ieee80211_is_data_qos(hdr->frame_control))
35 return;
36
37 qos_ctl = ieee80211_get_qos_ctl(hdr);
38 memmove(skb->data + IEEE80211_QOS_CTL_LEN,
39 skb->data, (void *)qos_ctl - (void *)skb->data);
40 skb_pull(skb, IEEE80211_QOS_CTL_LEN);
41
42 hdr = (void *)skb->data;
43 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
44 }
45
ath12k_dp_tx_get_tid(struct sk_buff * skb)46 static u8 ath12k_dp_tx_get_tid(struct sk_buff *skb)
47 {
48 struct ieee80211_hdr *hdr = (void *)skb->data;
49 struct ath12k_skb_cb *cb = ATH12K_SKB_CB(skb);
50
51 if (cb->flags & ATH12K_SKB_HW_80211_ENCAP)
52 return skb->priority & IEEE80211_QOS_CTL_TID_MASK;
53 else if (!ieee80211_is_data_qos(hdr->frame_control))
54 return HAL_DESC_REO_NON_QOS_TID;
55 else
56 return skb->priority & IEEE80211_QOS_CTL_TID_MASK;
57 }
58
ath12k_dp_tx_get_encrypt_type(u32 cipher)59 enum hal_encrypt_type ath12k_dp_tx_get_encrypt_type(u32 cipher)
60 {
61 switch (cipher) {
62 case WLAN_CIPHER_SUITE_WEP40:
63 return HAL_ENCRYPT_TYPE_WEP_40;
64 case WLAN_CIPHER_SUITE_WEP104:
65 return HAL_ENCRYPT_TYPE_WEP_104;
66 case WLAN_CIPHER_SUITE_TKIP:
67 return HAL_ENCRYPT_TYPE_TKIP_MIC;
68 case WLAN_CIPHER_SUITE_CCMP:
69 return HAL_ENCRYPT_TYPE_CCMP_128;
70 case WLAN_CIPHER_SUITE_CCMP_256:
71 return HAL_ENCRYPT_TYPE_CCMP_256;
72 case WLAN_CIPHER_SUITE_GCMP:
73 return HAL_ENCRYPT_TYPE_GCMP_128;
74 case WLAN_CIPHER_SUITE_GCMP_256:
75 return HAL_ENCRYPT_TYPE_AES_GCMP_256;
76 default:
77 return HAL_ENCRYPT_TYPE_OPEN;
78 }
79 }
80
ath12k_dp_tx_release_txbuf(struct ath12k_dp * dp,struct ath12k_tx_desc_info * tx_desc,u8 pool_id)81 static void ath12k_dp_tx_release_txbuf(struct ath12k_dp *dp,
82 struct ath12k_tx_desc_info *tx_desc,
83 u8 pool_id)
84 {
85 spin_lock_bh(&dp->tx_desc_lock[pool_id]);
86 list_move_tail(&tx_desc->list, &dp->tx_desc_free_list[pool_id]);
87 spin_unlock_bh(&dp->tx_desc_lock[pool_id]);
88 }
89
ath12k_dp_tx_assign_buffer(struct ath12k_dp * dp,u8 pool_id)90 static struct ath12k_tx_desc_info *ath12k_dp_tx_assign_buffer(struct ath12k_dp *dp,
91 u8 pool_id)
92 {
93 struct ath12k_tx_desc_info *desc;
94
95 spin_lock_bh(&dp->tx_desc_lock[pool_id]);
96 desc = list_first_entry_or_null(&dp->tx_desc_free_list[pool_id],
97 struct ath12k_tx_desc_info,
98 list);
99 if (!desc) {
100 spin_unlock_bh(&dp->tx_desc_lock[pool_id]);
101 ath12k_warn(dp->ab, "failed to allocate data Tx buffer\n");
102 return NULL;
103 }
104
105 list_move_tail(&desc->list, &dp->tx_desc_used_list[pool_id]);
106 spin_unlock_bh(&dp->tx_desc_lock[pool_id]);
107
108 return desc;
109 }
110
ath12k_hal_tx_cmd_ext_desc_setup(struct ath12k_base * ab,struct hal_tx_msdu_ext_desc * tcl_ext_cmd,struct hal_tx_info * ti)111 static void ath12k_hal_tx_cmd_ext_desc_setup(struct ath12k_base *ab,
112 struct hal_tx_msdu_ext_desc *tcl_ext_cmd,
113 struct hal_tx_info *ti)
114 {
115 tcl_ext_cmd->info0 = le32_encode_bits(ti->paddr,
116 HAL_TX_MSDU_EXT_INFO0_BUF_PTR_LO);
117 tcl_ext_cmd->info1 = le32_encode_bits(0x0,
118 HAL_TX_MSDU_EXT_INFO1_BUF_PTR_HI) |
119 le32_encode_bits(ti->data_len,
120 HAL_TX_MSDU_EXT_INFO1_BUF_LEN);
121
122 tcl_ext_cmd->info1 |= le32_encode_bits(1, HAL_TX_MSDU_EXT_INFO1_EXTN_OVERRIDE) |
123 le32_encode_bits(ti->encap_type,
124 HAL_TX_MSDU_EXT_INFO1_ENCAP_TYPE) |
125 le32_encode_bits(ti->encrypt_type,
126 HAL_TX_MSDU_EXT_INFO1_ENCRYPT_TYPE);
127 }
128
129 #define HTT_META_DATA_ALIGNMENT 0x8
130
ath12k_dp_metadata_align_skb(struct sk_buff * skb,u8 tail_len)131 static void *ath12k_dp_metadata_align_skb(struct sk_buff *skb, u8 tail_len)
132 {
133 struct sk_buff *tail;
134 void *metadata;
135
136 if (unlikely(skb_cow_data(skb, tail_len, &tail) < 0))
137 return NULL;
138
139 metadata = pskb_put(skb, tail, tail_len);
140 memset(metadata, 0, tail_len);
141 return metadata;
142 }
143
144 /* Preparing HTT Metadata when utilized with ext MSDU */
ath12k_dp_prepare_htt_metadata(struct sk_buff * skb)145 static int ath12k_dp_prepare_htt_metadata(struct sk_buff *skb)
146 {
147 struct hal_tx_msdu_metadata *desc_ext;
148 u8 htt_desc_size;
149 /* Size rounded of multiple of 8 bytes */
150 u8 htt_desc_size_aligned;
151
152 htt_desc_size = sizeof(struct hal_tx_msdu_metadata);
153 htt_desc_size_aligned = ALIGN(htt_desc_size, HTT_META_DATA_ALIGNMENT);
154
155 desc_ext = ath12k_dp_metadata_align_skb(skb, htt_desc_size_aligned);
156 if (!desc_ext)
157 return -ENOMEM;
158
159 desc_ext->info0 = le32_encode_bits(1, HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_FLAG) |
160 le32_encode_bits(0, HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_TYPE) |
161 le32_encode_bits(1,
162 HAL_TX_MSDU_METADATA_INFO0_HOST_TX_DESC_POOL);
163
164 return 0;
165 }
166
ath12k_dp_tx_move_payload(struct sk_buff * skb,unsigned long delta,bool head)167 static void ath12k_dp_tx_move_payload(struct sk_buff *skb,
168 unsigned long delta,
169 bool head)
170 {
171 unsigned long len = skb->len;
172
173 if (head) {
174 skb_push(skb, delta);
175 memmove(skb->data, skb->data + delta, len);
176 skb_trim(skb, len);
177 } else {
178 skb_put(skb, delta);
179 memmove(skb->data + delta, skb->data, len);
180 skb_pull(skb, delta);
181 }
182 }
183
ath12k_dp_tx_align_payload(struct ath12k_base * ab,struct sk_buff ** pskb)184 static int ath12k_dp_tx_align_payload(struct ath12k_base *ab,
185 struct sk_buff **pskb)
186 {
187 u32 iova_mask = ab->hw_params->iova_mask;
188 unsigned long offset, delta1, delta2;
189 struct sk_buff *skb2, *skb = *pskb;
190 unsigned int headroom = skb_headroom(skb);
191 int tailroom = skb_tailroom(skb);
192 int ret = 0;
193
194 offset = (unsigned long)skb->data & iova_mask;
195 delta1 = offset;
196 delta2 = iova_mask - offset + 1;
197
198 if (headroom >= delta1) {
199 ath12k_dp_tx_move_payload(skb, delta1, true);
200 } else if (tailroom >= delta2) {
201 ath12k_dp_tx_move_payload(skb, delta2, false);
202 } else {
203 skb2 = skb_realloc_headroom(skb, iova_mask);
204 if (!skb2) {
205 ret = -ENOMEM;
206 goto out;
207 }
208
209 dev_kfree_skb_any(skb);
210
211 offset = (unsigned long)skb2->data & iova_mask;
212 if (offset)
213 ath12k_dp_tx_move_payload(skb2, offset, true);
214 *pskb = skb2;
215 }
216
217 out:
218 return ret;
219 }
220
ath12k_dp_tx(struct ath12k * ar,struct ath12k_link_vif * arvif,struct sk_buff * skb,bool gsn_valid,int mcbc_gsn)221 int ath12k_dp_tx(struct ath12k *ar, struct ath12k_link_vif *arvif,
222 struct sk_buff *skb, bool gsn_valid, int mcbc_gsn)
223 {
224 struct ath12k_base *ab = ar->ab;
225 struct ath12k_dp *dp = &ab->dp;
226 struct hal_tx_info ti = {0};
227 struct ath12k_tx_desc_info *tx_desc;
228 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
229 struct ath12k_skb_cb *skb_cb = ATH12K_SKB_CB(skb);
230 struct hal_tcl_data_cmd *hal_tcl_desc;
231 struct hal_tx_msdu_ext_desc *msg;
232 struct sk_buff *skb_ext_desc;
233 struct hal_srng *tcl_ring;
234 struct ieee80211_hdr *hdr = (void *)skb->data;
235 struct ath12k_vif *ahvif = arvif->ahvif;
236 struct dp_tx_ring *tx_ring;
237 u8 pool_id;
238 u8 hal_ring_id;
239 int ret;
240 u8 ring_selector, ring_map = 0;
241 bool tcl_ring_retry;
242 bool msdu_ext_desc = false;
243 bool add_htt_metadata = false;
244 u32 iova_mask = ab->hw_params->iova_mask;
245
246 if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags))
247 return -ESHUTDOWN;
248
249 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) &&
250 !ieee80211_is_data(hdr->frame_control))
251 return -EOPNOTSUPP;
252
253 pool_id = skb_get_queue_mapping(skb) & (ATH12K_HW_MAX_QUEUES - 1);
254
255 /* Let the default ring selection be based on current processor
256 * number, where one of the 3 tcl rings are selected based on
257 * the smp_processor_id(). In case that ring
258 * is full/busy, we resort to other available rings.
259 * If all rings are full, we drop the packet.
260 * TODO: Add throttling logic when all rings are full
261 */
262 ring_selector = ab->hw_params->hw_ops->get_ring_selector(skb);
263
264 tcl_ring_sel:
265 tcl_ring_retry = false;
266 ti.ring_id = ring_selector % ab->hw_params->max_tx_ring;
267
268 ring_map |= BIT(ti.ring_id);
269 ti.rbm_id = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map[ti.ring_id].rbm_id;
270
271 tx_ring = &dp->tx_ring[ti.ring_id];
272
273 tx_desc = ath12k_dp_tx_assign_buffer(dp, pool_id);
274 if (!tx_desc)
275 return -ENOMEM;
276
277 ti.bank_id = arvif->bank_id;
278 ti.meta_data_flags = arvif->tcl_metadata;
279
280 if (ahvif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW &&
281 test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->dev_flags)) {
282 if (skb_cb->flags & ATH12K_SKB_CIPHER_SET) {
283 ti.encrypt_type =
284 ath12k_dp_tx_get_encrypt_type(skb_cb->cipher);
285
286 if (ieee80211_has_protected(hdr->frame_control))
287 skb_put(skb, IEEE80211_CCMP_MIC_LEN);
288 } else {
289 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN;
290 }
291
292 msdu_ext_desc = true;
293 }
294
295 if (gsn_valid) {
296 /* Reset and Initialize meta_data_flags with Global Sequence
297 * Number (GSN) info.
298 */
299 ti.meta_data_flags =
300 u32_encode_bits(HTT_TCL_META_DATA_TYPE_GLOBAL_SEQ_NUM,
301 HTT_TCL_META_DATA_TYPE) |
302 u32_encode_bits(mcbc_gsn, HTT_TCL_META_DATA_GLOBAL_SEQ_NUM);
303 }
304
305 ti.encap_type = ath12k_dp_tx_get_encap_type(arvif, skb);
306 ti.addr_search_flags = arvif->hal_addr_search_flags;
307 ti.search_type = arvif->search_type;
308 ti.type = HAL_TCL_DESC_TYPE_BUFFER;
309 ti.pkt_offset = 0;
310 ti.lmac_id = ar->lmac_id;
311
312 ti.vdev_id = arvif->vdev_id;
313 if (gsn_valid)
314 ti.vdev_id += HTT_TX_MLO_MCAST_HOST_REINJECT_BASE_VDEV_ID;
315
316 ti.bss_ast_hash = arvif->ast_hash;
317 ti.bss_ast_idx = arvif->ast_idx;
318 ti.dscp_tid_tbl_idx = 0;
319
320 if (skb->ip_summed == CHECKSUM_PARTIAL &&
321 ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW) {
322 ti.flags0 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_IP4_CKSUM_EN) |
323 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP4_CKSUM_EN) |
324 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP6_CKSUM_EN) |
325 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP4_CKSUM_EN) |
326 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP6_CKSUM_EN);
327 }
328
329 ti.flags1 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO3_TID_OVERWRITE);
330
331 ti.tid = ath12k_dp_tx_get_tid(skb);
332
333 switch (ti.encap_type) {
334 case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI:
335 ath12k_dp_tx_encap_nwifi(skb);
336 break;
337 case HAL_TCL_ENCAP_TYPE_RAW:
338 if (!test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) {
339 ret = -EINVAL;
340 goto fail_remove_tx_buf;
341 }
342 break;
343 case HAL_TCL_ENCAP_TYPE_ETHERNET:
344 /* no need to encap */
345 break;
346 case HAL_TCL_ENCAP_TYPE_802_3:
347 default:
348 /* TODO: Take care of other encap modes as well */
349 ret = -EINVAL;
350 atomic_inc(&ab->soc_stats.tx_err.misc_fail);
351 goto fail_remove_tx_buf;
352 }
353
354 if (iova_mask &&
355 (unsigned long)skb->data & iova_mask) {
356 ret = ath12k_dp_tx_align_payload(ab, &skb);
357 if (ret) {
358 ath12k_warn(ab, "failed to align TX buffer %d\n", ret);
359 /* don't bail out, give original buffer
360 * a chance even unaligned.
361 */
362 goto map;
363 }
364
365 /* hdr is pointing to a wrong place after alignment,
366 * so refresh it for later use.
367 */
368 hdr = (void *)skb->data;
369 }
370 map:
371 ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE);
372 if (dma_mapping_error(ab->dev, ti.paddr)) {
373 atomic_inc(&ab->soc_stats.tx_err.misc_fail);
374 ath12k_warn(ab, "failed to DMA map data Tx buffer\n");
375 ret = -ENOMEM;
376 goto fail_remove_tx_buf;
377 }
378
379 if (!test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->dev_flags) &&
380 !(skb_cb->flags & ATH12K_SKB_HW_80211_ENCAP) &&
381 !(skb_cb->flags & ATH12K_SKB_CIPHER_SET) &&
382 ieee80211_has_protected(hdr->frame_control)) {
383 /* Add metadata for sw encrypted vlan group traffic */
384 add_htt_metadata = true;
385 msdu_ext_desc = true;
386 ti.flags0 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TO_FW);
387 ti.meta_data_flags |= HTT_TCL_META_DATA_VALID_HTT;
388 ti.encap_type = HAL_TCL_ENCAP_TYPE_RAW;
389 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN;
390 }
391
392 tx_desc->skb = skb;
393 tx_desc->mac_id = ar->pdev_idx;
394 ti.desc_id = tx_desc->desc_id;
395 ti.data_len = skb->len;
396 skb_cb->paddr = ti.paddr;
397 skb_cb->vif = ahvif->vif;
398 skb_cb->ar = ar;
399
400 if (msdu_ext_desc) {
401 skb_ext_desc = dev_alloc_skb(sizeof(struct hal_tx_msdu_ext_desc));
402 if (!skb_ext_desc) {
403 ret = -ENOMEM;
404 goto fail_unmap_dma;
405 }
406
407 skb_put(skb_ext_desc, sizeof(struct hal_tx_msdu_ext_desc));
408 memset(skb_ext_desc->data, 0, skb_ext_desc->len);
409
410 msg = (struct hal_tx_msdu_ext_desc *)skb_ext_desc->data;
411 ath12k_hal_tx_cmd_ext_desc_setup(ab, msg, &ti);
412
413 if (add_htt_metadata) {
414 ret = ath12k_dp_prepare_htt_metadata(skb_ext_desc);
415 if (ret < 0) {
416 ath12k_dbg(ab, ATH12K_DBG_DP_TX,
417 "Failed to add HTT meta data, dropping packet\n");
418 kfree_skb(skb_ext_desc);
419 goto fail_unmap_dma;
420 }
421 }
422
423 ti.paddr = dma_map_single(ab->dev, skb_ext_desc->data,
424 skb_ext_desc->len, DMA_TO_DEVICE);
425 ret = dma_mapping_error(ab->dev, ti.paddr);
426 if (ret) {
427 kfree_skb(skb_ext_desc);
428 goto fail_unmap_dma;
429 }
430
431 ti.data_len = skb_ext_desc->len;
432 ti.type = HAL_TCL_DESC_TYPE_EXT_DESC;
433
434 skb_cb->paddr_ext_desc = ti.paddr;
435 }
436
437 hal_ring_id = tx_ring->tcl_data_ring.ring_id;
438 tcl_ring = &ab->hal.srng_list[hal_ring_id];
439
440 spin_lock_bh(&tcl_ring->lock);
441
442 ath12k_hal_srng_access_begin(ab, tcl_ring);
443
444 hal_tcl_desc = ath12k_hal_srng_src_get_next_entry(ab, tcl_ring);
445 if (!hal_tcl_desc) {
446 /* NOTE: It is highly unlikely we'll be running out of tcl_ring
447 * desc because the desc is directly enqueued onto hw queue.
448 */
449 ath12k_hal_srng_access_end(ab, tcl_ring);
450 ab->soc_stats.tx_err.desc_na[ti.ring_id]++;
451 spin_unlock_bh(&tcl_ring->lock);
452 ret = -ENOMEM;
453
454 /* Checking for available tcl descriptors in another ring in
455 * case of failure due to full tcl ring now, is better than
456 * checking this ring earlier for each pkt tx.
457 * Restart ring selection if some rings are not checked yet.
458 */
459 if (ring_map != (BIT(ab->hw_params->max_tx_ring) - 1) &&
460 ab->hw_params->tcl_ring_retry) {
461 tcl_ring_retry = true;
462 ring_selector++;
463 }
464
465 goto fail_unmap_dma;
466 }
467
468 ath12k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc, &ti);
469
470 ath12k_hal_srng_access_end(ab, tcl_ring);
471
472 spin_unlock_bh(&tcl_ring->lock);
473
474 ath12k_dbg_dump(ab, ATH12K_DBG_DP_TX, NULL, "dp tx msdu: ",
475 skb->data, skb->len);
476
477 atomic_inc(&ar->dp.num_tx_pending);
478
479 return 0;
480
481 fail_unmap_dma:
482 dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE);
483
484 if (skb_cb->paddr_ext_desc)
485 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc,
486 sizeof(struct hal_tx_msdu_ext_desc),
487 DMA_TO_DEVICE);
488
489 fail_remove_tx_buf:
490 ath12k_dp_tx_release_txbuf(dp, tx_desc, pool_id);
491 if (tcl_ring_retry)
492 goto tcl_ring_sel;
493
494 return ret;
495 }
496
ath12k_dp_tx_free_txbuf(struct ath12k_base * ab,struct sk_buff * msdu,u8 mac_id,struct dp_tx_ring * tx_ring)497 static void ath12k_dp_tx_free_txbuf(struct ath12k_base *ab,
498 struct sk_buff *msdu, u8 mac_id,
499 struct dp_tx_ring *tx_ring)
500 {
501 struct ath12k *ar;
502 struct ath12k_skb_cb *skb_cb;
503 u8 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id);
504
505 skb_cb = ATH12K_SKB_CB(msdu);
506 ar = ab->pdevs[pdev_id].ar;
507
508 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
509 if (skb_cb->paddr_ext_desc)
510 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc,
511 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE);
512
513 ieee80211_free_txskb(ar->ah->hw, msdu);
514
515 if (atomic_dec_and_test(&ar->dp.num_tx_pending))
516 wake_up(&ar->dp.tx_empty_waitq);
517 }
518
519 static void
ath12k_dp_tx_htt_tx_complete_buf(struct ath12k_base * ab,struct sk_buff * msdu,struct dp_tx_ring * tx_ring,struct ath12k_dp_htt_wbm_tx_status * ts)520 ath12k_dp_tx_htt_tx_complete_buf(struct ath12k_base *ab,
521 struct sk_buff *msdu,
522 struct dp_tx_ring *tx_ring,
523 struct ath12k_dp_htt_wbm_tx_status *ts)
524 {
525 struct ieee80211_tx_info *info;
526 struct ath12k_skb_cb *skb_cb;
527 struct ath12k *ar;
528
529 skb_cb = ATH12K_SKB_CB(msdu);
530 info = IEEE80211_SKB_CB(msdu);
531
532 ar = skb_cb->ar;
533
534 if (atomic_dec_and_test(&ar->dp.num_tx_pending))
535 wake_up(&ar->dp.tx_empty_waitq);
536
537 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
538 if (skb_cb->paddr_ext_desc)
539 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc,
540 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE);
541
542 memset(&info->status, 0, sizeof(info->status));
543
544 if (ts->acked) {
545 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
546 info->flags |= IEEE80211_TX_STAT_ACK;
547 info->status.ack_signal = ts->ack_rssi;
548
549 if (!test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT,
550 ab->wmi_ab.svc_map))
551 info->status.ack_signal += ATH12K_DEFAULT_NOISE_FLOOR;
552
553 info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID;
554 } else {
555 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
556 }
557 }
558
559 ieee80211_tx_status_skb(ath12k_ar_to_hw(ar), msdu);
560 }
561
562 static void
ath12k_dp_tx_process_htt_tx_complete(struct ath12k_base * ab,void * desc,u8 mac_id,struct sk_buff * msdu,struct dp_tx_ring * tx_ring)563 ath12k_dp_tx_process_htt_tx_complete(struct ath12k_base *ab,
564 void *desc, u8 mac_id,
565 struct sk_buff *msdu,
566 struct dp_tx_ring *tx_ring)
567 {
568 struct htt_tx_wbm_completion *status_desc;
569 struct ath12k_dp_htt_wbm_tx_status ts = {0};
570 enum hal_wbm_htt_tx_comp_status wbm_status;
571
572 status_desc = desc;
573
574 wbm_status = le32_get_bits(status_desc->info0,
575 HTT_TX_WBM_COMP_INFO0_STATUS);
576
577 switch (wbm_status) {
578 case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK:
579 ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK);
580 ts.ack_rssi = le32_get_bits(status_desc->info2,
581 HTT_TX_WBM_COMP_INFO2_ACK_RSSI);
582 ath12k_dp_tx_htt_tx_complete_buf(ab, msdu, tx_ring, &ts);
583 break;
584 case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP:
585 case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL:
586 case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ:
587 case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT:
588 ath12k_dp_tx_free_txbuf(ab, msdu, mac_id, tx_ring);
589 break;
590 case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY:
591 /* This event is to be handled only when the driver decides to
592 * use WDS offload functionality.
593 */
594 break;
595 default:
596 ath12k_warn(ab, "Unknown htt tx status %d\n", wbm_status);
597 break;
598 }
599 }
600
ath12k_dp_tx_update_txcompl(struct ath12k * ar,struct hal_tx_status * ts)601 static void ath12k_dp_tx_update_txcompl(struct ath12k *ar, struct hal_tx_status *ts)
602 {
603 struct ath12k_base *ab = ar->ab;
604 struct ath12k_peer *peer;
605 struct ieee80211_sta *sta;
606 struct ath12k_sta *ahsta;
607 struct ath12k_link_sta *arsta;
608 struct rate_info txrate = {0};
609 u16 rate, ru_tones;
610 u8 rate_idx = 0;
611 int ret;
612
613 spin_lock_bh(&ab->base_lock);
614 peer = ath12k_peer_find_by_id(ab, ts->peer_id);
615 if (!peer || !peer->sta) {
616 ath12k_dbg(ab, ATH12K_DBG_DP_TX,
617 "failed to find the peer by id %u\n", ts->peer_id);
618 spin_unlock_bh(&ab->base_lock);
619 return;
620 }
621 sta = peer->sta;
622 ahsta = ath12k_sta_to_ahsta(sta);
623 arsta = &ahsta->deflink;
624
625 /* This is to prefer choose the real NSS value arsta->last_txrate.nss,
626 * if it is invalid, then choose the NSS value while assoc.
627 */
628 if (arsta->last_txrate.nss)
629 txrate.nss = arsta->last_txrate.nss;
630 else
631 txrate.nss = arsta->peer_nss;
632 spin_unlock_bh(&ab->base_lock);
633
634 switch (ts->pkt_type) {
635 case HAL_TX_RATE_STATS_PKT_TYPE_11A:
636 case HAL_TX_RATE_STATS_PKT_TYPE_11B:
637 ret = ath12k_mac_hw_ratecode_to_legacy_rate(ts->mcs,
638 ts->pkt_type,
639 &rate_idx,
640 &rate);
641 if (ret < 0) {
642 ath12k_warn(ab, "Invalid tx legacy rate %d\n", ret);
643 return;
644 }
645
646 txrate.legacy = rate;
647 break;
648 case HAL_TX_RATE_STATS_PKT_TYPE_11N:
649 if (ts->mcs > ATH12K_HT_MCS_MAX) {
650 ath12k_warn(ab, "Invalid HT mcs index %d\n", ts->mcs);
651 return;
652 }
653
654 if (txrate.nss != 0)
655 txrate.mcs = ts->mcs + 8 * (txrate.nss - 1);
656
657 txrate.flags = RATE_INFO_FLAGS_MCS;
658
659 if (ts->sgi)
660 txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
661 break;
662 case HAL_TX_RATE_STATS_PKT_TYPE_11AC:
663 if (ts->mcs > ATH12K_VHT_MCS_MAX) {
664 ath12k_warn(ab, "Invalid VHT mcs index %d\n", ts->mcs);
665 return;
666 }
667
668 txrate.mcs = ts->mcs;
669 txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
670
671 if (ts->sgi)
672 txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
673 break;
674 case HAL_TX_RATE_STATS_PKT_TYPE_11AX:
675 if (ts->mcs > ATH12K_HE_MCS_MAX) {
676 ath12k_warn(ab, "Invalid HE mcs index %d\n", ts->mcs);
677 return;
678 }
679
680 txrate.mcs = ts->mcs;
681 txrate.flags = RATE_INFO_FLAGS_HE_MCS;
682 txrate.he_gi = ath12k_he_gi_to_nl80211_he_gi(ts->sgi);
683 break;
684 case HAL_TX_RATE_STATS_PKT_TYPE_11BE:
685 if (ts->mcs > ATH12K_EHT_MCS_MAX) {
686 ath12k_warn(ab, "Invalid EHT mcs index %d\n", ts->mcs);
687 return;
688 }
689
690 txrate.mcs = ts->mcs;
691 txrate.flags = RATE_INFO_FLAGS_EHT_MCS;
692 txrate.eht_gi = ath12k_mac_eht_gi_to_nl80211_eht_gi(ts->sgi);
693 break;
694 default:
695 ath12k_warn(ab, "Invalid tx pkt type: %d\n", ts->pkt_type);
696 return;
697 }
698
699 txrate.bw = ath12k_mac_bw_to_mac80211_bw(ts->bw);
700
701 if (ts->ofdma && ts->pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AX) {
702 txrate.bw = RATE_INFO_BW_HE_RU;
703 ru_tones = ath12k_mac_he_convert_tones_to_ru_tones(ts->tones);
704 txrate.he_ru_alloc =
705 ath12k_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones);
706 }
707
708 if (ts->ofdma && ts->pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11BE) {
709 txrate.bw = RATE_INFO_BW_EHT_RU;
710 txrate.eht_ru_alloc =
711 ath12k_mac_eht_ru_tones_to_nl80211_eht_ru_alloc(ts->tones);
712 }
713
714 spin_lock_bh(&ab->base_lock);
715 arsta->txrate = txrate;
716 spin_unlock_bh(&ab->base_lock);
717 }
718
ath12k_dp_tx_complete_msdu(struct ath12k * ar,struct sk_buff * msdu,struct hal_tx_status * ts)719 static void ath12k_dp_tx_complete_msdu(struct ath12k *ar,
720 struct sk_buff *msdu,
721 struct hal_tx_status *ts)
722 {
723 struct ath12k_base *ab = ar->ab;
724 struct ath12k_hw *ah = ar->ah;
725 struct ieee80211_tx_info *info;
726 struct ath12k_skb_cb *skb_cb;
727
728 if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) {
729 /* Must not happen */
730 return;
731 }
732
733 skb_cb = ATH12K_SKB_CB(msdu);
734
735 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
736 if (skb_cb->paddr_ext_desc)
737 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc,
738 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE);
739
740 rcu_read_lock();
741
742 if (!rcu_dereference(ab->pdevs_active[ar->pdev_idx])) {
743 ieee80211_free_txskb(ah->hw, msdu);
744 goto exit;
745 }
746
747 if (!skb_cb->vif) {
748 ieee80211_free_txskb(ah->hw, msdu);
749 goto exit;
750 }
751
752 info = IEEE80211_SKB_CB(msdu);
753 memset(&info->status, 0, sizeof(info->status));
754
755 /* skip tx rate update from ieee80211_status*/
756 info->status.rates[0].idx = -1;
757
758 switch (ts->status) {
759 case HAL_WBM_TQM_REL_REASON_FRAME_ACKED:
760 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
761 info->flags |= IEEE80211_TX_STAT_ACK;
762 info->status.ack_signal = ts->ack_rssi;
763
764 if (!test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT,
765 ab->wmi_ab.svc_map))
766 info->status.ack_signal += ATH12K_DEFAULT_NOISE_FLOOR;
767
768 info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID;
769 }
770 break;
771 case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX:
772 if (info->flags & IEEE80211_TX_CTL_NO_ACK) {
773 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
774 break;
775 }
776 fallthrough;
777 case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU:
778 case HAL_WBM_TQM_REL_REASON_DROP_THRESHOLD:
779 case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES:
780 /* The failure status is due to internal firmware tx failure
781 * hence drop the frame; do not update the status of frame to
782 * the upper layer
783 */
784 ieee80211_free_txskb(ah->hw, msdu);
785 goto exit;
786 default:
787 ath12k_dbg(ab, ATH12K_DBG_DP_TX, "tx frame is not acked status %d\n",
788 ts->status);
789 break;
790 }
791
792 /* NOTE: Tx rate status reporting. Tx completion status does not have
793 * necessary information (for example nss) to build the tx rate.
794 * Might end up reporting it out-of-band from HTT stats.
795 */
796
797 ath12k_dp_tx_update_txcompl(ar, ts);
798
799 ieee80211_tx_status_skb(ath12k_ar_to_hw(ar), msdu);
800
801 exit:
802 rcu_read_unlock();
803 }
804
ath12k_dp_tx_status_parse(struct ath12k_base * ab,struct hal_wbm_completion_ring_tx * desc,struct hal_tx_status * ts)805 static void ath12k_dp_tx_status_parse(struct ath12k_base *ab,
806 struct hal_wbm_completion_ring_tx *desc,
807 struct hal_tx_status *ts)
808 {
809 u32 info0 = le32_to_cpu(desc->rate_stats.info0);
810
811 ts->buf_rel_source =
812 le32_get_bits(desc->info0, HAL_WBM_COMPL_TX_INFO0_REL_SRC_MODULE);
813 if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW &&
814 ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)
815 return;
816
817 if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW)
818 return;
819
820 ts->status = le32_get_bits(desc->info0,
821 HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON);
822
823 ts->ppdu_id = le32_get_bits(desc->info1,
824 HAL_WBM_COMPL_TX_INFO1_TQM_STATUS_NUMBER);
825
826 ts->peer_id = le32_get_bits(desc->info3, HAL_WBM_COMPL_TX_INFO3_PEER_ID);
827
828 if (info0 & HAL_TX_RATE_STATS_INFO0_VALID) {
829 ts->pkt_type = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_PKT_TYPE);
830 ts->mcs = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_MCS);
831 ts->sgi = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_SGI);
832 ts->bw = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_BW);
833 ts->tones = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_TONES_IN_RU);
834 ts->ofdma = u32_get_bits(info0, HAL_TX_RATE_STATS_INFO0_OFDMA_TX);
835 }
836 }
837
ath12k_dp_tx_completion_handler(struct ath12k_base * ab,int ring_id)838 void ath12k_dp_tx_completion_handler(struct ath12k_base *ab, int ring_id)
839 {
840 struct ath12k *ar;
841 struct ath12k_dp *dp = &ab->dp;
842 int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id;
843 struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id];
844 struct ath12k_tx_desc_info *tx_desc = NULL;
845 struct sk_buff *msdu;
846 struct hal_tx_status ts = { 0 };
847 struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id];
848 struct hal_wbm_release_ring *desc;
849 u8 mac_id, pdev_id;
850 u64 desc_va;
851
852 spin_lock_bh(&status_ring->lock);
853
854 ath12k_hal_srng_access_begin(ab, status_ring);
855
856 while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) != tx_ring->tx_status_tail) {
857 desc = ath12k_hal_srng_dst_get_next_entry(ab, status_ring);
858 if (!desc)
859 break;
860
861 memcpy(&tx_ring->tx_status[tx_ring->tx_status_head],
862 desc, sizeof(*desc));
863 tx_ring->tx_status_head =
864 ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head);
865 }
866
867 if (ath12k_hal_srng_dst_peek(ab, status_ring) &&
868 (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) == tx_ring->tx_status_tail)) {
869 /* TODO: Process pending tx_status messages when kfifo_is_full() */
870 ath12k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n");
871 }
872
873 ath12k_hal_srng_access_end(ab, status_ring);
874
875 spin_unlock_bh(&status_ring->lock);
876
877 while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) {
878 struct hal_wbm_completion_ring_tx *tx_status;
879 u32 desc_id;
880
881 tx_ring->tx_status_tail =
882 ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail);
883 tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail];
884 ath12k_dp_tx_status_parse(ab, tx_status, &ts);
885
886 if (le32_get_bits(tx_status->info0, HAL_WBM_COMPL_TX_INFO0_CC_DONE)) {
887 /* HW done cookie conversion */
888 desc_va = ((u64)le32_to_cpu(tx_status->buf_va_hi) << 32 |
889 le32_to_cpu(tx_status->buf_va_lo));
890 tx_desc = (struct ath12k_tx_desc_info *)((unsigned long)desc_va);
891 } else {
892 /* SW does cookie conversion to VA */
893 desc_id = le32_get_bits(tx_status->buf_va_hi,
894 BUFFER_ADDR_INFO1_SW_COOKIE);
895
896 tx_desc = ath12k_dp_get_tx_desc(ab, desc_id);
897 }
898 if (!tx_desc) {
899 ath12k_warn(ab, "unable to retrieve tx_desc!");
900 continue;
901 }
902
903 msdu = tx_desc->skb;
904 mac_id = tx_desc->mac_id;
905
906 /* Release descriptor as soon as extracting necessary info
907 * to reduce contention
908 */
909 ath12k_dp_tx_release_txbuf(dp, tx_desc, tx_desc->pool_id);
910 if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) {
911 ath12k_dp_tx_process_htt_tx_complete(ab,
912 (void *)tx_status,
913 mac_id, msdu,
914 tx_ring);
915 continue;
916 }
917
918 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id);
919 ar = ab->pdevs[pdev_id].ar;
920
921 if (atomic_dec_and_test(&ar->dp.num_tx_pending))
922 wake_up(&ar->dp.tx_empty_waitq);
923
924 ath12k_dp_tx_complete_msdu(ar, msdu, &ts);
925 }
926 }
927
928 static int
ath12k_dp_tx_get_ring_id_type(struct ath12k_base * ab,int mac_id,u32 ring_id,enum hal_ring_type ring_type,enum htt_srng_ring_type * htt_ring_type,enum htt_srng_ring_id * htt_ring_id)929 ath12k_dp_tx_get_ring_id_type(struct ath12k_base *ab,
930 int mac_id, u32 ring_id,
931 enum hal_ring_type ring_type,
932 enum htt_srng_ring_type *htt_ring_type,
933 enum htt_srng_ring_id *htt_ring_id)
934 {
935 int ret = 0;
936
937 switch (ring_type) {
938 case HAL_RXDMA_BUF:
939 /* for some targets, host fills rx buffer to fw and fw fills to
940 * rxbuf ring for each rxdma
941 */
942 if (!ab->hw_params->rx_mac_buf_ring) {
943 if (!(ring_id == HAL_SRNG_SW2RXDMA_BUF0 ||
944 ring_id == HAL_SRNG_SW2RXDMA_BUF1)) {
945 ret = -EINVAL;
946 }
947 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING;
948 *htt_ring_type = HTT_SW_TO_HW_RING;
949 } else {
950 if (ring_id == HAL_SRNG_SW2RXDMA_BUF0) {
951 *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING;
952 *htt_ring_type = HTT_SW_TO_SW_RING;
953 } else {
954 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING;
955 *htt_ring_type = HTT_SW_TO_HW_RING;
956 }
957 }
958 break;
959 case HAL_RXDMA_DST:
960 *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING;
961 *htt_ring_type = HTT_HW_TO_SW_RING;
962 break;
963 case HAL_RXDMA_MONITOR_BUF:
964 *htt_ring_id = HTT_RX_MON_HOST2MON_BUF_RING;
965 *htt_ring_type = HTT_SW_TO_HW_RING;
966 break;
967 case HAL_RXDMA_MONITOR_STATUS:
968 *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING;
969 *htt_ring_type = HTT_SW_TO_HW_RING;
970 break;
971 case HAL_RXDMA_MONITOR_DST:
972 *htt_ring_id = HTT_RX_MON_MON2HOST_DEST_RING;
973 *htt_ring_type = HTT_HW_TO_SW_RING;
974 break;
975 case HAL_RXDMA_MONITOR_DESC:
976 *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING;
977 *htt_ring_type = HTT_SW_TO_HW_RING;
978 break;
979 default:
980 ath12k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type);
981 ret = -EINVAL;
982 }
983 return ret;
984 }
985
ath12k_dp_tx_htt_srng_setup(struct ath12k_base * ab,u32 ring_id,int mac_id,enum hal_ring_type ring_type)986 int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id,
987 int mac_id, enum hal_ring_type ring_type)
988 {
989 struct htt_srng_setup_cmd *cmd;
990 struct hal_srng *srng = &ab->hal.srng_list[ring_id];
991 struct hal_srng_params params;
992 struct sk_buff *skb;
993 u32 ring_entry_sz;
994 int len = sizeof(*cmd);
995 dma_addr_t hp_addr, tp_addr;
996 enum htt_srng_ring_type htt_ring_type;
997 enum htt_srng_ring_id htt_ring_id;
998 int ret;
999
1000 skb = ath12k_htc_alloc_skb(ab, len);
1001 if (!skb)
1002 return -ENOMEM;
1003
1004 memset(¶ms, 0, sizeof(params));
1005 ath12k_hal_srng_get_params(ab, srng, ¶ms);
1006
1007 hp_addr = ath12k_hal_srng_get_hp_addr(ab, srng);
1008 tp_addr = ath12k_hal_srng_get_tp_addr(ab, srng);
1009
1010 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
1011 ring_type, &htt_ring_type,
1012 &htt_ring_id);
1013 if (ret)
1014 goto err_free;
1015
1016 skb_put(skb, len);
1017 cmd = (struct htt_srng_setup_cmd *)skb->data;
1018 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_SRING_SETUP,
1019 HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE);
1020 if (htt_ring_type == HTT_SW_TO_HW_RING ||
1021 htt_ring_type == HTT_HW_TO_SW_RING)
1022 cmd->info0 |= le32_encode_bits(DP_SW2HW_MACID(mac_id),
1023 HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID);
1024 else
1025 cmd->info0 |= le32_encode_bits(mac_id,
1026 HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID);
1027 cmd->info0 |= le32_encode_bits(htt_ring_type,
1028 HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE);
1029 cmd->info0 |= le32_encode_bits(htt_ring_id,
1030 HTT_SRNG_SETUP_CMD_INFO0_RING_ID);
1031
1032 cmd->ring_base_addr_lo = cpu_to_le32(params.ring_base_paddr &
1033 HAL_ADDR_LSB_REG_MASK);
1034
1035 cmd->ring_base_addr_hi = cpu_to_le32((u64)params.ring_base_paddr >>
1036 HAL_ADDR_MSB_REG_SHIFT);
1037
1038 ret = ath12k_hal_srng_get_entrysize(ab, ring_type);
1039 if (ret < 0)
1040 goto err_free;
1041
1042 ring_entry_sz = ret;
1043
1044 ring_entry_sz >>= 2;
1045 cmd->info1 = le32_encode_bits(ring_entry_sz,
1046 HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE);
1047 cmd->info1 |= le32_encode_bits(params.num_entries * ring_entry_sz,
1048 HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE);
1049 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP),
1050 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP);
1051 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP),
1052 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP);
1053 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP),
1054 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP);
1055 if (htt_ring_type == HTT_SW_TO_HW_RING)
1056 cmd->info1 |= cpu_to_le32(HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS);
1057
1058 cmd->ring_head_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(hp_addr));
1059 cmd->ring_head_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(hp_addr));
1060
1061 cmd->ring_tail_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(tp_addr));
1062 cmd->ring_tail_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(tp_addr));
1063
1064 cmd->ring_msi_addr_lo = cpu_to_le32(lower_32_bits(params.msi_addr));
1065 cmd->ring_msi_addr_hi = cpu_to_le32(upper_32_bits(params.msi_addr));
1066 cmd->msi_data = cpu_to_le32(params.msi_data);
1067
1068 cmd->intr_info =
1069 le32_encode_bits(params.intr_batch_cntr_thres_entries * ring_entry_sz,
1070 HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH);
1071 cmd->intr_info |=
1072 le32_encode_bits(params.intr_timer_thres_us >> 3,
1073 HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH);
1074
1075 cmd->info2 = 0;
1076 if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) {
1077 cmd->info2 = le32_encode_bits(params.low_threshold,
1078 HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH);
1079 }
1080
1081 ath12k_dbg(ab, ATH12K_DBG_HAL,
1082 "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n",
1083 __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi,
1084 cmd->msi_data);
1085
1086 ath12k_dbg(ab, ATH12K_DBG_HAL,
1087 "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n",
1088 ring_id, ring_type, cmd->intr_info, cmd->info2);
1089
1090 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb);
1091 if (ret)
1092 goto err_free;
1093
1094 return 0;
1095
1096 err_free:
1097 dev_kfree_skb_any(skb);
1098
1099 return ret;
1100 }
1101
1102 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ)
1103
ath12k_dp_tx_htt_h2t_ver_req_msg(struct ath12k_base * ab)1104 int ath12k_dp_tx_htt_h2t_ver_req_msg(struct ath12k_base *ab)
1105 {
1106 struct ath12k_dp *dp = &ab->dp;
1107 struct sk_buff *skb;
1108 struct htt_ver_req_cmd *cmd;
1109 int len = sizeof(*cmd);
1110 int ret;
1111
1112 init_completion(&dp->htt_tgt_version_received);
1113
1114 skb = ath12k_htc_alloc_skb(ab, len);
1115 if (!skb)
1116 return -ENOMEM;
1117
1118 skb_put(skb, len);
1119 cmd = (struct htt_ver_req_cmd *)skb->data;
1120 cmd->ver_reg_info = le32_encode_bits(HTT_H2T_MSG_TYPE_VERSION_REQ,
1121 HTT_OPTION_TAG);
1122
1123 cmd->tcl_metadata_version = le32_encode_bits(HTT_TAG_TCL_METADATA_VERSION,
1124 HTT_OPTION_TAG) |
1125 le32_encode_bits(HTT_TCL_METADATA_VER_SZ,
1126 HTT_OPTION_LEN) |
1127 le32_encode_bits(HTT_OPTION_TCL_METADATA_VER_V2,
1128 HTT_OPTION_VALUE);
1129
1130 ret = ath12k_htc_send(&ab->htc, dp->eid, skb);
1131 if (ret) {
1132 dev_kfree_skb_any(skb);
1133 return ret;
1134 }
1135
1136 ret = wait_for_completion_timeout(&dp->htt_tgt_version_received,
1137 HTT_TARGET_VERSION_TIMEOUT_HZ);
1138 if (ret == 0) {
1139 ath12k_warn(ab, "htt target version request timed out\n");
1140 return -ETIMEDOUT;
1141 }
1142
1143 if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) {
1144 ath12k_err(ab, "unsupported htt major version %d supported version is %d\n",
1145 dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR);
1146 return -EOPNOTSUPP;
1147 }
1148
1149 return 0;
1150 }
1151
ath12k_dp_tx_htt_h2t_ppdu_stats_req(struct ath12k * ar,u32 mask)1152 int ath12k_dp_tx_htt_h2t_ppdu_stats_req(struct ath12k *ar, u32 mask)
1153 {
1154 struct ath12k_base *ab = ar->ab;
1155 struct ath12k_dp *dp = &ab->dp;
1156 struct sk_buff *skb;
1157 struct htt_ppdu_stats_cfg_cmd *cmd;
1158 int len = sizeof(*cmd);
1159 u8 pdev_mask;
1160 int ret;
1161 int i;
1162
1163 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
1164 skb = ath12k_htc_alloc_skb(ab, len);
1165 if (!skb)
1166 return -ENOMEM;
1167
1168 skb_put(skb, len);
1169 cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data;
1170 cmd->msg = le32_encode_bits(HTT_H2T_MSG_TYPE_PPDU_STATS_CFG,
1171 HTT_PPDU_STATS_CFG_MSG_TYPE);
1172
1173 pdev_mask = 1 << (i + 1);
1174 cmd->msg |= le32_encode_bits(pdev_mask, HTT_PPDU_STATS_CFG_PDEV_ID);
1175 cmd->msg |= le32_encode_bits(mask, HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK);
1176
1177 ret = ath12k_htc_send(&ab->htc, dp->eid, skb);
1178 if (ret) {
1179 dev_kfree_skb_any(skb);
1180 return ret;
1181 }
1182 }
1183
1184 return 0;
1185 }
1186
ath12k_dp_tx_htt_rx_filter_setup(struct ath12k_base * ab,u32 ring_id,int mac_id,enum hal_ring_type ring_type,int rx_buf_size,struct htt_rx_ring_tlv_filter * tlv_filter)1187 int ath12k_dp_tx_htt_rx_filter_setup(struct ath12k_base *ab, u32 ring_id,
1188 int mac_id, enum hal_ring_type ring_type,
1189 int rx_buf_size,
1190 struct htt_rx_ring_tlv_filter *tlv_filter)
1191 {
1192 struct htt_rx_ring_selection_cfg_cmd *cmd;
1193 struct hal_srng *srng = &ab->hal.srng_list[ring_id];
1194 struct hal_srng_params params;
1195 struct sk_buff *skb;
1196 int len = sizeof(*cmd);
1197 enum htt_srng_ring_type htt_ring_type;
1198 enum htt_srng_ring_id htt_ring_id;
1199 int ret;
1200
1201 skb = ath12k_htc_alloc_skb(ab, len);
1202 if (!skb)
1203 return -ENOMEM;
1204
1205 memset(¶ms, 0, sizeof(params));
1206 ath12k_hal_srng_get_params(ab, srng, ¶ms);
1207
1208 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
1209 ring_type, &htt_ring_type,
1210 &htt_ring_id);
1211 if (ret)
1212 goto err_free;
1213
1214 skb_put(skb, len);
1215 cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data;
1216 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG,
1217 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE);
1218 if (htt_ring_type == HTT_SW_TO_HW_RING ||
1219 htt_ring_type == HTT_HW_TO_SW_RING)
1220 cmd->info0 |=
1221 le32_encode_bits(DP_SW2HW_MACID(mac_id),
1222 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);
1223 else
1224 cmd->info0 |=
1225 le32_encode_bits(mac_id,
1226 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);
1227 cmd->info0 |= le32_encode_bits(htt_ring_id,
1228 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID);
1229 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP),
1230 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS);
1231 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP),
1232 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS);
1233 cmd->info0 |= le32_encode_bits(tlv_filter->offset_valid,
1234 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_OFFSET_VALID);
1235 cmd->info0 |=
1236 le32_encode_bits(tlv_filter->drop_threshold_valid,
1237 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_DROP_THRES_VAL);
1238 cmd->info0 |= le32_encode_bits(!tlv_filter->rxmon_disable,
1239 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_EN_RXMON);
1240
1241 cmd->info1 = le32_encode_bits(rx_buf_size,
1242 HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE);
1243 cmd->info1 |= le32_encode_bits(tlv_filter->conf_len_mgmt,
1244 HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT);
1245 cmd->info1 |= le32_encode_bits(tlv_filter->conf_len_ctrl,
1246 HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL);
1247 cmd->info1 |= le32_encode_bits(tlv_filter->conf_len_data,
1248 HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA);
1249 cmd->pkt_type_en_flags0 = cpu_to_le32(tlv_filter->pkt_filter_flags0);
1250 cmd->pkt_type_en_flags1 = cpu_to_le32(tlv_filter->pkt_filter_flags1);
1251 cmd->pkt_type_en_flags2 = cpu_to_le32(tlv_filter->pkt_filter_flags2);
1252 cmd->pkt_type_en_flags3 = cpu_to_le32(tlv_filter->pkt_filter_flags3);
1253 cmd->rx_filter_tlv = cpu_to_le32(tlv_filter->rx_filter);
1254
1255 cmd->info2 = le32_encode_bits(tlv_filter->rx_drop_threshold,
1256 HTT_RX_RING_SELECTION_CFG_CMD_INFO2_DROP_THRESHOLD);
1257 cmd->info2 |=
1258 le32_encode_bits(tlv_filter->enable_log_mgmt_type,
1259 HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_MGMT_TYPE);
1260 cmd->info2 |=
1261 le32_encode_bits(tlv_filter->enable_log_ctrl_type,
1262 HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_CTRL_TYPE);
1263 cmd->info2 |=
1264 le32_encode_bits(tlv_filter->enable_log_data_type,
1265 HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_DATA_TYPE);
1266
1267 cmd->info3 =
1268 le32_encode_bits(tlv_filter->enable_rx_tlv_offset,
1269 HTT_RX_RING_SELECTION_CFG_CMD_INFO3_EN_TLV_PKT_OFFSET);
1270 cmd->info3 |=
1271 le32_encode_bits(tlv_filter->rx_tlv_offset,
1272 HTT_RX_RING_SELECTION_CFG_CMD_INFO3_PKT_TLV_OFFSET);
1273
1274 if (tlv_filter->offset_valid) {
1275 cmd->rx_packet_offset =
1276 le32_encode_bits(tlv_filter->rx_packet_offset,
1277 HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET);
1278
1279 cmd->rx_packet_offset |=
1280 le32_encode_bits(tlv_filter->rx_header_offset,
1281 HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET);
1282
1283 cmd->rx_mpdu_offset =
1284 le32_encode_bits(tlv_filter->rx_mpdu_end_offset,
1285 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET);
1286
1287 cmd->rx_mpdu_offset |=
1288 le32_encode_bits(tlv_filter->rx_mpdu_start_offset,
1289 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET);
1290
1291 cmd->rx_msdu_offset =
1292 le32_encode_bits(tlv_filter->rx_msdu_end_offset,
1293 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET);
1294
1295 cmd->rx_msdu_offset |=
1296 le32_encode_bits(tlv_filter->rx_msdu_start_offset,
1297 HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET);
1298
1299 cmd->rx_attn_offset =
1300 le32_encode_bits(tlv_filter->rx_attn_offset,
1301 HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET);
1302 }
1303
1304 if (tlv_filter->rx_mpdu_start_wmask > 0 &&
1305 tlv_filter->rx_msdu_end_wmask > 0) {
1306 cmd->info2 |=
1307 le32_encode_bits(true,
1308 HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACT_SET);
1309 cmd->rx_mpdu_start_end_mask =
1310 le32_encode_bits(tlv_filter->rx_mpdu_start_wmask,
1311 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK);
1312 /* mpdu_end is not used for any hardwares so far
1313 * please assign it in future if any chip is
1314 * using through hal ops
1315 */
1316 cmd->rx_mpdu_start_end_mask |=
1317 le32_encode_bits(tlv_filter->rx_mpdu_end_wmask,
1318 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK);
1319 cmd->rx_msdu_end_word_mask =
1320 le32_encode_bits(tlv_filter->rx_msdu_end_wmask,
1321 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK);
1322 }
1323
1324 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb);
1325 if (ret)
1326 goto err_free;
1327
1328 return 0;
1329
1330 err_free:
1331 dev_kfree_skb_any(skb);
1332
1333 return ret;
1334 }
1335
1336 int
ath12k_dp_tx_htt_h2t_ext_stats_req(struct ath12k * ar,u8 type,struct htt_ext_stats_cfg_params * cfg_params,u64 cookie)1337 ath12k_dp_tx_htt_h2t_ext_stats_req(struct ath12k *ar, u8 type,
1338 struct htt_ext_stats_cfg_params *cfg_params,
1339 u64 cookie)
1340 {
1341 struct ath12k_base *ab = ar->ab;
1342 struct ath12k_dp *dp = &ab->dp;
1343 struct sk_buff *skb;
1344 struct htt_ext_stats_cfg_cmd *cmd;
1345 int len = sizeof(*cmd);
1346 int ret;
1347 u32 pdev_id;
1348
1349 skb = ath12k_htc_alloc_skb(ab, len);
1350 if (!skb)
1351 return -ENOMEM;
1352
1353 skb_put(skb, len);
1354
1355 cmd = (struct htt_ext_stats_cfg_cmd *)skb->data;
1356 memset(cmd, 0, sizeof(*cmd));
1357 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG;
1358
1359 pdev_id = ath12k_mac_get_target_pdev_id(ar);
1360 cmd->hdr.pdev_mask = 1 << pdev_id;
1361
1362 cmd->hdr.stats_type = type;
1363 cmd->cfg_param0 = cpu_to_le32(cfg_params->cfg0);
1364 cmd->cfg_param1 = cpu_to_le32(cfg_params->cfg1);
1365 cmd->cfg_param2 = cpu_to_le32(cfg_params->cfg2);
1366 cmd->cfg_param3 = cpu_to_le32(cfg_params->cfg3);
1367 cmd->cookie_lsb = cpu_to_le32(lower_32_bits(cookie));
1368 cmd->cookie_msb = cpu_to_le32(upper_32_bits(cookie));
1369
1370 ret = ath12k_htc_send(&ab->htc, dp->eid, skb);
1371 if (ret) {
1372 ath12k_warn(ab, "failed to send htt type stats request: %d",
1373 ret);
1374 dev_kfree_skb_any(skb);
1375 return ret;
1376 }
1377
1378 return 0;
1379 }
1380
ath12k_dp_tx_htt_monitor_mode_ring_config(struct ath12k * ar,bool reset)1381 int ath12k_dp_tx_htt_monitor_mode_ring_config(struct ath12k *ar, bool reset)
1382 {
1383 struct ath12k_base *ab = ar->ab;
1384 int ret;
1385
1386 ret = ath12k_dp_tx_htt_rx_monitor_mode_ring_config(ar, reset);
1387 if (ret) {
1388 ath12k_err(ab, "failed to setup rx monitor filter %d\n", ret);
1389 return ret;
1390 }
1391
1392 return 0;
1393 }
1394
ath12k_dp_tx_htt_rx_monitor_mode_ring_config(struct ath12k * ar,bool reset)1395 int ath12k_dp_tx_htt_rx_monitor_mode_ring_config(struct ath12k *ar, bool reset)
1396 {
1397 struct ath12k_base *ab = ar->ab;
1398 struct htt_rx_ring_tlv_filter tlv_filter = {0};
1399 int ret, ring_id, i;
1400
1401 tlv_filter.offset_valid = false;
1402
1403 if (!reset) {
1404 tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_DEST_RING;
1405
1406 tlv_filter.drop_threshold_valid = true;
1407 tlv_filter.rx_drop_threshold = HTT_RX_RING_TLV_DROP_THRESHOLD_VALUE;
1408
1409 tlv_filter.enable_log_mgmt_type = true;
1410 tlv_filter.enable_log_ctrl_type = true;
1411 tlv_filter.enable_log_data_type = true;
1412
1413 tlv_filter.conf_len_ctrl = HTT_RX_RING_DEFAULT_DMA_LENGTH;
1414 tlv_filter.conf_len_mgmt = HTT_RX_RING_DEFAULT_DMA_LENGTH;
1415 tlv_filter.conf_len_data = HTT_RX_RING_DEFAULT_DMA_LENGTH;
1416
1417 tlv_filter.enable_rx_tlv_offset = true;
1418 tlv_filter.rx_tlv_offset = HTT_RX_RING_PKT_TLV_OFFSET;
1419
1420 tlv_filter.pkt_filter_flags0 =
1421 HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 |
1422 HTT_RX_MON_MO_MGMT_FILTER_FLAGS0;
1423 tlv_filter.pkt_filter_flags1 =
1424 HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 |
1425 HTT_RX_MON_MO_MGMT_FILTER_FLAGS1;
1426 tlv_filter.pkt_filter_flags2 =
1427 HTT_RX_MON_FP_CTRL_FILTER_FLASG2 |
1428 HTT_RX_MON_MO_CTRL_FILTER_FLASG2;
1429 tlv_filter.pkt_filter_flags3 =
1430 HTT_RX_MON_FP_CTRL_FILTER_FLASG3 |
1431 HTT_RX_MON_MO_CTRL_FILTER_FLASG3 |
1432 HTT_RX_MON_FP_DATA_FILTER_FLASG3 |
1433 HTT_RX_MON_MO_DATA_FILTER_FLASG3;
1434 }
1435
1436 if (ab->hw_params->rxdma1_enable) {
1437 for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
1438 ring_id = ar->dp.rxdma_mon_dst_ring[i].ring_id;
1439 ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id,
1440 ar->dp.mac_id + i,
1441 HAL_RXDMA_MONITOR_DST,
1442 DP_RXDMA_REFILL_RING_SIZE,
1443 &tlv_filter);
1444 if (ret) {
1445 ath12k_err(ab,
1446 "failed to setup filter for monitor buf %d\n",
1447 ret);
1448 return ret;
1449 }
1450 }
1451 }
1452
1453 return 0;
1454 }
1455
ath12k_dp_tx_htt_tx_filter_setup(struct ath12k_base * ab,u32 ring_id,int mac_id,enum hal_ring_type ring_type,int tx_buf_size,struct htt_tx_ring_tlv_filter * htt_tlv_filter)1456 int ath12k_dp_tx_htt_tx_filter_setup(struct ath12k_base *ab, u32 ring_id,
1457 int mac_id, enum hal_ring_type ring_type,
1458 int tx_buf_size,
1459 struct htt_tx_ring_tlv_filter *htt_tlv_filter)
1460 {
1461 struct htt_tx_ring_selection_cfg_cmd *cmd;
1462 struct hal_srng *srng = &ab->hal.srng_list[ring_id];
1463 struct hal_srng_params params;
1464 struct sk_buff *skb;
1465 int len = sizeof(*cmd);
1466 enum htt_srng_ring_type htt_ring_type;
1467 enum htt_srng_ring_id htt_ring_id;
1468 int ret;
1469
1470 skb = ath12k_htc_alloc_skb(ab, len);
1471 if (!skb)
1472 return -ENOMEM;
1473
1474 memset(¶ms, 0, sizeof(params));
1475 ath12k_hal_srng_get_params(ab, srng, ¶ms);
1476
1477 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
1478 ring_type, &htt_ring_type,
1479 &htt_ring_id);
1480
1481 if (ret)
1482 goto err_free;
1483
1484 skb_put(skb, len);
1485 cmd = (struct htt_tx_ring_selection_cfg_cmd *)skb->data;
1486 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_TX_MONITOR_CFG,
1487 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE);
1488 if (htt_ring_type == HTT_SW_TO_HW_RING ||
1489 htt_ring_type == HTT_HW_TO_SW_RING)
1490 cmd->info0 |=
1491 le32_encode_bits(DP_SW2HW_MACID(mac_id),
1492 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);
1493 else
1494 cmd->info0 |=
1495 le32_encode_bits(mac_id,
1496 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);
1497 cmd->info0 |= le32_encode_bits(htt_ring_id,
1498 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID);
1499 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP),
1500 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS);
1501 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP),
1502 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS);
1503
1504 cmd->info1 |=
1505 le32_encode_bits(tx_buf_size,
1506 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE);
1507
1508 if (htt_tlv_filter->tx_mon_mgmt_filter) {
1509 cmd->info1 |=
1510 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT,
1511 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE);
1512 cmd->info1 |=
1513 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len,
1514 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT);
1515 cmd->info2 |=
1516 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT,
1517 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG);
1518 }
1519
1520 if (htt_tlv_filter->tx_mon_data_filter) {
1521 cmd->info1 |=
1522 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL,
1523 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE);
1524 cmd->info1 |=
1525 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len,
1526 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL);
1527 cmd->info2 |=
1528 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL,
1529 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG);
1530 }
1531
1532 if (htt_tlv_filter->tx_mon_ctrl_filter) {
1533 cmd->info1 |=
1534 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA,
1535 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE);
1536 cmd->info1 |=
1537 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len,
1538 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA);
1539 cmd->info2 |=
1540 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA,
1541 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG);
1542 }
1543
1544 cmd->tlv_filter_mask_in0 =
1545 cpu_to_le32(htt_tlv_filter->tx_mon_downstream_tlv_flags);
1546 cmd->tlv_filter_mask_in1 =
1547 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags0);
1548 cmd->tlv_filter_mask_in2 =
1549 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags1);
1550 cmd->tlv_filter_mask_in3 =
1551 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags2);
1552
1553 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb);
1554 if (ret)
1555 goto err_free;
1556
1557 return 0;
1558
1559 err_free:
1560 dev_kfree_skb_any(skb);
1561 return ret;
1562 }
1563