1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022, 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include "dp_rx.h"
8 #include "debug.h"
9 #include "hif.h"
10
11 const struct ce_attr ath12k_host_ce_config_qcn9274[] = {
12 /* CE0: host->target HTC control and raw streams */
13 {
14 .flags = CE_ATTR_FLAGS,
15 .src_nentries = 16,
16 .src_sz_max = 2048,
17 .dest_nentries = 0,
18 },
19
20 /* CE1: target->host HTT + HTC control */
21 {
22 .flags = CE_ATTR_FLAGS,
23 .src_nentries = 0,
24 .src_sz_max = 2048,
25 .dest_nentries = 512,
26 .recv_cb = ath12k_htc_rx_completion_handler,
27 },
28
29 /* CE2: target->host WMI */
30 {
31 .flags = CE_ATTR_FLAGS,
32 .src_nentries = 0,
33 .src_sz_max = 2048,
34 .dest_nentries = 128,
35 .recv_cb = ath12k_htc_rx_completion_handler,
36 },
37
38 /* CE3: host->target WMI (mac0) */
39 {
40 .flags = CE_ATTR_FLAGS,
41 .src_nentries = 32,
42 .src_sz_max = 2048,
43 .dest_nentries = 0,
44 },
45
46 /* CE4: host->target HTT */
47 {
48 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
49 .src_nentries = 2048,
50 .src_sz_max = 256,
51 .dest_nentries = 0,
52 },
53
54 /* CE5: target->host pktlog */
55 {
56 .flags = CE_ATTR_FLAGS,
57 .src_nentries = 0,
58 .src_sz_max = 2048,
59 .dest_nentries = 512,
60 .recv_cb = ath12k_dp_htt_htc_t2h_msg_handler,
61 },
62
63 /* CE6: target autonomous hif_memcpy */
64 {
65 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
66 .src_nentries = 0,
67 .src_sz_max = 0,
68 .dest_nentries = 0,
69 },
70
71 /* CE7: host->target WMI (mac1) */
72 {
73 .flags = CE_ATTR_FLAGS,
74 .src_nentries = 32,
75 .src_sz_max = 2048,
76 .dest_nentries = 0,
77 },
78
79 /* CE8: target autonomous hif_memcpy */
80 {
81 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
82 .src_nentries = 0,
83 .src_sz_max = 0,
84 .dest_nentries = 0,
85 },
86
87 /* CE9: MHI */
88 {
89 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
90 .src_nentries = 0,
91 .src_sz_max = 0,
92 .dest_nentries = 0,
93 },
94
95 /* CE10: MHI */
96 {
97 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
98 .src_nentries = 0,
99 .src_sz_max = 0,
100 .dest_nentries = 0,
101 },
102
103 /* CE11: MHI */
104 {
105 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
106 .src_nentries = 0,
107 .src_sz_max = 0,
108 .dest_nentries = 0,
109 },
110
111 /* CE12: CV Prefetch */
112 {
113 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
114 .src_nentries = 0,
115 .src_sz_max = 0,
116 .dest_nentries = 0,
117 },
118
119 /* CE13: CV Prefetch */
120 {
121 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
122 .src_nentries = 0,
123 .src_sz_max = 0,
124 .dest_nentries = 0,
125 },
126
127 /* CE14: target->host dbg log */
128 {
129 .flags = CE_ATTR_FLAGS,
130 .src_nentries = 0,
131 .src_sz_max = 2048,
132 .dest_nentries = 512,
133 .recv_cb = ath12k_htc_rx_completion_handler,
134 },
135
136 /* CE15: reserved for future use */
137 {
138 .flags = (CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
139 .src_nentries = 0,
140 .src_sz_max = 0,
141 .dest_nentries = 0,
142 },
143 };
144
145 const struct ce_attr ath12k_host_ce_config_wcn7850[] = {
146 /* CE0: host->target HTC control and raw streams */
147 {
148 .flags = CE_ATTR_FLAGS,
149 .src_nentries = 16,
150 .src_sz_max = 2048,
151 .dest_nentries = 0,
152 },
153
154 /* CE1: target->host HTT + HTC control */
155 {
156 .flags = CE_ATTR_FLAGS,
157 .src_nentries = 0,
158 .src_sz_max = 2048,
159 .dest_nentries = 512,
160 .recv_cb = ath12k_htc_rx_completion_handler,
161 },
162
163 /* CE2: target->host WMI */
164 {
165 .flags = CE_ATTR_FLAGS,
166 .src_nentries = 0,
167 .src_sz_max = 2048,
168 .dest_nentries = 64,
169 .recv_cb = ath12k_htc_rx_completion_handler,
170 },
171
172 /* CE3: host->target WMI (mac0) */
173 {
174 .flags = CE_ATTR_FLAGS,
175 .src_nentries = 32,
176 .src_sz_max = 2048,
177 .dest_nentries = 0,
178 },
179
180 /* CE4: host->target HTT */
181 {
182 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
183 .src_nentries = 2048,
184 .src_sz_max = 256,
185 .dest_nentries = 0,
186 },
187
188 /* CE5: target->host pktlog */
189 {
190 .flags = CE_ATTR_FLAGS,
191 .src_nentries = 0,
192 .src_sz_max = 0,
193 .dest_nentries = 0,
194 },
195
196 /* CE6: target autonomous hif_memcpy */
197 {
198 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
199 .src_nentries = 0,
200 .src_sz_max = 0,
201 .dest_nentries = 0,
202 },
203
204 /* CE7: host->target WMI (mac1) */
205 {
206 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
207 .src_nentries = 0,
208 .src_sz_max = 2048,
209 .dest_nentries = 0,
210 },
211
212 /* CE8: target autonomous hif_memcpy */
213 {
214 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
215 .src_nentries = 0,
216 .src_sz_max = 0,
217 .dest_nentries = 0,
218 },
219
220 };
221
222 const struct ce_attr ath12k_host_ce_config_ipq5332[] = {
223 /* CE0: host->target HTC control and raw streams */
224 {
225 .flags = CE_ATTR_FLAGS,
226 .src_nentries = 16,
227 .src_sz_max = 2048,
228 .dest_nentries = 0,
229 },
230 /* CE1: target->host HTT + HTC control */
231 {
232 .flags = CE_ATTR_FLAGS,
233 .src_nentries = 0,
234 .src_sz_max = 2048,
235 .dest_nentries = 512,
236 .recv_cb = ath12k_htc_rx_completion_handler,
237 },
238 /* CE2: target->host WMI */
239 {
240 .flags = CE_ATTR_FLAGS,
241 .src_nentries = 0,
242 .src_sz_max = 2048,
243 .dest_nentries = 128,
244 .recv_cb = ath12k_htc_rx_completion_handler,
245 },
246 /* CE3: host->target WMI */
247 {
248 .flags = CE_ATTR_FLAGS,
249 .src_nentries = 32,
250 .src_sz_max = 2048,
251 .dest_nentries = 0,
252 },
253 /* CE4: host->target HTT */
254 {
255 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
256 .src_nentries = 2048,
257 .src_sz_max = 256,
258 .dest_nentries = 0,
259 },
260 /* CE5: target -> host PKTLOG */
261 {
262 .flags = CE_ATTR_FLAGS,
263 .src_nentries = 0,
264 .src_sz_max = 2048,
265 .dest_nentries = 512,
266 .recv_cb = ath12k_dp_htt_htc_t2h_msg_handler,
267 },
268 /* CE6: Target autonomous HIF_memcpy */
269 {
270 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
271 .src_nentries = 0,
272 .src_sz_max = 0,
273 .dest_nentries = 0,
274 },
275 /* CE7: CV Prefetch */
276 {
277 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
278 .src_nentries = 0,
279 .src_sz_max = 0,
280 .dest_nentries = 0,
281 },
282 /* CE8: Target HIF memcpy (Generic HIF memcypy) */
283 {
284 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
285 .src_nentries = 0,
286 .src_sz_max = 0,
287 .dest_nentries = 0,
288 },
289 /* CE9: WMI logging/CFR/Spectral/Radar */
290 {
291 .flags = CE_ATTR_FLAGS,
292 .src_nentries = 0,
293 .src_sz_max = 2048,
294 .dest_nentries = 128,
295 },
296 /* CE10: Unused */
297 {
298 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
299 .src_nentries = 0,
300 .src_sz_max = 0,
301 .dest_nentries = 0,
302 },
303 /* CE11: Unused */
304 {
305 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
306 .src_nentries = 0,
307 .src_sz_max = 0,
308 .dest_nentries = 0,
309 },
310 };
311
ath12k_ce_rx_buf_enqueue_pipe(struct ath12k_ce_pipe * pipe,struct sk_buff * skb,dma_addr_t paddr)312 static int ath12k_ce_rx_buf_enqueue_pipe(struct ath12k_ce_pipe *pipe,
313 struct sk_buff *skb, dma_addr_t paddr)
314 {
315 struct ath12k_base *ab = pipe->ab;
316 struct ath12k_ce_ring *ring = pipe->dest_ring;
317 struct hal_srng *srng;
318 unsigned int write_index;
319 unsigned int nentries_mask = ring->nentries_mask;
320 struct hal_ce_srng_dest_desc *desc;
321 int ret;
322
323 lockdep_assert_held(&ab->ce.ce_lock);
324
325 write_index = ring->write_index;
326
327 srng = &ab->hal.srng_list[ring->hal_ring_id];
328
329 spin_lock_bh(&srng->lock);
330
331 ath12k_hal_srng_access_begin(ab, srng);
332
333 if (unlikely(ath12k_hal_srng_src_num_free(ab, srng, false) < 1)) {
334 ret = -ENOSPC;
335 goto exit;
336 }
337
338 desc = ath12k_hal_srng_src_get_next_entry(ab, srng);
339 if (!desc) {
340 ret = -ENOSPC;
341 goto exit;
342 }
343
344 ath12k_hal_ce_dst_set_desc(desc, paddr);
345
346 ring->skb[write_index] = skb;
347 write_index = CE_RING_IDX_INCR(nentries_mask, write_index);
348 ring->write_index = write_index;
349
350 pipe->rx_buf_needed--;
351
352 ret = 0;
353 exit:
354 ath12k_hal_srng_access_end(ab, srng);
355
356 spin_unlock_bh(&srng->lock);
357
358 return ret;
359 }
360
ath12k_ce_rx_post_pipe(struct ath12k_ce_pipe * pipe)361 static int ath12k_ce_rx_post_pipe(struct ath12k_ce_pipe *pipe)
362 {
363 struct ath12k_base *ab = pipe->ab;
364 struct sk_buff *skb;
365 dma_addr_t paddr;
366 int ret = 0;
367
368 if (!(pipe->dest_ring || pipe->status_ring))
369 return 0;
370
371 spin_lock_bh(&ab->ce.ce_lock);
372 while (pipe->rx_buf_needed) {
373 skb = dev_alloc_skb(pipe->buf_sz);
374 if (!skb) {
375 ret = -ENOMEM;
376 goto exit;
377 }
378
379 WARN_ON_ONCE(!IS_ALIGNED((unsigned long)skb->data, 4));
380
381 paddr = dma_map_single(ab->dev, skb->data,
382 skb->len + skb_tailroom(skb),
383 DMA_FROM_DEVICE);
384 if (unlikely(dma_mapping_error(ab->dev, paddr))) {
385 ath12k_warn(ab, "failed to dma map ce rx buf\n");
386 dev_kfree_skb_any(skb);
387 ret = -EIO;
388 goto exit;
389 }
390
391 ATH12K_SKB_RXCB(skb)->paddr = paddr;
392
393 ret = ath12k_ce_rx_buf_enqueue_pipe(pipe, skb, paddr);
394 if (ret) {
395 ath12k_warn(ab, "failed to enqueue rx buf: %d\n", ret);
396 dma_unmap_single(ab->dev, paddr,
397 skb->len + skb_tailroom(skb),
398 DMA_FROM_DEVICE);
399 dev_kfree_skb_any(skb);
400 goto exit;
401 }
402 }
403
404 exit:
405 spin_unlock_bh(&ab->ce.ce_lock);
406 return ret;
407 }
408
ath12k_ce_completed_recv_next(struct ath12k_ce_pipe * pipe,struct sk_buff ** skb,int * nbytes)409 static int ath12k_ce_completed_recv_next(struct ath12k_ce_pipe *pipe,
410 struct sk_buff **skb, int *nbytes)
411 {
412 struct ath12k_base *ab = pipe->ab;
413 struct hal_ce_srng_dst_status_desc *desc;
414 struct hal_srng *srng;
415 unsigned int sw_index;
416 unsigned int nentries_mask;
417 int ret = 0;
418
419 spin_lock_bh(&ab->ce.ce_lock);
420
421 sw_index = pipe->dest_ring->sw_index;
422 nentries_mask = pipe->dest_ring->nentries_mask;
423
424 srng = &ab->hal.srng_list[pipe->status_ring->hal_ring_id];
425
426 spin_lock_bh(&srng->lock);
427
428 ath12k_hal_srng_access_begin(ab, srng);
429
430 desc = ath12k_hal_srng_dst_get_next_entry(ab, srng);
431 if (!desc) {
432 ret = -EIO;
433 goto err;
434 }
435
436 /* Make sure descriptor is read after the head pointer. */
437 dma_rmb();
438
439 *nbytes = ath12k_hal_ce_dst_status_get_length(desc);
440
441 *skb = pipe->dest_ring->skb[sw_index];
442 pipe->dest_ring->skb[sw_index] = NULL;
443
444 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
445 pipe->dest_ring->sw_index = sw_index;
446
447 pipe->rx_buf_needed++;
448 err:
449 ath12k_hal_srng_access_end(ab, srng);
450
451 spin_unlock_bh(&srng->lock);
452
453 spin_unlock_bh(&ab->ce.ce_lock);
454
455 return ret;
456 }
457
ath12k_ce_recv_process_cb(struct ath12k_ce_pipe * pipe)458 static void ath12k_ce_recv_process_cb(struct ath12k_ce_pipe *pipe)
459 {
460 struct ath12k_base *ab = pipe->ab;
461 struct sk_buff *skb;
462 struct sk_buff_head list;
463 unsigned int nbytes, max_nbytes;
464 int ret;
465
466 __skb_queue_head_init(&list);
467 while (ath12k_ce_completed_recv_next(pipe, &skb, &nbytes) == 0) {
468 max_nbytes = skb->len + skb_tailroom(skb);
469 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr,
470 max_nbytes, DMA_FROM_DEVICE);
471
472 if (unlikely(max_nbytes < nbytes || nbytes == 0)) {
473 ath12k_warn(ab, "unexpected rx length (nbytes %d, max %d)",
474 nbytes, max_nbytes);
475 dev_kfree_skb_any(skb);
476 continue;
477 }
478
479 skb_put(skb, nbytes);
480 __skb_queue_tail(&list, skb);
481 }
482
483 while ((skb = __skb_dequeue(&list))) {
484 ath12k_dbg(ab, ATH12K_DBG_AHB, "rx ce pipe %d len %d\n",
485 pipe->pipe_num, skb->len);
486 pipe->recv_cb(ab, skb);
487 }
488
489 ret = ath12k_ce_rx_post_pipe(pipe);
490 if (ret && ret != -ENOSPC) {
491 ath12k_warn(ab, "failed to post rx buf to pipe: %d err: %d\n",
492 pipe->pipe_num, ret);
493 mod_timer(&ab->rx_replenish_retry,
494 jiffies + ATH12K_CE_RX_POST_RETRY_JIFFIES);
495 }
496 }
497
ath12k_ce_completed_send_next(struct ath12k_ce_pipe * pipe)498 static struct sk_buff *ath12k_ce_completed_send_next(struct ath12k_ce_pipe *pipe)
499 {
500 struct ath12k_base *ab = pipe->ab;
501 struct hal_ce_srng_src_desc *desc;
502 struct hal_srng *srng;
503 unsigned int sw_index;
504 unsigned int nentries_mask;
505 struct sk_buff *skb;
506
507 spin_lock_bh(&ab->ce.ce_lock);
508
509 sw_index = pipe->src_ring->sw_index;
510 nentries_mask = pipe->src_ring->nentries_mask;
511
512 srng = &ab->hal.srng_list[pipe->src_ring->hal_ring_id];
513
514 spin_lock_bh(&srng->lock);
515
516 ath12k_hal_srng_access_begin(ab, srng);
517
518 desc = ath12k_hal_srng_src_reap_next(ab, srng);
519 if (!desc) {
520 skb = ERR_PTR(-EIO);
521 goto err_unlock;
522 }
523
524 skb = pipe->src_ring->skb[sw_index];
525
526 pipe->src_ring->skb[sw_index] = NULL;
527
528 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
529 pipe->src_ring->sw_index = sw_index;
530
531 err_unlock:
532 spin_unlock_bh(&srng->lock);
533
534 spin_unlock_bh(&ab->ce.ce_lock);
535
536 return skb;
537 }
538
ath12k_ce_send_done_cb(struct ath12k_ce_pipe * pipe)539 static void ath12k_ce_send_done_cb(struct ath12k_ce_pipe *pipe)
540 {
541 struct ath12k_base *ab = pipe->ab;
542 struct sk_buff *skb;
543
544 while (!IS_ERR(skb = ath12k_ce_completed_send_next(pipe))) {
545 if (!skb)
546 continue;
547
548 dma_unmap_single(ab->dev, ATH12K_SKB_CB(skb)->paddr, skb->len,
549 DMA_TO_DEVICE);
550 dev_kfree_skb_any(skb);
551 }
552 }
553
ath12k_ce_srng_msi_ring_params_setup(struct ath12k_base * ab,u32 ce_id,struct hal_srng_params * ring_params)554 static void ath12k_ce_srng_msi_ring_params_setup(struct ath12k_base *ab, u32 ce_id,
555 struct hal_srng_params *ring_params)
556 {
557 u32 msi_data_start;
558 u32 msi_data_count, msi_data_idx;
559 u32 msi_irq_start;
560 u32 addr_lo;
561 u32 addr_hi;
562 int ret;
563
564 ret = ath12k_hif_get_user_msi_vector(ab, "CE",
565 &msi_data_count, &msi_data_start,
566 &msi_irq_start);
567
568 if (ret)
569 return;
570
571 ath12k_hif_get_msi_address(ab, &addr_lo, &addr_hi);
572 ath12k_hif_get_ce_msi_idx(ab, ce_id, &msi_data_idx);
573
574 ring_params->msi_addr = addr_lo;
575 ring_params->msi_addr |= (dma_addr_t)(((uint64_t)addr_hi) << 32);
576 ring_params->msi_data = (msi_data_idx % msi_data_count) + msi_data_start;
577 ring_params->flags |= HAL_SRNG_FLAGS_MSI_INTR;
578 }
579
ath12k_ce_init_ring(struct ath12k_base * ab,struct ath12k_ce_ring * ce_ring,int ce_id,enum hal_ring_type type)580 static int ath12k_ce_init_ring(struct ath12k_base *ab,
581 struct ath12k_ce_ring *ce_ring,
582 int ce_id, enum hal_ring_type type)
583 {
584 struct hal_srng_params params = { 0 };
585 int ret;
586
587 params.ring_base_paddr = ce_ring->base_addr_ce_space;
588 params.ring_base_vaddr = ce_ring->base_addr_owner_space;
589 params.num_entries = ce_ring->nentries;
590
591 if (!(CE_ATTR_DIS_INTR & ab->hw_params->host_ce_config[ce_id].flags))
592 ath12k_ce_srng_msi_ring_params_setup(ab, ce_id, ¶ms);
593
594 switch (type) {
595 case HAL_CE_SRC:
596 if (!(CE_ATTR_DIS_INTR & ab->hw_params->host_ce_config[ce_id].flags))
597 params.intr_batch_cntr_thres_entries = 1;
598 break;
599 case HAL_CE_DST:
600 params.max_buffer_len = ab->hw_params->host_ce_config[ce_id].src_sz_max;
601 if (!(ab->hw_params->host_ce_config[ce_id].flags & CE_ATTR_DIS_INTR)) {
602 params.intr_timer_thres_us = 1024;
603 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN;
604 params.low_threshold = ce_ring->nentries - 3;
605 }
606 break;
607 case HAL_CE_DST_STATUS:
608 if (!(ab->hw_params->host_ce_config[ce_id].flags & CE_ATTR_DIS_INTR)) {
609 params.intr_batch_cntr_thres_entries = 1;
610 params.intr_timer_thres_us = 0x1000;
611 }
612 break;
613 default:
614 ath12k_warn(ab, "Invalid CE ring type %d\n", type);
615 return -EINVAL;
616 }
617
618 /* TODO: Init other params needed by HAL to init the ring */
619
620 ret = ath12k_hal_srng_setup(ab, type, ce_id, 0, ¶ms);
621 if (ret < 0) {
622 ath12k_warn(ab, "failed to setup srng: %d ring_id %d\n",
623 ret, ce_id);
624 return ret;
625 }
626
627 ce_ring->hal_ring_id = ret;
628
629 return 0;
630 }
631
632 static struct ath12k_ce_ring *
ath12k_ce_alloc_ring(struct ath12k_base * ab,int nentries,int desc_sz)633 ath12k_ce_alloc_ring(struct ath12k_base *ab, int nentries, int desc_sz)
634 {
635 struct ath12k_ce_ring *ce_ring;
636 dma_addr_t base_addr;
637
638 ce_ring = kzalloc(struct_size(ce_ring, skb, nentries), GFP_KERNEL);
639 if (!ce_ring)
640 return ERR_PTR(-ENOMEM);
641
642 ce_ring->nentries = nentries;
643 ce_ring->nentries_mask = nentries - 1;
644
645 /* Legacy platforms that do not support cache
646 * coherent DMA are unsupported
647 */
648 ce_ring->base_addr_owner_space_unaligned =
649 dma_alloc_coherent(ab->dev,
650 nentries * desc_sz + CE_DESC_RING_ALIGN,
651 &base_addr, GFP_KERNEL);
652 if (!ce_ring->base_addr_owner_space_unaligned) {
653 kfree(ce_ring);
654 return ERR_PTR(-ENOMEM);
655 }
656
657 ce_ring->base_addr_ce_space_unaligned = base_addr;
658
659 ce_ring->base_addr_owner_space =
660 PTR_ALIGN(ce_ring->base_addr_owner_space_unaligned,
661 CE_DESC_RING_ALIGN);
662
663 ce_ring->base_addr_ce_space = ALIGN(ce_ring->base_addr_ce_space_unaligned,
664 CE_DESC_RING_ALIGN);
665
666 return ce_ring;
667 }
668
ath12k_ce_alloc_pipe(struct ath12k_base * ab,int ce_id)669 static int ath12k_ce_alloc_pipe(struct ath12k_base *ab, int ce_id)
670 {
671 struct ath12k_ce_pipe *pipe = &ab->ce.ce_pipe[ce_id];
672 const struct ce_attr *attr = &ab->hw_params->host_ce_config[ce_id];
673 struct ath12k_ce_ring *ring;
674 int nentries;
675 int desc_sz;
676
677 pipe->attr_flags = attr->flags;
678
679 if (attr->src_nentries) {
680 pipe->send_cb = ath12k_ce_send_done_cb;
681 nentries = roundup_pow_of_two(attr->src_nentries);
682 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_SRC);
683 ring = ath12k_ce_alloc_ring(ab, nentries, desc_sz);
684 if (IS_ERR(ring))
685 return PTR_ERR(ring);
686 pipe->src_ring = ring;
687 }
688
689 if (attr->dest_nentries) {
690 pipe->recv_cb = attr->recv_cb;
691 nentries = roundup_pow_of_two(attr->dest_nentries);
692 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_DST);
693 ring = ath12k_ce_alloc_ring(ab, nentries, desc_sz);
694 if (IS_ERR(ring))
695 return PTR_ERR(ring);
696 pipe->dest_ring = ring;
697
698 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_DST_STATUS);
699 ring = ath12k_ce_alloc_ring(ab, nentries, desc_sz);
700 if (IS_ERR(ring))
701 return PTR_ERR(ring);
702 pipe->status_ring = ring;
703 }
704
705 return 0;
706 }
707
ath12k_ce_per_engine_service(struct ath12k_base * ab,u16 ce_id)708 void ath12k_ce_per_engine_service(struct ath12k_base *ab, u16 ce_id)
709 {
710 struct ath12k_ce_pipe *pipe = &ab->ce.ce_pipe[ce_id];
711
712 if (pipe->send_cb)
713 pipe->send_cb(pipe);
714
715 if (pipe->recv_cb)
716 ath12k_ce_recv_process_cb(pipe);
717 }
718
ath12k_ce_poll_send_completed(struct ath12k_base * ab,u8 pipe_id)719 void ath12k_ce_poll_send_completed(struct ath12k_base *ab, u8 pipe_id)
720 {
721 struct ath12k_ce_pipe *pipe = &ab->ce.ce_pipe[pipe_id];
722
723 if ((pipe->attr_flags & CE_ATTR_DIS_INTR) && pipe->send_cb)
724 pipe->send_cb(pipe);
725 }
726
ath12k_ce_send(struct ath12k_base * ab,struct sk_buff * skb,u8 pipe_id,u16 transfer_id)727 int ath12k_ce_send(struct ath12k_base *ab, struct sk_buff *skb, u8 pipe_id,
728 u16 transfer_id)
729 {
730 struct ath12k_ce_pipe *pipe = &ab->ce.ce_pipe[pipe_id];
731 struct hal_ce_srng_src_desc *desc;
732 struct hal_srng *srng;
733 unsigned int write_index, sw_index;
734 unsigned int nentries_mask;
735 int ret = 0;
736 u8 byte_swap_data = 0;
737 int num_used;
738
739 /* Check if some entries could be regained by handling tx completion if
740 * the CE has interrupts disabled and the used entries is more than the
741 * defined usage threshold.
742 */
743 if (pipe->attr_flags & CE_ATTR_DIS_INTR) {
744 spin_lock_bh(&ab->ce.ce_lock);
745 write_index = pipe->src_ring->write_index;
746
747 sw_index = pipe->src_ring->sw_index;
748
749 if (write_index >= sw_index)
750 num_used = write_index - sw_index;
751 else
752 num_used = pipe->src_ring->nentries - sw_index +
753 write_index;
754
755 spin_unlock_bh(&ab->ce.ce_lock);
756
757 if (num_used > ATH12K_CE_USAGE_THRESHOLD)
758 ath12k_ce_poll_send_completed(ab, pipe->pipe_num);
759 }
760
761 if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags))
762 return -ESHUTDOWN;
763
764 spin_lock_bh(&ab->ce.ce_lock);
765
766 write_index = pipe->src_ring->write_index;
767 nentries_mask = pipe->src_ring->nentries_mask;
768
769 srng = &ab->hal.srng_list[pipe->src_ring->hal_ring_id];
770
771 spin_lock_bh(&srng->lock);
772
773 ath12k_hal_srng_access_begin(ab, srng);
774
775 if (unlikely(ath12k_hal_srng_src_num_free(ab, srng, false) < 1)) {
776 ath12k_hal_srng_access_end(ab, srng);
777 ret = -ENOBUFS;
778 goto unlock;
779 }
780
781 desc = ath12k_hal_srng_src_get_next_reaped(ab, srng);
782 if (!desc) {
783 ath12k_hal_srng_access_end(ab, srng);
784 ret = -ENOBUFS;
785 goto unlock;
786 }
787
788 if (pipe->attr_flags & CE_ATTR_BYTE_SWAP_DATA)
789 byte_swap_data = 1;
790
791 ath12k_hal_ce_src_set_desc(desc, ATH12K_SKB_CB(skb)->paddr,
792 skb->len, transfer_id, byte_swap_data);
793
794 pipe->src_ring->skb[write_index] = skb;
795 pipe->src_ring->write_index = CE_RING_IDX_INCR(nentries_mask,
796 write_index);
797
798 ath12k_hal_srng_access_end(ab, srng);
799
800 unlock:
801 spin_unlock_bh(&srng->lock);
802
803 spin_unlock_bh(&ab->ce.ce_lock);
804
805 return ret;
806 }
807
ath12k_ce_rx_pipe_cleanup(struct ath12k_ce_pipe * pipe)808 static void ath12k_ce_rx_pipe_cleanup(struct ath12k_ce_pipe *pipe)
809 {
810 struct ath12k_base *ab = pipe->ab;
811 struct ath12k_ce_ring *ring = pipe->dest_ring;
812 struct sk_buff *skb;
813 int i;
814
815 if (!(ring && pipe->buf_sz))
816 return;
817
818 for (i = 0; i < ring->nentries; i++) {
819 skb = ring->skb[i];
820 if (!skb)
821 continue;
822
823 ring->skb[i] = NULL;
824 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr,
825 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
826 dev_kfree_skb_any(skb);
827 }
828 }
829
ath12k_ce_cleanup_pipes(struct ath12k_base * ab)830 void ath12k_ce_cleanup_pipes(struct ath12k_base *ab)
831 {
832 struct ath12k_ce_pipe *pipe;
833 int pipe_num;
834
835 for (pipe_num = 0; pipe_num < ab->hw_params->ce_count; pipe_num++) {
836 pipe = &ab->ce.ce_pipe[pipe_num];
837 ath12k_ce_rx_pipe_cleanup(pipe);
838
839 /* Cleanup any src CE's which have interrupts disabled */
840 ath12k_ce_poll_send_completed(ab, pipe_num);
841
842 /* NOTE: Should we also clean up tx buffer in all pipes? */
843 }
844 }
845
ath12k_ce_rx_post_buf(struct ath12k_base * ab)846 void ath12k_ce_rx_post_buf(struct ath12k_base *ab)
847 {
848 struct ath12k_ce_pipe *pipe;
849 int i;
850 int ret;
851
852 for (i = 0; i < ab->hw_params->ce_count; i++) {
853 pipe = &ab->ce.ce_pipe[i];
854 ret = ath12k_ce_rx_post_pipe(pipe);
855 if (ret) {
856 if (ret == -ENOSPC)
857 continue;
858
859 ath12k_warn(ab, "failed to post rx buf to pipe: %d err: %d\n",
860 i, ret);
861 mod_timer(&ab->rx_replenish_retry,
862 jiffies + ATH12K_CE_RX_POST_RETRY_JIFFIES);
863
864 return;
865 }
866 }
867 }
868
ath12k_ce_rx_replenish_retry(struct timer_list * t)869 void ath12k_ce_rx_replenish_retry(struct timer_list *t)
870 {
871 struct ath12k_base *ab = timer_container_of(ab, t, rx_replenish_retry);
872
873 ath12k_ce_rx_post_buf(ab);
874 }
875
ath12k_ce_shadow_config(struct ath12k_base * ab)876 static void ath12k_ce_shadow_config(struct ath12k_base *ab)
877 {
878 int i;
879
880 for (i = 0; i < ab->hw_params->ce_count; i++) {
881 if (ab->hw_params->host_ce_config[i].src_nentries)
882 ath12k_hal_srng_update_shadow_config(ab, HAL_CE_SRC, i);
883
884 if (ab->hw_params->host_ce_config[i].dest_nentries) {
885 ath12k_hal_srng_update_shadow_config(ab, HAL_CE_DST, i);
886 ath12k_hal_srng_update_shadow_config(ab, HAL_CE_DST_STATUS, i);
887 }
888 }
889 }
890
ath12k_ce_get_shadow_config(struct ath12k_base * ab,u32 ** shadow_cfg,u32 * shadow_cfg_len)891 void ath12k_ce_get_shadow_config(struct ath12k_base *ab,
892 u32 **shadow_cfg, u32 *shadow_cfg_len)
893 {
894 if (!ab->hw_params->supports_shadow_regs)
895 return;
896
897 ath12k_hal_srng_get_shadow_config(ab, shadow_cfg, shadow_cfg_len);
898
899 /* shadow is already configured */
900 if (*shadow_cfg_len)
901 return;
902
903 /* shadow isn't configured yet, configure now.
904 * non-CE srngs are configured firstly, then
905 * all CE srngs.
906 */
907 ath12k_hal_srng_shadow_config(ab);
908 ath12k_ce_shadow_config(ab);
909
910 /* get the shadow configuration */
911 ath12k_hal_srng_get_shadow_config(ab, shadow_cfg, shadow_cfg_len);
912 }
913
ath12k_ce_init_pipes(struct ath12k_base * ab)914 int ath12k_ce_init_pipes(struct ath12k_base *ab)
915 {
916 struct ath12k_ce_pipe *pipe;
917 int i;
918 int ret;
919
920 ath12k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v3,
921 &ab->qmi.ce_cfg.shadow_reg_v3_len);
922
923 for (i = 0; i < ab->hw_params->ce_count; i++) {
924 pipe = &ab->ce.ce_pipe[i];
925
926 if (pipe->src_ring) {
927 ret = ath12k_ce_init_ring(ab, pipe->src_ring, i,
928 HAL_CE_SRC);
929 if (ret) {
930 ath12k_warn(ab, "failed to init src ring: %d\n",
931 ret);
932 /* Should we clear any partial init */
933 return ret;
934 }
935
936 pipe->src_ring->write_index = 0;
937 pipe->src_ring->sw_index = 0;
938 }
939
940 if (pipe->dest_ring) {
941 ret = ath12k_ce_init_ring(ab, pipe->dest_ring, i,
942 HAL_CE_DST);
943 if (ret) {
944 ath12k_warn(ab, "failed to init dest ring: %d\n",
945 ret);
946 /* Should we clear any partial init */
947 return ret;
948 }
949
950 pipe->rx_buf_needed = pipe->dest_ring->nentries ?
951 pipe->dest_ring->nentries - 2 : 0;
952
953 pipe->dest_ring->write_index = 0;
954 pipe->dest_ring->sw_index = 0;
955 }
956
957 if (pipe->status_ring) {
958 ret = ath12k_ce_init_ring(ab, pipe->status_ring, i,
959 HAL_CE_DST_STATUS);
960 if (ret) {
961 ath12k_warn(ab, "failed to init dest status ing: %d\n",
962 ret);
963 /* Should we clear any partial init */
964 return ret;
965 }
966
967 pipe->status_ring->write_index = 0;
968 pipe->status_ring->sw_index = 0;
969 }
970 }
971
972 return 0;
973 }
974
ath12k_ce_free_pipes(struct ath12k_base * ab)975 void ath12k_ce_free_pipes(struct ath12k_base *ab)
976 {
977 struct ath12k_ce_pipe *pipe;
978 int desc_sz;
979 int i;
980
981 for (i = 0; i < ab->hw_params->ce_count; i++) {
982 pipe = &ab->ce.ce_pipe[i];
983
984 if (pipe->src_ring) {
985 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_SRC);
986 dma_free_coherent(ab->dev,
987 pipe->src_ring->nentries * desc_sz +
988 CE_DESC_RING_ALIGN,
989 pipe->src_ring->base_addr_owner_space,
990 pipe->src_ring->base_addr_ce_space);
991 kfree(pipe->src_ring);
992 pipe->src_ring = NULL;
993 }
994
995 if (pipe->dest_ring) {
996 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_DST);
997 dma_free_coherent(ab->dev,
998 pipe->dest_ring->nentries * desc_sz +
999 CE_DESC_RING_ALIGN,
1000 pipe->dest_ring->base_addr_owner_space,
1001 pipe->dest_ring->base_addr_ce_space);
1002 kfree(pipe->dest_ring);
1003 pipe->dest_ring = NULL;
1004 }
1005
1006 if (pipe->status_ring) {
1007 desc_sz =
1008 ath12k_hal_ce_get_desc_size(HAL_CE_DESC_DST_STATUS);
1009 dma_free_coherent(ab->dev,
1010 pipe->status_ring->nentries * desc_sz +
1011 CE_DESC_RING_ALIGN,
1012 pipe->status_ring->base_addr_owner_space,
1013 pipe->status_ring->base_addr_ce_space);
1014 kfree(pipe->status_ring);
1015 pipe->status_ring = NULL;
1016 }
1017 }
1018 }
1019
ath12k_ce_alloc_pipes(struct ath12k_base * ab)1020 int ath12k_ce_alloc_pipes(struct ath12k_base *ab)
1021 {
1022 struct ath12k_ce_pipe *pipe;
1023 int i;
1024 int ret;
1025 const struct ce_attr *attr;
1026
1027 spin_lock_init(&ab->ce.ce_lock);
1028
1029 for (i = 0; i < ab->hw_params->ce_count; i++) {
1030 attr = &ab->hw_params->host_ce_config[i];
1031 pipe = &ab->ce.ce_pipe[i];
1032 pipe->pipe_num = i;
1033 pipe->ab = ab;
1034 pipe->buf_sz = attr->src_sz_max;
1035
1036 ret = ath12k_ce_alloc_pipe(ab, i);
1037 if (ret) {
1038 /* Free any partial successful allocation */
1039 ath12k_ce_free_pipes(ab);
1040 return ret;
1041 }
1042 }
1043
1044 return 0;
1045 }
1046
ath12k_ce_get_attr_flags(struct ath12k_base * ab,int ce_id)1047 int ath12k_ce_get_attr_flags(struct ath12k_base *ab, int ce_id)
1048 {
1049 if (ce_id >= ab->hw_params->ce_count)
1050 return -EINVAL;
1051
1052 return ab->hw_params->host_ce_config[ce_id].flags;
1053 }
1054