1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef ATH12K_CORE_H
8 #define ATH12K_CORE_H
9
10 #include <linux/types.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/bitfield.h>
14 #include <linux/dmi.h>
15 #include <linux/ctype.h>
16 #include <linux/firmware.h>
17 #include <linux/of_reserved_mem.h>
18 #include <linux/panic_notifier.h>
19 #include <linux/average.h>
20 #include <linux/of.h>
21 #include "qmi.h"
22 #include "htc.h"
23 #include "wmi.h"
24 #include "hal.h"
25 #include "dp.h"
26 #include "ce.h"
27 #include "mac.h"
28 #include "hw.h"
29 #include "hal_rx.h"
30 #include "reg.h"
31 #include "dbring.h"
32 #include "fw.h"
33 #include "acpi.h"
34 #include "wow.h"
35 #include "debugfs_htt_stats.h"
36 #include "coredump.h"
37
38 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
39
40 #define ATH12K_TX_MGMT_NUM_PENDING_MAX 512
41
42 #define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64
43
44 /* Pending management packets threshold for dropping probe responses */
45 #define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4)
46
47 /* SMBIOS type containing Board Data File Name Extension */
48 #define ATH12K_SMBIOS_BDF_EXT_TYPE 0xF8
49
50 /* SMBIOS type structure length (excluding strings-set) */
51 #define ATH12K_SMBIOS_BDF_EXT_LENGTH 0x9
52
53 /* The magic used by QCA spec */
54 #define ATH12K_SMBIOS_BDF_EXT_MAGIC "BDF_"
55
56 #define ATH12K_INVALID_HW_MAC_ID 0xFF
57 #define ATH12K_CONNECTION_LOSS_HZ (3 * HZ)
58
59 #define ATH12K_MON_TIMER_INTERVAL 10
60 #define ATH12K_RESET_TIMEOUT_HZ (20 * HZ)
61 #define ATH12K_RESET_MAX_FAIL_COUNT_FIRST 3
62 #define ATH12K_RESET_MAX_FAIL_COUNT_FINAL 5
63 #define ATH12K_RESET_FAIL_TIMEOUT_HZ (20 * HZ)
64 #define ATH12K_RECONFIGURE_TIMEOUT_HZ (10 * HZ)
65 #define ATH12K_RECOVER_START_TIMEOUT_HZ (20 * HZ)
66
67 #define ATH12K_MAX_DEVICES 3
68 #define ATH12K_GROUP_MAX_RADIO (ATH12K_MAX_DEVICES * MAX_RADIOS)
69 #define ATH12K_INVALID_GROUP_ID 0xFF
70 #define ATH12K_INVALID_DEVICE_ID 0xFF
71
72 #define ATH12K_MAX_MLO_PEERS 256
73 #define ATH12K_MLO_PEER_ID_INVALID 0xFFFF
74
75 enum ath12k_bdf_search {
76 ATH12K_BDF_SEARCH_DEFAULT,
77 ATH12K_BDF_SEARCH_BUS_AND_BOARD,
78 };
79
80 enum wme_ac {
81 WME_AC_BE,
82 WME_AC_BK,
83 WME_AC_VI,
84 WME_AC_VO,
85 WME_NUM_AC
86 };
87
88 #define ATH12K_HT_MCS_MAX 7
89 #define ATH12K_VHT_MCS_MAX 9
90 #define ATH12K_HE_MCS_MAX 11
91 #define ATH12K_EHT_MCS_MAX 15
92
93 enum ath12k_crypt_mode {
94 /* Only use hardware crypto engine */
95 ATH12K_CRYPT_MODE_HW,
96 /* Only use software crypto */
97 ATH12K_CRYPT_MODE_SW,
98 };
99
ath12k_tid_to_ac(u32 tid)100 static inline enum wme_ac ath12k_tid_to_ac(u32 tid)
101 {
102 return (((tid == 0) || (tid == 3)) ? WME_AC_BE :
103 ((tid == 1) || (tid == 2)) ? WME_AC_BK :
104 ((tid == 4) || (tid == 5)) ? WME_AC_VI :
105 WME_AC_VO);
106 }
107
ath12k_le32hilo_to_u64(__le32 hi,__le32 lo)108 static inline u64 ath12k_le32hilo_to_u64(__le32 hi, __le32 lo)
109 {
110 u64 hi64 = le32_to_cpu(hi);
111 u64 lo64 = le32_to_cpu(lo);
112
113 return (hi64 << 32) | lo64;
114 }
115
116 enum ath12k_skb_flags {
117 ATH12K_SKB_HW_80211_ENCAP = BIT(0),
118 ATH12K_SKB_CIPHER_SET = BIT(1),
119 };
120
121 struct ath12k_skb_cb {
122 dma_addr_t paddr;
123 struct ath12k *ar;
124 struct ieee80211_vif *vif;
125 dma_addr_t paddr_ext_desc;
126 u32 cipher;
127 u8 flags;
128 u8 link_id;
129 };
130
131 struct ath12k_skb_rxcb {
132 dma_addr_t paddr;
133 bool is_first_msdu;
134 bool is_last_msdu;
135 bool is_continuation;
136 bool is_mcbc;
137 bool is_eapol;
138 struct hal_rx_desc *rx_desc;
139 u8 err_rel_src;
140 u8 err_code;
141 u8 hw_link_id;
142 u8 unmapped;
143 u8 is_frag;
144 u8 tid;
145 u16 peer_id;
146 bool is_end_of_ppdu;
147 };
148
149 enum ath12k_hw_rev {
150 ATH12K_HW_QCN9274_HW10,
151 ATH12K_HW_QCN9274_HW20,
152 ATH12K_HW_WCN7850_HW20,
153 ATH12K_HW_IPQ5332_HW10,
154 };
155
156 enum ath12k_firmware_mode {
157 /* the default mode, standard 802.11 functionality */
158 ATH12K_FIRMWARE_MODE_NORMAL,
159
160 /* factory tests etc */
161 ATH12K_FIRMWARE_MODE_FTM,
162 };
163
164 #define ATH12K_IRQ_NUM_MAX 57
165 #define ATH12K_EXT_IRQ_NUM_MAX 16
166 #define ATH12K_MAX_TCL_RING_NUM 3
167
168 struct ath12k_ext_irq_grp {
169 struct ath12k_base *ab;
170 u32 irqs[ATH12K_EXT_IRQ_NUM_MAX];
171 u32 num_irq;
172 u32 grp_id;
173 u64 timestamp;
174 bool napi_enabled;
175 struct napi_struct napi;
176 struct net_device *napi_ndev;
177 };
178
179 enum ath12k_smbios_cc_type {
180 /* disable country code setting from SMBIOS */
181 ATH12K_SMBIOS_CC_DISABLE = 0,
182
183 /* set country code by ANSI country name, based on ISO3166-1 alpha2 */
184 ATH12K_SMBIOS_CC_ISO = 1,
185
186 /* worldwide regdomain */
187 ATH12K_SMBIOS_CC_WW = 2,
188 };
189
190 struct ath12k_smbios_bdf {
191 struct dmi_header hdr;
192 u8 features_disabled;
193
194 /* enum ath12k_smbios_cc_type */
195 u8 country_code_flag;
196
197 /* To set specific country, you need to set country code
198 * flag=ATH12K_SMBIOS_CC_ISO first, then if country is United
199 * States, then country code value = 0x5553 ("US",'U' = 0x55, 'S'=
200 * 0x53). To set country to INDONESIA, then country code value =
201 * 0x4944 ("IN", 'I'=0x49, 'D'=0x44). If country code flag =
202 * ATH12K_SMBIOS_CC_WW, then you can use worldwide regulatory
203 * setting.
204 */
205 u16 cc_code;
206
207 u8 bdf_enabled;
208 u8 bdf_ext[];
209 } __packed;
210
211 #define HEHANDLE_CAP_PHYINFO_SIZE 3
212 #define HECAP_PHYINFO_SIZE 9
213 #define HECAP_MACINFO_SIZE 5
214 #define HECAP_TXRX_MCS_NSS_SIZE 2
215 #define HECAP_PPET16_PPET8_MAX_SIZE 25
216
217 #define HE_PPET16_PPET8_SIZE 8
218
219 /* 802.11ax PPE (PPDU packet Extension) threshold */
220 struct he_ppe_threshold {
221 u32 numss_m1;
222 u32 ru_mask;
223 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE];
224 };
225
226 struct ath12k_he {
227 u8 hecap_macinfo[HECAP_MACINFO_SIZE];
228 u32 hecap_rxmcsnssmap;
229 u32 hecap_txmcsnssmap;
230 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE];
231 struct he_ppe_threshold hecap_ppet;
232 u32 heop_param;
233 };
234
235 enum {
236 WMI_HOST_TP_SCALE_MAX = 0,
237 WMI_HOST_TP_SCALE_50 = 1,
238 WMI_HOST_TP_SCALE_25 = 2,
239 WMI_HOST_TP_SCALE_12 = 3,
240 WMI_HOST_TP_SCALE_MIN = 4,
241 WMI_HOST_TP_SCALE_SIZE = 5,
242 };
243
244 enum ath12k_scan_state {
245 ATH12K_SCAN_IDLE,
246 ATH12K_SCAN_STARTING,
247 ATH12K_SCAN_RUNNING,
248 ATH12K_SCAN_ABORTING,
249 };
250
251 enum ath12k_11d_state {
252 ATH12K_11D_IDLE,
253 ATH12K_11D_PREPARING,
254 ATH12K_11D_RUNNING,
255 };
256
257 enum ath12k_hw_group_flags {
258 ATH12K_GROUP_FLAG_REGISTERED,
259 ATH12K_GROUP_FLAG_UNREGISTER,
260 };
261
262 enum ath12k_dev_flags {
263 ATH12K_FLAG_CAC_RUNNING,
264 ATH12K_FLAG_CRASH_FLUSH,
265 ATH12K_FLAG_RAW_MODE,
266 ATH12K_FLAG_HW_CRYPTO_DISABLED,
267 ATH12K_FLAG_RECOVERY,
268 ATH12K_FLAG_UNREGISTERING,
269 ATH12K_FLAG_REGISTERED,
270 ATH12K_FLAG_QMI_FAIL,
271 ATH12K_FLAG_HTC_SUSPEND_COMPLETE,
272 ATH12K_FLAG_CE_IRQ_ENABLED,
273 ATH12K_FLAG_EXT_IRQ_ENABLED,
274 ATH12K_FLAG_QMI_FW_READY_COMPLETE,
275 ATH12K_FLAG_FTM_SEGMENTED,
276 ATH12K_FLAG_FIXED_MEM_REGION,
277 };
278
279 struct ath12k_tx_conf {
280 bool changed;
281 u16 ac;
282 struct ieee80211_tx_queue_params tx_queue_params;
283 };
284
285 struct ath12k_key_conf {
286 enum set_key_cmd cmd;
287 struct list_head list;
288 struct ieee80211_sta *sta;
289 struct ieee80211_key_conf *key;
290 };
291
292 struct ath12k_vif_cache {
293 struct ath12k_tx_conf tx_conf;
294 struct ath12k_key_conf key_conf;
295 u32 bss_conf_changed;
296 };
297
298 struct ath12k_rekey_data {
299 u8 kck[NL80211_KCK_LEN];
300 u8 kek[NL80211_KCK_LEN];
301 u64 replay_ctr;
302 bool enable_offload;
303 };
304
305 struct ath12k_link_vif {
306 u32 vdev_id;
307 u32 beacon_interval;
308 u32 dtim_period;
309 u16 ast_hash;
310 u16 ast_idx;
311 u16 tcl_metadata;
312 u8 hal_addr_search_flags;
313 u8 search_type;
314
315 struct ath12k *ar;
316
317 int bank_id;
318 u8 vdev_id_check_en;
319
320 struct wmi_wmm_params_all_arg wmm_params;
321 struct list_head list;
322
323 bool is_created;
324 bool is_started;
325 bool is_up;
326 u8 bssid[ETH_ALEN];
327 struct cfg80211_bitrate_mask bitrate_mask;
328 struct delayed_work connection_loss_work;
329 int num_legacy_stations;
330 int rtscts_prot_mode;
331 int txpower;
332 bool rsnie_present;
333 bool wpaie_present;
334 u8 vdev_stats_id;
335 u32 punct_bitmap;
336 u8 link_id;
337 struct ath12k_vif *ahvif;
338 struct ath12k_rekey_data rekey_data;
339 struct ath12k_link_stats link_stats;
340 spinlock_t link_stats_lock; /* Protects updates to link_stats */
341
342 u8 current_cntdown_counter;
343
344 /* only used in station mode */
345 bool is_sta_assoc_link;
346
347 struct ath12k_reg_tpc_power_info reg_tpc_info;
348 };
349
350 struct ath12k_vif {
351 enum wmi_vdev_type vdev_type;
352 enum wmi_vdev_subtype vdev_subtype;
353 struct ieee80211_vif *vif;
354 struct ath12k_hw *ah;
355
356 union {
357 struct {
358 u32 uapsd;
359 } sta;
360 struct {
361 /* 127 stations; wmi limit */
362 u8 tim_bitmap[16];
363 u8 tim_len;
364 u32 ssid_len;
365 u8 ssid[IEEE80211_MAX_SSID_LEN];
366 bool hidden_ssid;
367 /* P2P_IE with NoA attribute for P2P_GO case */
368 u32 noa_len;
369 u8 *noa_data;
370 } ap;
371 } u;
372
373 u32 aid;
374 u32 key_cipher;
375 u8 tx_encap_type;
376 bool ps;
377 atomic_t mcbc_gsn;
378
379 struct ath12k_link_vif deflink;
380 struct ath12k_link_vif __rcu *link[ATH12K_NUM_MAX_LINKS];
381 struct ath12k_vif_cache *cache[IEEE80211_MLD_MAX_NUM_LINKS];
382 /* indicates bitmap of link vif created in FW */
383 u16 links_map;
384 u8 last_scan_link;
385
386 /* Must be last - ends in a flexible-array member.
387 *
388 * FIXME: Driver should not copy struct ieee80211_chanctx_conf,
389 * especially because it has a flexible array. Find a better way.
390 */
391 struct ieee80211_chanctx_conf chanctx;
392 };
393
394 struct ath12k_vif_iter {
395 u32 vdev_id;
396 struct ath12k *ar;
397 struct ath12k_link_vif *arvif;
398 };
399
400 #define HAL_AST_IDX_INVALID 0xFFFF
401 #define HAL_RX_MAX_MCS 12
402 #define HAL_RX_MAX_MCS_HT 31
403 #define HAL_RX_MAX_MCS_VHT 9
404 #define HAL_RX_MAX_MCS_HE 11
405 #define HAL_RX_MAX_MCS_BE 15
406 #define HAL_RX_MAX_NSS 8
407 #define HAL_RX_MAX_NUM_LEGACY_RATES 12
408
409 #define ATH12K_SCAN_TIMEOUT_HZ (20 * HZ)
410
411 struct ath12k_rx_peer_rate_stats {
412 u64 ht_mcs_count[HAL_RX_MAX_MCS_HT + 1];
413 u64 vht_mcs_count[HAL_RX_MAX_MCS_VHT + 1];
414 u64 he_mcs_count[HAL_RX_MAX_MCS_HE + 1];
415 u64 be_mcs_count[HAL_RX_MAX_MCS_BE + 1];
416 u64 nss_count[HAL_RX_MAX_NSS];
417 u64 bw_count[HAL_RX_BW_MAX];
418 u64 gi_count[HAL_RX_GI_MAX];
419 u64 legacy_count[HAL_RX_MAX_NUM_LEGACY_RATES];
420 u64 rx_rate[HAL_RX_BW_MAX][HAL_RX_GI_MAX][HAL_RX_MAX_NSS][HAL_RX_MAX_MCS_HT + 1];
421 };
422
423 struct ath12k_rx_peer_stats {
424 u64 num_msdu;
425 u64 num_mpdu_fcs_ok;
426 u64 num_mpdu_fcs_err;
427 u64 tcp_msdu_count;
428 u64 udp_msdu_count;
429 u64 other_msdu_count;
430 u64 ampdu_msdu_count;
431 u64 non_ampdu_msdu_count;
432 u64 stbc_count;
433 u64 beamformed_count;
434 u64 coding_count[HAL_RX_SU_MU_CODING_MAX];
435 u64 tid_count[IEEE80211_NUM_TIDS + 1];
436 u64 pream_cnt[HAL_RX_PREAMBLE_MAX];
437 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX];
438 u64 rx_duration;
439 u64 dcm_count;
440 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX];
441 struct ath12k_rx_peer_rate_stats pkt_stats;
442 struct ath12k_rx_peer_rate_stats byte_stats;
443 };
444
445 #define ATH12K_HE_MCS_NUM 12
446 #define ATH12K_VHT_MCS_NUM 10
447 #define ATH12K_BW_NUM 5
448 #define ATH12K_NSS_NUM 4
449 #define ATH12K_LEGACY_NUM 12
450 #define ATH12K_GI_NUM 4
451 #define ATH12K_HT_MCS_NUM 32
452
453 enum ath12k_pkt_rx_err {
454 ATH12K_PKT_RX_ERR_FCS,
455 ATH12K_PKT_RX_ERR_TKIP,
456 ATH12K_PKT_RX_ERR_CRYPT,
457 ATH12K_PKT_RX_ERR_PEER_IDX_INVAL,
458 ATH12K_PKT_RX_ERR_MAX,
459 };
460
461 enum ath12k_ampdu_subfrm_num {
462 ATH12K_AMPDU_SUBFRM_NUM_10,
463 ATH12K_AMPDU_SUBFRM_NUM_20,
464 ATH12K_AMPDU_SUBFRM_NUM_30,
465 ATH12K_AMPDU_SUBFRM_NUM_40,
466 ATH12K_AMPDU_SUBFRM_NUM_50,
467 ATH12K_AMPDU_SUBFRM_NUM_60,
468 ATH12K_AMPDU_SUBFRM_NUM_MORE,
469 ATH12K_AMPDU_SUBFRM_NUM_MAX,
470 };
471
472 enum ath12k_amsdu_subfrm_num {
473 ATH12K_AMSDU_SUBFRM_NUM_1,
474 ATH12K_AMSDU_SUBFRM_NUM_2,
475 ATH12K_AMSDU_SUBFRM_NUM_3,
476 ATH12K_AMSDU_SUBFRM_NUM_4,
477 ATH12K_AMSDU_SUBFRM_NUM_MORE,
478 ATH12K_AMSDU_SUBFRM_NUM_MAX,
479 };
480
481 enum ath12k_counter_type {
482 ATH12K_COUNTER_TYPE_BYTES,
483 ATH12K_COUNTER_TYPE_PKTS,
484 ATH12K_COUNTER_TYPE_MAX,
485 };
486
487 enum ath12k_stats_type {
488 ATH12K_STATS_TYPE_SUCC,
489 ATH12K_STATS_TYPE_FAIL,
490 ATH12K_STATS_TYPE_RETRY,
491 ATH12K_STATS_TYPE_AMPDU,
492 ATH12K_STATS_TYPE_MAX,
493 };
494
495 struct ath12k_htt_data_stats {
496 u64 legacy[ATH12K_COUNTER_TYPE_MAX][ATH12K_LEGACY_NUM];
497 u64 ht[ATH12K_COUNTER_TYPE_MAX][ATH12K_HT_MCS_NUM];
498 u64 vht[ATH12K_COUNTER_TYPE_MAX][ATH12K_VHT_MCS_NUM];
499 u64 he[ATH12K_COUNTER_TYPE_MAX][ATH12K_HE_MCS_NUM];
500 u64 bw[ATH12K_COUNTER_TYPE_MAX][ATH12K_BW_NUM];
501 u64 nss[ATH12K_COUNTER_TYPE_MAX][ATH12K_NSS_NUM];
502 u64 gi[ATH12K_COUNTER_TYPE_MAX][ATH12K_GI_NUM];
503 u64 transmit_type[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RECEPTION_TYPE_MAX];
504 u64 ru_loc[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RU_ALLOC_TYPE_MAX];
505 };
506
507 struct ath12k_htt_tx_stats {
508 struct ath12k_htt_data_stats stats[ATH12K_STATS_TYPE_MAX];
509 u64 tx_duration;
510 u64 ba_fails;
511 u64 ack_fails;
512 u16 ru_start;
513 u16 ru_tones;
514 u32 mu_group[MAX_MU_GROUP_ID];
515 };
516
517 struct ath12k_per_ppdu_tx_stats {
518 u16 succ_pkts;
519 u16 failed_pkts;
520 u16 retry_pkts;
521 u32 succ_bytes;
522 u32 failed_bytes;
523 u32 retry_bytes;
524 };
525
526 struct ath12k_wbm_tx_stats {
527 u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX];
528 };
529
530 DECLARE_EWMA(avg_rssi, 10, 8)
531
532 struct ath12k_link_sta {
533 struct ath12k_link_vif *arvif;
534 struct ath12k_sta *ahsta;
535
536 /* link address similar to ieee80211_link_sta */
537 u8 addr[ETH_ALEN];
538
539 /* the following are protected by ar->data_lock */
540 u32 changed; /* IEEE80211_RC_* */
541 u32 bw;
542 u32 nss;
543 u32 smps;
544
545 struct wiphy_work update_wk;
546 struct rate_info txrate;
547 struct rate_info last_txrate;
548 u64 rx_duration;
549 u64 tx_duration;
550 u8 rssi_comb;
551 struct ewma_avg_rssi avg_rssi;
552 u8 link_id;
553 struct ath12k_rx_peer_stats *rx_stats;
554 struct ath12k_wbm_tx_stats *wbm_tx_stats;
555 u32 bw_prev;
556 u32 peer_nss;
557 s8 rssi_beacon;
558
559 /* For now the assoc link will be considered primary */
560 bool is_assoc_link;
561
562 /* for firmware use only */
563 u8 link_idx;
564 };
565
566 struct ath12k_reoq_buf {
567 void *vaddr;
568 dma_addr_t paddr_aligned;
569 u32 size;
570 };
571
572 struct ath12k_sta {
573 struct ath12k_vif *ahvif;
574 enum hal_pn_type pn_type;
575 struct ath12k_link_sta deflink;
576 struct ath12k_link_sta __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS];
577 /* indicates bitmap of link sta created in FW */
578 u16 links_map;
579 u8 assoc_link_id;
580 u16 ml_peer_id;
581 u8 num_peer;
582
583 enum ieee80211_sta_state state;
584
585 struct ath12k_reoq_buf reoq_bufs[IEEE80211_NUM_TIDS + 1];
586 };
587
588 #define ATH12K_HALF_20MHZ_BW 10
589 #define ATH12K_2GHZ_MIN_CENTER 2412
590 #define ATH12K_2GHZ_MAX_CENTER 2484
591 #define ATH12K_5GHZ_MIN_CENTER 4900
592 #define ATH12K_5GHZ_MAX_CENTER 5920
593 #define ATH12K_6GHZ_MIN_CENTER 5935
594 #define ATH12K_6GHZ_MAX_CENTER 7115
595 #define ATH12K_MIN_2GHZ_FREQ (ATH12K_2GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW - 1)
596 #define ATH12K_MAX_2GHZ_FREQ (ATH12K_2GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW + 1)
597 #define ATH12K_MIN_5GHZ_FREQ (ATH12K_5GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW)
598 #define ATH12K_MAX_5GHZ_FREQ (ATH12K_5GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW)
599 #define ATH12K_MIN_6GHZ_FREQ (ATH12K_6GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW)
600 #define ATH12K_MAX_6GHZ_FREQ (ATH12K_6GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW)
601 #define ATH12K_NUM_CHANS 101
602 #define ATH12K_MAX_5GHZ_CHAN 173
603
ath12k_is_2ghz_channel_freq(u32 freq)604 static inline bool ath12k_is_2ghz_channel_freq(u32 freq)
605 {
606 return freq >= ATH12K_MIN_2GHZ_FREQ &&
607 freq <= ATH12K_MAX_2GHZ_FREQ;
608 }
609
610 enum ath12k_hw_state {
611 ATH12K_HW_STATE_OFF,
612 ATH12K_HW_STATE_ON,
613 ATH12K_HW_STATE_RESTARTING,
614 ATH12K_HW_STATE_RESTARTED,
615 ATH12K_HW_STATE_WEDGED,
616 ATH12K_HW_STATE_TM,
617 /* Add other states as required */
618 };
619
620 /* Antenna noise floor */
621 #define ATH12K_DEFAULT_NOISE_FLOOR -95
622
623 struct ath12k_ftm_event_obj {
624 u32 data_pos;
625 u32 expected_seq;
626 u8 *eventdata;
627 };
628
629 struct ath12k_fw_stats {
630 u32 pdev_id;
631 u32 stats_id;
632 struct list_head pdevs;
633 struct list_head vdevs;
634 struct list_head bcn;
635 u32 num_vdev_recvd;
636 u32 num_bcn_recvd;
637 };
638
639 struct ath12k_dbg_htt_stats {
640 enum ath12k_dbg_htt_ext_stats_type type;
641 u32 cfg_param[4];
642 u8 reset;
643 struct debug_htt_stats_req *stats_req;
644 };
645
646 struct ath12k_debug {
647 struct dentry *debugfs_pdev;
648 struct dentry *debugfs_pdev_symlink;
649 struct ath12k_dbg_htt_stats htt_stats;
650 enum wmi_halphy_ctrl_path_stats_id tpc_stats_type;
651 bool tpc_request;
652 struct completion tpc_complete;
653 struct wmi_tpc_stats_arg *tpc_stats;
654 u32 rx_filter;
655 bool extd_rx_stats;
656 };
657
658 struct ath12k_per_peer_tx_stats {
659 u32 succ_bytes;
660 u32 retry_bytes;
661 u32 failed_bytes;
662 u32 duration;
663 u16 succ_pkts;
664 u16 retry_pkts;
665 u16 failed_pkts;
666 u16 ru_start;
667 u16 ru_tones;
668 u8 ba_fails;
669 u8 ppdu_type;
670 u32 mu_grpid;
671 u32 mu_pos;
672 bool is_ampdu;
673 };
674
675 #define ATH12K_FLUSH_TIMEOUT (5 * HZ)
676 #define ATH12K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ)
677
678 struct ath12k {
679 struct ath12k_base *ab;
680 struct ath12k_pdev *pdev;
681 struct ath12k_hw *ah;
682 struct ath12k_wmi_pdev *wmi;
683 struct ath12k_pdev_dp dp;
684 u8 mac_addr[ETH_ALEN];
685 u32 ht_cap_info;
686 u32 vht_cap_info;
687 struct ath12k_he ar_he;
688 bool supports_6ghz;
689 struct {
690 struct completion started;
691 struct completion completed;
692 struct completion on_channel;
693 struct delayed_work timeout;
694 enum ath12k_scan_state state;
695 bool is_roc;
696 int roc_freq;
697 bool roc_notify;
698 struct wiphy_work vdev_clean_wk;
699 struct ath12k_link_vif *arvif;
700 } scan;
701
702 struct {
703 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
704 struct ieee80211_sband_iftype_data
705 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
706 } mac;
707
708 unsigned long dev_flags;
709 unsigned int filter_flags;
710 u32 min_tx_power;
711 u32 max_tx_power;
712 u32 txpower_limit_2g;
713 u32 txpower_limit_5g;
714 u32 txpower_scale;
715 u32 power_scale;
716 u32 chan_tx_pwr;
717 u32 num_stations;
718 u32 max_num_stations;
719
720 /* protects the radio specific data like debug stats, ppdu_stats_info stats,
721 * vdev_stop_status info, scan data, ath12k_sta info, ath12k_link_vif info,
722 * channel context data, survey info, test mode data.
723 */
724 spinlock_t data_lock;
725
726 struct list_head arvifs;
727 /* should never be NULL; needed for regular htt rx */
728 struct ieee80211_channel *rx_channel;
729
730 /* valid during scan; needed for mgmt rx during scan */
731 struct ieee80211_channel *scan_channel;
732
733 u8 cfg_tx_chainmask;
734 u8 cfg_rx_chainmask;
735 u8 num_rx_chains;
736 u8 num_tx_chains;
737 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */
738 u8 pdev_idx;
739 u8 lmac_id;
740 u8 hw_link_id;
741
742 struct completion peer_assoc_done;
743 struct completion peer_delete_done;
744
745 int install_key_status;
746 struct completion install_key_done;
747
748 int last_wmi_vdev_start_status;
749 struct completion vdev_setup_done;
750 struct completion vdev_delete_done;
751
752 int num_peers;
753 int max_num_peers;
754 u32 num_started_vdevs;
755 u32 num_created_vdevs;
756 unsigned long long allocated_vdev_map;
757
758 struct idr txmgmt_idr;
759 /* protects txmgmt_idr data */
760 spinlock_t txmgmt_idr_lock;
761 atomic_t num_pending_mgmt_tx;
762 wait_queue_head_t txmgmt_empty_waitq;
763
764 /* cycle count is reported twice for each visited channel during scan.
765 * access protected by data_lock
766 */
767 u32 survey_last_rx_clear_count;
768 u32 survey_last_cycle_count;
769
770 /* Channel info events are expected to come in pairs without and with
771 * COMPLETE flag set respectively for each channel visit during scan.
772 *
773 * However there are deviations from this rule. This flag is used to
774 * avoid reporting garbage data.
775 */
776 bool ch_info_can_report_survey;
777 struct survey_info survey[ATH12K_NUM_CHANS];
778 struct completion bss_survey_done;
779
780 struct work_struct regd_update_work;
781
782 struct wiphy_work wmi_mgmt_tx_work;
783 struct sk_buff_head wmi_mgmt_tx_queue;
784
785 struct ath12k_wow wow;
786 struct completion target_suspend;
787 bool target_suspend_ack;
788 struct ath12k_per_peer_tx_stats peer_tx_stats;
789 struct list_head ppdu_stats_info;
790 u32 ppdu_stat_list_depth;
791
792 struct ath12k_per_peer_tx_stats cached_stats;
793 u32 last_ppdu_id;
794 u32 cached_ppdu_id;
795 #ifdef CONFIG_ATH12K_DEBUGFS
796 struct ath12k_debug debug;
797 #endif
798
799 bool dfs_block_radar_events;
800 bool monitor_vdev_created;
801 bool monitor_started;
802 int monitor_vdev_id;
803
804 struct wiphy_radio_freq_range freq_range;
805
806 bool nlo_enabled;
807
808 /* Protected by wiphy::mtx lock. */
809 u32 vdev_id_11d_scan;
810 struct completion completed_11d_scan;
811 enum ath12k_11d_state state_11d;
812 u8 alpha2[REG_ALPHA2_LEN];
813 bool regdom_set_by_user;
814
815 struct completion fw_stats_complete;
816 struct completion fw_stats_done;
817
818 struct completion mlo_setup_done;
819 u32 mlo_setup_status;
820 u8 ftm_msgref;
821 struct ath12k_fw_stats fw_stats;
822 unsigned long last_tx_power_update;
823
824 s8 max_allowed_tx_power;
825 };
826
827 struct ath12k_hw {
828 struct ieee80211_hw *hw;
829 struct device *dev;
830
831 /* Protect the write operation of the hardware state ath12k_hw::state
832 * between hardware start<=>reconfigure<=>stop transitions.
833 */
834 struct mutex hw_mutex;
835 enum ath12k_hw_state state;
836 bool regd_updated;
837 bool use_6ghz_regd;
838
839 u8 num_radio;
840
841 DECLARE_BITMAP(free_ml_peer_id_map, ATH12K_MAX_MLO_PEERS);
842
843 /* protected by wiphy_lock() */
844 struct list_head ml_peers;
845
846 /* Keep last */
847 struct ath12k radio[] __aligned(sizeof(void *));
848 };
849
850 struct ath12k_band_cap {
851 u32 phy_id;
852 u32 max_bw_supported;
853 u32 ht_cap_info;
854 u32 he_cap_info[2];
855 u32 he_mcs;
856 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE];
857 struct ath12k_wmi_ppe_threshold_arg he_ppet;
858 u16 he_6ghz_capa;
859 u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE];
860 u32 eht_cap_phy_info[WMI_MAX_EHTCAP_PHY_SIZE];
861 u32 eht_mcs_20_only;
862 u32 eht_mcs_80;
863 u32 eht_mcs_160;
864 u32 eht_mcs_320;
865 struct ath12k_wmi_ppe_threshold_arg eht_ppet;
866 u32 eht_cap_info_internal;
867 };
868
869 struct ath12k_pdev_cap {
870 u32 supported_bands;
871 u32 ampdu_density;
872 u32 vht_cap;
873 u32 vht_mcs;
874 u32 he_mcs;
875 u32 tx_chain_mask;
876 u32 rx_chain_mask;
877 u32 tx_chain_mask_shift;
878 u32 rx_chain_mask_shift;
879 struct ath12k_band_cap band[NUM_NL80211_BANDS];
880 u32 eml_cap;
881 u32 mld_cap;
882 };
883
884 struct mlo_timestamp {
885 u32 info;
886 u32 sync_timestamp_lo_us;
887 u32 sync_timestamp_hi_us;
888 u32 mlo_offset_lo;
889 u32 mlo_offset_hi;
890 u32 mlo_offset_clks;
891 u32 mlo_comp_clks;
892 u32 mlo_comp_timer;
893 };
894
895 struct ath12k_pdev {
896 struct ath12k *ar;
897 u32 pdev_id;
898 u32 hw_link_id;
899 struct ath12k_pdev_cap cap;
900 u8 mac_addr[ETH_ALEN];
901 struct mlo_timestamp timestamp;
902 };
903
904 struct ath12k_fw_pdev {
905 u32 pdev_id;
906 u32 phy_id;
907 u32 supported_bands;
908 };
909
910 struct ath12k_board_data {
911 const struct firmware *fw;
912 const void *data;
913 size_t len;
914 };
915
916 struct ath12k_device_dp_tx_err_stats {
917 /* TCL Ring Descriptor unavailable */
918 u32 desc_na[DP_TCL_NUM_RING_MAX];
919 /* Other failures during dp_tx due to mem allocation failure
920 * idr unavailable etc.
921 */
922 atomic_t misc_fail;
923 };
924
925 struct ath12k_device_dp_stats {
926 u32 err_ring_pkts;
927 u32 invalid_rbm;
928 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX];
929 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX];
930 u32 hal_reo_error[DP_REO_DST_RING_MAX];
931 struct ath12k_device_dp_tx_err_stats tx_err;
932 u32 reo_rx[DP_REO_DST_RING_MAX][ATH12K_MAX_DEVICES];
933 u32 rx_wbm_rel_source[HAL_WBM_REL_SRC_MODULE_MAX][ATH12K_MAX_DEVICES];
934 u32 tqm_rel_reason[MAX_TQM_RELEASE_REASON];
935 u32 fw_tx_status[MAX_FW_TX_STATUS];
936 u32 tx_wbm_rel_source[HAL_WBM_REL_SRC_MODULE_MAX];
937 u32 tx_enqueued[DP_TCL_NUM_RING_MAX];
938 u32 tx_completed[DP_TCL_NUM_RING_MAX];
939 };
940
941 struct ath12k_reg_freq {
942 u32 start_freq;
943 u32 end_freq;
944 };
945
946 struct ath12k_mlo_memory {
947 struct target_mem_chunk chunk[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
948 int mlo_mem_size;
949 bool init_done;
950 };
951
952 struct ath12k_hw_link {
953 u8 device_id;
954 u8 pdev_idx;
955 };
956
957 /* Holds info on the group of devices that are registered as a single
958 * wiphy, protected with struct ath12k_hw_group::mutex.
959 */
960 struct ath12k_hw_group {
961 struct list_head list;
962 u8 id;
963 u8 num_devices;
964 u8 num_probed;
965 u8 num_started;
966 unsigned long flags;
967 struct ath12k_base *ab[ATH12K_MAX_DEVICES];
968
969 /* protects access to this struct */
970 struct mutex mutex;
971
972 /* Holds information of wiphy (hw) registration.
973 *
974 * In Multi/Single Link Operation case, all pdevs are registered as
975 * a single wiphy. In other (legacy/Non-MLO) cases, each pdev is
976 * registered as separate wiphys.
977 */
978 struct ath12k_hw *ah[ATH12K_GROUP_MAX_RADIO];
979 u8 num_hw;
980 bool mlo_capable;
981 struct device_node *wsi_node[ATH12K_MAX_DEVICES];
982 struct ath12k_mlo_memory mlo_mem;
983 struct ath12k_hw_link hw_links[ATH12K_GROUP_MAX_RADIO];
984 bool hw_link_id_init_done;
985 };
986
987 /* Holds WSI info specific to each device, excluding WSI group info */
988 struct ath12k_wsi_info {
989 u32 index;
990 u32 hw_link_id_base;
991 };
992
993 /* Master structure to hold the hw data which may be used in core module */
994 struct ath12k_base {
995 enum ath12k_hw_rev hw_rev;
996 struct platform_device *pdev;
997 struct device *dev;
998 struct ath12k_qmi qmi;
999 struct ath12k_wmi_base wmi_ab;
1000 struct completion fw_ready;
1001 u8 device_id;
1002 int num_radios;
1003 /* HW channel counters frequency value in hertz common to all MACs */
1004 u32 cc_freq_hz;
1005
1006 struct ath12k_dump_file_data *dump_data;
1007 size_t ath12k_coredump_len;
1008 struct work_struct dump_work;
1009
1010 struct ath12k_htc htc;
1011
1012 struct ath12k_dp dp;
1013
1014 void __iomem *mem;
1015 unsigned long mem_len;
1016
1017 void __iomem *mem_ce;
1018 u32 ce_remap_base_addr;
1019 bool ce_remap;
1020
1021 struct {
1022 enum ath12k_bus bus;
1023 const struct ath12k_hif_ops *ops;
1024 } hif;
1025
1026 struct {
1027 struct completion wakeup_completed;
1028 u32 wmi_conf_rx_decap_mode;
1029 } wow;
1030
1031 struct ath12k_ce ce;
1032 struct timer_list rx_replenish_retry;
1033 struct ath12k_hal hal;
1034 /* To synchronize core_start/core_stop */
1035 struct mutex core_lock;
1036 /* Protects data like peers */
1037 spinlock_t base_lock;
1038
1039 /* Single pdev device (struct ath12k_hw_params::single_pdev_only):
1040 *
1041 * Firmware maintains data for all bands but advertises a single
1042 * phy to the host which is stored as a single element in this
1043 * array.
1044 *
1045 * Other devices:
1046 *
1047 * This array will contain as many elements as the number of
1048 * radios.
1049 */
1050 struct ath12k_pdev pdevs[MAX_RADIOS];
1051
1052 /* struct ath12k_hw_params::single_pdev_only devices use this to
1053 * store phy specific data
1054 */
1055 struct ath12k_fw_pdev fw_pdev[MAX_RADIOS];
1056 u8 fw_pdev_count;
1057
1058 struct ath12k_pdev __rcu *pdevs_active[MAX_RADIOS];
1059
1060 struct ath12k_wmi_hal_reg_capabilities_ext_arg hal_reg_cap[MAX_RADIOS];
1061 unsigned long long free_vdev_map;
1062 unsigned long long free_vdev_stats_id_map;
1063 struct list_head peers;
1064 wait_queue_head_t peer_mapping_wq;
1065 u8 mac_addr[ETH_ALEN];
1066 bool wmi_ready;
1067 u32 wlan_init_status;
1068 int irq_num[ATH12K_IRQ_NUM_MAX];
1069 struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX];
1070 struct napi_struct *napi;
1071 struct ath12k_wmi_target_cap_arg target_caps;
1072 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE];
1073 bool pdevs_macaddr_valid;
1074
1075 const struct ath12k_hw_params *hw_params;
1076
1077 const struct firmware *cal_file;
1078
1079 /* Below regd's are protected by ab->data_lock */
1080 /* This is the regd set for every radio
1081 * by the firmware during initialization
1082 */
1083 struct ieee80211_regdomain *default_regd[MAX_RADIOS];
1084 /* This regd is set during dynamic country setting
1085 * This may or may not be used during the runtime
1086 */
1087 struct ieee80211_regdomain *new_regd[MAX_RADIOS];
1088
1089 struct ath12k_reg_info *reg_info[MAX_RADIOS];
1090
1091 /* Current DFS Regulatory */
1092 enum ath12k_dfs_region dfs_region;
1093 struct ath12k_device_dp_stats device_stats;
1094 #ifdef CONFIG_ATH12K_DEBUGFS
1095 struct dentry *debugfs_soc;
1096 #endif
1097
1098 unsigned long dev_flags;
1099 struct completion driver_recovery;
1100 struct workqueue_struct *workqueue;
1101 struct work_struct restart_work;
1102 struct workqueue_struct *workqueue_aux;
1103 struct work_struct reset_work;
1104 atomic_t reset_count;
1105 atomic_t recovery_count;
1106 bool is_reset;
1107 struct completion reset_complete;
1108 /* continuous recovery fail count */
1109 atomic_t fail_cont_count;
1110 unsigned long reset_fail_timeout;
1111 struct work_struct update_11d_work;
1112 u8 new_alpha2[2];
1113 struct {
1114 /* protected by data_lock */
1115 u32 fw_crash_counter;
1116 } stats;
1117 u32 pktlog_defs_checksum;
1118
1119 struct ath12k_dbring_cap *db_caps;
1120 u32 num_db_cap;
1121
1122 struct completion htc_suspend;
1123
1124 u64 fw_soc_drop_count;
1125 bool static_window_map;
1126
1127 struct work_struct rfkill_work;
1128 /* true means radio is on */
1129 bool rfkill_radio_on;
1130
1131 struct {
1132 enum ath12k_bdf_search bdf_search;
1133 u32 vendor;
1134 u32 device;
1135 u32 subsystem_vendor;
1136 u32 subsystem_device;
1137 } id;
1138
1139 struct {
1140 u32 api_version;
1141
1142 const struct firmware *fw;
1143 const u8 *amss_data;
1144 size_t amss_len;
1145 const u8 *amss_dualmac_data;
1146 size_t amss_dualmac_len;
1147 const u8 *m3_data;
1148 size_t m3_len;
1149
1150 DECLARE_BITMAP(fw_features, ATH12K_FW_FEATURE_COUNT);
1151 bool fw_features_valid;
1152 } fw;
1153
1154 const struct hal_rx_ops *hal_rx_ops;
1155
1156 struct completion restart_completed;
1157
1158 #ifdef CONFIG_ACPI
1159
1160 struct {
1161 bool started;
1162 u32 func_bit;
1163 bool acpi_tas_enable;
1164 bool acpi_bios_sar_enable;
1165 bool acpi_disable_11be;
1166 bool acpi_disable_rfkill;
1167 bool acpi_cca_enable;
1168 bool acpi_band_edge_enable;
1169 bool acpi_enable_bdf;
1170 u32 bit_flag;
1171 char bdf_string[ATH12K_ACPI_BDF_MAX_LEN];
1172 u8 tas_cfg[ATH12K_ACPI_DSM_TAS_CFG_SIZE];
1173 u8 tas_sar_power_table[ATH12K_ACPI_DSM_TAS_DATA_SIZE];
1174 u8 bios_sar_data[ATH12K_ACPI_DSM_BIOS_SAR_DATA_SIZE];
1175 u8 geo_offset_data[ATH12K_ACPI_DSM_GEO_OFFSET_DATA_SIZE];
1176 u8 cca_data[ATH12K_ACPI_DSM_CCA_DATA_SIZE];
1177 u8 band_edge_power[ATH12K_ACPI_DSM_BAND_EDGE_DATA_SIZE];
1178 } acpi;
1179
1180 #endif /* CONFIG_ACPI */
1181
1182 struct notifier_block panic_nb;
1183
1184 struct ath12k_hw_group *ag;
1185 struct ath12k_wsi_info wsi_info;
1186 enum ath12k_firmware_mode fw_mode;
1187 struct ath12k_ftm_event_obj ftm_event_obj;
1188 bool hw_group_ref;
1189
1190 /* Denote whether MLO is possible within the device */
1191 bool single_chip_mlo_support;
1192
1193 struct ath12k_reg_freq reg_freq_2ghz;
1194 struct ath12k_reg_freq reg_freq_5ghz;
1195 struct ath12k_reg_freq reg_freq_6ghz;
1196
1197 /* must be last */
1198 u8 drv_priv[] __aligned(sizeof(void *));
1199 };
1200
1201 struct ath12k_pdev_map {
1202 struct ath12k_base *ab;
1203 u8 pdev_idx;
1204 };
1205
1206 struct ath12k_fw_stats_vdev {
1207 struct list_head list;
1208
1209 u32 vdev_id;
1210 u32 beacon_snr;
1211 u32 data_snr;
1212 u32 num_tx_frames[WLAN_MAX_AC];
1213 u32 num_rx_frames;
1214 u32 num_tx_frames_retries[WLAN_MAX_AC];
1215 u32 num_tx_frames_failures[WLAN_MAX_AC];
1216 u32 num_rts_fail;
1217 u32 num_rts_success;
1218 u32 num_rx_err;
1219 u32 num_rx_discard;
1220 u32 num_tx_not_acked;
1221 u32 tx_rate_history[MAX_TX_RATE_VALUES];
1222 u32 beacon_rssi_history[MAX_TX_RATE_VALUES];
1223 };
1224
1225 struct ath12k_fw_stats_bcn {
1226 struct list_head list;
1227
1228 u32 vdev_id;
1229 u32 tx_bcn_succ_cnt;
1230 u32 tx_bcn_outage_cnt;
1231 };
1232
1233 struct ath12k_fw_stats_pdev {
1234 struct list_head list;
1235
1236 /* PDEV stats */
1237 s32 ch_noise_floor;
1238 u32 tx_frame_count;
1239 u32 rx_frame_count;
1240 u32 rx_clear_count;
1241 u32 cycle_count;
1242 u32 phy_err_count;
1243 u32 chan_tx_power;
1244 u32 ack_rx_bad;
1245 u32 rts_bad;
1246 u32 rts_good;
1247 u32 fcs_bad;
1248 u32 no_beacons;
1249 u32 mib_int_count;
1250
1251 /* PDEV TX stats */
1252 s32 comp_queued;
1253 s32 comp_delivered;
1254 s32 msdu_enqued;
1255 s32 mpdu_enqued;
1256 s32 wmm_drop;
1257 s32 local_enqued;
1258 s32 local_freed;
1259 s32 hw_queued;
1260 s32 hw_reaped;
1261 s32 underrun;
1262 s32 tx_abort;
1263 s32 mpdus_requed;
1264 u32 tx_ko;
1265 u32 data_rc;
1266 u32 self_triggers;
1267 u32 sw_retry_failure;
1268 u32 illgl_rate_phy_err;
1269 u32 pdev_cont_xretry;
1270 u32 pdev_tx_timeout;
1271 u32 pdev_resets;
1272 u32 stateless_tid_alloc_failure;
1273 u32 phy_underrun;
1274 u32 txop_ovf;
1275
1276 /* PDEV RX stats */
1277 s32 mid_ppdu_route_change;
1278 s32 status_rcvd;
1279 s32 r0_frags;
1280 s32 r1_frags;
1281 s32 r2_frags;
1282 s32 r3_frags;
1283 s32 htt_msdus;
1284 s32 htt_mpdus;
1285 s32 loc_msdus;
1286 s32 loc_mpdus;
1287 s32 oversize_amsdu;
1288 s32 phy_errs;
1289 s32 phy_err_drop;
1290 s32 mpdu_errs;
1291 };
1292
1293 int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab);
1294 void ath12k_core_hw_group_cleanup(struct ath12k_hw_group *ag);
1295 int ath12k_core_pre_init(struct ath12k_base *ab);
1296 int ath12k_core_init(struct ath12k_base *ath12k);
1297 void ath12k_core_deinit(struct ath12k_base *ath12k);
1298 struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size,
1299 enum ath12k_bus bus);
1300 void ath12k_core_free(struct ath12k_base *ath12k);
1301 int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab,
1302 struct ath12k_board_data *bd,
1303 char *filename);
1304 int ath12k_core_fetch_bdf(struct ath12k_base *ath12k,
1305 struct ath12k_board_data *bd);
1306 void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd);
1307 int ath12k_core_fetch_regdb(struct ath12k_base *ab, struct ath12k_board_data *bd);
1308 int ath12k_core_check_dt(struct ath12k_base *ath12k);
1309 int ath12k_core_check_smbios(struct ath12k_base *ab);
1310 void ath12k_core_halt(struct ath12k *ar);
1311 int ath12k_core_resume_early(struct ath12k_base *ab);
1312 int ath12k_core_resume(struct ath12k_base *ab);
1313 int ath12k_core_suspend(struct ath12k_base *ab);
1314 int ath12k_core_suspend_late(struct ath12k_base *ab);
1315 void ath12k_core_hw_group_unassign(struct ath12k_base *ab);
1316 u8 ath12k_get_num_partner_link(struct ath12k *ar);
1317
1318 const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab,
1319 const char *filename);
1320 u32 ath12k_core_get_max_station_per_radio(struct ath12k_base *ab);
1321 u32 ath12k_core_get_max_peers_per_radio(struct ath12k_base *ab);
1322 u32 ath12k_core_get_max_num_tids(struct ath12k_base *ab);
1323
1324 void ath12k_core_hw_group_set_mlo_capable(struct ath12k_hw_group *ag);
1325 void ath12k_fw_stats_init(struct ath12k *ar);
1326 void ath12k_fw_stats_bcn_free(struct list_head *head);
1327 void ath12k_fw_stats_free(struct ath12k_fw_stats *stats);
1328 void ath12k_fw_stats_reset(struct ath12k *ar);
1329 struct reserved_mem *ath12k_core_get_reserved_mem(struct ath12k_base *ab,
1330 int index);
1331
ath12k_scan_state_str(enum ath12k_scan_state state)1332 static inline const char *ath12k_scan_state_str(enum ath12k_scan_state state)
1333 {
1334 switch (state) {
1335 case ATH12K_SCAN_IDLE:
1336 return "idle";
1337 case ATH12K_SCAN_STARTING:
1338 return "starting";
1339 case ATH12K_SCAN_RUNNING:
1340 return "running";
1341 case ATH12K_SCAN_ABORTING:
1342 return "aborting";
1343 }
1344
1345 return "unknown";
1346 }
1347
ATH12K_SKB_CB(struct sk_buff * skb)1348 static inline struct ath12k_skb_cb *ATH12K_SKB_CB(struct sk_buff *skb)
1349 {
1350 BUILD_BUG_ON(sizeof(struct ath12k_skb_cb) >
1351 IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
1352 return (struct ath12k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
1353 }
1354
ATH12K_SKB_RXCB(struct sk_buff * skb)1355 static inline struct ath12k_skb_rxcb *ATH12K_SKB_RXCB(struct sk_buff *skb)
1356 {
1357 BUILD_BUG_ON(sizeof(struct ath12k_skb_rxcb) > sizeof(skb->cb));
1358 return (struct ath12k_skb_rxcb *)skb->cb;
1359 }
1360
ath12k_vif_to_ahvif(struct ieee80211_vif * vif)1361 static inline struct ath12k_vif *ath12k_vif_to_ahvif(struct ieee80211_vif *vif)
1362 {
1363 return (struct ath12k_vif *)vif->drv_priv;
1364 }
1365
ath12k_sta_to_ahsta(struct ieee80211_sta * sta)1366 static inline struct ath12k_sta *ath12k_sta_to_ahsta(struct ieee80211_sta *sta)
1367 {
1368 return (struct ath12k_sta *)sta->drv_priv;
1369 }
1370
ath12k_ahsta_to_sta(struct ath12k_sta * ahsta)1371 static inline struct ieee80211_sta *ath12k_ahsta_to_sta(struct ath12k_sta *ahsta)
1372 {
1373 return container_of((void *)ahsta, struct ieee80211_sta, drv_priv);
1374 }
1375
ath12k_ahvif_to_vif(struct ath12k_vif * ahvif)1376 static inline struct ieee80211_vif *ath12k_ahvif_to_vif(struct ath12k_vif *ahvif)
1377 {
1378 return container_of((void *)ahvif, struct ieee80211_vif, drv_priv);
1379 }
1380
ath12k_ab_to_ar(struct ath12k_base * ab,int mac_id)1381 static inline struct ath12k *ath12k_ab_to_ar(struct ath12k_base *ab,
1382 int mac_id)
1383 {
1384 return ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar;
1385 }
1386
ath12k_core_create_firmware_path(struct ath12k_base * ab,const char * filename,void * buf,size_t buf_len)1387 static inline void ath12k_core_create_firmware_path(struct ath12k_base *ab,
1388 const char *filename,
1389 void *buf, size_t buf_len)
1390 {
1391 const char *fw_name = NULL;
1392
1393 of_property_read_string(ab->dev->of_node, "firmware-name", &fw_name);
1394
1395 if (fw_name && strncmp(filename, "board", 5))
1396 snprintf(buf, buf_len, "%s/%s/%s/%s", ATH12K_FW_DIR,
1397 ab->hw_params->fw.dir, fw_name, filename);
1398 else
1399 snprintf(buf, buf_len, "%s/%s/%s", ATH12K_FW_DIR,
1400 ab->hw_params->fw.dir, filename);
1401 }
1402
ath12k_bus_str(enum ath12k_bus bus)1403 static inline const char *ath12k_bus_str(enum ath12k_bus bus)
1404 {
1405 switch (bus) {
1406 case ATH12K_BUS_PCI:
1407 return "pci";
1408 case ATH12K_BUS_AHB:
1409 return "ahb";
1410 }
1411
1412 return "unknown";
1413 }
1414
ath12k_hw_to_ah(struct ieee80211_hw * hw)1415 static inline struct ath12k_hw *ath12k_hw_to_ah(struct ieee80211_hw *hw)
1416 {
1417 return hw->priv;
1418 }
1419
ath12k_ah_to_ar(struct ath12k_hw * ah,u8 hw_link_id)1420 static inline struct ath12k *ath12k_ah_to_ar(struct ath12k_hw *ah, u8 hw_link_id)
1421 {
1422 if (WARN(hw_link_id >= ah->num_radio,
1423 "bad hw link id %d, so switch to default link\n", hw_link_id))
1424 hw_link_id = 0;
1425
1426 return &ah->radio[hw_link_id];
1427 }
1428
ath12k_ar_to_ah(struct ath12k * ar)1429 static inline struct ath12k_hw *ath12k_ar_to_ah(struct ath12k *ar)
1430 {
1431 return ar->ah;
1432 }
1433
ath12k_ar_to_hw(struct ath12k * ar)1434 static inline struct ieee80211_hw *ath12k_ar_to_hw(struct ath12k *ar)
1435 {
1436 return ar->ah->hw;
1437 }
1438
1439 #define for_each_ar(ah, ar, index) \
1440 for ((index) = 0; ((index) < (ah)->num_radio && \
1441 ((ar) = &(ah)->radio[(index)])); (index)++)
1442
ath12k_ag_to_ah(struct ath12k_hw_group * ag,int idx)1443 static inline struct ath12k_hw *ath12k_ag_to_ah(struct ath12k_hw_group *ag, int idx)
1444 {
1445 return ag->ah[idx];
1446 }
1447
ath12k_ag_set_ah(struct ath12k_hw_group * ag,int idx,struct ath12k_hw * ah)1448 static inline void ath12k_ag_set_ah(struct ath12k_hw_group *ag, int idx,
1449 struct ath12k_hw *ah)
1450 {
1451 ag->ah[idx] = ah;
1452 }
1453
ath12k_ab_to_ag(struct ath12k_base * ab)1454 static inline struct ath12k_hw_group *ath12k_ab_to_ag(struct ath12k_base *ab)
1455 {
1456 return ab->ag;
1457 }
1458
ath12k_ag_to_ab(struct ath12k_hw_group * ag,u8 device_id)1459 static inline struct ath12k_base *ath12k_ag_to_ab(struct ath12k_hw_group *ag,
1460 u8 device_id)
1461 {
1462 return ag->ab[device_id];
1463 }
1464
1465 #endif /* _CORE_H_ */
1466