1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/msi.h> 9 #include <linux/pci.h> 10 #include <linux/of.h> 11 #include <linux/time.h> 12 #include <linux/vmalloc.h> 13 14 #include "pci.h" 15 #include "core.h" 16 #include "hif.h" 17 #include "mhi.h" 18 #include "debug.h" 19 #include "pcic.h" 20 #include "qmi.h" 21 22 #define ATH11K_PCI_BAR_NUM 0 23 #define ATH11K_PCI_DMA_MASK 36 24 #define ATH11K_PCI_COHERENT_DMA_MASK 32 25 26 #define TCSR_SOC_HW_VERSION 0x0224 27 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8) 28 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0) 29 30 #define QCA6390_DEVICE_ID 0x1101 31 #define QCN9074_DEVICE_ID 0x1104 32 #define WCN6855_DEVICE_ID 0x1103 33 34 #define TCSR_SOC_HW_SUB_VER 0x1910010 35 36 static const struct pci_device_id ath11k_pci_id_table[] = { 37 { PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) }, 38 { PCI_VDEVICE(QCOM, WCN6855_DEVICE_ID) }, 39 { PCI_VDEVICE(QCOM, QCN9074_DEVICE_ID) }, 40 {} 41 }; 42 43 MODULE_DEVICE_TABLE(pci, ath11k_pci_id_table); 44 45 static int ath11k_pci_bus_wake_up(struct ath11k_base *ab) 46 { 47 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 48 49 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); 50 } 51 52 static void ath11k_pci_bus_release(struct ath11k_base *ab) 53 { 54 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 55 56 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); 57 } 58 59 static u32 ath11k_pci_get_window_start(struct ath11k_base *ab, u32 offset) 60 { 61 if (!ab->hw_params.static_window_map) 62 return ATH11K_PCI_WINDOW_START; 63 64 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK) 65 /* if offset lies within DP register range, use 3rd window */ 66 return 3 * ATH11K_PCI_WINDOW_START; 67 else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) < 68 ATH11K_PCI_WINDOW_RANGE_MASK) 69 /* if offset lies within CE register range, use 2nd window */ 70 return 2 * ATH11K_PCI_WINDOW_START; 71 else 72 return ATH11K_PCI_WINDOW_START; 73 } 74 75 static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset) 76 { 77 struct ath11k_base *ab = ab_pci->ab; 78 79 u32 window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset); 80 81 lockdep_assert_held(&ab_pci->window_lock); 82 83 if (window != ab_pci->register_window) { 84 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window, 85 ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS); 86 ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS); 87 ab_pci->register_window = window; 88 } 89 } 90 91 static void 92 ath11k_pci_window_write32(struct ath11k_base *ab, u32 offset, u32 value) 93 { 94 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 95 u32 window_start; 96 97 window_start = ath11k_pci_get_window_start(ab, offset); 98 99 if (window_start == ATH11K_PCI_WINDOW_START) { 100 spin_lock_bh(&ab_pci->window_lock); 101 ath11k_pci_select_window(ab_pci, offset); 102 iowrite32(value, ab->mem + window_start + 103 (offset & ATH11K_PCI_WINDOW_RANGE_MASK)); 104 spin_unlock_bh(&ab_pci->window_lock); 105 } else { 106 iowrite32(value, ab->mem + window_start + 107 (offset & ATH11K_PCI_WINDOW_RANGE_MASK)); 108 } 109 } 110 111 static u32 ath11k_pci_window_read32(struct ath11k_base *ab, u32 offset) 112 { 113 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 114 u32 window_start, val; 115 116 window_start = ath11k_pci_get_window_start(ab, offset); 117 118 if (window_start == ATH11K_PCI_WINDOW_START) { 119 spin_lock_bh(&ab_pci->window_lock); 120 ath11k_pci_select_window(ab_pci, offset); 121 val = ioread32(ab->mem + window_start + 122 (offset & ATH11K_PCI_WINDOW_RANGE_MASK)); 123 spin_unlock_bh(&ab_pci->window_lock); 124 } else { 125 val = ioread32(ab->mem + window_start + 126 (offset & ATH11K_PCI_WINDOW_RANGE_MASK)); 127 } 128 129 return val; 130 } 131 132 int ath11k_pci_get_msi_irq(struct ath11k_base *ab, unsigned int vector) 133 { 134 struct pci_dev *pci_dev = to_pci_dev(ab->dev); 135 136 return pci_irq_vector(pci_dev, vector); 137 } 138 139 static const struct ath11k_pci_ops ath11k_pci_ops_qca6390 = { 140 .wakeup = ath11k_pci_bus_wake_up, 141 .release = ath11k_pci_bus_release, 142 .get_msi_irq = ath11k_pci_get_msi_irq, 143 .window_write32 = ath11k_pci_window_write32, 144 .window_read32 = ath11k_pci_window_read32, 145 }; 146 147 static const struct ath11k_pci_ops ath11k_pci_ops_qcn9074 = { 148 .wakeup = NULL, 149 .release = NULL, 150 .get_msi_irq = ath11k_pci_get_msi_irq, 151 .window_write32 = ath11k_pci_window_write32, 152 .window_read32 = ath11k_pci_window_read32, 153 }; 154 155 static const struct ath11k_msi_config msi_config_one_msi = { 156 .total_vectors = 1, 157 .total_users = 4, 158 .users = (struct ath11k_msi_user[]) { 159 { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, 160 { .name = "CE", .num_vectors = 1, .base_vector = 0 }, 161 { .name = "WAKE", .num_vectors = 1, .base_vector = 0 }, 162 { .name = "DP", .num_vectors = 1, .base_vector = 0 }, 163 }, 164 }; 165 166 static inline void ath11k_pci_select_static_window(struct ath11k_pci *ab_pci) 167 { 168 u32 umac_window; 169 u32 ce_window; 170 u32 window; 171 172 umac_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET); 173 ce_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE); 174 window = (umac_window << 12) | (ce_window << 6); 175 176 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window, 177 ab_pci->ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS); 178 } 179 180 static void ath11k_pci_restore_window(struct ath11k_base *ab) 181 { 182 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 183 184 spin_lock_bh(&ab_pci->window_lock); 185 186 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | ab_pci->register_window, 187 ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS); 188 ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS); 189 190 spin_unlock_bh(&ab_pci->window_lock); 191 } 192 193 static void ath11k_pci_soc_global_reset(struct ath11k_base *ab) 194 { 195 u32 val, delay; 196 197 val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET); 198 199 val |= PCIE_SOC_GLOBAL_RESET_V; 200 201 ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 202 203 /* TODO: exact time to sleep is uncertain */ 204 delay = 10; 205 mdelay(delay); 206 207 /* Need to toggle V bit back otherwise stuck in reset status */ 208 val &= ~PCIE_SOC_GLOBAL_RESET_V; 209 210 ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 211 212 mdelay(delay); 213 214 val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET); 215 if (val == 0xffffffff) 216 ath11k_warn(ab, "link down error during global reset\n"); 217 218 /* Restore window register as its content is cleared during 219 * hardware global reset, such that it aligns with host cache. 220 */ 221 ath11k_pci_restore_window(ab); 222 } 223 224 static void ath11k_pci_clear_dbg_registers(struct ath11k_base *ab) 225 { 226 u32 val; 227 228 /* read cookie */ 229 val = ath11k_pcic_read32(ab, PCIE_Q6_COOKIE_ADDR); 230 ath11k_dbg(ab, ATH11K_DBG_PCI, "pcie_q6_cookie_addr 0x%x\n", val); 231 232 val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY); 233 ath11k_dbg(ab, ATH11K_DBG_PCI, "wlaon_warm_sw_entry 0x%x\n", val); 234 235 /* TODO: exact time to sleep is uncertain */ 236 mdelay(10); 237 238 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from 239 * continuing warm path and entering dead loop. 240 */ 241 ath11k_pcic_write32(ab, WLAON_WARM_SW_ENTRY, 0); 242 mdelay(10); 243 244 val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY); 245 ath11k_dbg(ab, ATH11K_DBG_PCI, "wlaon_warm_sw_entry 0x%x\n", val); 246 247 /* A read clear register. clear the register to prevent 248 * Q6 from entering wrong code path. 249 */ 250 val = ath11k_pcic_read32(ab, WLAON_SOC_RESET_CAUSE_REG); 251 ath11k_dbg(ab, ATH11K_DBG_PCI, "soc reset cause %d\n", val); 252 } 253 254 static int ath11k_pci_set_link_reg(struct ath11k_base *ab, 255 u32 offset, u32 value, u32 mask) 256 { 257 u32 v; 258 int i; 259 260 v = ath11k_pcic_read32(ab, offset); 261 if ((v & mask) == value) 262 return 0; 263 264 for (i = 0; i < 10; i++) { 265 ath11k_pcic_write32(ab, offset, (v & ~mask) | value); 266 267 v = ath11k_pcic_read32(ab, offset); 268 if ((v & mask) == value) 269 return 0; 270 271 mdelay(2); 272 } 273 274 ath11k_warn(ab, "failed to set pcie link register 0x%08x: 0x%08x != 0x%08x\n", 275 offset, v & mask, value); 276 277 return -ETIMEDOUT; 278 } 279 280 static int ath11k_pci_fix_l1ss(struct ath11k_base *ab) 281 { 282 int ret; 283 284 ret = ath11k_pci_set_link_reg(ab, 285 PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(ab), 286 PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL, 287 PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK); 288 if (ret) { 289 ath11k_warn(ab, "failed to set sysclk: %d\n", ret); 290 return ret; 291 } 292 293 ret = ath11k_pci_set_link_reg(ab, 294 PCIE_PCS_OSC_DTCT_CONFIG1_REG(ab), 295 PCIE_PCS_OSC_DTCT_CONFIG1_VAL, 296 PCIE_PCS_OSC_DTCT_CONFIG_MSK); 297 if (ret) { 298 ath11k_warn(ab, "failed to set dtct config1 error: %d\n", ret); 299 return ret; 300 } 301 302 ret = ath11k_pci_set_link_reg(ab, 303 PCIE_PCS_OSC_DTCT_CONFIG2_REG(ab), 304 PCIE_PCS_OSC_DTCT_CONFIG2_VAL, 305 PCIE_PCS_OSC_DTCT_CONFIG_MSK); 306 if (ret) { 307 ath11k_warn(ab, "failed to set dtct config2: %d\n", ret); 308 return ret; 309 } 310 311 ret = ath11k_pci_set_link_reg(ab, 312 PCIE_PCS_OSC_DTCT_CONFIG4_REG(ab), 313 PCIE_PCS_OSC_DTCT_CONFIG4_VAL, 314 PCIE_PCS_OSC_DTCT_CONFIG_MSK); 315 if (ret) { 316 ath11k_warn(ab, "failed to set dtct config4: %d\n", ret); 317 return ret; 318 } 319 320 return 0; 321 } 322 323 static void ath11k_pci_enable_ltssm(struct ath11k_base *ab) 324 { 325 u32 val; 326 int i; 327 328 val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM); 329 330 /* PCIE link seems very unstable after the Hot Reset*/ 331 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) { 332 if (val == 0xffffffff) 333 mdelay(5); 334 335 ath11k_pcic_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE); 336 val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM); 337 } 338 339 ath11k_dbg(ab, ATH11K_DBG_PCI, "ltssm 0x%x\n", val); 340 341 val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST); 342 val |= GCC_GCC_PCIE_HOT_RST_VAL; 343 ath11k_pcic_write32(ab, GCC_GCC_PCIE_HOT_RST, val); 344 val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST); 345 346 ath11k_dbg(ab, ATH11K_DBG_PCI, "pcie_hot_rst 0x%x\n", val); 347 348 mdelay(5); 349 } 350 351 static void ath11k_pci_clear_all_intrs(struct ath11k_base *ab) 352 { 353 /* This is a WAR for PCIE Hotreset. 354 * When target receive Hotreset, but will set the interrupt. 355 * So when download SBL again, SBL will open Interrupt and 356 * receive it, and crash immediately. 357 */ 358 ath11k_pcic_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL); 359 } 360 361 static void ath11k_pci_set_wlaon_pwr_ctrl(struct ath11k_base *ab) 362 { 363 u32 val; 364 365 val = ath11k_pcic_read32(ab, WLAON_QFPROM_PWR_CTRL_REG); 366 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK; 367 ath11k_pcic_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val); 368 } 369 370 static void ath11k_pci_force_wake(struct ath11k_base *ab) 371 { 372 ath11k_pcic_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1); 373 mdelay(5); 374 } 375 376 static void ath11k_pci_sw_reset(struct ath11k_base *ab, bool power_on) 377 { 378 mdelay(100); 379 380 if (power_on) { 381 ath11k_pci_enable_ltssm(ab); 382 ath11k_pci_clear_all_intrs(ab); 383 ath11k_pci_set_wlaon_pwr_ctrl(ab); 384 if (ab->hw_params.fix_l1ss) 385 ath11k_pci_fix_l1ss(ab); 386 } 387 388 ath11k_mhi_clear_vector(ab); 389 ath11k_pci_clear_dbg_registers(ab); 390 ath11k_pci_soc_global_reset(ab); 391 ath11k_mhi_set_mhictrl_reset(ab); 392 } 393 394 static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab) 395 { 396 struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; 397 398 cfg->tgt_ce = ab->hw_params.target_ce_config; 399 cfg->tgt_ce_len = ab->hw_params.target_ce_count; 400 401 cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map; 402 cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len; 403 ab->qmi.service_ins_id = ab->hw_params.qmi_service_ins_id; 404 405 ath11k_ce_get_shadow_config(ab, &cfg->shadow_reg_v2, 406 &cfg->shadow_reg_v2_len); 407 } 408 409 static void ath11k_pci_msi_config(struct ath11k_pci *ab_pci, bool enable) 410 { 411 struct pci_dev *dev = ab_pci->pdev; 412 u16 control; 413 414 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); 415 416 if (enable) 417 control |= PCI_MSI_FLAGS_ENABLE; 418 else 419 control &= ~PCI_MSI_FLAGS_ENABLE; 420 421 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); 422 } 423 424 static void ath11k_pci_msi_enable(struct ath11k_pci *ab_pci) 425 { 426 ath11k_pci_msi_config(ab_pci, true); 427 } 428 429 static void ath11k_pci_msi_disable(struct ath11k_pci *ab_pci) 430 { 431 ath11k_pci_msi_config(ab_pci, false); 432 } 433 434 static int ath11k_pci_alloc_msi(struct ath11k_pci *ab_pci) 435 { 436 struct ath11k_base *ab = ab_pci->ab; 437 const struct ath11k_msi_config *msi_config = ab->pci.msi.config; 438 struct pci_dev *pci_dev = ab_pci->pdev; 439 struct msi_desc *msi_desc; 440 int num_vectors; 441 int ret; 442 443 num_vectors = pci_alloc_irq_vectors(pci_dev, 444 msi_config->total_vectors, 445 msi_config->total_vectors, 446 PCI_IRQ_MSI); 447 if (num_vectors == msi_config->total_vectors) { 448 set_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags); 449 } else { 450 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, 451 1, 452 1, 453 PCI_IRQ_MSI); 454 if (num_vectors < 0) { 455 ret = -EINVAL; 456 goto reset_msi_config; 457 } 458 clear_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags); 459 ab->pci.msi.config = &msi_config_one_msi; 460 ath11k_dbg(ab, ATH11K_DBG_PCI, "request one msi vector\n"); 461 } 462 ath11k_info(ab, "MSI vectors: %d\n", num_vectors); 463 464 ath11k_pci_msi_disable(ab_pci); 465 466 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 467 if (!msi_desc) { 468 ath11k_err(ab, "msi_desc is NULL!\n"); 469 ret = -EINVAL; 470 goto free_msi_vector; 471 } 472 473 ab->pci.msi.ep_base_data = msi_desc->msg.data; 474 475 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO, 476 &ab->pci.msi.addr_lo); 477 478 if (msi_desc->pci.msi_attrib.is_64) { 479 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI, 480 &ab->pci.msi.addr_hi); 481 } else { 482 ab->pci.msi.addr_hi = 0; 483 } 484 485 ath11k_dbg(ab, ATH11K_DBG_PCI, "msi base data is %d\n", ab->pci.msi.ep_base_data); 486 487 return 0; 488 489 free_msi_vector: 490 pci_free_irq_vectors(ab_pci->pdev); 491 492 reset_msi_config: 493 return ret; 494 } 495 496 static void ath11k_pci_free_msi(struct ath11k_pci *ab_pci) 497 { 498 pci_free_irq_vectors(ab_pci->pdev); 499 } 500 501 static int ath11k_pci_config_msi_data(struct ath11k_pci *ab_pci) 502 { 503 struct msi_desc *msi_desc; 504 505 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 506 if (!msi_desc) { 507 ath11k_err(ab_pci->ab, "msi_desc is NULL!\n"); 508 pci_free_irq_vectors(ab_pci->pdev); 509 return -EINVAL; 510 } 511 512 ab_pci->ab->pci.msi.ep_base_data = msi_desc->msg.data; 513 514 ath11k_dbg(ab_pci->ab, ATH11K_DBG_PCI, "after request_irq msi_ep_base_data %d\n", 515 ab_pci->ab->pci.msi.ep_base_data); 516 517 return 0; 518 } 519 520 static int ath11k_pci_claim(struct ath11k_pci *ab_pci, struct pci_dev *pdev) 521 { 522 struct ath11k_base *ab = ab_pci->ab; 523 u16 device_id; 524 int ret = 0; 525 526 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); 527 if (device_id != ab_pci->dev_id) { 528 ath11k_err(ab, "pci device id mismatch: 0x%x 0x%x\n", 529 device_id, ab_pci->dev_id); 530 ret = -EIO; 531 goto out; 532 } 533 534 ret = pci_assign_resource(pdev, ATH11K_PCI_BAR_NUM); 535 if (ret) { 536 ath11k_err(ab, "failed to assign pci resource: %d\n", ret); 537 goto out; 538 } 539 540 ret = pci_enable_device(pdev); 541 if (ret) { 542 ath11k_err(ab, "failed to enable pci device: %d\n", ret); 543 goto out; 544 } 545 546 ret = pci_request_region(pdev, ATH11K_PCI_BAR_NUM, "ath11k_pci"); 547 if (ret) { 548 ath11k_err(ab, "failed to request pci region: %d\n", ret); 549 goto disable_device; 550 } 551 552 ret = dma_set_mask(&pdev->dev, 553 DMA_BIT_MASK(ATH11K_PCI_DMA_MASK)); 554 if (ret) { 555 ath11k_err(ab, "failed to set pci dma mask to %d: %d\n", 556 ATH11K_PCI_DMA_MASK, ret); 557 goto release_region; 558 } 559 560 ab_pci->dma_mask = DMA_BIT_MASK(ATH11K_PCI_DMA_MASK); 561 562 ret = dma_set_coherent_mask(&pdev->dev, 563 DMA_BIT_MASK(ATH11K_PCI_COHERENT_DMA_MASK)); 564 if (ret) { 565 ath11k_err(ab, "failed to set pci coherent dma mask to %d: %d\n", 566 ATH11K_PCI_COHERENT_DMA_MASK, ret); 567 goto release_region; 568 } 569 570 pci_set_master(pdev); 571 572 ab->mem_len = pci_resource_len(pdev, ATH11K_PCI_BAR_NUM); 573 ab->mem = pci_iomap(pdev, ATH11K_PCI_BAR_NUM, 0); 574 if (!ab->mem) { 575 ath11k_err(ab, "failed to map pci bar %d\n", ATH11K_PCI_BAR_NUM); 576 ret = -EIO; 577 goto release_region; 578 } 579 580 ab->mem_ce = ab->mem; 581 582 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pci_mem 0x%p\n", ab->mem); 583 return 0; 584 585 release_region: 586 pci_release_region(pdev, ATH11K_PCI_BAR_NUM); 587 disable_device: 588 pci_disable_device(pdev); 589 out: 590 return ret; 591 } 592 593 static void ath11k_pci_free_region(struct ath11k_pci *ab_pci) 594 { 595 struct ath11k_base *ab = ab_pci->ab; 596 struct pci_dev *pci_dev = ab_pci->pdev; 597 598 pci_iounmap(pci_dev, ab->mem); 599 ab->mem = NULL; 600 pci_release_region(pci_dev, ATH11K_PCI_BAR_NUM); 601 if (pci_is_enabled(pci_dev)) 602 pci_disable_device(pci_dev); 603 } 604 605 static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci) 606 { 607 struct ath11k_base *ab = ab_pci->ab; 608 609 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL, 610 &ab_pci->link_ctl); 611 612 ath11k_dbg(ab, ATH11K_DBG_PCI, "link_ctl 0x%04x L0s %d L1 %d\n", 613 ab_pci->link_ctl, 614 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S), 615 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1)); 616 617 /* disable L0s and L1 */ 618 pcie_capability_clear_word(ab_pci->pdev, PCI_EXP_LNKCTL, 619 PCI_EXP_LNKCTL_ASPMC); 620 621 set_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags); 622 } 623 624 static void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci) 625 { 626 if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags)) 627 pcie_capability_clear_and_set_word(ab_pci->pdev, PCI_EXP_LNKCTL, 628 PCI_EXP_LNKCTL_ASPMC, 629 ab_pci->link_ctl & 630 PCI_EXP_LNKCTL_ASPMC); 631 } 632 633 #ifdef CONFIG_DEV_COREDUMP 634 static int ath11k_pci_coredump_calculate_size(struct ath11k_base *ab, u32 *dump_seg_sz) 635 { 636 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 637 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl; 638 struct image_info *rddm_img, *fw_img; 639 struct ath11k_tlv_dump_data *dump_tlv; 640 enum ath11k_fw_crash_dump_type mem_type; 641 u32 len = 0, rddm_tlv_sz = 0, paging_tlv_sz = 0; 642 struct ath11k_dump_file_data *file_data; 643 int i; 644 645 rddm_img = mhi_ctrl->rddm_image; 646 if (!rddm_img) { 647 ath11k_err(ab, "No RDDM dump found\n"); 648 return 0; 649 } 650 651 fw_img = mhi_ctrl->fbc_image; 652 653 for (i = 0; i < fw_img->entries ; i++) { 654 if (!fw_img->mhi_buf[i].buf) 655 continue; 656 657 paging_tlv_sz += fw_img->mhi_buf[i].len; 658 } 659 dump_seg_sz[FW_CRASH_DUMP_PAGING_DATA] = paging_tlv_sz; 660 661 for (i = 0; i < rddm_img->entries; i++) { 662 if (!rddm_img->mhi_buf[i].buf) 663 continue; 664 665 rddm_tlv_sz += rddm_img->mhi_buf[i].len; 666 } 667 dump_seg_sz[FW_CRASH_DUMP_RDDM_DATA] = rddm_tlv_sz; 668 669 for (i = 0; i < ab->qmi.mem_seg_count; i++) { 670 mem_type = ath11k_coredump_get_dump_type(ab->qmi.target_mem[i].type); 671 672 if (mem_type == FW_CRASH_DUMP_NONE) 673 continue; 674 675 if (mem_type == FW_CRASH_DUMP_TYPE_MAX) { 676 ath11k_dbg(ab, ATH11K_DBG_PCI, 677 "target mem region type %d not supported", 678 ab->qmi.target_mem[i].type); 679 continue; 680 } 681 682 if (!ab->qmi.target_mem[i].anyaddr) 683 continue; 684 685 dump_seg_sz[mem_type] += ab->qmi.target_mem[i].size; 686 } 687 688 for (i = 0; i < FW_CRASH_DUMP_TYPE_MAX; i++) { 689 if (!dump_seg_sz[i]) 690 continue; 691 692 len += sizeof(*dump_tlv) + dump_seg_sz[i]; 693 } 694 695 if (len) 696 len += sizeof(*file_data); 697 698 return len; 699 } 700 701 static void ath11k_pci_coredump_download(struct ath11k_base *ab) 702 { 703 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 704 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl; 705 struct image_info *rddm_img, *fw_img; 706 struct timespec64 timestamp; 707 int i, len, mem_idx; 708 enum ath11k_fw_crash_dump_type mem_type; 709 struct ath11k_dump_file_data *file_data; 710 struct ath11k_tlv_dump_data *dump_tlv; 711 size_t hdr_len = sizeof(*file_data); 712 void *buf; 713 u32 dump_seg_sz[FW_CRASH_DUMP_TYPE_MAX] = {}; 714 715 ath11k_mhi_coredump(mhi_ctrl, false); 716 717 len = ath11k_pci_coredump_calculate_size(ab, dump_seg_sz); 718 if (!len) { 719 ath11k_warn(ab, "No crash dump data found for devcoredump"); 720 return; 721 } 722 723 rddm_img = mhi_ctrl->rddm_image; 724 fw_img = mhi_ctrl->fbc_image; 725 726 /* dev_coredumpv() requires vmalloc data */ 727 buf = vzalloc(len); 728 if (!buf) 729 return; 730 731 ab->dump_data = buf; 732 ab->ath11k_coredump_len = len; 733 file_data = ab->dump_data; 734 strscpy(file_data->df_magic, "ATH11K-FW-DUMP", sizeof(file_data->df_magic)); 735 file_data->len = cpu_to_le32(len); 736 file_data->version = cpu_to_le32(ATH11K_FW_CRASH_DUMP_V2); 737 file_data->chip_id = cpu_to_le32(ab_pci->dev_id); 738 file_data->qrtr_id = cpu_to_le32(ab_pci->ab->qmi.service_ins_id); 739 file_data->bus_id = cpu_to_le32(pci_domain_nr(ab_pci->pdev->bus)); 740 guid_gen(&file_data->guid); 741 ktime_get_real_ts64(×tamp); 742 file_data->tv_sec = cpu_to_le64(timestamp.tv_sec); 743 file_data->tv_nsec = cpu_to_le64(timestamp.tv_nsec); 744 buf += hdr_len; 745 dump_tlv = buf; 746 dump_tlv->type = cpu_to_le32(FW_CRASH_DUMP_PAGING_DATA); 747 dump_tlv->tlv_len = cpu_to_le32(dump_seg_sz[FW_CRASH_DUMP_PAGING_DATA]); 748 buf += COREDUMP_TLV_HDR_SIZE; 749 750 /* append all segments together as they are all part of a single contiguous 751 * block of memory 752 */ 753 for (i = 0; i < fw_img->entries ; i++) { 754 if (!fw_img->mhi_buf[i].buf) 755 continue; 756 757 memcpy_fromio(buf, (void const __iomem *)fw_img->mhi_buf[i].buf, 758 fw_img->mhi_buf[i].len); 759 buf += fw_img->mhi_buf[i].len; 760 } 761 762 dump_tlv = buf; 763 dump_tlv->type = cpu_to_le32(FW_CRASH_DUMP_RDDM_DATA); 764 dump_tlv->tlv_len = cpu_to_le32(dump_seg_sz[FW_CRASH_DUMP_RDDM_DATA]); 765 buf += COREDUMP_TLV_HDR_SIZE; 766 767 /* append all segments together as they are all part of a single contiguous 768 * block of memory 769 */ 770 for (i = 0; i < rddm_img->entries; i++) { 771 if (!rddm_img->mhi_buf[i].buf) 772 continue; 773 774 memcpy_fromio(buf, (void const __iomem *)rddm_img->mhi_buf[i].buf, 775 rddm_img->mhi_buf[i].len); 776 buf += rddm_img->mhi_buf[i].len; 777 } 778 779 mem_idx = FW_CRASH_DUMP_REMOTE_MEM_DATA; 780 for (; mem_idx < FW_CRASH_DUMP_TYPE_MAX; mem_idx++) { 781 if (mem_idx == FW_CRASH_DUMP_NONE) 782 continue; 783 784 for (i = 0; i < ab->qmi.mem_seg_count; i++) { 785 mem_type = ath11k_coredump_get_dump_type 786 (ab->qmi.target_mem[i].type); 787 788 if (mem_type != mem_idx) 789 continue; 790 791 if (!ab->qmi.target_mem[i].anyaddr) { 792 ath11k_dbg(ab, ATH11K_DBG_PCI, 793 "Skipping mem region type %d", 794 ab->qmi.target_mem[i].type); 795 continue; 796 } 797 798 dump_tlv = buf; 799 dump_tlv->type = cpu_to_le32(mem_idx); 800 dump_tlv->tlv_len = cpu_to_le32(dump_seg_sz[mem_idx]); 801 buf += COREDUMP_TLV_HDR_SIZE; 802 803 memcpy_fromio(buf, ab->qmi.target_mem[i].iaddr, 804 ab->qmi.target_mem[i].size); 805 806 buf += ab->qmi.target_mem[i].size; 807 } 808 } 809 810 queue_work(ab->workqueue, &ab->dump_work); 811 } 812 #endif 813 814 static int ath11k_pci_power_up(struct ath11k_base *ab) 815 { 816 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 817 int ret; 818 819 ab_pci->register_window = 0; 820 clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags); 821 ath11k_pci_sw_reset(ab_pci->ab, true); 822 823 /* Disable ASPM during firmware download due to problems switching 824 * to AMSS state. 825 */ 826 ath11k_pci_aspm_disable(ab_pci); 827 828 ath11k_pci_msi_enable(ab_pci); 829 830 ret = ath11k_mhi_start(ab_pci); 831 if (ret) { 832 ath11k_err(ab, "failed to start mhi: %d\n", ret); 833 return ret; 834 } 835 836 if (ab->hw_params.static_window_map) 837 ath11k_pci_select_static_window(ab_pci); 838 839 return 0; 840 } 841 842 static void ath11k_pci_power_down(struct ath11k_base *ab, bool is_suspend) 843 { 844 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 845 846 /* restore aspm in case firmware bootup fails */ 847 ath11k_pci_aspm_restore(ab_pci); 848 849 ath11k_pci_force_wake(ab_pci->ab); 850 851 ath11k_pci_msi_disable(ab_pci); 852 853 ath11k_mhi_stop(ab_pci, is_suspend); 854 clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags); 855 ath11k_pci_sw_reset(ab_pci->ab, false); 856 } 857 858 static int ath11k_pci_hif_suspend(struct ath11k_base *ab) 859 { 860 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab); 861 862 return ath11k_mhi_suspend(ar_pci); 863 } 864 865 static int ath11k_pci_hif_resume(struct ath11k_base *ab) 866 { 867 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab); 868 869 return ath11k_mhi_resume(ar_pci); 870 } 871 872 static void ath11k_pci_hif_ce_irq_enable(struct ath11k_base *ab) 873 { 874 ath11k_pcic_ce_irqs_enable(ab); 875 } 876 877 static void ath11k_pci_hif_ce_irq_disable(struct ath11k_base *ab) 878 { 879 ath11k_pcic_ce_irq_disable_sync(ab); 880 } 881 882 static int ath11k_pci_start(struct ath11k_base *ab) 883 { 884 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 885 886 /* TODO: for now don't restore ASPM in case of single MSI 887 * vector as MHI register reading in M2 causes system hang. 888 */ 889 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags)) 890 ath11k_pci_aspm_restore(ab_pci); 891 else 892 ath11k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n"); 893 894 ath11k_pcic_start(ab); 895 896 return 0; 897 } 898 899 static const struct ath11k_hif_ops ath11k_pci_hif_ops = { 900 .start = ath11k_pci_start, 901 .stop = ath11k_pcic_stop, 902 .read32 = ath11k_pcic_read32, 903 .write32 = ath11k_pcic_write32, 904 .read = ath11k_pcic_read, 905 .power_down = ath11k_pci_power_down, 906 .power_up = ath11k_pci_power_up, 907 .suspend = ath11k_pci_hif_suspend, 908 .resume = ath11k_pci_hif_resume, 909 .irq_enable = ath11k_pcic_ext_irq_enable, 910 .irq_disable = ath11k_pcic_ext_irq_disable, 911 .get_msi_address = ath11k_pcic_get_msi_address, 912 .get_user_msi_vector = ath11k_pcic_get_user_msi_assignment, 913 .map_service_to_pipe = ath11k_pcic_map_service_to_pipe, 914 .ce_irq_enable = ath11k_pci_hif_ce_irq_enable, 915 .ce_irq_disable = ath11k_pci_hif_ce_irq_disable, 916 .get_ce_msi_idx = ath11k_pcic_get_ce_msi_idx, 917 #ifdef CONFIG_DEV_COREDUMP 918 .coredump_download = ath11k_pci_coredump_download, 919 #endif 920 }; 921 922 static void ath11k_pci_read_hw_version(struct ath11k_base *ab, u32 *major, u32 *minor) 923 { 924 u32 soc_hw_version; 925 926 soc_hw_version = ath11k_pcic_read32(ab, TCSR_SOC_HW_VERSION); 927 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK, 928 soc_hw_version); 929 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK, 930 soc_hw_version); 931 932 ath11k_dbg(ab, ATH11K_DBG_PCI, "tcsr_soc_hw_version major %d minor %d\n", 933 *major, *minor); 934 } 935 936 static int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci, 937 const struct cpumask *m) 938 { 939 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab_pci->ab->dev_flags)) 940 return 0; 941 942 return irq_set_affinity_and_hint(ab_pci->pdev->irq, m); 943 } 944 945 static int ath11k_pci_probe(struct pci_dev *pdev, 946 const struct pci_device_id *pci_dev) 947 { 948 struct ath11k_base *ab; 949 struct ath11k_pci *ab_pci; 950 u32 soc_hw_version_major, soc_hw_version_minor; 951 int ret; 952 u32 sub_version; 953 954 ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI); 955 956 if (!ab) { 957 dev_err(&pdev->dev, "failed to allocate ath11k base\n"); 958 return -ENOMEM; 959 } 960 961 ab->dev = &pdev->dev; 962 pci_set_drvdata(pdev, ab); 963 ab_pci = ath11k_pci_priv(ab); 964 ab_pci->dev_id = pci_dev->device; 965 ab_pci->ab = ab; 966 ab_pci->pdev = pdev; 967 ab->hif.ops = &ath11k_pci_hif_ops; 968 ab->fw_mode = ATH11K_FIRMWARE_MODE_NORMAL; 969 pci_set_drvdata(pdev, ab); 970 spin_lock_init(&ab_pci->window_lock); 971 972 /* Set fixed_mem_region to true for platforms support reserved memory 973 * from DT. If memory is reserved from DT for FW, ath11k driver need not 974 * allocate memory. 975 */ 976 if (of_property_present(ab->dev->of_node, "memory-region")) 977 set_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags); 978 979 ret = ath11k_pci_claim(ab_pci, pdev); 980 if (ret) { 981 ath11k_err(ab, "failed to claim device: %d\n", ret); 982 goto err_free_core; 983 } 984 985 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n", 986 pdev->vendor, pdev->device, 987 pdev->subsystem_vendor, pdev->subsystem_device); 988 989 ab->id.vendor = pdev->vendor; 990 ab->id.device = pdev->device; 991 ab->id.subsystem_vendor = pdev->subsystem_vendor; 992 ab->id.subsystem_device = pdev->subsystem_device; 993 994 switch (pci_dev->device) { 995 case QCA6390_DEVICE_ID: 996 ret = ath11k_pcic_register_pci_ops(ab, &ath11k_pci_ops_qca6390); 997 if (ret) { 998 ath11k_err(ab, "failed to register PCI ops: %d\n", ret); 999 goto err_pci_free_region; 1000 } 1001 1002 ath11k_pci_read_hw_version(ab, &soc_hw_version_major, 1003 &soc_hw_version_minor); 1004 switch (soc_hw_version_major) { 1005 case 2: 1006 ab->hw_rev = ATH11K_HW_QCA6390_HW20; 1007 break; 1008 default: 1009 dev_err(&pdev->dev, "Unsupported QCA6390 SOC hardware version: %d %d\n", 1010 soc_hw_version_major, soc_hw_version_minor); 1011 ret = -EOPNOTSUPP; 1012 goto err_pci_free_region; 1013 } 1014 1015 break; 1016 case QCN9074_DEVICE_ID: 1017 ret = ath11k_pcic_register_pci_ops(ab, &ath11k_pci_ops_qcn9074); 1018 if (ret) { 1019 ath11k_err(ab, "failed to register PCI ops: %d\n", ret); 1020 goto err_pci_free_region; 1021 } 1022 ab->hw_rev = ATH11K_HW_QCN9074_HW10; 1023 break; 1024 case WCN6855_DEVICE_ID: 1025 ret = ath11k_pcic_register_pci_ops(ab, &ath11k_pci_ops_qca6390); 1026 if (ret) { 1027 ath11k_err(ab, "failed to register PCI ops: %d\n", ret); 1028 goto err_pci_free_region; 1029 } 1030 ab->id.bdf_search = ATH11K_BDF_SEARCH_BUS_AND_BOARD; 1031 ath11k_pci_read_hw_version(ab, &soc_hw_version_major, 1032 &soc_hw_version_minor); 1033 switch (soc_hw_version_major) { 1034 case 2: 1035 switch (soc_hw_version_minor) { 1036 case 0x00: 1037 case 0x01: 1038 ab->hw_rev = ATH11K_HW_WCN6855_HW20; 1039 break; 1040 case 0x10: 1041 case 0x11: 1042 sub_version = ath11k_pcic_read32(ab, TCSR_SOC_HW_SUB_VER); 1043 ath11k_dbg(ab, ATH11K_DBG_PCI, "sub_version 0x%x\n", 1044 sub_version); 1045 switch (sub_version) { 1046 case 0x1019A0E1: 1047 case 0x1019B0E1: 1048 case 0x1019C0E1: 1049 case 0x1019D0E1: 1050 ab->hw_rev = ATH11K_HW_QCA2066_HW21; 1051 break; 1052 case 0x001e60e1: 1053 ab->hw_rev = ATH11K_HW_QCA6698AQ_HW21; 1054 break; 1055 default: 1056 ab->hw_rev = ATH11K_HW_WCN6855_HW21; 1057 } 1058 break; 1059 default: 1060 goto unsupported_wcn6855_soc; 1061 } 1062 break; 1063 default: 1064 unsupported_wcn6855_soc: 1065 dev_err(&pdev->dev, "Unsupported WCN6855 SOC hardware version: %d %d\n", 1066 soc_hw_version_major, soc_hw_version_minor); 1067 ret = -EOPNOTSUPP; 1068 goto err_pci_free_region; 1069 } 1070 1071 break; 1072 default: 1073 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n", 1074 pci_dev->device); 1075 ret = -EOPNOTSUPP; 1076 goto err_pci_free_region; 1077 } 1078 1079 ret = ath11k_pcic_init_msi_config(ab); 1080 if (ret) { 1081 ath11k_err(ab, "failed to init msi config: %d\n", ret); 1082 goto err_pci_free_region; 1083 } 1084 1085 ret = ath11k_pci_alloc_msi(ab_pci); 1086 if (ret) { 1087 ath11k_err(ab, "failed to enable msi: %d\n", ret); 1088 goto err_pci_free_region; 1089 } 1090 1091 ret = ath11k_core_pre_init(ab); 1092 if (ret) 1093 goto err_pci_disable_msi; 1094 1095 ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0)); 1096 if (ret) { 1097 ath11k_err(ab, "failed to set irq affinity %d\n", ret); 1098 goto err_pci_disable_msi; 1099 } 1100 1101 ret = ath11k_mhi_register(ab_pci); 1102 if (ret) { 1103 ath11k_err(ab, "failed to register mhi: %d\n", ret); 1104 goto err_irq_affinity_cleanup; 1105 } 1106 1107 ret = ath11k_hal_srng_init(ab); 1108 if (ret) 1109 goto err_mhi_unregister; 1110 1111 ret = ath11k_ce_alloc_pipes(ab); 1112 if (ret) { 1113 ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret); 1114 goto err_hal_srng_deinit; 1115 } 1116 1117 ath11k_pci_init_qmi_ce_config(ab); 1118 1119 ret = ath11k_pcic_config_irq(ab); 1120 if (ret) { 1121 ath11k_err(ab, "failed to config irq: %d\n", ret); 1122 goto err_ce_free; 1123 } 1124 1125 /* kernel may allocate a dummy vector before request_irq and 1126 * then allocate a real vector when request_irq is called. 1127 * So get msi_data here again to avoid spurious interrupt 1128 * as msi_data will configured to srngs. 1129 */ 1130 ret = ath11k_pci_config_msi_data(ab_pci); 1131 if (ret) { 1132 ath11k_err(ab, "failed to config msi_data: %d\n", ret); 1133 goto err_free_irq; 1134 } 1135 1136 ret = ath11k_core_init(ab); 1137 if (ret) { 1138 ath11k_err(ab, "failed to init core: %d\n", ret); 1139 goto err_free_irq; 1140 } 1141 ath11k_qmi_fwreset_from_cold_boot(ab); 1142 return 0; 1143 1144 err_free_irq: 1145 /* __free_irq() expects the caller to have cleared the affinity hint */ 1146 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL); 1147 ath11k_pcic_free_irq(ab); 1148 1149 err_ce_free: 1150 ath11k_ce_free_pipes(ab); 1151 1152 err_hal_srng_deinit: 1153 ath11k_hal_srng_deinit(ab); 1154 1155 err_mhi_unregister: 1156 ath11k_mhi_unregister(ab_pci); 1157 1158 err_irq_affinity_cleanup: 1159 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL); 1160 1161 err_pci_disable_msi: 1162 ath11k_pci_free_msi(ab_pci); 1163 1164 err_pci_free_region: 1165 ath11k_pci_free_region(ab_pci); 1166 1167 err_free_core: 1168 ath11k_core_free(ab); 1169 1170 return ret; 1171 } 1172 1173 static void ath11k_pci_remove(struct pci_dev *pdev) 1174 { 1175 struct ath11k_base *ab = pci_get_drvdata(pdev); 1176 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 1177 1178 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL); 1179 1180 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) { 1181 ath11k_pci_power_down(ab, false); 1182 ath11k_debugfs_soc_destroy(ab); 1183 ath11k_qmi_deinit_service(ab); 1184 ath11k_core_pm_notifier_unregister(ab); 1185 goto qmi_fail; 1186 } 1187 1188 set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags); 1189 1190 cancel_work_sync(&ab->reset_work); 1191 cancel_work_sync(&ab->dump_work); 1192 ath11k_core_deinit(ab); 1193 1194 qmi_fail: 1195 ath11k_fw_destroy(ab); 1196 ath11k_mhi_unregister(ab_pci); 1197 1198 ath11k_pcic_free_irq(ab); 1199 ath11k_pci_free_msi(ab_pci); 1200 ath11k_pci_free_region(ab_pci); 1201 1202 ath11k_hal_srng_deinit(ab); 1203 ath11k_ce_free_pipes(ab); 1204 ath11k_core_free(ab); 1205 } 1206 1207 static void ath11k_pci_shutdown(struct pci_dev *pdev) 1208 { 1209 struct ath11k_base *ab = pci_get_drvdata(pdev); 1210 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 1211 1212 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL); 1213 ath11k_pci_power_down(ab, false); 1214 } 1215 1216 static __maybe_unused int ath11k_pci_pm_suspend(struct device *dev) 1217 { 1218 struct ath11k_base *ab = dev_get_drvdata(dev); 1219 int ret; 1220 1221 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) { 1222 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci suspend as qmi is not initialised\n"); 1223 return 0; 1224 } 1225 1226 ret = ath11k_core_suspend(ab); 1227 if (ret) 1228 ath11k_warn(ab, "failed to suspend core: %d\n", ret); 1229 1230 return 0; 1231 } 1232 1233 static __maybe_unused int ath11k_pci_pm_resume(struct device *dev) 1234 { 1235 struct ath11k_base *ab = dev_get_drvdata(dev); 1236 int ret; 1237 1238 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) { 1239 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci resume as qmi is not initialised\n"); 1240 return 0; 1241 } 1242 1243 ret = ath11k_core_resume(ab); 1244 if (ret) 1245 ath11k_warn(ab, "failed to resume core: %d\n", ret); 1246 1247 return ret; 1248 } 1249 1250 static __maybe_unused int ath11k_pci_pm_suspend_late(struct device *dev) 1251 { 1252 struct ath11k_base *ab = dev_get_drvdata(dev); 1253 int ret; 1254 1255 ret = ath11k_core_suspend_late(ab); 1256 if (ret) 1257 ath11k_warn(ab, "failed to late suspend core: %d\n", ret); 1258 1259 /* Similar to ath11k_pci_pm_suspend(), we return success here 1260 * even error happens, to allow system suspend/hibernation survive. 1261 */ 1262 return 0; 1263 } 1264 1265 static __maybe_unused int ath11k_pci_pm_resume_early(struct device *dev) 1266 { 1267 struct ath11k_base *ab = dev_get_drvdata(dev); 1268 int ret; 1269 1270 ret = ath11k_core_resume_early(ab); 1271 if (ret) 1272 ath11k_warn(ab, "failed to early resume core: %d\n", ret); 1273 1274 return ret; 1275 } 1276 1277 static const struct dev_pm_ops __maybe_unused ath11k_pci_pm_ops = { 1278 SET_SYSTEM_SLEEP_PM_OPS(ath11k_pci_pm_suspend, 1279 ath11k_pci_pm_resume) 1280 SET_LATE_SYSTEM_SLEEP_PM_OPS(ath11k_pci_pm_suspend_late, 1281 ath11k_pci_pm_resume_early) 1282 }; 1283 1284 static struct pci_driver ath11k_pci_driver = { 1285 .name = "ath11k_pci", 1286 .id_table = ath11k_pci_id_table, 1287 .probe = ath11k_pci_probe, 1288 .remove = ath11k_pci_remove, 1289 .shutdown = ath11k_pci_shutdown, 1290 #ifdef CONFIG_PM 1291 .driver.pm = &ath11k_pci_pm_ops, 1292 #endif 1293 }; 1294 1295 static int ath11k_pci_init(void) 1296 { 1297 int ret; 1298 1299 ret = pci_register_driver(&ath11k_pci_driver); 1300 if (ret) 1301 pr_err("failed to register ath11k pci driver: %d\n", 1302 ret); 1303 1304 return ret; 1305 } 1306 module_init(ath11k_pci_init); 1307 1308 static void ath11k_pci_exit(void) 1309 { 1310 pci_unregister_driver(&ath11k_pci_driver); 1311 } 1312 1313 module_exit(ath11k_pci_exit); 1314 1315 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies PCIe 802.11ax WLAN devices"); 1316 MODULE_LICENSE("Dual BSD/GPL"); 1317 1318 /* firmware files */ 1319 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/*"); 1320 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCN9074/hw1.0/*"); 1321 MODULE_FIRMWARE(ATH11K_FW_DIR "/WCN6855/hw2.0/*"); 1322 MODULE_FIRMWARE(ATH11K_FW_DIR "/WCN6855/hw2.1/*"); 1323