1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #include <linux/export.h> 8 #include <linux/module.h> 9 #include <linux/slab.h> 10 #include <linux/remoteproc.h> 11 #include <linux/firmware.h> 12 #include <linux/of.h> 13 14 #include "core.h" 15 #include "dp_tx.h" 16 #include "dp_rx.h" 17 #include "debug.h" 18 #include "hif.h" 19 #include "wow.h" 20 #include "fw.h" 21 22 unsigned int ath11k_debug_mask; 23 EXPORT_SYMBOL(ath11k_debug_mask); 24 module_param_named(debug_mask, ath11k_debug_mask, uint, 0644); 25 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 26 27 static unsigned int ath11k_crypto_mode; 28 module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644); 29 MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software"); 30 31 /* frame mode values are mapped as per enum ath11k_hw_txrx_mode */ 32 unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI; 33 module_param_named(frame_mode, ath11k_frame_mode, uint, 0644); 34 MODULE_PARM_DESC(frame_mode, 35 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)"); 36 37 bool ath11k_ftm_mode; 38 module_param_named(ftm_mode, ath11k_ftm_mode, bool, 0444); 39 MODULE_PARM_DESC(ftm_mode, "Boots up in factory test mode"); 40 41 static const struct ath11k_hw_params ath11k_hw_params[] = { 42 { 43 .hw_rev = ATH11K_HW_IPQ8074, 44 .name = "ipq8074 hw2.0", 45 .fw = { 46 .dir = "IPQ8074/hw2.0", 47 .board_size = 256 * 1024, 48 .cal_offset = 128 * 1024, 49 }, 50 .max_radios = 3, 51 .bdf_addr = 0x4B0C0000, 52 .hw_ops = &ipq8074_ops, 53 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 54 .internal_sleep_clock = false, 55 .regs = &ipq8074_regs, 56 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 57 .host_ce_config = ath11k_host_ce_config_ipq8074, 58 .ce_count = 12, 59 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074, 60 .target_ce_count = 11, 61 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074, 62 .svc_to_ce_map_len = 21, 63 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 64 .single_pdev_only = false, 65 .rxdma1_enable = true, 66 .num_rxdma_per_pdev = 1, 67 .rx_mac_buf_ring = false, 68 .vdev_start_delay = false, 69 .htt_peer_map_v2 = true, 70 71 .spectral = { 72 .fft_sz = 2, 73 /* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes. 74 * so added pad size as 2 bytes to compensate the BIN size 75 */ 76 .fft_pad_sz = 2, 77 .summary_pad_sz = 0, 78 .fft_hdr_len = 16, 79 .max_fft_bins = 512, 80 .fragment_160mhz = true, 81 }, 82 83 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 84 BIT(NL80211_IFTYPE_AP) | 85 BIT(NL80211_IFTYPE_MESH_POINT), 86 .supports_monitor = true, 87 .full_monitor_mode = false, 88 .supports_shadow_regs = false, 89 .idle_ps = false, 90 .supports_sta_ps = false, 91 .coldboot_cal_mm = true, 92 .coldboot_cal_ftm = true, 93 .cbcal_restart_fw = true, 94 .fw_mem_mode = 0, 95 .num_vdevs = 16 + 1, 96 .num_peers = 512, 97 .supports_suspend = false, 98 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 99 .supports_regdb = false, 100 .fix_l1ss = true, 101 .credit_flow = false, 102 .hal_params = &ath11k_hw_hal_params_ipq8074, 103 .supports_dynamic_smps_6ghz = false, 104 .alloc_cacheable_memory = true, 105 .supports_rssi_stats = false, 106 .fw_wmi_diag_event = false, 107 .current_cc_support = false, 108 .dbr_debug_support = true, 109 .global_reset = false, 110 .bios_sar_capa = NULL, 111 .m3_fw_support = false, 112 .fixed_bdf_addr = true, 113 .fixed_mem_region = true, 114 .static_window_map = false, 115 .hybrid_bus_type = false, 116 .fixed_fw_mem = false, 117 .support_off_channel_tx = false, 118 .supports_multi_bssid = false, 119 120 .sram_dump = {}, 121 122 .tcl_ring_retry = true, 123 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 124 .smp2p_wow_exit = false, 125 .support_dual_stations = false, 126 .pdev_suspend = false, 127 .cfr_support = true, 128 .cfr_num_stream_bufs = 255, 129 .cfr_stream_buf_size = 8200, 130 }, 131 { 132 .hw_rev = ATH11K_HW_IPQ6018_HW10, 133 .name = "ipq6018 hw1.0", 134 .fw = { 135 .dir = "IPQ6018/hw1.0", 136 .board_size = 256 * 1024, 137 .cal_offset = 128 * 1024, 138 }, 139 .max_radios = 2, 140 .bdf_addr = 0x4ABC0000, 141 .hw_ops = &ipq6018_ops, 142 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 143 .internal_sleep_clock = false, 144 .regs = &ipq8074_regs, 145 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 146 .host_ce_config = ath11k_host_ce_config_ipq8074, 147 .ce_count = 12, 148 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074, 149 .target_ce_count = 11, 150 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018, 151 .svc_to_ce_map_len = 19, 152 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 153 .single_pdev_only = false, 154 .rxdma1_enable = true, 155 .num_rxdma_per_pdev = 1, 156 .rx_mac_buf_ring = false, 157 .vdev_start_delay = false, 158 .htt_peer_map_v2 = true, 159 160 .spectral = { 161 .fft_sz = 4, 162 .fft_pad_sz = 0, 163 .summary_pad_sz = 0, 164 .fft_hdr_len = 16, 165 .max_fft_bins = 512, 166 .fragment_160mhz = true, 167 }, 168 169 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 170 BIT(NL80211_IFTYPE_AP) | 171 BIT(NL80211_IFTYPE_MESH_POINT), 172 .supports_monitor = true, 173 .full_monitor_mode = false, 174 .supports_shadow_regs = false, 175 .idle_ps = false, 176 .supports_sta_ps = false, 177 .coldboot_cal_mm = true, 178 .coldboot_cal_ftm = true, 179 .cbcal_restart_fw = true, 180 .fw_mem_mode = 0, 181 .num_vdevs = 16 + 1, 182 .num_peers = 512, 183 .supports_suspend = false, 184 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 185 .supports_regdb = false, 186 .fix_l1ss = true, 187 .credit_flow = false, 188 .hal_params = &ath11k_hw_hal_params_ipq8074, 189 .supports_dynamic_smps_6ghz = false, 190 .alloc_cacheable_memory = true, 191 .supports_rssi_stats = false, 192 .fw_wmi_diag_event = false, 193 .current_cc_support = false, 194 .dbr_debug_support = true, 195 .global_reset = false, 196 .bios_sar_capa = NULL, 197 .m3_fw_support = false, 198 .fixed_bdf_addr = true, 199 .fixed_mem_region = true, 200 .static_window_map = false, 201 .hybrid_bus_type = false, 202 .fixed_fw_mem = false, 203 .support_off_channel_tx = false, 204 .supports_multi_bssid = false, 205 206 .sram_dump = {}, 207 208 .tcl_ring_retry = true, 209 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 210 .smp2p_wow_exit = false, 211 .support_fw_mac_sequence = false, 212 .support_dual_stations = false, 213 .pdev_suspend = false, 214 .cfr_support = false, 215 .cfr_num_stream_bufs = 0, 216 .cfr_stream_buf_size = 0, 217 }, 218 { 219 .name = "qca6390 hw2.0", 220 .hw_rev = ATH11K_HW_QCA6390_HW20, 221 .fw = { 222 .dir = "QCA6390/hw2.0", 223 .board_size = 256 * 1024, 224 .cal_offset = 128 * 1024, 225 }, 226 .max_radios = 3, 227 .bdf_addr = 0x4B0C0000, 228 .hw_ops = &qca6390_ops, 229 .ring_mask = &ath11k_hw_ring_mask_qca6390, 230 .internal_sleep_clock = true, 231 .regs = &qca6390_regs, 232 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 233 .host_ce_config = ath11k_host_ce_config_qca6390, 234 .ce_count = 9, 235 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 236 .target_ce_count = 9, 237 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 238 .svc_to_ce_map_len = 14, 239 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 240 .single_pdev_only = true, 241 .rxdma1_enable = false, 242 .num_rxdma_per_pdev = 2, 243 .rx_mac_buf_ring = true, 244 .vdev_start_delay = true, 245 .htt_peer_map_v2 = false, 246 247 .spectral = { 248 .fft_sz = 0, 249 .fft_pad_sz = 0, 250 .summary_pad_sz = 0, 251 .fft_hdr_len = 0, 252 .max_fft_bins = 0, 253 .fragment_160mhz = false, 254 }, 255 256 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 257 BIT(NL80211_IFTYPE_AP) | 258 BIT(NL80211_IFTYPE_P2P_DEVICE) | 259 BIT(NL80211_IFTYPE_P2P_CLIENT) | 260 BIT(NL80211_IFTYPE_P2P_GO), 261 .supports_monitor = false, 262 .full_monitor_mode = false, 263 .supports_shadow_regs = true, 264 .idle_ps = true, 265 .supports_sta_ps = true, 266 .coldboot_cal_mm = false, 267 .coldboot_cal_ftm = false, 268 .cbcal_restart_fw = false, 269 .fw_mem_mode = 0, 270 .num_vdevs = 2 + 1, 271 .num_peers = 512, 272 .supports_suspend = true, 273 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 274 .supports_regdb = false, 275 .fix_l1ss = true, 276 .credit_flow = true, 277 .hal_params = &ath11k_hw_hal_params_qca6390, 278 .supports_dynamic_smps_6ghz = false, 279 .alloc_cacheable_memory = false, 280 .supports_rssi_stats = true, 281 .fw_wmi_diag_event = true, 282 .current_cc_support = true, 283 .dbr_debug_support = false, 284 .global_reset = true, 285 .bios_sar_capa = NULL, 286 .m3_fw_support = true, 287 .fixed_bdf_addr = false, 288 .fixed_mem_region = false, 289 .static_window_map = false, 290 .hybrid_bus_type = false, 291 .fixed_fw_mem = false, 292 .support_off_channel_tx = true, 293 .supports_multi_bssid = true, 294 295 .sram_dump = { 296 .start = 0x01400000, 297 .end = 0x0171ffff, 298 }, 299 300 .tcl_ring_retry = true, 301 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 302 .smp2p_wow_exit = false, 303 .support_fw_mac_sequence = true, 304 .support_dual_stations = true, 305 .pdev_suspend = false, 306 .cfr_support = false, 307 .cfr_num_stream_bufs = 0, 308 .cfr_stream_buf_size = 0, 309 }, 310 { 311 .name = "qcn9074 hw1.0", 312 .hw_rev = ATH11K_HW_QCN9074_HW10, 313 .fw = { 314 .dir = "QCN9074/hw1.0", 315 .board_size = 256 * 1024, 316 .cal_offset = 128 * 1024, 317 }, 318 .max_radios = 1, 319 .single_pdev_only = false, 320 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074, 321 .hw_ops = &qcn9074_ops, 322 .ring_mask = &ath11k_hw_ring_mask_qcn9074, 323 .internal_sleep_clock = false, 324 .regs = &qcn9074_regs, 325 .host_ce_config = ath11k_host_ce_config_qcn9074, 326 .ce_count = 6, 327 .target_ce_config = ath11k_target_ce_config_wlan_qcn9074, 328 .target_ce_count = 9, 329 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074, 330 .svc_to_ce_map_len = 18, 331 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 332 .rxdma1_enable = true, 333 .num_rxdma_per_pdev = 1, 334 .rx_mac_buf_ring = false, 335 .vdev_start_delay = false, 336 .htt_peer_map_v2 = true, 337 338 .spectral = { 339 .fft_sz = 2, 340 .fft_pad_sz = 0, 341 .summary_pad_sz = 16, 342 .fft_hdr_len = 24, 343 .max_fft_bins = 1024, 344 .fragment_160mhz = false, 345 }, 346 347 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 348 BIT(NL80211_IFTYPE_AP) | 349 BIT(NL80211_IFTYPE_MESH_POINT), 350 .supports_monitor = true, 351 .full_monitor_mode = true, 352 .supports_shadow_regs = false, 353 .idle_ps = false, 354 .supports_sta_ps = false, 355 .coldboot_cal_mm = false, 356 .coldboot_cal_ftm = true, 357 .cbcal_restart_fw = true, 358 .fw_mem_mode = 2, 359 .num_vdevs = 8, 360 .num_peers = 128, 361 .supports_suspend = false, 362 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 363 .supports_regdb = false, 364 .fix_l1ss = true, 365 .credit_flow = false, 366 .hal_params = &ath11k_hw_hal_params_ipq8074, 367 .supports_dynamic_smps_6ghz = true, 368 .alloc_cacheable_memory = true, 369 .supports_rssi_stats = false, 370 .fw_wmi_diag_event = false, 371 .current_cc_support = false, 372 .dbr_debug_support = true, 373 .global_reset = false, 374 .bios_sar_capa = NULL, 375 .m3_fw_support = true, 376 .fixed_bdf_addr = false, 377 .fixed_mem_region = false, 378 .static_window_map = true, 379 .hybrid_bus_type = false, 380 .fixed_fw_mem = false, 381 .support_off_channel_tx = false, 382 .supports_multi_bssid = false, 383 384 .sram_dump = {}, 385 386 .tcl_ring_retry = true, 387 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 388 .smp2p_wow_exit = false, 389 .support_fw_mac_sequence = false, 390 .support_dual_stations = false, 391 .pdev_suspend = false, 392 .cfr_support = false, 393 .cfr_num_stream_bufs = 0, 394 .cfr_stream_buf_size = 0, 395 }, 396 { 397 .name = "wcn6855 hw2.0", 398 .hw_rev = ATH11K_HW_WCN6855_HW20, 399 .fw = { 400 .dir = "WCN6855/hw2.0", 401 .board_size = 256 * 1024, 402 .cal_offset = 128 * 1024, 403 }, 404 .max_radios = 3, 405 .bdf_addr = 0x4B0C0000, 406 .hw_ops = &wcn6855_ops, 407 .ring_mask = &ath11k_hw_ring_mask_qca6390, 408 .internal_sleep_clock = true, 409 .regs = &wcn6855_regs, 410 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 411 .host_ce_config = ath11k_host_ce_config_qca6390, 412 .ce_count = 9, 413 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 414 .target_ce_count = 9, 415 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 416 .svc_to_ce_map_len = 14, 417 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 418 .single_pdev_only = true, 419 .rxdma1_enable = false, 420 .num_rxdma_per_pdev = 2, 421 .rx_mac_buf_ring = true, 422 .vdev_start_delay = true, 423 .htt_peer_map_v2 = false, 424 425 .spectral = { 426 .fft_sz = 0, 427 .fft_pad_sz = 0, 428 .summary_pad_sz = 0, 429 .fft_hdr_len = 0, 430 .max_fft_bins = 0, 431 .fragment_160mhz = false, 432 }, 433 434 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 435 BIT(NL80211_IFTYPE_AP) | 436 BIT(NL80211_IFTYPE_P2P_DEVICE) | 437 BIT(NL80211_IFTYPE_P2P_CLIENT) | 438 BIT(NL80211_IFTYPE_P2P_GO), 439 .supports_monitor = false, 440 .full_monitor_mode = false, 441 .supports_shadow_regs = true, 442 .idle_ps = true, 443 .supports_sta_ps = true, 444 .coldboot_cal_mm = false, 445 .coldboot_cal_ftm = false, 446 .cbcal_restart_fw = false, 447 .fw_mem_mode = 0, 448 .num_vdevs = 2 + 1, 449 .num_peers = 512, 450 .supports_suspend = true, 451 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 452 .supports_regdb = true, 453 .fix_l1ss = false, 454 .credit_flow = true, 455 .hal_params = &ath11k_hw_hal_params_qca6390, 456 .supports_dynamic_smps_6ghz = false, 457 .alloc_cacheable_memory = false, 458 .supports_rssi_stats = true, 459 .fw_wmi_diag_event = true, 460 .current_cc_support = true, 461 .dbr_debug_support = false, 462 .global_reset = true, 463 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 464 .m3_fw_support = true, 465 .fixed_bdf_addr = false, 466 .fixed_mem_region = false, 467 .static_window_map = false, 468 .hybrid_bus_type = false, 469 .fixed_fw_mem = false, 470 .support_off_channel_tx = true, 471 .supports_multi_bssid = true, 472 473 .sram_dump = { 474 .start = 0x01400000, 475 .end = 0x0177ffff, 476 }, 477 478 .tcl_ring_retry = true, 479 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 480 .smp2p_wow_exit = false, 481 .support_fw_mac_sequence = true, 482 .support_dual_stations = true, 483 .pdev_suspend = false, 484 .cfr_support = false, 485 .cfr_num_stream_bufs = 0, 486 .cfr_stream_buf_size = 0, 487 }, 488 { 489 .name = "wcn6855 hw2.1", 490 .hw_rev = ATH11K_HW_WCN6855_HW21, 491 .fw = { 492 .dir = "WCN6855/hw2.1", 493 .board_size = 256 * 1024, 494 .cal_offset = 128 * 1024, 495 }, 496 .max_radios = 3, 497 .bdf_addr = 0x4B0C0000, 498 .hw_ops = &wcn6855_ops, 499 .ring_mask = &ath11k_hw_ring_mask_qca6390, 500 .internal_sleep_clock = true, 501 .regs = &wcn6855_regs, 502 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 503 .host_ce_config = ath11k_host_ce_config_qca6390, 504 .ce_count = 9, 505 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 506 .target_ce_count = 9, 507 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 508 .svc_to_ce_map_len = 14, 509 .single_pdev_only = true, 510 .rxdma1_enable = false, 511 .num_rxdma_per_pdev = 2, 512 .rx_mac_buf_ring = true, 513 .vdev_start_delay = true, 514 .htt_peer_map_v2 = false, 515 516 .spectral = { 517 .fft_sz = 0, 518 .fft_pad_sz = 0, 519 .summary_pad_sz = 0, 520 .fft_hdr_len = 0, 521 .max_fft_bins = 0, 522 .fragment_160mhz = false, 523 }, 524 525 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 526 BIT(NL80211_IFTYPE_AP) | 527 BIT(NL80211_IFTYPE_P2P_DEVICE) | 528 BIT(NL80211_IFTYPE_P2P_CLIENT) | 529 BIT(NL80211_IFTYPE_P2P_GO), 530 .supports_monitor = false, 531 .supports_shadow_regs = true, 532 .idle_ps = true, 533 .supports_sta_ps = true, 534 .coldboot_cal_mm = false, 535 .coldboot_cal_ftm = false, 536 .cbcal_restart_fw = false, 537 .fw_mem_mode = 0, 538 .num_vdevs = 2 + 1, 539 .num_peers = 512, 540 .supports_suspend = true, 541 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 542 .supports_regdb = true, 543 .fix_l1ss = false, 544 .credit_flow = true, 545 .hal_params = &ath11k_hw_hal_params_qca6390, 546 .supports_dynamic_smps_6ghz = false, 547 .alloc_cacheable_memory = false, 548 .supports_rssi_stats = true, 549 .fw_wmi_diag_event = true, 550 .current_cc_support = true, 551 .dbr_debug_support = false, 552 .global_reset = true, 553 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 554 .m3_fw_support = true, 555 .fixed_bdf_addr = false, 556 .fixed_mem_region = false, 557 .static_window_map = false, 558 .hybrid_bus_type = false, 559 .fixed_fw_mem = false, 560 .support_off_channel_tx = true, 561 .supports_multi_bssid = true, 562 563 .sram_dump = { 564 .start = 0x01400000, 565 .end = 0x0177ffff, 566 }, 567 568 .tcl_ring_retry = true, 569 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 570 .smp2p_wow_exit = false, 571 .support_fw_mac_sequence = true, 572 .support_dual_stations = true, 573 .pdev_suspend = false, 574 .cfr_support = true, 575 .cfr_num_stream_bufs = 255, 576 .cfr_stream_buf_size = 8200, 577 }, 578 { 579 .name = "wcn6750 hw1.0", 580 .hw_rev = ATH11K_HW_WCN6750_HW10, 581 .fw = { 582 .dir = "WCN6750/hw1.0", 583 .board_size = 256 * 1024, 584 .cal_offset = 128 * 1024, 585 }, 586 .max_radios = 1, 587 .bdf_addr = 0x4B0C0000, 588 .hw_ops = &wcn6750_ops, 589 .ring_mask = &ath11k_hw_ring_mask_wcn6750, 590 .internal_sleep_clock = false, 591 .regs = &wcn6750_regs, 592 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750, 593 .host_ce_config = ath11k_host_ce_config_qca6390, 594 .ce_count = 9, 595 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 596 .target_ce_count = 9, 597 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 598 .svc_to_ce_map_len = 14, 599 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 600 .single_pdev_only = true, 601 .rxdma1_enable = false, 602 .num_rxdma_per_pdev = 1, 603 .rx_mac_buf_ring = true, 604 .vdev_start_delay = true, 605 .htt_peer_map_v2 = false, 606 607 .spectral = { 608 .fft_sz = 0, 609 .fft_pad_sz = 0, 610 .summary_pad_sz = 0, 611 .fft_hdr_len = 0, 612 .max_fft_bins = 0, 613 .fragment_160mhz = false, 614 }, 615 616 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 617 BIT(NL80211_IFTYPE_AP), 618 .supports_monitor = false, 619 .supports_shadow_regs = true, 620 .idle_ps = true, 621 .supports_sta_ps = true, 622 .coldboot_cal_mm = true, 623 .coldboot_cal_ftm = true, 624 .cbcal_restart_fw = false, 625 .fw_mem_mode = 0, 626 .num_vdevs = 3, 627 .num_peers = 512, 628 .supports_suspend = false, 629 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 630 .supports_regdb = true, 631 .fix_l1ss = false, 632 .credit_flow = true, 633 .hal_params = &ath11k_hw_hal_params_wcn6750, 634 .supports_dynamic_smps_6ghz = false, 635 .alloc_cacheable_memory = false, 636 .supports_rssi_stats = true, 637 .fw_wmi_diag_event = true, 638 .current_cc_support = true, 639 .dbr_debug_support = false, 640 .global_reset = false, 641 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 642 .m3_fw_support = false, 643 .fixed_bdf_addr = false, 644 .fixed_mem_region = false, 645 .static_window_map = true, 646 .hybrid_bus_type = true, 647 .fixed_fw_mem = true, 648 .support_off_channel_tx = true, 649 .supports_multi_bssid = true, 650 651 .sram_dump = {}, 652 653 .tcl_ring_retry = false, 654 .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750, 655 .smp2p_wow_exit = true, 656 .support_fw_mac_sequence = true, 657 .support_dual_stations = false, 658 .pdev_suspend = true, 659 .cfr_support = false, 660 .cfr_num_stream_bufs = 0, 661 .cfr_stream_buf_size = 0, 662 }, 663 { 664 .hw_rev = ATH11K_HW_IPQ5018_HW10, 665 .name = "ipq5018 hw1.0", 666 .fw = { 667 .dir = "IPQ5018/hw1.0", 668 .board_size = 256 * 1024, 669 .cal_offset = 128 * 1024, 670 }, 671 .max_radios = MAX_RADIOS_5018, 672 .bdf_addr = 0x4BA00000, 673 /* hal_desc_sz and hw ops are similar to qcn9074 */ 674 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 675 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 676 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 677 .credit_flow = false, 678 .spectral = { 679 .fft_sz = 2, 680 .fft_pad_sz = 0, 681 .summary_pad_sz = 16, 682 .fft_hdr_len = 24, 683 .max_fft_bins = 1024, 684 }, 685 .internal_sleep_clock = false, 686 .regs = &ipq5018_regs, 687 .hw_ops = &ipq5018_ops, 688 .host_ce_config = ath11k_host_ce_config_qcn9074, 689 .ce_count = CE_CNT_5018, 690 .target_ce_config = ath11k_target_ce_config_wlan_ipq5018, 691 .target_ce_count = TARGET_CE_CNT_5018, 692 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq5018, 693 .svc_to_ce_map_len = SVC_CE_MAP_LEN_5018, 694 .ce_ie_addr = &ath11k_ce_ie_addr_ipq5018, 695 .ce_remap = &ath11k_ce_remap_ipq5018, 696 .rxdma1_enable = true, 697 .num_rxdma_per_pdev = RXDMA_PER_PDEV_5018, 698 .rx_mac_buf_ring = false, 699 .vdev_start_delay = false, 700 .htt_peer_map_v2 = true, 701 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 702 BIT(NL80211_IFTYPE_AP) | 703 BIT(NL80211_IFTYPE_MESH_POINT), 704 .supports_monitor = false, 705 .supports_sta_ps = false, 706 .supports_shadow_regs = false, 707 .fw_mem_mode = 0, 708 .num_vdevs = 16 + 1, 709 .num_peers = 512, 710 .supports_regdb = false, 711 .idle_ps = false, 712 .supports_suspend = false, 713 .hal_params = &ath11k_hw_hal_params_ipq5018, 714 .single_pdev_only = false, 715 .coldboot_cal_mm = true, 716 .coldboot_cal_ftm = true, 717 .cbcal_restart_fw = true, 718 .fix_l1ss = true, 719 .supports_dynamic_smps_6ghz = false, 720 .alloc_cacheable_memory = true, 721 .supports_rssi_stats = false, 722 .fw_wmi_diag_event = false, 723 .current_cc_support = false, 724 .dbr_debug_support = true, 725 .global_reset = false, 726 .bios_sar_capa = NULL, 727 .m3_fw_support = false, 728 .fixed_bdf_addr = true, 729 .fixed_mem_region = true, 730 .static_window_map = false, 731 .hybrid_bus_type = false, 732 .fixed_fw_mem = false, 733 .support_off_channel_tx = false, 734 .supports_multi_bssid = false, 735 736 .sram_dump = {}, 737 738 .tcl_ring_retry = true, 739 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 740 .smp2p_wow_exit = false, 741 .support_fw_mac_sequence = false, 742 .support_dual_stations = false, 743 .pdev_suspend = false, 744 .cfr_support = false, 745 .cfr_num_stream_bufs = 0, 746 .cfr_stream_buf_size = 0, 747 }, 748 { 749 .name = "qca2066 hw2.1", 750 .hw_rev = ATH11K_HW_QCA2066_HW21, 751 .fw = { 752 .dir = "QCA2066/hw2.1", 753 .board_size = 256 * 1024, 754 .cal_offset = 128 * 1024, 755 }, 756 .max_radios = 3, 757 .bdf_addr = 0x4B0C0000, 758 .hw_ops = &wcn6855_ops, 759 .ring_mask = &ath11k_hw_ring_mask_qca6390, 760 .internal_sleep_clock = true, 761 .regs = &wcn6855_regs, 762 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 763 .host_ce_config = ath11k_host_ce_config_qca6390, 764 .ce_count = 9, 765 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 766 .target_ce_count = 9, 767 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 768 .svc_to_ce_map_len = 14, 769 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 770 .single_pdev_only = true, 771 .rxdma1_enable = false, 772 .num_rxdma_per_pdev = 2, 773 .rx_mac_buf_ring = true, 774 .vdev_start_delay = true, 775 .htt_peer_map_v2 = false, 776 777 .spectral = { 778 .fft_sz = 0, 779 .fft_pad_sz = 0, 780 .summary_pad_sz = 0, 781 .fft_hdr_len = 0, 782 .max_fft_bins = 0, 783 .fragment_160mhz = false, 784 }, 785 786 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 787 BIT(NL80211_IFTYPE_AP) | 788 BIT(NL80211_IFTYPE_P2P_DEVICE) | 789 BIT(NL80211_IFTYPE_P2P_CLIENT) | 790 BIT(NL80211_IFTYPE_P2P_GO), 791 .supports_monitor = false, 792 .full_monitor_mode = false, 793 .supports_shadow_regs = true, 794 .idle_ps = true, 795 .supports_sta_ps = true, 796 .coldboot_cal_mm = false, 797 .coldboot_cal_ftm = false, 798 .cbcal_restart_fw = false, 799 .fw_mem_mode = 0, 800 .num_vdevs = 2 + 1, 801 .num_peers = 512, 802 .supports_suspend = true, 803 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 804 .supports_regdb = true, 805 .fix_l1ss = false, 806 .credit_flow = true, 807 .hal_params = &ath11k_hw_hal_params_qca6390, 808 .supports_dynamic_smps_6ghz = false, 809 .alloc_cacheable_memory = false, 810 .supports_rssi_stats = true, 811 .fw_wmi_diag_event = true, 812 .current_cc_support = true, 813 .dbr_debug_support = false, 814 .global_reset = true, 815 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 816 .m3_fw_support = true, 817 .fixed_bdf_addr = false, 818 .fixed_mem_region = false, 819 .static_window_map = false, 820 .hybrid_bus_type = false, 821 .fixed_fw_mem = false, 822 .support_off_channel_tx = true, 823 .supports_multi_bssid = true, 824 825 .sram_dump = { 826 .start = 0x01400000, 827 .end = 0x0177ffff, 828 }, 829 830 .tcl_ring_retry = true, 831 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 832 .smp2p_wow_exit = false, 833 .support_fw_mac_sequence = true, 834 .support_dual_stations = true, 835 .cfr_support = false, 836 .cfr_num_stream_bufs = 0, 837 .cfr_stream_buf_size = 0, 838 }, 839 { 840 .name = "qca6698aq hw2.1", 841 .hw_rev = ATH11K_HW_QCA6698AQ_HW21, 842 .fw = { 843 .dir = "QCA6698AQ/hw2.1", 844 .board_size = 256 * 1024, 845 .cal_offset = 128 * 1024, 846 }, 847 .max_radios = 3, 848 .bdf_addr = 0x4B0C0000, 849 .hw_ops = &wcn6855_ops, 850 .ring_mask = &ath11k_hw_ring_mask_qca6390, 851 .internal_sleep_clock = true, 852 .regs = &wcn6855_regs, 853 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 854 .host_ce_config = ath11k_host_ce_config_qca6390, 855 .ce_count = 9, 856 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 857 .target_ce_count = 9, 858 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 859 .svc_to_ce_map_len = 14, 860 .single_pdev_only = true, 861 .rxdma1_enable = false, 862 .num_rxdma_per_pdev = 2, 863 .rx_mac_buf_ring = true, 864 .vdev_start_delay = true, 865 .htt_peer_map_v2 = false, 866 867 .spectral = { 868 .fft_sz = 0, 869 .fft_pad_sz = 0, 870 .summary_pad_sz = 0, 871 .fft_hdr_len = 0, 872 .max_fft_bins = 0, 873 .fragment_160mhz = false, 874 }, 875 876 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 877 BIT(NL80211_IFTYPE_AP) | 878 BIT(NL80211_IFTYPE_P2P_DEVICE) | 879 BIT(NL80211_IFTYPE_P2P_CLIENT) | 880 BIT(NL80211_IFTYPE_P2P_GO), 881 .supports_monitor = false, 882 .supports_shadow_regs = true, 883 .idle_ps = true, 884 .supports_sta_ps = true, 885 .coldboot_cal_mm = false, 886 .coldboot_cal_ftm = false, 887 .cbcal_restart_fw = false, 888 .fw_mem_mode = 0, 889 .num_vdevs = 2 + 1, 890 .num_peers = 512, 891 .supports_suspend = true, 892 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 893 .supports_regdb = true, 894 .fix_l1ss = false, 895 .credit_flow = true, 896 .hal_params = &ath11k_hw_hal_params_qca6390, 897 .supports_dynamic_smps_6ghz = false, 898 .alloc_cacheable_memory = false, 899 .supports_rssi_stats = true, 900 .fw_wmi_diag_event = true, 901 .current_cc_support = true, 902 .dbr_debug_support = false, 903 .global_reset = true, 904 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 905 .m3_fw_support = true, 906 .fixed_bdf_addr = false, 907 .fixed_mem_region = false, 908 .static_window_map = false, 909 .hybrid_bus_type = false, 910 .fixed_fw_mem = false, 911 .support_off_channel_tx = true, 912 .supports_multi_bssid = true, 913 914 .sram_dump = { 915 .start = 0x01400000, 916 .end = 0x0177ffff, 917 }, 918 919 .tcl_ring_retry = true, 920 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 921 .smp2p_wow_exit = false, 922 .support_fw_mac_sequence = true, 923 .support_dual_stations = true, 924 .pdev_suspend = false, 925 .cfr_support = true, 926 .cfr_num_stream_bufs = 255, 927 .cfr_stream_buf_size = 8200, 928 }, 929 }; 930 931 static const struct dmi_system_id ath11k_pm_quirk_table[] = { 932 { 933 .driver_data = (void *)ATH11K_PM_WOW, 934 .matches = { /* X13 G4 AMD #1 */ 935 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 936 DMI_MATCH(DMI_PRODUCT_NAME, "21J3"), 937 }, 938 }, 939 { 940 .driver_data = (void *)ATH11K_PM_WOW, 941 .matches = { /* X13 G4 AMD #2 */ 942 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 943 DMI_MATCH(DMI_PRODUCT_NAME, "21J4"), 944 }, 945 }, 946 { 947 .driver_data = (void *)ATH11K_PM_WOW, 948 .matches = { /* T14 G4 AMD #1 */ 949 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 950 DMI_MATCH(DMI_PRODUCT_NAME, "21K3"), 951 }, 952 }, 953 { 954 .driver_data = (void *)ATH11K_PM_WOW, 955 .matches = { /* T14 G4 AMD #2 */ 956 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 957 DMI_MATCH(DMI_PRODUCT_NAME, "21K4"), 958 }, 959 }, 960 { 961 .driver_data = (void *)ATH11K_PM_WOW, 962 .matches = { /* P14s G4 AMD #1 */ 963 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 964 DMI_MATCH(DMI_PRODUCT_NAME, "21K5"), 965 }, 966 }, 967 { 968 .driver_data = (void *)ATH11K_PM_WOW, 969 .matches = { /* P14s G4 AMD #2 */ 970 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 971 DMI_MATCH(DMI_PRODUCT_NAME, "21K6"), 972 }, 973 }, 974 { 975 .driver_data = (void *)ATH11K_PM_WOW, 976 .matches = { /* T16 G2 AMD #1 */ 977 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 978 DMI_MATCH(DMI_PRODUCT_NAME, "21K7"), 979 }, 980 }, 981 { 982 .driver_data = (void *)ATH11K_PM_WOW, 983 .matches = { /* T16 G2 AMD #2 */ 984 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 985 DMI_MATCH(DMI_PRODUCT_NAME, "21K8"), 986 }, 987 }, 988 { 989 .driver_data = (void *)ATH11K_PM_WOW, 990 .matches = { /* P16s G2 AMD #1 */ 991 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 992 DMI_MATCH(DMI_PRODUCT_NAME, "21K9"), 993 }, 994 }, 995 { 996 .driver_data = (void *)ATH11K_PM_WOW, 997 .matches = { /* P16s G2 AMD #2 */ 998 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 999 DMI_MATCH(DMI_PRODUCT_NAME, "21KA"), 1000 }, 1001 }, 1002 { 1003 .driver_data = (void *)ATH11K_PM_WOW, 1004 .matches = { /* T14s G4 AMD #1 */ 1005 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 1006 DMI_MATCH(DMI_PRODUCT_NAME, "21F8"), 1007 }, 1008 }, 1009 { 1010 .driver_data = (void *)ATH11K_PM_WOW, 1011 .matches = { /* T14s G4 AMD #2 */ 1012 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 1013 DMI_MATCH(DMI_PRODUCT_NAME, "21F9"), 1014 }, 1015 }, 1016 { 1017 .driver_data = (void *)ATH11K_PM_WOW, 1018 .matches = { /* Z13 G1 */ 1019 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 1020 DMI_MATCH(DMI_PRODUCT_NAME, "21D2"), 1021 }, 1022 }, 1023 { 1024 .driver_data = (void *)ATH11K_PM_WOW, 1025 .matches = { /* Z13 G1 */ 1026 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 1027 DMI_MATCH(DMI_PRODUCT_NAME, "21D3"), 1028 }, 1029 }, 1030 { 1031 .driver_data = (void *)ATH11K_PM_WOW, 1032 .matches = { /* Z16 G1 */ 1033 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 1034 DMI_MATCH(DMI_PRODUCT_NAME, "21D4"), 1035 }, 1036 }, 1037 { 1038 .driver_data = (void *)ATH11K_PM_WOW, 1039 .matches = { /* Z16 G1 */ 1040 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"), 1041 DMI_MATCH(DMI_PRODUCT_NAME, "21D5"), 1042 }, 1043 }, 1044 {} 1045 }; 1046 1047 static const struct __ath11k_core_usecase_firmware_table { 1048 u32 hw_rev; 1049 const char *compatible; 1050 const char *firmware_name; 1051 } ath11k_core_usecase_firmware_table[] = { 1052 { ATH11K_HW_WCN6855_HW21, "qcom,lemans-evk", "nfa765"}, 1053 { ATH11K_HW_WCN6855_HW21, "qcom,monaco-evk", "nfa765"}, 1054 { ATH11K_HW_WCN6855_HW21, "qcom,hamoa-iot-evk", "nfa765"}, 1055 { /* Sentinel */ } 1056 }; 1057 1058 const char *ath11k_core_get_usecase_firmware(struct ath11k_base *ab) 1059 { 1060 const struct __ath11k_core_usecase_firmware_table *entry = NULL; 1061 1062 entry = ath11k_core_usecase_firmware_table; 1063 while (entry->compatible) { 1064 if (ab->hw_rev == entry->hw_rev && 1065 of_machine_is_compatible(entry->compatible)) 1066 return entry->firmware_name; 1067 entry++; 1068 } 1069 1070 return NULL; 1071 } 1072 EXPORT_SYMBOL(ath11k_core_get_usecase_firmware); 1073 1074 void ath11k_fw_stats_pdevs_free(struct list_head *head) 1075 { 1076 struct ath11k_fw_stats_pdev *i, *tmp; 1077 1078 list_for_each_entry_safe(i, tmp, head, list) { 1079 list_del(&i->list); 1080 kfree(i); 1081 } 1082 } 1083 1084 void ath11k_fw_stats_vdevs_free(struct list_head *head) 1085 { 1086 struct ath11k_fw_stats_vdev *i, *tmp; 1087 1088 list_for_each_entry_safe(i, tmp, head, list) { 1089 list_del(&i->list); 1090 kfree(i); 1091 } 1092 } 1093 1094 void ath11k_fw_stats_bcn_free(struct list_head *head) 1095 { 1096 struct ath11k_fw_stats_bcn *i, *tmp; 1097 1098 list_for_each_entry_safe(i, tmp, head, list) { 1099 list_del(&i->list); 1100 kfree(i); 1101 } 1102 } 1103 1104 void ath11k_fw_stats_init(struct ath11k *ar) 1105 { 1106 INIT_LIST_HEAD(&ar->fw_stats.pdevs); 1107 INIT_LIST_HEAD(&ar->fw_stats.vdevs); 1108 INIT_LIST_HEAD(&ar->fw_stats.bcn); 1109 1110 init_completion(&ar->fw_stats_complete); 1111 init_completion(&ar->fw_stats_done); 1112 } 1113 1114 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats) 1115 { 1116 ath11k_fw_stats_pdevs_free(&stats->pdevs); 1117 ath11k_fw_stats_vdevs_free(&stats->vdevs); 1118 ath11k_fw_stats_bcn_free(&stats->bcn); 1119 } 1120 1121 bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab) 1122 { 1123 if (!ath11k_cold_boot_cal) 1124 return false; 1125 1126 if (ath11k_ftm_mode) 1127 return ab->hw_params.coldboot_cal_ftm; 1128 1129 else 1130 return ab->hw_params.coldboot_cal_mm; 1131 } 1132 1133 /* Check if we need to continue with suspend/resume operation. 1134 * Return: 1135 * a negative value: error happens and don't continue. 1136 * 0: no error but don't continue. 1137 * positive value: no error and do continue. 1138 */ 1139 static int ath11k_core_continue_suspend_resume(struct ath11k_base *ab) 1140 { 1141 struct ath11k *ar; 1142 1143 if (!ab->hw_params.supports_suspend) 1144 return -EOPNOTSUPP; 1145 1146 /* so far single_pdev_only chips have supports_suspend as true 1147 * so pass 0 as a dummy pdev_id here. 1148 */ 1149 ar = ab->pdevs[0].ar; 1150 if (!ar || ar->state != ATH11K_STATE_OFF) 1151 return 0; 1152 1153 return 1; 1154 } 1155 1156 static int ath11k_core_suspend_wow(struct ath11k_base *ab) 1157 { 1158 int ret; 1159 1160 ret = ath11k_dp_rx_pktlog_stop(ab, true); 1161 if (ret) { 1162 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n", 1163 ret); 1164 return ret; 1165 } 1166 1167 /* So far only single_pdev_only devices can reach here, 1168 * so it is valid to handle the first, and the only, pdev. 1169 */ 1170 ret = ath11k_mac_wait_tx_complete(ab->pdevs[0].ar); 1171 if (ret) { 1172 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret); 1173 return ret; 1174 } 1175 1176 ret = ath11k_wow_enable(ab); 1177 if (ret) { 1178 ath11k_warn(ab, "failed to enable wow during suspend: %d\n", ret); 1179 return ret; 1180 } 1181 1182 ret = ath11k_dp_rx_pktlog_stop(ab, false); 1183 if (ret) { 1184 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n", 1185 ret); 1186 return ret; 1187 } 1188 1189 ath11k_ce_stop_shadow_timers(ab); 1190 ath11k_dp_stop_shadow_timers(ab); 1191 1192 ath11k_hif_irq_disable(ab); 1193 ath11k_hif_ce_irq_disable(ab); 1194 1195 ret = ath11k_hif_suspend(ab); 1196 if (ret) { 1197 ath11k_warn(ab, "failed to suspend hif: %d\n", ret); 1198 return ret; 1199 } 1200 1201 return 0; 1202 } 1203 1204 static int ath11k_core_suspend_default(struct ath11k_base *ab) 1205 { 1206 int ret; 1207 1208 ret = ath11k_dp_rx_pktlog_stop(ab, true); 1209 if (ret) { 1210 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n", 1211 ret); 1212 return ret; 1213 } 1214 1215 /* So far only single_pdev_only devices can reach here, 1216 * so it is valid to handle the first, and the only, pdev. 1217 */ 1218 ret = ath11k_mac_wait_tx_complete(ab->pdevs[0].ar); 1219 if (ret) { 1220 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret); 1221 return ret; 1222 } 1223 1224 ret = ath11k_dp_rx_pktlog_stop(ab, false); 1225 if (ret) { 1226 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n", 1227 ret); 1228 return ret; 1229 } 1230 1231 ath11k_ce_stop_shadow_timers(ab); 1232 ath11k_dp_stop_shadow_timers(ab); 1233 1234 /* PM framework skips suspend_late/resume_early callbacks 1235 * if other devices report errors in their suspend callbacks. 1236 * However ath11k_core_resume() would still be called because 1237 * here we return success thus kernel put us on dpm_suspended_list. 1238 * Since we won't go through a power down/up cycle, there is 1239 * no chance to call complete(&ab->restart_completed) in 1240 * ath11k_core_restart(), making ath11k_core_resume() timeout. 1241 * So call it here to avoid this issue. This also works in case 1242 * no error happens thus suspend_late/resume_early get called, 1243 * because it will be reinitialized in ath11k_core_resume_early(). 1244 */ 1245 complete(&ab->restart_completed); 1246 1247 return 0; 1248 } 1249 1250 int ath11k_core_suspend(struct ath11k_base *ab) 1251 { 1252 int ret; 1253 1254 ret = ath11k_core_continue_suspend_resume(ab); 1255 if (ret <= 0) 1256 return ret; 1257 1258 if (ab->actual_pm_policy == ATH11K_PM_WOW) 1259 return ath11k_core_suspend_wow(ab); 1260 1261 return ath11k_core_suspend_default(ab); 1262 } 1263 EXPORT_SYMBOL(ath11k_core_suspend); 1264 1265 int ath11k_core_suspend_late(struct ath11k_base *ab) 1266 { 1267 int ret; 1268 1269 ret = ath11k_core_continue_suspend_resume(ab); 1270 if (ret <= 0) 1271 return ret; 1272 1273 if (ab->actual_pm_policy == ATH11K_PM_WOW) 1274 return 0; 1275 1276 ath11k_hif_irq_disable(ab); 1277 ath11k_hif_ce_irq_disable(ab); 1278 1279 ath11k_hif_power_down(ab, true); 1280 1281 return 0; 1282 } 1283 EXPORT_SYMBOL(ath11k_core_suspend_late); 1284 1285 int ath11k_core_resume_early(struct ath11k_base *ab) 1286 { 1287 int ret; 1288 1289 ret = ath11k_core_continue_suspend_resume(ab); 1290 if (ret <= 0) 1291 return ret; 1292 1293 if (ab->actual_pm_policy == ATH11K_PM_WOW) 1294 return 0; 1295 1296 reinit_completion(&ab->restart_completed); 1297 ret = ath11k_hif_power_up(ab); 1298 if (ret) 1299 ath11k_warn(ab, "failed to power up hif during resume: %d\n", ret); 1300 1301 return ret; 1302 } 1303 EXPORT_SYMBOL(ath11k_core_resume_early); 1304 1305 static int ath11k_core_resume_default(struct ath11k_base *ab) 1306 { 1307 struct ath11k *ar; 1308 long time_left; 1309 int ret; 1310 1311 time_left = wait_for_completion_timeout(&ab->restart_completed, 1312 ATH11K_RESET_TIMEOUT_HZ); 1313 if (time_left == 0) { 1314 ath11k_warn(ab, "timeout while waiting for restart complete"); 1315 return -ETIMEDOUT; 1316 } 1317 1318 /* So far only single_pdev_only devices can reach here, 1319 * so it is valid to handle the first, and the only, pdev. 1320 */ 1321 ar = ab->pdevs[0].ar; 1322 if (ab->hw_params.current_cc_support && 1323 ar->alpha2[0] != 0 && ar->alpha2[1] != 0) { 1324 ret = ath11k_reg_set_cc(ar); 1325 if (ret) { 1326 ath11k_warn(ab, "failed to set country code during resume: %d\n", 1327 ret); 1328 return ret; 1329 } 1330 } 1331 1332 ret = ath11k_dp_rx_pktlog_start(ab); 1333 if (ret) 1334 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n", 1335 ret); 1336 1337 return ret; 1338 } 1339 1340 static int ath11k_core_resume_wow(struct ath11k_base *ab) 1341 { 1342 int ret; 1343 1344 ret = ath11k_hif_resume(ab); 1345 if (ret) { 1346 ath11k_warn(ab, "failed to resume hif during resume: %d\n", ret); 1347 return ret; 1348 } 1349 1350 ath11k_hif_ce_irq_enable(ab); 1351 ath11k_hif_irq_enable(ab); 1352 1353 ret = ath11k_dp_rx_pktlog_start(ab); 1354 if (ret) { 1355 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n", 1356 ret); 1357 return ret; 1358 } 1359 1360 ret = ath11k_wow_wakeup(ab); 1361 if (ret) { 1362 ath11k_warn(ab, "failed to wakeup wow during resume: %d\n", ret); 1363 return ret; 1364 } 1365 1366 return 0; 1367 } 1368 1369 int ath11k_core_resume(struct ath11k_base *ab) 1370 { 1371 int ret; 1372 1373 ret = ath11k_core_continue_suspend_resume(ab); 1374 if (ret <= 0) 1375 return ret; 1376 1377 if (ab->actual_pm_policy == ATH11K_PM_WOW) 1378 return ath11k_core_resume_wow(ab); 1379 1380 return ath11k_core_resume_default(ab); 1381 } 1382 EXPORT_SYMBOL(ath11k_core_resume); 1383 1384 static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data) 1385 { 1386 struct ath11k_base *ab = data; 1387 const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC; 1388 struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr; 1389 ssize_t copied; 1390 size_t len; 1391 int i; 1392 1393 if (ab->qmi.target.bdf_ext[0] != '\0') 1394 return; 1395 1396 if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE) 1397 return; 1398 1399 if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) { 1400 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1401 "wrong smbios bdf ext type length (%d).\n", 1402 hdr->length); 1403 return; 1404 } 1405 1406 spin_lock_bh(&ab->base_lock); 1407 1408 switch (smbios->country_code_flag) { 1409 case ATH11K_SMBIOS_CC_ISO: 1410 ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff; 1411 ab->new_alpha2[1] = smbios->cc_code & 0xff; 1412 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios cc_code %c%c\n", 1413 ab->new_alpha2[0], ab->new_alpha2[1]); 1414 break; 1415 case ATH11K_SMBIOS_CC_WW: 1416 ab->new_alpha2[0] = '0'; 1417 ab->new_alpha2[1] = '0'; 1418 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios worldwide regdomain\n"); 1419 break; 1420 default: 1421 ath11k_dbg(ab, ATH11K_DBG_BOOT, "ignore smbios country code setting %d\n", 1422 smbios->country_code_flag); 1423 break; 1424 } 1425 1426 spin_unlock_bh(&ab->base_lock); 1427 1428 if (!smbios->bdf_enabled) { 1429 ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n"); 1430 return; 1431 } 1432 1433 /* Only one string exists (per spec) */ 1434 if (memcmp(smbios->bdf_ext, magic, strlen(magic)) != 0) { 1435 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1436 "bdf variant magic does not match.\n"); 1437 return; 1438 } 1439 1440 len = min_t(size_t, 1441 strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext)); 1442 for (i = 0; i < len; i++) { 1443 if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) { 1444 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1445 "bdf variant name contains non ascii chars.\n"); 1446 return; 1447 } 1448 } 1449 1450 /* Copy extension name without magic prefix */ 1451 copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic), 1452 sizeof(ab->qmi.target.bdf_ext)); 1453 if (copied < 0) { 1454 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1455 "bdf variant string is longer than the buffer can accommodate\n"); 1456 return; 1457 } 1458 1459 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1460 "found and validated bdf variant smbios_type 0x%x bdf %s\n", 1461 ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext); 1462 } 1463 1464 int ath11k_core_check_smbios(struct ath11k_base *ab) 1465 { 1466 ab->qmi.target.bdf_ext[0] = '\0'; 1467 dmi_walk(ath11k_core_check_cc_code_bdfext, ab); 1468 1469 if (ab->qmi.target.bdf_ext[0] == '\0') 1470 return -ENODATA; 1471 1472 return 0; 1473 } 1474 1475 int ath11k_core_check_dt(struct ath11k_base *ab) 1476 { 1477 size_t max_len = sizeof(ab->qmi.target.bdf_ext); 1478 const char *variant = NULL; 1479 struct device_node *node; 1480 1481 node = ab->dev->of_node; 1482 if (!node) 1483 return -ENOENT; 1484 1485 of_property_read_string(node, "qcom,calibration-variant", 1486 &variant); 1487 if (!variant) 1488 of_property_read_string(node, "qcom,ath11k-calibration-variant", 1489 &variant); 1490 if (!variant) 1491 return -ENODATA; 1492 1493 if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0) 1494 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1495 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 1496 variant); 1497 1498 return 0; 1499 } 1500 1501 enum ath11k_bdf_name_type { 1502 ATH11K_BDF_NAME_FULL, 1503 ATH11K_BDF_NAME_BUS_NAME, 1504 ATH11K_BDF_NAME_CHIP_ID, 1505 }; 1506 1507 static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name, 1508 size_t name_len, bool with_variant, 1509 enum ath11k_bdf_name_type name_type) 1510 { 1511 /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */ 1512 char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = {}; 1513 1514 if (with_variant && ab->qmi.target.bdf_ext[0] != '\0') 1515 scnprintf(variant, sizeof(variant), ",variant=%s", 1516 ab->qmi.target.bdf_ext); 1517 1518 switch (ab->id.bdf_search) { 1519 case ATH11K_BDF_SEARCH_BUS_AND_BOARD: 1520 switch (name_type) { 1521 case ATH11K_BDF_NAME_FULL: 1522 scnprintf(name, name_len, 1523 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s", 1524 ath11k_bus_str(ab->hif.bus), 1525 ab->id.vendor, ab->id.device, 1526 ab->id.subsystem_vendor, 1527 ab->id.subsystem_device, 1528 ab->qmi.target.chip_id, 1529 ab->qmi.target.board_id, 1530 variant); 1531 break; 1532 case ATH11K_BDF_NAME_BUS_NAME: 1533 scnprintf(name, name_len, 1534 "bus=%s", 1535 ath11k_bus_str(ab->hif.bus)); 1536 break; 1537 case ATH11K_BDF_NAME_CHIP_ID: 1538 scnprintf(name, name_len, 1539 "bus=%s,qmi-chip-id=%d", 1540 ath11k_bus_str(ab->hif.bus), 1541 ab->qmi.target.chip_id); 1542 break; 1543 } 1544 break; 1545 default: 1546 scnprintf(name, name_len, 1547 "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s", 1548 ath11k_bus_str(ab->hif.bus), 1549 ab->qmi.target.chip_id, 1550 ab->qmi.target.board_id, variant); 1551 break; 1552 } 1553 1554 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board name '%s'\n", name); 1555 1556 return 0; 1557 } 1558 1559 static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name, 1560 size_t name_len) 1561 { 1562 return __ath11k_core_create_board_name(ab, name, name_len, true, 1563 ATH11K_BDF_NAME_FULL); 1564 } 1565 1566 static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name, 1567 size_t name_len) 1568 { 1569 return __ath11k_core_create_board_name(ab, name, name_len, false, 1570 ATH11K_BDF_NAME_FULL); 1571 } 1572 1573 static int ath11k_core_create_bus_type_board_name(struct ath11k_base *ab, char *name, 1574 size_t name_len) 1575 { 1576 return __ath11k_core_create_board_name(ab, name, name_len, false, 1577 ATH11K_BDF_NAME_BUS_NAME); 1578 } 1579 1580 static int ath11k_core_create_chip_id_board_name(struct ath11k_base *ab, char *name, 1581 size_t name_len) 1582 { 1583 return __ath11k_core_create_board_name(ab, name, name_len, false, 1584 ATH11K_BDF_NAME_CHIP_ID); 1585 } 1586 1587 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab, 1588 const char *file) 1589 { 1590 const struct firmware *fw; 1591 char path[100]; 1592 int ret; 1593 1594 if (file == NULL) 1595 return ERR_PTR(-ENOENT); 1596 1597 ath11k_core_create_firmware_path(ab, file, path, sizeof(path)); 1598 1599 ret = firmware_request_nowarn(&fw, path, ab->dev); 1600 if (ret) 1601 return ERR_PTR(ret); 1602 1603 ath11k_dbg(ab, ATH11K_DBG_BOOT, "firmware request %s size %zu\n", 1604 path, fw->size); 1605 1606 return fw; 1607 } 1608 1609 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) 1610 { 1611 if (!IS_ERR(bd->fw)) 1612 release_firmware(bd->fw); 1613 1614 memset(bd, 0, sizeof(*bd)); 1615 } 1616 1617 static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab, 1618 struct ath11k_board_data *bd, 1619 const void *buf, size_t buf_len, 1620 const char *boardname, 1621 int ie_id, 1622 int name_id, 1623 int data_id) 1624 { 1625 const struct ath11k_fw_ie *hdr; 1626 bool name_match_found; 1627 int ret, board_ie_id; 1628 size_t board_ie_len; 1629 const void *board_ie_data; 1630 1631 name_match_found = false; 1632 1633 /* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */ 1634 while (buf_len > sizeof(struct ath11k_fw_ie)) { 1635 hdr = buf; 1636 board_ie_id = le32_to_cpu(hdr->id); 1637 board_ie_len = le32_to_cpu(hdr->len); 1638 board_ie_data = hdr->data; 1639 1640 buf_len -= sizeof(*hdr); 1641 buf += sizeof(*hdr); 1642 1643 if (buf_len < ALIGN(board_ie_len, 4)) { 1644 ath11k_err(ab, "invalid %s length: %zu < %zu\n", 1645 ath11k_bd_ie_type_str(ie_id), 1646 buf_len, ALIGN(board_ie_len, 4)); 1647 ret = -EINVAL; 1648 goto out; 1649 } 1650 1651 if (board_ie_id == name_id) { 1652 ath11k_dbg_dump(ab, ATH11K_DBG_BOOT, "board name", "", 1653 board_ie_data, board_ie_len); 1654 1655 if (board_ie_len != strlen(boardname)) 1656 goto next; 1657 1658 ret = memcmp(board_ie_data, boardname, strlen(boardname)); 1659 if (ret) 1660 goto next; 1661 1662 name_match_found = true; 1663 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1664 "found match %s for name '%s'", 1665 ath11k_bd_ie_type_str(ie_id), 1666 boardname); 1667 } else if (board_ie_id == data_id) { 1668 if (!name_match_found) 1669 /* no match found */ 1670 goto next; 1671 1672 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1673 "found %s for '%s'", 1674 ath11k_bd_ie_type_str(ie_id), 1675 boardname); 1676 1677 bd->data = board_ie_data; 1678 bd->len = board_ie_len; 1679 1680 ret = 0; 1681 goto out; 1682 } else { 1683 ath11k_warn(ab, "unknown %s id found: %d\n", 1684 ath11k_bd_ie_type_str(ie_id), 1685 board_ie_id); 1686 } 1687 next: 1688 /* jump over the padding */ 1689 board_ie_len = ALIGN(board_ie_len, 4); 1690 1691 buf_len -= board_ie_len; 1692 buf += board_ie_len; 1693 } 1694 1695 /* no match found */ 1696 ret = -ENOENT; 1697 1698 out: 1699 return ret; 1700 } 1701 1702 static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab, 1703 struct ath11k_board_data *bd, 1704 const char *boardname, 1705 int ie_id_match, 1706 int name_id, 1707 int data_id) 1708 { 1709 size_t len, magic_len; 1710 const u8 *data; 1711 char *filename, filepath[100]; 1712 size_t ie_len; 1713 struct ath11k_fw_ie *hdr; 1714 int ret, ie_id; 1715 1716 filename = ATH11K_BOARD_API2_FILE; 1717 1718 if (!bd->fw) 1719 bd->fw = ath11k_core_firmware_request(ab, filename); 1720 1721 if (IS_ERR(bd->fw)) 1722 return PTR_ERR(bd->fw); 1723 1724 data = bd->fw->data; 1725 len = bd->fw->size; 1726 1727 ath11k_core_create_firmware_path(ab, filename, 1728 filepath, sizeof(filepath)); 1729 1730 /* magic has extra null byte padded */ 1731 magic_len = strlen(ATH11K_BOARD_MAGIC) + 1; 1732 if (len < magic_len) { 1733 ath11k_err(ab, "failed to find magic value in %s, file too short: %zu\n", 1734 filepath, len); 1735 ret = -EINVAL; 1736 goto err; 1737 } 1738 1739 if (memcmp(data, ATH11K_BOARD_MAGIC, magic_len)) { 1740 ath11k_err(ab, "found invalid board magic\n"); 1741 ret = -EINVAL; 1742 goto err; 1743 } 1744 1745 /* magic is padded to 4 bytes */ 1746 magic_len = ALIGN(magic_len, 4); 1747 if (len < magic_len) { 1748 ath11k_err(ab, "failed: %s too small to contain board data, len: %zu\n", 1749 filepath, len); 1750 ret = -EINVAL; 1751 goto err; 1752 } 1753 1754 data += magic_len; 1755 len -= magic_len; 1756 1757 while (len > sizeof(struct ath11k_fw_ie)) { 1758 hdr = (struct ath11k_fw_ie *)data; 1759 ie_id = le32_to_cpu(hdr->id); 1760 ie_len = le32_to_cpu(hdr->len); 1761 1762 len -= sizeof(*hdr); 1763 data = hdr->data; 1764 1765 if (len < ALIGN(ie_len, 4)) { 1766 ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n", 1767 ie_id, ie_len, len); 1768 ret = -EINVAL; 1769 goto err; 1770 } 1771 1772 if (ie_id == ie_id_match) { 1773 ret = ath11k_core_parse_bd_ie_board(ab, bd, data, 1774 ie_len, 1775 boardname, 1776 ie_id_match, 1777 name_id, 1778 data_id); 1779 if (ret == -ENOENT) 1780 /* no match found, continue */ 1781 goto next; 1782 else if (ret) 1783 /* there was an error, bail out */ 1784 goto err; 1785 /* either found or error, so stop searching */ 1786 goto out; 1787 } 1788 next: 1789 /* jump over the padding */ 1790 ie_len = ALIGN(ie_len, 4); 1791 1792 len -= ie_len; 1793 data += ie_len; 1794 } 1795 1796 out: 1797 if (!bd->data || !bd->len) { 1798 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1799 "failed to fetch %s for %s from %s\n", 1800 ath11k_bd_ie_type_str(ie_id_match), 1801 boardname, filepath); 1802 ret = -ENODATA; 1803 goto err; 1804 } 1805 1806 return 0; 1807 1808 err: 1809 ath11k_core_free_bdf(ab, bd); 1810 return ret; 1811 } 1812 1813 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab, 1814 struct ath11k_board_data *bd, 1815 const char *name) 1816 { 1817 bd->fw = ath11k_core_firmware_request(ab, name); 1818 1819 if (IS_ERR(bd->fw)) 1820 return PTR_ERR(bd->fw); 1821 1822 bd->data = bd->fw->data; 1823 bd->len = bd->fw->size; 1824 1825 return 0; 1826 } 1827 1828 #define BOARD_NAME_SIZE 200 1829 int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) 1830 { 1831 char *boardname = NULL, *fallback_boardname = NULL, *chip_id_boardname = NULL; 1832 char *filename, filepath[100]; 1833 int bd_api; 1834 int ret = 0; 1835 1836 filename = ATH11K_BOARD_API2_FILE; 1837 boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL); 1838 if (!boardname) { 1839 ret = -ENOMEM; 1840 goto exit; 1841 } 1842 1843 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE); 1844 if (ret) { 1845 ath11k_err(ab, "failed to create board name: %d", ret); 1846 goto exit; 1847 } 1848 1849 bd_api = 2; 1850 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname, 1851 ATH11K_BD_IE_BOARD, 1852 ATH11K_BD_IE_BOARD_NAME, 1853 ATH11K_BD_IE_BOARD_DATA); 1854 if (!ret) 1855 goto exit; 1856 1857 fallback_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL); 1858 if (!fallback_boardname) { 1859 ret = -ENOMEM; 1860 goto exit; 1861 } 1862 1863 ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname, 1864 BOARD_NAME_SIZE); 1865 if (ret) { 1866 ath11k_err(ab, "failed to create fallback board name: %d", ret); 1867 goto exit; 1868 } 1869 1870 ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname, 1871 ATH11K_BD_IE_BOARD, 1872 ATH11K_BD_IE_BOARD_NAME, 1873 ATH11K_BD_IE_BOARD_DATA); 1874 if (!ret) 1875 goto exit; 1876 1877 chip_id_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL); 1878 if (!chip_id_boardname) { 1879 ret = -ENOMEM; 1880 goto exit; 1881 } 1882 1883 ret = ath11k_core_create_chip_id_board_name(ab, chip_id_boardname, 1884 BOARD_NAME_SIZE); 1885 if (ret) { 1886 ath11k_err(ab, "failed to create chip id board name: %d", ret); 1887 goto exit; 1888 } 1889 1890 ret = ath11k_core_fetch_board_data_api_n(ab, bd, chip_id_boardname, 1891 ATH11K_BD_IE_BOARD, 1892 ATH11K_BD_IE_BOARD_NAME, 1893 ATH11K_BD_IE_BOARD_DATA); 1894 1895 if (!ret) 1896 goto exit; 1897 1898 bd_api = 1; 1899 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE); 1900 if (ret) { 1901 ath11k_core_create_firmware_path(ab, filename, 1902 filepath, sizeof(filepath)); 1903 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1904 boardname, filepath); 1905 if (memcmp(boardname, fallback_boardname, strlen(boardname))) 1906 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1907 fallback_boardname, filepath); 1908 1909 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1910 chip_id_boardname, filepath); 1911 1912 ath11k_err(ab, "failed to fetch board.bin from %s\n", 1913 ab->hw_params.fw.dir); 1914 } 1915 1916 exit: 1917 kfree(boardname); 1918 kfree(fallback_boardname); 1919 kfree(chip_id_boardname); 1920 1921 if (!ret) 1922 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", bd_api); 1923 1924 return ret; 1925 } 1926 1927 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd) 1928 { 1929 char boardname[BOARD_NAME_SIZE], default_boardname[BOARD_NAME_SIZE]; 1930 int ret; 1931 1932 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE); 1933 if (ret) { 1934 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1935 "failed to create board name for regdb: %d", ret); 1936 goto exit; 1937 } 1938 1939 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname, 1940 ATH11K_BD_IE_REGDB, 1941 ATH11K_BD_IE_REGDB_NAME, 1942 ATH11K_BD_IE_REGDB_DATA); 1943 if (!ret) 1944 goto exit; 1945 1946 ret = ath11k_core_create_bus_type_board_name(ab, default_boardname, 1947 BOARD_NAME_SIZE); 1948 if (ret) { 1949 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1950 "failed to create default board name for regdb: %d", ret); 1951 goto exit; 1952 } 1953 1954 ret = ath11k_core_fetch_board_data_api_n(ab, bd, default_boardname, 1955 ATH11K_BD_IE_REGDB, 1956 ATH11K_BD_IE_REGDB_NAME, 1957 ATH11K_BD_IE_REGDB_DATA); 1958 if (!ret) 1959 goto exit; 1960 1961 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME); 1962 if (ret) 1963 ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n", 1964 ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir); 1965 1966 exit: 1967 if (!ret) 1968 ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n"); 1969 1970 return ret; 1971 } 1972 1973 static void ath11k_core_stop(struct ath11k_base *ab) 1974 { 1975 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags)) 1976 ath11k_qmi_firmware_stop(ab); 1977 1978 ath11k_hif_stop(ab); 1979 ath11k_wmi_detach(ab); 1980 ath11k_dp_pdev_reo_cleanup(ab); 1981 1982 /* De-Init of components as needed */ 1983 } 1984 1985 static int ath11k_core_soc_create(struct ath11k_base *ab) 1986 { 1987 int ret; 1988 1989 if (ath11k_ftm_mode) { 1990 ab->fw_mode = ATH11K_FIRMWARE_MODE_FTM; 1991 ath11k_info(ab, "Booting in factory test mode\n"); 1992 } 1993 1994 ret = ath11k_qmi_init_service(ab); 1995 if (ret) { 1996 ath11k_err(ab, "failed to initialize qmi :%d\n", ret); 1997 return ret; 1998 } 1999 2000 ret = ath11k_debugfs_soc_create(ab); 2001 if (ret) { 2002 ath11k_err(ab, "failed to create ath11k debugfs\n"); 2003 goto err_qmi_deinit; 2004 } 2005 2006 ret = ath11k_hif_power_up(ab); 2007 if (ret) { 2008 ath11k_err(ab, "failed to power up :%d\n", ret); 2009 goto err_debugfs_reg; 2010 } 2011 2012 return 0; 2013 2014 err_debugfs_reg: 2015 ath11k_debugfs_soc_destroy(ab); 2016 err_qmi_deinit: 2017 ath11k_qmi_deinit_service(ab); 2018 return ret; 2019 } 2020 2021 static void ath11k_core_soc_destroy(struct ath11k_base *ab) 2022 { 2023 ath11k_debugfs_soc_destroy(ab); 2024 ath11k_dp_free(ab); 2025 ath11k_reg_free(ab); 2026 ath11k_qmi_deinit_service(ab); 2027 } 2028 2029 static int ath11k_core_pdev_create(struct ath11k_base *ab) 2030 { 2031 int ret; 2032 2033 ret = ath11k_debugfs_pdev_create(ab); 2034 if (ret) { 2035 ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret); 2036 return ret; 2037 } 2038 2039 ret = ath11k_dp_pdev_alloc(ab); 2040 if (ret) { 2041 ath11k_err(ab, "failed to attach DP pdev: %d\n", ret); 2042 goto err_pdev_debug; 2043 } 2044 2045 ret = ath11k_mac_register(ab); 2046 if (ret) { 2047 ath11k_err(ab, "failed register the radio with mac80211: %d\n", ret); 2048 goto err_dp_pdev_free; 2049 } 2050 2051 ret = ath11k_thermal_register(ab); 2052 if (ret) { 2053 ath11k_err(ab, "could not register thermal device: %d\n", 2054 ret); 2055 goto err_mac_unregister; 2056 } 2057 2058 ret = ath11k_spectral_init(ab); 2059 if (ret) { 2060 ath11k_err(ab, "failed to init spectral %d\n", ret); 2061 goto err_thermal_unregister; 2062 } 2063 2064 ret = ath11k_cfr_init(ab); 2065 if (ret) { 2066 ath11k_err(ab, "failed to init cfr %d\n", ret); 2067 goto err_spectral_unregister; 2068 } 2069 2070 return 0; 2071 2072 err_spectral_unregister: 2073 ath11k_spectral_deinit(ab); 2074 err_thermal_unregister: 2075 ath11k_thermal_unregister(ab); 2076 err_mac_unregister: 2077 ath11k_mac_unregister(ab); 2078 err_dp_pdev_free: 2079 ath11k_dp_pdev_free(ab); 2080 err_pdev_debug: 2081 ath11k_debugfs_pdev_destroy(ab); 2082 2083 return ret; 2084 } 2085 2086 static void ath11k_core_pdev_suspend_target(struct ath11k_base *ab) 2087 { 2088 struct ath11k *ar; 2089 struct ath11k_pdev *pdev; 2090 unsigned long time_left; 2091 int ret; 2092 int i; 2093 2094 if (!ab->hw_params.pdev_suspend) 2095 return; 2096 2097 for (i = 0; i < ab->num_radios; i++) { 2098 pdev = &ab->pdevs[i]; 2099 ar = pdev->ar; 2100 2101 reinit_completion(&ab->htc_suspend); 2102 2103 ret = ath11k_wmi_pdev_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR, 2104 pdev->pdev_id); 2105 if (ret) { 2106 ath11k_warn(ab, "could not suspend target :%d\n", ret); 2107 /* pointless to try other pdevs */ 2108 return; 2109 } 2110 2111 time_left = wait_for_completion_timeout(&ab->htc_suspend, 3 * HZ); 2112 2113 if (!time_left) { 2114 ath11k_warn(ab, "suspend timed out - target pause event never came\n"); 2115 /* pointless to try other pdevs */ 2116 return; 2117 } 2118 } 2119 } 2120 2121 static void ath11k_core_pdev_destroy(struct ath11k_base *ab) 2122 { 2123 ath11k_cfr_deinit(ab); 2124 ath11k_spectral_deinit(ab); 2125 ath11k_thermal_unregister(ab); 2126 ath11k_mac_unregister(ab); 2127 ath11k_core_pdev_suspend_target(ab); 2128 ath11k_hif_irq_disable(ab); 2129 ath11k_dp_pdev_free(ab); 2130 ath11k_debugfs_pdev_destroy(ab); 2131 } 2132 2133 static int ath11k_core_start(struct ath11k_base *ab) 2134 { 2135 int ret; 2136 2137 ret = ath11k_wmi_attach(ab); 2138 if (ret) { 2139 ath11k_err(ab, "failed to attach wmi: %d\n", ret); 2140 return ret; 2141 } 2142 2143 ret = ath11k_htc_init(ab); 2144 if (ret) { 2145 ath11k_err(ab, "failed to init htc: %d\n", ret); 2146 goto err_wmi_detach; 2147 } 2148 2149 ret = ath11k_hif_start(ab); 2150 if (ret) { 2151 ath11k_err(ab, "failed to start HIF: %d\n", ret); 2152 goto err_wmi_detach; 2153 } 2154 2155 ret = ath11k_htc_wait_target(&ab->htc); 2156 if (ret) { 2157 ath11k_err(ab, "failed to connect to HTC: %d\n", ret); 2158 goto err_hif_stop; 2159 } 2160 2161 ret = ath11k_dp_htt_connect(&ab->dp); 2162 if (ret) { 2163 ath11k_err(ab, "failed to connect to HTT: %d\n", ret); 2164 goto err_hif_stop; 2165 } 2166 2167 ret = ath11k_wmi_connect(ab); 2168 if (ret) { 2169 ath11k_err(ab, "failed to connect wmi: %d\n", ret); 2170 goto err_hif_stop; 2171 } 2172 2173 ret = ath11k_htc_start(&ab->htc); 2174 if (ret) { 2175 ath11k_err(ab, "failed to start HTC: %d\n", ret); 2176 goto err_hif_stop; 2177 } 2178 2179 ret = ath11k_wmi_wait_for_service_ready(ab); 2180 if (ret) { 2181 ath11k_err(ab, "failed to receive wmi service ready event: %d\n", 2182 ret); 2183 goto err_hif_stop; 2184 } 2185 2186 ret = ath11k_mac_allocate(ab); 2187 if (ret) { 2188 ath11k_err(ab, "failed to create new hw device with mac80211 :%d\n", 2189 ret); 2190 goto err_hif_stop; 2191 } 2192 2193 ath11k_dp_pdev_pre_alloc(ab); 2194 2195 ret = ath11k_dp_pdev_reo_setup(ab); 2196 if (ret) { 2197 ath11k_err(ab, "failed to initialize reo destination rings: %d\n", ret); 2198 goto err_mac_destroy; 2199 } 2200 2201 ret = ath11k_wmi_cmd_init(ab); 2202 if (ret) { 2203 ath11k_err(ab, "failed to send wmi init cmd: %d\n", ret); 2204 goto err_reo_cleanup; 2205 } 2206 2207 ret = ath11k_wmi_wait_for_unified_ready(ab); 2208 if (ret) { 2209 ath11k_err(ab, "failed to receive wmi unified ready event: %d\n", 2210 ret); 2211 goto err_reo_cleanup; 2212 } 2213 2214 /* put hardware to DBS mode */ 2215 if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxdma_per_pdev > 1) { 2216 ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS); 2217 if (ret) { 2218 ath11k_err(ab, "failed to send dbs mode: %d\n", ret); 2219 goto err_hif_stop; 2220 } 2221 } 2222 2223 ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab); 2224 if (ret) { 2225 ath11k_err(ab, "failed to send htt version request message: %d\n", 2226 ret); 2227 goto err_reo_cleanup; 2228 } 2229 2230 return 0; 2231 2232 err_reo_cleanup: 2233 ath11k_dp_pdev_reo_cleanup(ab); 2234 err_mac_destroy: 2235 ath11k_mac_destroy(ab); 2236 err_hif_stop: 2237 ath11k_hif_stop(ab); 2238 err_wmi_detach: 2239 ath11k_wmi_detach(ab); 2240 2241 return ret; 2242 } 2243 2244 static int ath11k_core_start_firmware(struct ath11k_base *ab, 2245 enum ath11k_firmware_mode mode) 2246 { 2247 int ret; 2248 2249 ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2, 2250 &ab->qmi.ce_cfg.shadow_reg_v2_len); 2251 2252 ret = ath11k_qmi_firmware_start(ab, mode); 2253 if (ret) { 2254 ath11k_err(ab, "failed to send firmware start: %d\n", ret); 2255 return ret; 2256 } 2257 2258 return ret; 2259 } 2260 2261 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab) 2262 { 2263 int ret; 2264 2265 switch (ath11k_crypto_mode) { 2266 case ATH11K_CRYPT_MODE_SW: 2267 set_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags); 2268 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 2269 break; 2270 case ATH11K_CRYPT_MODE_HW: 2271 clear_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags); 2272 clear_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 2273 break; 2274 default: 2275 ath11k_info(ab, "invalid crypto_mode: %d\n", ath11k_crypto_mode); 2276 return -EINVAL; 2277 } 2278 2279 ret = ath11k_core_start_firmware(ab, ab->fw_mode); 2280 if (ret) { 2281 ath11k_err(ab, "failed to start firmware: %d\n", ret); 2282 return ret; 2283 } 2284 2285 ret = ath11k_ce_init_pipes(ab); 2286 if (ret) { 2287 ath11k_err(ab, "failed to initialize CE: %d\n", ret); 2288 goto err_firmware_stop; 2289 } 2290 2291 ret = ath11k_dp_alloc(ab); 2292 if (ret) { 2293 ath11k_err(ab, "failed to init DP: %d\n", ret); 2294 goto err_firmware_stop; 2295 } 2296 2297 if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW) 2298 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 2299 2300 mutex_lock(&ab->core_lock); 2301 ret = ath11k_core_start(ab); 2302 if (ret) { 2303 ath11k_err(ab, "failed to start core: %d\n", ret); 2304 goto err_dp_free; 2305 } 2306 2307 ret = ath11k_core_pdev_create(ab); 2308 if (ret) { 2309 ath11k_err(ab, "failed to create pdev core: %d\n", ret); 2310 goto err_core_stop; 2311 } 2312 ath11k_hif_irq_enable(ab); 2313 mutex_unlock(&ab->core_lock); 2314 2315 return 0; 2316 2317 err_core_stop: 2318 ath11k_core_stop(ab); 2319 ath11k_mac_destroy(ab); 2320 err_dp_free: 2321 ath11k_dp_free(ab); 2322 mutex_unlock(&ab->core_lock); 2323 err_firmware_stop: 2324 ath11k_qmi_firmware_stop(ab); 2325 2326 return ret; 2327 } 2328 2329 static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab) 2330 { 2331 int ret; 2332 2333 mutex_lock(&ab->core_lock); 2334 ath11k_thermal_unregister(ab); 2335 ath11k_dp_pdev_free(ab); 2336 ath11k_cfr_deinit(ab); 2337 ath11k_spectral_deinit(ab); 2338 ath11k_ce_cleanup_pipes(ab); 2339 ath11k_wmi_detach(ab); 2340 ath11k_dp_pdev_reo_cleanup(ab); 2341 mutex_unlock(&ab->core_lock); 2342 2343 ath11k_dp_free(ab); 2344 ath11k_hal_srng_clear(ab); 2345 2346 ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1; 2347 2348 clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags); 2349 2350 ret = ath11k_core_qmi_firmware_ready(ab); 2351 if (ret) 2352 goto err_hal_srng_deinit; 2353 2354 clear_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags); 2355 2356 return 0; 2357 2358 err_hal_srng_deinit: 2359 ath11k_hal_srng_deinit(ab); 2360 return ret; 2361 } 2362 2363 void ath11k_core_halt(struct ath11k *ar) 2364 { 2365 struct ath11k_base *ab = ar->ab; 2366 struct list_head *pos, *n; 2367 2368 lockdep_assert_held(&ar->conf_mutex); 2369 2370 ar->num_created_vdevs = 0; 2371 ar->allocated_vdev_map = 0; 2372 2373 ath11k_mac_scan_finish(ar); 2374 ath11k_mac_peer_cleanup_all(ar); 2375 cancel_delayed_work_sync(&ar->scan.timeout); 2376 cancel_work_sync(&ar->channel_update_work); 2377 cancel_work_sync(&ar->regd_update_work); 2378 cancel_work_sync(&ab->update_11d_work); 2379 2380 rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL); 2381 synchronize_rcu(); 2382 2383 spin_lock_bh(&ar->data_lock); 2384 list_for_each_safe(pos, n, &ar->arvifs) 2385 list_del_init(pos); 2386 spin_unlock_bh(&ar->data_lock); 2387 2388 idr_init(&ar->txmgmt_idr); 2389 } 2390 2391 static void ath11k_update_11d(struct work_struct *work) 2392 { 2393 struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work); 2394 struct ath11k *ar; 2395 struct ath11k_pdev *pdev; 2396 int ret, i; 2397 2398 for (i = 0; i < ab->num_radios; i++) { 2399 pdev = &ab->pdevs[i]; 2400 ar = pdev->ar; 2401 2402 spin_lock_bh(&ab->base_lock); 2403 memcpy(&ar->alpha2, &ab->new_alpha2, 2); 2404 spin_unlock_bh(&ab->base_lock); 2405 2406 ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c for pdev %d\n", 2407 ar->alpha2[0], ar->alpha2[1], i); 2408 2409 ret = ath11k_reg_set_cc(ar); 2410 if (ret) 2411 ath11k_warn(ar->ab, 2412 "pdev id %d failed set current country code: %d\n", 2413 i, ret); 2414 } 2415 } 2416 2417 void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab) 2418 { 2419 struct ath11k *ar; 2420 struct ath11k_pdev *pdev; 2421 int i; 2422 2423 spin_lock_bh(&ab->base_lock); 2424 ab->stats.fw_crash_counter++; 2425 spin_unlock_bh(&ab->base_lock); 2426 2427 for (i = 0; i < ab->num_radios; i++) { 2428 pdev = &ab->pdevs[i]; 2429 ar = pdev->ar; 2430 if (!ar || ar->state == ATH11K_STATE_OFF || 2431 ar->state == ATH11K_STATE_FTM) 2432 continue; 2433 2434 ieee80211_stop_queues(ar->hw); 2435 ath11k_mac_drain_tx(ar); 2436 ar->state_11d = ATH11K_11D_IDLE; 2437 complete(&ar->completed_11d_scan); 2438 complete(&ar->scan.started); 2439 complete_all(&ar->scan.completed); 2440 complete(&ar->scan.on_channel); 2441 complete(&ar->peer_assoc_done); 2442 complete(&ar->peer_delete_done); 2443 complete(&ar->install_key_done); 2444 complete(&ar->vdev_setup_done); 2445 complete(&ar->vdev_delete_done); 2446 complete(&ar->bss_survey_done); 2447 complete(&ar->thermal.wmi_sync); 2448 2449 wake_up(&ar->dp.tx_empty_waitq); 2450 idr_for_each(&ar->txmgmt_idr, 2451 ath11k_mac_tx_mgmt_pending_free, ar); 2452 idr_destroy(&ar->txmgmt_idr); 2453 wake_up(&ar->txmgmt_empty_waitq); 2454 2455 ar->monitor_vdev_id = -1; 2456 clear_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags); 2457 clear_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags); 2458 } 2459 2460 wake_up(&ab->wmi_ab.tx_credits_wq); 2461 wake_up(&ab->peer_mapping_wq); 2462 2463 reinit_completion(&ab->driver_recovery); 2464 } 2465 2466 static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab) 2467 { 2468 struct ath11k *ar; 2469 struct ath11k_pdev *pdev; 2470 int i; 2471 2472 for (i = 0; i < ab->num_radios; i++) { 2473 pdev = &ab->pdevs[i]; 2474 ar = pdev->ar; 2475 if (!ar || ar->state == ATH11K_STATE_OFF) 2476 continue; 2477 2478 mutex_lock(&ar->conf_mutex); 2479 2480 switch (ar->state) { 2481 case ATH11K_STATE_ON: 2482 ar->state = ATH11K_STATE_RESTARTING; 2483 ath11k_core_halt(ar); 2484 ieee80211_restart_hw(ar->hw); 2485 break; 2486 case ATH11K_STATE_OFF: 2487 ath11k_warn(ab, 2488 "cannot restart radio %d that hasn't been started\n", 2489 i); 2490 break; 2491 case ATH11K_STATE_RESTARTING: 2492 break; 2493 case ATH11K_STATE_RESTARTED: 2494 ar->state = ATH11K_STATE_WEDGED; 2495 fallthrough; 2496 case ATH11K_STATE_WEDGED: 2497 ath11k_warn(ab, 2498 "device is wedged, will not restart radio %d\n", i); 2499 break; 2500 case ATH11K_STATE_FTM: 2501 ath11k_dbg(ab, ATH11K_DBG_TESTMODE, 2502 "fw mode reset done radio %d\n", i); 2503 break; 2504 } 2505 2506 mutex_unlock(&ar->conf_mutex); 2507 } 2508 complete(&ab->driver_recovery); 2509 } 2510 2511 static void ath11k_core_restart(struct work_struct *work) 2512 { 2513 struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work); 2514 int ret; 2515 2516 ret = ath11k_core_reconfigure_on_crash(ab); 2517 if (ret) { 2518 ath11k_err(ab, "failed to reconfigure driver on crash recovery\n"); 2519 return; 2520 } 2521 2522 if (ab->is_reset) 2523 complete_all(&ab->reconfigure_complete); 2524 2525 if (!ab->is_reset) 2526 ath11k_core_post_reconfigure_recovery(ab); 2527 2528 complete(&ab->restart_completed); 2529 } 2530 2531 static void ath11k_core_reset(struct work_struct *work) 2532 { 2533 struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work); 2534 int reset_count, fail_cont_count; 2535 long time_left; 2536 2537 if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) { 2538 ath11k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags); 2539 return; 2540 } 2541 2542 /* Sometimes the recovery will fail and then the next all recovery fail, 2543 * this is to avoid infinite recovery since it can not recovery success. 2544 */ 2545 fail_cont_count = atomic_read(&ab->fail_cont_count); 2546 2547 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL) 2548 return; 2549 2550 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST && 2551 time_before(jiffies, ab->reset_fail_timeout)) 2552 return; 2553 2554 reset_count = atomic_inc_return(&ab->reset_count); 2555 2556 if (reset_count > 1) { 2557 /* Sometimes it happened another reset worker before the previous one 2558 * completed, then the second reset worker will destroy the previous one, 2559 * thus below is to avoid that. 2560 */ 2561 ath11k_warn(ab, "already resetting count %d\n", reset_count); 2562 2563 reinit_completion(&ab->reset_complete); 2564 time_left = wait_for_completion_timeout(&ab->reset_complete, 2565 ATH11K_RESET_TIMEOUT_HZ); 2566 2567 if (time_left) { 2568 ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n"); 2569 atomic_dec(&ab->reset_count); 2570 return; 2571 } 2572 2573 ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ; 2574 /* Record the continuous recovery fail count when recovery failed*/ 2575 atomic_inc(&ab->fail_cont_count); 2576 } 2577 2578 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n"); 2579 2580 ab->is_reset = true; 2581 atomic_set(&ab->recovery_count, 0); 2582 reinit_completion(&ab->recovery_start); 2583 atomic_set(&ab->recovery_start_count, 0); 2584 2585 ath11k_coredump_collect(ab); 2586 ath11k_core_pre_reconfigure_recovery(ab); 2587 2588 reinit_completion(&ab->reconfigure_complete); 2589 ath11k_core_post_reconfigure_recovery(ab); 2590 2591 ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n"); 2592 2593 time_left = wait_for_completion_timeout(&ab->recovery_start, 2594 ATH11K_RECOVER_START_TIMEOUT_HZ); 2595 2596 ath11k_hif_irq_disable(ab); 2597 ath11k_hif_ce_irq_disable(ab); 2598 2599 ath11k_hif_power_down(ab, false); 2600 ath11k_hif_power_up(ab); 2601 2602 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n"); 2603 } 2604 2605 static int ath11k_init_hw_params(struct ath11k_base *ab) 2606 { 2607 const struct ath11k_hw_params *hw_params = NULL; 2608 int i; 2609 2610 for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) { 2611 hw_params = &ath11k_hw_params[i]; 2612 2613 if (hw_params->hw_rev == ab->hw_rev) 2614 break; 2615 } 2616 2617 if (i == ARRAY_SIZE(ath11k_hw_params)) { 2618 ath11k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev); 2619 return -EINVAL; 2620 } 2621 2622 ab->hw_params = *hw_params; 2623 2624 ath11k_info(ab, "%s\n", ab->hw_params.name); 2625 2626 return 0; 2627 } 2628 2629 int ath11k_core_pre_init(struct ath11k_base *ab) 2630 { 2631 int ret; 2632 2633 ret = ath11k_init_hw_params(ab); 2634 if (ret) { 2635 ath11k_err(ab, "failed to get hw params: %d\n", ret); 2636 return ret; 2637 } 2638 2639 ret = ath11k_fw_pre_init(ab); 2640 if (ret) { 2641 ath11k_err(ab, "failed to pre init firmware: %d", ret); 2642 return ret; 2643 } 2644 2645 return 0; 2646 } 2647 EXPORT_SYMBOL(ath11k_core_pre_init); 2648 2649 static int ath11k_core_pm_notify(struct notifier_block *nb, 2650 unsigned long action, void *nouse) 2651 { 2652 struct ath11k_base *ab = container_of(nb, struct ath11k_base, 2653 pm_nb); 2654 2655 switch (action) { 2656 case PM_SUSPEND_PREPARE: 2657 ab->actual_pm_policy = ab->pm_policy; 2658 break; 2659 case PM_HIBERNATION_PREPARE: 2660 ab->actual_pm_policy = ATH11K_PM_DEFAULT; 2661 break; 2662 default: 2663 break; 2664 } 2665 2666 return NOTIFY_OK; 2667 } 2668 2669 static int ath11k_core_pm_notifier_register(struct ath11k_base *ab) 2670 { 2671 ab->pm_nb.notifier_call = ath11k_core_pm_notify; 2672 return register_pm_notifier(&ab->pm_nb); 2673 } 2674 2675 void ath11k_core_pm_notifier_unregister(struct ath11k_base *ab) 2676 { 2677 int ret; 2678 2679 ret = unregister_pm_notifier(&ab->pm_nb); 2680 if (ret) 2681 /* just warn here, there is nothing can be done in fail case */ 2682 ath11k_warn(ab, "failed to unregister PM notifier %d\n", ret); 2683 } 2684 EXPORT_SYMBOL(ath11k_core_pm_notifier_unregister); 2685 2686 int ath11k_core_init(struct ath11k_base *ab) 2687 { 2688 const struct dmi_system_id *dmi_id; 2689 int ret; 2690 2691 dmi_id = dmi_first_match(ath11k_pm_quirk_table); 2692 if (dmi_id) 2693 ab->pm_policy = (kernel_ulong_t)dmi_id->driver_data; 2694 else 2695 ab->pm_policy = ATH11K_PM_DEFAULT; 2696 2697 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pm policy %u\n", ab->pm_policy); 2698 2699 ret = ath11k_core_pm_notifier_register(ab); 2700 if (ret) { 2701 ath11k_err(ab, "failed to register PM notifier: %d\n", ret); 2702 return ret; 2703 } 2704 2705 ret = ath11k_core_soc_create(ab); 2706 if (ret) { 2707 ath11k_err(ab, "failed to create soc core: %d\n", ret); 2708 goto err_unregister_pm_notifier; 2709 } 2710 2711 return 0; 2712 2713 err_unregister_pm_notifier: 2714 ath11k_core_pm_notifier_unregister(ab); 2715 2716 return ret; 2717 } 2718 EXPORT_SYMBOL(ath11k_core_init); 2719 2720 void ath11k_core_deinit(struct ath11k_base *ab) 2721 { 2722 mutex_lock(&ab->core_lock); 2723 2724 ath11k_core_pdev_destroy(ab); 2725 ath11k_core_stop(ab); 2726 2727 mutex_unlock(&ab->core_lock); 2728 2729 ath11k_hif_power_down(ab, false); 2730 ath11k_mac_destroy(ab); 2731 ath11k_core_soc_destroy(ab); 2732 ath11k_core_pm_notifier_unregister(ab); 2733 } 2734 EXPORT_SYMBOL(ath11k_core_deinit); 2735 2736 void ath11k_core_free(struct ath11k_base *ab) 2737 { 2738 destroy_workqueue(ab->workqueue_aux); 2739 destroy_workqueue(ab->workqueue); 2740 2741 kfree(ab); 2742 } 2743 EXPORT_SYMBOL(ath11k_core_free); 2744 2745 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size, 2746 enum ath11k_bus bus) 2747 { 2748 struct ath11k_base *ab; 2749 2750 ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL); 2751 if (!ab) 2752 return NULL; 2753 2754 init_completion(&ab->driver_recovery); 2755 2756 ab->workqueue = create_singlethread_workqueue("ath11k_wq"); 2757 if (!ab->workqueue) 2758 goto err_sc_free; 2759 2760 ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq"); 2761 if (!ab->workqueue_aux) 2762 goto err_free_wq; 2763 2764 mutex_init(&ab->core_lock); 2765 mutex_init(&ab->tbl_mtx_lock); 2766 spin_lock_init(&ab->base_lock); 2767 mutex_init(&ab->vdev_id_11d_lock); 2768 init_completion(&ab->reset_complete); 2769 init_completion(&ab->reconfigure_complete); 2770 init_completion(&ab->recovery_start); 2771 2772 INIT_LIST_HEAD(&ab->peers); 2773 init_waitqueue_head(&ab->peer_mapping_wq); 2774 init_waitqueue_head(&ab->wmi_ab.tx_credits_wq); 2775 init_waitqueue_head(&ab->qmi.cold_boot_waitq); 2776 INIT_WORK(&ab->restart_work, ath11k_core_restart); 2777 INIT_WORK(&ab->update_11d_work, ath11k_update_11d); 2778 INIT_WORK(&ab->reset_work, ath11k_core_reset); 2779 INIT_WORK(&ab->dump_work, ath11k_coredump_upload); 2780 timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0); 2781 init_completion(&ab->htc_suspend); 2782 init_completion(&ab->wow.wakeup_completed); 2783 init_completion(&ab->restart_completed); 2784 2785 ab->dev = dev; 2786 ab->hif.bus = bus; 2787 2788 return ab; 2789 2790 err_free_wq: 2791 destroy_workqueue(ab->workqueue); 2792 err_sc_free: 2793 kfree(ab); 2794 return NULL; 2795 } 2796 EXPORT_SYMBOL(ath11k_core_alloc); 2797 2798 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards."); 2799 MODULE_LICENSE("Dual BSD/GPL"); 2800