1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/module.h>
8 #include <linux/slab.h>
9 #include <linux/remoteproc.h>
10 #include <linux/firmware.h>
11 #include <linux/of.h>
12
13 #include "core.h"
14 #include "dp_tx.h"
15 #include "dp_rx.h"
16 #include "debug.h"
17 #include "hif.h"
18 #include "wow.h"
19 #include "fw.h"
20
21 unsigned int ath11k_debug_mask;
22 EXPORT_SYMBOL(ath11k_debug_mask);
23 module_param_named(debug_mask, ath11k_debug_mask, uint, 0644);
24 MODULE_PARM_DESC(debug_mask, "Debugging mask");
25
26 static unsigned int ath11k_crypto_mode;
27 module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644);
28 MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software");
29
30 /* frame mode values are mapped as per enum ath11k_hw_txrx_mode */
31 unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI;
32 module_param_named(frame_mode, ath11k_frame_mode, uint, 0644);
33 MODULE_PARM_DESC(frame_mode,
34 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)");
35
36 bool ath11k_ftm_mode;
37 module_param_named(ftm_mode, ath11k_ftm_mode, bool, 0444);
38 MODULE_PARM_DESC(ftm_mode, "Boots up in factory test mode");
39
40 static const struct ath11k_hw_params ath11k_hw_params[] = {
41 {
42 .hw_rev = ATH11K_HW_IPQ8074,
43 .name = "ipq8074 hw2.0",
44 .fw = {
45 .dir = "IPQ8074/hw2.0",
46 .board_size = 256 * 1024,
47 .cal_offset = 128 * 1024,
48 },
49 .max_radios = 3,
50 .bdf_addr = 0x4B0C0000,
51 .hw_ops = &ipq8074_ops,
52 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
53 .internal_sleep_clock = false,
54 .regs = &ipq8074_regs,
55 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
56 .host_ce_config = ath11k_host_ce_config_ipq8074,
57 .ce_count = 12,
58 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
59 .target_ce_count = 11,
60 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074,
61 .svc_to_ce_map_len = 21,
62 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
63 .single_pdev_only = false,
64 .rxdma1_enable = true,
65 .num_rxdma_per_pdev = 1,
66 .rx_mac_buf_ring = false,
67 .vdev_start_delay = false,
68 .htt_peer_map_v2 = true,
69
70 .spectral = {
71 .fft_sz = 2,
72 /* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes.
73 * so added pad size as 2 bytes to compensate the BIN size
74 */
75 .fft_pad_sz = 2,
76 .summary_pad_sz = 0,
77 .fft_hdr_len = 16,
78 .max_fft_bins = 512,
79 .fragment_160mhz = true,
80 },
81
82 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
83 BIT(NL80211_IFTYPE_AP) |
84 BIT(NL80211_IFTYPE_MESH_POINT),
85 .supports_monitor = true,
86 .full_monitor_mode = false,
87 .supports_shadow_regs = false,
88 .idle_ps = false,
89 .supports_sta_ps = false,
90 .coldboot_cal_mm = true,
91 .coldboot_cal_ftm = true,
92 .cbcal_restart_fw = true,
93 .fw_mem_mode = 0,
94 .num_vdevs = 16 + 1,
95 .num_peers = 512,
96 .supports_suspend = false,
97 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
98 .supports_regdb = false,
99 .fix_l1ss = true,
100 .credit_flow = false,
101 .max_tx_ring = DP_TCL_NUM_RING_MAX,
102 .hal_params = &ath11k_hw_hal_params_ipq8074,
103 .supports_dynamic_smps_6ghz = false,
104 .alloc_cacheable_memory = true,
105 .supports_rssi_stats = false,
106 .fw_wmi_diag_event = false,
107 .current_cc_support = false,
108 .dbr_debug_support = true,
109 .global_reset = false,
110 .bios_sar_capa = NULL,
111 .m3_fw_support = false,
112 .fixed_bdf_addr = true,
113 .fixed_mem_region = true,
114 .static_window_map = false,
115 .hybrid_bus_type = false,
116 .fixed_fw_mem = false,
117 .support_off_channel_tx = false,
118 .supports_multi_bssid = false,
119
120 .sram_dump = {},
121
122 .tcl_ring_retry = true,
123 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
124 .smp2p_wow_exit = false,
125 .support_dual_stations = false,
126 .pdev_suspend = false,
127 },
128 {
129 .hw_rev = ATH11K_HW_IPQ6018_HW10,
130 .name = "ipq6018 hw1.0",
131 .fw = {
132 .dir = "IPQ6018/hw1.0",
133 .board_size = 256 * 1024,
134 .cal_offset = 128 * 1024,
135 },
136 .max_radios = 2,
137 .bdf_addr = 0x4ABC0000,
138 .hw_ops = &ipq6018_ops,
139 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
140 .internal_sleep_clock = false,
141 .regs = &ipq8074_regs,
142 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
143 .host_ce_config = ath11k_host_ce_config_ipq8074,
144 .ce_count = 12,
145 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
146 .target_ce_count = 11,
147 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018,
148 .svc_to_ce_map_len = 19,
149 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
150 .single_pdev_only = false,
151 .rxdma1_enable = true,
152 .num_rxdma_per_pdev = 1,
153 .rx_mac_buf_ring = false,
154 .vdev_start_delay = false,
155 .htt_peer_map_v2 = true,
156
157 .spectral = {
158 .fft_sz = 4,
159 .fft_pad_sz = 0,
160 .summary_pad_sz = 0,
161 .fft_hdr_len = 16,
162 .max_fft_bins = 512,
163 .fragment_160mhz = true,
164 },
165
166 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
167 BIT(NL80211_IFTYPE_AP) |
168 BIT(NL80211_IFTYPE_MESH_POINT),
169 .supports_monitor = true,
170 .full_monitor_mode = false,
171 .supports_shadow_regs = false,
172 .idle_ps = false,
173 .supports_sta_ps = false,
174 .coldboot_cal_mm = true,
175 .coldboot_cal_ftm = true,
176 .cbcal_restart_fw = true,
177 .fw_mem_mode = 0,
178 .num_vdevs = 16 + 1,
179 .num_peers = 512,
180 .supports_suspend = false,
181 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
182 .supports_regdb = false,
183 .fix_l1ss = true,
184 .credit_flow = false,
185 .max_tx_ring = DP_TCL_NUM_RING_MAX,
186 .hal_params = &ath11k_hw_hal_params_ipq8074,
187 .supports_dynamic_smps_6ghz = false,
188 .alloc_cacheable_memory = true,
189 .supports_rssi_stats = false,
190 .fw_wmi_diag_event = false,
191 .current_cc_support = false,
192 .dbr_debug_support = true,
193 .global_reset = false,
194 .bios_sar_capa = NULL,
195 .m3_fw_support = false,
196 .fixed_bdf_addr = true,
197 .fixed_mem_region = true,
198 .static_window_map = false,
199 .hybrid_bus_type = false,
200 .fixed_fw_mem = false,
201 .support_off_channel_tx = false,
202 .supports_multi_bssid = false,
203
204 .sram_dump = {},
205
206 .tcl_ring_retry = true,
207 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
208 .smp2p_wow_exit = false,
209 .support_fw_mac_sequence = false,
210 .support_dual_stations = false,
211 .pdev_suspend = false,
212 },
213 {
214 .name = "qca6390 hw2.0",
215 .hw_rev = ATH11K_HW_QCA6390_HW20,
216 .fw = {
217 .dir = "QCA6390/hw2.0",
218 .board_size = 256 * 1024,
219 .cal_offset = 128 * 1024,
220 },
221 .max_radios = 3,
222 .bdf_addr = 0x4B0C0000,
223 .hw_ops = &qca6390_ops,
224 .ring_mask = &ath11k_hw_ring_mask_qca6390,
225 .internal_sleep_clock = true,
226 .regs = &qca6390_regs,
227 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
228 .host_ce_config = ath11k_host_ce_config_qca6390,
229 .ce_count = 9,
230 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
231 .target_ce_count = 9,
232 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
233 .svc_to_ce_map_len = 14,
234 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
235 .single_pdev_only = true,
236 .rxdma1_enable = false,
237 .num_rxdma_per_pdev = 2,
238 .rx_mac_buf_ring = true,
239 .vdev_start_delay = true,
240 .htt_peer_map_v2 = false,
241
242 .spectral = {
243 .fft_sz = 0,
244 .fft_pad_sz = 0,
245 .summary_pad_sz = 0,
246 .fft_hdr_len = 0,
247 .max_fft_bins = 0,
248 .fragment_160mhz = false,
249 },
250
251 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
252 BIT(NL80211_IFTYPE_AP) |
253 BIT(NL80211_IFTYPE_P2P_DEVICE) |
254 BIT(NL80211_IFTYPE_P2P_CLIENT) |
255 BIT(NL80211_IFTYPE_P2P_GO),
256 .supports_monitor = false,
257 .full_monitor_mode = false,
258 .supports_shadow_regs = true,
259 .idle_ps = true,
260 .supports_sta_ps = true,
261 .coldboot_cal_mm = false,
262 .coldboot_cal_ftm = false,
263 .cbcal_restart_fw = false,
264 .fw_mem_mode = 0,
265 .num_vdevs = 2 + 1,
266 .num_peers = 512,
267 .supports_suspend = true,
268 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
269 .supports_regdb = false,
270 .fix_l1ss = true,
271 .credit_flow = true,
272 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
273 .hal_params = &ath11k_hw_hal_params_qca6390,
274 .supports_dynamic_smps_6ghz = false,
275 .alloc_cacheable_memory = false,
276 .supports_rssi_stats = true,
277 .fw_wmi_diag_event = true,
278 .current_cc_support = true,
279 .dbr_debug_support = false,
280 .global_reset = true,
281 .bios_sar_capa = NULL,
282 .m3_fw_support = true,
283 .fixed_bdf_addr = false,
284 .fixed_mem_region = false,
285 .static_window_map = false,
286 .hybrid_bus_type = false,
287 .fixed_fw_mem = false,
288 .support_off_channel_tx = true,
289 .supports_multi_bssid = true,
290
291 .sram_dump = {
292 .start = 0x01400000,
293 .end = 0x0171ffff,
294 },
295
296 .tcl_ring_retry = true,
297 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
298 .smp2p_wow_exit = false,
299 .support_fw_mac_sequence = true,
300 .support_dual_stations = true,
301 .pdev_suspend = false,
302 },
303 {
304 .name = "qcn9074 hw1.0",
305 .hw_rev = ATH11K_HW_QCN9074_HW10,
306 .fw = {
307 .dir = "QCN9074/hw1.0",
308 .board_size = 256 * 1024,
309 .cal_offset = 128 * 1024,
310 },
311 .max_radios = 1,
312 .single_pdev_only = false,
313 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074,
314 .hw_ops = &qcn9074_ops,
315 .ring_mask = &ath11k_hw_ring_mask_qcn9074,
316 .internal_sleep_clock = false,
317 .regs = &qcn9074_regs,
318 .host_ce_config = ath11k_host_ce_config_qcn9074,
319 .ce_count = 6,
320 .target_ce_config = ath11k_target_ce_config_wlan_qcn9074,
321 .target_ce_count = 9,
322 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074,
323 .svc_to_ce_map_len = 18,
324 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
325 .rxdma1_enable = true,
326 .num_rxdma_per_pdev = 1,
327 .rx_mac_buf_ring = false,
328 .vdev_start_delay = false,
329 .htt_peer_map_v2 = true,
330
331 .spectral = {
332 .fft_sz = 2,
333 .fft_pad_sz = 0,
334 .summary_pad_sz = 16,
335 .fft_hdr_len = 24,
336 .max_fft_bins = 1024,
337 .fragment_160mhz = false,
338 },
339
340 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
341 BIT(NL80211_IFTYPE_AP) |
342 BIT(NL80211_IFTYPE_MESH_POINT),
343 .supports_monitor = true,
344 .full_monitor_mode = true,
345 .supports_shadow_regs = false,
346 .idle_ps = false,
347 .supports_sta_ps = false,
348 .coldboot_cal_mm = false,
349 .coldboot_cal_ftm = true,
350 .cbcal_restart_fw = true,
351 .fw_mem_mode = 2,
352 .num_vdevs = 8,
353 .num_peers = 128,
354 .supports_suspend = false,
355 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
356 .supports_regdb = false,
357 .fix_l1ss = true,
358 .credit_flow = false,
359 .max_tx_ring = DP_TCL_NUM_RING_MAX,
360 .hal_params = &ath11k_hw_hal_params_ipq8074,
361 .supports_dynamic_smps_6ghz = true,
362 .alloc_cacheable_memory = true,
363 .supports_rssi_stats = false,
364 .fw_wmi_diag_event = false,
365 .current_cc_support = false,
366 .dbr_debug_support = true,
367 .global_reset = false,
368 .bios_sar_capa = NULL,
369 .m3_fw_support = true,
370 .fixed_bdf_addr = false,
371 .fixed_mem_region = false,
372 .static_window_map = true,
373 .hybrid_bus_type = false,
374 .fixed_fw_mem = false,
375 .support_off_channel_tx = false,
376 .supports_multi_bssid = false,
377
378 .sram_dump = {},
379
380 .tcl_ring_retry = true,
381 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
382 .smp2p_wow_exit = false,
383 .support_fw_mac_sequence = false,
384 .support_dual_stations = false,
385 .pdev_suspend = false,
386 },
387 {
388 .name = "wcn6855 hw2.0",
389 .hw_rev = ATH11K_HW_WCN6855_HW20,
390 .fw = {
391 .dir = "WCN6855/hw2.0",
392 .board_size = 256 * 1024,
393 .cal_offset = 128 * 1024,
394 },
395 .max_radios = 3,
396 .bdf_addr = 0x4B0C0000,
397 .hw_ops = &wcn6855_ops,
398 .ring_mask = &ath11k_hw_ring_mask_qca6390,
399 .internal_sleep_clock = true,
400 .regs = &wcn6855_regs,
401 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
402 .host_ce_config = ath11k_host_ce_config_qca6390,
403 .ce_count = 9,
404 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
405 .target_ce_count = 9,
406 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
407 .svc_to_ce_map_len = 14,
408 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
409 .single_pdev_only = true,
410 .rxdma1_enable = false,
411 .num_rxdma_per_pdev = 2,
412 .rx_mac_buf_ring = true,
413 .vdev_start_delay = true,
414 .htt_peer_map_v2 = false,
415
416 .spectral = {
417 .fft_sz = 0,
418 .fft_pad_sz = 0,
419 .summary_pad_sz = 0,
420 .fft_hdr_len = 0,
421 .max_fft_bins = 0,
422 .fragment_160mhz = false,
423 },
424
425 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
426 BIT(NL80211_IFTYPE_AP) |
427 BIT(NL80211_IFTYPE_P2P_DEVICE) |
428 BIT(NL80211_IFTYPE_P2P_CLIENT) |
429 BIT(NL80211_IFTYPE_P2P_GO),
430 .supports_monitor = false,
431 .full_monitor_mode = false,
432 .supports_shadow_regs = true,
433 .idle_ps = true,
434 .supports_sta_ps = true,
435 .coldboot_cal_mm = false,
436 .coldboot_cal_ftm = false,
437 .cbcal_restart_fw = false,
438 .fw_mem_mode = 0,
439 .num_vdevs = 2 + 1,
440 .num_peers = 512,
441 .supports_suspend = true,
442 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
443 .supports_regdb = true,
444 .fix_l1ss = false,
445 .credit_flow = true,
446 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
447 .hal_params = &ath11k_hw_hal_params_qca6390,
448 .supports_dynamic_smps_6ghz = false,
449 .alloc_cacheable_memory = false,
450 .supports_rssi_stats = true,
451 .fw_wmi_diag_event = true,
452 .current_cc_support = true,
453 .dbr_debug_support = false,
454 .global_reset = true,
455 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
456 .m3_fw_support = true,
457 .fixed_bdf_addr = false,
458 .fixed_mem_region = false,
459 .static_window_map = false,
460 .hybrid_bus_type = false,
461 .fixed_fw_mem = false,
462 .support_off_channel_tx = true,
463 .supports_multi_bssid = true,
464
465 .sram_dump = {
466 .start = 0x01400000,
467 .end = 0x0177ffff,
468 },
469
470 .tcl_ring_retry = true,
471 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
472 .smp2p_wow_exit = false,
473 .support_fw_mac_sequence = true,
474 .support_dual_stations = true,
475 .pdev_suspend = false,
476 },
477 {
478 .name = "wcn6855 hw2.1",
479 .hw_rev = ATH11K_HW_WCN6855_HW21,
480 .fw = {
481 .dir = "WCN6855/hw2.1",
482 .board_size = 256 * 1024,
483 .cal_offset = 128 * 1024,
484 },
485 .max_radios = 3,
486 .bdf_addr = 0x4B0C0000,
487 .hw_ops = &wcn6855_ops,
488 .ring_mask = &ath11k_hw_ring_mask_qca6390,
489 .internal_sleep_clock = true,
490 .regs = &wcn6855_regs,
491 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
492 .host_ce_config = ath11k_host_ce_config_qca6390,
493 .ce_count = 9,
494 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
495 .target_ce_count = 9,
496 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
497 .svc_to_ce_map_len = 14,
498 .single_pdev_only = true,
499 .rxdma1_enable = false,
500 .num_rxdma_per_pdev = 2,
501 .rx_mac_buf_ring = true,
502 .vdev_start_delay = true,
503 .htt_peer_map_v2 = false,
504
505 .spectral = {
506 .fft_sz = 0,
507 .fft_pad_sz = 0,
508 .summary_pad_sz = 0,
509 .fft_hdr_len = 0,
510 .max_fft_bins = 0,
511 .fragment_160mhz = false,
512 },
513
514 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
515 BIT(NL80211_IFTYPE_AP) |
516 BIT(NL80211_IFTYPE_P2P_DEVICE) |
517 BIT(NL80211_IFTYPE_P2P_CLIENT) |
518 BIT(NL80211_IFTYPE_P2P_GO),
519 .supports_monitor = false,
520 .supports_shadow_regs = true,
521 .idle_ps = true,
522 .supports_sta_ps = true,
523 .coldboot_cal_mm = false,
524 .coldboot_cal_ftm = false,
525 .cbcal_restart_fw = false,
526 .fw_mem_mode = 0,
527 .num_vdevs = 2 + 1,
528 .num_peers = 512,
529 .supports_suspend = true,
530 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
531 .supports_regdb = true,
532 .fix_l1ss = false,
533 .credit_flow = true,
534 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
535 .hal_params = &ath11k_hw_hal_params_qca6390,
536 .supports_dynamic_smps_6ghz = false,
537 .alloc_cacheable_memory = false,
538 .supports_rssi_stats = true,
539 .fw_wmi_diag_event = true,
540 .current_cc_support = true,
541 .dbr_debug_support = false,
542 .global_reset = true,
543 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
544 .m3_fw_support = true,
545 .fixed_bdf_addr = false,
546 .fixed_mem_region = false,
547 .static_window_map = false,
548 .hybrid_bus_type = false,
549 .fixed_fw_mem = false,
550 .support_off_channel_tx = true,
551 .supports_multi_bssid = true,
552
553 .sram_dump = {
554 .start = 0x01400000,
555 .end = 0x0177ffff,
556 },
557
558 .tcl_ring_retry = true,
559 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
560 .smp2p_wow_exit = false,
561 .support_fw_mac_sequence = true,
562 .support_dual_stations = true,
563 .pdev_suspend = false,
564 },
565 {
566 .name = "wcn6750 hw1.0",
567 .hw_rev = ATH11K_HW_WCN6750_HW10,
568 .fw = {
569 .dir = "WCN6750/hw1.0",
570 .board_size = 256 * 1024,
571 .cal_offset = 128 * 1024,
572 },
573 .max_radios = 1,
574 .bdf_addr = 0x4B0C0000,
575 .hw_ops = &wcn6750_ops,
576 .ring_mask = &ath11k_hw_ring_mask_wcn6750,
577 .internal_sleep_clock = false,
578 .regs = &wcn6750_regs,
579 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750,
580 .host_ce_config = ath11k_host_ce_config_qca6390,
581 .ce_count = 9,
582 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
583 .target_ce_count = 9,
584 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
585 .svc_to_ce_map_len = 14,
586 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
587 .single_pdev_only = true,
588 .rxdma1_enable = false,
589 .num_rxdma_per_pdev = 1,
590 .rx_mac_buf_ring = true,
591 .vdev_start_delay = true,
592 .htt_peer_map_v2 = false,
593
594 .spectral = {
595 .fft_sz = 0,
596 .fft_pad_sz = 0,
597 .summary_pad_sz = 0,
598 .fft_hdr_len = 0,
599 .max_fft_bins = 0,
600 .fragment_160mhz = false,
601 },
602
603 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
604 BIT(NL80211_IFTYPE_AP),
605 .supports_monitor = false,
606 .supports_shadow_regs = true,
607 .idle_ps = true,
608 .supports_sta_ps = true,
609 .coldboot_cal_mm = true,
610 .coldboot_cal_ftm = true,
611 .cbcal_restart_fw = false,
612 .fw_mem_mode = 0,
613 .num_vdevs = 3,
614 .num_peers = 512,
615 .supports_suspend = false,
616 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
617 .supports_regdb = true,
618 .fix_l1ss = false,
619 .credit_flow = true,
620 .max_tx_ring = DP_TCL_NUM_RING_MAX,
621 .hal_params = &ath11k_hw_hal_params_wcn6750,
622 .supports_dynamic_smps_6ghz = false,
623 .alloc_cacheable_memory = false,
624 .supports_rssi_stats = true,
625 .fw_wmi_diag_event = true,
626 .current_cc_support = true,
627 .dbr_debug_support = false,
628 .global_reset = false,
629 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
630 .m3_fw_support = false,
631 .fixed_bdf_addr = false,
632 .fixed_mem_region = false,
633 .static_window_map = true,
634 .hybrid_bus_type = true,
635 .fixed_fw_mem = true,
636 .support_off_channel_tx = true,
637 .supports_multi_bssid = true,
638
639 .sram_dump = {},
640
641 .tcl_ring_retry = false,
642 .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750,
643 .smp2p_wow_exit = true,
644 .support_fw_mac_sequence = true,
645 .support_dual_stations = false,
646 .pdev_suspend = true,
647 },
648 {
649 .hw_rev = ATH11K_HW_IPQ5018_HW10,
650 .name = "ipq5018 hw1.0",
651 .fw = {
652 .dir = "IPQ5018/hw1.0",
653 .board_size = 256 * 1024,
654 .cal_offset = 128 * 1024,
655 },
656 .max_radios = MAX_RADIOS_5018,
657 .bdf_addr = 0x4BA00000,
658 /* hal_desc_sz and hw ops are similar to qcn9074 */
659 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
660 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
661 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
662 .credit_flow = false,
663 .max_tx_ring = 1,
664 .spectral = {
665 .fft_sz = 2,
666 .fft_pad_sz = 0,
667 .summary_pad_sz = 16,
668 .fft_hdr_len = 24,
669 .max_fft_bins = 1024,
670 },
671 .internal_sleep_clock = false,
672 .regs = &ipq5018_regs,
673 .hw_ops = &ipq5018_ops,
674 .host_ce_config = ath11k_host_ce_config_qcn9074,
675 .ce_count = CE_CNT_5018,
676 .target_ce_config = ath11k_target_ce_config_wlan_ipq5018,
677 .target_ce_count = TARGET_CE_CNT_5018,
678 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq5018,
679 .svc_to_ce_map_len = SVC_CE_MAP_LEN_5018,
680 .ce_ie_addr = &ath11k_ce_ie_addr_ipq5018,
681 .ce_remap = &ath11k_ce_remap_ipq5018,
682 .rxdma1_enable = true,
683 .num_rxdma_per_pdev = RXDMA_PER_PDEV_5018,
684 .rx_mac_buf_ring = false,
685 .vdev_start_delay = false,
686 .htt_peer_map_v2 = true,
687 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
688 BIT(NL80211_IFTYPE_AP) |
689 BIT(NL80211_IFTYPE_MESH_POINT),
690 .supports_monitor = false,
691 .supports_sta_ps = false,
692 .supports_shadow_regs = false,
693 .fw_mem_mode = 0,
694 .num_vdevs = 16 + 1,
695 .num_peers = 512,
696 .supports_regdb = false,
697 .idle_ps = false,
698 .supports_suspend = false,
699 .hal_params = &ath11k_hw_hal_params_ipq8074,
700 .single_pdev_only = false,
701 .coldboot_cal_mm = true,
702 .coldboot_cal_ftm = true,
703 .cbcal_restart_fw = true,
704 .fix_l1ss = true,
705 .supports_dynamic_smps_6ghz = false,
706 .alloc_cacheable_memory = true,
707 .supports_rssi_stats = false,
708 .fw_wmi_diag_event = false,
709 .current_cc_support = false,
710 .dbr_debug_support = true,
711 .global_reset = false,
712 .bios_sar_capa = NULL,
713 .m3_fw_support = false,
714 .fixed_bdf_addr = true,
715 .fixed_mem_region = true,
716 .static_window_map = false,
717 .hybrid_bus_type = false,
718 .fixed_fw_mem = false,
719 .support_off_channel_tx = false,
720 .supports_multi_bssid = false,
721
722 .sram_dump = {},
723
724 .tcl_ring_retry = true,
725 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
726 .smp2p_wow_exit = false,
727 .support_fw_mac_sequence = false,
728 .support_dual_stations = false,
729 .pdev_suspend = false,
730 },
731 {
732 .name = "qca2066 hw2.1",
733 .hw_rev = ATH11K_HW_QCA2066_HW21,
734 .fw = {
735 .dir = "QCA2066/hw2.1",
736 .board_size = 256 * 1024,
737 .cal_offset = 128 * 1024,
738 },
739 .max_radios = 3,
740 .bdf_addr = 0x4B0C0000,
741 .hw_ops = &wcn6855_ops,
742 .ring_mask = &ath11k_hw_ring_mask_qca6390,
743 .internal_sleep_clock = true,
744 .regs = &wcn6855_regs,
745 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
746 .host_ce_config = ath11k_host_ce_config_qca6390,
747 .ce_count = 9,
748 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
749 .target_ce_count = 9,
750 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
751 .svc_to_ce_map_len = 14,
752 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
753 .single_pdev_only = true,
754 .rxdma1_enable = false,
755 .num_rxdma_per_pdev = 2,
756 .rx_mac_buf_ring = true,
757 .vdev_start_delay = true,
758 .htt_peer_map_v2 = false,
759
760 .spectral = {
761 .fft_sz = 0,
762 .fft_pad_sz = 0,
763 .summary_pad_sz = 0,
764 .fft_hdr_len = 0,
765 .max_fft_bins = 0,
766 .fragment_160mhz = false,
767 },
768
769 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
770 BIT(NL80211_IFTYPE_AP) |
771 BIT(NL80211_IFTYPE_P2P_DEVICE) |
772 BIT(NL80211_IFTYPE_P2P_CLIENT) |
773 BIT(NL80211_IFTYPE_P2P_GO),
774 .supports_monitor = false,
775 .full_monitor_mode = false,
776 .supports_shadow_regs = true,
777 .idle_ps = true,
778 .supports_sta_ps = true,
779 .coldboot_cal_mm = false,
780 .coldboot_cal_ftm = false,
781 .cbcal_restart_fw = false,
782 .fw_mem_mode = 0,
783 .num_vdevs = 2 + 1,
784 .num_peers = 512,
785 .supports_suspend = true,
786 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
787 .supports_regdb = true,
788 .fix_l1ss = false,
789 .credit_flow = true,
790 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
791 .hal_params = &ath11k_hw_hal_params_qca6390,
792 .supports_dynamic_smps_6ghz = false,
793 .alloc_cacheable_memory = false,
794 .supports_rssi_stats = true,
795 .fw_wmi_diag_event = true,
796 .current_cc_support = true,
797 .dbr_debug_support = false,
798 .global_reset = true,
799 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
800 .m3_fw_support = true,
801 .fixed_bdf_addr = false,
802 .fixed_mem_region = false,
803 .static_window_map = false,
804 .hybrid_bus_type = false,
805 .fixed_fw_mem = false,
806 .support_off_channel_tx = true,
807 .supports_multi_bssid = true,
808
809 .sram_dump = {
810 .start = 0x01400000,
811 .end = 0x0177ffff,
812 },
813
814 .tcl_ring_retry = true,
815 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
816 .smp2p_wow_exit = false,
817 .support_fw_mac_sequence = true,
818 .support_dual_stations = true,
819 },
820 {
821 .name = "qca6698aq hw2.1",
822 .hw_rev = ATH11K_HW_QCA6698AQ_HW21,
823 .fw = {
824 .dir = "QCA6698AQ/hw2.1",
825 .board_size = 256 * 1024,
826 .cal_offset = 128 * 1024,
827 },
828 .max_radios = 3,
829 .bdf_addr = 0x4B0C0000,
830 .hw_ops = &wcn6855_ops,
831 .ring_mask = &ath11k_hw_ring_mask_qca6390,
832 .internal_sleep_clock = true,
833 .regs = &wcn6855_regs,
834 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
835 .host_ce_config = ath11k_host_ce_config_qca6390,
836 .ce_count = 9,
837 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
838 .target_ce_count = 9,
839 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
840 .svc_to_ce_map_len = 14,
841 .single_pdev_only = true,
842 .rxdma1_enable = false,
843 .num_rxdma_per_pdev = 2,
844 .rx_mac_buf_ring = true,
845 .vdev_start_delay = true,
846 .htt_peer_map_v2 = false,
847
848 .spectral = {
849 .fft_sz = 0,
850 .fft_pad_sz = 0,
851 .summary_pad_sz = 0,
852 .fft_hdr_len = 0,
853 .max_fft_bins = 0,
854 .fragment_160mhz = false,
855 },
856
857 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
858 BIT(NL80211_IFTYPE_AP) |
859 BIT(NL80211_IFTYPE_P2P_DEVICE) |
860 BIT(NL80211_IFTYPE_P2P_CLIENT) |
861 BIT(NL80211_IFTYPE_P2P_GO),
862 .supports_monitor = false,
863 .supports_shadow_regs = true,
864 .idle_ps = true,
865 .supports_sta_ps = true,
866 .coldboot_cal_mm = false,
867 .coldboot_cal_ftm = false,
868 .cbcal_restart_fw = false,
869 .fw_mem_mode = 0,
870 .num_vdevs = 2 + 1,
871 .num_peers = 512,
872 .supports_suspend = true,
873 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
874 .supports_regdb = true,
875 .fix_l1ss = false,
876 .credit_flow = true,
877 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
878 .hal_params = &ath11k_hw_hal_params_qca6390,
879 .supports_dynamic_smps_6ghz = false,
880 .alloc_cacheable_memory = false,
881 .supports_rssi_stats = true,
882 .fw_wmi_diag_event = true,
883 .current_cc_support = true,
884 .dbr_debug_support = false,
885 .global_reset = true,
886 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
887 .m3_fw_support = true,
888 .fixed_bdf_addr = false,
889 .fixed_mem_region = false,
890 .static_window_map = false,
891 .hybrid_bus_type = false,
892 .fixed_fw_mem = false,
893 .support_off_channel_tx = true,
894 .supports_multi_bssid = true,
895
896 .sram_dump = {
897 .start = 0x01400000,
898 .end = 0x0177ffff,
899 },
900
901 .tcl_ring_retry = true,
902 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
903 .smp2p_wow_exit = false,
904 .support_fw_mac_sequence = true,
905 .support_dual_stations = true,
906 .pdev_suspend = false,
907 },
908 };
909
910 static const struct dmi_system_id ath11k_pm_quirk_table[] = {
911 {
912 .driver_data = (void *)ATH11K_PM_WOW,
913 .matches = {
914 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
915 DMI_MATCH(DMI_PRODUCT_NAME, "21J4"),
916 },
917 },
918 {
919 .driver_data = (void *)ATH11K_PM_WOW,
920 .matches = {
921 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
922 DMI_MATCH(DMI_PRODUCT_NAME, "21K4"),
923 },
924 },
925 {
926 .driver_data = (void *)ATH11K_PM_WOW,
927 .matches = {
928 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
929 DMI_MATCH(DMI_PRODUCT_NAME, "21K6"),
930 },
931 },
932 {
933 .driver_data = (void *)ATH11K_PM_WOW,
934 .matches = {
935 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
936 DMI_MATCH(DMI_PRODUCT_NAME, "21K8"),
937 },
938 },
939 {
940 .driver_data = (void *)ATH11K_PM_WOW,
941 .matches = {
942 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
943 DMI_MATCH(DMI_PRODUCT_NAME, "21KA"),
944 },
945 },
946 {
947 .driver_data = (void *)ATH11K_PM_WOW,
948 .matches = {
949 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
950 DMI_MATCH(DMI_PRODUCT_NAME, "21F9"),
951 },
952 },
953 {}
954 };
955
ath11k_fw_stats_pdevs_free(struct list_head * head)956 void ath11k_fw_stats_pdevs_free(struct list_head *head)
957 {
958 struct ath11k_fw_stats_pdev *i, *tmp;
959
960 list_for_each_entry_safe(i, tmp, head, list) {
961 list_del(&i->list);
962 kfree(i);
963 }
964 }
965
ath11k_fw_stats_vdevs_free(struct list_head * head)966 void ath11k_fw_stats_vdevs_free(struct list_head *head)
967 {
968 struct ath11k_fw_stats_vdev *i, *tmp;
969
970 list_for_each_entry_safe(i, tmp, head, list) {
971 list_del(&i->list);
972 kfree(i);
973 }
974 }
975
ath11k_fw_stats_bcn_free(struct list_head * head)976 void ath11k_fw_stats_bcn_free(struct list_head *head)
977 {
978 struct ath11k_fw_stats_bcn *i, *tmp;
979
980 list_for_each_entry_safe(i, tmp, head, list) {
981 list_del(&i->list);
982 kfree(i);
983 }
984 }
985
ath11k_fw_stats_init(struct ath11k * ar)986 void ath11k_fw_stats_init(struct ath11k *ar)
987 {
988 INIT_LIST_HEAD(&ar->fw_stats.pdevs);
989 INIT_LIST_HEAD(&ar->fw_stats.vdevs);
990 INIT_LIST_HEAD(&ar->fw_stats.bcn);
991
992 init_completion(&ar->fw_stats_complete);
993 init_completion(&ar->fw_stats_done);
994 }
995
ath11k_fw_stats_free(struct ath11k_fw_stats * stats)996 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats)
997 {
998 ath11k_fw_stats_pdevs_free(&stats->pdevs);
999 ath11k_fw_stats_vdevs_free(&stats->vdevs);
1000 ath11k_fw_stats_bcn_free(&stats->bcn);
1001 }
1002
ath11k_core_coldboot_cal_support(struct ath11k_base * ab)1003 bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab)
1004 {
1005 if (!ath11k_cold_boot_cal)
1006 return false;
1007
1008 if (ath11k_ftm_mode)
1009 return ab->hw_params.coldboot_cal_ftm;
1010
1011 else
1012 return ab->hw_params.coldboot_cal_mm;
1013 }
1014
1015 /* Check if we need to continue with suspend/resume operation.
1016 * Return:
1017 * a negative value: error happens and don't continue.
1018 * 0: no error but don't continue.
1019 * positive value: no error and do continue.
1020 */
ath11k_core_continue_suspend_resume(struct ath11k_base * ab)1021 static int ath11k_core_continue_suspend_resume(struct ath11k_base *ab)
1022 {
1023 struct ath11k *ar;
1024
1025 if (!ab->hw_params.supports_suspend)
1026 return -EOPNOTSUPP;
1027
1028 /* so far single_pdev_only chips have supports_suspend as true
1029 * so pass 0 as a dummy pdev_id here.
1030 */
1031 ar = ab->pdevs[0].ar;
1032 if (!ar || ar->state != ATH11K_STATE_OFF)
1033 return 0;
1034
1035 return 1;
1036 }
1037
ath11k_core_suspend_wow(struct ath11k_base * ab)1038 static int ath11k_core_suspend_wow(struct ath11k_base *ab)
1039 {
1040 int ret;
1041
1042 ret = ath11k_dp_rx_pktlog_stop(ab, true);
1043 if (ret) {
1044 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n",
1045 ret);
1046 return ret;
1047 }
1048
1049 /* So far only single_pdev_only devices can reach here,
1050 * so it is valid to handle the first, and the only, pdev.
1051 */
1052 ret = ath11k_mac_wait_tx_complete(ab->pdevs[0].ar);
1053 if (ret) {
1054 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret);
1055 return ret;
1056 }
1057
1058 ret = ath11k_wow_enable(ab);
1059 if (ret) {
1060 ath11k_warn(ab, "failed to enable wow during suspend: %d\n", ret);
1061 return ret;
1062 }
1063
1064 ret = ath11k_dp_rx_pktlog_stop(ab, false);
1065 if (ret) {
1066 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n",
1067 ret);
1068 return ret;
1069 }
1070
1071 ath11k_ce_stop_shadow_timers(ab);
1072 ath11k_dp_stop_shadow_timers(ab);
1073
1074 ath11k_hif_irq_disable(ab);
1075 ath11k_hif_ce_irq_disable(ab);
1076
1077 ret = ath11k_hif_suspend(ab);
1078 if (ret) {
1079 ath11k_warn(ab, "failed to suspend hif: %d\n", ret);
1080 return ret;
1081 }
1082
1083 return 0;
1084 }
1085
ath11k_core_suspend_default(struct ath11k_base * ab)1086 static int ath11k_core_suspend_default(struct ath11k_base *ab)
1087 {
1088 int ret;
1089
1090 ret = ath11k_dp_rx_pktlog_stop(ab, true);
1091 if (ret) {
1092 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n",
1093 ret);
1094 return ret;
1095 }
1096
1097 /* So far only single_pdev_only devices can reach here,
1098 * so it is valid to handle the first, and the only, pdev.
1099 */
1100 ret = ath11k_mac_wait_tx_complete(ab->pdevs[0].ar);
1101 if (ret) {
1102 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret);
1103 return ret;
1104 }
1105
1106 ret = ath11k_dp_rx_pktlog_stop(ab, false);
1107 if (ret) {
1108 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n",
1109 ret);
1110 return ret;
1111 }
1112
1113 ath11k_ce_stop_shadow_timers(ab);
1114 ath11k_dp_stop_shadow_timers(ab);
1115
1116 /* PM framework skips suspend_late/resume_early callbacks
1117 * if other devices report errors in their suspend callbacks.
1118 * However ath11k_core_resume() would still be called because
1119 * here we return success thus kernel put us on dpm_suspended_list.
1120 * Since we won't go through a power down/up cycle, there is
1121 * no chance to call complete(&ab->restart_completed) in
1122 * ath11k_core_restart(), making ath11k_core_resume() timeout.
1123 * So call it here to avoid this issue. This also works in case
1124 * no error happens thus suspend_late/resume_early get called,
1125 * because it will be reinitialized in ath11k_core_resume_early().
1126 */
1127 complete(&ab->restart_completed);
1128
1129 return 0;
1130 }
1131
ath11k_core_suspend(struct ath11k_base * ab)1132 int ath11k_core_suspend(struct ath11k_base *ab)
1133 {
1134 int ret;
1135
1136 ret = ath11k_core_continue_suspend_resume(ab);
1137 if (ret <= 0)
1138 return ret;
1139
1140 if (ab->actual_pm_policy == ATH11K_PM_WOW)
1141 return ath11k_core_suspend_wow(ab);
1142
1143 return ath11k_core_suspend_default(ab);
1144 }
1145 EXPORT_SYMBOL(ath11k_core_suspend);
1146
ath11k_core_suspend_late(struct ath11k_base * ab)1147 int ath11k_core_suspend_late(struct ath11k_base *ab)
1148 {
1149 int ret;
1150
1151 ret = ath11k_core_continue_suspend_resume(ab);
1152 if (ret <= 0)
1153 return ret;
1154
1155 if (ab->actual_pm_policy == ATH11K_PM_WOW)
1156 return 0;
1157
1158 ath11k_hif_irq_disable(ab);
1159 ath11k_hif_ce_irq_disable(ab);
1160
1161 ath11k_hif_power_down(ab, true);
1162
1163 return 0;
1164 }
1165 EXPORT_SYMBOL(ath11k_core_suspend_late);
1166
ath11k_core_resume_early(struct ath11k_base * ab)1167 int ath11k_core_resume_early(struct ath11k_base *ab)
1168 {
1169 int ret;
1170
1171 ret = ath11k_core_continue_suspend_resume(ab);
1172 if (ret <= 0)
1173 return ret;
1174
1175 if (ab->actual_pm_policy == ATH11K_PM_WOW)
1176 return 0;
1177
1178 reinit_completion(&ab->restart_completed);
1179 ret = ath11k_hif_power_up(ab);
1180 if (ret)
1181 ath11k_warn(ab, "failed to power up hif during resume: %d\n", ret);
1182
1183 return ret;
1184 }
1185 EXPORT_SYMBOL(ath11k_core_resume_early);
1186
ath11k_core_resume_default(struct ath11k_base * ab)1187 static int ath11k_core_resume_default(struct ath11k_base *ab)
1188 {
1189 struct ath11k *ar;
1190 long time_left;
1191 int ret;
1192
1193 time_left = wait_for_completion_timeout(&ab->restart_completed,
1194 ATH11K_RESET_TIMEOUT_HZ);
1195 if (time_left == 0) {
1196 ath11k_warn(ab, "timeout while waiting for restart complete");
1197 return -ETIMEDOUT;
1198 }
1199
1200 /* So far only single_pdev_only devices can reach here,
1201 * so it is valid to handle the first, and the only, pdev.
1202 */
1203 ar = ab->pdevs[0].ar;
1204 if (ab->hw_params.current_cc_support &&
1205 ar->alpha2[0] != 0 && ar->alpha2[1] != 0) {
1206 ret = ath11k_reg_set_cc(ar);
1207 if (ret) {
1208 ath11k_warn(ab, "failed to set country code during resume: %d\n",
1209 ret);
1210 return ret;
1211 }
1212 }
1213
1214 ret = ath11k_dp_rx_pktlog_start(ab);
1215 if (ret)
1216 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n",
1217 ret);
1218
1219 return ret;
1220 }
1221
ath11k_core_resume_wow(struct ath11k_base * ab)1222 static int ath11k_core_resume_wow(struct ath11k_base *ab)
1223 {
1224 int ret;
1225
1226 ret = ath11k_hif_resume(ab);
1227 if (ret) {
1228 ath11k_warn(ab, "failed to resume hif during resume: %d\n", ret);
1229 return ret;
1230 }
1231
1232 ath11k_hif_ce_irq_enable(ab);
1233 ath11k_hif_irq_enable(ab);
1234
1235 ret = ath11k_dp_rx_pktlog_start(ab);
1236 if (ret) {
1237 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n",
1238 ret);
1239 return ret;
1240 }
1241
1242 ret = ath11k_wow_wakeup(ab);
1243 if (ret) {
1244 ath11k_warn(ab, "failed to wakeup wow during resume: %d\n", ret);
1245 return ret;
1246 }
1247
1248 return 0;
1249 }
1250
ath11k_core_resume(struct ath11k_base * ab)1251 int ath11k_core_resume(struct ath11k_base *ab)
1252 {
1253 int ret;
1254
1255 ret = ath11k_core_continue_suspend_resume(ab);
1256 if (ret <= 0)
1257 return ret;
1258
1259 if (ab->actual_pm_policy == ATH11K_PM_WOW)
1260 return ath11k_core_resume_wow(ab);
1261
1262 return ath11k_core_resume_default(ab);
1263 }
1264 EXPORT_SYMBOL(ath11k_core_resume);
1265
ath11k_core_check_cc_code_bdfext(const struct dmi_header * hdr,void * data)1266 static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data)
1267 {
1268 struct ath11k_base *ab = data;
1269 const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC;
1270 struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr;
1271 ssize_t copied;
1272 size_t len;
1273 int i;
1274
1275 if (ab->qmi.target.bdf_ext[0] != '\0')
1276 return;
1277
1278 if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE)
1279 return;
1280
1281 if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) {
1282 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1283 "wrong smbios bdf ext type length (%d).\n",
1284 hdr->length);
1285 return;
1286 }
1287
1288 spin_lock_bh(&ab->base_lock);
1289
1290 switch (smbios->country_code_flag) {
1291 case ATH11K_SMBIOS_CC_ISO:
1292 ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff;
1293 ab->new_alpha2[1] = smbios->cc_code & 0xff;
1294 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios cc_code %c%c\n",
1295 ab->new_alpha2[0], ab->new_alpha2[1]);
1296 break;
1297 case ATH11K_SMBIOS_CC_WW:
1298 ab->new_alpha2[0] = '0';
1299 ab->new_alpha2[1] = '0';
1300 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios worldwide regdomain\n");
1301 break;
1302 default:
1303 ath11k_dbg(ab, ATH11K_DBG_BOOT, "ignore smbios country code setting %d\n",
1304 smbios->country_code_flag);
1305 break;
1306 }
1307
1308 spin_unlock_bh(&ab->base_lock);
1309
1310 if (!smbios->bdf_enabled) {
1311 ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n");
1312 return;
1313 }
1314
1315 /* Only one string exists (per spec) */
1316 if (memcmp(smbios->bdf_ext, magic, strlen(magic)) != 0) {
1317 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1318 "bdf variant magic does not match.\n");
1319 return;
1320 }
1321
1322 len = min_t(size_t,
1323 strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext));
1324 for (i = 0; i < len; i++) {
1325 if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) {
1326 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1327 "bdf variant name contains non ascii chars.\n");
1328 return;
1329 }
1330 }
1331
1332 /* Copy extension name without magic prefix */
1333 copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic),
1334 sizeof(ab->qmi.target.bdf_ext));
1335 if (copied < 0) {
1336 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1337 "bdf variant string is longer than the buffer can accommodate\n");
1338 return;
1339 }
1340
1341 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1342 "found and validated bdf variant smbios_type 0x%x bdf %s\n",
1343 ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext);
1344 }
1345
ath11k_core_check_smbios(struct ath11k_base * ab)1346 int ath11k_core_check_smbios(struct ath11k_base *ab)
1347 {
1348 ab->qmi.target.bdf_ext[0] = '\0';
1349 dmi_walk(ath11k_core_check_cc_code_bdfext, ab);
1350
1351 if (ab->qmi.target.bdf_ext[0] == '\0')
1352 return -ENODATA;
1353
1354 return 0;
1355 }
1356
ath11k_core_check_dt(struct ath11k_base * ab)1357 int ath11k_core_check_dt(struct ath11k_base *ab)
1358 {
1359 size_t max_len = sizeof(ab->qmi.target.bdf_ext);
1360 const char *variant = NULL;
1361 struct device_node *node;
1362
1363 node = ab->dev->of_node;
1364 if (!node)
1365 return -ENOENT;
1366
1367 of_property_read_string(node, "qcom,calibration-variant",
1368 &variant);
1369 if (!variant)
1370 of_property_read_string(node, "qcom,ath11k-calibration-variant",
1371 &variant);
1372 if (!variant)
1373 return -ENODATA;
1374
1375 if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0)
1376 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1377 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
1378 variant);
1379
1380 return 0;
1381 }
1382
1383 enum ath11k_bdf_name_type {
1384 ATH11K_BDF_NAME_FULL,
1385 ATH11K_BDF_NAME_BUS_NAME,
1386 ATH11K_BDF_NAME_CHIP_ID,
1387 };
1388
__ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len,bool with_variant,enum ath11k_bdf_name_type name_type)1389 static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
1390 size_t name_len, bool with_variant,
1391 enum ath11k_bdf_name_type name_type)
1392 {
1393 /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */
1394 char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 };
1395
1396 if (with_variant && ab->qmi.target.bdf_ext[0] != '\0')
1397 scnprintf(variant, sizeof(variant), ",variant=%s",
1398 ab->qmi.target.bdf_ext);
1399
1400 switch (ab->id.bdf_search) {
1401 case ATH11K_BDF_SEARCH_BUS_AND_BOARD:
1402 switch (name_type) {
1403 case ATH11K_BDF_NAME_FULL:
1404 scnprintf(name, name_len,
1405 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s",
1406 ath11k_bus_str(ab->hif.bus),
1407 ab->id.vendor, ab->id.device,
1408 ab->id.subsystem_vendor,
1409 ab->id.subsystem_device,
1410 ab->qmi.target.chip_id,
1411 ab->qmi.target.board_id,
1412 variant);
1413 break;
1414 case ATH11K_BDF_NAME_BUS_NAME:
1415 scnprintf(name, name_len,
1416 "bus=%s",
1417 ath11k_bus_str(ab->hif.bus));
1418 break;
1419 case ATH11K_BDF_NAME_CHIP_ID:
1420 scnprintf(name, name_len,
1421 "bus=%s,qmi-chip-id=%d",
1422 ath11k_bus_str(ab->hif.bus),
1423 ab->qmi.target.chip_id);
1424 break;
1425 }
1426 break;
1427 default:
1428 scnprintf(name, name_len,
1429 "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s",
1430 ath11k_bus_str(ab->hif.bus),
1431 ab->qmi.target.chip_id,
1432 ab->qmi.target.board_id, variant);
1433 break;
1434 }
1435
1436 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board name '%s'\n", name);
1437
1438 return 0;
1439 }
1440
ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len)1441 static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
1442 size_t name_len)
1443 {
1444 return __ath11k_core_create_board_name(ab, name, name_len, true,
1445 ATH11K_BDF_NAME_FULL);
1446 }
1447
ath11k_core_create_fallback_board_name(struct ath11k_base * ab,char * name,size_t name_len)1448 static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name,
1449 size_t name_len)
1450 {
1451 return __ath11k_core_create_board_name(ab, name, name_len, false,
1452 ATH11K_BDF_NAME_FULL);
1453 }
1454
ath11k_core_create_bus_type_board_name(struct ath11k_base * ab,char * name,size_t name_len)1455 static int ath11k_core_create_bus_type_board_name(struct ath11k_base *ab, char *name,
1456 size_t name_len)
1457 {
1458 return __ath11k_core_create_board_name(ab, name, name_len, false,
1459 ATH11K_BDF_NAME_BUS_NAME);
1460 }
1461
ath11k_core_create_chip_id_board_name(struct ath11k_base * ab,char * name,size_t name_len)1462 static int ath11k_core_create_chip_id_board_name(struct ath11k_base *ab, char *name,
1463 size_t name_len)
1464 {
1465 return __ath11k_core_create_board_name(ab, name, name_len, false,
1466 ATH11K_BDF_NAME_CHIP_ID);
1467 }
1468
ath11k_core_firmware_request(struct ath11k_base * ab,const char * file)1469 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab,
1470 const char *file)
1471 {
1472 const struct firmware *fw;
1473 char path[100];
1474 int ret;
1475
1476 if (file == NULL)
1477 return ERR_PTR(-ENOENT);
1478
1479 ath11k_core_create_firmware_path(ab, file, path, sizeof(path));
1480
1481 ret = firmware_request_nowarn(&fw, path, ab->dev);
1482 if (ret)
1483 return ERR_PTR(ret);
1484
1485 ath11k_dbg(ab, ATH11K_DBG_BOOT, "firmware request %s size %zu\n",
1486 path, fw->size);
1487
1488 return fw;
1489 }
1490
ath11k_core_free_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)1491 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1492 {
1493 if (!IS_ERR(bd->fw))
1494 release_firmware(bd->fw);
1495
1496 memset(bd, 0, sizeof(*bd));
1497 }
1498
ath11k_core_parse_bd_ie_board(struct ath11k_base * ab,struct ath11k_board_data * bd,const void * buf,size_t buf_len,const char * boardname,int ie_id,int name_id,int data_id)1499 static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab,
1500 struct ath11k_board_data *bd,
1501 const void *buf, size_t buf_len,
1502 const char *boardname,
1503 int ie_id,
1504 int name_id,
1505 int data_id)
1506 {
1507 const struct ath11k_fw_ie *hdr;
1508 bool name_match_found;
1509 int ret, board_ie_id;
1510 size_t board_ie_len;
1511 const void *board_ie_data;
1512
1513 name_match_found = false;
1514
1515 /* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */
1516 while (buf_len > sizeof(struct ath11k_fw_ie)) {
1517 hdr = buf;
1518 board_ie_id = le32_to_cpu(hdr->id);
1519 board_ie_len = le32_to_cpu(hdr->len);
1520 board_ie_data = hdr->data;
1521
1522 buf_len -= sizeof(*hdr);
1523 buf += sizeof(*hdr);
1524
1525 if (buf_len < ALIGN(board_ie_len, 4)) {
1526 ath11k_err(ab, "invalid %s length: %zu < %zu\n",
1527 ath11k_bd_ie_type_str(ie_id),
1528 buf_len, ALIGN(board_ie_len, 4));
1529 ret = -EINVAL;
1530 goto out;
1531 }
1532
1533 if (board_ie_id == name_id) {
1534 ath11k_dbg_dump(ab, ATH11K_DBG_BOOT, "board name", "",
1535 board_ie_data, board_ie_len);
1536
1537 if (board_ie_len != strlen(boardname))
1538 goto next;
1539
1540 ret = memcmp(board_ie_data, boardname, strlen(boardname));
1541 if (ret)
1542 goto next;
1543
1544 name_match_found = true;
1545 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1546 "found match %s for name '%s'",
1547 ath11k_bd_ie_type_str(ie_id),
1548 boardname);
1549 } else if (board_ie_id == data_id) {
1550 if (!name_match_found)
1551 /* no match found */
1552 goto next;
1553
1554 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1555 "found %s for '%s'",
1556 ath11k_bd_ie_type_str(ie_id),
1557 boardname);
1558
1559 bd->data = board_ie_data;
1560 bd->len = board_ie_len;
1561
1562 ret = 0;
1563 goto out;
1564 } else {
1565 ath11k_warn(ab, "unknown %s id found: %d\n",
1566 ath11k_bd_ie_type_str(ie_id),
1567 board_ie_id);
1568 }
1569 next:
1570 /* jump over the padding */
1571 board_ie_len = ALIGN(board_ie_len, 4);
1572
1573 buf_len -= board_ie_len;
1574 buf += board_ie_len;
1575 }
1576
1577 /* no match found */
1578 ret = -ENOENT;
1579
1580 out:
1581 return ret;
1582 }
1583
ath11k_core_fetch_board_data_api_n(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * boardname,int ie_id_match,int name_id,int data_id)1584 static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab,
1585 struct ath11k_board_data *bd,
1586 const char *boardname,
1587 int ie_id_match,
1588 int name_id,
1589 int data_id)
1590 {
1591 size_t len, magic_len;
1592 const u8 *data;
1593 char *filename, filepath[100];
1594 size_t ie_len;
1595 struct ath11k_fw_ie *hdr;
1596 int ret, ie_id;
1597
1598 filename = ATH11K_BOARD_API2_FILE;
1599
1600 if (!bd->fw)
1601 bd->fw = ath11k_core_firmware_request(ab, filename);
1602
1603 if (IS_ERR(bd->fw))
1604 return PTR_ERR(bd->fw);
1605
1606 data = bd->fw->data;
1607 len = bd->fw->size;
1608
1609 ath11k_core_create_firmware_path(ab, filename,
1610 filepath, sizeof(filepath));
1611
1612 /* magic has extra null byte padded */
1613 magic_len = strlen(ATH11K_BOARD_MAGIC) + 1;
1614 if (len < magic_len) {
1615 ath11k_err(ab, "failed to find magic value in %s, file too short: %zu\n",
1616 filepath, len);
1617 ret = -EINVAL;
1618 goto err;
1619 }
1620
1621 if (memcmp(data, ATH11K_BOARD_MAGIC, magic_len)) {
1622 ath11k_err(ab, "found invalid board magic\n");
1623 ret = -EINVAL;
1624 goto err;
1625 }
1626
1627 /* magic is padded to 4 bytes */
1628 magic_len = ALIGN(magic_len, 4);
1629 if (len < magic_len) {
1630 ath11k_err(ab, "failed: %s too small to contain board data, len: %zu\n",
1631 filepath, len);
1632 ret = -EINVAL;
1633 goto err;
1634 }
1635
1636 data += magic_len;
1637 len -= magic_len;
1638
1639 while (len > sizeof(struct ath11k_fw_ie)) {
1640 hdr = (struct ath11k_fw_ie *)data;
1641 ie_id = le32_to_cpu(hdr->id);
1642 ie_len = le32_to_cpu(hdr->len);
1643
1644 len -= sizeof(*hdr);
1645 data = hdr->data;
1646
1647 if (len < ALIGN(ie_len, 4)) {
1648 ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n",
1649 ie_id, ie_len, len);
1650 ret = -EINVAL;
1651 goto err;
1652 }
1653
1654 if (ie_id == ie_id_match) {
1655 ret = ath11k_core_parse_bd_ie_board(ab, bd, data,
1656 ie_len,
1657 boardname,
1658 ie_id_match,
1659 name_id,
1660 data_id);
1661 if (ret == -ENOENT)
1662 /* no match found, continue */
1663 goto next;
1664 else if (ret)
1665 /* there was an error, bail out */
1666 goto err;
1667 /* either found or error, so stop searching */
1668 goto out;
1669 }
1670 next:
1671 /* jump over the padding */
1672 ie_len = ALIGN(ie_len, 4);
1673
1674 len -= ie_len;
1675 data += ie_len;
1676 }
1677
1678 out:
1679 if (!bd->data || !bd->len) {
1680 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1681 "failed to fetch %s for %s from %s\n",
1682 ath11k_bd_ie_type_str(ie_id_match),
1683 boardname, filepath);
1684 ret = -ENODATA;
1685 goto err;
1686 }
1687
1688 return 0;
1689
1690 err:
1691 ath11k_core_free_bdf(ab, bd);
1692 return ret;
1693 }
1694
ath11k_core_fetch_board_data_api_1(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * name)1695 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab,
1696 struct ath11k_board_data *bd,
1697 const char *name)
1698 {
1699 bd->fw = ath11k_core_firmware_request(ab, name);
1700
1701 if (IS_ERR(bd->fw))
1702 return PTR_ERR(bd->fw);
1703
1704 bd->data = bd->fw->data;
1705 bd->len = bd->fw->size;
1706
1707 return 0;
1708 }
1709
1710 #define BOARD_NAME_SIZE 200
ath11k_core_fetch_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)1711 int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1712 {
1713 char *boardname = NULL, *fallback_boardname = NULL, *chip_id_boardname = NULL;
1714 char *filename, filepath[100];
1715 int bd_api;
1716 int ret = 0;
1717
1718 filename = ATH11K_BOARD_API2_FILE;
1719 boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL);
1720 if (!boardname) {
1721 ret = -ENOMEM;
1722 goto exit;
1723 }
1724
1725 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE);
1726 if (ret) {
1727 ath11k_err(ab, "failed to create board name: %d", ret);
1728 goto exit;
1729 }
1730
1731 bd_api = 2;
1732 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1733 ATH11K_BD_IE_BOARD,
1734 ATH11K_BD_IE_BOARD_NAME,
1735 ATH11K_BD_IE_BOARD_DATA);
1736 if (!ret)
1737 goto exit;
1738
1739 fallback_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL);
1740 if (!fallback_boardname) {
1741 ret = -ENOMEM;
1742 goto exit;
1743 }
1744
1745 ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname,
1746 BOARD_NAME_SIZE);
1747 if (ret) {
1748 ath11k_err(ab, "failed to create fallback board name: %d", ret);
1749 goto exit;
1750 }
1751
1752 ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname,
1753 ATH11K_BD_IE_BOARD,
1754 ATH11K_BD_IE_BOARD_NAME,
1755 ATH11K_BD_IE_BOARD_DATA);
1756 if (!ret)
1757 goto exit;
1758
1759 chip_id_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL);
1760 if (!chip_id_boardname) {
1761 ret = -ENOMEM;
1762 goto exit;
1763 }
1764
1765 ret = ath11k_core_create_chip_id_board_name(ab, chip_id_boardname,
1766 BOARD_NAME_SIZE);
1767 if (ret) {
1768 ath11k_err(ab, "failed to create chip id board name: %d", ret);
1769 goto exit;
1770 }
1771
1772 ret = ath11k_core_fetch_board_data_api_n(ab, bd, chip_id_boardname,
1773 ATH11K_BD_IE_BOARD,
1774 ATH11K_BD_IE_BOARD_NAME,
1775 ATH11K_BD_IE_BOARD_DATA);
1776
1777 if (!ret)
1778 goto exit;
1779
1780 bd_api = 1;
1781 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE);
1782 if (ret) {
1783 ath11k_core_create_firmware_path(ab, filename,
1784 filepath, sizeof(filepath));
1785 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1786 boardname, filepath);
1787 if (memcmp(boardname, fallback_boardname, strlen(boardname)))
1788 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1789 fallback_boardname, filepath);
1790
1791 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1792 chip_id_boardname, filepath);
1793
1794 ath11k_err(ab, "failed to fetch board.bin from %s\n",
1795 ab->hw_params.fw.dir);
1796 }
1797
1798 exit:
1799 kfree(boardname);
1800 kfree(fallback_boardname);
1801 kfree(chip_id_boardname);
1802
1803 if (!ret)
1804 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", bd_api);
1805
1806 return ret;
1807 }
1808
ath11k_core_fetch_regdb(struct ath11k_base * ab,struct ath11k_board_data * bd)1809 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd)
1810 {
1811 char boardname[BOARD_NAME_SIZE], default_boardname[BOARD_NAME_SIZE];
1812 int ret;
1813
1814 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE);
1815 if (ret) {
1816 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1817 "failed to create board name for regdb: %d", ret);
1818 goto exit;
1819 }
1820
1821 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1822 ATH11K_BD_IE_REGDB,
1823 ATH11K_BD_IE_REGDB_NAME,
1824 ATH11K_BD_IE_REGDB_DATA);
1825 if (!ret)
1826 goto exit;
1827
1828 ret = ath11k_core_create_bus_type_board_name(ab, default_boardname,
1829 BOARD_NAME_SIZE);
1830 if (ret) {
1831 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1832 "failed to create default board name for regdb: %d", ret);
1833 goto exit;
1834 }
1835
1836 ret = ath11k_core_fetch_board_data_api_n(ab, bd, default_boardname,
1837 ATH11K_BD_IE_REGDB,
1838 ATH11K_BD_IE_REGDB_NAME,
1839 ATH11K_BD_IE_REGDB_DATA);
1840 if (!ret)
1841 goto exit;
1842
1843 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME);
1844 if (ret)
1845 ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n",
1846 ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir);
1847
1848 exit:
1849 if (!ret)
1850 ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n");
1851
1852 return ret;
1853 }
1854
ath11k_core_stop(struct ath11k_base * ab)1855 static void ath11k_core_stop(struct ath11k_base *ab)
1856 {
1857 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
1858 ath11k_qmi_firmware_stop(ab);
1859
1860 ath11k_hif_stop(ab);
1861 ath11k_wmi_detach(ab);
1862 ath11k_dp_pdev_reo_cleanup(ab);
1863
1864 /* De-Init of components as needed */
1865 }
1866
ath11k_core_soc_create(struct ath11k_base * ab)1867 static int ath11k_core_soc_create(struct ath11k_base *ab)
1868 {
1869 int ret;
1870
1871 if (ath11k_ftm_mode) {
1872 ab->fw_mode = ATH11K_FIRMWARE_MODE_FTM;
1873 ath11k_info(ab, "Booting in factory test mode\n");
1874 }
1875
1876 ret = ath11k_qmi_init_service(ab);
1877 if (ret) {
1878 ath11k_err(ab, "failed to initialize qmi :%d\n", ret);
1879 return ret;
1880 }
1881
1882 ret = ath11k_debugfs_soc_create(ab);
1883 if (ret) {
1884 ath11k_err(ab, "failed to create ath11k debugfs\n");
1885 goto err_qmi_deinit;
1886 }
1887
1888 ret = ath11k_hif_power_up(ab);
1889 if (ret) {
1890 ath11k_err(ab, "failed to power up :%d\n", ret);
1891 goto err_debugfs_reg;
1892 }
1893
1894 return 0;
1895
1896 err_debugfs_reg:
1897 ath11k_debugfs_soc_destroy(ab);
1898 err_qmi_deinit:
1899 ath11k_qmi_deinit_service(ab);
1900 return ret;
1901 }
1902
ath11k_core_soc_destroy(struct ath11k_base * ab)1903 static void ath11k_core_soc_destroy(struct ath11k_base *ab)
1904 {
1905 ath11k_debugfs_soc_destroy(ab);
1906 ath11k_dp_free(ab);
1907 ath11k_reg_free(ab);
1908 ath11k_qmi_deinit_service(ab);
1909 }
1910
ath11k_core_pdev_create(struct ath11k_base * ab)1911 static int ath11k_core_pdev_create(struct ath11k_base *ab)
1912 {
1913 int ret;
1914
1915 ret = ath11k_debugfs_pdev_create(ab);
1916 if (ret) {
1917 ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret);
1918 return ret;
1919 }
1920
1921 ret = ath11k_dp_pdev_alloc(ab);
1922 if (ret) {
1923 ath11k_err(ab, "failed to attach DP pdev: %d\n", ret);
1924 goto err_pdev_debug;
1925 }
1926
1927 ret = ath11k_mac_register(ab);
1928 if (ret) {
1929 ath11k_err(ab, "failed register the radio with mac80211: %d\n", ret);
1930 goto err_dp_pdev_free;
1931 }
1932
1933 ret = ath11k_thermal_register(ab);
1934 if (ret) {
1935 ath11k_err(ab, "could not register thermal device: %d\n",
1936 ret);
1937 goto err_mac_unregister;
1938 }
1939
1940 ret = ath11k_spectral_init(ab);
1941 if (ret) {
1942 ath11k_err(ab, "failed to init spectral %d\n", ret);
1943 goto err_thermal_unregister;
1944 }
1945
1946 return 0;
1947
1948 err_thermal_unregister:
1949 ath11k_thermal_unregister(ab);
1950 err_mac_unregister:
1951 ath11k_mac_unregister(ab);
1952 err_dp_pdev_free:
1953 ath11k_dp_pdev_free(ab);
1954 err_pdev_debug:
1955 ath11k_debugfs_pdev_destroy(ab);
1956
1957 return ret;
1958 }
1959
ath11k_core_pdev_suspend_target(struct ath11k_base * ab)1960 static void ath11k_core_pdev_suspend_target(struct ath11k_base *ab)
1961 {
1962 struct ath11k *ar;
1963 struct ath11k_pdev *pdev;
1964 unsigned long time_left;
1965 int ret;
1966 int i;
1967
1968 if (!ab->hw_params.pdev_suspend)
1969 return;
1970
1971 for (i = 0; i < ab->num_radios; i++) {
1972 pdev = &ab->pdevs[i];
1973 ar = pdev->ar;
1974
1975 reinit_completion(&ab->htc_suspend);
1976
1977 ret = ath11k_wmi_pdev_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR,
1978 pdev->pdev_id);
1979 if (ret) {
1980 ath11k_warn(ab, "could not suspend target :%d\n", ret);
1981 /* pointless to try other pdevs */
1982 return;
1983 }
1984
1985 time_left = wait_for_completion_timeout(&ab->htc_suspend, 3 * HZ);
1986
1987 if (!time_left) {
1988 ath11k_warn(ab, "suspend timed out - target pause event never came\n");
1989 /* pointless to try other pdevs */
1990 return;
1991 }
1992 }
1993 }
1994
ath11k_core_pdev_destroy(struct ath11k_base * ab)1995 static void ath11k_core_pdev_destroy(struct ath11k_base *ab)
1996 {
1997 ath11k_spectral_deinit(ab);
1998 ath11k_thermal_unregister(ab);
1999 ath11k_mac_unregister(ab);
2000 ath11k_core_pdev_suspend_target(ab);
2001 ath11k_hif_irq_disable(ab);
2002 ath11k_dp_pdev_free(ab);
2003 ath11k_debugfs_pdev_destroy(ab);
2004 }
2005
ath11k_core_start(struct ath11k_base * ab)2006 static int ath11k_core_start(struct ath11k_base *ab)
2007 {
2008 int ret;
2009
2010 ret = ath11k_wmi_attach(ab);
2011 if (ret) {
2012 ath11k_err(ab, "failed to attach wmi: %d\n", ret);
2013 return ret;
2014 }
2015
2016 ret = ath11k_htc_init(ab);
2017 if (ret) {
2018 ath11k_err(ab, "failed to init htc: %d\n", ret);
2019 goto err_wmi_detach;
2020 }
2021
2022 ret = ath11k_hif_start(ab);
2023 if (ret) {
2024 ath11k_err(ab, "failed to start HIF: %d\n", ret);
2025 goto err_wmi_detach;
2026 }
2027
2028 ret = ath11k_htc_wait_target(&ab->htc);
2029 if (ret) {
2030 ath11k_err(ab, "failed to connect to HTC: %d\n", ret);
2031 goto err_hif_stop;
2032 }
2033
2034 ret = ath11k_dp_htt_connect(&ab->dp);
2035 if (ret) {
2036 ath11k_err(ab, "failed to connect to HTT: %d\n", ret);
2037 goto err_hif_stop;
2038 }
2039
2040 ret = ath11k_wmi_connect(ab);
2041 if (ret) {
2042 ath11k_err(ab, "failed to connect wmi: %d\n", ret);
2043 goto err_hif_stop;
2044 }
2045
2046 ret = ath11k_htc_start(&ab->htc);
2047 if (ret) {
2048 ath11k_err(ab, "failed to start HTC: %d\n", ret);
2049 goto err_hif_stop;
2050 }
2051
2052 ret = ath11k_wmi_wait_for_service_ready(ab);
2053 if (ret) {
2054 ath11k_err(ab, "failed to receive wmi service ready event: %d\n",
2055 ret);
2056 goto err_hif_stop;
2057 }
2058
2059 ret = ath11k_mac_allocate(ab);
2060 if (ret) {
2061 ath11k_err(ab, "failed to create new hw device with mac80211 :%d\n",
2062 ret);
2063 goto err_hif_stop;
2064 }
2065
2066 ath11k_dp_pdev_pre_alloc(ab);
2067
2068 ret = ath11k_dp_pdev_reo_setup(ab);
2069 if (ret) {
2070 ath11k_err(ab, "failed to initialize reo destination rings: %d\n", ret);
2071 goto err_mac_destroy;
2072 }
2073
2074 ret = ath11k_wmi_cmd_init(ab);
2075 if (ret) {
2076 ath11k_err(ab, "failed to send wmi init cmd: %d\n", ret);
2077 goto err_reo_cleanup;
2078 }
2079
2080 ret = ath11k_wmi_wait_for_unified_ready(ab);
2081 if (ret) {
2082 ath11k_err(ab, "failed to receive wmi unified ready event: %d\n",
2083 ret);
2084 goto err_reo_cleanup;
2085 }
2086
2087 /* put hardware to DBS mode */
2088 if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxdma_per_pdev > 1) {
2089 ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS);
2090 if (ret) {
2091 ath11k_err(ab, "failed to send dbs mode: %d\n", ret);
2092 goto err_hif_stop;
2093 }
2094 }
2095
2096 ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab);
2097 if (ret) {
2098 ath11k_err(ab, "failed to send htt version request message: %d\n",
2099 ret);
2100 goto err_reo_cleanup;
2101 }
2102
2103 return 0;
2104
2105 err_reo_cleanup:
2106 ath11k_dp_pdev_reo_cleanup(ab);
2107 err_mac_destroy:
2108 ath11k_mac_destroy(ab);
2109 err_hif_stop:
2110 ath11k_hif_stop(ab);
2111 err_wmi_detach:
2112 ath11k_wmi_detach(ab);
2113
2114 return ret;
2115 }
2116
ath11k_core_start_firmware(struct ath11k_base * ab,enum ath11k_firmware_mode mode)2117 static int ath11k_core_start_firmware(struct ath11k_base *ab,
2118 enum ath11k_firmware_mode mode)
2119 {
2120 int ret;
2121
2122 ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2,
2123 &ab->qmi.ce_cfg.shadow_reg_v2_len);
2124
2125 ret = ath11k_qmi_firmware_start(ab, mode);
2126 if (ret) {
2127 ath11k_err(ab, "failed to send firmware start: %d\n", ret);
2128 return ret;
2129 }
2130
2131 return ret;
2132 }
2133
ath11k_core_qmi_firmware_ready(struct ath11k_base * ab)2134 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab)
2135 {
2136 int ret;
2137
2138 switch (ath11k_crypto_mode) {
2139 case ATH11K_CRYPT_MODE_SW:
2140 set_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
2141 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
2142 break;
2143 case ATH11K_CRYPT_MODE_HW:
2144 clear_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
2145 clear_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
2146 break;
2147 default:
2148 ath11k_info(ab, "invalid crypto_mode: %d\n", ath11k_crypto_mode);
2149 return -EINVAL;
2150 }
2151
2152 ret = ath11k_core_start_firmware(ab, ab->fw_mode);
2153 if (ret) {
2154 ath11k_err(ab, "failed to start firmware: %d\n", ret);
2155 return ret;
2156 }
2157
2158 ret = ath11k_ce_init_pipes(ab);
2159 if (ret) {
2160 ath11k_err(ab, "failed to initialize CE: %d\n", ret);
2161 goto err_firmware_stop;
2162 }
2163
2164 ret = ath11k_dp_alloc(ab);
2165 if (ret) {
2166 ath11k_err(ab, "failed to init DP: %d\n", ret);
2167 goto err_firmware_stop;
2168 }
2169
2170 if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW)
2171 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
2172
2173 mutex_lock(&ab->core_lock);
2174 ret = ath11k_core_start(ab);
2175 if (ret) {
2176 ath11k_err(ab, "failed to start core: %d\n", ret);
2177 goto err_dp_free;
2178 }
2179
2180 ret = ath11k_core_pdev_create(ab);
2181 if (ret) {
2182 ath11k_err(ab, "failed to create pdev core: %d\n", ret);
2183 goto err_core_stop;
2184 }
2185 ath11k_hif_irq_enable(ab);
2186 mutex_unlock(&ab->core_lock);
2187
2188 return 0;
2189
2190 err_core_stop:
2191 ath11k_core_stop(ab);
2192 ath11k_mac_destroy(ab);
2193 err_dp_free:
2194 ath11k_dp_free(ab);
2195 mutex_unlock(&ab->core_lock);
2196 err_firmware_stop:
2197 ath11k_qmi_firmware_stop(ab);
2198
2199 return ret;
2200 }
2201
ath11k_core_reconfigure_on_crash(struct ath11k_base * ab)2202 static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab)
2203 {
2204 int ret;
2205
2206 mutex_lock(&ab->core_lock);
2207 ath11k_thermal_unregister(ab);
2208 ath11k_dp_pdev_free(ab);
2209 ath11k_spectral_deinit(ab);
2210 ath11k_ce_cleanup_pipes(ab);
2211 ath11k_wmi_detach(ab);
2212 ath11k_dp_pdev_reo_cleanup(ab);
2213 mutex_unlock(&ab->core_lock);
2214
2215 ath11k_dp_free(ab);
2216 ath11k_hal_srng_deinit(ab);
2217
2218 ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1;
2219
2220 ret = ath11k_hal_srng_init(ab);
2221 if (ret)
2222 return ret;
2223
2224 clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags);
2225
2226 ret = ath11k_core_qmi_firmware_ready(ab);
2227 if (ret)
2228 goto err_hal_srng_deinit;
2229
2230 clear_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags);
2231
2232 return 0;
2233
2234 err_hal_srng_deinit:
2235 ath11k_hal_srng_deinit(ab);
2236 return ret;
2237 }
2238
ath11k_core_halt(struct ath11k * ar)2239 void ath11k_core_halt(struct ath11k *ar)
2240 {
2241 struct ath11k_base *ab = ar->ab;
2242 struct list_head *pos, *n;
2243
2244 lockdep_assert_held(&ar->conf_mutex);
2245
2246 ar->num_created_vdevs = 0;
2247 ar->allocated_vdev_map = 0;
2248
2249 ath11k_mac_scan_finish(ar);
2250 ath11k_mac_peer_cleanup_all(ar);
2251 cancel_delayed_work_sync(&ar->scan.timeout);
2252 cancel_work_sync(&ar->channel_update_work);
2253 cancel_work_sync(&ar->regd_update_work);
2254 cancel_work_sync(&ab->update_11d_work);
2255
2256 rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL);
2257 synchronize_rcu();
2258
2259 spin_lock_bh(&ar->data_lock);
2260 list_for_each_safe(pos, n, &ar->arvifs)
2261 list_del_init(pos);
2262 spin_unlock_bh(&ar->data_lock);
2263
2264 idr_init(&ar->txmgmt_idr);
2265 }
2266
ath11k_update_11d(struct work_struct * work)2267 static void ath11k_update_11d(struct work_struct *work)
2268 {
2269 struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work);
2270 struct ath11k *ar;
2271 struct ath11k_pdev *pdev;
2272 int ret, i;
2273
2274 for (i = 0; i < ab->num_radios; i++) {
2275 pdev = &ab->pdevs[i];
2276 ar = pdev->ar;
2277
2278 spin_lock_bh(&ab->base_lock);
2279 memcpy(&ar->alpha2, &ab->new_alpha2, 2);
2280 spin_unlock_bh(&ab->base_lock);
2281
2282 ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c for pdev %d\n",
2283 ar->alpha2[0], ar->alpha2[1], i);
2284
2285 ret = ath11k_reg_set_cc(ar);
2286 if (ret)
2287 ath11k_warn(ar->ab,
2288 "pdev id %d failed set current country code: %d\n",
2289 i, ret);
2290 }
2291 }
2292
ath11k_core_pre_reconfigure_recovery(struct ath11k_base * ab)2293 void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab)
2294 {
2295 struct ath11k *ar;
2296 struct ath11k_pdev *pdev;
2297 int i;
2298
2299 spin_lock_bh(&ab->base_lock);
2300 ab->stats.fw_crash_counter++;
2301 spin_unlock_bh(&ab->base_lock);
2302
2303 for (i = 0; i < ab->num_radios; i++) {
2304 pdev = &ab->pdevs[i];
2305 ar = pdev->ar;
2306 if (!ar || ar->state == ATH11K_STATE_OFF ||
2307 ar->state == ATH11K_STATE_FTM)
2308 continue;
2309
2310 ieee80211_stop_queues(ar->hw);
2311 ath11k_mac_drain_tx(ar);
2312 ar->state_11d = ATH11K_11D_IDLE;
2313 complete(&ar->completed_11d_scan);
2314 complete(&ar->scan.started);
2315 complete_all(&ar->scan.completed);
2316 complete(&ar->scan.on_channel);
2317 complete(&ar->peer_assoc_done);
2318 complete(&ar->peer_delete_done);
2319 complete(&ar->install_key_done);
2320 complete(&ar->vdev_setup_done);
2321 complete(&ar->vdev_delete_done);
2322 complete(&ar->bss_survey_done);
2323 complete(&ar->thermal.wmi_sync);
2324
2325 wake_up(&ar->dp.tx_empty_waitq);
2326 idr_for_each(&ar->txmgmt_idr,
2327 ath11k_mac_tx_mgmt_pending_free, ar);
2328 idr_destroy(&ar->txmgmt_idr);
2329 wake_up(&ar->txmgmt_empty_waitq);
2330
2331 ar->monitor_vdev_id = -1;
2332 clear_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags);
2333 clear_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags);
2334 }
2335
2336 wake_up(&ab->wmi_ab.tx_credits_wq);
2337 wake_up(&ab->peer_mapping_wq);
2338
2339 reinit_completion(&ab->driver_recovery);
2340 }
2341
ath11k_core_post_reconfigure_recovery(struct ath11k_base * ab)2342 static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab)
2343 {
2344 struct ath11k *ar;
2345 struct ath11k_pdev *pdev;
2346 int i;
2347
2348 for (i = 0; i < ab->num_radios; i++) {
2349 pdev = &ab->pdevs[i];
2350 ar = pdev->ar;
2351 if (!ar || ar->state == ATH11K_STATE_OFF)
2352 continue;
2353
2354 mutex_lock(&ar->conf_mutex);
2355
2356 switch (ar->state) {
2357 case ATH11K_STATE_ON:
2358 ar->state = ATH11K_STATE_RESTARTING;
2359 ath11k_core_halt(ar);
2360 ieee80211_restart_hw(ar->hw);
2361 break;
2362 case ATH11K_STATE_OFF:
2363 ath11k_warn(ab,
2364 "cannot restart radio %d that hasn't been started\n",
2365 i);
2366 break;
2367 case ATH11K_STATE_RESTARTING:
2368 break;
2369 case ATH11K_STATE_RESTARTED:
2370 ar->state = ATH11K_STATE_WEDGED;
2371 fallthrough;
2372 case ATH11K_STATE_WEDGED:
2373 ath11k_warn(ab,
2374 "device is wedged, will not restart radio %d\n", i);
2375 break;
2376 case ATH11K_STATE_FTM:
2377 ath11k_dbg(ab, ATH11K_DBG_TESTMODE,
2378 "fw mode reset done radio %d\n", i);
2379 break;
2380 }
2381
2382 mutex_unlock(&ar->conf_mutex);
2383 }
2384 complete(&ab->driver_recovery);
2385 }
2386
ath11k_core_restart(struct work_struct * work)2387 static void ath11k_core_restart(struct work_struct *work)
2388 {
2389 struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work);
2390 int ret;
2391
2392 ret = ath11k_core_reconfigure_on_crash(ab);
2393 if (ret) {
2394 ath11k_err(ab, "failed to reconfigure driver on crash recovery\n");
2395 return;
2396 }
2397
2398 if (ab->is_reset)
2399 complete_all(&ab->reconfigure_complete);
2400
2401 if (!ab->is_reset)
2402 ath11k_core_post_reconfigure_recovery(ab);
2403
2404 complete(&ab->restart_completed);
2405 }
2406
ath11k_core_reset(struct work_struct * work)2407 static void ath11k_core_reset(struct work_struct *work)
2408 {
2409 struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work);
2410 int reset_count, fail_cont_count;
2411 long time_left;
2412
2413 if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) {
2414 ath11k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags);
2415 return;
2416 }
2417
2418 /* Sometimes the recovery will fail and then the next all recovery fail,
2419 * this is to avoid infinite recovery since it can not recovery success.
2420 */
2421 fail_cont_count = atomic_read(&ab->fail_cont_count);
2422
2423 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL)
2424 return;
2425
2426 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST &&
2427 time_before(jiffies, ab->reset_fail_timeout))
2428 return;
2429
2430 reset_count = atomic_inc_return(&ab->reset_count);
2431
2432 if (reset_count > 1) {
2433 /* Sometimes it happened another reset worker before the previous one
2434 * completed, then the second reset worker will destroy the previous one,
2435 * thus below is to avoid that.
2436 */
2437 ath11k_warn(ab, "already resetting count %d\n", reset_count);
2438
2439 reinit_completion(&ab->reset_complete);
2440 time_left = wait_for_completion_timeout(&ab->reset_complete,
2441 ATH11K_RESET_TIMEOUT_HZ);
2442
2443 if (time_left) {
2444 ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n");
2445 atomic_dec(&ab->reset_count);
2446 return;
2447 }
2448
2449 ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ;
2450 /* Record the continuous recovery fail count when recovery failed*/
2451 atomic_inc(&ab->fail_cont_count);
2452 }
2453
2454 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n");
2455
2456 ab->is_reset = true;
2457 atomic_set(&ab->recovery_count, 0);
2458 reinit_completion(&ab->recovery_start);
2459 atomic_set(&ab->recovery_start_count, 0);
2460
2461 ath11k_coredump_collect(ab);
2462 ath11k_core_pre_reconfigure_recovery(ab);
2463
2464 reinit_completion(&ab->reconfigure_complete);
2465 ath11k_core_post_reconfigure_recovery(ab);
2466
2467 ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n");
2468
2469 time_left = wait_for_completion_timeout(&ab->recovery_start,
2470 ATH11K_RECOVER_START_TIMEOUT_HZ);
2471
2472 ath11k_hif_irq_disable(ab);
2473 ath11k_hif_ce_irq_disable(ab);
2474
2475 ath11k_hif_power_down(ab, false);
2476 ath11k_hif_power_up(ab);
2477
2478 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n");
2479 }
2480
ath11k_init_hw_params(struct ath11k_base * ab)2481 static int ath11k_init_hw_params(struct ath11k_base *ab)
2482 {
2483 const struct ath11k_hw_params *hw_params = NULL;
2484 int i;
2485
2486 for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) {
2487 hw_params = &ath11k_hw_params[i];
2488
2489 if (hw_params->hw_rev == ab->hw_rev)
2490 break;
2491 }
2492
2493 if (i == ARRAY_SIZE(ath11k_hw_params)) {
2494 ath11k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev);
2495 return -EINVAL;
2496 }
2497
2498 ab->hw_params = *hw_params;
2499
2500 ath11k_info(ab, "%s\n", ab->hw_params.name);
2501
2502 return 0;
2503 }
2504
ath11k_core_pre_init(struct ath11k_base * ab)2505 int ath11k_core_pre_init(struct ath11k_base *ab)
2506 {
2507 int ret;
2508
2509 ret = ath11k_init_hw_params(ab);
2510 if (ret) {
2511 ath11k_err(ab, "failed to get hw params: %d\n", ret);
2512 return ret;
2513 }
2514
2515 ret = ath11k_fw_pre_init(ab);
2516 if (ret) {
2517 ath11k_err(ab, "failed to pre init firmware: %d", ret);
2518 return ret;
2519 }
2520
2521 return 0;
2522 }
2523 EXPORT_SYMBOL(ath11k_core_pre_init);
2524
ath11k_core_pm_notify(struct notifier_block * nb,unsigned long action,void * nouse)2525 static int ath11k_core_pm_notify(struct notifier_block *nb,
2526 unsigned long action, void *nouse)
2527 {
2528 struct ath11k_base *ab = container_of(nb, struct ath11k_base,
2529 pm_nb);
2530
2531 switch (action) {
2532 case PM_SUSPEND_PREPARE:
2533 ab->actual_pm_policy = ab->pm_policy;
2534 break;
2535 case PM_HIBERNATION_PREPARE:
2536 ab->actual_pm_policy = ATH11K_PM_DEFAULT;
2537 break;
2538 default:
2539 break;
2540 }
2541
2542 return NOTIFY_OK;
2543 }
2544
ath11k_core_pm_notifier_register(struct ath11k_base * ab)2545 static int ath11k_core_pm_notifier_register(struct ath11k_base *ab)
2546 {
2547 ab->pm_nb.notifier_call = ath11k_core_pm_notify;
2548 return register_pm_notifier(&ab->pm_nb);
2549 }
2550
ath11k_core_pm_notifier_unregister(struct ath11k_base * ab)2551 void ath11k_core_pm_notifier_unregister(struct ath11k_base *ab)
2552 {
2553 int ret;
2554
2555 ret = unregister_pm_notifier(&ab->pm_nb);
2556 if (ret)
2557 /* just warn here, there is nothing can be done in fail case */
2558 ath11k_warn(ab, "failed to unregister PM notifier %d\n", ret);
2559 }
2560 EXPORT_SYMBOL(ath11k_core_pm_notifier_unregister);
2561
ath11k_core_init(struct ath11k_base * ab)2562 int ath11k_core_init(struct ath11k_base *ab)
2563 {
2564 const struct dmi_system_id *dmi_id;
2565 int ret;
2566
2567 dmi_id = dmi_first_match(ath11k_pm_quirk_table);
2568 if (dmi_id)
2569 ab->pm_policy = (kernel_ulong_t)dmi_id->driver_data;
2570 else
2571 ab->pm_policy = ATH11K_PM_DEFAULT;
2572
2573 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pm policy %u\n", ab->pm_policy);
2574
2575 ret = ath11k_core_pm_notifier_register(ab);
2576 if (ret) {
2577 ath11k_err(ab, "failed to register PM notifier: %d\n", ret);
2578 return ret;
2579 }
2580
2581 ret = ath11k_core_soc_create(ab);
2582 if (ret) {
2583 ath11k_err(ab, "failed to create soc core: %d\n", ret);
2584 return ret;
2585 }
2586
2587 return 0;
2588 }
2589 EXPORT_SYMBOL(ath11k_core_init);
2590
ath11k_core_deinit(struct ath11k_base * ab)2591 void ath11k_core_deinit(struct ath11k_base *ab)
2592 {
2593 mutex_lock(&ab->core_lock);
2594
2595 ath11k_core_pdev_destroy(ab);
2596 ath11k_core_stop(ab);
2597
2598 mutex_unlock(&ab->core_lock);
2599
2600 ath11k_hif_power_down(ab, false);
2601 ath11k_mac_destroy(ab);
2602 ath11k_core_soc_destroy(ab);
2603 ath11k_core_pm_notifier_unregister(ab);
2604 }
2605 EXPORT_SYMBOL(ath11k_core_deinit);
2606
ath11k_core_free(struct ath11k_base * ab)2607 void ath11k_core_free(struct ath11k_base *ab)
2608 {
2609 destroy_workqueue(ab->workqueue_aux);
2610 destroy_workqueue(ab->workqueue);
2611
2612 kfree(ab);
2613 }
2614 EXPORT_SYMBOL(ath11k_core_free);
2615
ath11k_core_alloc(struct device * dev,size_t priv_size,enum ath11k_bus bus)2616 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
2617 enum ath11k_bus bus)
2618 {
2619 struct ath11k_base *ab;
2620
2621 ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL);
2622 if (!ab)
2623 return NULL;
2624
2625 init_completion(&ab->driver_recovery);
2626
2627 ab->workqueue = create_singlethread_workqueue("ath11k_wq");
2628 if (!ab->workqueue)
2629 goto err_sc_free;
2630
2631 ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq");
2632 if (!ab->workqueue_aux)
2633 goto err_free_wq;
2634
2635 mutex_init(&ab->core_lock);
2636 mutex_init(&ab->tbl_mtx_lock);
2637 spin_lock_init(&ab->base_lock);
2638 mutex_init(&ab->vdev_id_11d_lock);
2639 init_completion(&ab->reset_complete);
2640 init_completion(&ab->reconfigure_complete);
2641 init_completion(&ab->recovery_start);
2642
2643 INIT_LIST_HEAD(&ab->peers);
2644 init_waitqueue_head(&ab->peer_mapping_wq);
2645 init_waitqueue_head(&ab->wmi_ab.tx_credits_wq);
2646 init_waitqueue_head(&ab->qmi.cold_boot_waitq);
2647 INIT_WORK(&ab->restart_work, ath11k_core_restart);
2648 INIT_WORK(&ab->update_11d_work, ath11k_update_11d);
2649 INIT_WORK(&ab->reset_work, ath11k_core_reset);
2650 INIT_WORK(&ab->dump_work, ath11k_coredump_upload);
2651 timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0);
2652 init_completion(&ab->htc_suspend);
2653 init_completion(&ab->wow.wakeup_completed);
2654 init_completion(&ab->restart_completed);
2655
2656 ab->dev = dev;
2657 ab->hif.bus = bus;
2658
2659 return ab;
2660
2661 err_free_wq:
2662 destroy_workqueue(ab->workqueue);
2663 err_sc_free:
2664 kfree(ab);
2665 return NULL;
2666 }
2667 EXPORT_SYMBOL(ath11k_core_alloc);
2668
2669 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards.");
2670 MODULE_LICENSE("Dual BSD/GPL");
2671