1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 6 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 7 */ 8 9 #include <linux/export.h> 10 #include <linux/module.h> 11 #include <linux/firmware.h> 12 #include <linux/of.h> 13 #include <linux/property.h> 14 #include <linux/dmi.h> 15 #include <linux/ctype.h> 16 #include <linux/pm_qos.h> 17 #include <linux/nvmem-consumer.h> 18 #include <asm/byteorder.h> 19 20 #include "core.h" 21 #include "mac.h" 22 #include "htc.h" 23 #include "hif.h" 24 #include "wmi.h" 25 #include "bmi.h" 26 #include "debug.h" 27 #include "htt.h" 28 #include "testmode.h" 29 #include "wmi-ops.h" 30 #include "coredump.h" 31 #include "leds.h" 32 33 unsigned int ath10k_debug_mask; 34 EXPORT_SYMBOL(ath10k_debug_mask); 35 36 static unsigned int ath10k_cryptmode_param; 37 static bool uart_print; 38 static bool skip_otp; 39 static bool fw_diag_log; 40 41 /* frame mode values are mapped as per enum ath10k_hw_txrx_mode */ 42 unsigned int ath10k_frame_mode = ATH10K_HW_TXRX_NATIVE_WIFI; 43 44 unsigned long ath10k_coredump_mask = BIT(ATH10K_FW_CRASH_DUMP_REGISTERS) | 45 BIT(ATH10K_FW_CRASH_DUMP_CE_DATA); 46 47 /* FIXME: most of these should be readonly */ 48 module_param_named(debug_mask, ath10k_debug_mask, uint, 0644); 49 module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644); 50 module_param(uart_print, bool, 0644); 51 module_param(skip_otp, bool, 0644); 52 module_param(fw_diag_log, bool, 0644); 53 module_param_named(frame_mode, ath10k_frame_mode, uint, 0644); 54 module_param_named(coredump_mask, ath10k_coredump_mask, ulong, 0444); 55 56 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 57 MODULE_PARM_DESC(uart_print, "Uart target debugging"); 58 MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode"); 59 MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software"); 60 MODULE_PARM_DESC(frame_mode, 61 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)"); 62 MODULE_PARM_DESC(coredump_mask, "Bitfield of what to include in firmware crash file"); 63 MODULE_PARM_DESC(fw_diag_log, "Diag based fw log debugging"); 64 65 static const struct ath10k_hw_params ath10k_hw_params_list[] = { 66 { 67 .id = QCA988X_HW_2_0_VERSION, 68 .dev_id = QCA988X_2_0_DEVICE_ID, 69 .bus = ATH10K_BUS_PCI, 70 .name = "qca988x hw2.0", 71 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, 72 .uart_pin = 7, 73 .led_pin = 1, 74 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 75 .otp_exe_param = 0, 76 .channel_counters_freq_hz = 88000, 77 .max_probe_resp_desc_thres = 0, 78 .cal_data_len = 2116, 79 .fw = { 80 .dir = QCA988X_HW_2_0_FW_DIR, 81 .board_size = QCA988X_BOARD_DATA_SZ, 82 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, 83 }, 84 .rx_desc_ops = &qca988x_rx_desc_ops, 85 .hw_ops = &qca988x_ops, 86 .decap_align_bytes = 4, 87 .spectral_bin_discard = 0, 88 .spectral_bin_offset = 0, 89 .vht160_mcs_rx_highest = 0, 90 .vht160_mcs_tx_highest = 0, 91 .n_cipher_suites = 8, 92 .ast_skid_limit = 0x10, 93 .num_wds_entries = 0x20, 94 .target_64bit = false, 95 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 96 .shadow_reg_support = false, 97 .rri_on_ddr = false, 98 .hw_filter_reset_required = true, 99 .fw_diag_ce_download = false, 100 .credit_size_workaround = false, 101 .tx_stats_over_pktlog = true, 102 .dynamic_sar_support = false, 103 .hw_restart_disconnect = false, 104 .use_fw_tx_credits = true, 105 .delay_unmap_buffer = false, 106 .mcast_frame_registration = false, 107 }, 108 { 109 .id = QCA988X_HW_2_0_VERSION, 110 .dev_id = QCA988X_2_0_DEVICE_ID_UBNT, 111 .name = "qca988x hw2.0 ubiquiti", 112 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, 113 .uart_pin = 7, 114 .led_pin = 0, 115 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 116 .otp_exe_param = 0, 117 .channel_counters_freq_hz = 88000, 118 .max_probe_resp_desc_thres = 0, 119 .cal_data_len = 2116, 120 .fw = { 121 .dir = QCA988X_HW_2_0_FW_DIR, 122 .board_size = QCA988X_BOARD_DATA_SZ, 123 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, 124 }, 125 .rx_desc_ops = &qca988x_rx_desc_ops, 126 .hw_ops = &qca988x_ops, 127 .decap_align_bytes = 4, 128 .spectral_bin_discard = 0, 129 .spectral_bin_offset = 0, 130 .vht160_mcs_rx_highest = 0, 131 .vht160_mcs_tx_highest = 0, 132 .n_cipher_suites = 8, 133 .ast_skid_limit = 0x10, 134 .num_wds_entries = 0x20, 135 .target_64bit = false, 136 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 137 .shadow_reg_support = false, 138 .rri_on_ddr = false, 139 .hw_filter_reset_required = true, 140 .fw_diag_ce_download = false, 141 .credit_size_workaround = false, 142 .tx_stats_over_pktlog = true, 143 .dynamic_sar_support = false, 144 .hw_restart_disconnect = false, 145 .use_fw_tx_credits = true, 146 .delay_unmap_buffer = false, 147 .mcast_frame_registration = false, 148 }, 149 { 150 .id = QCA9887_HW_1_0_VERSION, 151 .dev_id = QCA9887_1_0_DEVICE_ID, 152 .bus = ATH10K_BUS_PCI, 153 .name = "qca9887 hw1.0", 154 .patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR, 155 .uart_pin = 7, 156 .led_pin = 1, 157 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, 158 .otp_exe_param = 0, 159 .channel_counters_freq_hz = 88000, 160 .max_probe_resp_desc_thres = 0, 161 .cal_data_len = 2116, 162 .fw = { 163 .dir = QCA9887_HW_1_0_FW_DIR, 164 .board_size = QCA9887_BOARD_DATA_SZ, 165 .board_ext_size = QCA9887_BOARD_EXT_DATA_SZ, 166 }, 167 .rx_desc_ops = &qca988x_rx_desc_ops, 168 .hw_ops = &qca988x_ops, 169 .decap_align_bytes = 4, 170 .spectral_bin_discard = 0, 171 .spectral_bin_offset = 0, 172 .vht160_mcs_rx_highest = 0, 173 .vht160_mcs_tx_highest = 0, 174 .n_cipher_suites = 8, 175 .ast_skid_limit = 0x10, 176 .num_wds_entries = 0x20, 177 .target_64bit = false, 178 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 179 .shadow_reg_support = false, 180 .rri_on_ddr = false, 181 .hw_filter_reset_required = true, 182 .fw_diag_ce_download = false, 183 .credit_size_workaround = false, 184 .tx_stats_over_pktlog = false, 185 .dynamic_sar_support = false, 186 .hw_restart_disconnect = false, 187 .use_fw_tx_credits = true, 188 .delay_unmap_buffer = false, 189 .mcast_frame_registration = false, 190 }, 191 { 192 .id = QCA6174_HW_3_2_VERSION, 193 .dev_id = QCA6174_3_2_DEVICE_ID, 194 .bus = ATH10K_BUS_SDIO, 195 .name = "qca6174 hw3.2 sdio", 196 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 197 .uart_pin = 19, 198 .led_pin = 0, 199 .otp_exe_param = 0, 200 .channel_counters_freq_hz = 88000, 201 .max_probe_resp_desc_thres = 0, 202 .cal_data_len = 0, 203 .fw = { 204 .dir = QCA6174_HW_3_0_FW_DIR, 205 .board_size = QCA6174_BOARD_DATA_SZ, 206 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 207 }, 208 .rx_desc_ops = &qca988x_rx_desc_ops, 209 .hw_ops = &qca6174_sdio_ops, 210 .hw_clk = qca6174_clk, 211 .target_cpu_freq = 176000000, 212 .decap_align_bytes = 4, 213 .n_cipher_suites = 8, 214 .num_peers = 10, 215 .ast_skid_limit = 0x10, 216 .num_wds_entries = 0x20, 217 .uart_pin_workaround = true, 218 .tx_stats_over_pktlog = false, 219 .credit_size_workaround = false, 220 .bmi_large_size_download = true, 221 .supports_peer_stats_info = true, 222 .dynamic_sar_support = true, 223 .hw_restart_disconnect = false, 224 .use_fw_tx_credits = true, 225 .delay_unmap_buffer = false, 226 .mcast_frame_registration = false, 227 }, 228 { 229 .id = QCA6174_HW_2_1_VERSION, 230 .dev_id = QCA6164_2_1_DEVICE_ID, 231 .bus = ATH10K_BUS_PCI, 232 .name = "qca6164 hw2.1", 233 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, 234 .uart_pin = 6, 235 .led_pin = 0, 236 .otp_exe_param = 0, 237 .channel_counters_freq_hz = 88000, 238 .max_probe_resp_desc_thres = 0, 239 .cal_data_len = 8124, 240 .fw = { 241 .dir = QCA6174_HW_2_1_FW_DIR, 242 .board_size = QCA6174_BOARD_DATA_SZ, 243 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 244 }, 245 .rx_desc_ops = &qca988x_rx_desc_ops, 246 .hw_ops = &qca988x_ops, 247 .decap_align_bytes = 4, 248 .spectral_bin_discard = 0, 249 .spectral_bin_offset = 0, 250 .vht160_mcs_rx_highest = 0, 251 .vht160_mcs_tx_highest = 0, 252 .n_cipher_suites = 8, 253 .ast_skid_limit = 0x10, 254 .num_wds_entries = 0x20, 255 .target_64bit = false, 256 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 257 .shadow_reg_support = false, 258 .rri_on_ddr = false, 259 .hw_filter_reset_required = true, 260 .fw_diag_ce_download = false, 261 .credit_size_workaround = false, 262 .tx_stats_over_pktlog = false, 263 .dynamic_sar_support = false, 264 .hw_restart_disconnect = false, 265 .use_fw_tx_credits = true, 266 .delay_unmap_buffer = false, 267 .mcast_frame_registration = false, 268 }, 269 { 270 .id = QCA6174_HW_2_1_VERSION, 271 .dev_id = QCA6174_2_1_DEVICE_ID, 272 .bus = ATH10K_BUS_PCI, 273 .name = "qca6174 hw2.1", 274 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, 275 .uart_pin = 6, 276 .led_pin = 0, 277 .otp_exe_param = 0, 278 .channel_counters_freq_hz = 88000, 279 .max_probe_resp_desc_thres = 0, 280 .cal_data_len = 8124, 281 .fw = { 282 .dir = QCA6174_HW_2_1_FW_DIR, 283 .board_size = QCA6174_BOARD_DATA_SZ, 284 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 285 }, 286 .rx_desc_ops = &qca988x_rx_desc_ops, 287 .hw_ops = &qca988x_ops, 288 .decap_align_bytes = 4, 289 .spectral_bin_discard = 0, 290 .spectral_bin_offset = 0, 291 .vht160_mcs_rx_highest = 0, 292 .vht160_mcs_tx_highest = 0, 293 .n_cipher_suites = 8, 294 .ast_skid_limit = 0x10, 295 .num_wds_entries = 0x20, 296 .target_64bit = false, 297 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 298 .shadow_reg_support = false, 299 .rri_on_ddr = false, 300 .hw_filter_reset_required = true, 301 .fw_diag_ce_download = false, 302 .credit_size_workaround = false, 303 .tx_stats_over_pktlog = false, 304 .dynamic_sar_support = false, 305 .hw_restart_disconnect = false, 306 .use_fw_tx_credits = true, 307 .delay_unmap_buffer = false, 308 .mcast_frame_registration = false, 309 }, 310 { 311 .id = QCA6174_HW_3_0_VERSION, 312 .dev_id = QCA6174_2_1_DEVICE_ID, 313 .bus = ATH10K_BUS_PCI, 314 .name = "qca6174 hw3.0", 315 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 316 .uart_pin = 6, 317 .led_pin = 0, 318 .otp_exe_param = 0, 319 .channel_counters_freq_hz = 88000, 320 .max_probe_resp_desc_thres = 0, 321 .cal_data_len = 8124, 322 .fw = { 323 .dir = QCA6174_HW_3_0_FW_DIR, 324 .board_size = QCA6174_BOARD_DATA_SZ, 325 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 326 }, 327 .rx_desc_ops = &qca988x_rx_desc_ops, 328 .hw_ops = &qca988x_ops, 329 .decap_align_bytes = 4, 330 .spectral_bin_discard = 0, 331 .spectral_bin_offset = 0, 332 .vht160_mcs_rx_highest = 0, 333 .vht160_mcs_tx_highest = 0, 334 .n_cipher_suites = 8, 335 .ast_skid_limit = 0x10, 336 .num_wds_entries = 0x20, 337 .target_64bit = false, 338 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 339 .shadow_reg_support = false, 340 .rri_on_ddr = false, 341 .hw_filter_reset_required = true, 342 .fw_diag_ce_download = false, 343 .credit_size_workaround = false, 344 .tx_stats_over_pktlog = false, 345 .dynamic_sar_support = false, 346 .hw_restart_disconnect = false, 347 .use_fw_tx_credits = true, 348 .delay_unmap_buffer = false, 349 .mcast_frame_registration = false, 350 }, 351 { 352 .id = QCA6174_HW_3_2_VERSION, 353 .dev_id = QCA6174_2_1_DEVICE_ID, 354 .bus = ATH10K_BUS_PCI, 355 .name = "qca6174 hw3.2", 356 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, 357 .uart_pin = 6, 358 .led_pin = 0, 359 .otp_exe_param = 0, 360 .channel_counters_freq_hz = 88000, 361 .max_probe_resp_desc_thres = 0, 362 .cal_data_len = 8124, 363 .fw = { 364 /* uses same binaries as hw3.0 */ 365 .dir = QCA6174_HW_3_0_FW_DIR, 366 .board_size = QCA6174_BOARD_DATA_SZ, 367 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, 368 }, 369 .rx_desc_ops = &qca988x_rx_desc_ops, 370 .hw_ops = &qca6174_ops, 371 .hw_clk = qca6174_clk, 372 .target_cpu_freq = 176000000, 373 .decap_align_bytes = 4, 374 .spectral_bin_discard = 0, 375 .spectral_bin_offset = 0, 376 .vht160_mcs_rx_highest = 0, 377 .vht160_mcs_tx_highest = 0, 378 .n_cipher_suites = 8, 379 .ast_skid_limit = 0x10, 380 .num_wds_entries = 0x20, 381 .target_64bit = false, 382 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 383 .shadow_reg_support = false, 384 .rri_on_ddr = false, 385 .hw_filter_reset_required = true, 386 .fw_diag_ce_download = true, 387 .credit_size_workaround = false, 388 .tx_stats_over_pktlog = false, 389 .supports_peer_stats_info = true, 390 .dynamic_sar_support = true, 391 .hw_restart_disconnect = false, 392 .use_fw_tx_credits = true, 393 .delay_unmap_buffer = false, 394 .mcast_frame_registration = true, 395 }, 396 { 397 .id = QCA99X0_HW_2_0_DEV_VERSION, 398 .dev_id = QCA99X0_2_0_DEVICE_ID, 399 .bus = ATH10K_BUS_PCI, 400 .name = "qca99x0 hw2.0", 401 .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR, 402 .uart_pin = 7, 403 .led_pin = 17, 404 .otp_exe_param = 0x00000700, 405 .continuous_frag_desc = true, 406 .cck_rate_map_rev2 = true, 407 .channel_counters_freq_hz = 150000, 408 .max_probe_resp_desc_thres = 24, 409 .tx_chain_mask = 0xf, 410 .rx_chain_mask = 0xf, 411 .max_spatial_stream = 4, 412 .cal_data_len = 12064, 413 .fw = { 414 .dir = QCA99X0_HW_2_0_FW_DIR, 415 .board_size = QCA99X0_BOARD_DATA_SZ, 416 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 417 }, 418 .sw_decrypt_mcast_mgmt = true, 419 .rx_desc_ops = &qca99x0_rx_desc_ops, 420 .hw_ops = &qca99x0_ops, 421 .decap_align_bytes = 1, 422 .spectral_bin_discard = 4, 423 .spectral_bin_offset = 0, 424 .vht160_mcs_rx_highest = 0, 425 .vht160_mcs_tx_highest = 0, 426 .n_cipher_suites = 11, 427 .ast_skid_limit = 0x10, 428 .num_wds_entries = 0x20, 429 .target_64bit = false, 430 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 431 .shadow_reg_support = false, 432 .rri_on_ddr = false, 433 .hw_filter_reset_required = true, 434 .fw_diag_ce_download = false, 435 .credit_size_workaround = false, 436 .tx_stats_over_pktlog = false, 437 .dynamic_sar_support = false, 438 .hw_restart_disconnect = false, 439 .use_fw_tx_credits = true, 440 .delay_unmap_buffer = false, 441 .mcast_frame_registration = false, 442 }, 443 { 444 .id = QCA9984_HW_1_0_DEV_VERSION, 445 .dev_id = QCA9984_1_0_DEVICE_ID, 446 .bus = ATH10K_BUS_PCI, 447 .name = "qca9984/qca9994 hw1.0", 448 .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR, 449 .uart_pin = 7, 450 .led_pin = 17, 451 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 452 .otp_exe_param = 0x00000700, 453 .continuous_frag_desc = true, 454 .cck_rate_map_rev2 = true, 455 .channel_counters_freq_hz = 150000, 456 .max_probe_resp_desc_thres = 24, 457 .tx_chain_mask = 0xf, 458 .rx_chain_mask = 0xf, 459 .max_spatial_stream = 4, 460 .cal_data_len = 12064, 461 .fw = { 462 .dir = QCA9984_HW_1_0_FW_DIR, 463 .board_size = QCA99X0_BOARD_DATA_SZ, 464 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 465 .ext_board_size = QCA99X0_EXT_BOARD_DATA_SZ, 466 }, 467 .sw_decrypt_mcast_mgmt = true, 468 .rx_desc_ops = &qca99x0_rx_desc_ops, 469 .hw_ops = &qca99x0_ops, 470 .decap_align_bytes = 1, 471 .spectral_bin_discard = 12, 472 .spectral_bin_offset = 8, 473 474 /* Can do only 2x2 VHT160 or 80+80. 1560Mbps is 4x4 80Mhz 475 * or 2x2 160Mhz, long-guard-interval. 476 */ 477 .vht160_mcs_rx_highest = 1560, 478 .vht160_mcs_tx_highest = 1560, 479 .n_cipher_suites = 11, 480 .ast_skid_limit = 0x10, 481 .num_wds_entries = 0x20, 482 .target_64bit = false, 483 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 484 .shadow_reg_support = false, 485 .rri_on_ddr = false, 486 .hw_filter_reset_required = true, 487 .fw_diag_ce_download = false, 488 .credit_size_workaround = false, 489 .tx_stats_over_pktlog = false, 490 .dynamic_sar_support = false, 491 .hw_restart_disconnect = false, 492 .use_fw_tx_credits = true, 493 .delay_unmap_buffer = false, 494 .mcast_frame_registration = false, 495 }, 496 { 497 .id = QCA9888_HW_2_0_DEV_VERSION, 498 .dev_id = QCA9888_2_0_DEVICE_ID, 499 .bus = ATH10K_BUS_PCI, 500 .name = "qca9888 hw2.0", 501 .patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR, 502 .uart_pin = 7, 503 .led_pin = 17, 504 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 505 .otp_exe_param = 0x00000700, 506 .continuous_frag_desc = true, 507 .channel_counters_freq_hz = 150000, 508 .max_probe_resp_desc_thres = 24, 509 .tx_chain_mask = 3, 510 .rx_chain_mask = 3, 511 .max_spatial_stream = 2, 512 .cal_data_len = 12064, 513 .fw = { 514 .dir = QCA9888_HW_2_0_FW_DIR, 515 .board_size = QCA99X0_BOARD_DATA_SZ, 516 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, 517 }, 518 .sw_decrypt_mcast_mgmt = true, 519 .rx_desc_ops = &qca99x0_rx_desc_ops, 520 .hw_ops = &qca99x0_ops, 521 .decap_align_bytes = 1, 522 .spectral_bin_discard = 12, 523 .spectral_bin_offset = 8, 524 525 /* Can do only 1x1 VHT160 or 80+80. 780Mbps is 2x2 80Mhz or 526 * 1x1 160Mhz, long-guard-interval. 527 */ 528 .vht160_mcs_rx_highest = 780, 529 .vht160_mcs_tx_highest = 780, 530 .n_cipher_suites = 11, 531 .ast_skid_limit = 0x10, 532 .num_wds_entries = 0x20, 533 .target_64bit = false, 534 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 535 .shadow_reg_support = false, 536 .rri_on_ddr = false, 537 .hw_filter_reset_required = true, 538 .fw_diag_ce_download = false, 539 .credit_size_workaround = false, 540 .tx_stats_over_pktlog = false, 541 .dynamic_sar_support = false, 542 .hw_restart_disconnect = false, 543 .use_fw_tx_credits = true, 544 .delay_unmap_buffer = false, 545 .mcast_frame_registration = false, 546 }, 547 { 548 .id = QCA9377_HW_1_0_DEV_VERSION, 549 .dev_id = QCA9377_1_0_DEVICE_ID, 550 .bus = ATH10K_BUS_PCI, 551 .name = "qca9377 hw1.0", 552 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 553 .uart_pin = 6, 554 .led_pin = 0, 555 .otp_exe_param = 0, 556 .channel_counters_freq_hz = 88000, 557 .max_probe_resp_desc_thres = 0, 558 .cal_data_len = 8124, 559 .fw = { 560 .dir = QCA9377_HW_1_0_FW_DIR, 561 .board_size = QCA9377_BOARD_DATA_SZ, 562 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 563 }, 564 .rx_desc_ops = &qca988x_rx_desc_ops, 565 .hw_ops = &qca988x_ops, 566 .decap_align_bytes = 4, 567 .spectral_bin_discard = 0, 568 .spectral_bin_offset = 0, 569 .vht160_mcs_rx_highest = 0, 570 .vht160_mcs_tx_highest = 0, 571 .n_cipher_suites = 8, 572 .ast_skid_limit = 0x10, 573 .num_wds_entries = 0x20, 574 .target_64bit = false, 575 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 576 .shadow_reg_support = false, 577 .rri_on_ddr = false, 578 .hw_filter_reset_required = true, 579 .fw_diag_ce_download = false, 580 .credit_size_workaround = false, 581 .tx_stats_over_pktlog = false, 582 .dynamic_sar_support = false, 583 .hw_restart_disconnect = false, 584 .use_fw_tx_credits = true, 585 .delay_unmap_buffer = false, 586 .mcast_frame_registration = false, 587 }, 588 { 589 .id = QCA9377_HW_1_1_DEV_VERSION, 590 .dev_id = QCA9377_1_0_DEVICE_ID, 591 .bus = ATH10K_BUS_PCI, 592 .name = "qca9377 hw1.1", 593 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 594 .uart_pin = 6, 595 .led_pin = 0, 596 .otp_exe_param = 0, 597 .channel_counters_freq_hz = 88000, 598 .max_probe_resp_desc_thres = 0, 599 .cal_data_len = 8124, 600 .fw = { 601 .dir = QCA9377_HW_1_0_FW_DIR, 602 .board_size = QCA9377_BOARD_DATA_SZ, 603 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 604 }, 605 .rx_desc_ops = &qca988x_rx_desc_ops, 606 .hw_ops = &qca6174_ops, 607 .hw_clk = qca6174_clk, 608 .target_cpu_freq = 176000000, 609 .decap_align_bytes = 4, 610 .spectral_bin_discard = 0, 611 .spectral_bin_offset = 0, 612 .vht160_mcs_rx_highest = 0, 613 .vht160_mcs_tx_highest = 0, 614 .n_cipher_suites = 8, 615 .ast_skid_limit = 0x10, 616 .num_wds_entries = 0x20, 617 .target_64bit = false, 618 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 619 .shadow_reg_support = false, 620 .rri_on_ddr = false, 621 .hw_filter_reset_required = true, 622 .fw_diag_ce_download = true, 623 .credit_size_workaround = false, 624 .tx_stats_over_pktlog = false, 625 .dynamic_sar_support = false, 626 .hw_restart_disconnect = false, 627 .use_fw_tx_credits = true, 628 .delay_unmap_buffer = false, 629 .mcast_frame_registration = false, 630 }, 631 { 632 .id = QCA9377_HW_1_1_DEV_VERSION, 633 .dev_id = QCA9377_1_0_DEVICE_ID, 634 .bus = ATH10K_BUS_SDIO, 635 .name = "qca9377 hw1.1 sdio", 636 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, 637 .uart_pin = 19, 638 .led_pin = 0, 639 .otp_exe_param = 0, 640 .channel_counters_freq_hz = 88000, 641 .max_probe_resp_desc_thres = 0, 642 .cal_data_len = 8124, 643 .fw = { 644 .dir = QCA9377_HW_1_0_FW_DIR, 645 .board_size = QCA9377_BOARD_DATA_SZ, 646 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, 647 }, 648 .rx_desc_ops = &qca988x_rx_desc_ops, 649 .hw_ops = &qca6174_ops, 650 .hw_clk = qca6174_clk, 651 .target_cpu_freq = 176000000, 652 .decap_align_bytes = 4, 653 .n_cipher_suites = 8, 654 .num_peers = TARGET_QCA9377_HL_NUM_PEERS, 655 .ast_skid_limit = 0x10, 656 .num_wds_entries = 0x20, 657 .uart_pin_workaround = true, 658 .credit_size_workaround = true, 659 .dynamic_sar_support = false, 660 .hw_restart_disconnect = false, 661 .use_fw_tx_credits = true, 662 .delay_unmap_buffer = false, 663 .mcast_frame_registration = false, 664 }, 665 { 666 .id = QCA4019_HW_1_0_DEV_VERSION, 667 .dev_id = 0, 668 .bus = ATH10K_BUS_AHB, 669 .name = "qca4019 hw1.0", 670 .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR, 671 .uart_pin = 7, 672 .led_pin = 0, 673 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, 674 .otp_exe_param = 0x0010000, 675 .continuous_frag_desc = true, 676 .cck_rate_map_rev2 = true, 677 .channel_counters_freq_hz = 125000, 678 .max_probe_resp_desc_thres = 24, 679 .tx_chain_mask = 0x3, 680 .rx_chain_mask = 0x3, 681 .max_spatial_stream = 2, 682 .cal_data_len = 12064, 683 .fw = { 684 .dir = QCA4019_HW_1_0_FW_DIR, 685 .board_size = QCA4019_BOARD_DATA_SZ, 686 .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ, 687 }, 688 .sw_decrypt_mcast_mgmt = true, 689 .rx_desc_ops = &qca99x0_rx_desc_ops, 690 .hw_ops = &qca99x0_ops, 691 .decap_align_bytes = 1, 692 .spectral_bin_discard = 4, 693 .spectral_bin_offset = 0, 694 .vht160_mcs_rx_highest = 0, 695 .vht160_mcs_tx_highest = 0, 696 .n_cipher_suites = 11, 697 .ast_skid_limit = 0x10, 698 .num_wds_entries = 0x20, 699 .target_64bit = false, 700 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL, 701 .shadow_reg_support = false, 702 .rri_on_ddr = false, 703 .hw_filter_reset_required = true, 704 .fw_diag_ce_download = false, 705 .credit_size_workaround = false, 706 .tx_stats_over_pktlog = false, 707 .dynamic_sar_support = false, 708 .hw_restart_disconnect = false, 709 .use_fw_tx_credits = true, 710 .delay_unmap_buffer = false, 711 .mcast_frame_registration = false, 712 }, 713 { 714 .id = WCN3990_HW_1_0_DEV_VERSION, 715 .dev_id = 0, 716 .bus = ATH10K_BUS_SNOC, 717 .name = "wcn3990 hw1.0", 718 .led_pin = 0, 719 .continuous_frag_desc = true, 720 .tx_chain_mask = 0x7, 721 .rx_chain_mask = 0x7, 722 .max_spatial_stream = 4, 723 .fw = { 724 .dir = WCN3990_HW_1_0_FW_DIR, 725 .board_size = WCN3990_BOARD_DATA_SZ, 726 .board_ext_size = WCN3990_BOARD_EXT_DATA_SZ, 727 }, 728 .sw_decrypt_mcast_mgmt = true, 729 .rx_desc_ops = &wcn3990_rx_desc_ops, 730 .hw_ops = &wcn3990_ops, 731 .decap_align_bytes = 1, 732 .num_peers = TARGET_HL_TLV_NUM_PEERS, 733 .n_cipher_suites = 11, 734 .ast_skid_limit = TARGET_HL_TLV_AST_SKID_LIMIT, 735 .num_wds_entries = TARGET_HL_TLV_NUM_WDS_ENTRIES, 736 .target_64bit = true, 737 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC, 738 .shadow_reg_support = true, 739 .rri_on_ddr = true, 740 .hw_filter_reset_required = false, 741 .fw_diag_ce_download = false, 742 .credit_size_workaround = false, 743 .tx_stats_over_pktlog = false, 744 .dynamic_sar_support = true, 745 .hw_restart_disconnect = true, 746 .use_fw_tx_credits = false, 747 .delay_unmap_buffer = true, 748 .mcast_frame_registration = false, 749 }, 750 }; 751 752 static const char *const ath10k_core_fw_feature_str[] = { 753 [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx", 754 [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x", 755 [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx", 756 [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p", 757 [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2", 758 [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps", 759 [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan", 760 [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp", 761 [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad", 762 [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init", 763 [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode", 764 [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca", 765 [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp", 766 [ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl", 767 [ATH10K_FW_FEATURE_BTCOEX_PARAM] = "btcoex-param", 768 [ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR] = "skip-null-func-war", 769 [ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST] = "allows-mesh-bcast", 770 [ATH10K_FW_FEATURE_NO_PS] = "no-ps", 771 [ATH10K_FW_FEATURE_MGMT_TX_BY_REF] = "mgmt-tx-by-reference", 772 [ATH10K_FW_FEATURE_NON_BMI] = "non-bmi", 773 [ATH10K_FW_FEATURE_SINGLE_CHAN_INFO_PER_CHANNEL] = "single-chan-info-per-channel", 774 [ATH10K_FW_FEATURE_PEER_FIXED_RATE] = "peer-fixed-rate", 775 [ATH10K_FW_FEATURE_IRAM_RECOVERY] = "iram-recovery", 776 }; 777 778 static unsigned int ath10k_core_get_fw_feature_str(char *buf, 779 size_t buf_len, 780 enum ath10k_fw_features feat) 781 { 782 /* make sure that ath10k_core_fw_feature_str[] gets updated */ 783 BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) != 784 ATH10K_FW_FEATURE_COUNT); 785 786 if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) || 787 WARN_ON(!ath10k_core_fw_feature_str[feat])) { 788 return scnprintf(buf, buf_len, "bit%d", feat); 789 } 790 791 return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]); 792 } 793 794 void ath10k_core_get_fw_features_str(struct ath10k *ar, 795 char *buf, 796 size_t buf_len) 797 { 798 size_t len = 0; 799 int i; 800 801 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { 802 if (test_bit(i, ar->normal_mode_fw.fw_file.fw_features)) { 803 if (len > 0) 804 len += scnprintf(buf + len, buf_len - len, ","); 805 806 len += ath10k_core_get_fw_feature_str(buf + len, 807 buf_len - len, 808 i); 809 } 810 } 811 } 812 813 static void ath10k_send_suspend_complete(struct ath10k *ar) 814 { 815 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n"); 816 817 complete(&ar->target_suspend); 818 } 819 820 static int ath10k_init_sdio(struct ath10k *ar, enum ath10k_firmware_mode mode) 821 { 822 bool mtu_workaround = ar->hw_params.credit_size_workaround; 823 int ret; 824 u32 param = 0; 825 826 ret = ath10k_bmi_write32(ar, hi_mbox_io_block_sz, 256); 827 if (ret) 828 return ret; 829 830 ret = ath10k_bmi_write32(ar, hi_mbox_isr_yield_limit, 99); 831 if (ret) 832 return ret; 833 834 ret = ath10k_bmi_read32(ar, hi_acs_flags, ¶m); 835 if (ret) 836 return ret; 837 838 param |= HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET; 839 840 if (mode == ATH10K_FIRMWARE_MODE_NORMAL && !mtu_workaround) 841 param |= HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE; 842 else 843 param &= ~HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE; 844 845 if (mode == ATH10K_FIRMWARE_MODE_UTF) 846 param &= ~HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET; 847 else 848 param |= HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET; 849 850 ret = ath10k_bmi_write32(ar, hi_acs_flags, param); 851 if (ret) 852 return ret; 853 854 ret = ath10k_bmi_read32(ar, hi_option_flag2, ¶m); 855 if (ret) 856 return ret; 857 858 param |= HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_HOST; 859 860 ret = ath10k_bmi_write32(ar, hi_option_flag2, param); 861 if (ret) 862 return ret; 863 864 return 0; 865 } 866 867 static int ath10k_init_configure_target(struct ath10k *ar) 868 { 869 u32 param_host; 870 int ret; 871 872 /* tell target which HTC version it is used*/ 873 ret = ath10k_bmi_write32(ar, hi_app_host_interest, 874 HTC_PROTOCOL_VERSION); 875 if (ret) { 876 ath10k_err(ar, "settings HTC version failed\n"); 877 return ret; 878 } 879 880 /* set the firmware mode to STA/IBSS/AP */ 881 ret = ath10k_bmi_read32(ar, hi_option_flag, ¶m_host); 882 if (ret) { 883 ath10k_err(ar, "setting firmware mode (1/2) failed\n"); 884 return ret; 885 } 886 887 /* TODO following parameters need to be re-visited. */ 888 /* num_device */ 889 param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT); 890 /* Firmware mode */ 891 /* FIXME: Why FW_MODE_AP ??.*/ 892 param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT); 893 /* mac_addr_method */ 894 param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT); 895 /* firmware_bridge */ 896 param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT); 897 /* fwsubmode */ 898 param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT); 899 900 ret = ath10k_bmi_write32(ar, hi_option_flag, param_host); 901 if (ret) { 902 ath10k_err(ar, "setting firmware mode (2/2) failed\n"); 903 return ret; 904 } 905 906 /* We do all byte-swapping on the host */ 907 ret = ath10k_bmi_write32(ar, hi_be, 0); 908 if (ret) { 909 ath10k_err(ar, "setting host CPU BE mode failed\n"); 910 return ret; 911 } 912 913 /* FW descriptor/Data swap flags */ 914 ret = ath10k_bmi_write32(ar, hi_fw_swap, 0); 915 916 if (ret) { 917 ath10k_err(ar, "setting FW data/desc swap flags failed\n"); 918 return ret; 919 } 920 921 /* Some devices have a special sanity check that verifies the PCI 922 * Device ID is written to this host interest var. It is known to be 923 * required to boot QCA6164. 924 */ 925 ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext, 926 ar->dev_id); 927 if (ret) { 928 ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret); 929 return ret; 930 } 931 932 return 0; 933 } 934 935 static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar, 936 const char *dir, 937 const char *file) 938 { 939 char filename[100]; 940 const struct firmware *fw; 941 int ret; 942 943 if (file == NULL) 944 return ERR_PTR(-ENOENT); 945 946 if (dir == NULL) 947 dir = "."; 948 949 if (ar->board_name) { 950 snprintf(filename, sizeof(filename), "%s/%s/%s", 951 dir, ar->board_name, file); 952 ret = firmware_request_nowarn(&fw, filename, ar->dev); 953 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot fw request '%s': %d\n", 954 filename, ret); 955 if (!ret) 956 return fw; 957 } 958 959 snprintf(filename, sizeof(filename), "%s/%s", dir, file); 960 ret = firmware_request_nowarn(&fw, filename, ar->dev); 961 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot fw request '%s': %d\n", 962 filename, ret); 963 if (ret) 964 return ERR_PTR(ret); 965 966 return fw; 967 } 968 969 static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data, 970 size_t data_len) 971 { 972 u32 board_data_size = ar->hw_params.fw.board_size; 973 u32 board_ext_data_size = ar->hw_params.fw.board_ext_size; 974 u32 board_ext_data_addr; 975 int ret; 976 977 ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr); 978 if (ret) { 979 ath10k_err(ar, "could not read board ext data addr (%d)\n", 980 ret); 981 return ret; 982 } 983 984 ath10k_dbg(ar, ATH10K_DBG_BOOT, 985 "boot push board extended data addr 0x%x\n", 986 board_ext_data_addr); 987 988 if (board_ext_data_addr == 0) 989 return 0; 990 991 if (data_len != (board_data_size + board_ext_data_size)) { 992 ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n", 993 data_len, board_data_size, board_ext_data_size); 994 return -EINVAL; 995 } 996 997 ret = ath10k_bmi_write_memory(ar, board_ext_data_addr, 998 data + board_data_size, 999 board_ext_data_size); 1000 if (ret) { 1001 ath10k_err(ar, "could not write board ext data (%d)\n", ret); 1002 return ret; 1003 } 1004 1005 ret = ath10k_bmi_write32(ar, hi_board_ext_data_config, 1006 (board_ext_data_size << 16) | 1); 1007 if (ret) { 1008 ath10k_err(ar, "could not write board ext data bit (%d)\n", 1009 ret); 1010 return ret; 1011 } 1012 1013 return 0; 1014 } 1015 1016 static int ath10k_core_get_board_id_from_otp(struct ath10k *ar) 1017 { 1018 u32 result, address; 1019 u8 board_id, chip_id; 1020 bool ext_bid_support; 1021 int ret, bmi_board_id_param; 1022 1023 address = ar->hw_params.patch_load_addr; 1024 1025 if (!ar->normal_mode_fw.fw_file.otp_data || 1026 !ar->normal_mode_fw.fw_file.otp_len) { 1027 ath10k_warn(ar, 1028 "failed to retrieve board id because of invalid otp\n"); 1029 return -ENODATA; 1030 } 1031 1032 if (ar->id.bmi_ids_valid) { 1033 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1034 "boot already acquired valid otp board id,skip download, board_id %d chip_id %d\n", 1035 ar->id.bmi_board_id, ar->id.bmi_chip_id); 1036 goto skip_otp_download; 1037 } 1038 1039 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1040 "boot upload otp to 0x%x len %zd for board id\n", 1041 address, ar->normal_mode_fw.fw_file.otp_len); 1042 1043 ret = ath10k_bmi_fast_download(ar, address, 1044 ar->normal_mode_fw.fw_file.otp_data, 1045 ar->normal_mode_fw.fw_file.otp_len); 1046 if (ret) { 1047 ath10k_err(ar, "could not write otp for board id check: %d\n", 1048 ret); 1049 return ret; 1050 } 1051 1052 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT || 1053 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE || 1054 ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM) 1055 bmi_board_id_param = BMI_PARAM_GET_FLASH_BOARD_ID; 1056 else 1057 bmi_board_id_param = BMI_PARAM_GET_EEPROM_BOARD_ID; 1058 1059 ret = ath10k_bmi_execute(ar, address, bmi_board_id_param, &result); 1060 if (ret) { 1061 ath10k_err(ar, "could not execute otp for board id check: %d\n", 1062 ret); 1063 return ret; 1064 } 1065 1066 board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP); 1067 chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP); 1068 ext_bid_support = (result & ATH10K_BMI_EXT_BOARD_ID_SUPPORT); 1069 1070 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1071 "boot get otp board id result 0x%08x board_id %d chip_id %d ext_bid_support %d\n", 1072 result, board_id, chip_id, ext_bid_support); 1073 1074 ar->id.ext_bid_supported = ext_bid_support; 1075 1076 if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0 || 1077 (board_id == 0)) { 1078 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1079 "board id does not exist in otp, ignore it\n"); 1080 return -EOPNOTSUPP; 1081 } 1082 1083 ar->id.bmi_ids_valid = true; 1084 ar->id.bmi_board_id = board_id; 1085 ar->id.bmi_chip_id = chip_id; 1086 1087 skip_otp_download: 1088 1089 return 0; 1090 } 1091 1092 static void ath10k_core_check_bdfext(const struct dmi_header *hdr, void *data) 1093 { 1094 struct ath10k *ar = data; 1095 const char *bdf_ext; 1096 const char *magic = ATH10K_SMBIOS_BDF_EXT_MAGIC; 1097 u8 bdf_enabled; 1098 int i; 1099 1100 if (hdr->type != ATH10K_SMBIOS_BDF_EXT_TYPE) 1101 return; 1102 1103 if (hdr->length != ATH10K_SMBIOS_BDF_EXT_LENGTH) { 1104 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1105 "wrong smbios bdf ext type length (%d).\n", 1106 hdr->length); 1107 return; 1108 } 1109 1110 bdf_enabled = *((u8 *)hdr + ATH10K_SMBIOS_BDF_EXT_OFFSET); 1111 if (!bdf_enabled) { 1112 ath10k_dbg(ar, ATH10K_DBG_BOOT, "bdf variant name not found.\n"); 1113 return; 1114 } 1115 1116 /* Only one string exists (per spec) */ 1117 bdf_ext = (char *)hdr + hdr->length; 1118 1119 if (memcmp(bdf_ext, magic, strlen(magic)) != 0) { 1120 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1121 "bdf variant magic does not match.\n"); 1122 return; 1123 } 1124 1125 for (i = 0; i < strlen(bdf_ext); i++) { 1126 if (!isascii(bdf_ext[i]) || !isprint(bdf_ext[i])) { 1127 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1128 "bdf variant name contains non ascii chars.\n"); 1129 return; 1130 } 1131 } 1132 1133 /* Copy extension name without magic suffix */ 1134 if (strscpy(ar->id.bdf_ext, bdf_ext + strlen(magic), 1135 sizeof(ar->id.bdf_ext)) < 0) { 1136 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1137 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 1138 bdf_ext); 1139 return; 1140 } 1141 1142 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1143 "found and validated bdf variant smbios_type 0x%x bdf %s\n", 1144 ATH10K_SMBIOS_BDF_EXT_TYPE, bdf_ext); 1145 } 1146 1147 static int ath10k_core_check_smbios(struct ath10k *ar) 1148 { 1149 ar->id.bdf_ext[0] = '\0'; 1150 dmi_walk(ath10k_core_check_bdfext, ar); 1151 1152 if (ar->id.bdf_ext[0] == '\0') 1153 return -ENODATA; 1154 1155 return 0; 1156 } 1157 1158 int ath10k_core_check_dt(struct ath10k *ar) 1159 { 1160 struct device_node *node; 1161 const char *variant = NULL; 1162 1163 node = ar->dev->of_node; 1164 if (!node) 1165 return -ENOENT; 1166 1167 of_property_read_string(node, "qcom,calibration-variant", 1168 &variant); 1169 if (!variant) 1170 of_property_read_string(node, "qcom,ath10k-calibration-variant", 1171 &variant); 1172 if (!variant) 1173 return -ENODATA; 1174 1175 if (strscpy(ar->id.bdf_ext, variant, sizeof(ar->id.bdf_ext)) < 0) 1176 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1177 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 1178 variant); 1179 1180 return 0; 1181 } 1182 EXPORT_SYMBOL(ath10k_core_check_dt); 1183 1184 static int ath10k_download_fw(struct ath10k *ar) 1185 { 1186 u32 address, data_len; 1187 const void *data; 1188 int ret; 1189 struct pm_qos_request latency_qos = {}; 1190 1191 address = ar->hw_params.patch_load_addr; 1192 1193 data = ar->running_fw->fw_file.firmware_data; 1194 data_len = ar->running_fw->fw_file.firmware_len; 1195 1196 ret = ath10k_swap_code_seg_configure(ar, &ar->running_fw->fw_file); 1197 if (ret) { 1198 ath10k_err(ar, "failed to configure fw code swap: %d\n", 1199 ret); 1200 return ret; 1201 } 1202 1203 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1204 "boot uploading firmware image %p len %d\n", 1205 data, data_len); 1206 1207 /* Check if device supports to download firmware via 1208 * diag copy engine. Downloading firmware via diag CE 1209 * greatly reduces the time to download firmware. 1210 */ 1211 if (ar->hw_params.fw_diag_ce_download) { 1212 ret = ath10k_hw_diag_fast_download(ar, address, 1213 data, data_len); 1214 if (ret == 0) 1215 /* firmware upload via diag ce was successful */ 1216 return 0; 1217 1218 ath10k_warn(ar, 1219 "failed to upload firmware via diag ce, trying BMI: %d", 1220 ret); 1221 } 1222 1223 cpu_latency_qos_add_request(&latency_qos, 0); 1224 1225 ret = ath10k_bmi_fast_download(ar, address, data, data_len); 1226 1227 cpu_latency_qos_remove_request(&latency_qos); 1228 1229 return ret; 1230 } 1231 1232 void ath10k_core_free_board_files(struct ath10k *ar) 1233 { 1234 if (!IS_ERR(ar->normal_mode_fw.board)) 1235 release_firmware(ar->normal_mode_fw.board); 1236 1237 if (!IS_ERR(ar->normal_mode_fw.ext_board)) 1238 release_firmware(ar->normal_mode_fw.ext_board); 1239 1240 ar->normal_mode_fw.board = NULL; 1241 ar->normal_mode_fw.board_data = NULL; 1242 ar->normal_mode_fw.board_len = 0; 1243 ar->normal_mode_fw.ext_board = NULL; 1244 ar->normal_mode_fw.ext_board_data = NULL; 1245 ar->normal_mode_fw.ext_board_len = 0; 1246 } 1247 EXPORT_SYMBOL(ath10k_core_free_board_files); 1248 1249 static void ath10k_core_free_firmware_files(struct ath10k *ar) 1250 { 1251 if (!IS_ERR(ar->normal_mode_fw.fw_file.firmware)) 1252 release_firmware(ar->normal_mode_fw.fw_file.firmware); 1253 1254 if (!IS_ERR(ar->cal_file)) 1255 release_firmware(ar->cal_file); 1256 1257 if (!IS_ERR(ar->pre_cal_file)) 1258 release_firmware(ar->pre_cal_file); 1259 1260 ath10k_swap_code_seg_release(ar, &ar->normal_mode_fw.fw_file); 1261 1262 ar->normal_mode_fw.fw_file.otp_data = NULL; 1263 ar->normal_mode_fw.fw_file.otp_len = 0; 1264 1265 ar->normal_mode_fw.fw_file.firmware = NULL; 1266 ar->normal_mode_fw.fw_file.firmware_data = NULL; 1267 ar->normal_mode_fw.fw_file.firmware_len = 0; 1268 1269 ar->cal_file = NULL; 1270 ar->pre_cal_file = NULL; 1271 } 1272 1273 static int ath10k_fetch_cal_file(struct ath10k *ar) 1274 { 1275 char filename[100]; 1276 1277 /* pre-cal-<bus>-<id>.bin */ 1278 scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin", 1279 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1280 1281 ar->pre_cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); 1282 if (!IS_ERR(ar->pre_cal_file)) 1283 goto success; 1284 1285 /* cal-<bus>-<id>.bin */ 1286 scnprintf(filename, sizeof(filename), "cal-%s-%s.bin", 1287 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1288 1289 ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); 1290 if (IS_ERR(ar->cal_file)) 1291 /* calibration file is optional, don't print any warnings */ 1292 return PTR_ERR(ar->cal_file); 1293 success: 1294 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n", 1295 ATH10K_FW_DIR, filename); 1296 1297 return 0; 1298 } 1299 1300 static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar, int bd_ie_type) 1301 { 1302 const struct firmware *fw; 1303 char boardname[100]; 1304 1305 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1306 scnprintf(boardname, sizeof(boardname), "board-%s-%s.bin", 1307 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); 1308 1309 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar, 1310 ar->hw_params.fw.dir, 1311 boardname); 1312 if (IS_ERR(ar->normal_mode_fw.board)) { 1313 fw = ath10k_fetch_fw_file(ar, 1314 ar->hw_params.fw.dir, 1315 ATH10K_BOARD_DATA_FILE); 1316 ar->normal_mode_fw.board = fw; 1317 } 1318 1319 if (IS_ERR(ar->normal_mode_fw.board)) 1320 return PTR_ERR(ar->normal_mode_fw.board); 1321 1322 ar->normal_mode_fw.board_data = ar->normal_mode_fw.board->data; 1323 ar->normal_mode_fw.board_len = ar->normal_mode_fw.board->size; 1324 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1325 fw = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, 1326 ATH10K_EBOARD_DATA_FILE); 1327 ar->normal_mode_fw.ext_board = fw; 1328 if (IS_ERR(ar->normal_mode_fw.ext_board)) 1329 return PTR_ERR(ar->normal_mode_fw.ext_board); 1330 1331 ar->normal_mode_fw.ext_board_data = ar->normal_mode_fw.ext_board->data; 1332 ar->normal_mode_fw.ext_board_len = ar->normal_mode_fw.ext_board->size; 1333 } 1334 1335 return 0; 1336 } 1337 1338 static int ath10k_core_parse_bd_ie_board(struct ath10k *ar, 1339 const void *buf, size_t buf_len, 1340 const char *boardname, 1341 int bd_ie_type) 1342 { 1343 const struct ath10k_fw_ie *hdr; 1344 bool name_match_found; 1345 int ret, board_ie_id; 1346 size_t board_ie_len; 1347 const void *board_ie_data; 1348 1349 name_match_found = false; 1350 1351 /* go through ATH10K_BD_IE_BOARD_ elements */ 1352 while (buf_len > sizeof(struct ath10k_fw_ie)) { 1353 hdr = buf; 1354 board_ie_id = le32_to_cpu(hdr->id); 1355 board_ie_len = le32_to_cpu(hdr->len); 1356 board_ie_data = hdr->data; 1357 1358 buf_len -= sizeof(*hdr); 1359 buf += sizeof(*hdr); 1360 1361 if (buf_len < ALIGN(board_ie_len, 4)) { 1362 ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n", 1363 buf_len, ALIGN(board_ie_len, 4)); 1364 ret = -EINVAL; 1365 goto out; 1366 } 1367 1368 switch (board_ie_id) { 1369 case ATH10K_BD_IE_BOARD_NAME: 1370 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "", 1371 board_ie_data, board_ie_len); 1372 1373 if (board_ie_len != strlen(boardname)) 1374 break; 1375 1376 ret = memcmp(board_ie_data, boardname, strlen(boardname)); 1377 if (ret) 1378 break; 1379 1380 name_match_found = true; 1381 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1382 "boot found match for name '%s'", 1383 boardname); 1384 break; 1385 case ATH10K_BD_IE_BOARD_DATA: 1386 if (!name_match_found) 1387 /* no match found */ 1388 break; 1389 1390 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1391 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1392 "boot found board data for '%s'", 1393 boardname); 1394 1395 ar->normal_mode_fw.board_data = board_ie_data; 1396 ar->normal_mode_fw.board_len = board_ie_len; 1397 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1398 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1399 "boot found eboard data for '%s'", 1400 boardname); 1401 1402 ar->normal_mode_fw.ext_board_data = board_ie_data; 1403 ar->normal_mode_fw.ext_board_len = board_ie_len; 1404 } 1405 1406 ret = 0; 1407 goto out; 1408 default: 1409 ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n", 1410 board_ie_id); 1411 break; 1412 } 1413 1414 /* jump over the padding */ 1415 board_ie_len = ALIGN(board_ie_len, 4); 1416 1417 buf_len -= board_ie_len; 1418 buf += board_ie_len; 1419 } 1420 1421 /* no match found */ 1422 ret = -ENOENT; 1423 1424 out: 1425 return ret; 1426 } 1427 1428 static int ath10k_core_search_bd(struct ath10k *ar, 1429 const char *boardname, 1430 const u8 *data, 1431 size_t len) 1432 { 1433 size_t ie_len; 1434 struct ath10k_fw_ie *hdr; 1435 int ret = -ENOENT, ie_id; 1436 1437 while (len > sizeof(struct ath10k_fw_ie)) { 1438 hdr = (struct ath10k_fw_ie *)data; 1439 ie_id = le32_to_cpu(hdr->id); 1440 ie_len = le32_to_cpu(hdr->len); 1441 1442 len -= sizeof(*hdr); 1443 data = hdr->data; 1444 1445 if (len < ALIGN(ie_len, 4)) { 1446 ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n", 1447 ie_id, ie_len, len); 1448 return -EINVAL; 1449 } 1450 1451 switch (ie_id) { 1452 case ATH10K_BD_IE_BOARD: 1453 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len, 1454 boardname, 1455 ATH10K_BD_IE_BOARD); 1456 if (ret == -ENOENT) 1457 /* no match found, continue */ 1458 break; 1459 1460 /* either found or error, so stop searching */ 1461 goto out; 1462 case ATH10K_BD_IE_BOARD_EXT: 1463 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len, 1464 boardname, 1465 ATH10K_BD_IE_BOARD_EXT); 1466 if (ret == -ENOENT) 1467 /* no match found, continue */ 1468 break; 1469 1470 /* either found or error, so stop searching */ 1471 goto out; 1472 } 1473 1474 /* jump over the padding */ 1475 ie_len = ALIGN(ie_len, 4); 1476 1477 len -= ie_len; 1478 data += ie_len; 1479 } 1480 1481 out: 1482 /* return result of parse_bd_ie_board() or -ENOENT */ 1483 return ret; 1484 } 1485 1486 static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar, 1487 const char *boardname, 1488 const char *fallback_boardname1, 1489 const char *fallback_boardname2, 1490 const char *filename) 1491 { 1492 size_t len, magic_len; 1493 const u8 *data; 1494 int ret; 1495 1496 /* Skip if already fetched during board data download */ 1497 if (!ar->normal_mode_fw.board) 1498 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar, 1499 ar->hw_params.fw.dir, 1500 filename); 1501 if (IS_ERR(ar->normal_mode_fw.board)) 1502 return PTR_ERR(ar->normal_mode_fw.board); 1503 1504 data = ar->normal_mode_fw.board->data; 1505 len = ar->normal_mode_fw.board->size; 1506 1507 /* magic has extra null byte padded */ 1508 magic_len = strlen(ATH10K_BOARD_MAGIC) + 1; 1509 if (len < magic_len) { 1510 ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n", 1511 ar->hw_params.fw.dir, filename, len); 1512 ret = -EINVAL; 1513 goto err; 1514 } 1515 1516 if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) { 1517 ath10k_err(ar, "found invalid board magic\n"); 1518 ret = -EINVAL; 1519 goto err; 1520 } 1521 1522 /* magic is padded to 4 bytes */ 1523 magic_len = ALIGN(magic_len, 4); 1524 if (len < magic_len) { 1525 ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n", 1526 ar->hw_params.fw.dir, filename, len); 1527 ret = -EINVAL; 1528 goto err; 1529 } 1530 1531 data += magic_len; 1532 len -= magic_len; 1533 1534 /* attempt to find boardname in the IE list */ 1535 ret = ath10k_core_search_bd(ar, boardname, data, len); 1536 1537 /* if we didn't find it and have a fallback name, try that */ 1538 if (ret == -ENOENT && fallback_boardname1) 1539 ret = ath10k_core_search_bd(ar, fallback_boardname1, data, len); 1540 1541 if (ret == -ENOENT && fallback_boardname2) 1542 ret = ath10k_core_search_bd(ar, fallback_boardname2, data, len); 1543 1544 if (ret == -ENOENT) { 1545 ath10k_err(ar, 1546 "failed to fetch board data for %s from %s/%s\n", 1547 boardname, ar->hw_params.fw.dir, filename); 1548 ret = -ENODATA; 1549 } 1550 1551 if (ret) 1552 goto err; 1553 1554 return 0; 1555 1556 err: 1557 ath10k_core_free_board_files(ar); 1558 return ret; 1559 } 1560 1561 static int ath10k_core_create_board_name(struct ath10k *ar, char *name, 1562 size_t name_len, bool with_variant, 1563 bool with_chip_id) 1564 { 1565 /* strlen(',variant=') + strlen(ar->id.bdf_ext) */ 1566 char variant[9 + ATH10K_SMBIOS_BDF_EXT_STR_LENGTH] = {}; 1567 1568 if (with_variant && ar->id.bdf_ext[0] != '\0') 1569 scnprintf(variant, sizeof(variant), ",variant=%s", 1570 ar->id.bdf_ext); 1571 1572 if (ar->id.bmi_ids_valid) { 1573 scnprintf(name, name_len, 1574 "bus=%s,bmi-chip-id=%d,bmi-board-id=%d%s", 1575 ath10k_bus_str(ar->hif.bus), 1576 ar->id.bmi_chip_id, 1577 ar->id.bmi_board_id, variant); 1578 goto out; 1579 } 1580 1581 if (ar->id.qmi_ids_valid) { 1582 if (with_chip_id) 1583 scnprintf(name, name_len, 1584 "bus=%s,qmi-board-id=%x,qmi-chip-id=%x%s", 1585 ath10k_bus_str(ar->hif.bus), 1586 ar->id.qmi_board_id, ar->id.qmi_chip_id, 1587 variant); 1588 else 1589 scnprintf(name, name_len, 1590 "bus=%s,qmi-board-id=%x", 1591 ath10k_bus_str(ar->hif.bus), 1592 ar->id.qmi_board_id); 1593 goto out; 1594 } 1595 1596 scnprintf(name, name_len, 1597 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x%s", 1598 ath10k_bus_str(ar->hif.bus), 1599 ar->id.vendor, ar->id.device, 1600 ar->id.subsystem_vendor, ar->id.subsystem_device, variant); 1601 out: 1602 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name); 1603 1604 return 0; 1605 } 1606 1607 static int ath10k_core_create_eboard_name(struct ath10k *ar, char *name, 1608 size_t name_len) 1609 { 1610 if (ar->id.bmi_ids_valid) { 1611 scnprintf(name, name_len, 1612 "bus=%s,bmi-chip-id=%d,bmi-eboard-id=%d", 1613 ath10k_bus_str(ar->hif.bus), 1614 ar->id.bmi_chip_id, 1615 ar->id.bmi_eboard_id); 1616 1617 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using eboard name '%s'\n", name); 1618 return 0; 1619 } 1620 /* Fallback if returned board id is zero */ 1621 return -1; 1622 } 1623 1624 int ath10k_core_fetch_board_file(struct ath10k *ar, int bd_ie_type) 1625 { 1626 char boardname[100], fallback_boardname1[100], fallback_boardname2[100]; 1627 int ret; 1628 1629 if (bd_ie_type == ATH10K_BD_IE_BOARD) { 1630 /* With variant and chip id */ 1631 ret = ath10k_core_create_board_name(ar, boardname, 1632 sizeof(boardname), true, 1633 true); 1634 if (ret) { 1635 ath10k_err(ar, "failed to create board name: %d", ret); 1636 return ret; 1637 } 1638 1639 /* Without variant and only chip-id */ 1640 ret = ath10k_core_create_board_name(ar, fallback_boardname1, 1641 sizeof(boardname), false, 1642 true); 1643 if (ret) { 1644 ath10k_err(ar, "failed to create 1st fallback board name: %d", 1645 ret); 1646 return ret; 1647 } 1648 1649 /* Without variant and without chip-id */ 1650 ret = ath10k_core_create_board_name(ar, fallback_boardname2, 1651 sizeof(boardname), false, 1652 false); 1653 if (ret) { 1654 ath10k_err(ar, "failed to create 2nd fallback board name: %d", 1655 ret); 1656 return ret; 1657 } 1658 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { 1659 ret = ath10k_core_create_eboard_name(ar, boardname, 1660 sizeof(boardname)); 1661 if (ret) { 1662 ath10k_err(ar, "fallback to eboard.bin since board id 0"); 1663 goto fallback; 1664 } 1665 } 1666 1667 ar->bd_api = 2; 1668 ret = ath10k_core_fetch_board_data_api_n(ar, boardname, 1669 fallback_boardname1, 1670 fallback_boardname2, 1671 ATH10K_BOARD_API2_FILE); 1672 if (!ret) 1673 goto success; 1674 1675 fallback: 1676 ar->bd_api = 1; 1677 ret = ath10k_core_fetch_board_data_api_1(ar, bd_ie_type); 1678 if (ret) { 1679 ath10k_err(ar, "failed to fetch board-2.bin or board.bin from %s\n", 1680 ar->hw_params.fw.dir); 1681 return ret; 1682 } 1683 1684 success: 1685 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api); 1686 return 0; 1687 } 1688 EXPORT_SYMBOL(ath10k_core_fetch_board_file); 1689 1690 static int ath10k_core_get_ext_board_id_from_otp(struct ath10k *ar) 1691 { 1692 u32 result, address; 1693 u8 ext_board_id; 1694 int ret; 1695 1696 address = ar->hw_params.patch_load_addr; 1697 1698 if (!ar->normal_mode_fw.fw_file.otp_data || 1699 !ar->normal_mode_fw.fw_file.otp_len) { 1700 ath10k_warn(ar, 1701 "failed to retrieve extended board id due to otp binary missing\n"); 1702 return -ENODATA; 1703 } 1704 1705 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1706 "boot upload otp to 0x%x len %zd for ext board id\n", 1707 address, ar->normal_mode_fw.fw_file.otp_len); 1708 1709 ret = ath10k_bmi_fast_download(ar, address, 1710 ar->normal_mode_fw.fw_file.otp_data, 1711 ar->normal_mode_fw.fw_file.otp_len); 1712 if (ret) { 1713 ath10k_err(ar, "could not write otp for ext board id check: %d\n", 1714 ret); 1715 return ret; 1716 } 1717 1718 ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EXT_BOARD_ID, &result); 1719 if (ret) { 1720 ath10k_err(ar, "could not execute otp for ext board id check: %d\n", 1721 ret); 1722 return ret; 1723 } 1724 1725 if (!result) { 1726 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1727 "ext board id does not exist in otp, ignore it\n"); 1728 return -EOPNOTSUPP; 1729 } 1730 1731 ext_board_id = result & ATH10K_BMI_EBOARD_ID_STATUS_MASK; 1732 1733 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1734 "boot get otp ext board id result 0x%08x ext_board_id %d\n", 1735 result, ext_board_id); 1736 1737 ar->id.bmi_eboard_id = ext_board_id; 1738 1739 return 0; 1740 } 1741 1742 static int ath10k_download_board_data(struct ath10k *ar, const void *data, 1743 size_t data_len) 1744 { 1745 u32 board_data_size = ar->hw_params.fw.board_size; 1746 u32 eboard_data_size = ar->hw_params.fw.ext_board_size; 1747 u32 board_address; 1748 u32 ext_board_address; 1749 int ret; 1750 1751 ret = ath10k_push_board_ext_data(ar, data, data_len); 1752 if (ret) { 1753 ath10k_err(ar, "could not push board ext data (%d)\n", ret); 1754 goto exit; 1755 } 1756 1757 ret = ath10k_bmi_read32(ar, hi_board_data, &board_address); 1758 if (ret) { 1759 ath10k_err(ar, "could not read board data addr (%d)\n", ret); 1760 goto exit; 1761 } 1762 1763 ret = ath10k_bmi_write_memory(ar, board_address, data, 1764 min_t(u32, board_data_size, 1765 data_len)); 1766 if (ret) { 1767 ath10k_err(ar, "could not write board data (%d)\n", ret); 1768 goto exit; 1769 } 1770 1771 ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1); 1772 if (ret) { 1773 ath10k_err(ar, "could not write board data bit (%d)\n", ret); 1774 goto exit; 1775 } 1776 1777 if (!ar->id.ext_bid_supported) 1778 goto exit; 1779 1780 /* Extended board data download */ 1781 ret = ath10k_core_get_ext_board_id_from_otp(ar); 1782 if (ret == -EOPNOTSUPP) { 1783 /* Not fetching ext_board_data if ext board id is 0 */ 1784 ath10k_dbg(ar, ATH10K_DBG_BOOT, "otp returned ext board id 0\n"); 1785 return 0; 1786 } else if (ret) { 1787 ath10k_err(ar, "failed to get extended board id: %d\n", ret); 1788 goto exit; 1789 } 1790 1791 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD_EXT); 1792 if (ret) 1793 goto exit; 1794 1795 if (ar->normal_mode_fw.ext_board_data) { 1796 ext_board_address = board_address + EXT_BOARD_ADDRESS_OFFSET; 1797 ath10k_dbg(ar, ATH10K_DBG_BOOT, 1798 "boot writing ext board data to addr 0x%x", 1799 ext_board_address); 1800 ret = ath10k_bmi_write_memory(ar, ext_board_address, 1801 ar->normal_mode_fw.ext_board_data, 1802 min_t(u32, eboard_data_size, data_len)); 1803 if (ret) 1804 ath10k_err(ar, "failed to write ext board data: %d\n", ret); 1805 } 1806 1807 exit: 1808 return ret; 1809 } 1810 1811 static int ath10k_download_and_run_otp(struct ath10k *ar) 1812 { 1813 u32 result, address = ar->hw_params.patch_load_addr; 1814 u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param; 1815 int ret; 1816 1817 ret = ath10k_download_board_data(ar, 1818 ar->running_fw->board_data, 1819 ar->running_fw->board_len); 1820 if (ret) { 1821 ath10k_err(ar, "failed to download board data: %d\n", ret); 1822 return ret; 1823 } 1824 1825 /* OTP is optional */ 1826 1827 if (!ar->running_fw->fw_file.otp_data || 1828 !ar->running_fw->fw_file.otp_len) { 1829 ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %p otp_len %zd)!\n", 1830 ar->running_fw->fw_file.otp_data, 1831 ar->running_fw->fw_file.otp_len); 1832 return 0; 1833 } 1834 1835 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n", 1836 address, ar->running_fw->fw_file.otp_len); 1837 1838 ret = ath10k_bmi_fast_download(ar, address, 1839 ar->running_fw->fw_file.otp_data, 1840 ar->running_fw->fw_file.otp_len); 1841 if (ret) { 1842 ath10k_err(ar, "could not write otp (%d)\n", ret); 1843 return ret; 1844 } 1845 1846 /* As of now pre-cal is valid for 10_4 variants */ 1847 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT || 1848 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE || 1849 ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM) 1850 bmi_otp_exe_param = BMI_PARAM_FLASH_SECTION_ALL; 1851 1852 ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result); 1853 if (ret) { 1854 ath10k_err(ar, "could not execute otp (%d)\n", ret); 1855 return ret; 1856 } 1857 1858 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result); 1859 1860 if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT, 1861 ar->running_fw->fw_file.fw_features)) && 1862 result != 0) { 1863 ath10k_err(ar, "otp calibration failed: %d", result); 1864 return -EINVAL; 1865 } 1866 1867 return 0; 1868 } 1869 1870 static int ath10k_download_cal_file(struct ath10k *ar, 1871 const struct firmware *file) 1872 { 1873 int ret; 1874 1875 if (!file) 1876 return -ENOENT; 1877 1878 if (IS_ERR(file)) 1879 return PTR_ERR(file); 1880 1881 ret = ath10k_download_board_data(ar, file->data, file->size); 1882 if (ret) { 1883 ath10k_err(ar, "failed to download cal_file data: %d\n", ret); 1884 return ret; 1885 } 1886 1887 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n"); 1888 1889 return 0; 1890 } 1891 1892 static int ath10k_download_cal_dt(struct ath10k *ar, const char *dt_name) 1893 { 1894 struct device_node *node; 1895 int data_len; 1896 void *data; 1897 int ret; 1898 1899 node = ar->dev->of_node; 1900 if (!node) 1901 /* Device Tree is optional, don't print any warnings if 1902 * there's no node for ath10k. 1903 */ 1904 return -ENOENT; 1905 1906 if (!of_get_property(node, dt_name, &data_len)) { 1907 /* The calibration data node is optional */ 1908 return -ENOENT; 1909 } 1910 1911 if (data_len != ar->hw_params.cal_data_len) { 1912 ath10k_warn(ar, "invalid calibration data length in DT: %d\n", 1913 data_len); 1914 ret = -EMSGSIZE; 1915 goto out; 1916 } 1917 1918 data = kmalloc(data_len, GFP_KERNEL); 1919 if (!data) { 1920 ret = -ENOMEM; 1921 goto out; 1922 } 1923 1924 ret = of_property_read_u8_array(node, dt_name, data, data_len); 1925 if (ret) { 1926 ath10k_warn(ar, "failed to read calibration data from DT: %d\n", 1927 ret); 1928 goto out_free; 1929 } 1930 1931 ret = ath10k_download_board_data(ar, data, data_len); 1932 if (ret) { 1933 ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n", 1934 ret); 1935 goto out_free; 1936 } 1937 1938 ret = 0; 1939 1940 out_free: 1941 kfree(data); 1942 1943 out: 1944 return ret; 1945 } 1946 1947 static int ath10k_download_cal_eeprom(struct ath10k *ar) 1948 { 1949 size_t data_len; 1950 void *data = NULL; 1951 int ret; 1952 1953 ret = ath10k_hif_fetch_cal_eeprom(ar, &data, &data_len); 1954 if (ret) { 1955 if (ret != -EOPNOTSUPP) 1956 ath10k_warn(ar, "failed to read calibration data from EEPROM: %d\n", 1957 ret); 1958 goto out_free; 1959 } 1960 1961 ret = ath10k_download_board_data(ar, data, data_len); 1962 if (ret) { 1963 ath10k_warn(ar, "failed to download calibration data from EEPROM: %d\n", 1964 ret); 1965 goto out_free; 1966 } 1967 1968 ret = 0; 1969 1970 out_free: 1971 kfree(data); 1972 1973 return ret; 1974 } 1975 1976 static int ath10k_download_cal_nvmem(struct ath10k *ar, const char *cell_name) 1977 { 1978 struct nvmem_cell *cell; 1979 void *buf; 1980 size_t len; 1981 int ret; 1982 1983 cell = devm_nvmem_cell_get(ar->dev, cell_name); 1984 if (IS_ERR(cell)) { 1985 ret = PTR_ERR(cell); 1986 return ret; 1987 } 1988 1989 buf = nvmem_cell_read(cell, &len); 1990 if (IS_ERR(buf)) 1991 return PTR_ERR(buf); 1992 1993 if (ar->hw_params.cal_data_len != len) { 1994 kfree(buf); 1995 ath10k_warn(ar, "invalid calibration data length in nvmem-cell '%s': %zu != %u\n", 1996 cell_name, len, ar->hw_params.cal_data_len); 1997 return -EMSGSIZE; 1998 } 1999 2000 ret = ath10k_download_board_data(ar, buf, len); 2001 kfree(buf); 2002 if (ret) 2003 ath10k_warn(ar, "failed to download calibration data from nvmem-cell '%s': %d\n", 2004 cell_name, ret); 2005 2006 return ret; 2007 } 2008 2009 int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name, 2010 struct ath10k_fw_file *fw_file) 2011 { 2012 size_t magic_len, len, ie_len; 2013 int ie_id, i, index, bit, ret; 2014 struct ath10k_fw_ie *hdr; 2015 const u8 *data; 2016 __le32 *timestamp, *version; 2017 2018 /* first fetch the firmware file (firmware-*.bin) */ 2019 fw_file->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, 2020 name); 2021 if (IS_ERR(fw_file->firmware)) 2022 return PTR_ERR(fw_file->firmware); 2023 2024 data = fw_file->firmware->data; 2025 len = fw_file->firmware->size; 2026 2027 /* magic also includes the null byte, check that as well */ 2028 magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1; 2029 2030 if (len < magic_len) { 2031 ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n", 2032 ar->hw_params.fw.dir, name, len); 2033 ret = -EINVAL; 2034 goto err; 2035 } 2036 2037 if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) { 2038 ath10k_err(ar, "invalid firmware magic\n"); 2039 ret = -EINVAL; 2040 goto err; 2041 } 2042 2043 /* jump over the padding */ 2044 magic_len = ALIGN(magic_len, 4); 2045 2046 len -= magic_len; 2047 data += magic_len; 2048 2049 /* loop elements */ 2050 while (len > sizeof(struct ath10k_fw_ie)) { 2051 hdr = (struct ath10k_fw_ie *)data; 2052 2053 ie_id = le32_to_cpu(hdr->id); 2054 ie_len = le32_to_cpu(hdr->len); 2055 2056 len -= sizeof(*hdr); 2057 data += sizeof(*hdr); 2058 2059 if (len < ie_len) { 2060 ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n", 2061 ie_id, len, ie_len); 2062 ret = -EINVAL; 2063 goto err; 2064 } 2065 2066 switch (ie_id) { 2067 case ATH10K_FW_IE_FW_VERSION: 2068 if (ie_len > sizeof(fw_file->fw_version) - 1) 2069 break; 2070 2071 memcpy(fw_file->fw_version, data, ie_len); 2072 fw_file->fw_version[ie_len] = '\0'; 2073 2074 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2075 "found fw version %s\n", 2076 fw_file->fw_version); 2077 break; 2078 case ATH10K_FW_IE_TIMESTAMP: 2079 if (ie_len != sizeof(u32)) 2080 break; 2081 2082 timestamp = (__le32 *)data; 2083 2084 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n", 2085 le32_to_cpup(timestamp)); 2086 break; 2087 case ATH10K_FW_IE_FEATURES: 2088 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2089 "found firmware features ie (%zd B)\n", 2090 ie_len); 2091 2092 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { 2093 index = i / 8; 2094 bit = i % 8; 2095 2096 if (index == ie_len) 2097 break; 2098 2099 if (data[index] & (1 << bit)) { 2100 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2101 "Enabling feature bit: %i\n", 2102 i); 2103 __set_bit(i, fw_file->fw_features); 2104 } 2105 } 2106 2107 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "", 2108 fw_file->fw_features, 2109 sizeof(fw_file->fw_features)); 2110 break; 2111 case ATH10K_FW_IE_FW_IMAGE: 2112 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2113 "found fw image ie (%zd B)\n", 2114 ie_len); 2115 2116 fw_file->firmware_data = data; 2117 fw_file->firmware_len = ie_len; 2118 2119 break; 2120 case ATH10K_FW_IE_OTP_IMAGE: 2121 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2122 "found otp image ie (%zd B)\n", 2123 ie_len); 2124 2125 fw_file->otp_data = data; 2126 fw_file->otp_len = ie_len; 2127 2128 break; 2129 case ATH10K_FW_IE_WMI_OP_VERSION: 2130 if (ie_len != sizeof(u32)) 2131 break; 2132 2133 version = (__le32 *)data; 2134 2135 fw_file->wmi_op_version = le32_to_cpup(version); 2136 2137 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n", 2138 fw_file->wmi_op_version); 2139 break; 2140 case ATH10K_FW_IE_HTT_OP_VERSION: 2141 if (ie_len != sizeof(u32)) 2142 break; 2143 2144 version = (__le32 *)data; 2145 2146 fw_file->htt_op_version = le32_to_cpup(version); 2147 2148 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n", 2149 fw_file->htt_op_version); 2150 break; 2151 case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE: 2152 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2153 "found fw code swap image ie (%zd B)\n", 2154 ie_len); 2155 fw_file->codeswap_data = data; 2156 fw_file->codeswap_len = ie_len; 2157 break; 2158 default: 2159 ath10k_warn(ar, "Unknown FW IE: %u\n", 2160 le32_to_cpu(hdr->id)); 2161 break; 2162 } 2163 2164 /* jump over the padding */ 2165 ie_len = ALIGN(ie_len, 4); 2166 2167 len -= ie_len; 2168 data += ie_len; 2169 } 2170 2171 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, fw_file->fw_features) && 2172 (!fw_file->firmware_data || !fw_file->firmware_len)) { 2173 ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n", 2174 ar->hw_params.fw.dir, name); 2175 ret = -ENOMEDIUM; 2176 goto err; 2177 } 2178 2179 return 0; 2180 2181 err: 2182 ath10k_core_free_firmware_files(ar); 2183 return ret; 2184 } 2185 2186 static void ath10k_core_get_fw_name(struct ath10k *ar, char *fw_name, 2187 size_t fw_name_len, int fw_api) 2188 { 2189 switch (ar->hif.bus) { 2190 case ATH10K_BUS_SDIO: 2191 case ATH10K_BUS_USB: 2192 scnprintf(fw_name, fw_name_len, "%s-%s-%d.bin", 2193 ATH10K_FW_FILE_BASE, ath10k_bus_str(ar->hif.bus), 2194 fw_api); 2195 break; 2196 case ATH10K_BUS_PCI: 2197 case ATH10K_BUS_AHB: 2198 case ATH10K_BUS_SNOC: 2199 scnprintf(fw_name, fw_name_len, "%s-%d.bin", 2200 ATH10K_FW_FILE_BASE, fw_api); 2201 break; 2202 } 2203 } 2204 2205 static int ath10k_core_fetch_firmware_files(struct ath10k *ar) 2206 { 2207 int ret, i; 2208 char fw_name[100]; 2209 2210 /* calibration file is optional, don't check for any errors */ 2211 ath10k_fetch_cal_file(ar); 2212 2213 for (i = ATH10K_FW_API_MAX; i >= ATH10K_FW_API_MIN; i--) { 2214 ar->fw_api = i; 2215 ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", 2216 ar->fw_api); 2217 2218 ath10k_core_get_fw_name(ar, fw_name, sizeof(fw_name), ar->fw_api); 2219 ret = ath10k_core_fetch_firmware_api_n(ar, fw_name, 2220 &ar->normal_mode_fw.fw_file); 2221 if (!ret) 2222 goto success; 2223 } 2224 2225 /* we end up here if we couldn't fetch any firmware */ 2226 2227 ath10k_err(ar, "Failed to find firmware-N.bin (N between %d and %d) from %s: %d", 2228 ATH10K_FW_API_MIN, ATH10K_FW_API_MAX, ar->hw_params.fw.dir, 2229 ret); 2230 2231 return ret; 2232 2233 success: 2234 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api); 2235 2236 return 0; 2237 } 2238 2239 static int ath10k_core_pre_cal_download(struct ath10k *ar) 2240 { 2241 int ret; 2242 2243 ret = ath10k_download_cal_nvmem(ar, "pre-calibration"); 2244 if (ret == 0) { 2245 ar->cal_mode = ATH10K_PRE_CAL_MODE_NVMEM; 2246 goto success; 2247 } else if (ret == -EPROBE_DEFER) { 2248 return ret; 2249 } 2250 2251 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2252 "boot did not find a pre-calibration nvmem-cell, try file next: %d\n", 2253 ret); 2254 2255 ret = ath10k_download_cal_file(ar, ar->pre_cal_file); 2256 if (ret == 0) { 2257 ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE; 2258 goto success; 2259 } 2260 2261 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2262 "boot did not find a pre calibration file, try DT next: %d\n", 2263 ret); 2264 2265 ret = ath10k_download_cal_dt(ar, "qcom,pre-calibration-data"); 2266 if (ret == -ENOENT) 2267 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-pre-calibration-data"); 2268 if (ret) { 2269 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2270 "unable to load pre cal data from DT: %d\n", ret); 2271 return ret; 2272 } 2273 ar->cal_mode = ATH10K_PRE_CAL_MODE_DT; 2274 2275 success: 2276 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", 2277 ath10k_cal_mode_str(ar->cal_mode)); 2278 2279 return 0; 2280 } 2281 2282 static int ath10k_core_pre_cal_config(struct ath10k *ar) 2283 { 2284 int ret; 2285 2286 ret = ath10k_core_pre_cal_download(ar); 2287 if (ret) { 2288 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2289 "failed to load pre cal data: %d\n", ret); 2290 return ret; 2291 } 2292 2293 ret = ath10k_core_get_board_id_from_otp(ar); 2294 if (ret) { 2295 ath10k_err(ar, "failed to get board id: %d\n", ret); 2296 return ret; 2297 } 2298 2299 ret = ath10k_download_and_run_otp(ar); 2300 if (ret) { 2301 ath10k_err(ar, "failed to run otp: %d\n", ret); 2302 return ret; 2303 } 2304 2305 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2306 "pre cal configuration done successfully\n"); 2307 2308 return 0; 2309 } 2310 2311 static int ath10k_download_cal_data(struct ath10k *ar) 2312 { 2313 int ret; 2314 2315 ret = ath10k_core_pre_cal_config(ar); 2316 if (ret == 0) 2317 return 0; 2318 2319 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2320 "pre cal download procedure failed, try cal file: %d\n", 2321 ret); 2322 2323 ret = ath10k_download_cal_nvmem(ar, "calibration"); 2324 if (ret == 0) { 2325 ar->cal_mode = ATH10K_CAL_MODE_NVMEM; 2326 goto done; 2327 } else if (ret == -EPROBE_DEFER) { 2328 return ret; 2329 } 2330 2331 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2332 "boot did not find a calibration nvmem-cell, try file next: %d\n", 2333 ret); 2334 2335 ret = ath10k_download_cal_file(ar, ar->cal_file); 2336 if (ret == 0) { 2337 ar->cal_mode = ATH10K_CAL_MODE_FILE; 2338 goto done; 2339 } 2340 2341 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2342 "boot did not find a calibration file, try DT next: %d\n", 2343 ret); 2344 2345 ret = ath10k_download_cal_dt(ar, "qcom,calibration-data"); 2346 if (ret == -ENOENT) 2347 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-calibration-data"); 2348 if (ret == 0) { 2349 ar->cal_mode = ATH10K_CAL_MODE_DT; 2350 goto done; 2351 } 2352 2353 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2354 "boot did not find DT entry, try target EEPROM next: %d\n", 2355 ret); 2356 2357 ret = ath10k_download_cal_eeprom(ar); 2358 if (ret == 0) { 2359 ar->cal_mode = ATH10K_CAL_MODE_EEPROM; 2360 goto done; 2361 } 2362 2363 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2364 "boot did not find target EEPROM entry, try OTP next: %d\n", 2365 ret); 2366 2367 ret = ath10k_download_and_run_otp(ar); 2368 if (ret) { 2369 ath10k_err(ar, "failed to run otp: %d\n", ret); 2370 return ret; 2371 } 2372 2373 ar->cal_mode = ATH10K_CAL_MODE_OTP; 2374 2375 done: 2376 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", 2377 ath10k_cal_mode_str(ar->cal_mode)); 2378 return 0; 2379 } 2380 2381 static void ath10k_core_fetch_btcoex_dt(struct ath10k *ar) 2382 { 2383 struct device_node *node; 2384 u8 coex_support = 0; 2385 int ret; 2386 2387 node = ar->dev->of_node; 2388 if (!node) 2389 goto out; 2390 2391 ret = of_property_read_u8(node, "qcom,coexist-support", &coex_support); 2392 if (ret) { 2393 ar->coex_support = true; 2394 goto out; 2395 } 2396 2397 if (coex_support) { 2398 ar->coex_support = true; 2399 } else { 2400 ar->coex_support = false; 2401 ar->coex_gpio_pin = -1; 2402 goto out; 2403 } 2404 2405 ret = of_property_read_u32(node, "qcom,coexist-gpio-pin", 2406 &ar->coex_gpio_pin); 2407 if (ret) 2408 ar->coex_gpio_pin = -1; 2409 2410 out: 2411 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot coex_support %d coex_gpio_pin %d\n", 2412 ar->coex_support, ar->coex_gpio_pin); 2413 } 2414 2415 static int ath10k_init_uart(struct ath10k *ar) 2416 { 2417 int ret; 2418 2419 /* 2420 * Explicitly setting UART prints to zero as target turns it on 2421 * based on scratch registers. 2422 */ 2423 ret = ath10k_bmi_write32(ar, hi_serial_enable, 0); 2424 if (ret) { 2425 ath10k_warn(ar, "could not disable UART prints (%d)\n", ret); 2426 return ret; 2427 } 2428 2429 if (!uart_print) { 2430 if (ar->hw_params.uart_pin_workaround) { 2431 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, 2432 ar->hw_params.uart_pin); 2433 if (ret) { 2434 ath10k_warn(ar, "failed to set UART TX pin: %d", 2435 ret); 2436 return ret; 2437 } 2438 } 2439 2440 return 0; 2441 } 2442 2443 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin); 2444 if (ret) { 2445 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); 2446 return ret; 2447 } 2448 2449 ret = ath10k_bmi_write32(ar, hi_serial_enable, 1); 2450 if (ret) { 2451 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); 2452 return ret; 2453 } 2454 2455 /* Set the UART baud rate to 19200. */ 2456 ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200); 2457 if (ret) { 2458 ath10k_warn(ar, "could not set the baud rate (%d)\n", ret); 2459 return ret; 2460 } 2461 2462 ath10k_info(ar, "UART prints enabled\n"); 2463 return 0; 2464 } 2465 2466 static int ath10k_init_hw_params(struct ath10k *ar) 2467 { 2468 const struct ath10k_hw_params *hw_params; 2469 int i; 2470 2471 for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) { 2472 hw_params = &ath10k_hw_params_list[i]; 2473 2474 if (hw_params->bus == ar->hif.bus && 2475 hw_params->id == ar->target_version && 2476 hw_params->dev_id == ar->dev_id) 2477 break; 2478 } 2479 2480 if (i == ARRAY_SIZE(ath10k_hw_params_list)) { 2481 ath10k_err(ar, "Unsupported hardware version: 0x%x\n", 2482 ar->target_version); 2483 return -EINVAL; 2484 } 2485 2486 ar->hw_params = *hw_params; 2487 2488 ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n", 2489 ar->hw_params.name, ar->target_version); 2490 2491 return 0; 2492 } 2493 2494 static void ath10k_core_recovery_check_work(struct work_struct *work) 2495 { 2496 struct ath10k *ar = container_of(work, struct ath10k, recovery_check_work); 2497 long time_left; 2498 2499 /* Sometimes the recovery will fail and then the next all recovery fail, 2500 * so avoid infinite recovery. 2501 */ 2502 if (atomic_read(&ar->fail_cont_count) >= ATH10K_RECOVERY_MAX_FAIL_COUNT) { 2503 ath10k_err(ar, "consecutive fail %d times, will shutdown driver!", 2504 atomic_read(&ar->fail_cont_count)); 2505 ar->state = ATH10K_STATE_WEDGED; 2506 return; 2507 } 2508 2509 ath10k_dbg(ar, ATH10K_DBG_BOOT, "total recovery count: %d", ++ar->recovery_count); 2510 2511 if (atomic_read(&ar->pending_recovery)) { 2512 /* Sometimes it happened another recovery work before the previous one 2513 * completed, then the second recovery work will destroy the previous 2514 * one, thus below is to avoid that. 2515 */ 2516 time_left = wait_for_completion_timeout(&ar->driver_recovery, 2517 ATH10K_RECOVERY_TIMEOUT_HZ); 2518 if (time_left) { 2519 ath10k_warn(ar, "previous recovery succeeded, skip this!\n"); 2520 return; 2521 } 2522 2523 /* Record the continuous recovery fail count when recovery failed. */ 2524 atomic_inc(&ar->fail_cont_count); 2525 2526 /* Avoid having multiple recoveries at the same time. */ 2527 return; 2528 } 2529 2530 atomic_inc(&ar->pending_recovery); 2531 queue_work(ar->workqueue, &ar->restart_work); 2532 } 2533 2534 void ath10k_core_start_recovery(struct ath10k *ar) 2535 { 2536 /* Use workqueue_aux to avoid blocking recovery tracking */ 2537 queue_work(ar->workqueue_aux, &ar->recovery_check_work); 2538 } 2539 EXPORT_SYMBOL(ath10k_core_start_recovery); 2540 2541 void ath10k_core_napi_enable(struct ath10k *ar) 2542 { 2543 lockdep_assert_held(&ar->conf_mutex); 2544 2545 if (test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags)) 2546 return; 2547 2548 napi_enable(&ar->napi); 2549 set_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags); 2550 } 2551 EXPORT_SYMBOL(ath10k_core_napi_enable); 2552 2553 void ath10k_core_napi_sync_disable(struct ath10k *ar) 2554 { 2555 lockdep_assert_held(&ar->conf_mutex); 2556 2557 if (!test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags)) 2558 return; 2559 2560 napi_synchronize(&ar->napi); 2561 napi_disable(&ar->napi); 2562 clear_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags); 2563 } 2564 EXPORT_SYMBOL(ath10k_core_napi_sync_disable); 2565 2566 static void ath10k_core_restart(struct work_struct *work) 2567 { 2568 struct ath10k *ar = container_of(work, struct ath10k, restart_work); 2569 int ret; 2570 2571 reinit_completion(&ar->driver_recovery); 2572 2573 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); 2574 2575 /* Place a barrier to make sure the compiler doesn't reorder 2576 * CRASH_FLUSH and calling other functions. 2577 */ 2578 barrier(); 2579 2580 ieee80211_stop_queues(ar->hw); 2581 ath10k_drain_tx(ar); 2582 complete(&ar->scan.started); 2583 complete(&ar->scan.completed); 2584 complete(&ar->scan.on_channel); 2585 complete(&ar->offchan_tx_completed); 2586 complete(&ar->install_key_done); 2587 complete(&ar->vdev_setup_done); 2588 complete(&ar->vdev_delete_done); 2589 complete(&ar->thermal.wmi_sync); 2590 complete(&ar->bss_survey_done); 2591 wake_up(&ar->htt.empty_tx_wq); 2592 wake_up(&ar->wmi.tx_credits_wq); 2593 wake_up(&ar->peer_mapping_wq); 2594 2595 /* TODO: We can have one instance of cancelling coverage_class_work by 2596 * moving it to ath10k_halt(), so that both stop() and restart() would 2597 * call that but it takes conf_mutex() and if we call cancel_work_sync() 2598 * with conf_mutex it will deadlock. 2599 */ 2600 cancel_work_sync(&ar->set_coverage_class_work); 2601 2602 mutex_lock(&ar->conf_mutex); 2603 2604 switch (ar->state) { 2605 case ATH10K_STATE_ON: 2606 ar->state = ATH10K_STATE_RESTARTING; 2607 ath10k_halt(ar); 2608 ath10k_scan_finish(ar); 2609 ieee80211_restart_hw(ar->hw); 2610 break; 2611 case ATH10K_STATE_OFF: 2612 /* this can happen if driver is being unloaded 2613 * or if the crash happens during FW probing 2614 */ 2615 ath10k_warn(ar, "cannot restart a device that hasn't been started\n"); 2616 break; 2617 case ATH10K_STATE_RESTARTING: 2618 /* hw restart might be requested from multiple places */ 2619 break; 2620 case ATH10K_STATE_RESTARTED: 2621 ar->state = ATH10K_STATE_WEDGED; 2622 fallthrough; 2623 case ATH10K_STATE_WEDGED: 2624 ath10k_warn(ar, "device is wedged, will not restart\n"); 2625 break; 2626 case ATH10K_STATE_UTF: 2627 ath10k_warn(ar, "firmware restart in UTF mode not supported\n"); 2628 break; 2629 } 2630 2631 mutex_unlock(&ar->conf_mutex); 2632 2633 ret = ath10k_coredump_submit(ar); 2634 if (ret) 2635 ath10k_warn(ar, "failed to send firmware crash dump via devcoredump: %d", 2636 ret); 2637 } 2638 2639 static void ath10k_core_set_coverage_class_work(struct work_struct *work) 2640 { 2641 struct ath10k *ar = container_of(work, struct ath10k, 2642 set_coverage_class_work); 2643 2644 if (ar->hw_params.hw_ops->set_coverage_class) 2645 ar->hw_params.hw_ops->set_coverage_class(ar, -1, -1); 2646 } 2647 2648 static int ath10k_core_init_firmware_features(struct ath10k *ar) 2649 { 2650 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file; 2651 int max_num_peers; 2652 2653 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, fw_file->fw_features) && 2654 !test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) { 2655 ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well"); 2656 return -EINVAL; 2657 } 2658 2659 if (fw_file->wmi_op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) { 2660 ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n", 2661 ATH10K_FW_WMI_OP_VERSION_MAX, fw_file->wmi_op_version); 2662 return -EINVAL; 2663 } 2664 2665 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI; 2666 switch (ath10k_cryptmode_param) { 2667 case ATH10K_CRYPT_MODE_HW: 2668 clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2669 clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags); 2670 break; 2671 case ATH10K_CRYPT_MODE_SW: 2672 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, 2673 fw_file->fw_features)) { 2674 ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware"); 2675 return -EINVAL; 2676 } 2677 2678 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2679 set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags); 2680 break; 2681 default: 2682 ath10k_info(ar, "invalid cryptmode: %d\n", 2683 ath10k_cryptmode_param); 2684 return -EINVAL; 2685 } 2686 2687 ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT; 2688 ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT; 2689 2690 if (ath10k_frame_mode == ATH10K_HW_TXRX_RAW) { 2691 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, 2692 fw_file->fw_features)) { 2693 ath10k_err(ar, "rawmode = 1 requires support from firmware"); 2694 return -EINVAL; 2695 } 2696 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); 2697 } 2698 2699 if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 2700 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW; 2701 2702 /* Workaround: 2703 * 2704 * Firmware A-MSDU aggregation breaks with RAW Tx encap mode 2705 * and causes enormous performance issues (malformed frames, 2706 * etc). 2707 * 2708 * Disabling A-MSDU makes RAW mode stable with heavy traffic 2709 * albeit a bit slower compared to regular operation. 2710 */ 2711 ar->htt.max_num_amsdu = 1; 2712 } 2713 2714 /* Backwards compatibility for firmwares without 2715 * ATH10K_FW_IE_WMI_OP_VERSION. 2716 */ 2717 if (fw_file->wmi_op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) { 2718 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) { 2719 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, 2720 fw_file->fw_features)) 2721 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_2; 2722 else 2723 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1; 2724 } else { 2725 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_MAIN; 2726 } 2727 } 2728 2729 switch (fw_file->wmi_op_version) { 2730 case ATH10K_FW_WMI_OP_VERSION_MAIN: 2731 max_num_peers = TARGET_NUM_PEERS; 2732 ar->max_num_stations = TARGET_NUM_STATIONS; 2733 ar->max_num_vdevs = TARGET_NUM_VDEVS; 2734 ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC; 2735 ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV | 2736 WMI_STAT_PEER; 2737 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2738 break; 2739 case ATH10K_FW_WMI_OP_VERSION_10_1: 2740 case ATH10K_FW_WMI_OP_VERSION_10_2: 2741 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2742 if (ath10k_peer_stats_enabled(ar)) { 2743 max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS; 2744 ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS; 2745 } else { 2746 max_num_peers = TARGET_10X_NUM_PEERS; 2747 ar->max_num_stations = TARGET_10X_NUM_STATIONS; 2748 } 2749 ar->max_num_vdevs = TARGET_10X_NUM_VDEVS; 2750 ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC; 2751 ar->fw_stats_req_mask = WMI_STAT_PEER; 2752 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2753 break; 2754 case ATH10K_FW_WMI_OP_VERSION_TLV: 2755 max_num_peers = TARGET_TLV_NUM_PEERS; 2756 ar->max_num_stations = TARGET_TLV_NUM_STATIONS; 2757 ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS; 2758 ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS; 2759 if (ar->hif.bus == ATH10K_BUS_SDIO) 2760 ar->htt.max_num_pending_tx = 2761 TARGET_TLV_NUM_MSDU_DESC_HL; 2762 else 2763 ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC; 2764 ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS; 2765 ar->fw_stats_req_mask = WMI_TLV_STAT_PDEV | WMI_TLV_STAT_VDEV | 2766 WMI_TLV_STAT_PEER | WMI_TLV_STAT_PEER_EXTD; 2767 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; 2768 ar->wmi.mgmt_max_num_pending_tx = TARGET_TLV_MGMT_NUM_MSDU_DESC; 2769 break; 2770 case ATH10K_FW_WMI_OP_VERSION_10_4: 2771 max_num_peers = TARGET_10_4_NUM_PEERS; 2772 ar->max_num_stations = TARGET_10_4_NUM_STATIONS; 2773 ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS; 2774 ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS; 2775 ar->num_tids = TARGET_10_4_TGT_NUM_TIDS; 2776 ar->fw_stats_req_mask = WMI_10_4_STAT_PEER | 2777 WMI_10_4_STAT_PEER_EXTD | 2778 WMI_10_4_STAT_VDEV_EXTD; 2779 ar->max_spatial_stream = ar->hw_params.max_spatial_stream; 2780 ar->max_num_tdls_vdevs = TARGET_10_4_NUM_TDLS_VDEVS; 2781 2782 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 2783 fw_file->fw_features)) 2784 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC_PFC; 2785 else 2786 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC; 2787 break; 2788 case ATH10K_FW_WMI_OP_VERSION_UNSET: 2789 case ATH10K_FW_WMI_OP_VERSION_MAX: 2790 default: 2791 WARN_ON(1); 2792 return -EINVAL; 2793 } 2794 2795 if (ar->hw_params.num_peers) 2796 ar->max_num_peers = ar->hw_params.num_peers; 2797 else 2798 ar->max_num_peers = max_num_peers; 2799 2800 /* Backwards compatibility for firmwares without 2801 * ATH10K_FW_IE_HTT_OP_VERSION. 2802 */ 2803 if (fw_file->htt_op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) { 2804 switch (fw_file->wmi_op_version) { 2805 case ATH10K_FW_WMI_OP_VERSION_MAIN: 2806 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_MAIN; 2807 break; 2808 case ATH10K_FW_WMI_OP_VERSION_10_1: 2809 case ATH10K_FW_WMI_OP_VERSION_10_2: 2810 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2811 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1; 2812 break; 2813 case ATH10K_FW_WMI_OP_VERSION_TLV: 2814 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV; 2815 break; 2816 case ATH10K_FW_WMI_OP_VERSION_10_4: 2817 case ATH10K_FW_WMI_OP_VERSION_UNSET: 2818 case ATH10K_FW_WMI_OP_VERSION_MAX: 2819 ath10k_err(ar, "htt op version not found from fw meta data"); 2820 return -EINVAL; 2821 } 2822 } 2823 2824 return 0; 2825 } 2826 2827 static int ath10k_core_reset_rx_filter(struct ath10k *ar) 2828 { 2829 int ret; 2830 int vdev_id; 2831 int vdev_type; 2832 int vdev_subtype; 2833 const u8 *vdev_addr; 2834 2835 vdev_id = 0; 2836 vdev_type = WMI_VDEV_TYPE_STA; 2837 vdev_subtype = ath10k_wmi_get_vdev_subtype(ar, WMI_VDEV_SUBTYPE_NONE); 2838 vdev_addr = ar->mac_addr; 2839 2840 ret = ath10k_wmi_vdev_create(ar, vdev_id, vdev_type, vdev_subtype, 2841 vdev_addr); 2842 if (ret) { 2843 ath10k_err(ar, "failed to create dummy vdev: %d\n", ret); 2844 return ret; 2845 } 2846 2847 ret = ath10k_wmi_vdev_delete(ar, vdev_id); 2848 if (ret) { 2849 ath10k_err(ar, "failed to delete dummy vdev: %d\n", ret); 2850 return ret; 2851 } 2852 2853 /* WMI and HTT may use separate HIF pipes and are not guaranteed to be 2854 * serialized properly implicitly. 2855 * 2856 * Moreover (most) WMI commands have no explicit acknowledges. It is 2857 * possible to infer it implicitly by poking firmware with echo 2858 * command - getting a reply means all preceding comments have been 2859 * (mostly) processed. 2860 * 2861 * In case of vdev create/delete this is sufficient. 2862 * 2863 * Without this it's possible to end up with a race when HTT Rx ring is 2864 * started before vdev create/delete hack is complete allowing a short 2865 * window of opportunity to receive (and Tx ACK) a bunch of frames. 2866 */ 2867 ret = ath10k_wmi_barrier(ar); 2868 if (ret) { 2869 ath10k_err(ar, "failed to ping firmware: %d\n", ret); 2870 return ret; 2871 } 2872 2873 return 0; 2874 } 2875 2876 static int ath10k_core_compat_services(struct ath10k *ar) 2877 { 2878 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file; 2879 2880 /* all 10.x firmware versions support thermal throttling but don't 2881 * advertise the support via service flags so we have to hardcode 2882 * it here 2883 */ 2884 switch (fw_file->wmi_op_version) { 2885 case ATH10K_FW_WMI_OP_VERSION_10_1: 2886 case ATH10K_FW_WMI_OP_VERSION_10_2: 2887 case ATH10K_FW_WMI_OP_VERSION_10_2_4: 2888 case ATH10K_FW_WMI_OP_VERSION_10_4: 2889 set_bit(WMI_SERVICE_THERM_THROT, ar->wmi.svc_map); 2890 break; 2891 default: 2892 break; 2893 } 2894 2895 return 0; 2896 } 2897 2898 #define TGT_IRAM_READ_PER_ITR (8 * 1024) 2899 2900 static int ath10k_core_copy_target_iram(struct ath10k *ar) 2901 { 2902 const struct ath10k_hw_mem_layout *hw_mem; 2903 const struct ath10k_mem_region *tmp, *mem_region = NULL; 2904 dma_addr_t paddr; 2905 void *vaddr = NULL; 2906 u8 num_read_itr; 2907 int i, ret; 2908 u32 len, remaining_len; 2909 2910 /* copy target iram feature must work also when 2911 * ATH10K_FW_CRASH_DUMP_RAM_DATA is disabled, so 2912 * _ath10k_coredump_get_mem_layout() to accomplist that 2913 */ 2914 hw_mem = _ath10k_coredump_get_mem_layout(ar); 2915 if (!hw_mem) 2916 /* if CONFIG_DEV_COREDUMP is disabled we get NULL, then 2917 * just silently disable the feature by doing nothing 2918 */ 2919 return 0; 2920 2921 for (i = 0; i < hw_mem->region_table.size; i++) { 2922 tmp = &hw_mem->region_table.regions[i]; 2923 if (tmp->type == ATH10K_MEM_REGION_TYPE_REG) { 2924 mem_region = tmp; 2925 break; 2926 } 2927 } 2928 2929 if (!mem_region) 2930 return -ENOMEM; 2931 2932 for (i = 0; i < ar->wmi.num_mem_chunks; i++) { 2933 if (ar->wmi.mem_chunks[i].req_id == 2934 WMI_IRAM_RECOVERY_HOST_MEM_REQ_ID) { 2935 vaddr = ar->wmi.mem_chunks[i].vaddr; 2936 len = ar->wmi.mem_chunks[i].len; 2937 break; 2938 } 2939 } 2940 2941 if (!vaddr || !len) { 2942 ath10k_warn(ar, "No allocated memory for IRAM back up"); 2943 return -ENOMEM; 2944 } 2945 2946 len = (len < mem_region->len) ? len : mem_region->len; 2947 paddr = mem_region->start; 2948 num_read_itr = len / TGT_IRAM_READ_PER_ITR; 2949 remaining_len = len % TGT_IRAM_READ_PER_ITR; 2950 for (i = 0; i < num_read_itr; i++) { 2951 ret = ath10k_hif_diag_read(ar, paddr, vaddr, 2952 TGT_IRAM_READ_PER_ITR); 2953 if (ret) { 2954 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d", 2955 ret); 2956 return ret; 2957 } 2958 2959 paddr += TGT_IRAM_READ_PER_ITR; 2960 vaddr += TGT_IRAM_READ_PER_ITR; 2961 } 2962 2963 if (remaining_len) { 2964 ret = ath10k_hif_diag_read(ar, paddr, vaddr, remaining_len); 2965 if (ret) { 2966 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d", 2967 ret); 2968 return ret; 2969 } 2970 } 2971 2972 ath10k_dbg(ar, ATH10K_DBG_BOOT, "target IRAM back up completed\n"); 2973 2974 return 0; 2975 } 2976 2977 int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode, 2978 const struct ath10k_fw_components *fw) 2979 { 2980 int status; 2981 u32 val; 2982 2983 lockdep_assert_held(&ar->conf_mutex); 2984 2985 clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); 2986 2987 ar->running_fw = fw; 2988 2989 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 2990 ar->running_fw->fw_file.fw_features)) { 2991 ath10k_bmi_start(ar); 2992 2993 /* Enable hardware clock to speed up firmware download */ 2994 if (ar->hw_params.hw_ops->enable_pll_clk) { 2995 status = ar->hw_params.hw_ops->enable_pll_clk(ar); 2996 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot enable pll ret %d\n", 2997 status); 2998 } 2999 3000 if (ath10k_init_configure_target(ar)) { 3001 status = -EINVAL; 3002 goto err; 3003 } 3004 3005 status = ath10k_download_cal_data(ar); 3006 if (status) 3007 goto err; 3008 3009 /* Some of qca988x solutions are having global reset issue 3010 * during target initialization. Bypassing PLL setting before 3011 * downloading firmware and letting the SoC run on REF_CLK is 3012 * fixing the problem. Corresponding firmware change is also 3013 * needed to set the clock source once the target is 3014 * initialized. 3015 */ 3016 if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT, 3017 ar->running_fw->fw_file.fw_features)) { 3018 status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1); 3019 if (status) { 3020 ath10k_err(ar, "could not write to skip_clock_init: %d\n", 3021 status); 3022 goto err; 3023 } 3024 } 3025 3026 status = ath10k_download_fw(ar); 3027 if (status) 3028 goto err; 3029 3030 status = ath10k_init_uart(ar); 3031 if (status) 3032 goto err; 3033 3034 if (ar->hif.bus == ATH10K_BUS_SDIO) { 3035 status = ath10k_init_sdio(ar, mode); 3036 if (status) { 3037 ath10k_err(ar, "failed to init SDIO: %d\n", status); 3038 goto err; 3039 } 3040 } 3041 } 3042 3043 ar->htc.htc_ops.target_send_suspend_complete = 3044 ath10k_send_suspend_complete; 3045 3046 status = ath10k_htc_init(ar); 3047 if (status) { 3048 ath10k_err(ar, "could not init HTC (%d)\n", status); 3049 goto err; 3050 } 3051 3052 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 3053 ar->running_fw->fw_file.fw_features)) { 3054 status = ath10k_bmi_done(ar); 3055 if (status) 3056 goto err; 3057 } 3058 3059 status = ath10k_wmi_attach(ar); 3060 if (status) { 3061 ath10k_err(ar, "WMI attach failed: %d\n", status); 3062 goto err; 3063 } 3064 3065 status = ath10k_htt_init(ar); 3066 if (status) { 3067 ath10k_err(ar, "failed to init htt: %d\n", status); 3068 goto err_wmi_detach; 3069 } 3070 3071 status = ath10k_htt_tx_start(&ar->htt); 3072 if (status) { 3073 ath10k_err(ar, "failed to alloc htt tx: %d\n", status); 3074 goto err_wmi_detach; 3075 } 3076 3077 /* If firmware indicates Full Rx Reorder support it must be used in a 3078 * slightly different manner. Let HTT code know. 3079 */ 3080 ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER, 3081 ar->wmi.svc_map)); 3082 3083 status = ath10k_htt_rx_alloc(&ar->htt); 3084 if (status) { 3085 ath10k_err(ar, "failed to alloc htt rx: %d\n", status); 3086 goto err_htt_tx_detach; 3087 } 3088 3089 status = ath10k_hif_start(ar); 3090 if (status) { 3091 ath10k_err(ar, "could not start HIF: %d\n", status); 3092 goto err_htt_rx_detach; 3093 } 3094 3095 status = ath10k_htc_wait_target(&ar->htc); 3096 if (status) { 3097 ath10k_err(ar, "failed to connect to HTC: %d\n", status); 3098 goto err_hif_stop; 3099 } 3100 3101 status = ath10k_hif_start_post(ar); 3102 if (status) { 3103 ath10k_err(ar, "failed to swap mailbox: %d\n", status); 3104 goto err_hif_stop; 3105 } 3106 3107 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3108 status = ath10k_htt_connect(&ar->htt); 3109 if (status) { 3110 ath10k_err(ar, "failed to connect htt (%d)\n", status); 3111 goto err_hif_stop; 3112 } 3113 } 3114 3115 status = ath10k_wmi_connect(ar); 3116 if (status) { 3117 ath10k_err(ar, "could not connect wmi: %d\n", status); 3118 goto err_hif_stop; 3119 } 3120 3121 status = ath10k_htc_start(&ar->htc); 3122 if (status) { 3123 ath10k_err(ar, "failed to start htc: %d\n", status); 3124 goto err_hif_stop; 3125 } 3126 3127 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3128 status = ath10k_wmi_wait_for_service_ready(ar); 3129 if (status) { 3130 ath10k_warn(ar, "wmi service ready event not received"); 3131 goto err_hif_stop; 3132 } 3133 } 3134 3135 ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n", 3136 ar->hw->wiphy->fw_version); 3137 3138 if (test_bit(ATH10K_FW_FEATURE_IRAM_RECOVERY, 3139 ar->running_fw->fw_file.fw_features)) { 3140 status = ath10k_core_copy_target_iram(ar); 3141 if (status) { 3142 ath10k_warn(ar, "failed to copy target iram contents: %d", 3143 status); 3144 goto err_hif_stop; 3145 } 3146 } 3147 3148 if (test_bit(WMI_SERVICE_EXT_RES_CFG_SUPPORT, ar->wmi.svc_map) && 3149 mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3150 val = 0; 3151 if (ath10k_peer_stats_enabled(ar)) 3152 val = WMI_10_4_PEER_STATS; 3153 3154 /* Enable vdev stats by default */ 3155 val |= WMI_10_4_VDEV_STATS; 3156 3157 if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map)) 3158 val |= WMI_10_4_BSS_CHANNEL_INFO_64; 3159 3160 ath10k_core_fetch_btcoex_dt(ar); 3161 3162 /* 10.4 firmware supports BT-Coex without reloading firmware 3163 * via pdev param. To support Bluetooth coexistence pdev param, 3164 * WMI_COEX_GPIO_SUPPORT of extended resource config should be 3165 * enabled always. 3166 * 3167 * We can still enable BTCOEX if firmware has the support 3168 * even though btceox_support value is 3169 * ATH10K_DT_BTCOEX_NOT_FOUND 3170 */ 3171 3172 if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) && 3173 test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM, 3174 ar->running_fw->fw_file.fw_features) && 3175 ar->coex_support) 3176 val |= WMI_10_4_COEX_GPIO_SUPPORT; 3177 3178 if (test_bit(WMI_SERVICE_TDLS_EXPLICIT_MODE_ONLY, 3179 ar->wmi.svc_map)) 3180 val |= WMI_10_4_TDLS_EXPLICIT_MODE_ONLY; 3181 3182 if (test_bit(WMI_SERVICE_TDLS_UAPSD_BUFFER_STA, 3183 ar->wmi.svc_map)) 3184 val |= WMI_10_4_TDLS_UAPSD_BUFFER_STA; 3185 3186 if (test_bit(WMI_SERVICE_TX_DATA_ACK_RSSI, 3187 ar->wmi.svc_map)) 3188 val |= WMI_10_4_TX_DATA_ACK_RSSI; 3189 3190 if (test_bit(WMI_SERVICE_REPORT_AIRTIME, ar->wmi.svc_map)) 3191 val |= WMI_10_4_REPORT_AIRTIME; 3192 3193 if (test_bit(WMI_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT, 3194 ar->wmi.svc_map)) 3195 val |= WMI_10_4_EXT_PEER_TID_CONFIGS_SUPPORT; 3196 3197 status = ath10k_mac_ext_resource_config(ar, val); 3198 if (status) { 3199 ath10k_err(ar, 3200 "failed to send ext resource cfg command : %d\n", 3201 status); 3202 goto err_hif_stop; 3203 } 3204 } 3205 3206 status = ath10k_wmi_cmd_init(ar); 3207 if (status) { 3208 ath10k_err(ar, "could not send WMI init command (%d)\n", 3209 status); 3210 goto err_hif_stop; 3211 } 3212 3213 status = ath10k_wmi_wait_for_unified_ready(ar); 3214 if (status) { 3215 ath10k_err(ar, "wmi unified ready event not received\n"); 3216 goto err_hif_stop; 3217 } 3218 3219 status = ath10k_core_compat_services(ar); 3220 if (status) { 3221 ath10k_err(ar, "compat services failed: %d\n", status); 3222 goto err_hif_stop; 3223 } 3224 3225 status = ath10k_wmi_pdev_set_base_macaddr(ar, ar->mac_addr); 3226 if (status && status != -EOPNOTSUPP) { 3227 ath10k_err(ar, 3228 "failed to set base mac address: %d\n", status); 3229 goto err_hif_stop; 3230 } 3231 3232 /* Some firmware revisions do not properly set up hardware rx filter 3233 * registers. 3234 * 3235 * A known example from QCA9880 and 10.2.4 is that MAC_PCU_ADDR1_MASK 3236 * is filled with 0s instead of 1s allowing HW to respond with ACKs to 3237 * any frames that matches MAC_PCU_RX_FILTER which is also 3238 * misconfigured to accept anything. 3239 * 3240 * The ADDR1 is programmed using internal firmware structure field and 3241 * can't be (easily/sanely) reached from the driver explicitly. It is 3242 * possible to implicitly make it correct by creating a dummy vdev and 3243 * then deleting it. 3244 */ 3245 if (ar->hw_params.hw_filter_reset_required && 3246 mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3247 status = ath10k_core_reset_rx_filter(ar); 3248 if (status) { 3249 ath10k_err(ar, 3250 "failed to reset rx filter: %d\n", status); 3251 goto err_hif_stop; 3252 } 3253 } 3254 3255 status = ath10k_htt_rx_ring_refill(ar); 3256 if (status) { 3257 ath10k_err(ar, "failed to refill htt rx ring: %d\n", status); 3258 goto err_hif_stop; 3259 } 3260 3261 if (ar->max_num_vdevs >= 64) 3262 ar->free_vdev_map = 0xFFFFFFFFFFFFFFFFLL; 3263 else 3264 ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1; 3265 3266 INIT_LIST_HEAD(&ar->arvifs); 3267 3268 /* we don't care about HTT in UTF mode */ 3269 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { 3270 status = ath10k_htt_setup(&ar->htt); 3271 if (status) { 3272 ath10k_err(ar, "failed to setup htt: %d\n", status); 3273 goto err_hif_stop; 3274 } 3275 } 3276 3277 status = ath10k_debug_start(ar); 3278 if (status) 3279 goto err_hif_stop; 3280 3281 status = ath10k_hif_set_target_log_mode(ar, fw_diag_log); 3282 if (status && status != -EOPNOTSUPP) { 3283 ath10k_warn(ar, "set target log mode failed: %d\n", status); 3284 goto err_hif_stop; 3285 } 3286 3287 status = ath10k_leds_start(ar); 3288 if (status) 3289 goto err_hif_stop; 3290 3291 return 0; 3292 3293 err_hif_stop: 3294 ath10k_hif_stop(ar); 3295 err_htt_rx_detach: 3296 ath10k_htt_rx_free(&ar->htt); 3297 err_htt_tx_detach: 3298 ath10k_htt_tx_free(&ar->htt); 3299 err_wmi_detach: 3300 ath10k_wmi_detach(ar); 3301 err: 3302 return status; 3303 } 3304 EXPORT_SYMBOL(ath10k_core_start); 3305 3306 int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt) 3307 { 3308 int ret; 3309 unsigned long time_left; 3310 3311 reinit_completion(&ar->target_suspend); 3312 3313 ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt); 3314 if (ret) { 3315 ath10k_warn(ar, "could not suspend target (%d)\n", ret); 3316 return ret; 3317 } 3318 3319 time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ); 3320 3321 if (!time_left) { 3322 ath10k_warn(ar, "suspend timed out - target pause event never came\n"); 3323 return -ETIMEDOUT; 3324 } 3325 3326 return 0; 3327 } 3328 3329 void ath10k_core_stop(struct ath10k *ar) 3330 { 3331 lockdep_assert_held(&ar->conf_mutex); 3332 ath10k_debug_stop(ar); 3333 3334 /* try to suspend target */ 3335 if (ar->state != ATH10K_STATE_RESTARTING && 3336 ar->state != ATH10K_STATE_UTF) 3337 ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR); 3338 3339 ath10k_hif_stop(ar); 3340 ath10k_htt_tx_stop(&ar->htt); 3341 ath10k_htt_rx_free(&ar->htt); 3342 ath10k_wmi_detach(ar); 3343 3344 ar->id.bmi_ids_valid = false; 3345 } 3346 EXPORT_SYMBOL(ath10k_core_stop); 3347 3348 /* mac80211 manages fw/hw initialization through start/stop hooks. However in 3349 * order to know what hw capabilities should be advertised to mac80211 it is 3350 * necessary to load the firmware (and tear it down immediately since start 3351 * hook will try to init it again) before registering 3352 */ 3353 static int ath10k_core_probe_fw(struct ath10k *ar) 3354 { 3355 struct bmi_target_info target_info = {}; 3356 int ret = 0; 3357 3358 ret = ath10k_hif_power_up(ar, ATH10K_FIRMWARE_MODE_NORMAL); 3359 if (ret) { 3360 ath10k_err(ar, "could not power on hif bus (%d)\n", ret); 3361 return ret; 3362 } 3363 3364 switch (ar->hif.bus) { 3365 case ATH10K_BUS_SDIO: 3366 ret = ath10k_bmi_get_target_info_sdio(ar, &target_info); 3367 if (ret) { 3368 ath10k_err(ar, "could not get target info (%d)\n", ret); 3369 goto err_power_down; 3370 } 3371 ar->target_version = target_info.version; 3372 ar->hw->wiphy->hw_version = target_info.version; 3373 break; 3374 case ATH10K_BUS_PCI: 3375 case ATH10K_BUS_AHB: 3376 case ATH10K_BUS_USB: 3377 ret = ath10k_bmi_get_target_info(ar, &target_info); 3378 if (ret) { 3379 ath10k_err(ar, "could not get target info (%d)\n", ret); 3380 goto err_power_down; 3381 } 3382 ar->target_version = target_info.version; 3383 ar->hw->wiphy->hw_version = target_info.version; 3384 break; 3385 case ATH10K_BUS_SNOC: 3386 ret = ath10k_hif_get_target_info(ar, &target_info); 3387 if (ret) { 3388 ath10k_err(ar, "could not get target info (%d)\n", ret); 3389 goto err_power_down; 3390 } 3391 ar->target_version = target_info.version; 3392 ar->hw->wiphy->hw_version = target_info.version; 3393 break; 3394 default: 3395 ath10k_err(ar, "incorrect hif bus type: %d\n", ar->hif.bus); 3396 } 3397 3398 ret = ath10k_init_hw_params(ar); 3399 if (ret) { 3400 ath10k_err(ar, "could not get hw params (%d)\n", ret); 3401 goto err_power_down; 3402 } 3403 3404 ret = ath10k_core_fetch_firmware_files(ar); 3405 if (ret) { 3406 ath10k_err(ar, "could not fetch firmware files (%d)\n", ret); 3407 goto err_power_down; 3408 } 3409 3410 BUILD_BUG_ON(sizeof(ar->hw->wiphy->fw_version) != 3411 sizeof(ar->normal_mode_fw.fw_file.fw_version)); 3412 memcpy(ar->hw->wiphy->fw_version, ar->normal_mode_fw.fw_file.fw_version, 3413 sizeof(ar->hw->wiphy->fw_version)); 3414 3415 ath10k_debug_print_hwfw_info(ar); 3416 3417 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 3418 ar->normal_mode_fw.fw_file.fw_features)) { 3419 ret = ath10k_core_pre_cal_download(ar); 3420 if (ret) { 3421 /* pre calibration data download is not necessary 3422 * for all the chipsets. Ignore failures and continue. 3423 */ 3424 ath10k_dbg(ar, ATH10K_DBG_BOOT, 3425 "could not load pre cal data: %d\n", ret); 3426 } 3427 3428 ret = ath10k_core_get_board_id_from_otp(ar); 3429 if (ret && ret != -EOPNOTSUPP) { 3430 ath10k_err(ar, "failed to get board id from otp: %d\n", 3431 ret); 3432 goto err_free_firmware_files; 3433 } 3434 3435 ret = ath10k_core_check_smbios(ar); 3436 if (ret) 3437 ath10k_dbg(ar, ATH10K_DBG_BOOT, "SMBIOS bdf variant name not set.\n"); 3438 3439 ret = ath10k_core_check_dt(ar); 3440 if (ret) 3441 ath10k_dbg(ar, ATH10K_DBG_BOOT, "DT bdf variant name not set.\n"); 3442 3443 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD); 3444 if (ret) { 3445 ath10k_err(ar, "failed to fetch board file: %d\n", ret); 3446 goto err_free_firmware_files; 3447 } 3448 3449 ath10k_debug_print_board_info(ar); 3450 } 3451 3452 device_get_mac_address(ar->dev, ar->mac_addr); 3453 3454 ret = ath10k_core_init_firmware_features(ar); 3455 if (ret) { 3456 ath10k_err(ar, "fatal problem with firmware features: %d\n", 3457 ret); 3458 goto err_free_firmware_files; 3459 } 3460 3461 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, 3462 ar->normal_mode_fw.fw_file.fw_features)) { 3463 ret = ath10k_swap_code_seg_init(ar, 3464 &ar->normal_mode_fw.fw_file); 3465 if (ret) { 3466 ath10k_err(ar, "failed to initialize code swap segment: %d\n", 3467 ret); 3468 goto err_free_firmware_files; 3469 } 3470 } 3471 3472 mutex_lock(&ar->conf_mutex); 3473 3474 ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL, 3475 &ar->normal_mode_fw); 3476 if (ret) { 3477 ath10k_err(ar, "could not init core (%d)\n", ret); 3478 goto err_unlock; 3479 } 3480 3481 ath10k_debug_print_boot_info(ar); 3482 ath10k_core_stop(ar); 3483 3484 mutex_unlock(&ar->conf_mutex); 3485 3486 ath10k_hif_power_down(ar); 3487 return 0; 3488 3489 err_unlock: 3490 mutex_unlock(&ar->conf_mutex); 3491 3492 err_free_firmware_files: 3493 ath10k_core_free_firmware_files(ar); 3494 3495 err_power_down: 3496 ath10k_hif_power_down(ar); 3497 3498 return ret; 3499 } 3500 3501 static void ath10k_core_register_work(struct work_struct *work) 3502 { 3503 struct ath10k *ar = container_of(work, struct ath10k, register_work); 3504 int status; 3505 3506 /* peer stats are enabled by default */ 3507 set_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags); 3508 3509 status = ath10k_core_probe_fw(ar); 3510 if (status) { 3511 ath10k_err(ar, "could not probe fw (%d)\n", status); 3512 goto err; 3513 } 3514 3515 status = ath10k_mac_register(ar); 3516 if (status) { 3517 ath10k_err(ar, "could not register to mac80211 (%d)\n", status); 3518 goto err_release_fw; 3519 } 3520 3521 status = ath10k_coredump_register(ar); 3522 if (status) { 3523 ath10k_err(ar, "unable to register coredump\n"); 3524 goto err_unregister_mac; 3525 } 3526 3527 status = ath10k_debug_register(ar); 3528 if (status) { 3529 ath10k_err(ar, "unable to initialize debugfs\n"); 3530 goto err_unregister_coredump; 3531 } 3532 3533 status = ath10k_spectral_create(ar); 3534 if (status) { 3535 ath10k_err(ar, "failed to initialize spectral\n"); 3536 goto err_debug_destroy; 3537 } 3538 3539 status = ath10k_thermal_register(ar); 3540 if (status) { 3541 ath10k_err(ar, "could not register thermal device: %d\n", 3542 status); 3543 goto err_spectral_destroy; 3544 } 3545 3546 status = ath10k_leds_register(ar); 3547 if (status) { 3548 ath10k_err(ar, "could not register leds: %d\n", 3549 status); 3550 goto err_thermal_unregister; 3551 } 3552 3553 set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags); 3554 return; 3555 3556 err_thermal_unregister: 3557 ath10k_thermal_unregister(ar); 3558 err_spectral_destroy: 3559 ath10k_spectral_destroy(ar); 3560 err_debug_destroy: 3561 ath10k_debug_destroy(ar); 3562 err_unregister_coredump: 3563 ath10k_coredump_unregister(ar); 3564 err_unregister_mac: 3565 ath10k_mac_unregister(ar); 3566 err_release_fw: 3567 ath10k_core_free_firmware_files(ar); 3568 err: 3569 /* TODO: It's probably a good idea to release device from the driver 3570 * but calling device_release_driver() here will cause a deadlock. 3571 */ 3572 return; 3573 } 3574 3575 int ath10k_core_register(struct ath10k *ar, 3576 const struct ath10k_bus_params *bus_params) 3577 { 3578 ar->bus_param = *bus_params; 3579 3580 queue_work(ar->workqueue, &ar->register_work); 3581 3582 return 0; 3583 } 3584 EXPORT_SYMBOL(ath10k_core_register); 3585 3586 void ath10k_core_unregister(struct ath10k *ar) 3587 { 3588 cancel_work_sync(&ar->register_work); 3589 3590 if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags)) 3591 return; 3592 3593 ath10k_leds_unregister(ar); 3594 3595 ath10k_thermal_unregister(ar); 3596 /* Stop spectral before unregistering from mac80211 to remove the 3597 * relayfs debugfs file cleanly. Otherwise the parent debugfs tree 3598 * would be already be free'd recursively, leading to a double free. 3599 */ 3600 ath10k_spectral_destroy(ar); 3601 3602 /* We must unregister from mac80211 before we stop HTC and HIF. 3603 * Otherwise we will fail to submit commands to FW and mac80211 will be 3604 * unhappy about callback failures. 3605 */ 3606 ath10k_mac_unregister(ar); 3607 3608 ath10k_testmode_destroy(ar); 3609 3610 ath10k_core_free_firmware_files(ar); 3611 ath10k_core_free_board_files(ar); 3612 3613 ath10k_debug_unregister(ar); 3614 } 3615 EXPORT_SYMBOL(ath10k_core_unregister); 3616 3617 struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev, 3618 enum ath10k_bus bus, 3619 enum ath10k_hw_rev hw_rev, 3620 const struct ath10k_hif_ops *hif_ops) 3621 { 3622 struct ath10k *ar; 3623 int ret; 3624 3625 ar = ath10k_mac_create(priv_size); 3626 if (!ar) 3627 return NULL; 3628 3629 ar->ath_common.priv = ar; 3630 ar->ath_common.hw = ar->hw; 3631 ar->dev = dev; 3632 ar->hw_rev = hw_rev; 3633 ar->hif.ops = hif_ops; 3634 ar->hif.bus = bus; 3635 3636 switch (hw_rev) { 3637 case ATH10K_HW_QCA988X: 3638 case ATH10K_HW_QCA9887: 3639 ar->regs = &qca988x_regs; 3640 ar->hw_ce_regs = &qcax_ce_regs; 3641 ar->hw_values = &qca988x_values; 3642 break; 3643 case ATH10K_HW_QCA6174: 3644 case ATH10K_HW_QCA9377: 3645 ar->regs = &qca6174_regs; 3646 ar->hw_ce_regs = &qcax_ce_regs; 3647 ar->hw_values = &qca6174_values; 3648 break; 3649 case ATH10K_HW_QCA99X0: 3650 case ATH10K_HW_QCA9984: 3651 ar->regs = &qca99x0_regs; 3652 ar->hw_ce_regs = &qcax_ce_regs; 3653 ar->hw_values = &qca99x0_values; 3654 break; 3655 case ATH10K_HW_QCA9888: 3656 ar->regs = &qca99x0_regs; 3657 ar->hw_ce_regs = &qcax_ce_regs; 3658 ar->hw_values = &qca9888_values; 3659 break; 3660 case ATH10K_HW_QCA4019: 3661 ar->regs = &qca4019_regs; 3662 ar->hw_ce_regs = &qcax_ce_regs; 3663 ar->hw_values = &qca4019_values; 3664 break; 3665 case ATH10K_HW_WCN3990: 3666 ar->regs = &wcn3990_regs; 3667 ar->hw_ce_regs = &wcn3990_ce_regs; 3668 ar->hw_values = &wcn3990_values; 3669 break; 3670 default: 3671 ath10k_err(ar, "unsupported core hardware revision %d\n", 3672 hw_rev); 3673 ret = -EOPNOTSUPP; 3674 goto err_free_mac; 3675 } 3676 3677 init_completion(&ar->scan.started); 3678 init_completion(&ar->scan.completed); 3679 init_completion(&ar->scan.on_channel); 3680 init_completion(&ar->target_suspend); 3681 init_completion(&ar->driver_recovery); 3682 init_completion(&ar->wow.wakeup_completed); 3683 3684 init_completion(&ar->install_key_done); 3685 init_completion(&ar->vdev_setup_done); 3686 init_completion(&ar->vdev_delete_done); 3687 init_completion(&ar->thermal.wmi_sync); 3688 init_completion(&ar->bss_survey_done); 3689 init_completion(&ar->peer_delete_done); 3690 init_completion(&ar->peer_stats_info_complete); 3691 3692 INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work); 3693 3694 ar->workqueue = create_singlethread_workqueue("ath10k_wq"); 3695 if (!ar->workqueue) 3696 goto err_free_mac; 3697 3698 ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq"); 3699 if (!ar->workqueue_aux) 3700 goto err_free_wq; 3701 3702 ar->workqueue_tx_complete = 3703 create_singlethread_workqueue("ath10k_tx_complete_wq"); 3704 if (!ar->workqueue_tx_complete) 3705 goto err_free_aux_wq; 3706 3707 mutex_init(&ar->conf_mutex); 3708 mutex_init(&ar->dump_mutex); 3709 spin_lock_init(&ar->data_lock); 3710 3711 for (int ac = 0; ac < IEEE80211_NUM_ACS; ac++) 3712 spin_lock_init(&ar->queue_lock[ac]); 3713 3714 INIT_LIST_HEAD(&ar->peers); 3715 init_waitqueue_head(&ar->peer_mapping_wq); 3716 init_waitqueue_head(&ar->htt.empty_tx_wq); 3717 init_waitqueue_head(&ar->wmi.tx_credits_wq); 3718 3719 skb_queue_head_init(&ar->htt.rx_indication_head); 3720 3721 init_completion(&ar->offchan_tx_completed); 3722 INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work); 3723 skb_queue_head_init(&ar->offchan_tx_queue); 3724 3725 INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work); 3726 skb_queue_head_init(&ar->wmi_mgmt_tx_queue); 3727 3728 INIT_WORK(&ar->register_work, ath10k_core_register_work); 3729 INIT_WORK(&ar->restart_work, ath10k_core_restart); 3730 INIT_WORK(&ar->recovery_check_work, ath10k_core_recovery_check_work); 3731 INIT_WORK(&ar->set_coverage_class_work, 3732 ath10k_core_set_coverage_class_work); 3733 3734 ar->napi_dev = alloc_netdev_dummy(0); 3735 if (!ar->napi_dev) 3736 goto err_free_tx_complete; 3737 3738 ret = ath10k_coredump_create(ar); 3739 if (ret) 3740 goto err_free_netdev; 3741 3742 ret = ath10k_debug_create(ar); 3743 if (ret) 3744 goto err_free_coredump; 3745 3746 return ar; 3747 3748 err_free_coredump: 3749 ath10k_coredump_destroy(ar); 3750 err_free_netdev: 3751 free_netdev(ar->napi_dev); 3752 err_free_tx_complete: 3753 destroy_workqueue(ar->workqueue_tx_complete); 3754 err_free_aux_wq: 3755 destroy_workqueue(ar->workqueue_aux); 3756 err_free_wq: 3757 destroy_workqueue(ar->workqueue); 3758 err_free_mac: 3759 ath10k_mac_destroy(ar); 3760 3761 return NULL; 3762 } 3763 EXPORT_SYMBOL(ath10k_core_create); 3764 3765 void ath10k_core_destroy(struct ath10k *ar) 3766 { 3767 destroy_workqueue(ar->workqueue); 3768 3769 destroy_workqueue(ar->workqueue_aux); 3770 3771 destroy_workqueue(ar->workqueue_tx_complete); 3772 3773 free_netdev(ar->napi_dev); 3774 ath10k_debug_destroy(ar); 3775 ath10k_coredump_destroy(ar); 3776 ath10k_htt_tx_destroy(&ar->htt); 3777 ath10k_wmi_free_host_mem(ar); 3778 ath10k_mac_destroy(ar); 3779 } 3780 EXPORT_SYMBOL(ath10k_core_destroy); 3781 3782 MODULE_AUTHOR("Qualcomm Atheros"); 3783 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ac wireless LAN cards."); 3784 MODULE_LICENSE("Dual BSD/GPL"); 3785