xref: /linux/drivers/pinctrl/pinctrl-at91.c (revision 41594663c3fb565940ec2b947bd7e623e3f0e600)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * at91 pinctrl driver based on at91 pinmux core
4  *
5  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
6  */
7 
8 #include <linux/clk.h>
9 #include <linux/err.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm.h>
17 #include <linux/property.h>
18 #include <linux/seq_file.h>
19 #include <linux/slab.h>
20 #include <linux/string_helpers.h>
21 
22 /* Since we request GPIOs from ourself */
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinconf.h>
26 #include <linux/pinctrl/pinctrl.h>
27 #include <linux/pinctrl/pinmux.h>
28 
29 #include "pinctrl-at91.h"
30 #include "core.h"
31 
32 #define MAX_GPIO_BANKS		5
33 #define MAX_NB_GPIO_PER_BANK	32
34 
35 struct at91_pinctrl_mux_ops;
36 
37 /**
38  * struct at91_gpio_chip: at91 gpio chip
39  * @chip: gpio chip
40  * @range: gpio range
41  * @next: bank sharing same clock
42  * @pioc_hwirq: PIO bank interrupt identifier on AIC
43  * @pioc_virq: PIO bank Linux virtual interrupt
44  * @regbase: PIO bank virtual address
45  * @clock: associated clock
46  * @ops: at91 pinctrl mux ops
47  * @wakeups: wakeup interrupts
48  * @backups: interrupts disabled in suspend
49  * @id: gpio chip identifier
50  */
51 struct at91_gpio_chip {
52 	struct gpio_chip	chip;
53 	struct pinctrl_gpio_range range;
54 	struct at91_gpio_chip	*next;
55 	int			pioc_hwirq;
56 	int			pioc_virq;
57 	void __iomem		*regbase;
58 	struct clk		*clock;
59 	const struct at91_pinctrl_mux_ops *ops;
60 	u32			wakeups;
61 	u32			backups;
62 	u32			id;
63 };
64 
65 static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
66 
67 static int gpio_banks;
68 
69 #define PULL_UP		(1 << 0)
70 #define MULTI_DRIVE	(1 << 1)
71 #define DEGLITCH	(1 << 2)
72 #define PULL_DOWN	(1 << 3)
73 #define DIS_SCHMIT	(1 << 4)
74 #define DRIVE_STRENGTH_SHIFT	5
75 #define DRIVE_STRENGTH_MASK		0x3
76 #define DRIVE_STRENGTH   (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
77 #define OUTPUT		(1 << 7)
78 #define OUTPUT_VAL_SHIFT	8
79 #define OUTPUT_VAL	(0x1 << OUTPUT_VAL_SHIFT)
80 #define SLEWRATE_SHIFT	9
81 #define SLEWRATE_MASK	0x1
82 #define SLEWRATE	(SLEWRATE_MASK << SLEWRATE_SHIFT)
83 #define DEBOUNCE	(1 << 16)
84 #define DEBOUNCE_VAL_SHIFT	17
85 #define DEBOUNCE_VAL	(0x3fff << DEBOUNCE_VAL_SHIFT)
86 
87 /*
88  * These defines will translated the dt binding settings to our internal
89  * settings. They are not necessarily the same value as the register setting.
90  * The actual drive strength current of low, medium and high must be looked up
91  * from the corresponding device datasheet. This value is different for pins
92  * that are even in the same banks. It is also dependent on VCC.
93  * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
94  * strength when there is no dt config for it.
95  */
96 enum drive_strength_bit {
97 	DRIVE_STRENGTH_BIT_DEF,
98 	DRIVE_STRENGTH_BIT_LOW,
99 	DRIVE_STRENGTH_BIT_MED,
100 	DRIVE_STRENGTH_BIT_HI,
101 };
102 
103 #define DRIVE_STRENGTH_BIT_MSK(name)	(DRIVE_STRENGTH_BIT_##name << \
104 					 DRIVE_STRENGTH_SHIFT)
105 
106 enum slewrate_bit {
107 	SLEWRATE_BIT_ENA,
108 	SLEWRATE_BIT_DIS,
109 };
110 
111 #define SLEWRATE_BIT_MSK(name)		(SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
112 
113 /**
114  * struct at91_pmx_func - describes AT91 pinmux functions
115  * @name: the name of this specific function
116  * @groups: corresponding pin groups
117  * @ngroups: the number of groups
118  */
119 struct at91_pmx_func {
120 	const char	*name;
121 	const char	**groups;
122 	unsigned	ngroups;
123 };
124 
125 enum at91_mux {
126 	AT91_MUX_GPIO = 0,
127 	AT91_MUX_PERIPH_A = 1,
128 	AT91_MUX_PERIPH_B = 2,
129 	AT91_MUX_PERIPH_C = 3,
130 	AT91_MUX_PERIPH_D = 4,
131 };
132 
133 /**
134  * struct at91_pmx_pin - describes an At91 pin mux
135  * @bank: the bank of the pin
136  * @pin: the pin number in the @bank
137  * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
138  * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
139  */
140 struct at91_pmx_pin {
141 	uint32_t	bank;
142 	uint32_t	pin;
143 	enum at91_mux	mux;
144 	unsigned long	conf;
145 };
146 
147 /**
148  * struct at91_pin_group - describes an At91 pin group
149  * @name: the name of this specific pin group
150  * @pins_conf: the mux mode for each pin in this group. The size of this
151  *	array is the same as pins.
152  * @pins: an array of discrete physical pins used in this group, taken
153  *	from the driver-local pin enumeration space
154  * @npins: the number of pins in this group array, i.e. the number of
155  *	elements in .pins so we can iterate over that array
156  */
157 struct at91_pin_group {
158 	const char		*name;
159 	struct at91_pmx_pin	*pins_conf;
160 	unsigned int		*pins;
161 	unsigned		npins;
162 };
163 
164 /**
165  * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
166  * on new IP with support for periph C and D the way to mux in
167  * periph A and B has changed
168  * So provide the right call back
169  * if not present means the IP does not support it
170  * @get_periph: return the periph mode configured
171  * @mux_A_periph: mux as periph A
172  * @mux_B_periph: mux as periph B
173  * @mux_C_periph: mux as periph C
174  * @mux_D_periph: mux as periph D
175  * @get_deglitch: get deglitch status
176  * @set_deglitch: enable/disable deglitch
177  * @get_debounce: get debounce status
178  * @set_debounce: enable/disable debounce
179  * @get_pulldown: get pulldown status
180  * @set_pulldown: enable/disable pulldown
181  * @get_schmitt_trig: get schmitt trigger status
182  * @disable_schmitt_trig: disable schmitt trigger
183  * @get_drivestrength: get driver strength
184  * @set_drivestrength: set driver strength
185  * @get_slewrate: get slew rate
186  * @set_slewrate: set slew rate
187  * @irq_type: return irq type
188  */
189 struct at91_pinctrl_mux_ops {
190 	enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
191 	void (*mux_A_periph)(void __iomem *pio, unsigned mask);
192 	void (*mux_B_periph)(void __iomem *pio, unsigned mask);
193 	void (*mux_C_periph)(void __iomem *pio, unsigned mask);
194 	void (*mux_D_periph)(void __iomem *pio, unsigned mask);
195 	bool (*get_deglitch)(void __iomem *pio, unsigned pin);
196 	void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
197 	bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
198 	void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
199 	bool (*get_pulldown)(void __iomem *pio, unsigned pin);
200 	void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
201 	bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
202 	void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
203 	unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
204 	void (*set_drivestrength)(void __iomem *pio, unsigned pin,
205 					u32 strength);
206 	unsigned (*get_slewrate)(void __iomem *pio, unsigned pin);
207 	void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate);
208 	/* irq */
209 	int (*irq_type)(struct irq_data *d, unsigned type);
210 };
211 
212 static int gpio_irq_type(struct irq_data *d, unsigned type);
213 static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
214 
215 struct at91_pinctrl {
216 	struct device		*dev;
217 	struct pinctrl_dev	*pctl;
218 
219 	int			nactive_banks;
220 
221 	uint32_t		*mux_mask;
222 	int			nmux;
223 
224 	struct at91_pmx_func	*functions;
225 	int			nfunctions;
226 
227 	struct at91_pin_group	*groups;
228 	int			ngroups;
229 
230 	const struct at91_pinctrl_mux_ops *ops;
231 };
232 
at91_pinctrl_find_group_by_name(const struct at91_pinctrl * info,const char * name)233 static inline const struct at91_pin_group *at91_pinctrl_find_group_by_name(
234 				const struct at91_pinctrl *info,
235 				const char *name)
236 {
237 	const struct at91_pin_group *grp = NULL;
238 	int i;
239 
240 	for (i = 0; i < info->ngroups; i++) {
241 		if (strcmp(info->groups[i].name, name))
242 			continue;
243 
244 		grp = &info->groups[i];
245 		dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
246 		break;
247 	}
248 
249 	return grp;
250 }
251 
at91_get_groups_count(struct pinctrl_dev * pctldev)252 static int at91_get_groups_count(struct pinctrl_dev *pctldev)
253 {
254 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
255 
256 	return info->ngroups;
257 }
258 
at91_get_group_name(struct pinctrl_dev * pctldev,unsigned selector)259 static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
260 				       unsigned selector)
261 {
262 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
263 
264 	return info->groups[selector].name;
265 }
266 
at91_get_group_pins(struct pinctrl_dev * pctldev,unsigned selector,const unsigned ** pins,unsigned * npins)267 static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
268 			       const unsigned **pins,
269 			       unsigned *npins)
270 {
271 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
272 
273 	if (selector >= info->ngroups)
274 		return -EINVAL;
275 
276 	*pins = info->groups[selector].pins;
277 	*npins = info->groups[selector].npins;
278 
279 	return 0;
280 }
281 
at91_pin_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned offset)282 static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
283 		   unsigned offset)
284 {
285 	seq_printf(s, "%s", dev_name(pctldev->dev));
286 }
287 
at91_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned * num_maps)288 static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
289 			struct device_node *np,
290 			struct pinctrl_map **map, unsigned *num_maps)
291 {
292 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
293 	const struct at91_pin_group *grp;
294 	struct pinctrl_map *new_map;
295 	struct device_node *parent;
296 	int map_num = 1;
297 	int i;
298 
299 	/*
300 	 * first find the group of this node and check if we need to create
301 	 * config maps for pins
302 	 */
303 	grp = at91_pinctrl_find_group_by_name(info, np->name);
304 	if (!grp) {
305 		dev_err(info->dev, "unable to find group for node %pOFn\n",
306 			np);
307 		return -EINVAL;
308 	}
309 
310 	map_num += grp->npins;
311 	new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map),
312 			       GFP_KERNEL);
313 	if (!new_map)
314 		return -ENOMEM;
315 
316 	*map = new_map;
317 	*num_maps = map_num;
318 
319 	/* create mux map */
320 	parent = of_get_parent(np);
321 	if (!parent) {
322 		devm_kfree(pctldev->dev, new_map);
323 		return -EINVAL;
324 	}
325 	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
326 	new_map[0].data.mux.function = parent->name;
327 	new_map[0].data.mux.group = np->name;
328 	of_node_put(parent);
329 
330 	/* create config map */
331 	new_map++;
332 	for (i = 0; i < grp->npins; i++) {
333 		new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
334 		new_map[i].data.configs.group_or_pin =
335 				pin_get_name(pctldev, grp->pins[i]);
336 		new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
337 		new_map[i].data.configs.num_configs = 1;
338 	}
339 
340 	dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
341 		(*map)->data.mux.function, (*map)->data.mux.group, map_num);
342 
343 	return 0;
344 }
345 
at91_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * map,unsigned num_maps)346 static void at91_dt_free_map(struct pinctrl_dev *pctldev,
347 				struct pinctrl_map *map, unsigned num_maps)
348 {
349 }
350 
351 static const struct pinctrl_ops at91_pctrl_ops = {
352 	.get_groups_count	= at91_get_groups_count,
353 	.get_group_name		= at91_get_group_name,
354 	.get_group_pins		= at91_get_group_pins,
355 	.pin_dbg_show		= at91_pin_dbg_show,
356 	.dt_node_to_map		= at91_dt_node_to_map,
357 	.dt_free_map		= at91_dt_free_map,
358 };
359 
pin_to_controller(struct at91_pinctrl * info,unsigned int bank)360 static void __iomem *pin_to_controller(struct at91_pinctrl *info,
361 				 unsigned int bank)
362 {
363 	if (!gpio_chips[bank])
364 		return NULL;
365 
366 	return gpio_chips[bank]->regbase;
367 }
368 
pin_to_bank(unsigned pin)369 static inline int pin_to_bank(unsigned pin)
370 {
371 	return pin /= MAX_NB_GPIO_PER_BANK;
372 }
373 
pin_to_mask(unsigned int pin)374 static unsigned pin_to_mask(unsigned int pin)
375 {
376 	return 1 << pin;
377 }
378 
two_bit_pin_value_shift_amount(unsigned int pin)379 static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
380 {
381 	/* return the shift value for a pin for "two bit" per pin registers,
382 	 * i.e. drive strength */
383 	return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
384 			? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
385 }
386 
sama5d3_get_drive_register(unsigned int pin)387 static unsigned sama5d3_get_drive_register(unsigned int pin)
388 {
389 	/* drive strength is split between two registers
390 	 * with two bits per pin */
391 	return (pin >= MAX_NB_GPIO_PER_BANK/2)
392 			? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
393 }
394 
at91sam9x5_get_drive_register(unsigned int pin)395 static unsigned at91sam9x5_get_drive_register(unsigned int pin)
396 {
397 	/* drive strength is split between two registers
398 	 * with two bits per pin */
399 	return (pin >= MAX_NB_GPIO_PER_BANK/2)
400 			? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
401 }
402 
at91_mux_disable_interrupt(void __iomem * pio,unsigned mask)403 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
404 {
405 	writel_relaxed(mask, pio + PIO_IDR);
406 }
407 
at91_mux_get_pullup(void __iomem * pio,unsigned pin)408 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
409 {
410 	return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
411 }
412 
at91_mux_set_pullup(void __iomem * pio,unsigned mask,bool on)413 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
414 {
415 	if (on)
416 		writel_relaxed(mask, pio + PIO_PPDDR);
417 
418 	writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
419 }
420 
at91_mux_get_output(void __iomem * pio,unsigned int pin,bool * val)421 static bool at91_mux_get_output(void __iomem *pio, unsigned int pin, bool *val)
422 {
423 	*val = (readl_relaxed(pio + PIO_ODSR) >> pin) & 0x1;
424 	return (readl_relaxed(pio + PIO_OSR) >> pin) & 0x1;
425 }
426 
at91_mux_set_output(void __iomem * pio,unsigned int mask,bool is_on,bool val)427 static void at91_mux_set_output(void __iomem *pio, unsigned int mask,
428 				bool is_on, bool val)
429 {
430 	writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
431 	writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR));
432 }
433 
at91_mux_get_multidrive(void __iomem * pio,unsigned pin)434 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
435 {
436 	return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
437 }
438 
at91_mux_set_multidrive(void __iomem * pio,unsigned mask,bool on)439 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
440 {
441 	writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
442 }
443 
at91_mux_set_A_periph(void __iomem * pio,unsigned mask)444 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
445 {
446 	writel_relaxed(mask, pio + PIO_ASR);
447 }
448 
at91_mux_set_B_periph(void __iomem * pio,unsigned mask)449 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
450 {
451 	writel_relaxed(mask, pio + PIO_BSR);
452 }
453 
at91_mux_pio3_set_A_periph(void __iomem * pio,unsigned mask)454 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
455 {
456 
457 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
458 						pio + PIO_ABCDSR1);
459 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
460 						pio + PIO_ABCDSR2);
461 }
462 
at91_mux_pio3_set_B_periph(void __iomem * pio,unsigned mask)463 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
464 {
465 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
466 						pio + PIO_ABCDSR1);
467 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
468 						pio + PIO_ABCDSR2);
469 }
470 
at91_mux_pio3_set_C_periph(void __iomem * pio,unsigned mask)471 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
472 {
473 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
474 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
475 }
476 
at91_mux_pio3_set_D_periph(void __iomem * pio,unsigned mask)477 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
478 {
479 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
480 	writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
481 }
482 
at91_mux_pio3_get_periph(void __iomem * pio,unsigned mask)483 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
484 {
485 	unsigned select;
486 
487 	if (readl_relaxed(pio + PIO_PSR) & mask)
488 		return AT91_MUX_GPIO;
489 
490 	select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
491 	select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
492 
493 	return select + 1;
494 }
495 
at91_mux_get_periph(void __iomem * pio,unsigned mask)496 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
497 {
498 	unsigned select;
499 
500 	if (readl_relaxed(pio + PIO_PSR) & mask)
501 		return AT91_MUX_GPIO;
502 
503 	select = readl_relaxed(pio + PIO_ABSR) & mask;
504 
505 	return select + 1;
506 }
507 
at91_mux_get_deglitch(void __iomem * pio,unsigned pin)508 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
509 {
510 	return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1;
511 }
512 
at91_mux_set_deglitch(void __iomem * pio,unsigned mask,bool is_on)513 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
514 {
515 	writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
516 }
517 
at91_mux_pio3_get_deglitch(void __iomem * pio,unsigned pin)518 static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
519 {
520 	if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1)
521 		return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
522 
523 	return false;
524 }
525 
at91_mux_pio3_set_deglitch(void __iomem * pio,unsigned mask,bool is_on)526 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
527 {
528 	if (is_on)
529 		writel_relaxed(mask, pio + PIO_IFSCDR);
530 	at91_mux_set_deglitch(pio, mask, is_on);
531 }
532 
at91_mux_pio3_get_debounce(void __iomem * pio,unsigned pin,u32 * div)533 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
534 {
535 	*div = readl_relaxed(pio + PIO_SCDR);
536 
537 	return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) &&
538 	       ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
539 }
540 
at91_mux_pio3_set_debounce(void __iomem * pio,unsigned mask,bool is_on,u32 div)541 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
542 				bool is_on, u32 div)
543 {
544 	if (is_on) {
545 		writel_relaxed(mask, pio + PIO_IFSCER);
546 		writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR);
547 		writel_relaxed(mask, pio + PIO_IFER);
548 	} else
549 		writel_relaxed(mask, pio + PIO_IFSCDR);
550 }
551 
at91_mux_pio3_get_pulldown(void __iomem * pio,unsigned pin)552 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
553 {
554 	return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1);
555 }
556 
at91_mux_pio3_set_pulldown(void __iomem * pio,unsigned mask,bool is_on)557 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
558 {
559 	if (is_on)
560 		writel_relaxed(mask, pio + PIO_PUDR);
561 
562 	writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
563 }
564 
at91_mux_pio3_disable_schmitt_trig(void __iomem * pio,unsigned mask)565 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
566 {
567 	writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
568 }
569 
at91_mux_pio3_get_schmitt_trig(void __iomem * pio,unsigned pin)570 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
571 {
572 	return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1;
573 }
574 
read_drive_strength(void __iomem * reg,unsigned pin)575 static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
576 {
577 	unsigned tmp = readl_relaxed(reg);
578 
579 	tmp = tmp >> two_bit_pin_value_shift_amount(pin);
580 
581 	return tmp & DRIVE_STRENGTH_MASK;
582 }
583 
at91_mux_sama5d3_get_drivestrength(void __iomem * pio,unsigned pin)584 static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
585 							unsigned pin)
586 {
587 	unsigned tmp = read_drive_strength(pio +
588 					sama5d3_get_drive_register(pin), pin);
589 
590 	/* SAMA5 strength is 1:1 with our defines,
591 	 * except 0 is equivalent to low per datasheet */
592 	if (!tmp)
593 		tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
594 
595 	return tmp;
596 }
597 
at91_mux_sam9x5_get_drivestrength(void __iomem * pio,unsigned pin)598 static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
599 							unsigned pin)
600 {
601 	unsigned tmp = read_drive_strength(pio +
602 				at91sam9x5_get_drive_register(pin), pin);
603 
604 	/* strength is inverse in SAM9x5s hardware with the pinctrl defines
605 	 * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
606 	tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
607 
608 	return tmp;
609 }
610 
at91_mux_sam9x60_get_drivestrength(void __iomem * pio,unsigned pin)611 static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio,
612 						   unsigned pin)
613 {
614 	unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
615 
616 	if (tmp & BIT(pin))
617 		return DRIVE_STRENGTH_BIT_HI;
618 
619 	return DRIVE_STRENGTH_BIT_LOW;
620 }
621 
at91_mux_sam9x60_get_slewrate(void __iomem * pio,unsigned pin)622 static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin)
623 {
624 	unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
625 
626 	if ((tmp & BIT(pin)))
627 		return SLEWRATE_BIT_ENA;
628 
629 	return SLEWRATE_BIT_DIS;
630 }
631 
set_drive_strength(void __iomem * reg,unsigned pin,u32 strength)632 static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
633 {
634 	unsigned tmp = readl_relaxed(reg);
635 	unsigned shift = two_bit_pin_value_shift_amount(pin);
636 
637 	tmp &= ~(DRIVE_STRENGTH_MASK  <<  shift);
638 	tmp |= strength << shift;
639 
640 	writel_relaxed(tmp, reg);
641 }
642 
at91_mux_sama5d3_set_drivestrength(void __iomem * pio,unsigned pin,u32 setting)643 static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
644 						u32 setting)
645 {
646 	/* do nothing if setting is zero */
647 	if (!setting)
648 		return;
649 
650 	/* strength is 1 to 1 with setting for SAMA5 */
651 	set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
652 }
653 
at91_mux_sam9x5_set_drivestrength(void __iomem * pio,unsigned pin,u32 setting)654 static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
655 						u32 setting)
656 {
657 	/* do nothing if setting is zero */
658 	if (!setting)
659 		return;
660 
661 	/* strength is inverse on SAM9x5s with our defines
662 	 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
663 	setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
664 
665 	set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
666 				setting);
667 }
668 
at91_mux_sam9x60_set_drivestrength(void __iomem * pio,unsigned pin,u32 setting)669 static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin,
670 					       u32 setting)
671 {
672 	unsigned int tmp;
673 
674 	if (setting <= DRIVE_STRENGTH_BIT_DEF ||
675 	    setting == DRIVE_STRENGTH_BIT_MED ||
676 	    setting > DRIVE_STRENGTH_BIT_HI)
677 		return;
678 
679 	tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
680 
681 	/* Strength is 0: low, 1: hi */
682 	if (setting == DRIVE_STRENGTH_BIT_LOW)
683 		tmp &= ~BIT(pin);
684 	else
685 		tmp |= BIT(pin);
686 
687 	writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1);
688 }
689 
at91_mux_sam9x60_set_slewrate(void __iomem * pio,unsigned pin,u32 setting)690 static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
691 					  u32 setting)
692 {
693 	unsigned int tmp;
694 
695 	if (setting < SLEWRATE_BIT_ENA || setting > SLEWRATE_BIT_DIS)
696 		return;
697 
698 	tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
699 
700 	if (setting == SLEWRATE_BIT_DIS)
701 		tmp &= ~BIT(pin);
702 	else
703 		tmp |= BIT(pin);
704 
705 	writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR);
706 }
707 
708 static const struct at91_pinctrl_mux_ops at91rm9200_ops = {
709 	.get_periph	= at91_mux_get_periph,
710 	.mux_A_periph	= at91_mux_set_A_periph,
711 	.mux_B_periph	= at91_mux_set_B_periph,
712 	.get_deglitch	= at91_mux_get_deglitch,
713 	.set_deglitch	= at91_mux_set_deglitch,
714 	.irq_type	= gpio_irq_type,
715 };
716 
717 static const struct at91_pinctrl_mux_ops at91sam9x5_ops = {
718 	.get_periph	= at91_mux_pio3_get_periph,
719 	.mux_A_periph	= at91_mux_pio3_set_A_periph,
720 	.mux_B_periph	= at91_mux_pio3_set_B_periph,
721 	.mux_C_periph	= at91_mux_pio3_set_C_periph,
722 	.mux_D_periph	= at91_mux_pio3_set_D_periph,
723 	.get_deglitch	= at91_mux_pio3_get_deglitch,
724 	.set_deglitch	= at91_mux_pio3_set_deglitch,
725 	.get_debounce	= at91_mux_pio3_get_debounce,
726 	.set_debounce	= at91_mux_pio3_set_debounce,
727 	.get_pulldown	= at91_mux_pio3_get_pulldown,
728 	.set_pulldown	= at91_mux_pio3_set_pulldown,
729 	.get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
730 	.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
731 	.get_drivestrength = at91_mux_sam9x5_get_drivestrength,
732 	.set_drivestrength = at91_mux_sam9x5_set_drivestrength,
733 	.irq_type	= alt_gpio_irq_type,
734 };
735 
736 static const struct at91_pinctrl_mux_ops sam9x60_ops = {
737 	.get_periph	= at91_mux_pio3_get_periph,
738 	.mux_A_periph	= at91_mux_pio3_set_A_periph,
739 	.mux_B_periph	= at91_mux_pio3_set_B_periph,
740 	.mux_C_periph	= at91_mux_pio3_set_C_periph,
741 	.mux_D_periph	= at91_mux_pio3_set_D_periph,
742 	.get_deglitch	= at91_mux_pio3_get_deglitch,
743 	.set_deglitch	= at91_mux_pio3_set_deglitch,
744 	.get_debounce	= at91_mux_pio3_get_debounce,
745 	.set_debounce	= at91_mux_pio3_set_debounce,
746 	.get_pulldown	= at91_mux_pio3_get_pulldown,
747 	.set_pulldown	= at91_mux_pio3_set_pulldown,
748 	.get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
749 	.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
750 	.get_drivestrength = at91_mux_sam9x60_get_drivestrength,
751 	.set_drivestrength = at91_mux_sam9x60_set_drivestrength,
752 	.get_slewrate   = at91_mux_sam9x60_get_slewrate,
753 	.set_slewrate   = at91_mux_sam9x60_set_slewrate,
754 	.irq_type	= alt_gpio_irq_type,
755 };
756 
757 static const struct at91_pinctrl_mux_ops sama5d3_ops = {
758 	.get_periph	= at91_mux_pio3_get_periph,
759 	.mux_A_periph	= at91_mux_pio3_set_A_periph,
760 	.mux_B_periph	= at91_mux_pio3_set_B_periph,
761 	.mux_C_periph	= at91_mux_pio3_set_C_periph,
762 	.mux_D_periph	= at91_mux_pio3_set_D_periph,
763 	.get_deglitch	= at91_mux_pio3_get_deglitch,
764 	.set_deglitch	= at91_mux_pio3_set_deglitch,
765 	.get_debounce	= at91_mux_pio3_get_debounce,
766 	.set_debounce	= at91_mux_pio3_set_debounce,
767 	.get_pulldown	= at91_mux_pio3_get_pulldown,
768 	.set_pulldown	= at91_mux_pio3_set_pulldown,
769 	.get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
770 	.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
771 	.get_drivestrength = at91_mux_sama5d3_get_drivestrength,
772 	.set_drivestrength = at91_mux_sama5d3_set_drivestrength,
773 	.irq_type	= alt_gpio_irq_type,
774 };
775 
at91_pin_dbg(const struct device * dev,const struct at91_pmx_pin * pin)776 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
777 {
778 	if (pin->mux) {
779 		dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n",
780 			pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
781 	} else {
782 		dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n",
783 			pin->bank + 'A', pin->pin, pin->conf);
784 	}
785 }
786 
pin_check_config(struct at91_pinctrl * info,const char * name,int index,const struct at91_pmx_pin * pin)787 static int pin_check_config(struct at91_pinctrl *info, const char *name,
788 			    int index, const struct at91_pmx_pin *pin)
789 {
790 	int mux;
791 
792 	/* check if it's a valid config */
793 	if (pin->bank >= gpio_banks) {
794 		dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
795 			name, index, pin->bank, gpio_banks);
796 		return -EINVAL;
797 	}
798 
799 	if (!gpio_chips[pin->bank]) {
800 		dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n",
801 			name, index, pin->bank);
802 		return -ENXIO;
803 	}
804 
805 	if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
806 		dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
807 			name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
808 		return -EINVAL;
809 	}
810 
811 	if (!pin->mux)
812 		return 0;
813 
814 	mux = pin->mux - 1;
815 
816 	if (mux >= info->nmux) {
817 		dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
818 			name, index, mux, info->nmux);
819 		return -EINVAL;
820 	}
821 
822 	if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
823 		dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
824 			name, index, mux, pin->bank + 'A', pin->pin);
825 		return -EINVAL;
826 	}
827 
828 	return 0;
829 }
830 
at91_mux_gpio_disable(void __iomem * pio,unsigned mask)831 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
832 {
833 	writel_relaxed(mask, pio + PIO_PDR);
834 }
835 
at91_mux_gpio_enable(void __iomem * pio,unsigned mask,bool input)836 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
837 {
838 	writel_relaxed(mask, pio + PIO_PER);
839 	writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
840 }
841 
at91_pmx_set(struct pinctrl_dev * pctldev,unsigned selector,unsigned group)842 static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
843 			unsigned group)
844 {
845 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
846 	const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
847 	const struct at91_pmx_pin *pin;
848 	uint32_t npins = info->groups[group].npins;
849 	int i, ret;
850 	unsigned mask;
851 	void __iomem *pio;
852 
853 	dev_dbg(info->dev, "enable function %s group %s\n",
854 		info->functions[selector].name, info->groups[group].name);
855 
856 	/* first check that all the pins of the group are valid with a valid
857 	 * parameter */
858 	for (i = 0; i < npins; i++) {
859 		pin = &pins_conf[i];
860 		ret = pin_check_config(info, info->groups[group].name, i, pin);
861 		if (ret)
862 			return ret;
863 	}
864 
865 	for (i = 0; i < npins; i++) {
866 		pin = &pins_conf[i];
867 		at91_pin_dbg(info->dev, pin);
868 		pio = pin_to_controller(info, pin->bank);
869 
870 		if (!pio)
871 			continue;
872 
873 		mask = pin_to_mask(pin->pin);
874 		at91_mux_disable_interrupt(pio, mask);
875 		switch (pin->mux) {
876 		case AT91_MUX_GPIO:
877 			at91_mux_gpio_enable(pio, mask, 1);
878 			break;
879 		case AT91_MUX_PERIPH_A:
880 			info->ops->mux_A_periph(pio, mask);
881 			break;
882 		case AT91_MUX_PERIPH_B:
883 			info->ops->mux_B_periph(pio, mask);
884 			break;
885 		case AT91_MUX_PERIPH_C:
886 			if (!info->ops->mux_C_periph)
887 				return -EINVAL;
888 			info->ops->mux_C_periph(pio, mask);
889 			break;
890 		case AT91_MUX_PERIPH_D:
891 			if (!info->ops->mux_D_periph)
892 				return -EINVAL;
893 			info->ops->mux_D_periph(pio, mask);
894 			break;
895 		}
896 		if (pin->mux)
897 			at91_mux_gpio_disable(pio, mask);
898 	}
899 
900 	return 0;
901 }
902 
at91_pmx_get_funcs_count(struct pinctrl_dev * pctldev)903 static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
904 {
905 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
906 
907 	return info->nfunctions;
908 }
909 
at91_pmx_get_func_name(struct pinctrl_dev * pctldev,unsigned selector)910 static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
911 					  unsigned selector)
912 {
913 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
914 
915 	return info->functions[selector].name;
916 }
917 
at91_pmx_get_groups(struct pinctrl_dev * pctldev,unsigned selector,const char * const ** groups,unsigned * const num_groups)918 static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
919 			       const char * const **groups,
920 			       unsigned * const num_groups)
921 {
922 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
923 
924 	*groups = info->functions[selector].groups;
925 	*num_groups = info->functions[selector].ngroups;
926 
927 	return 0;
928 }
929 
at91_gpio_request_enable(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned offset)930 static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
931 				    struct pinctrl_gpio_range *range,
932 				    unsigned offset)
933 {
934 	struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
935 	struct at91_gpio_chip *at91_chip;
936 	struct gpio_chip *chip;
937 	unsigned mask;
938 
939 	if (!range) {
940 		dev_err(npct->dev, "invalid range\n");
941 		return -EINVAL;
942 	}
943 	if (!range->gc) {
944 		dev_err(npct->dev, "missing GPIO chip in range\n");
945 		return -EINVAL;
946 	}
947 	chip = range->gc;
948 	at91_chip = gpiochip_get_data(chip);
949 
950 	dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
951 
952 	mask = 1 << (offset - chip->base);
953 
954 	dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
955 		offset, 'A' + range->id, offset - chip->base, mask);
956 
957 	writel_relaxed(mask, at91_chip->regbase + PIO_PER);
958 
959 	return 0;
960 }
961 
at91_gpio_disable_free(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned offset)962 static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
963 				   struct pinctrl_gpio_range *range,
964 				   unsigned offset)
965 {
966 	struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
967 
968 	dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
969 	/* Set the pin to some default state, GPIO is usually default */
970 }
971 
972 static const struct pinmux_ops at91_pmx_ops = {
973 	.get_functions_count	= at91_pmx_get_funcs_count,
974 	.get_function_name	= at91_pmx_get_func_name,
975 	.get_function_groups	= at91_pmx_get_groups,
976 	.set_mux		= at91_pmx_set,
977 	.gpio_request_enable	= at91_gpio_request_enable,
978 	.gpio_disable_free	= at91_gpio_disable_free,
979 };
980 
at91_pinconf_get(struct pinctrl_dev * pctldev,unsigned pin_id,unsigned long * config)981 static int at91_pinconf_get(struct pinctrl_dev *pctldev,
982 			     unsigned pin_id, unsigned long *config)
983 {
984 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
985 	void __iomem *pio;
986 	unsigned pin;
987 	int div;
988 	bool out;
989 
990 	*config = 0;
991 	dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
992 	pio = pin_to_controller(info, pin_to_bank(pin_id));
993 
994 	if (!pio)
995 		return -EINVAL;
996 
997 	pin = pin_id % MAX_NB_GPIO_PER_BANK;
998 
999 	if (at91_mux_get_multidrive(pio, pin))
1000 		*config |= MULTI_DRIVE;
1001 
1002 	if (at91_mux_get_pullup(pio, pin))
1003 		*config |= PULL_UP;
1004 
1005 	if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
1006 		*config |= DEGLITCH;
1007 	if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
1008 		*config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
1009 	if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
1010 		*config |= PULL_DOWN;
1011 	if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
1012 		*config |= DIS_SCHMIT;
1013 	if (info->ops->get_drivestrength)
1014 		*config |= (info->ops->get_drivestrength(pio, pin)
1015 				<< DRIVE_STRENGTH_SHIFT);
1016 	if (info->ops->get_slewrate)
1017 		*config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT);
1018 	if (at91_mux_get_output(pio, pin, &out))
1019 		*config |= OUTPUT | (out << OUTPUT_VAL_SHIFT);
1020 
1021 	return 0;
1022 }
1023 
at91_pinconf_set(struct pinctrl_dev * pctldev,unsigned pin_id,unsigned long * configs,unsigned num_configs)1024 static int at91_pinconf_set(struct pinctrl_dev *pctldev,
1025 			     unsigned pin_id, unsigned long *configs,
1026 			     unsigned num_configs)
1027 {
1028 	struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1029 	unsigned mask;
1030 	void __iomem *pio;
1031 	int i;
1032 	unsigned long config;
1033 	unsigned pin;
1034 
1035 	for (i = 0; i < num_configs; i++) {
1036 		config = configs[i];
1037 
1038 		dev_dbg(info->dev,
1039 			"%s:%d, pin_id=%d, config=0x%lx",
1040 			__func__, __LINE__, pin_id, config);
1041 		pio = pin_to_controller(info, pin_to_bank(pin_id));
1042 
1043 		if (!pio)
1044 			return -EINVAL;
1045 
1046 		pin = pin_id % MAX_NB_GPIO_PER_BANK;
1047 		mask = pin_to_mask(pin);
1048 
1049 		if (config & PULL_UP && config & PULL_DOWN)
1050 			return -EINVAL;
1051 
1052 		at91_mux_set_output(pio, mask, config & OUTPUT,
1053 				    (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
1054 		at91_mux_set_pullup(pio, mask, config & PULL_UP);
1055 		at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
1056 		if (info->ops->set_deglitch)
1057 			info->ops->set_deglitch(pio, mask, config & DEGLITCH);
1058 		if (info->ops->set_debounce)
1059 			info->ops->set_debounce(pio, mask, config & DEBOUNCE,
1060 				(config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
1061 		if (info->ops->set_pulldown)
1062 			info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
1063 		if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
1064 			info->ops->disable_schmitt_trig(pio, mask);
1065 		if (info->ops->set_drivestrength)
1066 			info->ops->set_drivestrength(pio, pin,
1067 				(config & DRIVE_STRENGTH)
1068 					>> DRIVE_STRENGTH_SHIFT);
1069 		if (info->ops->set_slewrate)
1070 			info->ops->set_slewrate(pio, pin,
1071 				(config & SLEWRATE) >> SLEWRATE_SHIFT);
1072 
1073 	} /* for each config */
1074 
1075 	return 0;
1076 }
1077 
1078 #define DBG_SHOW_FLAG(flag) do {		\
1079 	if (config & flag) {			\
1080 		if (num_conf)			\
1081 			seq_puts(s, "|");	\
1082 		seq_puts(s, #flag);		\
1083 		num_conf++;			\
1084 	}					\
1085 } while (0)
1086 
1087 #define DBG_SHOW_FLAG_MASKED(mask, flag, name) do { \
1088 	if ((config & mask) == flag) {		\
1089 		if (num_conf)			\
1090 			seq_puts(s, "|");	\
1091 		seq_puts(s, #name);		\
1092 		num_conf++;			\
1093 	}					\
1094 } while (0)
1095 
at91_pinconf_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned pin_id)1096 static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
1097 				   struct seq_file *s, unsigned pin_id)
1098 {
1099 	unsigned long config;
1100 	int val, num_conf = 0;
1101 
1102 	at91_pinconf_get(pctldev, pin_id, &config);
1103 
1104 	DBG_SHOW_FLAG(MULTI_DRIVE);
1105 	DBG_SHOW_FLAG(PULL_UP);
1106 	DBG_SHOW_FLAG(PULL_DOWN);
1107 	DBG_SHOW_FLAG(DIS_SCHMIT);
1108 	DBG_SHOW_FLAG(DEGLITCH);
1109 	DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
1110 			     DRIVE_STRENGTH_LOW);
1111 	DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
1112 			     DRIVE_STRENGTH_MED);
1113 	DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
1114 			     DRIVE_STRENGTH_HI);
1115 	DBG_SHOW_FLAG(SLEWRATE);
1116 	DBG_SHOW_FLAG(DEBOUNCE);
1117 	if (config & DEBOUNCE) {
1118 		val = config >> DEBOUNCE_VAL_SHIFT;
1119 		seq_printf(s, "(%d)", val);
1120 	}
1121 
1122 	return;
1123 }
1124 
at91_pinconf_group_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned group)1125 static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
1126 					 struct seq_file *s, unsigned group)
1127 {
1128 }
1129 
1130 static const struct pinconf_ops at91_pinconf_ops = {
1131 	.pin_config_get			= at91_pinconf_get,
1132 	.pin_config_set			= at91_pinconf_set,
1133 	.pin_config_dbg_show		= at91_pinconf_dbg_show,
1134 	.pin_config_group_dbg_show	= at91_pinconf_group_dbg_show,
1135 };
1136 
1137 static struct pinctrl_desc at91_pinctrl_desc = {
1138 	.pctlops	= &at91_pctrl_ops,
1139 	.pmxops		= &at91_pmx_ops,
1140 	.confops	= &at91_pinconf_ops,
1141 	.owner		= THIS_MODULE,
1142 };
1143 
1144 static const char *gpio_compat = "atmel,at91rm9200-gpio";
1145 
at91_pinctrl_child_count(struct at91_pinctrl * info,struct device_node * np)1146 static void at91_pinctrl_child_count(struct at91_pinctrl *info,
1147 				     struct device_node *np)
1148 {
1149 	struct device_node *child;
1150 
1151 	for_each_child_of_node(np, child) {
1152 		if (of_device_is_compatible(child, gpio_compat)) {
1153 			if (of_device_is_available(child))
1154 				info->nactive_banks++;
1155 		} else {
1156 			info->nfunctions++;
1157 			info->ngroups += of_get_child_count(child);
1158 		}
1159 	}
1160 }
1161 
at91_pinctrl_mux_mask(struct at91_pinctrl * info,struct device_node * np)1162 static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
1163 				 struct device_node *np)
1164 {
1165 	int ret = 0;
1166 	int size;
1167 	const __be32 *list;
1168 
1169 	list = of_get_property(np, "atmel,mux-mask", &size);
1170 	if (!list) {
1171 		dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1172 		return -EINVAL;
1173 	}
1174 
1175 	size /= sizeof(*list);
1176 	if (!size || size % gpio_banks) {
1177 		dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks);
1178 		return -EINVAL;
1179 	}
1180 	info->nmux = size / gpio_banks;
1181 
1182 	info->mux_mask = devm_kcalloc(info->dev, size, sizeof(u32),
1183 				      GFP_KERNEL);
1184 	if (!info->mux_mask)
1185 		return -ENOMEM;
1186 
1187 	ret = of_property_read_u32_array(np, "atmel,mux-mask",
1188 					  info->mux_mask, size);
1189 	if (ret)
1190 		dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1191 	return ret;
1192 }
1193 
at91_pinctrl_parse_groups(struct device_node * np,struct at91_pin_group * grp,struct at91_pinctrl * info,u32 index)1194 static int at91_pinctrl_parse_groups(struct device_node *np,
1195 				     struct at91_pin_group *grp,
1196 				     struct at91_pinctrl *info, u32 index)
1197 {
1198 	struct at91_pmx_pin *pin;
1199 	int size;
1200 	const __be32 *list;
1201 	int i, j;
1202 
1203 	dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
1204 
1205 	/* Initialise group */
1206 	grp->name = np->name;
1207 
1208 	/*
1209 	 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
1210 	 * do sanity check and calculate pins number
1211 	 */
1212 	list = of_get_property(np, "atmel,pins", &size);
1213 	/* we do not check return since it's safe node passed down */
1214 	size /= sizeof(*list);
1215 	if (!size || size % 4) {
1216 		dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1217 		return -EINVAL;
1218 	}
1219 
1220 	grp->npins = size / 4;
1221 	pin = grp->pins_conf = devm_kcalloc(info->dev,
1222 					    grp->npins,
1223 					    sizeof(struct at91_pmx_pin),
1224 					    GFP_KERNEL);
1225 	grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
1226 				 GFP_KERNEL);
1227 	if (!grp->pins_conf || !grp->pins)
1228 		return -ENOMEM;
1229 
1230 	for (i = 0, j = 0; i < size; i += 4, j++) {
1231 		pin->bank = be32_to_cpu(*list++);
1232 		pin->pin = be32_to_cpu(*list++);
1233 		grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
1234 		pin->mux = be32_to_cpu(*list++);
1235 		pin->conf = be32_to_cpu(*list++);
1236 
1237 		at91_pin_dbg(info->dev, pin);
1238 		pin++;
1239 	}
1240 
1241 	return 0;
1242 }
1243 
at91_pinctrl_parse_functions(struct device_node * np,struct at91_pinctrl * info,u32 index)1244 static int at91_pinctrl_parse_functions(struct device_node *np,
1245 					struct at91_pinctrl *info, u32 index)
1246 {
1247 	struct at91_pmx_func *func;
1248 	struct at91_pin_group *grp;
1249 	int ret;
1250 	static u32 grp_index;
1251 	u32 i = 0;
1252 
1253 	dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
1254 
1255 	func = &info->functions[index];
1256 
1257 	/* Initialise function */
1258 	func->name = np->name;
1259 	func->ngroups = of_get_child_count(np);
1260 	if (func->ngroups == 0) {
1261 		dev_err(info->dev, "no groups defined\n");
1262 		return -EINVAL;
1263 	}
1264 	func->groups = devm_kcalloc(info->dev,
1265 			func->ngroups, sizeof(char *), GFP_KERNEL);
1266 	if (!func->groups)
1267 		return -ENOMEM;
1268 
1269 	for_each_child_of_node_scoped(np, child) {
1270 		func->groups[i] = child->name;
1271 		grp = &info->groups[grp_index++];
1272 		ret = at91_pinctrl_parse_groups(child, grp, info, i++);
1273 		if (ret)
1274 			return ret;
1275 	}
1276 
1277 	return 0;
1278 }
1279 
1280 static const struct of_device_id at91_pinctrl_of_match[] = {
1281 	{ .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
1282 	{ .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
1283 	{ .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
1284 	{ .compatible = "microchip,sam9x60-pinctrl", .data = &sam9x60_ops },
1285 	{ /* sentinel */ }
1286 };
1287 
at91_pinctrl_probe_dt(struct platform_device * pdev,struct at91_pinctrl * info)1288 static int at91_pinctrl_probe_dt(struct platform_device *pdev,
1289 				 struct at91_pinctrl *info)
1290 {
1291 	struct device *dev = &pdev->dev;
1292 	int ret = 0;
1293 	int i, j, ngpio_chips_enabled = 0;
1294 	uint32_t *tmp;
1295 	struct device_node *np = dev->of_node;
1296 
1297 	if (!np)
1298 		return -ENODEV;
1299 
1300 	info->dev = &pdev->dev;
1301 	info->ops = device_get_match_data(&pdev->dev);
1302 	at91_pinctrl_child_count(info, np);
1303 
1304 	/*
1305 	 * We need all the GPIO drivers to probe FIRST, or we will not be able
1306 	 * to obtain references to the struct gpio_chip * for them, and we
1307 	 * need this to proceed.
1308 	 */
1309 	for (i = 0; i < MAX_GPIO_BANKS; i++)
1310 		if (gpio_chips[i])
1311 			ngpio_chips_enabled++;
1312 
1313 	if (ngpio_chips_enabled < info->nactive_banks)
1314 		return -EPROBE_DEFER;
1315 
1316 	ret = at91_pinctrl_mux_mask(info, np);
1317 	if (ret)
1318 		return ret;
1319 
1320 	dev_dbg(dev, "nmux = %d\n", info->nmux);
1321 
1322 	dev_dbg(dev, "mux-mask\n");
1323 	tmp = info->mux_mask;
1324 	for (i = 0; i < gpio_banks; i++) {
1325 		for (j = 0; j < info->nmux; j++, tmp++) {
1326 			dev_dbg(dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
1327 		}
1328 	}
1329 
1330 	dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
1331 	dev_dbg(dev, "ngroups = %d\n", info->ngroups);
1332 	info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions),
1333 				       GFP_KERNEL);
1334 	if (!info->functions)
1335 		return -ENOMEM;
1336 
1337 	info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups),
1338 				    GFP_KERNEL);
1339 	if (!info->groups)
1340 		return -ENOMEM;
1341 
1342 	dev_dbg(dev, "nbanks = %d\n", gpio_banks);
1343 	dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
1344 	dev_dbg(dev, "ngroups = %d\n", info->ngroups);
1345 
1346 	i = 0;
1347 
1348 	for_each_child_of_node_scoped(np, child) {
1349 		if (of_device_is_compatible(child, gpio_compat))
1350 			continue;
1351 		ret = at91_pinctrl_parse_functions(child, info, i++);
1352 		if (ret)
1353 			return dev_err_probe(dev, ret, "failed to parse function\n");
1354 	}
1355 
1356 	return 0;
1357 }
1358 
at91_pinctrl_probe(struct platform_device * pdev)1359 static int at91_pinctrl_probe(struct platform_device *pdev)
1360 {
1361 	struct device *dev = &pdev->dev;
1362 	struct at91_pinctrl *info;
1363 	struct pinctrl_pin_desc *pdesc;
1364 	int ret, i, j, k;
1365 
1366 	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
1367 	if (!info)
1368 		return -ENOMEM;
1369 
1370 	ret = at91_pinctrl_probe_dt(pdev, info);
1371 	if (ret)
1372 		return ret;
1373 
1374 	at91_pinctrl_desc.name = dev_name(dev);
1375 	at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK;
1376 	at91_pinctrl_desc.pins = pdesc =
1377 		devm_kcalloc(dev, at91_pinctrl_desc.npins, sizeof(*pdesc), GFP_KERNEL);
1378 	if (!at91_pinctrl_desc.pins)
1379 		return -ENOMEM;
1380 
1381 	for (i = 0, k = 0; i < gpio_banks; i++) {
1382 		char **names;
1383 
1384 		names = devm_kasprintf_strarray(dev, "pio", MAX_NB_GPIO_PER_BANK);
1385 		if (IS_ERR(names))
1386 			return PTR_ERR(names);
1387 
1388 		for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1389 			char *name = names[j];
1390 
1391 			strreplace(name, '-', i + 'A');
1392 
1393 			pdesc->number = k;
1394 			pdesc->name = name;
1395 			pdesc++;
1396 		}
1397 	}
1398 
1399 	platform_set_drvdata(pdev, info);
1400 	info->pctl = devm_pinctrl_register(dev, &at91_pinctrl_desc, info);
1401 	if (IS_ERR(info->pctl))
1402 		return dev_err_probe(dev, PTR_ERR(info->pctl), "could not register AT91 pinctrl driver\n");
1403 
1404 	/* We will handle a range of GPIO pins */
1405 	for (i = 0; i < gpio_banks; i++)
1406 		if (gpio_chips[i]) {
1407 			pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1408 			gpiochip_add_pin_range(&gpio_chips[i]->chip, dev_name(info->pctl->dev), 0,
1409 				gpio_chips[i]->range.pin_base, gpio_chips[i]->range.npins);
1410 		}
1411 
1412 	dev_info(dev, "initialized AT91 pinctrl driver\n");
1413 
1414 	return 0;
1415 }
1416 
at91_gpio_get_direction(struct gpio_chip * chip,unsigned offset)1417 static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1418 {
1419 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1420 	void __iomem *pio = at91_gpio->regbase;
1421 	unsigned mask = 1 << offset;
1422 	u32 osr;
1423 
1424 	osr = readl_relaxed(pio + PIO_OSR);
1425 	if (osr & mask)
1426 		return GPIO_LINE_DIRECTION_OUT;
1427 
1428 	return GPIO_LINE_DIRECTION_IN;
1429 }
1430 
at91_gpio_direction_input(struct gpio_chip * chip,unsigned offset)1431 static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1432 {
1433 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1434 	void __iomem *pio = at91_gpio->regbase;
1435 	unsigned mask = 1 << offset;
1436 
1437 	writel_relaxed(mask, pio + PIO_ODR);
1438 	return 0;
1439 }
1440 
at91_gpio_get(struct gpio_chip * chip,unsigned offset)1441 static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1442 {
1443 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1444 	void __iomem *pio = at91_gpio->regbase;
1445 	unsigned mask = 1 << offset;
1446 	u32 pdsr;
1447 
1448 	pdsr = readl_relaxed(pio + PIO_PDSR);
1449 	return (pdsr & mask) != 0;
1450 }
1451 
at91_gpio_set(struct gpio_chip * chip,unsigned offset,int val)1452 static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1453 				int val)
1454 {
1455 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1456 	void __iomem *pio = at91_gpio->regbase;
1457 	unsigned mask = 1 << offset;
1458 
1459 	writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1460 }
1461 
at91_gpio_set_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)1462 static void at91_gpio_set_multiple(struct gpio_chip *chip,
1463 				      unsigned long *mask, unsigned long *bits)
1464 {
1465 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1466 	void __iomem *pio = at91_gpio->regbase;
1467 
1468 #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
1469 	/* Mask additionally to ngpio as not all GPIO controllers have 32 pins */
1470 	uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio);
1471 	uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio);
1472 
1473 	writel_relaxed(set_mask, pio + PIO_SODR);
1474 	writel_relaxed(clear_mask, pio + PIO_CODR);
1475 }
1476 
at91_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int val)1477 static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1478 				int val)
1479 {
1480 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1481 	void __iomem *pio = at91_gpio->regbase;
1482 	unsigned mask = 1 << offset;
1483 
1484 	writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1485 	writel_relaxed(mask, pio + PIO_OER);
1486 
1487 	return 0;
1488 }
1489 
1490 #ifdef CONFIG_DEBUG_FS
at91_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)1491 static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1492 {
1493 	enum at91_mux mode;
1494 	int i;
1495 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1496 	void __iomem *pio = at91_gpio->regbase;
1497 	const char *gpio_label;
1498 
1499 	for_each_requested_gpio(chip, i, gpio_label) {
1500 		unsigned mask = pin_to_mask(i);
1501 
1502 		mode = at91_gpio->ops->get_periph(pio, mask);
1503 		seq_printf(s, "[%s] GPIO%s%d: ",
1504 			   gpio_label, chip->label, i);
1505 		if (mode == AT91_MUX_GPIO) {
1506 			seq_printf(s, "[gpio] ");
1507 			seq_printf(s, "%s ",
1508 				      readl_relaxed(pio + PIO_OSR) & mask ?
1509 				      "output" : "input");
1510 			seq_printf(s, "%s\n",
1511 				      readl_relaxed(pio + PIO_PDSR) & mask ?
1512 				      "set" : "clear");
1513 		} else {
1514 			seq_printf(s, "[periph %c]\n",
1515 				   mode + 'A' - 1);
1516 		}
1517 	}
1518 }
1519 #else
1520 #define at91_gpio_dbg_show	NULL
1521 #endif
1522 
gpio_irq_request_resources(struct irq_data * d)1523 static int gpio_irq_request_resources(struct irq_data *d)
1524 {
1525 	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1526 
1527 	return gpiochip_lock_as_irq(&at91_gpio->chip, irqd_to_hwirq(d));
1528 }
1529 
gpio_irq_release_resources(struct irq_data * d)1530 static void gpio_irq_release_resources(struct irq_data *d)
1531 {
1532 	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1533 
1534 	gpiochip_unlock_as_irq(&at91_gpio->chip, irqd_to_hwirq(d));
1535 }
1536 
1537 /* Several AIC controller irqs are dispatched through this GPIO handler.
1538  * To use any AT91_PIN_* as an externally triggered IRQ, first call
1539  * at91_set_gpio_input() then maybe enable its glitch filter.
1540  * Then just request_irq() with the pin ID; it works like any ARM IRQ
1541  * handler.
1542  * First implementation always triggers on rising and falling edges
1543  * whereas the newer PIO3 can be additionally configured to trigger on
1544  * level, edge with any polarity.
1545  *
1546  * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1547  * configuring them with at91_set_a_periph() or at91_set_b_periph().
1548  * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1549  */
1550 
gpio_irq_mask(struct irq_data * d)1551 static void gpio_irq_mask(struct irq_data *d)
1552 {
1553 	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1554 	void __iomem	*pio = at91_gpio->regbase;
1555 	unsigned	mask = 1 << d->hwirq;
1556 	unsigned        gpio = irqd_to_hwirq(d);
1557 
1558 	gpiochip_disable_irq(&at91_gpio->chip, gpio);
1559 
1560 	if (pio)
1561 		writel_relaxed(mask, pio + PIO_IDR);
1562 }
1563 
gpio_irq_unmask(struct irq_data * d)1564 static void gpio_irq_unmask(struct irq_data *d)
1565 {
1566 	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1567 	void __iomem	*pio = at91_gpio->regbase;
1568 	unsigned	mask = 1 << d->hwirq;
1569 	unsigned        gpio = irqd_to_hwirq(d);
1570 
1571 	gpiochip_enable_irq(&at91_gpio->chip, gpio);
1572 
1573 	if (pio)
1574 		writel_relaxed(mask, pio + PIO_IER);
1575 }
1576 
gpio_irq_type(struct irq_data * d,unsigned type)1577 static int gpio_irq_type(struct irq_data *d, unsigned type)
1578 {
1579 	switch (type) {
1580 	case IRQ_TYPE_NONE:
1581 	case IRQ_TYPE_EDGE_BOTH:
1582 		return 0;
1583 	default:
1584 		return -EINVAL;
1585 	}
1586 }
1587 
1588 /* Alternate irq type for PIO3 support */
alt_gpio_irq_type(struct irq_data * d,unsigned type)1589 static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1590 {
1591 	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1592 	void __iomem	*pio = at91_gpio->regbase;
1593 	unsigned	mask = 1 << d->hwirq;
1594 
1595 	switch (type) {
1596 	case IRQ_TYPE_EDGE_RISING:
1597 		irq_set_handler_locked(d, handle_simple_irq);
1598 		writel_relaxed(mask, pio + PIO_ESR);
1599 		writel_relaxed(mask, pio + PIO_REHLSR);
1600 		break;
1601 	case IRQ_TYPE_EDGE_FALLING:
1602 		irq_set_handler_locked(d, handle_simple_irq);
1603 		writel_relaxed(mask, pio + PIO_ESR);
1604 		writel_relaxed(mask, pio + PIO_FELLSR);
1605 		break;
1606 	case IRQ_TYPE_LEVEL_LOW:
1607 		irq_set_handler_locked(d, handle_level_irq);
1608 		writel_relaxed(mask, pio + PIO_LSR);
1609 		writel_relaxed(mask, pio + PIO_FELLSR);
1610 		break;
1611 	case IRQ_TYPE_LEVEL_HIGH:
1612 		irq_set_handler_locked(d, handle_level_irq);
1613 		writel_relaxed(mask, pio + PIO_LSR);
1614 		writel_relaxed(mask, pio + PIO_REHLSR);
1615 		break;
1616 	case IRQ_TYPE_EDGE_BOTH:
1617 		/*
1618 		 * disable additional interrupt modes:
1619 		 * fall back to default behavior
1620 		 */
1621 		irq_set_handler_locked(d, handle_simple_irq);
1622 		writel_relaxed(mask, pio + PIO_AIMDR);
1623 		return 0;
1624 	case IRQ_TYPE_NONE:
1625 	default:
1626 		pr_warn("AT91: No type for GPIO irq offset %d\n", d->irq);
1627 		return -EINVAL;
1628 	}
1629 
1630 	/* enable additional interrupt modes */
1631 	writel_relaxed(mask, pio + PIO_AIMER);
1632 
1633 	return 0;
1634 }
1635 
gpio_irq_ack(struct irq_data * d)1636 static void gpio_irq_ack(struct irq_data *d)
1637 {
1638 	/* the interrupt is already cleared before by reading ISR */
1639 }
1640 
gpio_irq_set_wake(struct irq_data * d,unsigned state)1641 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1642 {
1643 	struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1644 	unsigned mask = 1 << d->hwirq;
1645 
1646 	if (state)
1647 		at91_gpio->wakeups |= mask;
1648 	else
1649 		at91_gpio->wakeups &= ~mask;
1650 
1651 	irq_set_irq_wake(at91_gpio->pioc_virq, state);
1652 
1653 	return 0;
1654 }
1655 
at91_gpio_suspend(struct device * dev)1656 static int at91_gpio_suspend(struct device *dev)
1657 {
1658 	struct at91_gpio_chip *at91_chip = dev_get_drvdata(dev);
1659 	void __iomem *pio = at91_chip->regbase;
1660 
1661 	at91_chip->backups = readl_relaxed(pio + PIO_IMR);
1662 	writel_relaxed(at91_chip->backups, pio + PIO_IDR);
1663 	writel_relaxed(at91_chip->wakeups, pio + PIO_IER);
1664 
1665 	if (!at91_chip->wakeups)
1666 		clk_disable_unprepare(at91_chip->clock);
1667 	else
1668 		dev_dbg(dev, "GPIO-%c may wake for %08x\n",
1669 			'A' + at91_chip->id, at91_chip->wakeups);
1670 
1671 	return 0;
1672 }
1673 
at91_gpio_resume(struct device * dev)1674 static int at91_gpio_resume(struct device *dev)
1675 {
1676 	struct at91_gpio_chip *at91_chip = dev_get_drvdata(dev);
1677 	void __iomem *pio = at91_chip->regbase;
1678 
1679 	if (!at91_chip->wakeups)
1680 		clk_prepare_enable(at91_chip->clock);
1681 
1682 	writel_relaxed(at91_chip->wakeups, pio + PIO_IDR);
1683 	writel_relaxed(at91_chip->backups, pio + PIO_IER);
1684 
1685 	return 0;
1686 }
1687 
gpio_irq_handler(struct irq_desc * desc)1688 static void gpio_irq_handler(struct irq_desc *desc)
1689 {
1690 	struct irq_chip *chip = irq_desc_get_chip(desc);
1691 	struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
1692 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gpio_chip);
1693 	void __iomem	*pio = at91_gpio->regbase;
1694 	unsigned long	isr;
1695 	int		n;
1696 
1697 	chained_irq_enter(chip, desc);
1698 	for (;;) {
1699 		/* Reading ISR acks pending (edge triggered) GPIO interrupts.
1700 		 * When there are none pending, we're finished unless we need
1701 		 * to process multiple banks (like ID_PIOCDE on sam9263).
1702 		 */
1703 		isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1704 		if (!isr) {
1705 			if (!at91_gpio->next)
1706 				break;
1707 			at91_gpio = at91_gpio->next;
1708 			pio = at91_gpio->regbase;
1709 			gpio_chip = &at91_gpio->chip;
1710 			continue;
1711 		}
1712 
1713 		for_each_set_bit(n, &isr, BITS_PER_LONG)
1714 			generic_handle_domain_irq(gpio_chip->irq.domain, n);
1715 	}
1716 	chained_irq_exit(chip, desc);
1717 	/* now it may re-trigger */
1718 }
1719 
at91_gpio_of_irq_setup(struct platform_device * pdev,struct at91_gpio_chip * at91_gpio)1720 static int at91_gpio_of_irq_setup(struct platform_device *pdev,
1721 				  struct at91_gpio_chip *at91_gpio)
1722 {
1723 	struct device		*dev = &pdev->dev;
1724 	struct gpio_chip	*gpiochip_prev = NULL;
1725 	struct at91_gpio_chip   *prev = NULL;
1726 	struct irq_data		*d = irq_get_irq_data(at91_gpio->pioc_virq);
1727 	struct irq_chip		*gpio_irqchip;
1728 	struct gpio_irq_chip	*girq;
1729 	int i;
1730 
1731 	gpio_irqchip = devm_kzalloc(dev, sizeof(*gpio_irqchip), GFP_KERNEL);
1732 	if (!gpio_irqchip)
1733 		return -ENOMEM;
1734 
1735 	at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1736 
1737 	gpio_irqchip->name = "GPIO";
1738 	gpio_irqchip->irq_request_resources = gpio_irq_request_resources;
1739 	gpio_irqchip->irq_release_resources = gpio_irq_release_resources;
1740 	gpio_irqchip->irq_ack = gpio_irq_ack;
1741 	gpio_irqchip->irq_disable = gpio_irq_mask;
1742 	gpio_irqchip->irq_mask = gpio_irq_mask;
1743 	gpio_irqchip->irq_unmask = gpio_irq_unmask;
1744 	gpio_irqchip->irq_set_wake = pm_ptr(gpio_irq_set_wake);
1745 	gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type;
1746 	gpio_irqchip->flags = IRQCHIP_IMMUTABLE;
1747 
1748 	/* Disable irqs of this PIO controller */
1749 	writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1750 
1751 	/*
1752 	 * Let the generic code handle this edge IRQ, the chained
1753 	 * handler will perform the actual work of handling the parent
1754 	 * interrupt.
1755 	 */
1756 	girq = &at91_gpio->chip.irq;
1757 	gpio_irq_chip_set_chip(girq, gpio_irqchip);
1758 	girq->default_type = IRQ_TYPE_NONE;
1759 	girq->handler = handle_edge_irq;
1760 
1761 	/*
1762 	 * The top level handler handles one bank of GPIOs, except
1763 	 * on some SoC it can handle up to three...
1764 	 * We only set up the handler for the first of the list.
1765 	 */
1766 	gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq);
1767 	if (!gpiochip_prev) {
1768 		girq->parent_handler = gpio_irq_handler;
1769 		girq->num_parents = 1;
1770 		girq->parents = devm_kcalloc(dev, girq->num_parents,
1771 					     sizeof(*girq->parents),
1772 					     GFP_KERNEL);
1773 		if (!girq->parents)
1774 			return -ENOMEM;
1775 		girq->parents[0] = at91_gpio->pioc_virq;
1776 		return 0;
1777 	}
1778 
1779 	prev = gpiochip_get_data(gpiochip_prev);
1780 	/* we can only have 2 banks before */
1781 	for (i = 0; i < 2; i++) {
1782 		if (prev->next) {
1783 			prev = prev->next;
1784 		} else {
1785 			prev->next = at91_gpio;
1786 			return 0;
1787 		}
1788 	}
1789 
1790 	return -EINVAL;
1791 }
1792 
1793 /* This structure is replicated for each GPIO block allocated at probe time */
1794 static const struct gpio_chip at91_gpio_template = {
1795 	.request		= gpiochip_generic_request,
1796 	.free			= gpiochip_generic_free,
1797 	.get_direction		= at91_gpio_get_direction,
1798 	.direction_input	= at91_gpio_direction_input,
1799 	.get			= at91_gpio_get,
1800 	.direction_output	= at91_gpio_direction_output,
1801 	.set			= at91_gpio_set,
1802 	.set_multiple		= at91_gpio_set_multiple,
1803 	.dbg_show		= at91_gpio_dbg_show,
1804 	.can_sleep		= false,
1805 	.ngpio			= MAX_NB_GPIO_PER_BANK,
1806 };
1807 
1808 static const struct of_device_id at91_gpio_of_match[] = {
1809 	{ .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1810 	{ .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1811 	{ .compatible = "microchip,sam9x60-gpio", .data = &sam9x60_ops },
1812 	{ /* sentinel */ }
1813 };
1814 
at91_gpio_probe(struct platform_device * pdev)1815 static int at91_gpio_probe(struct platform_device *pdev)
1816 {
1817 	struct device *dev = &pdev->dev;
1818 	struct device_node *np = dev->of_node;
1819 	struct at91_gpio_chip *at91_chip = NULL;
1820 	struct gpio_chip *chip;
1821 	struct pinctrl_gpio_range *range;
1822 	int ret = 0;
1823 	int irq, i;
1824 	int alias_idx = of_alias_get_id(np, "gpio");
1825 	uint32_t ngpio;
1826 	char **names;
1827 
1828 	BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1829 	if (gpio_chips[alias_idx])
1830 		return dev_err_probe(dev, -EBUSY, "%d slot is occupied.\n", alias_idx);
1831 
1832 	irq = platform_get_irq(pdev, 0);
1833 	if (irq < 0)
1834 		return irq;
1835 
1836 	at91_chip = devm_kzalloc(dev, sizeof(*at91_chip), GFP_KERNEL);
1837 	if (!at91_chip)
1838 		return -ENOMEM;
1839 
1840 	at91_chip->regbase = devm_platform_ioremap_resource(pdev, 0);
1841 	if (IS_ERR(at91_chip->regbase))
1842 		return PTR_ERR(at91_chip->regbase);
1843 
1844 	at91_chip->ops = device_get_match_data(dev);
1845 	at91_chip->pioc_virq = irq;
1846 
1847 	at91_chip->clock = devm_clk_get_enabled(dev, NULL);
1848 	if (IS_ERR(at91_chip->clock))
1849 		return dev_err_probe(dev, PTR_ERR(at91_chip->clock), "failed to get clock, ignoring.\n");
1850 
1851 	at91_chip->chip = at91_gpio_template;
1852 	at91_chip->id = alias_idx;
1853 
1854 	chip = &at91_chip->chip;
1855 	chip->label = dev_name(dev);
1856 	chip->parent = dev;
1857 	chip->owner = THIS_MODULE;
1858 	chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1859 
1860 	if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1861 		if (ngpio >= MAX_NB_GPIO_PER_BANK)
1862 			dev_err(dev, "at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1863 				alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1864 		else
1865 			chip->ngpio = ngpio;
1866 	}
1867 
1868 	names = devm_kasprintf_strarray(dev, "pio", chip->ngpio);
1869 	if (IS_ERR(names))
1870 		return PTR_ERR(names);
1871 
1872 	for (i = 0; i < chip->ngpio; i++)
1873 		strreplace(names[i], '-', alias_idx + 'A');
1874 
1875 	chip->names = (const char *const *)names;
1876 
1877 	range = &at91_chip->range;
1878 	range->name = chip->label;
1879 	range->id = alias_idx;
1880 	range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1881 
1882 	range->npins = chip->ngpio;
1883 	range->gc = chip;
1884 
1885 	ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1886 	if (ret)
1887 		return ret;
1888 
1889 	ret = gpiochip_add_data(chip, at91_chip);
1890 	if (ret)
1891 		return ret;
1892 
1893 	gpio_chips[alias_idx] = at91_chip;
1894 	platform_set_drvdata(pdev, at91_chip);
1895 	gpio_banks = max(gpio_banks, alias_idx + 1);
1896 
1897 	dev_info(dev, "at address %p\n", at91_chip->regbase);
1898 
1899 	return 0;
1900 }
1901 
1902 static DEFINE_NOIRQ_DEV_PM_OPS(at91_gpio_pm_ops, at91_gpio_suspend, at91_gpio_resume);
1903 
1904 static struct platform_driver at91_gpio_driver = {
1905 	.driver = {
1906 		.name = "gpio-at91",
1907 		.of_match_table = at91_gpio_of_match,
1908 		.pm = pm_sleep_ptr(&at91_gpio_pm_ops),
1909 	},
1910 	.probe = at91_gpio_probe,
1911 };
1912 
1913 static struct platform_driver at91_pinctrl_driver = {
1914 	.driver = {
1915 		.name = "pinctrl-at91",
1916 		.of_match_table = at91_pinctrl_of_match,
1917 	},
1918 	.probe = at91_pinctrl_probe,
1919 };
1920 
1921 static struct platform_driver * const drivers[] = {
1922 	&at91_gpio_driver,
1923 	&at91_pinctrl_driver,
1924 };
1925 
at91_pinctrl_init(void)1926 static int __init at91_pinctrl_init(void)
1927 {
1928 	return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1929 }
1930 arch_initcall(at91_pinctrl_init);
1931