1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ASIX AX8817X based USB 2.0 Ethernet Devices 4 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com> 5 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net> 6 * Copyright (C) 2006 James Painter <jamie.painter@iname.com> 7 * Copyright (c) 2002-2003 TiVo Inc. 8 */ 9 10 #include "asix.h" 11 12 #define PHY_MODE_MARVELL 0x0000 13 #define MII_MARVELL_LED_CTRL 0x0018 14 #define MII_MARVELL_STATUS 0x001b 15 #define MII_MARVELL_CTRL 0x0014 16 17 #define MARVELL_LED_MANUAL 0x0019 18 19 #define MARVELL_STATUS_HWCFG 0x0004 20 21 #define MARVELL_CTRL_TXDELAY 0x0002 22 #define MARVELL_CTRL_RXDELAY 0x0080 23 24 #define PHY_MODE_RTL8211CL 0x000C 25 26 #define AX88772A_PHY14H 0x14 27 #define AX88772A_PHY14H_DEFAULT 0x442C 28 29 #define AX88772A_PHY15H 0x15 30 #define AX88772A_PHY15H_DEFAULT 0x03C8 31 32 #define AX88772A_PHY16H 0x16 33 #define AX88772A_PHY16H_DEFAULT 0x4044 34 35 struct ax88172_int_data { 36 __le16 res1; 37 u8 link; 38 __le16 res2; 39 u8 status; 40 __le16 res3; 41 } __packed; 42 43 static void asix_status(struct usbnet *dev, struct urb *urb) 44 { 45 struct ax88172_int_data *event; 46 int link; 47 48 if (urb->actual_length < 8) 49 return; 50 51 event = urb->transfer_buffer; 52 link = event->link & 0x01; 53 if (netif_carrier_ok(dev->net) != link) { 54 usbnet_link_change(dev, link, 1); 55 netdev_dbg(dev->net, "Link Status is: %d\n", link); 56 } 57 } 58 59 static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr) 60 { 61 if (is_valid_ether_addr(addr)) { 62 eth_hw_addr_set(dev->net, addr); 63 } else { 64 netdev_info(dev->net, "invalid hw address, using random\n"); 65 eth_hw_addr_random(dev->net); 66 } 67 } 68 69 /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */ 70 static u32 asix_get_phyid(struct usbnet *dev) 71 { 72 int phy_reg; 73 u32 phy_id; 74 int i; 75 76 /* Poll for the rare case the FW or phy isn't ready yet. */ 77 for (i = 0; i < 100; i++) { 78 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1); 79 if (phy_reg < 0) 80 return 0; 81 if (phy_reg != 0 && phy_reg != 0xFFFF) 82 break; 83 mdelay(1); 84 } 85 86 if (phy_reg <= 0 || phy_reg == 0xFFFF) 87 return 0; 88 89 phy_id = (phy_reg & 0xffff) << 16; 90 91 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2); 92 if (phy_reg < 0) 93 return 0; 94 95 phy_id |= (phy_reg & 0xffff); 96 97 return phy_id; 98 } 99 100 /* We need to override some ethtool_ops so we require our 101 own structure so we don't interfere with other usbnet 102 devices that may be connected at the same time. */ 103 static const struct ethtool_ops ax88172_ethtool_ops = { 104 .get_drvinfo = usbnet_get_drvinfo, 105 .get_link = usbnet_get_link, 106 .get_msglevel = usbnet_get_msglevel, 107 .set_msglevel = usbnet_set_msglevel, 108 .get_wol = asix_get_wol, 109 .set_wol = asix_set_wol, 110 .get_eeprom_len = asix_get_eeprom_len, 111 .get_eeprom = asix_get_eeprom, 112 .set_eeprom = asix_set_eeprom, 113 .nway_reset = usbnet_nway_reset, 114 .get_link_ksettings = usbnet_get_link_ksettings_mii, 115 .set_link_ksettings = usbnet_set_link_ksettings_mii, 116 }; 117 118 static void ax88172_set_multicast(struct net_device *net) 119 { 120 struct usbnet *dev = netdev_priv(net); 121 struct asix_data *data = (struct asix_data *)&dev->data; 122 u8 rx_ctl = 0x8c; 123 124 if (net->flags & IFF_PROMISC) { 125 rx_ctl |= 0x01; 126 } else if (net->flags & IFF_ALLMULTI || 127 netdev_mc_count(net) > AX_MAX_MCAST) { 128 rx_ctl |= 0x02; 129 } else if (netdev_mc_empty(net)) { 130 /* just broadcast and directed */ 131 } else { 132 /* We use the 20 byte dev->data 133 * for our 8 byte filter buffer 134 * to avoid allocating memory that 135 * is tricky to free later */ 136 struct netdev_hw_addr *ha; 137 u32 crc_bits; 138 139 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE); 140 141 /* Build the multicast hash filter. */ 142 netdev_for_each_mc_addr(ha, net) { 143 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26; 144 data->multi_filter[crc_bits >> 3] |= 145 1 << (crc_bits & 7); 146 } 147 148 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0, 149 AX_MCAST_FILTER_SIZE, data->multi_filter); 150 151 rx_ctl |= 0x10; 152 } 153 154 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL); 155 } 156 157 static int ax88172_link_reset(struct usbnet *dev) 158 { 159 u8 mode; 160 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 161 162 mii_check_media(&dev->mii, 1, 1); 163 mii_ethtool_gset(&dev->mii, &ecmd); 164 mode = AX88172_MEDIUM_DEFAULT; 165 166 if (ecmd.duplex != DUPLEX_FULL) 167 mode |= ~AX88172_MEDIUM_FD; 168 169 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", 170 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode); 171 172 asix_write_medium_mode(dev, mode, 0); 173 174 return 0; 175 } 176 177 static const struct net_device_ops ax88172_netdev_ops = { 178 .ndo_open = usbnet_open, 179 .ndo_stop = usbnet_stop, 180 .ndo_start_xmit = usbnet_start_xmit, 181 .ndo_tx_timeout = usbnet_tx_timeout, 182 .ndo_change_mtu = usbnet_change_mtu, 183 .ndo_get_stats64 = dev_get_tstats64, 184 .ndo_set_mac_address = eth_mac_addr, 185 .ndo_validate_addr = eth_validate_addr, 186 .ndo_eth_ioctl = usbnet_mii_ioctl, 187 .ndo_set_rx_mode = ax88172_set_multicast, 188 }; 189 190 static void asix_phy_reset(struct usbnet *dev, unsigned int reset_bits) 191 { 192 unsigned int timeout = 5000; 193 194 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits); 195 196 /* give phy_id a chance to process reset */ 197 udelay(500); 198 199 /* See IEEE 802.3 "22.2.4.1.1 Reset": 500ms max */ 200 while (timeout--) { 201 if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR) 202 & BMCR_RESET) 203 udelay(100); 204 else 205 return; 206 } 207 208 netdev_err(dev->net, "BMCR_RESET timeout on phy_id %d\n", 209 dev->mii.phy_id); 210 } 211 212 static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf) 213 { 214 int ret = 0; 215 u8 buf[ETH_ALEN] = {0}; 216 int i; 217 unsigned long gpio_bits = dev->driver_info->data; 218 219 ret = usbnet_get_endpoints(dev, intf); 220 if (ret) 221 goto out; 222 223 /* Toggle the GPIOs in a manufacturer/model specific way */ 224 for (i = 2; i >= 0; i--) { 225 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, 226 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL, 0); 227 if (ret < 0) 228 goto out; 229 msleep(5); 230 } 231 232 ret = asix_write_rx_ctl(dev, 0x80, 0); 233 if (ret < 0) 234 goto out; 235 236 /* Get the MAC address */ 237 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, 238 0, 0, ETH_ALEN, buf, 0); 239 if (ret < 0) { 240 netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n", 241 ret); 242 goto out; 243 } 244 245 asix_set_netdev_dev_addr(dev, buf); 246 247 /* Initialize MII structure */ 248 dev->mii.dev = dev->net; 249 dev->mii.mdio_read = asix_mdio_read; 250 dev->mii.mdio_write = asix_mdio_write; 251 dev->mii.phy_id_mask = 0x3f; 252 dev->mii.reg_num_mask = 0x1f; 253 254 dev->mii.phy_id = asix_read_phy_addr(dev, true); 255 if (dev->mii.phy_id < 0) 256 return dev->mii.phy_id; 257 258 dev->net->netdev_ops = &ax88172_netdev_ops; 259 dev->net->ethtool_ops = &ax88172_ethtool_ops; 260 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */ 261 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */ 262 263 asix_phy_reset(dev, BMCR_RESET); 264 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, 265 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); 266 mii_nway_restart(&dev->mii); 267 268 return 0; 269 270 out: 271 return ret; 272 } 273 274 static void ax88772_ethtool_get_strings(struct net_device *netdev, u32 sset, 275 u8 *data) 276 { 277 switch (sset) { 278 case ETH_SS_TEST: 279 net_selftest_get_strings(data); 280 break; 281 } 282 } 283 284 static int ax88772_ethtool_get_sset_count(struct net_device *ndev, int sset) 285 { 286 switch (sset) { 287 case ETH_SS_TEST: 288 return net_selftest_get_count(); 289 default: 290 return -EOPNOTSUPP; 291 } 292 } 293 294 static void ax88772_ethtool_get_pauseparam(struct net_device *ndev, 295 struct ethtool_pauseparam *pause) 296 { 297 struct usbnet *dev = netdev_priv(ndev); 298 struct asix_common_private *priv = dev->driver_priv; 299 300 phylink_ethtool_get_pauseparam(priv->phylink, pause); 301 } 302 303 static int ax88772_ethtool_set_pauseparam(struct net_device *ndev, 304 struct ethtool_pauseparam *pause) 305 { 306 struct usbnet *dev = netdev_priv(ndev); 307 struct asix_common_private *priv = dev->driver_priv; 308 309 return phylink_ethtool_set_pauseparam(priv->phylink, pause); 310 } 311 312 static const struct ethtool_ops ax88772_ethtool_ops = { 313 .get_drvinfo = usbnet_get_drvinfo, 314 .get_link = usbnet_get_link, 315 .get_msglevel = usbnet_get_msglevel, 316 .set_msglevel = usbnet_set_msglevel, 317 .get_wol = asix_get_wol, 318 .set_wol = asix_set_wol, 319 .get_eeprom_len = asix_get_eeprom_len, 320 .get_eeprom = asix_get_eeprom, 321 .set_eeprom = asix_set_eeprom, 322 .nway_reset = phy_ethtool_nway_reset, 323 .get_link_ksettings = phy_ethtool_get_link_ksettings, 324 .set_link_ksettings = phy_ethtool_set_link_ksettings, 325 .self_test = net_selftest, 326 .get_strings = ax88772_ethtool_get_strings, 327 .get_sset_count = ax88772_ethtool_get_sset_count, 328 .get_pauseparam = ax88772_ethtool_get_pauseparam, 329 .set_pauseparam = ax88772_ethtool_set_pauseparam, 330 }; 331 332 static int ax88772_reset(struct usbnet *dev) 333 { 334 struct asix_data *data = (struct asix_data *)&dev->data; 335 struct asix_common_private *priv = dev->driver_priv; 336 int ret; 337 338 /* Rewrite MAC address */ 339 ether_addr_copy(data->mac_addr, dev->net->dev_addr); 340 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, 341 ETH_ALEN, data->mac_addr, 0); 342 if (ret < 0) 343 goto out; 344 345 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 346 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0); 347 if (ret < 0) 348 goto out; 349 350 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, 0); 351 if (ret < 0) 352 goto out; 353 354 phylink_start(priv->phylink); 355 356 return 0; 357 358 out: 359 return ret; 360 } 361 362 static int ax88772_hw_reset(struct usbnet *dev, int in_pm) 363 { 364 struct asix_data *data = (struct asix_data *)&dev->data; 365 struct asix_common_private *priv = dev->driver_priv; 366 u16 rx_ctl; 367 int ret; 368 369 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 370 AX_GPIO_GPO2EN, 5, in_pm); 371 if (ret < 0) 372 goto out; 373 374 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, priv->embd_phy, 375 0, 0, NULL, in_pm); 376 if (ret < 0) { 377 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret); 378 goto out; 379 } 380 381 if (priv->embd_phy) { 382 ret = asix_sw_reset(dev, AX_SWRESET_IPPD, in_pm); 383 if (ret < 0) 384 goto out; 385 386 usleep_range(10000, 11000); 387 388 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm); 389 if (ret < 0) 390 goto out; 391 392 msleep(60); 393 394 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL, 395 in_pm); 396 if (ret < 0) 397 goto out; 398 } else { 399 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL, 400 in_pm); 401 if (ret < 0) 402 goto out; 403 } 404 405 msleep(150); 406 407 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 408 MII_PHYSID1))){ 409 ret = -EIO; 410 goto out; 411 } 412 413 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 414 if (ret < 0) 415 goto out; 416 417 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm); 418 if (ret < 0) 419 goto out; 420 421 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0, 422 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, 423 AX88772_IPG2_DEFAULT, 0, NULL, in_pm); 424 if (ret < 0) { 425 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret); 426 goto out; 427 } 428 429 /* Rewrite MAC address */ 430 ether_addr_copy(data->mac_addr, dev->net->dev_addr); 431 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, 432 ETH_ALEN, data->mac_addr, in_pm); 433 if (ret < 0) 434 goto out; 435 436 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 437 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 438 if (ret < 0) 439 goto out; 440 441 rx_ctl = asix_read_rx_ctl(dev, in_pm); 442 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n", 443 rx_ctl); 444 445 rx_ctl = asix_read_medium_status(dev, in_pm); 446 netdev_dbg(dev->net, 447 "Medium Status is 0x%04x after all initializations\n", 448 rx_ctl); 449 450 return 0; 451 452 out: 453 return ret; 454 } 455 456 static int ax88772a_hw_reset(struct usbnet *dev, int in_pm) 457 { 458 struct asix_data *data = (struct asix_data *)&dev->data; 459 struct asix_common_private *priv = dev->driver_priv; 460 u16 rx_ctl, phy14h, phy15h, phy16h; 461 int ret; 462 463 ret = asix_write_gpio(dev, AX_GPIO_RSE, 5, in_pm); 464 if (ret < 0) 465 goto out; 466 467 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, priv->embd_phy | 468 AX_PHYSEL_SSEN, 0, 0, NULL, in_pm); 469 if (ret < 0) { 470 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret); 471 goto out; 472 } 473 usleep_range(10000, 11000); 474 475 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_IPRL, in_pm); 476 if (ret < 0) 477 goto out; 478 479 usleep_range(10000, 11000); 480 481 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm); 482 if (ret < 0) 483 goto out; 484 485 msleep(160); 486 487 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm); 488 if (ret < 0) 489 goto out; 490 491 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm); 492 if (ret < 0) 493 goto out; 494 495 msleep(200); 496 497 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 498 MII_PHYSID1))) { 499 ret = -1; 500 goto out; 501 } 502 503 if (priv->chipcode == AX_AX88772B_CHIPCODE) { 504 ret = asix_write_cmd(dev, AX_QCTCTRL, 0x8000, 0x8001, 505 0, NULL, in_pm); 506 if (ret < 0) { 507 netdev_dbg(dev->net, "Write BQ setting failed: %d\n", 508 ret); 509 goto out; 510 } 511 } else if (priv->chipcode == AX_AX88772A_CHIPCODE) { 512 /* Check if the PHY registers have default settings */ 513 phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 514 AX88772A_PHY14H); 515 phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 516 AX88772A_PHY15H); 517 phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, 518 AX88772A_PHY16H); 519 520 netdev_dbg(dev->net, 521 "772a_hw_reset: MR20=0x%x MR21=0x%x MR22=0x%x\n", 522 phy14h, phy15h, phy16h); 523 524 /* Restore PHY registers default setting if not */ 525 if (phy14h != AX88772A_PHY14H_DEFAULT) 526 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, 527 AX88772A_PHY14H, 528 AX88772A_PHY14H_DEFAULT); 529 if (phy15h != AX88772A_PHY15H_DEFAULT) 530 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, 531 AX88772A_PHY15H, 532 AX88772A_PHY15H_DEFAULT); 533 if (phy16h != AX88772A_PHY16H_DEFAULT) 534 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, 535 AX88772A_PHY16H, 536 AX88772A_PHY16H_DEFAULT); 537 } 538 539 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0, 540 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, 541 AX88772_IPG2_DEFAULT, 0, NULL, in_pm); 542 if (ret < 0) { 543 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret); 544 goto out; 545 } 546 547 /* Rewrite MAC address */ 548 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); 549 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, 550 data->mac_addr, in_pm); 551 if (ret < 0) 552 goto out; 553 554 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 555 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 556 if (ret < 0) 557 goto out; 558 559 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm); 560 if (ret < 0) 561 return ret; 562 563 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 564 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm); 565 if (ret < 0) 566 goto out; 567 568 rx_ctl = asix_read_rx_ctl(dev, in_pm); 569 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n", 570 rx_ctl); 571 572 rx_ctl = asix_read_medium_status(dev, in_pm); 573 netdev_dbg(dev->net, 574 "Medium Status is 0x%04x after all initializations\n", 575 rx_ctl); 576 577 return 0; 578 579 out: 580 return ret; 581 } 582 583 static const struct net_device_ops ax88772_netdev_ops = { 584 .ndo_open = usbnet_open, 585 .ndo_stop = usbnet_stop, 586 .ndo_start_xmit = usbnet_start_xmit, 587 .ndo_tx_timeout = usbnet_tx_timeout, 588 .ndo_change_mtu = usbnet_change_mtu, 589 .ndo_get_stats64 = dev_get_tstats64, 590 .ndo_set_mac_address = asix_set_mac_address, 591 .ndo_validate_addr = eth_validate_addr, 592 .ndo_eth_ioctl = phy_do_ioctl_running, 593 .ndo_set_rx_mode = asix_set_multicast, 594 }; 595 596 static void ax88772_suspend(struct usbnet *dev) 597 { 598 struct asix_common_private *priv = dev->driver_priv; 599 u16 medium; 600 601 if (netif_running(dev->net)) { 602 rtnl_lock(); 603 phylink_suspend(priv->phylink, false); 604 rtnl_unlock(); 605 } 606 607 /* Stop MAC operation */ 608 medium = asix_read_medium_status(dev, 1); 609 medium &= ~AX_MEDIUM_RE; 610 asix_write_medium_mode(dev, medium, 1); 611 612 netdev_dbg(dev->net, "ax88772_suspend: medium=0x%04x\n", 613 asix_read_medium_status(dev, 1)); 614 } 615 616 /* Notes on PM callbacks and locking context: 617 * 618 * - asix_suspend()/asix_resume() are invoked for both runtime PM and 619 * system-wide suspend/resume. For struct usb_driver the ->resume() 620 * callback does not receive pm_message_t, so the resume type cannot 621 * be distinguished here. 622 * 623 * - The MAC driver must hold RTNL when calling phylink interfaces such as 624 * phylink_suspend()/resume(). Those calls will also perform MDIO I/O. 625 * 626 * - Taking RTNL and doing MDIO from a runtime-PM resume callback (while 627 * the USB PM lock is held) is fragile. Since autosuspend brings no 628 * measurable power saving here, we block it by holding a PM usage 629 * reference in ax88772_bind(). 630 */ 631 static int asix_suspend(struct usb_interface *intf, pm_message_t message) 632 { 633 struct usbnet *dev = usb_get_intfdata(intf); 634 struct asix_common_private *priv = dev->driver_priv; 635 636 if (priv && priv->suspend) 637 priv->suspend(dev); 638 639 return usbnet_suspend(intf, message); 640 } 641 642 static void ax88772_resume(struct usbnet *dev) 643 { 644 struct asix_common_private *priv = dev->driver_priv; 645 int i; 646 647 for (i = 0; i < 3; i++) 648 if (!priv->reset(dev, 1)) 649 break; 650 651 if (netif_running(dev->net)) { 652 rtnl_lock(); 653 phylink_resume(priv->phylink); 654 rtnl_unlock(); 655 } 656 } 657 658 static int asix_resume(struct usb_interface *intf) 659 { 660 struct usbnet *dev = usb_get_intfdata(intf); 661 struct asix_common_private *priv = dev->driver_priv; 662 663 if (priv && priv->resume) 664 priv->resume(dev); 665 666 return usbnet_resume(intf); 667 } 668 669 static int ax88772_init_mdio(struct usbnet *dev) 670 { 671 struct asix_common_private *priv = dev->driver_priv; 672 int ret; 673 674 priv->mdio = mdiobus_alloc(); 675 if (!priv->mdio) 676 return -ENOMEM; 677 678 priv->mdio->priv = dev; 679 priv->mdio->read = &asix_mdio_bus_read; 680 priv->mdio->write = &asix_mdio_bus_write; 681 priv->mdio->name = "Asix MDIO Bus"; 682 priv->mdio->phy_mask = ~(BIT(priv->phy_addr & 0x1f) | BIT(AX_EMBD_PHY_ADDR)); 683 /* mii bus name is usb-<usb bus number>-<usb device number> */ 684 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "usb-%03d:%03d", 685 dev->udev->bus->busnum, dev->udev->devnum); 686 687 ret = mdiobus_register(priv->mdio); 688 if (ret) { 689 netdev_err(dev->net, "Could not register MDIO bus (err %d)\n", ret); 690 mdiobus_free(priv->mdio); 691 priv->mdio = NULL; 692 } 693 694 return ret; 695 } 696 697 static void ax88772_mdio_unregister(struct asix_common_private *priv) 698 { 699 mdiobus_unregister(priv->mdio); 700 mdiobus_free(priv->mdio); 701 } 702 703 static int ax88772_init_phy(struct usbnet *dev) 704 { 705 struct asix_common_private *priv = dev->driver_priv; 706 int ret; 707 708 priv->phydev = mdiobus_get_phy(priv->mdio, priv->phy_addr); 709 if (!priv->phydev) { 710 netdev_err(dev->net, "Could not find PHY\n"); 711 return -ENODEV; 712 } 713 714 ret = phylink_connect_phy(priv->phylink, priv->phydev); 715 if (ret) { 716 netdev_err(dev->net, "Could not connect PHY\n"); 717 return ret; 718 } 719 720 phy_suspend(priv->phydev); 721 priv->phydev->mac_managed_pm = true; 722 723 phy_attached_info(priv->phydev); 724 725 if (priv->embd_phy) 726 return 0; 727 728 /* In case main PHY is not the embedded PHY and MAC is RMII clock 729 * provider, we need to suspend embedded PHY by keeping PLL enabled 730 * (AX_SWRESET_IPPD == 0). 731 */ 732 priv->phydev_int = mdiobus_get_phy(priv->mdio, AX_EMBD_PHY_ADDR); 733 if (!priv->phydev_int) { 734 rtnl_lock(); 735 phylink_disconnect_phy(priv->phylink); 736 rtnl_unlock(); 737 netdev_err(dev->net, "Could not find internal PHY\n"); 738 return -ENODEV; 739 } 740 741 priv->phydev_int->mac_managed_pm = true; 742 phy_suspend(priv->phydev_int); 743 744 return 0; 745 } 746 747 static void ax88772_mac_config(struct phylink_config *config, unsigned int mode, 748 const struct phylink_link_state *state) 749 { 750 /* Nothing to do */ 751 } 752 753 static void ax88772_mac_link_down(struct phylink_config *config, 754 unsigned int mode, phy_interface_t interface) 755 { 756 struct usbnet *dev = netdev_priv(to_net_dev(config->dev)); 757 758 asix_write_medium_mode(dev, 0, 0); 759 } 760 761 static void ax88772_mac_link_up(struct phylink_config *config, 762 struct phy_device *phy, 763 unsigned int mode, phy_interface_t interface, 764 int speed, int duplex, 765 bool tx_pause, bool rx_pause) 766 { 767 struct usbnet *dev = netdev_priv(to_net_dev(config->dev)); 768 u16 m = AX_MEDIUM_AC | AX_MEDIUM_RE; 769 770 m |= duplex ? AX_MEDIUM_FD : 0; 771 772 switch (speed) { 773 case SPEED_100: 774 m |= AX_MEDIUM_PS; 775 break; 776 case SPEED_10: 777 break; 778 default: 779 return; 780 } 781 782 if (tx_pause) 783 m |= AX_MEDIUM_TFC; 784 785 if (rx_pause) 786 m |= AX_MEDIUM_RFC; 787 788 asix_write_medium_mode(dev, m, 0); 789 } 790 791 static const struct phylink_mac_ops ax88772_phylink_mac_ops = { 792 .mac_config = ax88772_mac_config, 793 .mac_link_down = ax88772_mac_link_down, 794 .mac_link_up = ax88772_mac_link_up, 795 }; 796 797 static int ax88772_phylink_setup(struct usbnet *dev) 798 { 799 struct asix_common_private *priv = dev->driver_priv; 800 phy_interface_t phy_if_mode; 801 struct phylink *phylink; 802 803 priv->phylink_config.dev = &dev->net->dev; 804 priv->phylink_config.type = PHYLINK_NETDEV; 805 priv->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | 806 MAC_10 | MAC_100; 807 808 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 809 priv->phylink_config.supported_interfaces); 810 __set_bit(PHY_INTERFACE_MODE_RMII, 811 priv->phylink_config.supported_interfaces); 812 813 if (priv->embd_phy) 814 phy_if_mode = PHY_INTERFACE_MODE_INTERNAL; 815 else 816 phy_if_mode = PHY_INTERFACE_MODE_RMII; 817 818 phylink = phylink_create(&priv->phylink_config, dev->net->dev.fwnode, 819 phy_if_mode, &ax88772_phylink_mac_ops); 820 if (IS_ERR(phylink)) 821 return PTR_ERR(phylink); 822 823 priv->phylink = phylink; 824 return 0; 825 } 826 827 static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf) 828 { 829 struct asix_common_private *priv; 830 u8 buf[ETH_ALEN] = {0}; 831 int ret, i; 832 833 priv = devm_kzalloc(&dev->udev->dev, sizeof(*priv), GFP_KERNEL); 834 if (!priv) 835 return -ENOMEM; 836 837 dev->driver_priv = priv; 838 839 ret = usbnet_get_endpoints(dev, intf); 840 if (ret) 841 return ret; 842 843 /* Maybe the boot loader passed the MAC address via device tree */ 844 if (!eth_platform_get_mac_address(&dev->udev->dev, buf)) { 845 netif_dbg(dev, ifup, dev->net, 846 "MAC address read from device tree"); 847 } else { 848 /* Try getting the MAC address from EEPROM */ 849 if (dev->driver_info->data & FLAG_EEPROM_MAC) { 850 for (i = 0; i < (ETH_ALEN >> 1); i++) { 851 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM, 852 0x04 + i, 0, 2, buf + i * 2, 853 0); 854 if (ret < 0) 855 break; 856 } 857 } else { 858 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 859 0, 0, ETH_ALEN, buf, 0); 860 } 861 862 if (ret < 0) { 863 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", 864 ret); 865 return ret; 866 } 867 } 868 869 asix_set_netdev_dev_addr(dev, buf); 870 871 dev->net->netdev_ops = &ax88772_netdev_ops; 872 dev->net->ethtool_ops = &ax88772_ethtool_ops; 873 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */ 874 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */ 875 876 ret = asix_read_phy_addr(dev, true); 877 if (ret < 0) 878 return ret; 879 880 priv->phy_addr = ret; 881 priv->embd_phy = ((priv->phy_addr & 0x1f) == AX_EMBD_PHY_ADDR); 882 883 ret = asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0, 0, 1, 884 &priv->chipcode, 0); 885 if (ret < 0) { 886 netdev_dbg(dev->net, "Failed to read STATMNGSTS_REG: %d\n", ret); 887 return ret; 888 } 889 890 priv->chipcode &= AX_CHIPCODE_MASK; 891 892 priv->resume = ax88772_resume; 893 priv->suspend = ax88772_suspend; 894 if (priv->chipcode == AX_AX88772_CHIPCODE) 895 priv->reset = ax88772_hw_reset; 896 else 897 priv->reset = ax88772a_hw_reset; 898 899 ret = priv->reset(dev, 0); 900 if (ret < 0) { 901 netdev_dbg(dev->net, "Failed to reset AX88772: %d\n", ret); 902 return ret; 903 } 904 905 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ 906 if (dev->driver_info->flags & FLAG_FRAMING_AX) { 907 /* hard_mtu is still the default - the device does not support 908 jumbo eth frames */ 909 dev->rx_urb_size = 2048; 910 } 911 912 priv->presvd_phy_bmcr = 0; 913 priv->presvd_phy_advertise = 0; 914 915 ret = ax88772_init_mdio(dev); 916 if (ret) 917 goto mdio_err; 918 919 ret = ax88772_phylink_setup(dev); 920 if (ret) 921 goto phylink_err; 922 923 ret = ax88772_init_phy(dev); 924 if (ret) 925 goto initphy_err; 926 927 /* Keep this interface runtime-PM active by taking a usage ref. 928 * Prevents runtime suspend while bound and avoids resume paths 929 * that could deadlock (autoresume under RTNL while USB PM lock 930 * is held, phylink/MDIO wants RTNL). 931 */ 932 pm_runtime_get_noresume(&intf->dev); 933 934 return 0; 935 936 initphy_err: 937 phylink_destroy(priv->phylink); 938 phylink_err: 939 ax88772_mdio_unregister(priv); 940 mdio_err: 941 return ret; 942 } 943 944 static int ax88772_stop(struct usbnet *dev) 945 { 946 struct asix_common_private *priv = dev->driver_priv; 947 948 phylink_stop(priv->phylink); 949 950 return 0; 951 } 952 953 static void ax88772_unbind(struct usbnet *dev, struct usb_interface *intf) 954 { 955 struct asix_common_private *priv = dev->driver_priv; 956 957 rtnl_lock(); 958 phylink_disconnect_phy(priv->phylink); 959 rtnl_unlock(); 960 phylink_destroy(priv->phylink); 961 ax88772_mdio_unregister(priv); 962 asix_rx_fixup_common_free(dev->driver_priv); 963 /* Drop the PM usage ref taken in bind() */ 964 pm_runtime_put(&intf->dev); 965 } 966 967 static void ax88178_unbind(struct usbnet *dev, struct usb_interface *intf) 968 { 969 asix_rx_fixup_common_free(dev->driver_priv); 970 kfree(dev->driver_priv); 971 } 972 973 static const struct ethtool_ops ax88178_ethtool_ops = { 974 .get_drvinfo = usbnet_get_drvinfo, 975 .get_link = usbnet_get_link, 976 .get_msglevel = usbnet_get_msglevel, 977 .set_msglevel = usbnet_set_msglevel, 978 .get_wol = asix_get_wol, 979 .set_wol = asix_set_wol, 980 .get_eeprom_len = asix_get_eeprom_len, 981 .get_eeprom = asix_get_eeprom, 982 .set_eeprom = asix_set_eeprom, 983 .nway_reset = usbnet_nway_reset, 984 .get_link_ksettings = usbnet_get_link_ksettings_mii, 985 .set_link_ksettings = usbnet_set_link_ksettings_mii, 986 }; 987 988 static int marvell_phy_init(struct usbnet *dev) 989 { 990 struct asix_data *data = (struct asix_data *)&dev->data; 991 u16 reg; 992 993 netdev_dbg(dev->net, "marvell_phy_init()\n"); 994 995 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS); 996 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg); 997 998 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL, 999 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY); 1000 1001 if (data->ledmode) { 1002 reg = asix_mdio_read(dev->net, dev->mii.phy_id, 1003 MII_MARVELL_LED_CTRL); 1004 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg); 1005 1006 reg &= 0xf8ff; 1007 reg |= (1 + 0x0100); 1008 asix_mdio_write(dev->net, dev->mii.phy_id, 1009 MII_MARVELL_LED_CTRL, reg); 1010 1011 reg = asix_mdio_read(dev->net, dev->mii.phy_id, 1012 MII_MARVELL_LED_CTRL); 1013 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg); 1014 } 1015 1016 return 0; 1017 } 1018 1019 static int rtl8211cl_phy_init(struct usbnet *dev) 1020 { 1021 struct asix_data *data = (struct asix_data *)&dev->data; 1022 1023 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n"); 1024 1025 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005); 1026 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0); 1027 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01, 1028 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080); 1029 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); 1030 1031 if (data->ledmode == 12) { 1032 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002); 1033 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb); 1034 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); 1035 } 1036 1037 return 0; 1038 } 1039 1040 static int marvell_led_status(struct usbnet *dev, u16 speed) 1041 { 1042 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL); 1043 1044 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg); 1045 1046 /* Clear out the center LED bits - 0x03F0 */ 1047 reg &= 0xfc0f; 1048 1049 switch (speed) { 1050 case SPEED_1000: 1051 reg |= 0x03e0; 1052 break; 1053 case SPEED_100: 1054 reg |= 0x03b0; 1055 break; 1056 default: 1057 reg |= 0x02f0; 1058 } 1059 1060 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg); 1061 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg); 1062 1063 return 0; 1064 } 1065 1066 static int ax88178_reset(struct usbnet *dev) 1067 { 1068 struct asix_data *data = (struct asix_data *)&dev->data; 1069 int ret; 1070 __le16 eeprom; 1071 u8 status; 1072 int gpio0 = 0; 1073 u32 phyid; 1074 1075 ret = asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status, 0); 1076 if (ret < 0) { 1077 netdev_dbg(dev->net, "Failed to read GPIOS: %d\n", ret); 1078 return ret; 1079 } 1080 1081 netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status); 1082 1083 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL, 0); 1084 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom, 0); 1085 if (ret < 0) { 1086 netdev_dbg(dev->net, "Failed to read EEPROM: %d\n", ret); 1087 return ret; 1088 } 1089 1090 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL, 0); 1091 1092 netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom); 1093 1094 if (eeprom == cpu_to_le16(0xffff)) { 1095 data->phymode = PHY_MODE_MARVELL; 1096 data->ledmode = 0; 1097 gpio0 = 1; 1098 } else { 1099 data->phymode = le16_to_cpu(eeprom) & 0x7F; 1100 data->ledmode = le16_to_cpu(eeprom) >> 8; 1101 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1; 1102 } 1103 netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode); 1104 1105 /* Power up external GigaPHY through AX88178 GPIO pin */ 1106 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | 1107 AX_GPIO_GPO1EN, 40, 0); 1108 if ((le16_to_cpu(eeprom) >> 8) != 1) { 1109 asix_write_gpio(dev, 0x003c, 30, 0); 1110 asix_write_gpio(dev, 0x001c, 300, 0); 1111 asix_write_gpio(dev, 0x003c, 30, 0); 1112 } else { 1113 netdev_dbg(dev->net, "gpio phymode == 1 path\n"); 1114 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30, 0); 1115 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30, 0); 1116 } 1117 1118 /* Read PHYID register *AFTER* powering up PHY */ 1119 phyid = asix_get_phyid(dev); 1120 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid); 1121 1122 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */ 1123 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL, 0); 1124 1125 asix_sw_reset(dev, 0, 0); 1126 msleep(150); 1127 1128 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0); 1129 msleep(150); 1130 1131 asix_write_rx_ctl(dev, 0, 0); 1132 1133 if (data->phymode == PHY_MODE_MARVELL) { 1134 marvell_phy_init(dev); 1135 msleep(60); 1136 } else if (data->phymode == PHY_MODE_RTL8211CL) 1137 rtl8211cl_phy_init(dev); 1138 1139 asix_phy_reset(dev, BMCR_RESET | BMCR_ANENABLE); 1140 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, 1141 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); 1142 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000, 1143 ADVERTISE_1000FULL); 1144 1145 asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT, 0); 1146 mii_nway_restart(&dev->mii); 1147 1148 /* Rewrite MAC address */ 1149 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); 1150 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, 1151 data->mac_addr, 0); 1152 if (ret < 0) 1153 return ret; 1154 1155 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0); 1156 if (ret < 0) 1157 return ret; 1158 1159 return 0; 1160 } 1161 1162 static int ax88178_link_reset(struct usbnet *dev) 1163 { 1164 u16 mode; 1165 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 1166 struct asix_data *data = (struct asix_data *)&dev->data; 1167 u32 speed; 1168 1169 netdev_dbg(dev->net, "ax88178_link_reset()\n"); 1170 1171 mii_check_media(&dev->mii, 1, 1); 1172 mii_ethtool_gset(&dev->mii, &ecmd); 1173 mode = AX88178_MEDIUM_DEFAULT; 1174 speed = ethtool_cmd_speed(&ecmd); 1175 1176 if (speed == SPEED_1000) 1177 mode |= AX_MEDIUM_GM; 1178 else if (speed == SPEED_100) 1179 mode |= AX_MEDIUM_PS; 1180 else 1181 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM); 1182 1183 mode |= AX_MEDIUM_ENCK; 1184 1185 if (ecmd.duplex == DUPLEX_FULL) 1186 mode |= AX_MEDIUM_FD; 1187 else 1188 mode &= ~AX_MEDIUM_FD; 1189 1190 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", 1191 speed, ecmd.duplex, mode); 1192 1193 asix_write_medium_mode(dev, mode, 0); 1194 1195 if (data->phymode == PHY_MODE_MARVELL && data->ledmode) 1196 marvell_led_status(dev, speed); 1197 1198 return 0; 1199 } 1200 1201 static void ax88178_set_mfb(struct usbnet *dev) 1202 { 1203 u16 mfb = AX_RX_CTL_MFB_16384; 1204 u16 rxctl; 1205 u16 medium; 1206 int old_rx_urb_size = dev->rx_urb_size; 1207 1208 if (dev->hard_mtu < 2048) { 1209 dev->rx_urb_size = 2048; 1210 mfb = AX_RX_CTL_MFB_2048; 1211 } else if (dev->hard_mtu < 4096) { 1212 dev->rx_urb_size = 4096; 1213 mfb = AX_RX_CTL_MFB_4096; 1214 } else if (dev->hard_mtu < 8192) { 1215 dev->rx_urb_size = 8192; 1216 mfb = AX_RX_CTL_MFB_8192; 1217 } else if (dev->hard_mtu < 16384) { 1218 dev->rx_urb_size = 16384; 1219 mfb = AX_RX_CTL_MFB_16384; 1220 } 1221 1222 rxctl = asix_read_rx_ctl(dev, 0); 1223 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb, 0); 1224 1225 medium = asix_read_medium_status(dev, 0); 1226 if (dev->net->mtu > 1500) 1227 medium |= AX_MEDIUM_JFE; 1228 else 1229 medium &= ~AX_MEDIUM_JFE; 1230 asix_write_medium_mode(dev, medium, 0); 1231 1232 if (dev->rx_urb_size > old_rx_urb_size) 1233 usbnet_unlink_rx_urbs(dev); 1234 } 1235 1236 static int ax88178_change_mtu(struct net_device *net, int new_mtu) 1237 { 1238 struct usbnet *dev = netdev_priv(net); 1239 int ll_mtu = new_mtu + net->hard_header_len + 4; 1240 1241 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu); 1242 1243 if ((ll_mtu % dev->maxpacket) == 0) 1244 return -EDOM; 1245 1246 WRITE_ONCE(net->mtu, new_mtu); 1247 dev->hard_mtu = net->mtu + net->hard_header_len; 1248 ax88178_set_mfb(dev); 1249 1250 /* max qlen depend on hard_mtu and rx_urb_size */ 1251 usbnet_update_max_qlen(dev); 1252 1253 return 0; 1254 } 1255 1256 static const struct net_device_ops ax88178_netdev_ops = { 1257 .ndo_open = usbnet_open, 1258 .ndo_stop = usbnet_stop, 1259 .ndo_start_xmit = usbnet_start_xmit, 1260 .ndo_tx_timeout = usbnet_tx_timeout, 1261 .ndo_get_stats64 = dev_get_tstats64, 1262 .ndo_set_mac_address = asix_set_mac_address, 1263 .ndo_validate_addr = eth_validate_addr, 1264 .ndo_set_rx_mode = asix_set_multicast, 1265 .ndo_eth_ioctl = usbnet_mii_ioctl, 1266 .ndo_change_mtu = ax88178_change_mtu, 1267 }; 1268 1269 static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf) 1270 { 1271 int ret; 1272 u8 buf[ETH_ALEN] = {0}; 1273 1274 ret = usbnet_get_endpoints(dev, intf); 1275 if (ret) 1276 return ret; 1277 1278 /* Get the MAC address */ 1279 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf, 0); 1280 if (ret < 0) { 1281 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret); 1282 return ret; 1283 } 1284 1285 asix_set_netdev_dev_addr(dev, buf); 1286 1287 /* Initialize MII structure */ 1288 dev->mii.dev = dev->net; 1289 dev->mii.mdio_read = asix_mdio_read; 1290 dev->mii.mdio_write = asix_mdio_write; 1291 dev->mii.phy_id_mask = 0x1f; 1292 dev->mii.reg_num_mask = 0xff; 1293 dev->mii.supports_gmii = 1; 1294 1295 dev->mii.phy_id = asix_read_phy_addr(dev, true); 1296 if (dev->mii.phy_id < 0) 1297 return dev->mii.phy_id; 1298 1299 dev->net->netdev_ops = &ax88178_netdev_ops; 1300 dev->net->ethtool_ops = &ax88178_ethtool_ops; 1301 dev->net->max_mtu = 16384 - (dev->net->hard_header_len + 4); 1302 1303 /* Blink LEDS so users know driver saw dongle */ 1304 asix_sw_reset(dev, 0, 0); 1305 msleep(150); 1306 1307 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0); 1308 msleep(150); 1309 1310 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ 1311 if (dev->driver_info->flags & FLAG_FRAMING_AX) { 1312 /* hard_mtu is still the default - the device does not support 1313 jumbo eth frames */ 1314 dev->rx_urb_size = 2048; 1315 } 1316 1317 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL); 1318 if (!dev->driver_priv) 1319 return -ENOMEM; 1320 1321 return 0; 1322 } 1323 1324 static const struct driver_info ax8817x_info = { 1325 .description = "ASIX AX8817x USB 2.0 Ethernet", 1326 .bind = ax88172_bind, 1327 .status = asix_status, 1328 .link_reset = ax88172_link_reset, 1329 .reset = ax88172_link_reset, 1330 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1331 .data = 0x00130103, 1332 }; 1333 1334 static const struct driver_info dlink_dub_e100_info = { 1335 .description = "DLink DUB-E100 USB Ethernet", 1336 .bind = ax88172_bind, 1337 .status = asix_status, 1338 .link_reset = ax88172_link_reset, 1339 .reset = ax88172_link_reset, 1340 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1341 .data = 0x009f9d9f, 1342 }; 1343 1344 static const struct driver_info netgear_fa120_info = { 1345 .description = "Netgear FA-120 USB Ethernet", 1346 .bind = ax88172_bind, 1347 .status = asix_status, 1348 .link_reset = ax88172_link_reset, 1349 .reset = ax88172_link_reset, 1350 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1351 .data = 0x00130103, 1352 }; 1353 1354 static const struct driver_info hawking_uf200_info = { 1355 .description = "Hawking UF200 USB Ethernet", 1356 .bind = ax88172_bind, 1357 .status = asix_status, 1358 .link_reset = ax88172_link_reset, 1359 .reset = ax88172_link_reset, 1360 .flags = FLAG_ETHER | FLAG_LINK_INTR, 1361 .data = 0x001f1d1f, 1362 }; 1363 1364 static const struct driver_info ax88772_info = { 1365 .description = "ASIX AX88772 USB 2.0 Ethernet", 1366 .bind = ax88772_bind, 1367 .unbind = ax88772_unbind, 1368 .reset = ax88772_reset, 1369 .stop = ax88772_stop, 1370 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_MULTI_PACKET, 1371 .rx_fixup = asix_rx_fixup_common, 1372 .tx_fixup = asix_tx_fixup, 1373 }; 1374 1375 static const struct driver_info ax88772b_info = { 1376 .description = "ASIX AX88772B USB 2.0 Ethernet", 1377 .bind = ax88772_bind, 1378 .unbind = ax88772_unbind, 1379 .reset = ax88772_reset, 1380 .stop = ax88772_stop, 1381 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_MULTI_PACKET, 1382 .rx_fixup = asix_rx_fixup_common, 1383 .tx_fixup = asix_tx_fixup, 1384 .data = FLAG_EEPROM_MAC, 1385 }; 1386 1387 static const struct driver_info lxausb_t1l_info = { 1388 .description = "Linux Automation GmbH USB 10Base-T1L", 1389 .bind = ax88772_bind, 1390 .unbind = ax88772_unbind, 1391 .reset = ax88772_reset, 1392 .stop = ax88772_stop, 1393 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_MULTI_PACKET, 1394 .rx_fixup = asix_rx_fixup_common, 1395 .tx_fixup = asix_tx_fixup, 1396 .data = FLAG_EEPROM_MAC, 1397 }; 1398 1399 static const struct driver_info ax88178_info = { 1400 .description = "ASIX AX88178 USB 2.0 Ethernet", 1401 .bind = ax88178_bind, 1402 .unbind = ax88178_unbind, 1403 .status = asix_status, 1404 .link_reset = ax88178_link_reset, 1405 .reset = ax88178_reset, 1406 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | 1407 FLAG_MULTI_PACKET, 1408 .rx_fixup = asix_rx_fixup_common, 1409 .tx_fixup = asix_tx_fixup, 1410 }; 1411 1412 /* 1413 * USBLINK 20F9 "USB 2.0 LAN" USB ethernet adapter, typically found in 1414 * no-name packaging. 1415 * USB device strings are: 1416 * 1: Manufacturer: USBLINK 1417 * 2: Product: HG20F9 USB2.0 1418 * 3: Serial: 000003 1419 * Appears to be compatible with Asix 88772B. 1420 */ 1421 static const struct driver_info hg20f9_info = { 1422 .description = "HG20F9 USB 2.0 Ethernet", 1423 .bind = ax88772_bind, 1424 .unbind = ax88772_unbind, 1425 .reset = ax88772_reset, 1426 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_MULTI_PACKET, 1427 .rx_fixup = asix_rx_fixup_common, 1428 .tx_fixup = asix_tx_fixup, 1429 .data = FLAG_EEPROM_MAC, 1430 }; 1431 1432 static const struct driver_info lyconsys_fibergecko100_info = { 1433 .description = "LyconSys FiberGecko 100 USB 2.0 to SFP Adapter", 1434 .bind = ax88178_bind, 1435 .status = asix_status, 1436 .link_reset = ax88178_link_reset, 1437 .reset = ax88178_link_reset, 1438 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | 1439 FLAG_MULTI_PACKET, 1440 .rx_fixup = asix_rx_fixup_common, 1441 .tx_fixup = asix_tx_fixup, 1442 .data = 0x20061201, 1443 }; 1444 1445 static const struct usb_device_id products [] = { 1446 { 1447 // Linksys USB200M 1448 USB_DEVICE (0x077b, 0x2226), 1449 .driver_info = (unsigned long) &ax8817x_info, 1450 }, { 1451 // Netgear FA120 1452 USB_DEVICE (0x0846, 0x1040), 1453 .driver_info = (unsigned long) &netgear_fa120_info, 1454 }, { 1455 // DLink DUB-E100 1456 USB_DEVICE (0x2001, 0x1a00), 1457 .driver_info = (unsigned long) &dlink_dub_e100_info, 1458 }, { 1459 // Intellinet, ST Lab USB Ethernet 1460 USB_DEVICE (0x0b95, 0x1720), 1461 .driver_info = (unsigned long) &ax8817x_info, 1462 }, { 1463 // Hawking UF200, TrendNet TU2-ET100 1464 USB_DEVICE (0x07b8, 0x420a), 1465 .driver_info = (unsigned long) &hawking_uf200_info, 1466 }, { 1467 // Billionton Systems, USB2AR 1468 USB_DEVICE (0x08dd, 0x90ff), 1469 .driver_info = (unsigned long) &ax8817x_info, 1470 }, { 1471 // Billionton Systems, GUSB2AM-1G-B 1472 USB_DEVICE(0x08dd, 0x0114), 1473 .driver_info = (unsigned long) &ax88178_info, 1474 }, { 1475 // ATEN UC210T 1476 USB_DEVICE (0x0557, 0x2009), 1477 .driver_info = (unsigned long) &ax8817x_info, 1478 }, { 1479 // Buffalo LUA-U2-KTX 1480 USB_DEVICE (0x0411, 0x003d), 1481 .driver_info = (unsigned long) &ax8817x_info, 1482 }, { 1483 // Buffalo LUA-U2-GT 10/100/1000 1484 USB_DEVICE (0x0411, 0x006e), 1485 .driver_info = (unsigned long) &ax88178_info, 1486 }, { 1487 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter" 1488 USB_DEVICE (0x6189, 0x182d), 1489 .driver_info = (unsigned long) &ax8817x_info, 1490 }, { 1491 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter" 1492 USB_DEVICE (0x0df6, 0x0056), 1493 .driver_info = (unsigned long) &ax88178_info, 1494 }, { 1495 // Sitecom LN-028 "USB 2.0 10/100/1000 Ethernet adapter" 1496 USB_DEVICE (0x0df6, 0x061c), 1497 .driver_info = (unsigned long) &ax88178_info, 1498 }, { 1499 // corega FEther USB2-TX 1500 USB_DEVICE (0x07aa, 0x0017), 1501 .driver_info = (unsigned long) &ax8817x_info, 1502 }, { 1503 // Surecom EP-1427X-2 1504 USB_DEVICE (0x1189, 0x0893), 1505 .driver_info = (unsigned long) &ax8817x_info, 1506 }, { 1507 // goodway corp usb gwusb2e 1508 USB_DEVICE (0x1631, 0x6200), 1509 .driver_info = (unsigned long) &ax8817x_info, 1510 }, { 1511 // JVC MP-PRX1 Port Replicator 1512 USB_DEVICE (0x04f1, 0x3008), 1513 .driver_info = (unsigned long) &ax8817x_info, 1514 }, { 1515 // Lenovo U2L100P 10/100 1516 USB_DEVICE (0x17ef, 0x7203), 1517 .driver_info = (unsigned long)&ax88772b_info, 1518 }, { 1519 // ASIX AX88772B 10/100 1520 USB_DEVICE (0x0b95, 0x772b), 1521 .driver_info = (unsigned long) &ax88772b_info, 1522 }, { 1523 // ASIX AX88772 10/100 1524 USB_DEVICE (0x0b95, 0x7720), 1525 .driver_info = (unsigned long) &ax88772_info, 1526 }, { 1527 // ASIX AX88178 10/100/1000 1528 USB_DEVICE (0x0b95, 0x1780), 1529 .driver_info = (unsigned long) &ax88178_info, 1530 }, { 1531 // Logitec LAN-GTJ/U2A 1532 USB_DEVICE (0x0789, 0x0160), 1533 .driver_info = (unsigned long) &ax88178_info, 1534 }, { 1535 // Linksys USB200M Rev 2 1536 USB_DEVICE (0x13b1, 0x0018), 1537 .driver_info = (unsigned long) &ax88772_info, 1538 }, { 1539 // 0Q0 cable ethernet 1540 USB_DEVICE (0x1557, 0x7720), 1541 .driver_info = (unsigned long) &ax88772_info, 1542 }, { 1543 // DLink DUB-E100 H/W Ver B1 1544 USB_DEVICE (0x07d1, 0x3c05), 1545 .driver_info = (unsigned long) &ax88772_info, 1546 }, { 1547 // DLink DUB-E100 H/W Ver B1 Alternate 1548 USB_DEVICE (0x2001, 0x3c05), 1549 .driver_info = (unsigned long) &ax88772_info, 1550 }, { 1551 // DLink DUB-E100 H/W Ver C1 1552 USB_DEVICE (0x2001, 0x1a02), 1553 .driver_info = (unsigned long) &ax88772_info, 1554 }, { 1555 // Linksys USB1000 1556 USB_DEVICE (0x1737, 0x0039), 1557 .driver_info = (unsigned long) &ax88178_info, 1558 }, { 1559 // IO-DATA ETG-US2 1560 USB_DEVICE (0x04bb, 0x0930), 1561 .driver_info = (unsigned long) &ax88178_info, 1562 }, { 1563 // Belkin F5D5055 1564 USB_DEVICE(0x050d, 0x5055), 1565 .driver_info = (unsigned long) &ax88178_info, 1566 }, { 1567 // Apple USB Ethernet Adapter 1568 USB_DEVICE(0x05ac, 0x1402), 1569 .driver_info = (unsigned long) &ax88772_info, 1570 }, { 1571 // Cables-to-Go USB Ethernet Adapter 1572 USB_DEVICE(0x0b95, 0x772a), 1573 .driver_info = (unsigned long) &ax88772_info, 1574 }, { 1575 // ABOCOM for pci 1576 USB_DEVICE(0x14ea, 0xab11), 1577 .driver_info = (unsigned long) &ax88178_info, 1578 }, { 1579 // ASIX 88772a 1580 USB_DEVICE(0x0db0, 0xa877), 1581 .driver_info = (unsigned long) &ax88772_info, 1582 }, { 1583 // Asus USB Ethernet Adapter 1584 USB_DEVICE (0x0b95, 0x7e2b), 1585 .driver_info = (unsigned long)&ax88772b_info, 1586 }, { 1587 /* ASIX 88172a demo board */ 1588 USB_DEVICE(0x0b95, 0x172a), 1589 .driver_info = (unsigned long) &ax88172a_info, 1590 }, { 1591 /* 1592 * USBLINK HG20F9 "USB 2.0 LAN" 1593 * Appears to have gazumped Linksys's manufacturer ID but 1594 * doesn't (yet) conflict with any known Linksys product. 1595 */ 1596 USB_DEVICE(0x066b, 0x20f9), 1597 .driver_info = (unsigned long) &hg20f9_info, 1598 }, { 1599 // Linux Automation GmbH USB 10Base-T1L 1600 USB_DEVICE(0x33f7, 0x0004), 1601 .driver_info = (unsigned long) &lxausb_t1l_info, 1602 }, { 1603 /* LyconSys FiberGecko 100 */ 1604 USB_DEVICE(0x1d2a, 0x0801), 1605 .driver_info = (unsigned long) &lyconsys_fibergecko100_info, 1606 }, 1607 { }, // END 1608 }; 1609 MODULE_DEVICE_TABLE(usb, products); 1610 1611 static struct usb_driver asix_driver = { 1612 .name = DRIVER_NAME, 1613 .id_table = products, 1614 .probe = usbnet_probe, 1615 .suspend = asix_suspend, 1616 .resume = asix_resume, 1617 .reset_resume = asix_resume, 1618 .disconnect = usbnet_disconnect, 1619 /* usbnet enables autosuspend by default (supports_autosuspend=1). 1620 * We keep runtime-PM active for AX88772* by taking a PM usage 1621 * reference in ax88772_bind() (pm_runtime_get_noresume()) and 1622 * dropping it in unbind(), which effectively blocks autosuspend. 1623 */ 1624 .supports_autosuspend = 1, 1625 .disable_hub_initiated_lpm = 1, 1626 }; 1627 1628 module_usb_driver(asix_driver); 1629 1630 MODULE_AUTHOR("David Hollis"); 1631 MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices"); 1632 MODULE_LICENSE("GPL"); 1633