1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 #ifndef __AMDGPU_PSP_H__ 26 #define __AMDGPU_PSP_H__ 27 28 #include "amdgpu.h" 29 #include "psp_gfx_if.h" 30 #include "ta_xgmi_if.h" 31 #include "ta_ras_if.h" 32 #include "ta_rap_if.h" 33 #include "ta_secureDisplay_if.h" 34 35 #define PSP_FENCE_BUFFER_SIZE 0x1000 36 #define PSP_CMD_BUFFER_SIZE 0x1000 37 #define PSP_1_MEG 0x100000 38 #define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000) 39 #define PSP_TMR_ALIGNMENT 0x100000 40 #define PSP_FW_NAME_LEN 0x24 41 42 extern const struct attribute_group amdgpu_flash_attr_group; 43 44 enum psp_shared_mem_size { 45 PSP_ASD_SHARED_MEM_SIZE = 0x0, 46 PSP_XGMI_SHARED_MEM_SIZE = 0x4000, 47 PSP_RAS_SHARED_MEM_SIZE = 0x4000, 48 PSP_HDCP_SHARED_MEM_SIZE = 0x4000, 49 PSP_DTM_SHARED_MEM_SIZE = 0x4000, 50 PSP_RAP_SHARED_MEM_SIZE = 0x4000, 51 PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000, 52 }; 53 54 enum ta_type_id { 55 TA_TYPE_XGMI = 1, 56 TA_TYPE_RAS, 57 TA_TYPE_HDCP, 58 TA_TYPE_DTM, 59 TA_TYPE_RAP, 60 TA_TYPE_SECUREDISPLAY, 61 62 TA_TYPE_MAX_INDEX, 63 }; 64 65 struct psp_context; 66 struct psp_xgmi_node_info; 67 struct psp_xgmi_topology_info; 68 struct psp_bin_desc; 69 70 enum psp_bootloader_cmd { 71 PSP_BL__LOAD_SYSDRV = 0x10000, 72 PSP_BL__LOAD_SOSDRV = 0x20000, 73 PSP_BL__LOAD_KEY_DATABASE = 0x80000, 74 PSP_BL__LOAD_SOCDRV = 0xB0000, 75 PSP_BL__LOAD_DBGDRV = 0xC0000, 76 PSP_BL__LOAD_HADDRV = PSP_BL__LOAD_DBGDRV, 77 PSP_BL__LOAD_INTFDRV = 0xD0000, 78 PSP_BL__LOAD_RASDRV = 0xE0000, 79 PSP_BL__LOAD_IPKEYMGRDRV = 0xF0000, 80 PSP_BL__DRAM_LONG_TRAIN = 0x100000, 81 PSP_BL__DRAM_SHORT_TRAIN = 0x200000, 82 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000, 83 PSP_BL__LOAD_SPDMDRV = 0x20000000, 84 }; 85 86 enum psp_ring_type { 87 PSP_RING_TYPE__INVALID = 0, 88 /* 89 * These values map to the way the PSP kernel identifies the 90 * rings. 91 */ 92 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 93 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 94 }; 95 96 struct psp_ring { 97 enum psp_ring_type ring_type; 98 struct psp_gfx_rb_frame *ring_mem; 99 uint64_t ring_mem_mc_addr; 100 void *ring_mem_handle; 101 uint32_t ring_size; 102 uint32_t ring_wptr; 103 }; 104 105 /* More registers may will be supported */ 106 enum psp_reg_prog_id { 107 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */ 108 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */ 109 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */ 110 PSP_REG_LAST 111 }; 112 113 struct psp_funcs { 114 int (*init_microcode)(struct psp_context *psp); 115 int (*wait_for_bootloader)(struct psp_context *psp); 116 int (*bootloader_load_kdb)(struct psp_context *psp); 117 int (*bootloader_load_spl)(struct psp_context *psp); 118 int (*bootloader_load_sysdrv)(struct psp_context *psp); 119 int (*bootloader_load_soc_drv)(struct psp_context *psp); 120 int (*bootloader_load_intf_drv)(struct psp_context *psp); 121 int (*bootloader_load_dbg_drv)(struct psp_context *psp); 122 int (*bootloader_load_ras_drv)(struct psp_context *psp); 123 int (*bootloader_load_ipkeymgr_drv)(struct psp_context *psp); 124 int (*bootloader_load_spdm_drv)(struct psp_context *psp); 125 int (*bootloader_load_sos)(struct psp_context *psp); 126 int (*ring_create)(struct psp_context *psp, 127 enum psp_ring_type ring_type); 128 int (*ring_stop)(struct psp_context *psp, 129 enum psp_ring_type ring_type); 130 int (*ring_destroy)(struct psp_context *psp, 131 enum psp_ring_type ring_type); 132 bool (*smu_reload_quirk)(struct psp_context *psp); 133 int (*mode1_reset)(struct psp_context *psp); 134 int (*mem_training)(struct psp_context *psp, uint32_t ops); 135 uint32_t (*ring_get_wptr)(struct psp_context *psp); 136 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value); 137 int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 138 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver); 139 int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 140 int (*vbflash_stat)(struct psp_context *psp); 141 int (*fatal_error_recovery_quirk)(struct psp_context *psp); 142 bool (*get_ras_capability)(struct psp_context *psp); 143 bool (*is_aux_sos_load_required)(struct psp_context *psp); 144 bool (*is_reload_needed)(struct psp_context *psp); 145 }; 146 147 struct ta_funcs { 148 int (*fn_ta_initialize)(struct psp_context *psp); 149 int (*fn_ta_invoke)(struct psp_context *psp, uint32_t ta_cmd_id); 150 int (*fn_ta_terminate)(struct psp_context *psp); 151 }; 152 153 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64 154 struct psp_xgmi_node_info { 155 uint64_t node_id; 156 uint8_t num_hops; 157 uint8_t is_sharing_enabled; 158 enum ta_xgmi_assigned_sdma_engine sdma_engine; 159 uint8_t num_links; 160 struct xgmi_connected_port_num port_num[TA_XGMI__MAX_PORT_NUM]; 161 }; 162 163 struct psp_xgmi_topology_info { 164 uint32_t num_nodes; 165 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES]; 166 }; 167 168 struct psp_bin_desc { 169 uint32_t fw_version; 170 uint32_t feature_version; 171 uint32_t size_bytes; 172 uint8_t *start_addr; 173 }; 174 175 struct ta_mem_context { 176 struct amdgpu_bo *shared_bo; 177 uint64_t shared_mc_addr; 178 void *shared_buf; 179 enum psp_shared_mem_size shared_mem_size; 180 }; 181 182 struct ta_context { 183 bool initialized; 184 uint32_t session_id; 185 uint32_t resp_status; 186 struct ta_mem_context mem_context; 187 struct psp_bin_desc bin_desc; 188 enum psp_gfx_cmd_id ta_load_type; 189 enum ta_type_id ta_type; 190 }; 191 192 struct ta_cp_context { 193 struct ta_context context; 194 struct mutex mutex; 195 }; 196 197 struct psp_xgmi_context { 198 struct ta_context context; 199 struct psp_xgmi_topology_info top_info; 200 bool supports_extended_data; 201 uint8_t xgmi_ta_caps; 202 }; 203 204 struct psp_ras_context { 205 struct ta_context context; 206 struct amdgpu_ras *ras; 207 struct mutex mutex; 208 }; 209 210 #define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942 211 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000 212 #define GDDR6_MEM_TRAINING_OFFSET 0x8000 213 /*Define the VRAM size that will be encroached by BIST training.*/ 214 #define BIST_MEM_TRAINING_ENCROACHED_SIZE 0x2000000 215 216 enum psp_memory_training_init_flag { 217 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0, 218 PSP_MEM_TRAIN_SUPPORT = 0x1, 219 PSP_MEM_TRAIN_INIT_FAILED = 0x2, 220 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4, 221 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8, 222 }; 223 224 enum psp_memory_training_ops { 225 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1, 226 PSP_MEM_TRAIN_SAVE = 0x2, 227 PSP_MEM_TRAIN_RESTORE = 0x4, 228 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8, 229 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG, 230 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG, 231 }; 232 233 struct psp_memory_training_context { 234 /*training data size*/ 235 u64 train_data_size; 236 /* 237 * sys_cache 238 * cpu virtual address 239 * system memory buffer that used to store the training data. 240 */ 241 void *sys_cache; 242 243 /*vram offset of the p2c training data*/ 244 u64 p2c_train_data_offset; 245 246 /*vram offset of the c2p training data*/ 247 u64 c2p_train_data_offset; 248 struct amdgpu_bo *c2p_bo; 249 250 enum psp_memory_training_init_flag init; 251 u32 training_cnt; 252 bool enable_mem_training; 253 }; 254 255 /** PSP runtime DB **/ 256 #define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000 257 #define PSP_RUNTIME_DB_OFFSET 0x100000 258 #define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5 259 #define PSP_RUNTIME_DB_VER_1 0x0100 260 #define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40 261 262 enum psp_runtime_entry_type { 263 PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0, 264 PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1, 265 PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */ 266 PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */ 267 PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */ 268 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */ 269 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */ 270 }; 271 272 /* PSP runtime DB header */ 273 struct psp_runtime_data_header { 274 /* determine the existence of runtime db */ 275 uint16_t cookie; 276 /* version of runtime db */ 277 uint16_t version; 278 }; 279 280 /* PSP runtime DB entry */ 281 struct psp_runtime_entry { 282 /* type of runtime db entry */ 283 uint32_t entry_type; 284 /* offset of entry in bytes */ 285 uint16_t offset; 286 /* size of entry in bytes */ 287 uint16_t size; 288 }; 289 290 /* PSP runtime DB directory */ 291 struct psp_runtime_data_directory { 292 /* number of valid entries */ 293 uint16_t entry_count; 294 /* db entries*/ 295 struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT]; 296 }; 297 298 /* PSP runtime DB boot config feature bitmask */ 299 enum psp_runtime_boot_cfg_feature { 300 BOOT_CFG_FEATURE_GECC = 0x1, 301 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2, 302 }; 303 304 /* PSP run time DB SCPM authentication defines */ 305 enum psp_runtime_scpm_authentication { 306 SCPM_DISABLE = 0x0, 307 SCPM_ENABLE = 0x1, 308 SCPM_ENABLE_WITH_SCPM_ERR = 0x2, 309 }; 310 311 /* PSP runtime DB boot config entry */ 312 struct psp_runtime_boot_cfg_entry { 313 uint32_t boot_cfg_bitmask; 314 uint32_t reserved; 315 }; 316 317 /* PSP runtime DB SCPM entry */ 318 struct psp_runtime_scpm_entry { 319 enum psp_runtime_scpm_authentication scpm_status; 320 }; 321 322 struct psp_context { 323 struct amdgpu_device *adev; 324 struct psp_ring km_ring; 325 struct psp_gfx_cmd_resp *cmd; 326 327 const struct psp_funcs *funcs; 328 const struct ta_funcs *ta_funcs; 329 330 /* firmware buffer */ 331 struct amdgpu_bo *fw_pri_bo; 332 uint64_t fw_pri_mc_addr; 333 void *fw_pri_buf; 334 335 /* sos firmware */ 336 const struct firmware *sos_fw; 337 struct psp_bin_desc sys; 338 struct psp_bin_desc sos; 339 struct psp_bin_desc toc; 340 struct psp_bin_desc kdb; 341 struct psp_bin_desc spl; 342 struct psp_bin_desc rl; 343 struct psp_bin_desc soc_drv; 344 struct psp_bin_desc intf_drv; 345 struct psp_bin_desc dbg_drv; 346 struct psp_bin_desc ras_drv; 347 struct psp_bin_desc ipkeymgr_drv; 348 struct psp_bin_desc spdm_drv; 349 350 /* tmr buffer */ 351 struct amdgpu_bo *tmr_bo; 352 uint64_t tmr_mc_addr; 353 354 /* asd firmware */ 355 const struct firmware *asd_fw; 356 357 /* toc firmware */ 358 const struct firmware *toc_fw; 359 360 /* cap firmware */ 361 const struct firmware *cap_fw; 362 363 /* fence buffer */ 364 struct amdgpu_bo *fence_buf_bo; 365 uint64_t fence_buf_mc_addr; 366 void *fence_buf; 367 368 /* cmd buffer */ 369 struct amdgpu_bo *cmd_buf_bo; 370 uint64_t cmd_buf_mc_addr; 371 struct psp_gfx_cmd_resp *cmd_buf_mem; 372 373 /* fence value associated with cmd buffer */ 374 atomic_t fence_value; 375 /* flag to mark whether gfx fw autoload is supported or not */ 376 bool autoload_supported; 377 /* flag to mark whether psp use runtime TMR or boottime TMR */ 378 bool boot_time_tmr; 379 /* flag to mark whether df cstate management centralized to PMFW */ 380 bool pmfw_centralized_cstate_management; 381 382 /* xgmi ta firmware and buffer */ 383 const struct firmware *ta_fw; 384 uint32_t ta_fw_version; 385 386 uint32_t cap_fw_version; 387 uint32_t cap_feature_version; 388 uint32_t cap_ucode_size; 389 390 struct ta_context asd_context; 391 struct psp_xgmi_context xgmi_context; 392 struct psp_ras_context ras_context; 393 struct ta_cp_context hdcp_context; 394 struct ta_cp_context dtm_context; 395 struct ta_cp_context rap_context; 396 struct ta_cp_context securedisplay_context; 397 struct mutex mutex; 398 struct psp_memory_training_context mem_train_ctx; 399 400 uint32_t boot_cfg_bitmask; 401 402 /* firmware upgrades supported */ 403 bool sup_pd_fw_up; 404 bool sup_ifwi_up; 405 406 char *vbflash_tmp_buf; 407 size_t vbflash_image_size; 408 bool vbflash_done; 409 }; 410 411 struct amdgpu_psp_funcs { 412 bool (*check_fw_loading_status)(struct amdgpu_device *adev, 413 enum AMDGPU_UCODE_ID); 414 }; 415 416 417 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 418 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 419 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 420 #define psp_init_microcode(psp) \ 421 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 422 #define psp_bootloader_load_kdb(psp) \ 423 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0) 424 #define psp_bootloader_load_spl(psp) \ 425 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0) 426 #define psp_bootloader_load_sysdrv(psp) \ 427 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 428 #define psp_bootloader_load_soc_drv(psp) \ 429 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0) 430 #define psp_bootloader_load_intf_drv(psp) \ 431 ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0) 432 #define psp_bootloader_load_dbg_drv(psp) \ 433 ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0) 434 #define psp_bootloader_load_ras_drv(psp) \ 435 ((psp)->funcs->bootloader_load_ras_drv ? \ 436 (psp)->funcs->bootloader_load_ras_drv((psp)) : 0) 437 #define psp_bootloader_load_ipkeymgr_drv(psp) \ 438 ((psp)->funcs->bootloader_load_ipkeymgr_drv ? \ 439 (psp)->funcs->bootloader_load_ipkeymgr_drv((psp)) : 0) 440 #define psp_bootloader_load_spdm_drv(psp) \ 441 ((psp)->funcs->bootloader_load_spdm_drv ? \ 442 (psp)->funcs->bootloader_load_spdm_drv((psp)) : 0) 443 #define psp_bootloader_load_sos(psp) \ 444 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 445 #define psp_smu_reload_quirk(psp) \ 446 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 447 #define psp_mode1_reset(psp) \ 448 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 449 #define psp_mem_training(psp, ops) \ 450 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0) 451 452 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp)) 453 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value)) 454 455 #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \ 456 ((psp)->funcs->load_usbc_pd_fw ? \ 457 (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL) 458 459 #define psp_read_usbc_pd_fw(psp, fw_ver) \ 460 ((psp)->funcs->read_usbc_pd_fw ? \ 461 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL) 462 463 #define psp_update_spirom(psp, fw_pri_mc_addr) \ 464 ((psp)->funcs->update_spirom ? \ 465 (psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL) 466 467 #define psp_vbflash_status(psp) \ 468 ((psp)->funcs->vbflash_stat ? \ 469 (psp)->funcs->vbflash_stat((psp)) : -EINVAL) 470 471 #define psp_fatal_error_recovery_quirk(psp) \ 472 ((psp)->funcs->fatal_error_recovery_quirk ? \ 473 (psp)->funcs->fatal_error_recovery_quirk((psp)) : 0) 474 475 #define psp_is_aux_sos_load_required(psp) \ 476 ((psp)->funcs->is_aux_sos_load_required ? (psp)->funcs->is_aux_sos_load_required((psp)) : 0) 477 478 extern const struct amd_ip_funcs psp_ip_funcs; 479 480 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 481 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 482 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; 483 extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block; 484 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; 485 extern const struct amdgpu_ip_block_version psp_v13_0_ip_block; 486 extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block; 487 extern const struct amdgpu_ip_block_version psp_v14_0_ip_block; 488 489 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 490 uint32_t field_val, uint32_t mask, bool check_changed); 491 extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 492 uint32_t field_val, uint32_t mask, uint32_t msec_timeout); 493 494 int psp_execute_ip_fw_load(struct psp_context *psp, 495 struct amdgpu_firmware_info *ucode); 496 497 int psp_gpu_reset(struct amdgpu_device *adev); 498 499 int psp_ta_init_shared_buf(struct psp_context *psp, 500 struct ta_mem_context *mem_ctx); 501 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx); 502 int psp_ta_unload(struct psp_context *psp, struct ta_context *context); 503 int psp_ta_load(struct psp_context *psp, struct ta_context *context); 504 int psp_ta_invoke(struct psp_context *psp, 505 uint32_t ta_cmd_id, 506 struct ta_context *context); 507 508 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta); 509 int psp_xgmi_terminate(struct psp_context *psp); 510 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 511 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id); 512 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id); 513 int psp_xgmi_get_topology_info(struct psp_context *psp, 514 int number_devices, 515 struct psp_xgmi_topology_info *topology, 516 bool get_extended_data); 517 int psp_xgmi_set_topology_info(struct psp_context *psp, 518 int number_devices, 519 struct psp_xgmi_topology_info *topology); 520 int psp_ras_initialize(struct psp_context *psp); 521 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 522 int psp_ras_enable_features(struct psp_context *psp, 523 union ta_ras_cmd_input *info, bool enable); 524 int psp_ras_trigger_error(struct psp_context *psp, 525 struct ta_ras_trigger_error_input *info, uint32_t instance_mask); 526 int psp_ras_terminate(struct psp_context *psp); 527 int psp_ras_query_address(struct psp_context *psp, 528 struct ta_ras_query_address_input *addr_in, 529 struct ta_ras_query_address_output *addr_out); 530 531 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 532 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 533 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status); 534 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 535 536 int psp_rlc_autoload_start(struct psp_context *psp); 537 538 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 539 uint32_t value); 540 int psp_ring_cmd_submit(struct psp_context *psp, 541 uint64_t cmd_buf_mc_addr, 542 uint64_t fence_mc_addr, 543 int index); 544 int psp_init_asd_microcode(struct psp_context *psp, 545 const char *chip_name); 546 int psp_init_toc_microcode(struct psp_context *psp, 547 const char *chip_name); 548 int psp_init_sos_microcode(struct psp_context *psp, 549 const char *chip_name); 550 int psp_init_ta_microcode(struct psp_context *psp, 551 const char *chip_name); 552 int psp_init_cap_microcode(struct psp_context *psp, 553 const char *chip_name); 554 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 555 uint64_t *output_ptr); 556 557 int psp_load_fw_list(struct psp_context *psp, 558 struct amdgpu_firmware_info **ucode_list, int ucode_count); 559 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size); 560 561 int psp_spatial_partition(struct psp_context *psp, int mode); 562 int psp_memory_partition(struct psp_context *psp, int mode); 563 564 int is_psp_fw_valid(struct psp_bin_desc bin); 565 566 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev); 567 bool amdgpu_psp_get_ras_capability(struct psp_context *psp); 568 569 int psp_config_sq_perfmon(struct psp_context *psp, uint32_t xcp_id, 570 bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable); 571 bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev); 572 573 #endif 574