1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. 4 */ 5 6 #include <drm/amdxdna_accel.h> 7 #include <drm/drm_device.h> 8 #include <drm/drm_drv.h> 9 #include <drm/drm_file.h> 10 #include <drm/drm_gem.h> 11 #include <drm/drm_gem_shmem_helper.h> 12 #include <drm/drm_print.h> 13 #include <drm/gpu_scheduler.h> 14 #include <linux/xarray.h> 15 #include <trace/events/amdxdna.h> 16 17 #include "amdxdna_ctx.h" 18 #include "amdxdna_gem.h" 19 #include "amdxdna_pci_drv.h" 20 #include "amdxdna_pm.h" 21 22 #define MAX_HWCTX_ID 255 23 #define MAX_ARG_COUNT 4095 24 25 struct amdxdna_fence { 26 struct dma_fence base; 27 spinlock_t lock; /* for base */ 28 struct amdxdna_hwctx *hwctx; 29 }; 30 31 static const char *amdxdna_fence_get_driver_name(struct dma_fence *fence) 32 { 33 return KBUILD_MODNAME; 34 } 35 36 static const char *amdxdna_fence_get_timeline_name(struct dma_fence *fence) 37 { 38 struct amdxdna_fence *xdna_fence; 39 40 xdna_fence = container_of(fence, struct amdxdna_fence, base); 41 42 return xdna_fence->hwctx->name; 43 } 44 45 static const struct dma_fence_ops fence_ops = { 46 .get_driver_name = amdxdna_fence_get_driver_name, 47 .get_timeline_name = amdxdna_fence_get_timeline_name, 48 }; 49 50 static struct dma_fence *amdxdna_fence_create(struct amdxdna_hwctx *hwctx) 51 { 52 struct amdxdna_fence *fence; 53 54 fence = kzalloc_obj(*fence); 55 if (!fence) 56 return NULL; 57 58 fence->hwctx = hwctx; 59 spin_lock_init(&fence->lock); 60 dma_fence_init(&fence->base, &fence_ops, &fence->lock, hwctx->id, 0); 61 return &fence->base; 62 } 63 64 static void amdxdna_hwctx_release_expanded_heap(struct amdxdna_hwctx *hwctx) 65 { 66 struct amdxdna_client *client = hwctx->client; 67 struct amdxdna_gem_obj *heap; 68 unsigned long heap_id; 69 70 mutex_lock(&client->mm_lock); 71 if (hwctx->last_attached_heap) { 72 xa_for_each_range(&client->dev_heap_xa, heap_id, heap, 1, 73 hwctx->last_attached_heap) { 74 amdxdna_gem_unpin(heap); 75 drm_gem_object_put(to_gobj(heap)); 76 } 77 } 78 mutex_unlock(&client->mm_lock); 79 } 80 81 static void amdxdna_hwctx_destroy_rcu(struct amdxdna_hwctx *hwctx, 82 struct srcu_struct *ss) 83 { 84 struct amdxdna_client *client = hwctx->client; 85 struct amdxdna_dev *xdna = client->xdna; 86 87 synchronize_srcu(ss); 88 89 /* At this point, user is not able to submit new commands */ 90 xdna->dev_info->ops->hwctx_fini(hwctx); 91 92 amdxdna_hwctx_release_expanded_heap(hwctx); 93 kfree(hwctx->name); 94 kfree(hwctx); 95 } 96 97 int amdxdna_hwctx_walk(struct amdxdna_client *client, void *arg, 98 int (*walk)(struct amdxdna_hwctx *hwctx, void *arg)) 99 { 100 struct amdxdna_hwctx *hwctx; 101 unsigned long hwctx_id; 102 int ret = 0, idx; 103 104 idx = srcu_read_lock(&client->hwctx_srcu); 105 amdxdna_for_each_hwctx(client, hwctx_id, hwctx) { 106 ret = walk(hwctx, arg); 107 if (ret) 108 break; 109 } 110 srcu_read_unlock(&client->hwctx_srcu, idx); 111 112 return ret; 113 } 114 115 void *amdxdna_cmd_get_payload(struct amdxdna_gem_obj *abo, u32 *size) 116 { 117 struct amdxdna_cmd *cmd = amdxdna_gem_vmap(abo); 118 u32 num_masks, count; 119 120 if (!cmd) 121 return NULL; 122 123 if (amdxdna_cmd_get_op(abo) == ERT_CMD_CHAIN) 124 num_masks = 0; 125 else 126 num_masks = 1 + FIELD_GET(AMDXDNA_CMD_EXTRA_CU_MASK, cmd->header); 127 128 if (size) { 129 count = FIELD_GET(AMDXDNA_CMD_COUNT, cmd->header); 130 if (unlikely(count <= num_masks || 131 count * sizeof(u32) + 132 offsetof(struct amdxdna_cmd, data[0]) > 133 abo->mem.size)) { 134 *size = 0; 135 return NULL; 136 } 137 *size = (count - num_masks) * sizeof(u32); 138 } 139 return &cmd->data[num_masks]; 140 } 141 142 u32 amdxdna_cmd_get_cu_idx(struct amdxdna_gem_obj *abo) 143 { 144 struct amdxdna_cmd *cmd = amdxdna_gem_vmap(abo); 145 u32 num_masks, i; 146 u32 *cu_mask; 147 148 if (!cmd) 149 return INVALID_CU_IDX; 150 151 if (amdxdna_cmd_get_op(abo) == ERT_CMD_CHAIN) 152 return INVALID_CU_IDX; 153 154 num_masks = 1 + FIELD_GET(AMDXDNA_CMD_EXTRA_CU_MASK, cmd->header); 155 cu_mask = cmd->data; 156 for (i = 0; i < num_masks; i++) { 157 if (cu_mask[i]) 158 return ffs(cu_mask[i]) - 1; 159 } 160 161 return INVALID_CU_IDX; 162 } 163 164 int amdxdna_cmd_set_error(struct amdxdna_gem_obj *abo, 165 struct amdxdna_sched_job *job, u32 cmd_idx, 166 enum ert_cmd_state error_state, 167 void *err_data, size_t size) 168 { 169 struct amdxdna_client *client = job->hwctx->client; 170 struct amdxdna_cmd *cmd = amdxdna_gem_vmap(abo); 171 struct amdxdna_cmd_chain *cc = NULL; 172 173 if (!cmd) 174 return -ENOMEM; 175 176 cmd->header &= ~AMDXDNA_CMD_STATE; 177 cmd->header |= FIELD_PREP(AMDXDNA_CMD_STATE, error_state); 178 179 if (amdxdna_cmd_get_op(abo) == ERT_CMD_CHAIN) { 180 cc = amdxdna_cmd_get_payload(abo, NULL); 181 cc->error_index = (cmd_idx < cc->command_count) ? cmd_idx : 0; 182 abo = amdxdna_gem_get_obj(client, cc->data[0], AMDXDNA_BO_SHARE); 183 if (!abo) 184 return -EINVAL; 185 cmd = amdxdna_gem_vmap(abo); 186 if (!cmd) 187 return -ENOMEM; 188 } 189 190 memset(cmd->data, 0xff, abo->mem.size - sizeof(*cmd)); 191 if (err_data) 192 memcpy(cmd->data, err_data, min(size, abo->mem.size - sizeof(*cmd))); 193 194 if (cc) 195 amdxdna_gem_put_obj(abo); 196 197 return 0; 198 } 199 200 /* 201 * This should be called in close() and remove(). DO NOT call in other syscalls. 202 * This guarantee that when hwctx and resources will be released, if user 203 * doesn't call amdxdna_drm_destroy_hwctx_ioctl. 204 */ 205 void amdxdna_hwctx_remove_all(struct amdxdna_client *client) 206 { 207 struct amdxdna_hwctx *hwctx; 208 unsigned long hwctx_id; 209 210 amdxdna_for_each_hwctx(client, hwctx_id, hwctx) { 211 XDNA_DBG(client->xdna, "PID %d close HW context %d", 212 client->pid, hwctx->id); 213 xa_erase(&client->hwctx_xa, hwctx->id); 214 amdxdna_hwctx_destroy_rcu(hwctx, &client->hwctx_srcu); 215 } 216 } 217 218 int amdxdna_drm_create_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 219 { 220 struct amdxdna_client *client = filp->driver_priv; 221 struct amdxdna_drm_create_hwctx *args = data; 222 struct amdxdna_dev *xdna = to_xdna_dev(dev); 223 struct amdxdna_hwctx *hwctx; 224 int ret, idx; 225 226 if (args->ext || args->ext_flags) 227 return -EINVAL; 228 229 if (!xdna->dev_info->ops->hwctx_init) 230 return -EOPNOTSUPP; 231 232 hwctx = kzalloc_obj(*hwctx); 233 if (!hwctx) 234 return -ENOMEM; 235 236 if (copy_from_user(&hwctx->qos, u64_to_user_ptr(args->qos_p), sizeof(hwctx->qos))) { 237 XDNA_ERR(xdna, "Access QoS info failed"); 238 kfree(hwctx); 239 return -EFAULT; 240 } 241 242 hwctx->client = client; 243 hwctx->fw_ctx_id = -1; 244 hwctx->num_tiles = args->num_tiles; 245 hwctx->umq_bo_hdl = args->umq_bo; 246 hwctx->doorbell_offset = AMDXDNA_INVALID_DOORBELL_OFFSET; 247 hwctx->mem_size = args->mem_size; 248 hwctx->max_opc = args->max_opc; 249 250 guard(mutex)(&xdna->dev_lock); 251 252 if (!drm_dev_enter(dev, &idx)) { 253 ret = -ENODEV; 254 goto free_hwctx; 255 } 256 257 ret = xdna->dev_info->ops->hwctx_init(hwctx); 258 if (ret) { 259 XDNA_ERR(xdna, "Init hwctx failed, ret %d", ret); 260 goto release_expanded_heap; 261 } 262 263 hwctx->name = kasprintf(GFP_KERNEL, "hwctx.%d.%d", client->pid, hwctx->fw_ctx_id); 264 if (!hwctx->name) { 265 ret = -ENOMEM; 266 goto fini_hwctx; 267 } 268 269 ret = xa_alloc_cyclic(&client->hwctx_xa, &hwctx->id, hwctx, 270 XA_LIMIT(AMDXDNA_INVALID_CTX_HANDLE + 1, MAX_HWCTX_ID), 271 &client->next_hwctxid, GFP_KERNEL); 272 if (ret < 0) { 273 XDNA_ERR(xdna, "Allocate hwctx ID failed, ret %d", ret); 274 goto free_name; 275 } 276 277 args->handle = hwctx->id; 278 args->syncobj_handle = hwctx->syncobj_hdl; 279 args->umq_doorbell = hwctx->doorbell_offset; 280 281 atomic64_set(&hwctx->job_submit_cnt, 0); 282 atomic64_set(&hwctx->job_free_cnt, 0); 283 XDNA_DBG(xdna, "PID %d create HW context %d, ret %d", client->pid, args->handle, ret); 284 drm_dev_exit(idx); 285 return 0; 286 287 free_name: 288 kfree(hwctx->name); 289 fini_hwctx: 290 xdna->dev_info->ops->hwctx_fini(hwctx); 291 release_expanded_heap: 292 amdxdna_hwctx_release_expanded_heap(hwctx); 293 drm_dev_exit(idx); 294 free_hwctx: 295 kfree(hwctx); 296 return ret; 297 } 298 299 int amdxdna_drm_destroy_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 300 { 301 struct amdxdna_client *client = filp->driver_priv; 302 struct amdxdna_drm_destroy_hwctx *args = data; 303 struct amdxdna_dev *xdna = to_xdna_dev(dev); 304 struct amdxdna_hwctx *hwctx; 305 int ret = 0, idx; 306 307 if (XDNA_MBZ_DBG(xdna, &args->pad, sizeof(args->pad))) 308 return -EINVAL; 309 310 if (!drm_dev_enter(dev, &idx)) 311 return -ENODEV; 312 313 mutex_lock(&xdna->dev_lock); 314 hwctx = xa_erase(&client->hwctx_xa, args->handle); 315 if (!hwctx) { 316 ret = -EINVAL; 317 XDNA_DBG(xdna, "PID %d HW context %d not exist", 318 client->pid, args->handle); 319 goto out; 320 } 321 322 /* 323 * The pushed jobs are handled by DRM scheduler during destroy. 324 * SRCU to synchronize with exec command ioctls. 325 */ 326 amdxdna_hwctx_destroy_rcu(hwctx, &client->hwctx_srcu); 327 328 XDNA_DBG(xdna, "PID %d destroyed HW context %d", client->pid, args->handle); 329 out: 330 mutex_unlock(&xdna->dev_lock); 331 drm_dev_exit(idx); 332 return ret; 333 } 334 335 int amdxdna_drm_config_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 336 { 337 struct amdxdna_client *client = filp->driver_priv; 338 struct amdxdna_drm_config_hwctx *args = data; 339 struct amdxdna_dev *xdna = to_xdna_dev(dev); 340 struct amdxdna_hwctx *hwctx; 341 u32 buf_size; 342 void *buf; 343 int ret; 344 u64 val; 345 346 if (XDNA_MBZ_DBG(xdna, &args->pad, sizeof(args->pad))) 347 return -EINVAL; 348 349 if (!xdna->dev_info->ops->hwctx_config) 350 return -EOPNOTSUPP; 351 352 val = args->param_val; 353 buf_size = args->param_val_size; 354 355 switch (args->param_type) { 356 case DRM_AMDXDNA_HWCTX_CONFIG_CU: 357 /* For those types that param_val is pointer */ 358 if (buf_size > PAGE_SIZE) { 359 XDNA_ERR(xdna, "Config CU param buffer too large"); 360 return -E2BIG; 361 } 362 363 /* Hwctx needs to keep buf */ 364 buf = kzalloc(PAGE_SIZE, GFP_KERNEL); 365 if (!buf) 366 return -ENOMEM; 367 368 if (copy_from_user(buf, u64_to_user_ptr(val), buf_size)) { 369 kfree(buf); 370 return -EFAULT; 371 } 372 373 break; 374 case DRM_AMDXDNA_HWCTX_ASSIGN_DBG_BUF: 375 case DRM_AMDXDNA_HWCTX_REMOVE_DBG_BUF: 376 /* For those types that param_val is a value */ 377 buf = NULL; 378 buf_size = 0; 379 break; 380 default: 381 XDNA_DBG(xdna, "Unknown HW context config type %d", args->param_type); 382 return -EINVAL; 383 } 384 385 guard(mutex)(&xdna->dev_lock); 386 hwctx = xa_load(&client->hwctx_xa, args->handle); 387 if (!hwctx) { 388 XDNA_DBG(xdna, "PID %d failed to get hwctx %d", client->pid, args->handle); 389 ret = -EINVAL; 390 goto free_buf; 391 } 392 393 ret = xdna->dev_info->ops->hwctx_config(hwctx, args->param_type, val, buf, buf_size); 394 395 free_buf: 396 kfree(buf); 397 return ret; 398 } 399 400 int amdxdna_hwctx_sync_debug_bo(struct amdxdna_client *client, u32 debug_bo_hdl) 401 { 402 struct amdxdna_dev *xdna = client->xdna; 403 struct amdxdna_hwctx *hwctx; 404 struct amdxdna_gem_obj *abo; 405 struct drm_gem_object *gobj; 406 int ret; 407 408 if (!xdna->dev_info->ops->hwctx_sync_debug_bo) 409 return -EOPNOTSUPP; 410 411 gobj = drm_gem_object_lookup(client->filp, debug_bo_hdl); 412 if (!gobj) 413 return -EINVAL; 414 415 abo = to_xdna_obj(gobj); 416 guard(mutex)(&xdna->dev_lock); 417 hwctx = xa_load(&client->hwctx_xa, abo->assigned_hwctx); 418 if (!hwctx) { 419 ret = -EINVAL; 420 goto put_obj; 421 } 422 423 ret = xdna->dev_info->ops->hwctx_sync_debug_bo(hwctx, debug_bo_hdl); 424 425 put_obj: 426 drm_gem_object_put(gobj); 427 return ret; 428 } 429 430 static int amdxdna_hwctx_expand_heap(struct amdxdna_hwctx *hwctx) 431 { 432 struct amdxdna_client *client = hwctx->client; 433 struct amdxdna_dev *xdna = client->xdna; 434 struct amdxdna_gem_obj *heap; 435 unsigned long heap_id, nid; 436 int ret = 0; 437 438 nid = hwctx->last_attached_heap + 1; 439 if (nid == client->dev_heap_nid) 440 goto out; 441 442 xa_for_each_range(&client->dev_heap_xa, heap_id, heap, 443 nid, client->dev_heap_nid) { 444 drm_gem_object_get(to_gobj(heap)); 445 ret = amdxdna_gem_pin(heap); 446 if (ret) { 447 drm_gem_object_put(to_gobj(heap)); 448 break; 449 } 450 451 mutex_unlock(&client->mm_lock); 452 ret = xdna->dev_info->ops->hwctx_heap_expand(hwctx, heap); 453 mutex_lock(&client->mm_lock); 454 if (ret) { 455 amdxdna_gem_unpin(heap); 456 drm_gem_object_put(to_gobj(heap)); 457 break; 458 } 459 460 hwctx->last_attached_heap = heap_id; 461 } 462 463 out: 464 return ret; 465 } 466 467 int amdxdna_update_heap(struct amdxdna_client *client, struct amdxdna_hwctx *hwctx) 468 { 469 unsigned long hwctx_id; 470 int ret; 471 472 guard(mutex)(&client->mm_lock); 473 474 if (hwctx) 475 return amdxdna_hwctx_expand_heap(hwctx); 476 477 amdxdna_for_each_hwctx(client, hwctx_id, hwctx) { 478 ret = amdxdna_hwctx_expand_heap(hwctx); 479 if (ret) 480 return ret; 481 } 482 483 return 0; 484 } 485 486 static void 487 amdxdna_arg_bos_put(struct amdxdna_sched_job *job) 488 { 489 int i; 490 491 for (i = 0; i < job->bo_cnt; i++) { 492 if (!job->bos[i]) 493 break; 494 drm_gem_object_put(job->bos[i]); 495 } 496 } 497 498 static int 499 amdxdna_arg_bos_lookup(struct amdxdna_client *client, 500 struct amdxdna_sched_job *job, 501 u32 *bo_hdls, u32 bo_cnt) 502 { 503 struct drm_gem_object *gobj; 504 int i, ret; 505 506 job->bo_cnt = bo_cnt; 507 for (i = 0; i < job->bo_cnt; i++) { 508 struct amdxdna_gem_obj *abo; 509 510 gobj = drm_gem_object_lookup(client->filp, bo_hdls[i]); 511 if (!gobj) { 512 ret = -ENOENT; 513 goto put_shmem_bo; 514 } 515 abo = to_xdna_obj(gobj); 516 517 mutex_lock(&abo->lock); 518 if (abo->pinned) { 519 mutex_unlock(&abo->lock); 520 job->bos[i] = gobj; 521 continue; 522 } 523 524 ret = amdxdna_gem_pin_nolock(abo); 525 if (ret) { 526 mutex_unlock(&abo->lock); 527 drm_gem_object_put(gobj); 528 goto put_shmem_bo; 529 } 530 abo->pinned = true; 531 mutex_unlock(&abo->lock); 532 533 job->bos[i] = gobj; 534 } 535 536 return 0; 537 538 put_shmem_bo: 539 amdxdna_arg_bos_put(job); 540 return ret; 541 } 542 543 void amdxdna_sched_job_cleanup(struct amdxdna_sched_job *job) 544 { 545 trace_amdxdna_debug_point(job->hwctx->name, job->seq, "job release"); 546 amdxdna_pm_suspend_put(job->hwctx->client->xdna); 547 amdxdna_arg_bos_put(job); 548 amdxdna_gem_put_obj(job->cmd_bo); 549 dma_fence_put(job->fence); 550 } 551 552 int amdxdna_cmd_submit(struct amdxdna_client *client, 553 struct amdxdna_drv_cmd *drv_cmd, 554 u32 cmd_bo_hdl, u32 *arg_bo_hdls, u32 arg_bo_cnt, 555 u32 hwctx_hdl, u64 *seq) 556 { 557 struct amdxdna_dev *xdna = client->xdna; 558 struct amdxdna_sched_job *job; 559 struct amdxdna_hwctx *hwctx; 560 int ret, idx; 561 562 XDNA_DBG(xdna, "Command BO hdl %d, Arg BO count %d", cmd_bo_hdl, arg_bo_cnt); 563 job = kzalloc_flex(*job, bos, arg_bo_cnt); 564 if (!job) 565 return -ENOMEM; 566 567 job->drv_cmd = drv_cmd; 568 569 if (cmd_bo_hdl != AMDXDNA_INVALID_BO_HANDLE) { 570 job->cmd_bo = amdxdna_gem_get_obj(client, cmd_bo_hdl, AMDXDNA_BO_SHARE); 571 if (!job->cmd_bo) { 572 XDNA_ERR(xdna, "Failed to get cmd bo from %d", cmd_bo_hdl); 573 ret = -EINVAL; 574 goto free_job; 575 } 576 } 577 578 ret = amdxdna_arg_bos_lookup(client, job, arg_bo_hdls, arg_bo_cnt); 579 if (ret) { 580 XDNA_ERR(xdna, "Argument BOs lookup failed, ret %d", ret); 581 goto cmd_put; 582 } 583 584 ret = amdxdna_pm_resume_get(xdna); 585 if (ret) { 586 XDNA_ERR(xdna, "Resume failed, ret %d", ret); 587 goto put_bos; 588 } 589 590 idx = srcu_read_lock(&client->hwctx_srcu); 591 hwctx = xa_load(&client->hwctx_xa, hwctx_hdl); 592 if (!hwctx) { 593 XDNA_DBG(xdna, "PID %d failed to get hwctx %d", 594 client->pid, hwctx_hdl); 595 ret = -EINVAL; 596 goto unlock_srcu; 597 } 598 599 job->hwctx = hwctx; 600 job->mm = current->mm; 601 602 job->fence = amdxdna_fence_create(hwctx); 603 if (!job->fence) { 604 XDNA_ERR(xdna, "Failed to create fence"); 605 ret = -ENOMEM; 606 goto unlock_srcu; 607 } 608 kref_init(&job->refcnt); 609 610 ret = xdna->dev_info->ops->cmd_submit(hwctx, job, seq); 611 if (ret) 612 goto put_fence; 613 614 /* 615 * The amdxdna_hwctx_destroy_rcu() will release hwctx and associated 616 * resource after synchronize_srcu(). The submitted jobs should be 617 * handled by the queue, for example DRM scheduler, in device layer. 618 * For here we can unlock SRCU. 619 */ 620 srcu_read_unlock(&client->hwctx_srcu, idx); 621 trace_amdxdna_debug_point(hwctx->name, *seq, "job pushed"); 622 623 return 0; 624 625 put_fence: 626 dma_fence_put(job->fence); 627 unlock_srcu: 628 srcu_read_unlock(&client->hwctx_srcu, idx); 629 amdxdna_pm_suspend_put(xdna); 630 put_bos: 631 amdxdna_arg_bos_put(job); 632 cmd_put: 633 amdxdna_gem_put_obj(job->cmd_bo); 634 free_job: 635 kfree(job); 636 return ret; 637 } 638 639 /* 640 * The submit command ioctl submits a command to firmware. One firmware command 641 * may contain multiple command BOs for processing as a whole. 642 * The command sequence number is returned which can be used for wait command ioctl. 643 */ 644 static int amdxdna_drm_submit_execbuf(struct amdxdna_client *client, 645 struct amdxdna_drm_exec_cmd *args) 646 { 647 struct amdxdna_dev *xdna = client->xdna; 648 u32 *arg_bo_hdls = NULL; 649 u32 cmd_bo_hdl; 650 int ret; 651 652 if (args->arg_count > MAX_ARG_COUNT) { 653 XDNA_ERR(xdna, "Invalid arg bo count %d", args->arg_count); 654 return -EINVAL; 655 } 656 657 /* Only support single command for now. */ 658 if (args->cmd_count != 1) { 659 XDNA_ERR(xdna, "Invalid cmd bo count %d", args->cmd_count); 660 return -EINVAL; 661 } 662 663 cmd_bo_hdl = (u32)args->cmd_handles; 664 if (args->arg_count) { 665 arg_bo_hdls = kcalloc(args->arg_count, sizeof(u32), GFP_KERNEL); 666 if (!arg_bo_hdls) 667 return -ENOMEM; 668 ret = copy_from_user(arg_bo_hdls, u64_to_user_ptr(args->args), 669 args->arg_count * sizeof(u32)); 670 if (ret) { 671 ret = -EFAULT; 672 goto free_cmd_bo_hdls; 673 } 674 } 675 676 ret = amdxdna_cmd_submit(client, NULL, cmd_bo_hdl, arg_bo_hdls, 677 args->arg_count, args->hwctx, &args->seq); 678 if (ret) 679 XDNA_DBG(xdna, "Submit cmds failed, ret %d", ret); 680 681 free_cmd_bo_hdls: 682 kfree(arg_bo_hdls); 683 if (!ret) 684 XDNA_DBG(xdna, "Pushed cmd %lld to scheduler", args->seq); 685 return ret; 686 } 687 688 int amdxdna_drm_submit_cmd_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 689 { 690 struct amdxdna_client *client = filp->driver_priv; 691 struct amdxdna_drm_exec_cmd *args = data; 692 693 if (args->ext || args->ext_flags) 694 return -EINVAL; 695 696 trace_amdxdna_debug_point(current->comm, args->type, "job received"); 697 698 switch (args->type) { 699 case AMDXDNA_CMD_SUBMIT_EXEC_BUF: 700 return amdxdna_drm_submit_execbuf(client, args); 701 } 702 703 XDNA_ERR(client->xdna, "Invalid command type %d", args->type); 704 return -EINVAL; 705 } 706 707 int amdxdna_drm_wait_cmd_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 708 { 709 struct amdxdna_client *client = filp->driver_priv; 710 struct amdxdna_dev *xdna = to_xdna_dev(dev); 711 struct amdxdna_drm_wait_cmd *args = data; 712 struct amdxdna_hwctx *hwctx; 713 int ret, idx; 714 715 XDNA_DBG(xdna, "PID %d ctx %d timeout set %d ms for cmd %llu", 716 client->pid, args->hwctx, args->timeout, args->seq); 717 718 if (!xdna->dev_info->ops->cmd_wait) 719 return -EOPNOTSUPP; 720 721 idx = srcu_read_lock(&client->hwctx_srcu); 722 hwctx = xa_load(&client->hwctx_xa, args->hwctx); 723 if (!hwctx) { 724 XDNA_DBG(xdna, "PID %d failed to get ctx %d", client->pid, args->hwctx); 725 ret = -EINVAL; 726 goto unlock_ctx_srcu; 727 } 728 729 ret = xdna->dev_info->ops->cmd_wait(hwctx, args->seq, args->timeout); 730 731 XDNA_DBG(xdna, "PID %d ctx %d cmd %lld wait finished, ret %d", 732 client->pid, args->hwctx, args->seq, ret); 733 734 trace_amdxdna_debug_point(current->comm, args->seq, "job returned to user"); 735 736 unlock_ctx_srcu: 737 srcu_read_unlock(&client->hwctx_srcu, idx); 738 return ret; 739 } 740