1 /*
2 * Copyright 2015-2026 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "core_types.h"
28 #include "timing_generator.h"
29 #include "hw_sequencer.h"
30 #include "hw_sequencer_private.h"
31 #include "basics/dc_common.h"
32 #include "resource.h"
33 #include "dc_dmub_srv.h"
34 #include "dc_state_priv.h"
35 #include "opp.h"
36 #include "dsc.h"
37 #include "dchubbub.h"
38 #include "dccg.h"
39 #include "abm.h"
40 #include "dcn10/dcn10_hubbub.h"
41 #include "dce/dmub_hw_lock_mgr.h"
42
43 #define MAX_NUM_MCACHE 8
44
45 /* used as index in array of black_color_format */
46 enum black_color_format {
47 BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,
48 BLACK_COLOR_FORMAT_RGB_LIMITED,
49 BLACK_COLOR_FORMAT_YUV_TV,
50 BLACK_COLOR_FORMAT_YUV_CV,
51 BLACK_COLOR_FORMAT_YUV_SUPER_AA,
52 BLACK_COLOR_FORMAT_DEBUG,
53 };
54
55 enum dc_color_space_type {
56 COLOR_SPACE_RGB_TYPE,
57 COLOR_SPACE_RGB_LIMITED_TYPE,
58 COLOR_SPACE_YCBCR601_TYPE,
59 COLOR_SPACE_YCBCR709_TYPE,
60 COLOR_SPACE_YCBCR2020_TYPE,
61 COLOR_SPACE_YCBCR601_LIMITED_TYPE,
62 COLOR_SPACE_YCBCR709_LIMITED_TYPE,
63 COLOR_SPACE_YCBCR709_BLACK_TYPE,
64 };
65
66 static const struct tg_color black_color_format[] = {
67 /* BlackColorFormat_RGB_FullRange */
68 {0, 0, 0},
69 /* BlackColorFormat_RGB_Limited */
70 {0x40, 0x40, 0x40},
71 /* BlackColorFormat_YUV_TV */
72 {0x200, 0x40, 0x200},
73 /* BlackColorFormat_YUV_CV */
74 {0x1f4, 0x40, 0x1f4},
75 /* BlackColorFormat_YUV_SuperAA */
76 {0x1a2, 0x20, 0x1a2},
77 /* visual confirm debug */
78 {0xff, 0xff, 0},
79 };
80
81 struct out_csc_color_matrix_type {
82 enum dc_color_space_type color_space_type;
83 uint16_t regval[12];
84 };
85
86 static const struct out_csc_color_matrix_type output_csc_matrix[] = {
87 { COLOR_SPACE_RGB_TYPE,
88 { 0x2000, 0, 0, 0,
89 0, 0x2000, 0, 0,
90 0, 0, 0x2000, 0} },
91 { COLOR_SPACE_RGB_LIMITED_TYPE,
92 { 0x1B67, 0, 0, 0x201,
93 0, 0x1B67, 0, 0x201,
94 0, 0, 0x1B67, 0x201} },
95 { COLOR_SPACE_YCBCR601_TYPE,
96 { 0xE04, 0xF444, 0xFDB9, 0x1004,
97 0x831, 0x1016, 0x320, 0x201,
98 0xFB45, 0xF6B7, 0xE04, 0x1004} },
99 { COLOR_SPACE_YCBCR709_TYPE,
100 { 0xE04, 0xF345, 0xFEB7, 0x1004,
101 0x5D3, 0x1399, 0x1FA, 0x201,
102 0xFCCA, 0xF533, 0xE04, 0x1004} },
103 /* TODO: correct values below */
104 { COLOR_SPACE_YCBCR601_LIMITED_TYPE,
105 { 0xE00, 0xF447, 0xFDB9, 0x1000,
106 0x991, 0x12C9, 0x3A6, 0x200,
107 0xFB47, 0xF6B9, 0xE00, 0x1000} },
108 { COLOR_SPACE_YCBCR709_LIMITED_TYPE,
109 { 0xE00, 0xF349, 0xFEB7, 0x1000,
110 0x6CE, 0x16E3, 0x24F, 0x200,
111 0xFCCB, 0xF535, 0xE00, 0x1000} },
112 { COLOR_SPACE_YCBCR2020_TYPE,
113 { 0x1000, 0xF149, 0xFEB7, 0x1004,
114 0x0868, 0x15B2, 0x01E6, 0x201,
115 0xFB88, 0xF478, 0x1000, 0x1004} },
116 { COLOR_SPACE_YCBCR709_BLACK_TYPE,
117 { 0x0000, 0x0000, 0x0000, 0x1000,
118 0x0000, 0x0000, 0x0000, 0x0200,
119 0x0000, 0x0000, 0x0000, 0x1000} },
120 };
121
is_rgb_type(enum dc_color_space color_space)122 static bool is_rgb_type(
123 enum dc_color_space color_space)
124 {
125 bool ret = false;
126
127 if (color_space == COLOR_SPACE_SRGB ||
128 color_space == COLOR_SPACE_XR_RGB ||
129 color_space == COLOR_SPACE_MSREF_SCRGB ||
130 color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
131 color_space == COLOR_SPACE_ADOBERGB ||
132 color_space == COLOR_SPACE_DCIP3 ||
133 color_space == COLOR_SPACE_DOLBYVISION)
134 ret = true;
135 return ret;
136 }
137
is_rgb_limited_type(enum dc_color_space color_space)138 static bool is_rgb_limited_type(
139 enum dc_color_space color_space)
140 {
141 bool ret = false;
142
143 if (color_space == COLOR_SPACE_SRGB_LIMITED ||
144 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE)
145 ret = true;
146 return ret;
147 }
148
is_ycbcr601_type(enum dc_color_space color_space)149 static bool is_ycbcr601_type(
150 enum dc_color_space color_space)
151 {
152 bool ret = false;
153
154 if (color_space == COLOR_SPACE_YCBCR601 ||
155 color_space == COLOR_SPACE_XV_YCC_601)
156 ret = true;
157 return ret;
158 }
159
is_ycbcr601_limited_type(enum dc_color_space color_space)160 static bool is_ycbcr601_limited_type(
161 enum dc_color_space color_space)
162 {
163 bool ret = false;
164
165 if (color_space == COLOR_SPACE_YCBCR601_LIMITED)
166 ret = true;
167 return ret;
168 }
169
is_ycbcr709_type(enum dc_color_space color_space)170 static bool is_ycbcr709_type(
171 enum dc_color_space color_space)
172 {
173 bool ret = false;
174
175 if (color_space == COLOR_SPACE_YCBCR709 ||
176 color_space == COLOR_SPACE_XV_YCC_709)
177 ret = true;
178 return ret;
179 }
180
is_ycbcr2020_type(enum dc_color_space color_space)181 static bool is_ycbcr2020_type(
182 enum dc_color_space color_space)
183 {
184 bool ret = false;
185
186 if (color_space == COLOR_SPACE_2020_YCBCR_LIMITED || color_space == COLOR_SPACE_2020_YCBCR_FULL)
187 ret = true;
188 return ret;
189 }
190
is_ycbcr709_limited_type(enum dc_color_space color_space)191 static bool is_ycbcr709_limited_type(
192 enum dc_color_space color_space)
193 {
194 bool ret = false;
195
196 if (color_space == COLOR_SPACE_YCBCR709_LIMITED)
197 ret = true;
198 return ret;
199 }
200
get_color_space_type(enum dc_color_space color_space)201 static enum dc_color_space_type get_color_space_type(enum dc_color_space color_space)
202 {
203 enum dc_color_space_type type = COLOR_SPACE_RGB_TYPE;
204
205 if (is_rgb_type(color_space))
206 type = COLOR_SPACE_RGB_TYPE;
207 else if (is_rgb_limited_type(color_space))
208 type = COLOR_SPACE_RGB_LIMITED_TYPE;
209 else if (is_ycbcr601_type(color_space))
210 type = COLOR_SPACE_YCBCR601_TYPE;
211 else if (is_ycbcr709_type(color_space))
212 type = COLOR_SPACE_YCBCR709_TYPE;
213 else if (is_ycbcr601_limited_type(color_space))
214 type = COLOR_SPACE_YCBCR601_LIMITED_TYPE;
215 else if (is_ycbcr709_limited_type(color_space))
216 type = COLOR_SPACE_YCBCR709_LIMITED_TYPE;
217 else if (is_ycbcr2020_type(color_space))
218 type = COLOR_SPACE_YCBCR2020_TYPE;
219 else if (color_space == COLOR_SPACE_YCBCR709)
220 type = COLOR_SPACE_YCBCR709_BLACK_TYPE;
221 else if (color_space == COLOR_SPACE_YCBCR709_BLACK)
222 type = COLOR_SPACE_YCBCR709_BLACK_TYPE;
223 return type;
224 }
225
find_color_matrix(enum dc_color_space color_space,uint32_t * array_size)226 const uint16_t *find_color_matrix(enum dc_color_space color_space,
227 uint32_t *array_size)
228 {
229 int i;
230 enum dc_color_space_type type;
231 const uint16_t *val = NULL;
232 int arr_size = ARRAY_SIZE(output_csc_matrix);
233
234 type = get_color_space_type(color_space);
235 for (i = 0; i < arr_size; i++)
236 if (output_csc_matrix[i].color_space_type == type) {
237 val = output_csc_matrix[i].regval;
238 *array_size = 12;
239 break;
240 }
241
242 return val;
243 }
244
245
color_space_to_black_color(const struct dc * dc,enum dc_color_space colorspace,struct tg_color * black_color)246 void color_space_to_black_color(
247 const struct dc *dc,
248 enum dc_color_space colorspace,
249 struct tg_color *black_color)
250 {
251 (void)dc;
252 switch (colorspace) {
253 case COLOR_SPACE_YCBCR601:
254 case COLOR_SPACE_YCBCR709:
255 case COLOR_SPACE_YCBCR709_BLACK:
256 case COLOR_SPACE_YCBCR601_LIMITED:
257 case COLOR_SPACE_YCBCR709_LIMITED:
258 case COLOR_SPACE_2020_YCBCR_LIMITED:
259 case COLOR_SPACE_2020_YCBCR_FULL:
260 *black_color = black_color_format[BLACK_COLOR_FORMAT_YUV_CV];
261 break;
262
263 case COLOR_SPACE_SRGB_LIMITED:
264 *black_color =
265 black_color_format[BLACK_COLOR_FORMAT_RGB_LIMITED];
266 break;
267
268 /*
269 * Remove default and add case for all color space
270 * so when we forget to add new color space
271 * compiler will give a warning
272 */
273 case COLOR_SPACE_UNKNOWN:
274 case COLOR_SPACE_SRGB:
275 case COLOR_SPACE_XR_RGB:
276 case COLOR_SPACE_MSREF_SCRGB:
277 case COLOR_SPACE_XV_YCC_709:
278 case COLOR_SPACE_XV_YCC_601:
279 case COLOR_SPACE_2020_RGB_FULLRANGE:
280 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
281 case COLOR_SPACE_ADOBERGB:
282 case COLOR_SPACE_DCIP3:
283 case COLOR_SPACE_DISPLAYNATIVE:
284 case COLOR_SPACE_DOLBYVISION:
285 case COLOR_SPACE_APPCTRL:
286 case COLOR_SPACE_CUSTOMPOINTS:
287 /* fefault is sRGB black (full range). */
288 *black_color =
289 black_color_format[BLACK_COLOR_FORMAT_RGB_FULLRANGE];
290 /* default is sRGB black 0. */
291 break;
292 }
293 }
294
hwss_wait_for_blank_complete(struct timing_generator * tg)295 bool hwss_wait_for_blank_complete(
296 struct timing_generator *tg)
297 {
298 int counter;
299
300 /* Not applicable if the pipe is not primary, save 300ms of boot time */
301 if (!tg->funcs->is_blanked)
302 return true;
303 for (counter = 0; counter < 100; counter++) {
304 if (tg->funcs->is_blanked(tg))
305 break;
306
307 msleep(1);
308 }
309
310 if (counter == 100) {
311 dm_error("DC: failed to blank crtc!\n");
312 return false;
313 }
314
315 return true;
316 }
317
get_mpctree_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)318 void get_mpctree_visual_confirm_color(
319 struct pipe_ctx *pipe_ctx,
320 struct tg_color *color)
321 {
322 const struct tg_color pipe_colors[6] = {
323 {MAX_TG_COLOR_VALUE, 0, 0}, /* red */
324 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* yellow */
325 {0, MAX_TG_COLOR_VALUE, 0}, /* green */
326 {0, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* cyan */
327 {0, 0, MAX_TG_COLOR_VALUE}, /* blue */
328 {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, /* magenta */
329 };
330
331 struct pipe_ctx *top_pipe = pipe_ctx;
332
333 while (top_pipe->top_pipe)
334 top_pipe = top_pipe->top_pipe;
335
336 *color = pipe_colors[top_pipe->pipe_idx];
337 }
338
get_surface_visual_confirm_color(const struct pipe_ctx * pipe_ctx,struct tg_color * color)339 void get_surface_visual_confirm_color(
340 const struct pipe_ctx *pipe_ctx,
341 struct tg_color *color)
342 {
343 uint32_t color_value = MAX_TG_COLOR_VALUE;
344
345 switch (pipe_ctx->plane_res.scl_data.format) {
346 case PIXEL_FORMAT_ARGB8888:
347 /* set border color to red */
348 color->color_r_cr = color_value;
349 if (pipe_ctx->plane_state->layer_index > 0) {
350 /* set border color to pink */
351 color->color_b_cb = color_value;
352 color->color_g_y = color_value * 0.5;
353 }
354 break;
355
356 case PIXEL_FORMAT_ARGB2101010:
357 /* set border color to blue */
358 color->color_b_cb = color_value;
359 if (pipe_ctx->plane_state->layer_index > 0) {
360 /* set border color to cyan */
361 color->color_g_y = color_value;
362 }
363 break;
364 case PIXEL_FORMAT_420BPP8:
365 /* set border color to green */
366 color->color_g_y = color_value;
367 break;
368 case PIXEL_FORMAT_420BPP10:
369 /* set border color to yellow */
370 color->color_g_y = color_value;
371 color->color_r_cr = color_value;
372 break;
373 case PIXEL_FORMAT_FP16:
374 /* set border color to white */
375 color->color_r_cr = color_value;
376 color->color_b_cb = color_value;
377 color->color_g_y = color_value;
378 if (pipe_ctx->plane_state->layer_index > 0) {
379 /* set border color to orange */
380 color->color_g_y = 0.22 * color_value;
381 color->color_b_cb = 0;
382 }
383 break;
384 default:
385 break;
386 }
387 }
388
get_hdr_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)389 void get_hdr_visual_confirm_color(
390 struct pipe_ctx *pipe_ctx,
391 struct tg_color *color)
392 {
393 uint32_t color_value = MAX_TG_COLOR_VALUE;
394 bool is_sdr = false;
395
396 /* Determine the overscan color based on the top-most (desktop) plane's context */
397 struct pipe_ctx *top_pipe_ctx = pipe_ctx;
398
399 while (top_pipe_ctx->top_pipe != NULL)
400 top_pipe_ctx = top_pipe_ctx->top_pipe;
401
402 switch (top_pipe_ctx->plane_res.scl_data.format) {
403 case PIXEL_FORMAT_ARGB2101010:
404 if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) {
405 /* HDR10, ARGB2101010 - set border color to red */
406 color->color_r_cr = color_value;
407 } else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {
408 /* FreeSync 2 ARGB2101010 - set border color to pink */
409 color->color_r_cr = color_value;
410 color->color_b_cb = color_value;
411 } else
412 is_sdr = true;
413 break;
414 case PIXEL_FORMAT_FP16:
415 if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) {
416 /* HDR10, FP16 - set border color to blue */
417 color->color_b_cb = color_value;
418 } else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {
419 /* FreeSync 2 HDR - set border color to green */
420 color->color_g_y = color_value;
421 } else
422 is_sdr = true;
423 break;
424 default:
425 is_sdr = true;
426 break;
427 }
428
429 if (is_sdr) {
430 /* SDR - set border color to Gray */
431 color->color_r_cr = color_value/2;
432 color->color_b_cb = color_value/2;
433 color->color_g_y = color_value/2;
434 }
435 }
436
437 /* Visual Confirm color definition for Smart Mux */
get_smartmux_visual_confirm_color(struct dc * dc,struct tg_color * color)438 void get_smartmux_visual_confirm_color(
439 struct dc *dc,
440 struct tg_color *color)
441 {
442 uint32_t color_value = MAX_TG_COLOR_VALUE;
443
444 const struct tg_color sm_ver_colors[5] = {
445 {0, 0, 0}, /* SMUX_MUXCONTROL_UNSUPPORTED - Black */
446 {0, MAX_TG_COLOR_VALUE, 0}, /* SMUX_MUXCONTROL_v10 - Green */
447 {0, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* SMUX_MUXCONTROL_v15 - Cyan */
448 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* SMUX_MUXCONTROL_MDM - Yellow */
449 {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, /* SMUX_MUXCONTROL_vUNKNOWN - Magenta*/
450 };
451
452 if (dc->caps.is_apu) {
453 /* APU driving the eDP */
454 *color = sm_ver_colors[dc->config.smart_mux_version];
455 } else {
456 /* dGPU driving the eDP - red */
457 color->color_r_cr = color_value;
458 color->color_g_y = 0;
459 color->color_b_cb = 0;
460 }
461 }
462
463 /* Visual Confirm color definition for VABC */
get_vabc_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)464 void get_vabc_visual_confirm_color(
465 struct pipe_ctx *pipe_ctx,
466 struct tg_color *color)
467 {
468 uint32_t color_value = MAX_TG_COLOR_VALUE;
469 struct dc_link *edp_link = NULL;
470
471 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link) {
472 if (pipe_ctx->stream->link->connector_signal == SIGNAL_TYPE_EDP)
473 edp_link = pipe_ctx->stream->link;
474 }
475
476 if (edp_link) {
477 switch (edp_link->backlight_control_type) {
478 case BACKLIGHT_CONTROL_PWM:
479 color->color_r_cr = color_value;
480 color->color_g_y = 0;
481 color->color_b_cb = 0;
482 break;
483 case BACKLIGHT_CONTROL_AMD_AUX:
484 color->color_r_cr = 0;
485 color->color_g_y = color_value;
486 color->color_b_cb = 0;
487 break;
488 case BACKLIGHT_CONTROL_VESA_AUX:
489 color->color_r_cr = 0;
490 color->color_g_y = 0;
491 color->color_b_cb = color_value;
492 break;
493 }
494 } else {
495 color->color_r_cr = 0;
496 color->color_g_y = 0;
497 color->color_b_cb = 0;
498 }
499 }
500
get_subvp_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)501 void get_subvp_visual_confirm_color(
502 struct pipe_ctx *pipe_ctx,
503 struct tg_color *color)
504 {
505 uint32_t color_value = MAX_TG_COLOR_VALUE;
506 if (pipe_ctx) {
507 switch (pipe_ctx->p_state_type) {
508 case P_STATE_SUB_VP:
509 color->color_r_cr = color_value;
510 color->color_g_y = 0;
511 color->color_b_cb = 0;
512 break;
513 case P_STATE_DRR_SUB_VP:
514 color->color_r_cr = 0;
515 color->color_g_y = color_value;
516 color->color_b_cb = 0;
517 break;
518 case P_STATE_V_BLANK_SUB_VP:
519 color->color_r_cr = 0;
520 color->color_g_y = 0;
521 color->color_b_cb = color_value;
522 break;
523 default:
524 break;
525 }
526 }
527 }
528
get_mclk_switch_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)529 void get_mclk_switch_visual_confirm_color(
530 struct pipe_ctx *pipe_ctx,
531 struct tg_color *color)
532 {
533 uint32_t color_value = MAX_TG_COLOR_VALUE;
534
535 if (pipe_ctx) {
536 switch (pipe_ctx->p_state_type) {
537 case P_STATE_V_BLANK:
538 color->color_r_cr = color_value;
539 color->color_g_y = color_value;
540 color->color_b_cb = 0;
541 break;
542 case P_STATE_FPO:
543 color->color_r_cr = 0;
544 color->color_g_y = color_value;
545 color->color_b_cb = color_value;
546 break;
547 case P_STATE_V_ACTIVE:
548 color->color_r_cr = color_value;
549 color->color_g_y = 0;
550 color->color_b_cb = color_value;
551 break;
552 case P_STATE_SUB_VP:
553 color->color_r_cr = color_value;
554 color->color_g_y = 0;
555 color->color_b_cb = 0;
556 break;
557 case P_STATE_DRR_SUB_VP:
558 color->color_r_cr = 0;
559 color->color_g_y = color_value;
560 color->color_b_cb = 0;
561 break;
562 case P_STATE_V_BLANK_SUB_VP:
563 color->color_r_cr = 0;
564 color->color_g_y = 0;
565 color->color_b_cb = color_value;
566 break;
567 default:
568 break;
569 }
570 }
571 }
572
get_cursor_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)573 void get_cursor_visual_confirm_color(
574 struct pipe_ctx *pipe_ctx,
575 struct tg_color *color)
576 {
577 uint32_t color_value = MAX_TG_COLOR_VALUE;
578
579 if (pipe_ctx->stream && pipe_ctx->stream->cursor_position.enable) {
580 color->color_r_cr = color_value;
581 color->color_g_y = 0;
582 color->color_b_cb = 0;
583 } else {
584 color->color_r_cr = 0;
585 color->color_g_y = 0;
586 color->color_b_cb = color_value;
587 }
588 }
589
get_dcc_visual_confirm_color(struct dc * dc,struct pipe_ctx * pipe_ctx,struct tg_color * color)590 void get_dcc_visual_confirm_color(
591 struct dc *dc,
592 struct pipe_ctx *pipe_ctx,
593 struct tg_color *color)
594 {
595 const uint32_t MCACHE_ID_UNASSIGNED = 0xF;
596
597 if (!pipe_ctx->plane_state->dcc.enable) {
598 color->color_r_cr = 0; /* black - DCC disabled */
599 color->color_g_y = 0;
600 color->color_b_cb = 0;
601 return;
602 }
603
604 if (dc->ctx->dce_version < DCN_VERSION_4_01) {
605 color->color_r_cr = MAX_TG_COLOR_VALUE; /* red - DCC enabled */
606 color->color_g_y = 0;
607 color->color_b_cb = 0;
608 return;
609 }
610
611 uint32_t first_id = pipe_ctx->mcache_regs.main.p0.mcache_id_first;
612 uint32_t second_id = pipe_ctx->mcache_regs.main.p0.mcache_id_second;
613
614 if (first_id != MCACHE_ID_UNASSIGNED && second_id != MCACHE_ID_UNASSIGNED && first_id != second_id) {
615 color->color_r_cr = MAX_TG_COLOR_VALUE/2; /* grey - 2 mcache */
616 color->color_g_y = MAX_TG_COLOR_VALUE/2;
617 color->color_b_cb = MAX_TG_COLOR_VALUE/2;
618 }
619
620 else if (first_id != MCACHE_ID_UNASSIGNED || second_id != MCACHE_ID_UNASSIGNED) {
621 const struct tg_color id_colors[MAX_NUM_MCACHE] = {
622 {0, MAX_TG_COLOR_VALUE, 0}, /* green */
623 {0, 0, MAX_TG_COLOR_VALUE}, /* blue */
624 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* yellow */
625 {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, /* magenta */
626 {0, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* cyan */
627 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* white */
628 {MAX_TG_COLOR_VALUE/2, 0, 0}, /* dark red */
629 {0, MAX_TG_COLOR_VALUE/2, 0}, /* dark green */
630 };
631
632 uint32_t assigned_id = (first_id != MCACHE_ID_UNASSIGNED) ? first_id : second_id;
633 *color = id_colors[assigned_id];
634 }
635 }
636
set_p_state_switch_method(struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx)637 void set_p_state_switch_method(
638 struct dc *dc,
639 struct dc_state *context,
640 struct pipe_ctx *pipe_ctx)
641 {
642 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
643 bool enable_subvp;
644
645 if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba)
646 return;
647
648 pipe_ctx->p_state_type = P_STATE_UNKNOWN;
649 if (vba->DRAMClockChangeSupport[vba->VoltageLevel][vba->maxMpcComb] !=
650 dm_dram_clock_change_unsupported) {
651 /* MCLK switching is supported */
652 if (!pipe_ctx->has_vactive_margin) {
653 /* In Vblank - yellow */
654 pipe_ctx->p_state_type = P_STATE_V_BLANK;
655
656 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
657 /* FPO + Vblank - cyan */
658 pipe_ctx->p_state_type = P_STATE_FPO;
659 }
660 } else {
661 /* In Vactive - pink */
662 pipe_ctx->p_state_type = P_STATE_V_ACTIVE;
663 }
664
665 /* SubVP */
666 enable_subvp = false;
667
668 for (int i = 0; i < dc->res_pool->pipe_count; i++) {
669 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
670
671 if (pipe->stream && dc_state_get_paired_subvp_stream(context, pipe->stream) &&
672 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {
673 /* SubVP enable - red */
674 pipe_ctx->p_state_type = P_STATE_SUB_VP;
675 enable_subvp = true;
676
677 if (pipe_ctx->stream == pipe->stream)
678 return;
679 break;
680 }
681 }
682
683 if (enable_subvp && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_NONE) {
684 if (pipe_ctx->stream->allow_freesync == 1) {
685 /* SubVP enable and DRR on - green */
686 pipe_ctx->p_state_type = P_STATE_DRR_SUB_VP;
687 } else {
688 /* SubVP enable and No DRR - blue */
689 pipe_ctx->p_state_type = P_STATE_V_BLANK_SUB_VP;
690 }
691 }
692 }
693 }
694
set_drr_and_clear_adjust_pending(struct pipe_ctx * pipe_ctx,struct dc_stream_state * stream,struct drr_params * params)695 void set_drr_and_clear_adjust_pending(
696 struct pipe_ctx *pipe_ctx,
697 struct dc_stream_state *stream,
698 struct drr_params *params)
699 {
700 /* params can be null.*/
701 if (pipe_ctx && pipe_ctx->stream_res.tg &&
702 pipe_ctx->stream_res.tg->funcs->set_drr)
703 pipe_ctx->stream_res.tg->funcs->set_drr(
704 pipe_ctx->stream_res.tg, params);
705
706 if (stream)
707 stream->adjust.timing_adjust_pending = false;
708 }
709
get_fams2_visual_confirm_color(struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx,struct tg_color * color)710 void get_fams2_visual_confirm_color(
711 struct dc *dc,
712 struct dc_state *context,
713 struct pipe_ctx *pipe_ctx,
714 struct tg_color *color)
715 {
716 uint32_t color_value = MAX_TG_COLOR_VALUE;
717
718 if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !context || !dc->debug.fams2_config.bits.enable)
719 return;
720
721 /* driver only handles visual confirm when FAMS2 is disabled */
722 if (!dc_state_is_fams2_in_use(dc, context)) {
723 /* when FAMS2 is disabled, all pipes are grey */
724 color->color_g_y = color_value / 2;
725 color->color_b_cb = color_value / 2;
726 color->color_r_cr = color_value / 2;
727 }
728 }
729
hwss_build_fast_sequence(struct dc * dc,struct dc_dmub_cmd * dc_dmub_cmd,unsigned int dmub_cmd_count,struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],unsigned int * num_steps,struct pipe_ctx * pipe_ctx,struct dc_stream_status * stream_status,struct dc_state * context)730 void hwss_build_fast_sequence(struct dc *dc,
731 struct dc_dmub_cmd *dc_dmub_cmd,
732 unsigned int dmub_cmd_count,
733 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],
734 unsigned int *num_steps,
735 struct pipe_ctx *pipe_ctx,
736 struct dc_stream_status *stream_status,
737 struct dc_state *context)
738 {
739 struct dc_plane_state *plane = pipe_ctx->plane_state;
740 struct dc_stream_state *stream = pipe_ctx->stream;
741 struct dce_hwseq *hws = dc->hwseq;
742 struct pipe_ctx *current_pipe = NULL;
743 struct pipe_ctx *current_mpc_pipe = NULL;
744 bool is_dmub_lock_required = false;
745 unsigned int i = 0;
746
747 *num_steps = 0; // Initialize to 0
748
749 if (!plane || !stream)
750 return;
751
752 if (dc->hwss.wait_for_dcc_meta_propagation) {
753 block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc;
754 block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = pipe_ctx;
755 block_sequence[*num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP;
756 (*num_steps)++;
757 }
758 if (dc->hwss.subvp_pipe_control_lock_fast) {
759 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;
760 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = true;
761 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip =
762 plane->flip_immediate && stream_status->mall_stream_config.type == SUBVP_MAIN;
763 block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;
764 (*num_steps)++;
765 }
766 if (dc->hwss.dmub_hw_control_lock_fast) {
767 is_dmub_lock_required = dc_state_is_fams2_in_use(dc, context) ||
768 dmub_hw_lock_mgr_does_link_require_lock(dc, stream->link);
769
770 block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc;
771 block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.lock = true;
772 block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = is_dmub_lock_required;
773 block_sequence[*num_steps].func = DMUB_HW_CONTROL_LOCK_FAST;
774 (*num_steps)++;
775 }
776 if (dc->hwss.pipe_control_lock) {
777 block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;
778 block_sequence[*num_steps].params.pipe_control_lock_params.lock = true;
779 block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;
780 block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK;
781 (*num_steps)++;
782 }
783
784 for (i = 0; i < dmub_cmd_count; i++) {
785 block_sequence[*num_steps].params.send_dmcub_cmd_params.ctx = dc->ctx;
786 block_sequence[*num_steps].params.send_dmcub_cmd_params.cmd = &(dc_dmub_cmd[i].dmub_cmd);
787 block_sequence[*num_steps].params.send_dmcub_cmd_params.wait_type = dc_dmub_cmd[i].wait_type;
788 block_sequence[*num_steps].func = DMUB_SEND_DMCUB_CMD;
789 (*num_steps)++;
790 }
791
792 current_pipe = pipe_ctx;
793 while (current_pipe) {
794 current_mpc_pipe = current_pipe;
795 while (current_mpc_pipe) {
796 if (current_mpc_pipe->plane_state) {
797 if (dc->hwss.set_flip_control_gsl && current_mpc_pipe->plane_state->update_flags.raw) {
798 block_sequence[*num_steps].params.set_flip_control_gsl_params.hubp = current_mpc_pipe->plane_res.hubp;
799 block_sequence[*num_steps].params.set_flip_control_gsl_params.flip_immediate = current_mpc_pipe->plane_state->flip_immediate;
800 block_sequence[*num_steps].func = HUBP_SET_FLIP_CONTROL_GSL;
801 (*num_steps)++;
802 }
803 if (dc->hwss.program_triplebuffer && dc->debug.enable_tri_buf && current_mpc_pipe->plane_state->update_flags.raw) {
804 block_sequence[*num_steps].params.program_triplebuffer_params.dc = dc;
805 block_sequence[*num_steps].params.program_triplebuffer_params.pipe_ctx = current_mpc_pipe;
806 block_sequence[*num_steps].params.program_triplebuffer_params.enableTripleBuffer = current_mpc_pipe->plane_state->triplebuffer_flips;
807 block_sequence[*num_steps].func = HUBP_PROGRAM_TRIPLEBUFFER;
808 (*num_steps)++;
809 }
810 if (dc->hwss.update_plane_addr && current_mpc_pipe->plane_state->update_flags.bits.addr_update) {
811 if (resource_is_pipe_type(current_mpc_pipe, OTG_MASTER) &&
812 stream_status->mall_stream_config.type == SUBVP_MAIN) {
813 block_sequence[*num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;
814 block_sequence[*num_steps].params.subvp_save_surf_addr.addr = ¤t_mpc_pipe->plane_state->address;
815 block_sequence[*num_steps].params.subvp_save_surf_addr.subvp_index = current_mpc_pipe->subvp_index;
816 block_sequence[*num_steps].func = DMUB_SUBVP_SAVE_SURF_ADDR;
817 (*num_steps)++;
818 }
819
820 block_sequence[*num_steps].params.update_plane_addr_params.dc = dc;
821 block_sequence[*num_steps].params.update_plane_addr_params.pipe_ctx = current_mpc_pipe;
822 block_sequence[*num_steps].func = HUBP_UPDATE_PLANE_ADDR;
823 (*num_steps)++;
824 }
825
826 if (hws->funcs.set_input_transfer_func && current_mpc_pipe->plane_state->update_flags.bits.gamma_change) {
827 block_sequence[*num_steps].params.set_input_transfer_func_params.dc = dc;
828 block_sequence[*num_steps].params.set_input_transfer_func_params.pipe_ctx = current_mpc_pipe;
829 block_sequence[*num_steps].params.set_input_transfer_func_params.plane_state = current_mpc_pipe->plane_state;
830 block_sequence[*num_steps].func = DPP_SET_INPUT_TRANSFER_FUNC;
831 (*num_steps)++;
832 }
833
834 if (dc->hwss.program_gamut_remap && current_mpc_pipe->plane_state->update_flags.bits.gamut_remap_change) {
835 block_sequence[*num_steps].params.program_gamut_remap_params.pipe_ctx = current_mpc_pipe;
836 block_sequence[*num_steps].func = DPP_PROGRAM_GAMUT_REMAP;
837 (*num_steps)++;
838 }
839 if (current_mpc_pipe->plane_state->update_flags.bits.input_csc_change) {
840 block_sequence[*num_steps].params.setup_dpp_params.pipe_ctx = current_mpc_pipe;
841 block_sequence[*num_steps].func = DPP_SETUP_DPP;
842 (*num_steps)++;
843 }
844 if (current_mpc_pipe->plane_state->update_flags.bits.coeff_reduction_change) {
845 block_sequence[*num_steps].params.program_bias_and_scale_params.pipe_ctx = current_mpc_pipe;
846 block_sequence[*num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE;
847 (*num_steps)++;
848 }
849 if (current_mpc_pipe->plane_state->update_flags.bits.cm_hist_change) {
850 block_sequence[*num_steps].params.control_cm_hist_params.dpp
851 = current_mpc_pipe->plane_res.dpp;
852 block_sequence[*num_steps].params.control_cm_hist_params.cm_hist_control
853 = current_mpc_pipe->plane_state->cm_hist_control;
854 block_sequence[*num_steps].params.control_cm_hist_params.color_space
855 = current_mpc_pipe->plane_state->color_space;
856 block_sequence[*num_steps].func = DPP_PROGRAM_CM_HIST;
857 (*num_steps)++;
858 }
859 }
860 if (hws->funcs.set_output_transfer_func && current_mpc_pipe->stream->update_flags.bits.out_tf) {
861 block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc;
862 block_sequence[*num_steps].params.set_output_transfer_func_params.pipe_ctx = current_mpc_pipe;
863 block_sequence[*num_steps].params.set_output_transfer_func_params.stream = current_mpc_pipe->stream;
864 block_sequence[*num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC;
865 (*num_steps)++;
866 }
867 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE &&
868 dc->hwss.update_visual_confirm_color) {
869 block_sequence[*num_steps].params.update_visual_confirm_params.dc = dc;
870 block_sequence[*num_steps].params.update_visual_confirm_params.pipe_ctx = current_mpc_pipe;
871 block_sequence[*num_steps].params.update_visual_confirm_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;
872 block_sequence[*num_steps].func = MPC_UPDATE_VISUAL_CONFIRM;
873 (*num_steps)++;
874 }
875 if (current_mpc_pipe->stream->update_flags.bits.out_csc) {
876 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc = dc->res_pool->mpc;
877 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;
878 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.power_on = true;
879 block_sequence[*num_steps].func = MPC_POWER_ON_MPC_MEM_PWR;
880 (*num_steps)++;
881
882 if (current_mpc_pipe->stream->csc_color_matrix.enable_adjustment == true) {
883 block_sequence[*num_steps].params.set_output_csc_params.mpc = dc->res_pool->mpc;
884 block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
885 block_sequence[*num_steps].params.set_output_csc_params.regval = current_mpc_pipe->stream->csc_color_matrix.matrix;
886 block_sequence[*num_steps].params.set_output_csc_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
887 block_sequence[*num_steps].func = MPC_SET_OUTPUT_CSC;
888 (*num_steps)++;
889 } else {
890 block_sequence[*num_steps].params.set_ocsc_default_params.mpc = dc->res_pool->mpc;
891 block_sequence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
892 block_sequence[*num_steps].params.set_ocsc_default_params.color_space = current_mpc_pipe->stream->output_color_space;
893 block_sequence[*num_steps].params.set_ocsc_default_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
894 block_sequence[*num_steps].func = MPC_SET_OCSC_DEFAULT;
895 (*num_steps)++;
896 }
897 }
898 current_mpc_pipe = current_mpc_pipe->bottom_pipe;
899 }
900 current_pipe = current_pipe->next_odm_pipe;
901 }
902
903 if (dc->hwss.pipe_control_lock) {
904 block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;
905 block_sequence[*num_steps].params.pipe_control_lock_params.lock = false;
906 block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;
907 block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK;
908 (*num_steps)++;
909 }
910 if (dc->hwss.subvp_pipe_control_lock_fast) {
911 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;
912 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = false;
913 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip =
914 plane->flip_immediate && stream_status->mall_stream_config.type == SUBVP_MAIN;
915 block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;
916 (*num_steps)++;
917 }
918 if (dc->hwss.dmub_hw_control_lock_fast) {
919 block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc;
920 block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.lock = false;
921 block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = is_dmub_lock_required;
922 block_sequence[*num_steps].func = DMUB_HW_CONTROL_LOCK_FAST;
923 (*num_steps)++;
924 }
925
926 current_pipe = pipe_ctx;
927 while (current_pipe) {
928 current_mpc_pipe = current_pipe;
929
930 while (current_mpc_pipe) {
931 if (!current_mpc_pipe->bottom_pipe && !current_mpc_pipe->next_odm_pipe &&
932 current_mpc_pipe->stream && current_mpc_pipe->plane_state &&
933 current_mpc_pipe->plane_state->update_flags.bits.addr_update &&
934 !current_mpc_pipe->plane_state->skip_manual_trigger) {
935 if (dc->hwss.program_cursor_offload_now) {
936 block_sequence[*num_steps].params.program_cursor_update_now_params.dc = dc;
937 block_sequence[*num_steps].params.program_cursor_update_now_params.pipe_ctx = current_mpc_pipe;
938 block_sequence[*num_steps].func = PROGRAM_CURSOR_UPDATE_NOW;
939 (*num_steps)++;
940 }
941
942 block_sequence[*num_steps].params.program_manual_trigger_params.pipe_ctx = current_mpc_pipe;
943 block_sequence[*num_steps].func = OPTC_PROGRAM_MANUAL_TRIGGER;
944 (*num_steps)++;
945 }
946 current_mpc_pipe = current_mpc_pipe->bottom_pipe;
947 }
948 current_pipe = current_pipe->next_odm_pipe;
949 }
950 }
951
hwss_execute_sequence(struct dc * dc,struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],int num_steps)952 void hwss_execute_sequence(struct dc *dc,
953 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],
954 int num_steps)
955 {
956 unsigned int i;
957 union block_sequence_params *params;
958 struct dce_hwseq *hws = dc->hwseq;
959
960 for (i = 0; i < num_steps; i++) {
961 params = &(block_sequence[i].params);
962 switch (block_sequence[i].func) {
963
964 case DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST:
965 dc->hwss.subvp_pipe_control_lock_fast(params);
966 break;
967 case OPTC_PIPE_CONTROL_LOCK:
968 dc->hwss.pipe_control_lock(params->pipe_control_lock_params.dc,
969 params->pipe_control_lock_params.pipe_ctx,
970 params->pipe_control_lock_params.lock);
971 break;
972 case HUBP_SET_FLIP_CONTROL_GSL:
973 params->set_flip_control_gsl_params.hubp->funcs->hubp_set_flip_control_surface_gsl(
974 params->set_flip_control_gsl_params.hubp,
975 params->set_flip_control_gsl_params.flip_immediate);
976 break;
977 case HUBP_PROGRAM_TRIPLEBUFFER:
978 dc->hwss.program_triplebuffer(params->program_triplebuffer_params.dc,
979 params->program_triplebuffer_params.pipe_ctx,
980 params->program_triplebuffer_params.enableTripleBuffer);
981 break;
982 case HUBP_UPDATE_PLANE_ADDR:
983 dc->hwss.update_plane_addr(params->update_plane_addr_params.dc,
984 params->update_plane_addr_params.pipe_ctx);
985 break;
986 case DPP_SET_INPUT_TRANSFER_FUNC:
987 hws->funcs.set_input_transfer_func(params->set_input_transfer_func_params.dc,
988 params->set_input_transfer_func_params.pipe_ctx,
989 params->set_input_transfer_func_params.plane_state);
990 break;
991 case DPP_PROGRAM_GAMUT_REMAP:
992 dc->hwss.program_gamut_remap(params->program_gamut_remap_params.pipe_ctx);
993 break;
994 case DPP_SETUP_DPP:
995 hwss_setup_dpp(params);
996 break;
997 case DPP_PROGRAM_BIAS_AND_SCALE:
998 hwss_program_bias_and_scale(params);
999 break;
1000 case OPTC_PROGRAM_MANUAL_TRIGGER:
1001 hwss_program_manual_trigger(params);
1002 break;
1003 case DPP_SET_OUTPUT_TRANSFER_FUNC:
1004 hws->funcs.set_output_transfer_func(params->set_output_transfer_func_params.dc,
1005 params->set_output_transfer_func_params.pipe_ctx,
1006 params->set_output_transfer_func_params.stream);
1007 break;
1008 case MPC_UPDATE_VISUAL_CONFIRM:
1009 dc->hwss.update_visual_confirm_color(params->update_visual_confirm_params.dc,
1010 params->update_visual_confirm_params.pipe_ctx,
1011 params->update_visual_confirm_params.mpcc_id);
1012 break;
1013 case MPC_POWER_ON_MPC_MEM_PWR:
1014 hwss_power_on_mpc_mem_pwr(params);
1015 break;
1016 case MPC_SET_OUTPUT_CSC:
1017 hwss_set_output_csc(params);
1018 break;
1019 case MPC_SET_OCSC_DEFAULT:
1020 hwss_set_ocsc_default(params);
1021 break;
1022 case DMUB_SEND_DMCUB_CMD:
1023 hwss_send_dmcub_cmd(params);
1024 break;
1025 case DMUB_SUBVP_SAVE_SURF_ADDR:
1026 hwss_subvp_save_surf_addr(params);
1027 break;
1028 case HUBP_WAIT_FOR_DCC_META_PROP:
1029 dc->hwss.wait_for_dcc_meta_propagation(
1030 params->wait_for_dcc_meta_propagation_params.dc,
1031 params->wait_for_dcc_meta_propagation_params.top_pipe_to_program);
1032 break;
1033 case DMUB_HW_CONTROL_LOCK_FAST:
1034 dc->hwss.dmub_hw_control_lock_fast(params);
1035 break;
1036 case HUBP_PROGRAM_SURFACE_CONFIG:
1037 hwss_program_surface_config(params);
1038 break;
1039 case HUBP_PROGRAM_MCACHE_ID:
1040 hwss_program_mcache_id_and_split_coordinate(params);
1041 break;
1042 case DPP_PROGRAM_CM_HIST:
1043 hwss_program_cm_hist(params);
1044 break;
1045 case PROGRAM_CURSOR_UPDATE_NOW:
1046 dc->hwss.program_cursor_offload_now(
1047 params->program_cursor_update_now_params.dc,
1048 params->program_cursor_update_now_params.pipe_ctx);
1049 break;
1050 case HUBP_WAIT_PIPE_READ_START:
1051 params->hubp_wait_pipe_read_start_params.hubp->funcs->hubp_wait_pipe_read_start(
1052 params->hubp_wait_pipe_read_start_params.hubp);
1053 break;
1054 case HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM:
1055 dc->hwss.apply_update_flags_for_phantom(params->apply_update_flags_for_phantom_params.pipe_ctx);
1056 break;
1057 case HWS_UPDATE_PHANTOM_VP_POSITION:
1058 dc->hwss.update_phantom_vp_position(params->update_phantom_vp_position_params.dc,
1059 params->update_phantom_vp_position_params.context,
1060 params->update_phantom_vp_position_params.pipe_ctx);
1061 break;
1062 case OPTC_SET_ODM_COMBINE:
1063 hwss_set_odm_combine(params);
1064 break;
1065 case OPTC_SET_ODM_BYPASS:
1066 hwss_set_odm_bypass(params);
1067 break;
1068 case OPP_PIPE_CLOCK_CONTROL:
1069 hwss_opp_pipe_clock_control(params);
1070 break;
1071 case OPP_PROGRAM_LEFT_EDGE_EXTRA_PIXEL:
1072 hwss_opp_program_left_edge_extra_pixel(params);
1073 break;
1074 case DCCG_SET_DTO_DSCCLK:
1075 hwss_dccg_set_dto_dscclk(params);
1076 break;
1077 case DSC_SET_CONFIG:
1078 hwss_dsc_set_config(params);
1079 break;
1080 case DSC_ENABLE:
1081 hwss_dsc_enable(params);
1082 break;
1083 case TG_SET_DSC_CONFIG:
1084 hwss_tg_set_dsc_config(params);
1085 break;
1086 case DSC_DISCONNECT:
1087 hwss_dsc_disconnect(params);
1088 break;
1089 case DSC_READ_STATE:
1090 hwss_dsc_read_state(params);
1091 break;
1092 case DSC_CALCULATE_AND_SET_CONFIG:
1093 hwss_dsc_calculate_and_set_config(params);
1094 break;
1095 case DSC_ENABLE_WITH_OPP:
1096 hwss_dsc_enable_with_opp(params);
1097 break;
1098 case TG_PROGRAM_GLOBAL_SYNC:
1099 hwss_tg_program_global_sync(params);
1100 break;
1101 case TG_WAIT_FOR_STATE:
1102 hwss_tg_wait_for_state(params);
1103 break;
1104 case TG_SET_VTG_PARAMS:
1105 hwss_tg_set_vtg_params(params);
1106 break;
1107 case TG_SETUP_VERTICAL_INTERRUPT2:
1108 hwss_tg_setup_vertical_interrupt2(params);
1109 break;
1110 case DPP_SET_HDR_MULTIPLIER:
1111 hwss_dpp_set_hdr_multiplier(params);
1112 break;
1113 case HUBP_PROGRAM_DET_SIZE:
1114 hwss_program_det_size(params);
1115 break;
1116 case HUBP_PROGRAM_DET_SEGMENTS:
1117 hwss_program_det_segments(params);
1118 break;
1119 case OPP_SET_DYN_EXPANSION:
1120 hwss_opp_set_dyn_expansion(params);
1121 break;
1122 case OPP_PROGRAM_FMT:
1123 hwss_opp_program_fmt(params);
1124 break;
1125 case OPP_PROGRAM_BIT_DEPTH_REDUCTION:
1126 hwss_opp_program_bit_depth_reduction(params);
1127 break;
1128 case OPP_SET_DISP_PATTERN_GENERATOR:
1129 hwss_opp_set_disp_pattern_generator(params);
1130 break;
1131 case ABM_SET_PIPE:
1132 hwss_set_abm_pipe(params);
1133 break;
1134 case ABM_SET_LEVEL:
1135 hwss_set_abm_level(params);
1136 break;
1137 case ABM_SET_IMMEDIATE_DISABLE:
1138 hwss_set_abm_immediate_disable(params);
1139 break;
1140 case MPC_REMOVE_MPCC:
1141 hwss_mpc_remove_mpcc(params);
1142 break;
1143 case OPP_SET_MPCC_DISCONNECT_PENDING:
1144 hwss_opp_set_mpcc_disconnect_pending(params);
1145 break;
1146 case DC_SET_OPTIMIZED_REQUIRED:
1147 hwss_dc_set_optimized_required(params);
1148 break;
1149 case HUBP_DISCONNECT:
1150 hwss_hubp_disconnect(params);
1151 break;
1152 case HUBBUB_FORCE_PSTATE_CHANGE_CONTROL:
1153 hwss_hubbub_force_pstate_change_control(params);
1154 break;
1155 case TG_ENABLE_CRTC:
1156 hwss_tg_enable_crtc(params);
1157 break;
1158 case TG_SET_GSL:
1159 hwss_tg_set_gsl(params);
1160 break;
1161 case TG_SET_GSL_SOURCE_SELECT:
1162 hwss_tg_set_gsl_source_select(params);
1163 break;
1164 case HUBP_WAIT_FLIP_PENDING:
1165 hwss_hubp_wait_flip_pending(params);
1166 break;
1167 case TG_WAIT_DOUBLE_BUFFER_PENDING:
1168 hwss_tg_wait_double_buffer_pending(params);
1169 break;
1170 case UPDATE_FORCE_PSTATE:
1171 hwss_update_force_pstate(params);
1172 break;
1173 case HUBBUB_APPLY_DEDCN21_147_WA:
1174 hwss_hubbub_apply_dedcn21_147_wa(params);
1175 break;
1176 case HUBBUB_ALLOW_SELF_REFRESH_CONTROL:
1177 hwss_hubbub_allow_self_refresh_control(params);
1178 break;
1179 case TG_GET_FRAME_COUNT:
1180 hwss_tg_get_frame_count(params);
1181 break;
1182 case MPC_SET_DWB_MUX:
1183 hwss_mpc_set_dwb_mux(params);
1184 break;
1185 case MPC_DISABLE_DWB_MUX:
1186 hwss_mpc_disable_dwb_mux(params);
1187 break;
1188 case MCIF_WB_CONFIG_BUF:
1189 hwss_mcif_wb_config_buf(params);
1190 break;
1191 case MCIF_WB_CONFIG_ARB:
1192 hwss_mcif_wb_config_arb(params);
1193 break;
1194 case MCIF_WB_ENABLE:
1195 hwss_mcif_wb_enable(params);
1196 break;
1197 case MCIF_WB_DISABLE:
1198 hwss_mcif_wb_disable(params);
1199 break;
1200 case DWBC_ENABLE:
1201 hwss_dwbc_enable(params);
1202 break;
1203 case DWBC_DISABLE:
1204 hwss_dwbc_disable(params);
1205 break;
1206 case DWBC_UPDATE:
1207 hwss_dwbc_update(params);
1208 break;
1209 case HUBP_UPDATE_MALL_SEL:
1210 hwss_hubp_update_mall_sel(params);
1211 break;
1212 case HUBP_PREPARE_SUBVP_BUFFERING:
1213 hwss_hubp_prepare_subvp_buffering(params);
1214 break;
1215 case HUBP_SET_BLANK_EN:
1216 hwss_hubp_set_blank_en(params);
1217 break;
1218 case HUBP_DISABLE_CONTROL:
1219 hwss_hubp_disable_control(params);
1220 break;
1221 case HUBBUB_SOFT_RESET:
1222 hwss_hubbub_soft_reset(params);
1223 break;
1224 case HUBP_CLK_CNTL:
1225 hwss_hubp_clk_cntl(params);
1226 break;
1227 case HUBP_INIT:
1228 hwss_hubp_init(params);
1229 break;
1230 case HUBP_SET_VM_SYSTEM_APERTURE_SETTINGS:
1231 hwss_hubp_set_vm_system_aperture_settings(params);
1232 break;
1233 case HUBP_SET_FLIP_INT:
1234 hwss_hubp_set_flip_int(params);
1235 break;
1236 case DPP_DPPCLK_CONTROL:
1237 hwss_dpp_dppclk_control(params);
1238 break;
1239 case DISABLE_PHANTOM_CRTC:
1240 hwss_disable_phantom_crtc(params);
1241 break;
1242 case DSC_PG_STATUS:
1243 hwss_dsc_pg_status(params);
1244 break;
1245 case DSC_WAIT_DISCONNECT_PENDING_CLEAR:
1246 hwss_dsc_wait_disconnect_pending_clear(params);
1247 break;
1248 case DSC_DISABLE:
1249 hwss_dsc_disable(params);
1250 break;
1251 case DCCG_SET_REF_DSCCLK:
1252 hwss_dccg_set_ref_dscclk(params);
1253 break;
1254 case DPP_PG_CONTROL:
1255 hwss_dpp_pg_control(params);
1256 break;
1257 case HUBP_PG_CONTROL:
1258 hwss_hubp_pg_control(params);
1259 break;
1260 case HUBP_RESET:
1261 hwss_hubp_reset(params);
1262 break;
1263 case DPP_RESET:
1264 hwss_dpp_reset(params);
1265 break;
1266 case DPP_ROOT_CLOCK_CONTROL:
1267 hwss_dpp_root_clock_control(params);
1268 break;
1269 case DC_IP_REQUEST_CNTL:
1270 hwss_dc_ip_request_cntl(params);
1271 break;
1272 case DCCG_UPDATE_DPP_DTO:
1273 hwss_dccg_update_dpp_dto(params);
1274 break;
1275 case HUBP_VTG_SEL:
1276 hwss_hubp_vtg_sel(params);
1277 break;
1278 case HUBP_SETUP2:
1279 hwss_hubp_setup2(params);
1280 break;
1281 case HUBP_SETUP:
1282 hwss_hubp_setup(params);
1283 break;
1284 case HUBP_SET_UNBOUNDED_REQUESTING:
1285 hwss_hubp_set_unbounded_requesting(params);
1286 break;
1287 case HUBP_SETUP_INTERDEPENDENT2:
1288 hwss_hubp_setup_interdependent2(params);
1289 break;
1290 case HUBP_SETUP_INTERDEPENDENT:
1291 hwss_hubp_setup_interdependent(params);
1292 break;
1293 case DPP_SET_CURSOR_MATRIX:
1294 hwss_dpp_set_cursor_matrix(params);
1295 break;
1296 case MPC_UPDATE_BLENDING:
1297 hwss_mpc_update_blending(params);
1298 break;
1299 case MPC_ASSERT_IDLE_MPCC:
1300 hwss_mpc_assert_idle_mpcc(params);
1301 break;
1302 case MPC_INSERT_PLANE:
1303 hwss_mpc_insert_plane(params);
1304 break;
1305 case DPP_SET_SCALER:
1306 hwss_dpp_set_scaler(params);
1307 break;
1308 case HUBP_MEM_PROGRAM_VIEWPORT:
1309 hwss_hubp_mem_program_viewport(params);
1310 break;
1311 case ABORT_CURSOR_OFFLOAD_UPDATE:
1312 hwss_abort_cursor_offload_update(params);
1313 break;
1314 case SET_CURSOR_ATTRIBUTE:
1315 hwss_set_cursor_attribute(params);
1316 break;
1317 case SET_CURSOR_POSITION:
1318 hwss_set_cursor_position(params);
1319 break;
1320 case SET_CURSOR_SDR_WHITE_LEVEL:
1321 hwss_set_cursor_sdr_white_level(params);
1322 break;
1323 case PROGRAM_OUTPUT_CSC:
1324 hwss_program_output_csc(params);
1325 break;
1326 case HUBP_SET_BLANK:
1327 hwss_hubp_set_blank(params);
1328 break;
1329 case PHANTOM_HUBP_POST_ENABLE:
1330 hwss_phantom_hubp_post_enable(params);
1331 break;
1332 default:
1333 ASSERT(false);
1334 break;
1335 }
1336 }
1337 }
1338
1339 /*
1340 * Helper function to add OPTC pipe control lock to block sequence
1341 */
hwss_add_optc_pipe_control_lock(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx,bool lock)1342 void hwss_add_optc_pipe_control_lock(struct block_sequence_state *seq_state,
1343 struct dc *dc,
1344 struct pipe_ctx *pipe_ctx,
1345 bool lock)
1346 {
1347 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1348 seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.dc = dc;
1349 seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;
1350 seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.lock = lock;
1351 seq_state->steps[*seq_state->num_steps].func = OPTC_PIPE_CONTROL_LOCK;
1352 (*seq_state->num_steps)++;
1353 }
1354 }
1355
1356 /*
1357 * Helper function to add HUBP set flip control GSL to block sequence
1358 */
hwss_add_hubp_set_flip_control_gsl(struct block_sequence_state * seq_state,struct hubp * hubp,bool flip_immediate)1359 void hwss_add_hubp_set_flip_control_gsl(struct block_sequence_state *seq_state,
1360 struct hubp *hubp,
1361 bool flip_immediate)
1362 {
1363 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1364 seq_state->steps[*seq_state->num_steps].params.set_flip_control_gsl_params.hubp = hubp;
1365 seq_state->steps[*seq_state->num_steps].params.set_flip_control_gsl_params.flip_immediate = flip_immediate;
1366 seq_state->steps[*seq_state->num_steps].func = HUBP_SET_FLIP_CONTROL_GSL;
1367 (*seq_state->num_steps)++;
1368 }
1369 }
1370
1371 /*
1372 * Helper function to add HUBP program triplebuffer to block sequence
1373 */
hwss_add_hubp_program_triplebuffer(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx,bool enableTripleBuffer)1374 void hwss_add_hubp_program_triplebuffer(struct block_sequence_state *seq_state,
1375 struct dc *dc,
1376 struct pipe_ctx *pipe_ctx,
1377 bool enableTripleBuffer)
1378 {
1379 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1380 seq_state->steps[*seq_state->num_steps].params.program_triplebuffer_params.dc = dc;
1381 seq_state->steps[*seq_state->num_steps].params.program_triplebuffer_params.pipe_ctx = pipe_ctx;
1382 seq_state->steps[*seq_state->num_steps].params.program_triplebuffer_params.enableTripleBuffer = enableTripleBuffer;
1383 seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_TRIPLEBUFFER;
1384 (*seq_state->num_steps)++;
1385 }
1386 }
1387
1388 /*
1389 * Helper function to add HUBP update plane address to block sequence
1390 */
hwss_add_hubp_update_plane_addr(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx)1391 void hwss_add_hubp_update_plane_addr(struct block_sequence_state *seq_state,
1392 struct dc *dc,
1393 struct pipe_ctx *pipe_ctx)
1394 {
1395 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1396 seq_state->steps[*seq_state->num_steps].params.update_plane_addr_params.dc = dc;
1397 seq_state->steps[*seq_state->num_steps].params.update_plane_addr_params.pipe_ctx = pipe_ctx;
1398 seq_state->steps[*seq_state->num_steps].func = HUBP_UPDATE_PLANE_ADDR;
1399 (*seq_state->num_steps)++;
1400 }
1401 }
1402
1403 /*
1404 * Helper function to add DPP set input transfer function to block sequence
1405 */
hwss_add_dpp_set_input_transfer_func(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx,struct dc_plane_state * plane_state)1406 void hwss_add_dpp_set_input_transfer_func(struct block_sequence_state *seq_state,
1407 struct dc *dc,
1408 struct pipe_ctx *pipe_ctx,
1409 struct dc_plane_state *plane_state)
1410 {
1411 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1412 seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.dc = dc;
1413 seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.pipe_ctx = pipe_ctx;
1414 seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.plane_state = plane_state;
1415 seq_state->steps[*seq_state->num_steps].func = DPP_SET_INPUT_TRANSFER_FUNC;
1416 (*seq_state->num_steps)++;
1417 }
1418 }
1419
1420 /*
1421 * Helper function to add DPP program gamut remap to block sequence
1422 */
hwss_add_dpp_program_gamut_remap(struct block_sequence_state * seq_state,struct pipe_ctx * pipe_ctx)1423 void hwss_add_dpp_program_gamut_remap(struct block_sequence_state *seq_state,
1424 struct pipe_ctx *pipe_ctx)
1425 {
1426 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1427 seq_state->steps[*seq_state->num_steps].params.program_gamut_remap_params.pipe_ctx = pipe_ctx;
1428 seq_state->steps[*seq_state->num_steps].func = DPP_PROGRAM_GAMUT_REMAP;
1429 (*seq_state->num_steps)++;
1430 }
1431 }
1432
1433 /*
1434 * Helper function to add DPP program bias and scale to block sequence
1435 */
hwss_add_dpp_program_bias_and_scale(struct block_sequence_state * seq_state,struct pipe_ctx * pipe_ctx)1436 void hwss_add_dpp_program_bias_and_scale(struct block_sequence_state *seq_state, struct pipe_ctx *pipe_ctx)
1437 {
1438 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1439 seq_state->steps[*seq_state->num_steps].params.program_bias_and_scale_params.pipe_ctx = pipe_ctx;
1440 seq_state->steps[*seq_state->num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE;
1441 (*seq_state->num_steps)++;
1442 }
1443 }
1444
1445 /*
1446 * Helper function to add OPTC program manual trigger to block sequence
1447 */
hwss_add_optc_program_manual_trigger(struct block_sequence_state * seq_state,struct pipe_ctx * pipe_ctx)1448 void hwss_add_optc_program_manual_trigger(struct block_sequence_state *seq_state,
1449 struct pipe_ctx *pipe_ctx)
1450 {
1451 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1452 seq_state->steps[*seq_state->num_steps].params.program_manual_trigger_params.pipe_ctx = pipe_ctx;
1453 seq_state->steps[*seq_state->num_steps].func = OPTC_PROGRAM_MANUAL_TRIGGER;
1454 (*seq_state->num_steps)++;
1455 }
1456 }
1457
1458 /*
1459 * Helper function to add DPP set output transfer function to block sequence
1460 */
hwss_add_dpp_set_output_transfer_func(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx,struct dc_stream_state * stream)1461 void hwss_add_dpp_set_output_transfer_func(struct block_sequence_state *seq_state,
1462 struct dc *dc,
1463 struct pipe_ctx *pipe_ctx,
1464 struct dc_stream_state *stream)
1465 {
1466 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1467 seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.dc = dc;
1468 seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.pipe_ctx = pipe_ctx;
1469 seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.stream = stream;
1470 seq_state->steps[*seq_state->num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC;
1471 (*seq_state->num_steps)++;
1472 }
1473 }
1474
1475 /*
1476 * Helper function to add MPC update visual confirm to block sequence
1477 */
hwss_add_mpc_update_visual_confirm(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx,int mpcc_id)1478 void hwss_add_mpc_update_visual_confirm(struct block_sequence_state *seq_state,
1479 struct dc *dc,
1480 struct pipe_ctx *pipe_ctx,
1481 int mpcc_id)
1482 {
1483 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1484 seq_state->steps[*seq_state->num_steps].params.update_visual_confirm_params.dc = dc;
1485 seq_state->steps[*seq_state->num_steps].params.update_visual_confirm_params.pipe_ctx = pipe_ctx;
1486 seq_state->steps[*seq_state->num_steps].params.update_visual_confirm_params.mpcc_id = mpcc_id;
1487 seq_state->steps[*seq_state->num_steps].func = MPC_UPDATE_VISUAL_CONFIRM;
1488 (*seq_state->num_steps)++;
1489 }
1490 }
1491
1492 /*
1493 * Helper function to add MPC power on MPC mem PWR to block sequence
1494 */
hwss_add_mpc_power_on_mpc_mem_pwr(struct block_sequence_state * seq_state,struct mpc * mpc,int mpcc_id,bool power_on)1495 void hwss_add_mpc_power_on_mpc_mem_pwr(struct block_sequence_state *seq_state,
1496 struct mpc *mpc,
1497 int mpcc_id,
1498 bool power_on)
1499 {
1500 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1501 seq_state->steps[*seq_state->num_steps].params.power_on_mpc_mem_pwr_params.mpc = mpc;
1502 seq_state->steps[*seq_state->num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = mpcc_id;
1503 seq_state->steps[*seq_state->num_steps].params.power_on_mpc_mem_pwr_params.power_on = power_on;
1504 seq_state->steps[*seq_state->num_steps].func = MPC_POWER_ON_MPC_MEM_PWR;
1505 (*seq_state->num_steps)++;
1506 }
1507 }
1508
1509 /*
1510 * Helper function to add MPC set output CSC to block sequence
1511 */
hwss_add_mpc_set_output_csc(struct block_sequence_state * seq_state,struct mpc * mpc,int opp_id,const uint16_t * regval,enum mpc_output_csc_mode ocsc_mode)1512 void hwss_add_mpc_set_output_csc(struct block_sequence_state *seq_state,
1513 struct mpc *mpc,
1514 int opp_id,
1515 const uint16_t *regval,
1516 enum mpc_output_csc_mode ocsc_mode)
1517 {
1518 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1519 seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.mpc = mpc;
1520 seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.opp_id = opp_id;
1521 seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.regval = regval;
1522 seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.ocsc_mode = ocsc_mode;
1523 seq_state->steps[*seq_state->num_steps].func = MPC_SET_OUTPUT_CSC;
1524 (*seq_state->num_steps)++;
1525 }
1526 }
1527
1528 /*
1529 * Helper function to add MPC set OCSC default to block sequence
1530 */
hwss_add_mpc_set_ocsc_default(struct block_sequence_state * seq_state,struct mpc * mpc,int opp_id,enum dc_color_space colorspace,enum mpc_output_csc_mode ocsc_mode)1531 void hwss_add_mpc_set_ocsc_default(struct block_sequence_state *seq_state,
1532 struct mpc *mpc,
1533 int opp_id,
1534 enum dc_color_space colorspace,
1535 enum mpc_output_csc_mode ocsc_mode)
1536 {
1537 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1538 seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.mpc = mpc;
1539 seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.opp_id = opp_id;
1540 seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.color_space = colorspace;
1541 seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.ocsc_mode = ocsc_mode;
1542 seq_state->steps[*seq_state->num_steps].func = MPC_SET_OCSC_DEFAULT;
1543 (*seq_state->num_steps)++;
1544 }
1545 }
1546
1547 /*
1548 * Helper function to add DMUB send DMCUB command to block sequence
1549 */
hwss_add_dmub_send_dmcub_cmd(struct block_sequence_state * seq_state,struct dc_context * ctx,union dmub_rb_cmd * cmd,enum dm_dmub_wait_type wait_type)1550 void hwss_add_dmub_send_dmcub_cmd(struct block_sequence_state *seq_state,
1551 struct dc_context *ctx,
1552 union dmub_rb_cmd *cmd,
1553 enum dm_dmub_wait_type wait_type)
1554 {
1555 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1556 seq_state->steps[*seq_state->num_steps].params.send_dmcub_cmd_params.ctx = ctx;
1557 seq_state->steps[*seq_state->num_steps].params.send_dmcub_cmd_params.cmd = cmd;
1558 seq_state->steps[*seq_state->num_steps].params.send_dmcub_cmd_params.wait_type = wait_type;
1559 seq_state->steps[*seq_state->num_steps].func = DMUB_SEND_DMCUB_CMD;
1560 (*seq_state->num_steps)++;
1561 }
1562 }
1563
1564 /*
1565 * Helper function to add DMUB SubVP save surface address to block sequence
1566 */
hwss_add_dmub_subvp_save_surf_addr(struct block_sequence_state * seq_state,struct dc_dmub_srv * dc_dmub_srv,struct dc_plane_address * addr,uint8_t subvp_index)1567 void hwss_add_dmub_subvp_save_surf_addr(struct block_sequence_state *seq_state,
1568 struct dc_dmub_srv *dc_dmub_srv,
1569 struct dc_plane_address *addr,
1570 uint8_t subvp_index)
1571 {
1572 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1573 seq_state->steps[*seq_state->num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc_dmub_srv;
1574 seq_state->steps[*seq_state->num_steps].params.subvp_save_surf_addr.addr = addr;
1575 seq_state->steps[*seq_state->num_steps].params.subvp_save_surf_addr.subvp_index = subvp_index;
1576 seq_state->steps[*seq_state->num_steps].func = DMUB_SUBVP_SAVE_SURF_ADDR;
1577 (*seq_state->num_steps)++;
1578 }
1579 }
1580
1581 /*
1582 * Helper function to add HUBP wait for DCC meta propagation to block sequence
1583 */
hwss_add_hubp_wait_for_dcc_meta_prop(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * top_pipe_to_program)1584 void hwss_add_hubp_wait_for_dcc_meta_prop(struct block_sequence_state *seq_state,
1585 struct dc *dc,
1586 struct pipe_ctx *top_pipe_to_program)
1587 {
1588 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1589 seq_state->steps[*seq_state->num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc;
1590 seq_state->steps[*seq_state->num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = top_pipe_to_program;
1591 seq_state->steps[*seq_state->num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP;
1592 (*seq_state->num_steps)++;
1593 }
1594 }
1595
1596 /*
1597 * Helper function to add HUBP wait pipe read start to block sequence
1598 */
hwss_add_hubp_wait_pipe_read_start(struct block_sequence_state * seq_state,struct hubp * hubp)1599 void hwss_add_hubp_wait_pipe_read_start(struct block_sequence_state *seq_state,
1600 struct hubp *hubp)
1601 {
1602 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1603 seq_state->steps[*seq_state->num_steps].params.hubp_wait_pipe_read_start_params.hubp = hubp;
1604 seq_state->steps[*seq_state->num_steps].func = HUBP_WAIT_PIPE_READ_START;
1605 (*seq_state->num_steps)++;
1606 }
1607 }
1608
1609 /*
1610 * Helper function to add HWS apply update flags for phantom to block sequence
1611 */
hwss_add_hws_apply_update_flags_for_phantom(struct block_sequence_state * seq_state,struct pipe_ctx * pipe_ctx)1612 void hwss_add_hws_apply_update_flags_for_phantom(struct block_sequence_state *seq_state,
1613 struct pipe_ctx *pipe_ctx)
1614 {
1615 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1616 seq_state->steps[*seq_state->num_steps].params.apply_update_flags_for_phantom_params.pipe_ctx = pipe_ctx;
1617 seq_state->steps[*seq_state->num_steps].func = HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM;
1618 (*seq_state->num_steps)++;
1619 }
1620 }
1621
1622 /*
1623 * Helper function to add HWS update phantom VP position to block sequence
1624 */
hwss_add_hws_update_phantom_vp_position(struct block_sequence_state * seq_state,struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx)1625 void hwss_add_hws_update_phantom_vp_position(struct block_sequence_state *seq_state,
1626 struct dc *dc,
1627 struct dc_state *context,
1628 struct pipe_ctx *pipe_ctx)
1629 {
1630 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1631 seq_state->steps[*seq_state->num_steps].params.update_phantom_vp_position_params.dc = dc;
1632 seq_state->steps[*seq_state->num_steps].params.update_phantom_vp_position_params.context = context;
1633 seq_state->steps[*seq_state->num_steps].params.update_phantom_vp_position_params.pipe_ctx = pipe_ctx;
1634 seq_state->steps[*seq_state->num_steps].func = HWS_UPDATE_PHANTOM_VP_POSITION;
1635 (*seq_state->num_steps)++;
1636 }
1637 }
1638
1639 /*
1640 * Helper function to add OPTC set ODM combine to block sequence
1641 */
hwss_add_optc_set_odm_combine(struct block_sequence_state * seq_state,struct timing_generator * tg,int opp_inst[MAX_PIPES],int opp_head_count,int odm_slice_width,int last_odm_slice_width)1642 void hwss_add_optc_set_odm_combine(struct block_sequence_state *seq_state,
1643 struct timing_generator *tg, int opp_inst[MAX_PIPES], int opp_head_count,
1644 int odm_slice_width, int last_odm_slice_width)
1645 {
1646 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1647 seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.tg = tg;
1648 memcpy(seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.opp_inst, opp_inst, sizeof(int) * MAX_PIPES);
1649 seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.opp_head_count = opp_head_count;
1650 seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.odm_slice_width = odm_slice_width;
1651 seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.last_odm_slice_width = last_odm_slice_width;
1652 seq_state->steps[*seq_state->num_steps].func = OPTC_SET_ODM_COMBINE;
1653 (*seq_state->num_steps)++;
1654 }
1655 }
1656
1657 /*
1658 * Helper function to add OPTC set ODM bypass to block sequence
1659 */
hwss_add_optc_set_odm_bypass(struct block_sequence_state * seq_state,struct timing_generator * tg,struct dc_crtc_timing * timing)1660 void hwss_add_optc_set_odm_bypass(struct block_sequence_state *seq_state,
1661 struct timing_generator *tg, struct dc_crtc_timing *timing)
1662 {
1663 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1664 seq_state->steps[*seq_state->num_steps].params.set_odm_bypass_params.tg = tg;
1665 seq_state->steps[*seq_state->num_steps].params.set_odm_bypass_params.timing = timing;
1666 seq_state->steps[*seq_state->num_steps].func = OPTC_SET_ODM_BYPASS;
1667 (*seq_state->num_steps)++;
1668 }
1669 }
1670
hwss_send_dmcub_cmd(union block_sequence_params * params)1671 void hwss_send_dmcub_cmd(union block_sequence_params *params)
1672 {
1673 struct dc_context *ctx = params->send_dmcub_cmd_params.ctx;
1674 union dmub_rb_cmd *cmd = params->send_dmcub_cmd_params.cmd;
1675 enum dm_dmub_wait_type wait_type = params->send_dmcub_cmd_params.wait_type;
1676
1677 dc_wake_and_execute_dmub_cmd(ctx, cmd, wait_type);
1678 }
1679
1680 /*
1681 * Helper function to add TG program global sync to block sequence
1682 */
hwss_add_tg_program_global_sync(struct block_sequence_state * seq_state,struct timing_generator * tg,int vready_offset,unsigned int vstartup_lines,unsigned int vupdate_offset_pixels,unsigned int vupdate_vupdate_width_pixels,unsigned int pstate_keepout_start_lines)1683 void hwss_add_tg_program_global_sync(struct block_sequence_state *seq_state,
1684 struct timing_generator *tg,
1685 int vready_offset,
1686 unsigned int vstartup_lines,
1687 unsigned int vupdate_offset_pixels,
1688 unsigned int vupdate_vupdate_width_pixels,
1689 unsigned int pstate_keepout_start_lines)
1690 {
1691 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1692 seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.tg = tg;
1693 seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vready_offset = vready_offset;
1694 seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vstartup_lines = vstartup_lines;
1695 seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vupdate_offset_pixels = vupdate_offset_pixels;
1696 seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vupdate_vupdate_width_pixels = vupdate_vupdate_width_pixels;
1697 seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.pstate_keepout_start_lines = pstate_keepout_start_lines;
1698 seq_state->steps[*seq_state->num_steps].func = TG_PROGRAM_GLOBAL_SYNC;
1699 (*seq_state->num_steps)++;
1700 }
1701 }
1702
1703 /*
1704 * Helper function to add TG wait for state to block sequence
1705 */
hwss_add_tg_wait_for_state(struct block_sequence_state * seq_state,struct timing_generator * tg,enum crtc_state state)1706 void hwss_add_tg_wait_for_state(struct block_sequence_state *seq_state,
1707 struct timing_generator *tg,
1708 enum crtc_state state)
1709 {
1710 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1711 seq_state->steps[*seq_state->num_steps].params.tg_wait_for_state_params.tg = tg;
1712 seq_state->steps[*seq_state->num_steps].params.tg_wait_for_state_params.state = state;
1713 seq_state->steps[*seq_state->num_steps].func = TG_WAIT_FOR_STATE;
1714 (*seq_state->num_steps)++;
1715 }
1716 }
1717
1718 /*
1719 * Helper function to add TG set VTG params to block sequence
1720 */
hwss_add_tg_set_vtg_params(struct block_sequence_state * seq_state,struct timing_generator * tg,struct dc_crtc_timing * dc_crtc_timing,bool program_fp2)1721 void hwss_add_tg_set_vtg_params(struct block_sequence_state *seq_state,
1722 struct timing_generator *tg,
1723 struct dc_crtc_timing *dc_crtc_timing,
1724 bool program_fp2)
1725 {
1726 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1727 seq_state->steps[*seq_state->num_steps].params.tg_set_vtg_params_params.tg = tg;
1728 seq_state->steps[*seq_state->num_steps].params.tg_set_vtg_params_params.timing = dc_crtc_timing;
1729 seq_state->steps[*seq_state->num_steps].params.tg_set_vtg_params_params.program_fp2 = program_fp2;
1730 seq_state->steps[*seq_state->num_steps].func = TG_SET_VTG_PARAMS;
1731 (*seq_state->num_steps)++;
1732 }
1733 }
1734
1735 /*
1736 * Helper function to add TG setup vertical interrupt2 to block sequence
1737 */
hwss_add_tg_setup_vertical_interrupt2(struct block_sequence_state * seq_state,struct timing_generator * tg,int start_line)1738 void hwss_add_tg_setup_vertical_interrupt2(struct block_sequence_state *seq_state,
1739 struct timing_generator *tg, int start_line)
1740 {
1741 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1742 seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt2_params.tg = tg;
1743 seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt2_params.start_line = start_line;
1744 seq_state->steps[*seq_state->num_steps].func = TG_SETUP_VERTICAL_INTERRUPT2;
1745 (*seq_state->num_steps)++;
1746 }
1747 }
1748
1749 /*
1750 * Helper function to add DPP set HDR multiplier to block sequence
1751 */
hwss_add_dpp_set_hdr_multiplier(struct block_sequence_state * seq_state,struct dpp * dpp,uint32_t hw_mult)1752 void hwss_add_dpp_set_hdr_multiplier(struct block_sequence_state *seq_state,
1753 struct dpp *dpp, uint32_t hw_mult)
1754 {
1755 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1756 seq_state->steps[*seq_state->num_steps].params.dpp_set_hdr_multiplier_params.dpp = dpp;
1757 seq_state->steps[*seq_state->num_steps].params.dpp_set_hdr_multiplier_params.hw_mult = hw_mult;
1758 seq_state->steps[*seq_state->num_steps].func = DPP_SET_HDR_MULTIPLIER;
1759 (*seq_state->num_steps)++;
1760 }
1761 }
1762
1763 /*
1764 * Helper function to add HUBP program DET size to block sequence
1765 */
hwss_add_hubp_program_det_size(struct block_sequence_state * seq_state,struct hubbub * hubbub,unsigned int hubp_inst,unsigned int det_buffer_size_kb)1766 void hwss_add_hubp_program_det_size(struct block_sequence_state *seq_state,
1767 struct hubbub *hubbub,
1768 unsigned int hubp_inst,
1769 unsigned int det_buffer_size_kb)
1770 {
1771 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1772 seq_state->steps[*seq_state->num_steps].params.program_det_size_params.hubbub = hubbub;
1773 seq_state->steps[*seq_state->num_steps].params.program_det_size_params.hubp_inst = hubp_inst;
1774 seq_state->steps[*seq_state->num_steps].params.program_det_size_params.det_buffer_size_kb = det_buffer_size_kb;
1775 seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_DET_SIZE;
1776 (*seq_state->num_steps)++;
1777 }
1778 }
1779
hwss_add_hubp_program_mcache_id(struct block_sequence_state * seq_state,struct hubp * hubp,struct dml2_hubp_pipe_mcache_regs * mcache_regs)1780 void hwss_add_hubp_program_mcache_id(struct block_sequence_state *seq_state,
1781 struct hubp *hubp,
1782 struct dml2_hubp_pipe_mcache_regs *mcache_regs)
1783 {
1784 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1785 seq_state->steps[*seq_state->num_steps].params.program_mcache_id_and_split_coordinate.hubp = hubp;
1786 seq_state->steps[*seq_state->num_steps].params.program_mcache_id_and_split_coordinate.mcache_regs = mcache_regs;
1787 seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_MCACHE_ID;
1788 (*seq_state->num_steps)++;
1789 }
1790 }
1791
hwss_add_hubbub_force_pstate_change_control(struct block_sequence_state * seq_state,struct hubbub * hubbub,bool enable,bool wait)1792 void hwss_add_hubbub_force_pstate_change_control(struct block_sequence_state *seq_state,
1793 struct hubbub *hubbub,
1794 bool enable,
1795 bool wait)
1796 {
1797 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1798 seq_state->steps[*seq_state->num_steps].params.hubbub_force_pstate_change_control_params.hubbub = hubbub;
1799 seq_state->steps[*seq_state->num_steps].params.hubbub_force_pstate_change_control_params.enable = enable;
1800 seq_state->steps[*seq_state->num_steps].params.hubbub_force_pstate_change_control_params.wait = wait;
1801 seq_state->steps[*seq_state->num_steps].func = HUBBUB_FORCE_PSTATE_CHANGE_CONTROL;
1802 (*seq_state->num_steps)++;
1803 }
1804 }
1805
1806 /*
1807 * Helper function to add HUBP program DET segments to block sequence
1808 */
hwss_add_hubp_program_det_segments(struct block_sequence_state * seq_state,struct hubbub * hubbub,unsigned int hubp_inst,unsigned int det_size)1809 void hwss_add_hubp_program_det_segments(struct block_sequence_state *seq_state,
1810 struct hubbub *hubbub,
1811 unsigned int hubp_inst,
1812 unsigned int det_size)
1813 {
1814 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1815 seq_state->steps[*seq_state->num_steps].params.program_det_segments_params.hubbub = hubbub;
1816 seq_state->steps[*seq_state->num_steps].params.program_det_segments_params.hubp_inst = hubp_inst;
1817 seq_state->steps[*seq_state->num_steps].params.program_det_segments_params.det_size = det_size;
1818 seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_DET_SEGMENTS;
1819 (*seq_state->num_steps)++;
1820 }
1821 }
1822
1823 /*
1824 * Helper function to add OPP set dynamic expansion to block sequence
1825 */
hwss_add_opp_set_dyn_expansion(struct block_sequence_state * seq_state,struct output_pixel_processor * opp,enum dc_color_space color_space,enum dc_color_depth color_depth,enum signal_type signal)1826 void hwss_add_opp_set_dyn_expansion(struct block_sequence_state *seq_state,
1827 struct output_pixel_processor *opp,
1828 enum dc_color_space color_space,
1829 enum dc_color_depth color_depth,
1830 enum signal_type signal)
1831 {
1832 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1833 seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.opp = opp;
1834 seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.color_space = color_space;
1835 seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.color_depth = color_depth;
1836 seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.signal = signal;
1837 seq_state->steps[*seq_state->num_steps].func = OPP_SET_DYN_EXPANSION;
1838 (*seq_state->num_steps)++;
1839 }
1840 }
1841
1842 /*
1843 * Helper function to add OPP program FMT to block sequence
1844 */
hwss_add_opp_program_fmt(struct block_sequence_state * seq_state,struct output_pixel_processor * opp,struct bit_depth_reduction_params * fmt_bit_depth,struct clamping_and_pixel_encoding_params * clamping)1845 void hwss_add_opp_program_fmt(struct block_sequence_state *seq_state,
1846 struct output_pixel_processor *opp,
1847 struct bit_depth_reduction_params *fmt_bit_depth,
1848 struct clamping_and_pixel_encoding_params *clamping)
1849 {
1850 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1851 seq_state->steps[*seq_state->num_steps].params.opp_program_fmt_params.opp = opp;
1852 seq_state->steps[*seq_state->num_steps].params.opp_program_fmt_params.fmt_bit_depth = fmt_bit_depth;
1853 seq_state->steps[*seq_state->num_steps].params.opp_program_fmt_params.clamping = clamping;
1854 seq_state->steps[*seq_state->num_steps].func = OPP_PROGRAM_FMT;
1855 (*seq_state->num_steps)++;
1856 }
1857 }
1858
hwss_add_opp_program_left_edge_extra_pixel(struct block_sequence_state * seq_state,struct output_pixel_processor * opp,enum dc_pixel_encoding pixel_encoding,bool is_otg_master)1859 void hwss_add_opp_program_left_edge_extra_pixel(struct block_sequence_state *seq_state,
1860 struct output_pixel_processor *opp,
1861 enum dc_pixel_encoding pixel_encoding,
1862 bool is_otg_master)
1863 {
1864 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1865 seq_state->steps[*seq_state->num_steps].func = OPP_PROGRAM_LEFT_EDGE_EXTRA_PIXEL;
1866 seq_state->steps[*seq_state->num_steps].params.opp_program_left_edge_extra_pixel_params.opp = opp;
1867 seq_state->steps[*seq_state->num_steps].params.opp_program_left_edge_extra_pixel_params.pixel_encoding = pixel_encoding;
1868 seq_state->steps[*seq_state->num_steps].params.opp_program_left_edge_extra_pixel_params.is_otg_master = is_otg_master;
1869 (*seq_state->num_steps)++;
1870 }
1871 }
1872
1873 /*
1874 * Helper function to add ABM set pipe to block sequence
1875 */
hwss_add_abm_set_pipe(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx)1876 void hwss_add_abm_set_pipe(struct block_sequence_state *seq_state,
1877 struct dc *dc,
1878 struct pipe_ctx *pipe_ctx)
1879 {
1880 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1881 seq_state->steps[*seq_state->num_steps].params.set_abm_pipe_params.dc = dc;
1882 seq_state->steps[*seq_state->num_steps].params.set_abm_pipe_params.pipe_ctx = pipe_ctx;
1883 seq_state->steps[*seq_state->num_steps].func = ABM_SET_PIPE;
1884 (*seq_state->num_steps)++;
1885 }
1886 }
1887
1888 /*
1889 * Helper function to add ABM set level to block sequence
1890 */
hwss_add_abm_set_level(struct block_sequence_state * seq_state,struct abm * abm,uint32_t abm_level)1891 void hwss_add_abm_set_level(struct block_sequence_state *seq_state,
1892 struct abm *abm,
1893 uint32_t abm_level)
1894 {
1895 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1896 seq_state->steps[*seq_state->num_steps].params.set_abm_level_params.abm = abm;
1897 seq_state->steps[*seq_state->num_steps].params.set_abm_level_params.abm_level = abm_level;
1898 seq_state->steps[*seq_state->num_steps].func = ABM_SET_LEVEL;
1899 (*seq_state->num_steps)++;
1900 }
1901 }
1902
1903 /*
1904 * Helper function to add TG enable CRTC to block sequence
1905 */
hwss_add_tg_enable_crtc(struct block_sequence_state * seq_state,struct timing_generator * tg)1906 void hwss_add_tg_enable_crtc(struct block_sequence_state *seq_state,
1907 struct timing_generator *tg)
1908 {
1909 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1910 seq_state->steps[*seq_state->num_steps].params.tg_enable_crtc_params.tg = tg;
1911 seq_state->steps[*seq_state->num_steps].func = TG_ENABLE_CRTC;
1912 (*seq_state->num_steps)++;
1913 }
1914 }
1915
1916 /*
1917 * Helper function to add HUBP wait flip pending to block sequence
1918 */
hwss_add_hubp_wait_flip_pending(struct block_sequence_state * seq_state,struct hubp * hubp,unsigned int timeout_us,unsigned int polling_interval_us)1919 void hwss_add_hubp_wait_flip_pending(struct block_sequence_state *seq_state,
1920 struct hubp *hubp,
1921 unsigned int timeout_us,
1922 unsigned int polling_interval_us)
1923 {
1924 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1925 seq_state->steps[*seq_state->num_steps].params.hubp_wait_flip_pending_params.hubp = hubp;
1926 seq_state->steps[*seq_state->num_steps].params.hubp_wait_flip_pending_params.timeout_us = timeout_us;
1927 seq_state->steps[*seq_state->num_steps].params.hubp_wait_flip_pending_params.polling_interval_us = polling_interval_us;
1928 seq_state->steps[*seq_state->num_steps].func = HUBP_WAIT_FLIP_PENDING;
1929 (*seq_state->num_steps)++;
1930 }
1931 }
1932
1933 /*
1934 * Helper function to add TG wait double buffer pending to block sequence
1935 */
hwss_add_tg_wait_double_buffer_pending(struct block_sequence_state * seq_state,struct timing_generator * tg,unsigned int timeout_us,unsigned int polling_interval_us)1936 void hwss_add_tg_wait_double_buffer_pending(struct block_sequence_state *seq_state,
1937 struct timing_generator *tg,
1938 unsigned int timeout_us,
1939 unsigned int polling_interval_us)
1940 {
1941 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1942 seq_state->steps[*seq_state->num_steps].params.tg_wait_double_buffer_pending_params.tg = tg;
1943 seq_state->steps[*seq_state->num_steps].params.tg_wait_double_buffer_pending_params.timeout_us = timeout_us;
1944 seq_state->steps[*seq_state->num_steps].params.tg_wait_double_buffer_pending_params.polling_interval_us = polling_interval_us;
1945 seq_state->steps[*seq_state->num_steps].func = TG_WAIT_DOUBLE_BUFFER_PENDING;
1946 (*seq_state->num_steps)++;
1947 }
1948 }
1949
hwss_program_manual_trigger(union block_sequence_params * params)1950 void hwss_program_manual_trigger(union block_sequence_params *params)
1951 {
1952 struct pipe_ctx *pipe_ctx = params->program_manual_trigger_params.pipe_ctx;
1953
1954 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
1955 pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
1956 }
1957
hwss_setup_dpp(union block_sequence_params * params)1958 void hwss_setup_dpp(union block_sequence_params *params)
1959 {
1960 struct pipe_ctx *pipe_ctx = params->setup_dpp_params.pipe_ctx;
1961 struct dpp *dpp = pipe_ctx->plane_res.dpp;
1962 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1963
1964 if (!plane_state)
1965 return;
1966
1967 if (dpp && dpp->funcs->dpp_setup) {
1968 // program the input csc
1969 dpp->funcs->dpp_setup(dpp,
1970 plane_state->format,
1971 EXPANSION_MODE_ZERO,
1972 plane_state->input_csc_color_matrix,
1973 plane_state->color_space,
1974 NULL);
1975 }
1976 }
1977
hwss_program_bias_and_scale(union block_sequence_params * params)1978 void hwss_program_bias_and_scale(union block_sequence_params *params)
1979 {
1980 struct pipe_ctx *pipe_ctx = params->program_bias_and_scale_params.pipe_ctx;
1981 struct dpp *dpp = pipe_ctx->plane_res.dpp;
1982 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1983 struct dc_bias_and_scale bns_params = plane_state->bias_and_scale;
1984
1985 //TODO :for CNVC set scale and bias registers if necessary
1986 if (dpp->funcs->dpp_program_bias_and_scale)
1987 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1988 }
1989
hwss_power_on_mpc_mem_pwr(union block_sequence_params * params)1990 void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params)
1991 {
1992 struct mpc *mpc = params->power_on_mpc_mem_pwr_params.mpc;
1993 int mpcc_id = params->power_on_mpc_mem_pwr_params.mpcc_id;
1994 bool power_on = params->power_on_mpc_mem_pwr_params.power_on;
1995
1996 if (mpc->funcs->power_on_mpc_mem_pwr)
1997 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, power_on);
1998 }
1999
hwss_set_output_csc(union block_sequence_params * params)2000 void hwss_set_output_csc(union block_sequence_params *params)
2001 {
2002 struct mpc *mpc = params->set_output_csc_params.mpc;
2003 int opp_id = params->set_output_csc_params.opp_id;
2004 const uint16_t *matrix = params->set_output_csc_params.regval;
2005 enum mpc_output_csc_mode ocsc_mode = params->set_output_csc_params.ocsc_mode;
2006
2007 if (mpc->funcs->set_output_csc != NULL)
2008 mpc->funcs->set_output_csc(mpc,
2009 opp_id,
2010 matrix,
2011 ocsc_mode);
2012 }
2013
hwss_set_ocsc_default(union block_sequence_params * params)2014 void hwss_set_ocsc_default(union block_sequence_params *params)
2015 {
2016 struct mpc *mpc = params->set_ocsc_default_params.mpc;
2017 int opp_id = params->set_ocsc_default_params.opp_id;
2018 enum dc_color_space colorspace = params->set_ocsc_default_params.color_space;
2019 enum mpc_output_csc_mode ocsc_mode = params->set_ocsc_default_params.ocsc_mode;
2020
2021 if (mpc->funcs->set_ocsc_default != NULL)
2022 mpc->funcs->set_ocsc_default(mpc,
2023 opp_id,
2024 colorspace,
2025 ocsc_mode);
2026 }
2027
hwss_subvp_save_surf_addr(union block_sequence_params * params)2028 void hwss_subvp_save_surf_addr(union block_sequence_params *params)
2029 {
2030 struct dc_dmub_srv *dc_dmub_srv = params->subvp_save_surf_addr.dc_dmub_srv;
2031 const struct dc_plane_address *addr = params->subvp_save_surf_addr.addr;
2032 uint8_t subvp_index = params->subvp_save_surf_addr.subvp_index;
2033
2034 dc_dmub_srv_subvp_save_surf_addr(dc_dmub_srv, addr, subvp_index);
2035 }
2036
hwss_program_surface_config(union block_sequence_params * params)2037 void hwss_program_surface_config(union block_sequence_params *params)
2038 {
2039 struct hubp *hubp = params->program_surface_config_params.hubp;
2040 enum surface_pixel_format format = params->program_surface_config_params.format;
2041 struct dc_tiling_info *tiling_info = params->program_surface_config_params.tiling_info;
2042 struct plane_size size = params->program_surface_config_params.plane_size;
2043 enum dc_rotation_angle rotation = params->program_surface_config_params.rotation;
2044 struct dc_plane_dcc_param *dcc = params->program_surface_config_params.dcc;
2045 bool horizontal_mirror = params->program_surface_config_params.horizontal_mirror;
2046 int compat_level = params->program_surface_config_params.compat_level;
2047
2048 hubp->funcs->hubp_program_surface_config(
2049 hubp,
2050 format,
2051 tiling_info,
2052 &size,
2053 rotation,
2054 dcc,
2055 horizontal_mirror,
2056 compat_level);
2057
2058 hubp->power_gated = false;
2059 }
2060
hwss_program_mcache_id_and_split_coordinate(union block_sequence_params * params)2061 void hwss_program_mcache_id_and_split_coordinate(union block_sequence_params *params)
2062 {
2063 struct hubp *hubp = params->program_mcache_id_and_split_coordinate.hubp;
2064 struct dml2_hubp_pipe_mcache_regs *mcache_regs = params->program_mcache_id_and_split_coordinate.mcache_regs;
2065
2066 hubp->funcs->hubp_program_mcache_id_and_split_coordinate(hubp, mcache_regs);
2067
2068 }
2069
hwss_program_cm_hist(union block_sequence_params * params)2070 void hwss_program_cm_hist(union block_sequence_params *params)
2071 {
2072 struct dpp *dpp = params->control_cm_hist_params.dpp;
2073
2074 if (dpp && dpp->funcs->dpp_cm_hist_control)
2075 dpp->funcs->dpp_cm_hist_control(dpp,
2076 params->control_cm_hist_params.cm_hist_control,
2077 params->control_cm_hist_params.color_space);
2078 }
2079
get_surface_tile_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)2080 void get_surface_tile_visual_confirm_color(
2081 struct pipe_ctx *pipe_ctx,
2082 struct tg_color *color)
2083 {
2084 uint32_t color_value = MAX_TG_COLOR_VALUE;
2085 /* Determine the overscan color based on the bottom-most plane's context */
2086 struct pipe_ctx *bottom_pipe_ctx = pipe_ctx;
2087
2088 while (bottom_pipe_ctx->bottom_pipe != NULL)
2089 bottom_pipe_ctx = bottom_pipe_ctx->bottom_pipe;
2090
2091 switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) {
2092 case DC_SW_LINEAR:
2093 /* LINEAR Surface - set border color to red */
2094 color->color_r_cr = color_value;
2095 break;
2096 default:
2097 break;
2098 }
2099 }
2100
2101 /**
2102 * hwss_wait_for_all_blank_complete - wait for all active OPPs to finish pending blank
2103 * pattern updates
2104 *
2105 * @dc: [in] dc reference
2106 * @context: [in] hardware context in use
2107 */
hwss_wait_for_all_blank_complete(struct dc * dc,struct dc_state * context)2108 void hwss_wait_for_all_blank_complete(struct dc *dc,
2109 struct dc_state *context)
2110 {
2111 struct pipe_ctx *opp_head;
2112 struct dce_hwseq *hws = dc->hwseq;
2113 int i;
2114
2115 if (!hws->funcs.wait_for_blank_complete)
2116 return;
2117
2118 for (i = 0; i < MAX_PIPES; i++) {
2119 opp_head = &context->res_ctx.pipe_ctx[i];
2120
2121 if (!resource_is_pipe_type(opp_head, OPP_HEAD) ||
2122 dc_state_get_pipe_subvp_type(context, opp_head) == SUBVP_PHANTOM)
2123 continue;
2124
2125 hws->funcs.wait_for_blank_complete(opp_head->stream_res.opp);
2126 }
2127 }
2128
hwss_wait_for_odm_update_pending_complete(struct dc * dc,struct dc_state * context)2129 void hwss_wait_for_odm_update_pending_complete(struct dc *dc, struct dc_state *context)
2130 {
2131 struct pipe_ctx *otg_master;
2132 struct timing_generator *tg;
2133 int i;
2134
2135 for (i = 0; i < MAX_PIPES; i++) {
2136 otg_master = &context->res_ctx.pipe_ctx[i];
2137 if (!resource_is_pipe_type(otg_master, OTG_MASTER) ||
2138 dc_state_get_pipe_subvp_type(context, otg_master) == SUBVP_PHANTOM)
2139 continue;
2140 tg = otg_master->stream_res.tg;
2141 if (tg->funcs->wait_odm_doublebuffer_pending_clear)
2142 tg->funcs->wait_odm_doublebuffer_pending_clear(tg);
2143 if (tg->funcs->wait_otg_disable)
2144 tg->funcs->wait_otg_disable(tg);
2145 }
2146
2147 /* ODM update may require to reprogram blank pattern for each OPP */
2148 hwss_wait_for_all_blank_complete(dc, context);
2149 }
2150
hwss_wait_for_no_pipes_pending(struct dc * dc,struct dc_state * context)2151 void hwss_wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
2152 {
2153 int i;
2154
2155 for (i = 0; i < MAX_PIPES; i++) {
2156 int count = 0;
2157 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2158
2159 if (!pipe->plane_state || dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)
2160 continue;
2161
2162 /* Timeout 100 ms */
2163 while (count < 100000) {
2164 /* Must set to false to start with, due to OR in update function */
2165 pipe->plane_state->status.is_flip_pending = false;
2166 dc->hwss.update_pending_status(pipe);
2167 if (!pipe->plane_state->status.is_flip_pending)
2168 break;
2169 udelay(1);
2170 count++;
2171 }
2172 ASSERT(!pipe->plane_state->status.is_flip_pending);
2173 }
2174 }
2175
hwss_wait_for_outstanding_hw_updates(struct dc * dc,struct dc_state * dc_context)2176 void hwss_wait_for_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context)
2177 {
2178 /*
2179 * This function calls HWSS to wait for any potentially double buffered
2180 * operations to complete. It should be invoked as a pre-amble prior
2181 * to full update programming before asserting any HW locks.
2182 */
2183 int pipe_idx;
2184 int opp_inst;
2185 int opp_count = dc->res_pool->res_cap->num_opp;
2186 struct hubp *hubp;
2187 int mpcc_inst;
2188 const struct pipe_ctx *pipe_ctx;
2189
2190 for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {
2191 pipe_ctx = &dc_context->res_ctx.pipe_ctx[pipe_idx];
2192
2193 if (!pipe_ctx->stream)
2194 continue;
2195
2196 /* For full update we must wait for all double buffer updates, not just DRR updates. This
2197 * is particularly important for minimal transitions. Only check for OTG_MASTER pipes,
2198 * as non-OTG Master pipes share the same OTG as
2199 */
2200 if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && dc->hwss.wait_for_all_pending_updates) {
2201 dc->hwss.wait_for_all_pending_updates(pipe_ctx);
2202 }
2203
2204 hubp = pipe_ctx->plane_res.hubp;
2205 if (!hubp)
2206 continue;
2207
2208 mpcc_inst = hubp->inst;
2209 // MPCC inst is equal to pipe index in practice
2210 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
2211 if ((dc->res_pool->opps[opp_inst] != NULL) &&
2212 (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst])) {
2213 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
2214 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
2215 break;
2216 }
2217 }
2218 }
2219 hwss_wait_for_odm_update_pending_complete(dc, dc_context);
2220 }
2221
hwss_process_outstanding_hw_updates(struct dc * dc,struct dc_state * dc_context)2222 void hwss_process_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context)
2223 {
2224 /* wait for outstanding updates */
2225 hwss_wait_for_outstanding_hw_updates(dc, dc_context);
2226
2227 /* perform outstanding post update programming */
2228 if (dc->hwss.program_outstanding_updates)
2229 dc->hwss.program_outstanding_updates(dc, dc_context);
2230 }
2231
hwss_set_odm_combine(union block_sequence_params * params)2232 void hwss_set_odm_combine(union block_sequence_params *params)
2233 {
2234 struct timing_generator *tg = params->set_odm_combine_params.tg;
2235 int *opp_inst = params->set_odm_combine_params.opp_inst;
2236 int opp_head_count = params->set_odm_combine_params.opp_head_count;
2237 int odm_slice_width = params->set_odm_combine_params.odm_slice_width;
2238 int last_odm_slice_width = params->set_odm_combine_params.last_odm_slice_width;
2239
2240 if (tg && tg->funcs->set_odm_combine)
2241 tg->funcs->set_odm_combine(tg, opp_inst, opp_head_count,
2242 odm_slice_width, last_odm_slice_width);
2243 }
2244
hwss_set_odm_bypass(union block_sequence_params * params)2245 void hwss_set_odm_bypass(union block_sequence_params *params)
2246 {
2247 struct timing_generator *tg = params->set_odm_bypass_params.tg;
2248 const struct dc_crtc_timing *timing = params->set_odm_bypass_params.timing;
2249
2250 if (tg && tg->funcs->set_odm_bypass)
2251 tg->funcs->set_odm_bypass(tg, timing);
2252 }
2253
hwss_opp_pipe_clock_control(union block_sequence_params * params)2254 void hwss_opp_pipe_clock_control(union block_sequence_params *params)
2255 {
2256 struct output_pixel_processor *opp = params->opp_pipe_clock_control_params.opp;
2257 bool enable = params->opp_pipe_clock_control_params.enable;
2258
2259 if (opp && opp->funcs->opp_pipe_clock_control)
2260 opp->funcs->opp_pipe_clock_control(opp, enable);
2261 }
2262
hwss_opp_program_left_edge_extra_pixel(union block_sequence_params * params)2263 void hwss_opp_program_left_edge_extra_pixel(union block_sequence_params *params)
2264 {
2265 struct output_pixel_processor *opp = params->opp_program_left_edge_extra_pixel_params.opp;
2266 enum dc_pixel_encoding pixel_encoding = params->opp_program_left_edge_extra_pixel_params.pixel_encoding;
2267 bool is_otg_master = params->opp_program_left_edge_extra_pixel_params.is_otg_master;
2268
2269 if (opp && opp->funcs->opp_program_left_edge_extra_pixel)
2270 opp->funcs->opp_program_left_edge_extra_pixel(opp, pixel_encoding, is_otg_master);
2271 }
2272
hwss_dccg_set_dto_dscclk(union block_sequence_params * params)2273 void hwss_dccg_set_dto_dscclk(union block_sequence_params *params)
2274 {
2275 struct dccg *dccg = params->dccg_set_dto_dscclk_params.dccg;
2276 int inst = params->dccg_set_dto_dscclk_params.inst;
2277 int num_slices_h = params->dccg_set_dto_dscclk_params.num_slices_h;
2278
2279 if (dccg && dccg->funcs->set_dto_dscclk)
2280 dccg->funcs->set_dto_dscclk(dccg, inst, num_slices_h);
2281 }
2282
hwss_dsc_set_config(union block_sequence_params * params)2283 void hwss_dsc_set_config(union block_sequence_params *params)
2284 {
2285 struct display_stream_compressor *dsc = params->dsc_set_config_params.dsc;
2286 struct dsc_config *dsc_cfg = params->dsc_set_config_params.dsc_cfg;
2287 struct dsc_optc_config *dsc_optc_cfg = params->dsc_set_config_params.dsc_optc_cfg;
2288
2289 if (dsc && dsc->funcs->dsc_set_config)
2290 dsc->funcs->dsc_set_config(dsc, dsc_cfg, dsc_optc_cfg);
2291 }
2292
hwss_dsc_enable(union block_sequence_params * params)2293 void hwss_dsc_enable(union block_sequence_params *params)
2294 {
2295 struct display_stream_compressor *dsc = params->dsc_enable_params.dsc;
2296 int opp_inst = params->dsc_enable_params.opp_inst;
2297
2298 if (dsc && dsc->funcs->dsc_enable)
2299 dsc->funcs->dsc_enable(dsc, opp_inst);
2300 }
2301
hwss_tg_set_dsc_config(union block_sequence_params * params)2302 void hwss_tg_set_dsc_config(union block_sequence_params *params)
2303 {
2304 struct timing_generator *tg = params->tg_set_dsc_config_params.tg;
2305 enum optc_dsc_mode optc_dsc_mode = OPTC_DSC_DISABLED;
2306 uint32_t bytes_per_pixel = 0;
2307 uint32_t slice_width = 0;
2308
2309 if (params->tg_set_dsc_config_params.enable) {
2310 struct dsc_optc_config *dsc_optc_cfg = params->tg_set_dsc_config_params.dsc_optc_cfg;
2311
2312 if (dsc_optc_cfg) {
2313 bytes_per_pixel = dsc_optc_cfg->bytes_per_pixel;
2314 slice_width = dsc_optc_cfg->slice_width;
2315 optc_dsc_mode = dsc_optc_cfg->is_pixel_format_444 ?
2316 OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
2317 }
2318 }
2319
2320 if (tg && tg->funcs->set_dsc_config)
2321 tg->funcs->set_dsc_config(tg, optc_dsc_mode, bytes_per_pixel, slice_width);
2322 }
2323
hwss_dsc_disconnect(union block_sequence_params * params)2324 void hwss_dsc_disconnect(union block_sequence_params *params)
2325 {
2326 struct display_stream_compressor *dsc = params->dsc_disconnect_params.dsc;
2327
2328 if (dsc && dsc->funcs->dsc_disconnect)
2329 dsc->funcs->dsc_disconnect(dsc);
2330 }
2331
hwss_dsc_read_state(union block_sequence_params * params)2332 void hwss_dsc_read_state(union block_sequence_params *params)
2333 {
2334 struct display_stream_compressor *dsc = params->dsc_read_state_params.dsc;
2335 struct dcn_dsc_state *dsc_state = params->dsc_read_state_params.dsc_state;
2336
2337 if (dsc && dsc->funcs->dsc_read_state)
2338 dsc->funcs->dsc_read_state(dsc, dsc_state);
2339 }
2340
hwss_dsc_calculate_and_set_config(union block_sequence_params * params)2341 void hwss_dsc_calculate_and_set_config(union block_sequence_params *params)
2342 {
2343 struct pipe_ctx *pipe_ctx = params->dsc_calculate_and_set_config_params.pipe_ctx;
2344 struct pipe_ctx *top_pipe = pipe_ctx;
2345 bool enable = params->dsc_calculate_and_set_config_params.enable;
2346 int opp_cnt = params->dsc_calculate_and_set_config_params.opp_cnt;
2347
2348 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
2349 struct dc_stream_state *stream = pipe_ctx->stream;
2350
2351 if (!dsc || !enable)
2352 return;
2353
2354 /* Calculate DSC configuration - extracted from dcn32_update_dsc_on_stream */
2355 struct dsc_config dsc_cfg;
2356
2357 while (top_pipe->prev_odm_pipe)
2358 top_pipe = top_pipe->prev_odm_pipe;
2359
2360 dsc_cfg.pic_width = (stream->timing.h_addressable + top_pipe->dsc_padding_params.dsc_hactive_padding +
2361 stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
2362 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
2363 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
2364 dsc_cfg.color_depth = stream->timing.display_color_depth;
2365 dsc_cfg.is_odm = top_pipe->next_odm_pipe ? true : false;
2366 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
2367 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
2368 dsc_cfg.dsc_padding = top_pipe->dsc_padding_params.dsc_hactive_padding;
2369
2370 /* Set DSC configuration */
2371 if (dsc->funcs->dsc_set_config)
2372 dsc->funcs->dsc_set_config(dsc, &dsc_cfg,
2373 ¶ms->dsc_calculate_and_set_config_params.dsc_optc_cfg);
2374 }
2375
hwss_dsc_enable_with_opp(union block_sequence_params * params)2376 void hwss_dsc_enable_with_opp(union block_sequence_params *params)
2377 {
2378 struct pipe_ctx *pipe_ctx = params->dsc_enable_with_opp_params.pipe_ctx;
2379 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
2380
2381 if (dsc && dsc->funcs->dsc_enable)
2382 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
2383 }
2384
hwss_tg_program_global_sync(union block_sequence_params * params)2385 void hwss_tg_program_global_sync(union block_sequence_params *params)
2386 {
2387 struct timing_generator *tg = params->tg_program_global_sync_params.tg;
2388 int vready_offset = params->tg_program_global_sync_params.vready_offset;
2389 unsigned int vstartup_lines = params->tg_program_global_sync_params.vstartup_lines;
2390 unsigned int vupdate_offset_pixels = params->tg_program_global_sync_params.vupdate_offset_pixels;
2391 unsigned int vupdate_vupdate_width_pixels = params->tg_program_global_sync_params.vupdate_vupdate_width_pixels;
2392 unsigned int pstate_keepout_start_lines = params->tg_program_global_sync_params.pstate_keepout_start_lines;
2393
2394 if (tg->funcs->program_global_sync) {
2395 tg->funcs->program_global_sync(tg, vready_offset, vstartup_lines,
2396 vupdate_offset_pixels, vupdate_vupdate_width_pixels, pstate_keepout_start_lines);
2397 }
2398 }
2399
hwss_tg_wait_for_state(union block_sequence_params * params)2400 void hwss_tg_wait_for_state(union block_sequence_params *params)
2401 {
2402 struct timing_generator *tg = params->tg_wait_for_state_params.tg;
2403 enum crtc_state state = params->tg_wait_for_state_params.state;
2404
2405 if (tg->funcs->wait_for_state)
2406 tg->funcs->wait_for_state(tg, state);
2407 }
2408
hwss_tg_set_vtg_params(union block_sequence_params * params)2409 void hwss_tg_set_vtg_params(union block_sequence_params *params)
2410 {
2411 struct timing_generator *tg = params->tg_set_vtg_params_params.tg;
2412 struct dc_crtc_timing *timing = params->tg_set_vtg_params_params.timing;
2413 bool program_fp2 = params->tg_set_vtg_params_params.program_fp2;
2414
2415 if (tg->funcs->set_vtg_params)
2416 tg->funcs->set_vtg_params(tg, timing, program_fp2);
2417 }
2418
hwss_tg_setup_vertical_interrupt2(union block_sequence_params * params)2419 void hwss_tg_setup_vertical_interrupt2(union block_sequence_params *params)
2420 {
2421 struct timing_generator *tg = params->tg_setup_vertical_interrupt2_params.tg;
2422 int start_line = params->tg_setup_vertical_interrupt2_params.start_line;
2423
2424 if (tg->funcs->setup_vertical_interrupt2)
2425 tg->funcs->setup_vertical_interrupt2(tg, start_line);
2426 }
2427
hwss_dpp_set_hdr_multiplier(union block_sequence_params * params)2428 void hwss_dpp_set_hdr_multiplier(union block_sequence_params *params)
2429 {
2430 struct dpp *dpp = params->dpp_set_hdr_multiplier_params.dpp;
2431 uint32_t hw_mult = params->dpp_set_hdr_multiplier_params.hw_mult;
2432
2433 if (dpp->funcs->dpp_set_hdr_multiplier)
2434 dpp->funcs->dpp_set_hdr_multiplier(dpp, hw_mult);
2435 }
2436
hwss_program_det_size(union block_sequence_params * params)2437 void hwss_program_det_size(union block_sequence_params *params)
2438 {
2439 struct hubbub *hubbub = params->program_det_size_params.hubbub;
2440 unsigned int hubp_inst = params->program_det_size_params.hubp_inst;
2441 unsigned int det_buffer_size_kb = params->program_det_size_params.det_buffer_size_kb;
2442
2443 if (hubbub->funcs->program_det_size)
2444 hubbub->funcs->program_det_size(hubbub, hubp_inst, det_buffer_size_kb);
2445 }
2446
hwss_program_det_segments(union block_sequence_params * params)2447 void hwss_program_det_segments(union block_sequence_params *params)
2448 {
2449 struct hubbub *hubbub = params->program_det_segments_params.hubbub;
2450 unsigned int hubp_inst = params->program_det_segments_params.hubp_inst;
2451 unsigned int det_size = params->program_det_segments_params.det_size;
2452
2453 if (hubbub->funcs->program_det_segments)
2454 hubbub->funcs->program_det_segments(hubbub, hubp_inst, det_size);
2455 }
2456
hwss_opp_set_dyn_expansion(union block_sequence_params * params)2457 void hwss_opp_set_dyn_expansion(union block_sequence_params *params)
2458 {
2459 struct output_pixel_processor *opp = params->opp_set_dyn_expansion_params.opp;
2460 enum dc_color_space color_space = params->opp_set_dyn_expansion_params.color_space;
2461 enum dc_color_depth color_depth = params->opp_set_dyn_expansion_params.color_depth;
2462 enum signal_type signal = params->opp_set_dyn_expansion_params.signal;
2463
2464 if (opp->funcs->opp_set_dyn_expansion)
2465 opp->funcs->opp_set_dyn_expansion(opp, color_space, color_depth, signal);
2466 }
2467
hwss_opp_program_fmt(union block_sequence_params * params)2468 void hwss_opp_program_fmt(union block_sequence_params *params)
2469 {
2470 struct output_pixel_processor *opp = params->opp_program_fmt_params.opp;
2471 struct bit_depth_reduction_params *fmt_bit_depth = params->opp_program_fmt_params.fmt_bit_depth;
2472 struct clamping_and_pixel_encoding_params *clamping = params->opp_program_fmt_params.clamping;
2473
2474 if (opp->funcs->opp_program_fmt)
2475 opp->funcs->opp_program_fmt(opp, fmt_bit_depth, clamping);
2476 }
2477
hwss_opp_program_bit_depth_reduction(union block_sequence_params * params)2478 void hwss_opp_program_bit_depth_reduction(union block_sequence_params *params)
2479 {
2480 struct output_pixel_processor *opp = params->opp_program_bit_depth_reduction_params.opp;
2481 bool use_default_params = params->opp_program_bit_depth_reduction_params.use_default_params;
2482 struct pipe_ctx *pipe_ctx = params->opp_program_bit_depth_reduction_params.pipe_ctx;
2483 struct bit_depth_reduction_params bit_depth_params;
2484
2485 if (use_default_params)
2486 memset(&bit_depth_params, 0, sizeof(bit_depth_params));
2487 else
2488 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &bit_depth_params);
2489
2490 if (opp->funcs->opp_program_bit_depth_reduction)
2491 opp->funcs->opp_program_bit_depth_reduction(opp, &bit_depth_params);
2492 }
2493
hwss_opp_set_disp_pattern_generator(union block_sequence_params * params)2494 void hwss_opp_set_disp_pattern_generator(union block_sequence_params *params)
2495 {
2496 struct output_pixel_processor *opp = params->opp_set_disp_pattern_generator_params.opp;
2497 enum controller_dp_test_pattern test_pattern = params->opp_set_disp_pattern_generator_params.test_pattern;
2498 enum controller_dp_color_space color_space = params->opp_set_disp_pattern_generator_params.color_space;
2499 enum dc_color_depth color_depth = params->opp_set_disp_pattern_generator_params.color_depth;
2500 struct tg_color *solid_color = params->opp_set_disp_pattern_generator_params.use_solid_color ?
2501 ¶ms->opp_set_disp_pattern_generator_params.solid_color : NULL;
2502 int width = params->opp_set_disp_pattern_generator_params.width;
2503 int height = params->opp_set_disp_pattern_generator_params.height;
2504 int offset = params->opp_set_disp_pattern_generator_params.offset;
2505
2506 if (opp && opp->funcs->opp_set_disp_pattern_generator) {
2507 opp->funcs->opp_set_disp_pattern_generator(opp, test_pattern, color_space,
2508 color_depth, solid_color, width, height, offset);
2509 }
2510 }
2511
hwss_set_abm_pipe(union block_sequence_params * params)2512 void hwss_set_abm_pipe(union block_sequence_params *params)
2513 {
2514 struct dc *dc = params->set_abm_pipe_params.dc;
2515 struct pipe_ctx *pipe_ctx = params->set_abm_pipe_params.pipe_ctx;
2516
2517 dc->hwss.set_pipe(pipe_ctx);
2518 }
2519
hwss_set_abm_level(union block_sequence_params * params)2520 void hwss_set_abm_level(union block_sequence_params *params)
2521 {
2522 struct abm *abm = params->set_abm_level_params.abm;
2523 unsigned int abm_level = params->set_abm_level_params.abm_level;
2524
2525 if (abm->funcs->set_abm_level)
2526 abm->funcs->set_abm_level(abm, abm_level);
2527 }
2528
hwss_set_abm_immediate_disable(union block_sequence_params * params)2529 void hwss_set_abm_immediate_disable(union block_sequence_params *params)
2530 {
2531 struct dc *dc = params->set_abm_immediate_disable_params.dc;
2532 struct pipe_ctx *pipe_ctx = params->set_abm_immediate_disable_params.pipe_ctx;
2533
2534 if (dc && dc->hwss.set_abm_immediate_disable)
2535 dc->hwss.set_abm_immediate_disable(pipe_ctx);
2536 }
2537
hwss_mpc_remove_mpcc(union block_sequence_params * params)2538 void hwss_mpc_remove_mpcc(union block_sequence_params *params)
2539 {
2540 struct mpc *mpc = params->mpc_remove_mpcc_params.mpc;
2541 struct mpc_tree *mpc_tree_params = params->mpc_remove_mpcc_params.mpc_tree_params;
2542 struct mpcc *mpcc_to_remove = params->mpc_remove_mpcc_params.mpcc_to_remove;
2543
2544 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
2545 }
2546
hwss_opp_set_mpcc_disconnect_pending(union block_sequence_params * params)2547 void hwss_opp_set_mpcc_disconnect_pending(union block_sequence_params *params)
2548 {
2549 struct output_pixel_processor *opp = params->opp_set_mpcc_disconnect_pending_params.opp;
2550 int mpcc_inst = params->opp_set_mpcc_disconnect_pending_params.mpcc_inst;
2551 bool pending = params->opp_set_mpcc_disconnect_pending_params.pending;
2552
2553 opp->mpcc_disconnect_pending[mpcc_inst] = pending;
2554 }
2555
hwss_dc_set_optimized_required(union block_sequence_params * params)2556 void hwss_dc_set_optimized_required(union block_sequence_params *params)
2557 {
2558 struct dc *dc = params->dc_set_optimized_required_params.dc;
2559 bool optimized_required = params->dc_set_optimized_required_params.optimized_required;
2560
2561 dc->optimized_required = optimized_required;
2562 }
2563
hwss_hubp_disconnect(union block_sequence_params * params)2564 void hwss_hubp_disconnect(union block_sequence_params *params)
2565 {
2566 struct hubp *hubp = params->hubp_disconnect_params.hubp;
2567
2568 if (hubp->funcs->hubp_disconnect)
2569 hubp->funcs->hubp_disconnect(hubp);
2570 }
2571
hwss_hubbub_force_pstate_change_control(union block_sequence_params * params)2572 void hwss_hubbub_force_pstate_change_control(union block_sequence_params *params)
2573 {
2574 struct hubbub *hubbub = params->hubbub_force_pstate_change_control_params.hubbub;
2575 bool enable = params->hubbub_force_pstate_change_control_params.enable;
2576 bool wait = params->hubbub_force_pstate_change_control_params.wait;
2577
2578 if (hubbub->funcs->force_pstate_change_control) {
2579 hubbub->funcs->force_pstate_change_control(hubbub, enable, wait);
2580 /* Add delay when enabling pstate change control */
2581 if (enable)
2582 udelay(500);
2583 }
2584 }
2585
hwss_tg_enable_crtc(union block_sequence_params * params)2586 void hwss_tg_enable_crtc(union block_sequence_params *params)
2587 {
2588 struct timing_generator *tg = params->tg_enable_crtc_params.tg;
2589
2590 if (tg->funcs->enable_crtc)
2591 tg->funcs->enable_crtc(tg);
2592 }
2593
hwss_tg_set_gsl(union block_sequence_params * params)2594 void hwss_tg_set_gsl(union block_sequence_params *params)
2595 {
2596 struct timing_generator *tg = params->tg_set_gsl_params.tg;
2597 struct gsl_params *gsl = ¶ms->tg_set_gsl_params.gsl;
2598
2599 if (tg->funcs->set_gsl)
2600 tg->funcs->set_gsl(tg, gsl);
2601 }
2602
hwss_tg_set_gsl_source_select(union block_sequence_params * params)2603 void hwss_tg_set_gsl_source_select(union block_sequence_params *params)
2604 {
2605 struct timing_generator *tg = params->tg_set_gsl_source_select_params.tg;
2606 int group_idx = params->tg_set_gsl_source_select_params.group_idx;
2607 uint32_t gsl_ready_signal = params->tg_set_gsl_source_select_params.gsl_ready_signal;
2608
2609 if (tg->funcs->set_gsl_source_select)
2610 tg->funcs->set_gsl_source_select(tg, group_idx, gsl_ready_signal);
2611 }
2612
hwss_hubp_wait_flip_pending(union block_sequence_params * params)2613 void hwss_hubp_wait_flip_pending(union block_sequence_params *params)
2614 {
2615 struct hubp *hubp = params->hubp_wait_flip_pending_params.hubp;
2616 unsigned int timeout_us = params->hubp_wait_flip_pending_params.timeout_us;
2617 unsigned int polling_interval_us = params->hubp_wait_flip_pending_params.polling_interval_us;
2618 int j = 0;
2619
2620 for (j = 0; j < timeout_us / polling_interval_us
2621 && hubp->funcs->hubp_is_flip_pending(hubp); j++)
2622 udelay(polling_interval_us);
2623 }
2624
hwss_tg_wait_double_buffer_pending(union block_sequence_params * params)2625 void hwss_tg_wait_double_buffer_pending(union block_sequence_params *params)
2626 {
2627 struct timing_generator *tg = params->tg_wait_double_buffer_pending_params.tg;
2628 unsigned int timeout_us = params->tg_wait_double_buffer_pending_params.timeout_us;
2629 unsigned int polling_interval_us = params->tg_wait_double_buffer_pending_params.polling_interval_us;
2630 int j = 0;
2631
2632 if (tg->funcs->get_optc_double_buffer_pending) {
2633 for (j = 0; j < timeout_us / polling_interval_us
2634 && tg->funcs->get_optc_double_buffer_pending(tg); j++)
2635 udelay(polling_interval_us);
2636 }
2637 }
2638
hwss_update_force_pstate(union block_sequence_params * params)2639 void hwss_update_force_pstate(union block_sequence_params *params)
2640 {
2641 struct dc *dc = params->update_force_pstate_params.dc;
2642 struct dc_state *context = params->update_force_pstate_params.context;
2643 struct dce_hwseq *hwseq = dc->hwseq;
2644
2645 if (hwseq->funcs.update_force_pstate)
2646 hwseq->funcs.update_force_pstate(dc, context);
2647 }
2648
hwss_hubbub_apply_dedcn21_147_wa(union block_sequence_params * params)2649 void hwss_hubbub_apply_dedcn21_147_wa(union block_sequence_params *params)
2650 {
2651 struct hubbub *hubbub = params->hubbub_apply_dedcn21_147_wa_params.hubbub;
2652
2653 hubbub->funcs->apply_DEDCN21_147_wa(hubbub);
2654 }
2655
hwss_hubbub_allow_self_refresh_control(union block_sequence_params * params)2656 void hwss_hubbub_allow_self_refresh_control(union block_sequence_params *params)
2657 {
2658 struct hubbub *hubbub = params->hubbub_allow_self_refresh_control_params.hubbub;
2659 bool allow = params->hubbub_allow_self_refresh_control_params.allow;
2660
2661 hubbub->funcs->allow_self_refresh_control(hubbub, allow);
2662
2663 if (!allow && params->hubbub_allow_self_refresh_control_params.disallow_self_refresh_applied)
2664 *params->hubbub_allow_self_refresh_control_params.disallow_self_refresh_applied = true;
2665 }
2666
hwss_tg_get_frame_count(union block_sequence_params * params)2667 void hwss_tg_get_frame_count(union block_sequence_params *params)
2668 {
2669 struct timing_generator *tg = params->tg_get_frame_count_params.tg;
2670 unsigned int *frame_count = params->tg_get_frame_count_params.frame_count;
2671
2672 *frame_count = tg->funcs->get_frame_count(tg);
2673 }
2674
hwss_mpc_set_dwb_mux(union block_sequence_params * params)2675 void hwss_mpc_set_dwb_mux(union block_sequence_params *params)
2676 {
2677 struct mpc *mpc = params->mpc_set_dwb_mux_params.mpc;
2678 int dwb_id = params->mpc_set_dwb_mux_params.dwb_id;
2679 int mpcc_id = params->mpc_set_dwb_mux_params.mpcc_id;
2680
2681 if (mpc->funcs->set_dwb_mux)
2682 mpc->funcs->set_dwb_mux(mpc, dwb_id, mpcc_id);
2683 }
2684
hwss_mpc_disable_dwb_mux(union block_sequence_params * params)2685 void hwss_mpc_disable_dwb_mux(union block_sequence_params *params)
2686 {
2687 struct mpc *mpc = params->mpc_disable_dwb_mux_params.mpc;
2688 unsigned int dwb_id = params->mpc_disable_dwb_mux_params.dwb_id;
2689
2690 if (mpc->funcs->disable_dwb_mux)
2691 mpc->funcs->disable_dwb_mux(mpc, dwb_id);
2692 }
2693
hwss_mcif_wb_config_buf(union block_sequence_params * params)2694 void hwss_mcif_wb_config_buf(union block_sequence_params *params)
2695 {
2696 struct mcif_wb *mcif_wb = params->mcif_wb_config_buf_params.mcif_wb;
2697 struct mcif_buf_params *mcif_buf_params = params->mcif_wb_config_buf_params.mcif_buf_params;
2698 unsigned int dest_height = params->mcif_wb_config_buf_params.dest_height;
2699
2700 if (mcif_wb->funcs->config_mcif_buf)
2701 mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, dest_height);
2702 }
2703
hwss_mcif_wb_config_arb(union block_sequence_params * params)2704 void hwss_mcif_wb_config_arb(union block_sequence_params *params)
2705 {
2706 struct mcif_wb *mcif_wb = params->mcif_wb_config_arb_params.mcif_wb;
2707 struct mcif_arb_params *mcif_arb_params = params->mcif_wb_config_arb_params.mcif_arb_params;
2708
2709 if (mcif_wb->funcs->config_mcif_arb)
2710 mcif_wb->funcs->config_mcif_arb(mcif_wb, mcif_arb_params);
2711 }
2712
hwss_mcif_wb_enable(union block_sequence_params * params)2713 void hwss_mcif_wb_enable(union block_sequence_params *params)
2714 {
2715 struct mcif_wb *mcif_wb = params->mcif_wb_enable_params.mcif_wb;
2716
2717 if (mcif_wb->funcs->enable_mcif)
2718 mcif_wb->funcs->enable_mcif(mcif_wb);
2719 }
2720
hwss_mcif_wb_disable(union block_sequence_params * params)2721 void hwss_mcif_wb_disable(union block_sequence_params *params)
2722 {
2723 struct mcif_wb *mcif_wb = params->mcif_wb_disable_params.mcif_wb;
2724
2725 if (mcif_wb->funcs->disable_mcif)
2726 mcif_wb->funcs->disable_mcif(mcif_wb);
2727 }
2728
hwss_dwbc_enable(union block_sequence_params * params)2729 void hwss_dwbc_enable(union block_sequence_params *params)
2730 {
2731 struct dwbc *dwb = params->dwbc_enable_params.dwb;
2732 struct dc_dwb_params *dwb_params = params->dwbc_enable_params.dwb_params;
2733
2734 if (dwb->funcs->enable)
2735 dwb->funcs->enable(dwb, dwb_params);
2736 }
2737
hwss_dwbc_disable(union block_sequence_params * params)2738 void hwss_dwbc_disable(union block_sequence_params *params)
2739 {
2740 struct dwbc *dwb = params->dwbc_disable_params.dwb;
2741
2742 if (dwb->funcs->disable)
2743 dwb->funcs->disable(dwb);
2744 }
2745
hwss_dwbc_update(union block_sequence_params * params)2746 void hwss_dwbc_update(union block_sequence_params *params)
2747 {
2748 struct dwbc *dwb = params->dwbc_update_params.dwb;
2749 struct dc_dwb_params *dwb_params = params->dwbc_update_params.dwb_params;
2750
2751 if (dwb->funcs->update)
2752 dwb->funcs->update(dwb, dwb_params);
2753 }
2754
hwss_hubp_update_mall_sel(union block_sequence_params * params)2755 void hwss_hubp_update_mall_sel(union block_sequence_params *params)
2756 {
2757 struct hubp *hubp = params->hubp_update_mall_sel_params.hubp;
2758 uint32_t mall_sel = params->hubp_update_mall_sel_params.mall_sel;
2759 bool cache_cursor = params->hubp_update_mall_sel_params.cache_cursor;
2760
2761 if (hubp && hubp->funcs->hubp_update_mall_sel)
2762 hubp->funcs->hubp_update_mall_sel(hubp, mall_sel, cache_cursor);
2763 }
2764
hwss_hubp_prepare_subvp_buffering(union block_sequence_params * params)2765 void hwss_hubp_prepare_subvp_buffering(union block_sequence_params *params)
2766 {
2767 struct hubp *hubp = params->hubp_prepare_subvp_buffering_params.hubp;
2768 bool enable = params->hubp_prepare_subvp_buffering_params.enable;
2769
2770 if (hubp && hubp->funcs->hubp_prepare_subvp_buffering)
2771 hubp->funcs->hubp_prepare_subvp_buffering(hubp, enable);
2772 }
2773
hwss_hubp_set_blank_en(union block_sequence_params * params)2774 void hwss_hubp_set_blank_en(union block_sequence_params *params)
2775 {
2776 struct hubp *hubp = params->hubp_set_blank_en_params.hubp;
2777 bool enable = params->hubp_set_blank_en_params.enable;
2778
2779 if (hubp && hubp->funcs->set_hubp_blank_en)
2780 hubp->funcs->set_hubp_blank_en(hubp, enable);
2781 }
2782
hwss_hubp_disable_control(union block_sequence_params * params)2783 void hwss_hubp_disable_control(union block_sequence_params *params)
2784 {
2785 struct hubp *hubp = params->hubp_disable_control_params.hubp;
2786 bool disable = params->hubp_disable_control_params.disable;
2787
2788 if (hubp && hubp->funcs->hubp_disable_control)
2789 hubp->funcs->hubp_disable_control(hubp, disable);
2790 }
2791
hwss_hubbub_soft_reset(union block_sequence_params * params)2792 void hwss_hubbub_soft_reset(union block_sequence_params *params)
2793 {
2794 struct hubbub *hubbub = params->hubbub_soft_reset_params.hubbub;
2795 bool reset = params->hubbub_soft_reset_params.reset;
2796
2797 if (hubbub)
2798 params->hubbub_soft_reset_params.hubbub_soft_reset(hubbub, reset);
2799 }
2800
hwss_hubp_clk_cntl(union block_sequence_params * params)2801 void hwss_hubp_clk_cntl(union block_sequence_params *params)
2802 {
2803 struct hubp *hubp = params->hubp_clk_cntl_params.hubp;
2804 bool enable = params->hubp_clk_cntl_params.enable;
2805
2806 if (hubp && hubp->funcs->hubp_clk_cntl) {
2807 hubp->funcs->hubp_clk_cntl(hubp, enable);
2808 hubp->power_gated = !enable;
2809 }
2810 }
2811
hwss_hubp_init(union block_sequence_params * params)2812 void hwss_hubp_init(union block_sequence_params *params)
2813 {
2814 struct hubp *hubp = params->hubp_init_params.hubp;
2815
2816 if (hubp && hubp->funcs->hubp_init)
2817 hubp->funcs->hubp_init(hubp);
2818 }
2819
hwss_hubp_set_vm_system_aperture_settings(union block_sequence_params * params)2820 void hwss_hubp_set_vm_system_aperture_settings(union block_sequence_params *params)
2821 {
2822 struct hubp *hubp = params->hubp_set_vm_system_aperture_settings_params.hubp;
2823 struct vm_system_aperture_param apt;
2824
2825 apt.sys_default = params->hubp_set_vm_system_aperture_settings_params.sys_default;
2826 apt.sys_high = params->hubp_set_vm_system_aperture_settings_params.sys_high;
2827 apt.sys_low = params->hubp_set_vm_system_aperture_settings_params.sys_low;
2828
2829 if (hubp && hubp->funcs->hubp_set_vm_system_aperture_settings)
2830 hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
2831 }
2832
hwss_hubp_set_flip_int(union block_sequence_params * params)2833 void hwss_hubp_set_flip_int(union block_sequence_params *params)
2834 {
2835 struct hubp *hubp = params->hubp_set_flip_int_params.hubp;
2836
2837 if (hubp && hubp->funcs->hubp_set_flip_int)
2838 hubp->funcs->hubp_set_flip_int(hubp);
2839 }
2840
hwss_dpp_dppclk_control(union block_sequence_params * params)2841 void hwss_dpp_dppclk_control(union block_sequence_params *params)
2842 {
2843 struct dpp *dpp = params->dpp_dppclk_control_params.dpp;
2844 bool dppclk_div = params->dpp_dppclk_control_params.dppclk_div;
2845 bool enable = params->dpp_dppclk_control_params.enable;
2846
2847 if (dpp && dpp->funcs->dpp_dppclk_control)
2848 dpp->funcs->dpp_dppclk_control(dpp, dppclk_div, enable);
2849 }
2850
hwss_disable_phantom_crtc(union block_sequence_params * params)2851 void hwss_disable_phantom_crtc(union block_sequence_params *params)
2852 {
2853 struct timing_generator *tg = params->disable_phantom_crtc_params.tg;
2854
2855 if (tg && tg->funcs->disable_phantom_crtc)
2856 tg->funcs->disable_phantom_crtc(tg);
2857 }
2858
hwss_dsc_pg_status(union block_sequence_params * params)2859 void hwss_dsc_pg_status(union block_sequence_params *params)
2860 {
2861 struct dce_hwseq *hws = params->dsc_pg_status_params.hws;
2862 int dsc_inst = params->dsc_pg_status_params.dsc_inst;
2863
2864 if (hws && hws->funcs.dsc_pg_status)
2865 params->dsc_pg_status_params.is_ungated = hws->funcs.dsc_pg_status(hws, dsc_inst);
2866 }
2867
hwss_dsc_wait_disconnect_pending_clear(union block_sequence_params * params)2868 void hwss_dsc_wait_disconnect_pending_clear(union block_sequence_params *params)
2869 {
2870 struct display_stream_compressor *dsc = params->dsc_wait_disconnect_pending_clear_params.dsc;
2871
2872 if (!params->dsc_wait_disconnect_pending_clear_params.is_ungated)
2873 return;
2874 if (*params->dsc_wait_disconnect_pending_clear_params.is_ungated == false)
2875 return;
2876
2877 if (dsc && dsc->funcs->dsc_wait_disconnect_pending_clear)
2878 dsc->funcs->dsc_wait_disconnect_pending_clear(dsc);
2879 }
2880
hwss_dsc_disable(union block_sequence_params * params)2881 void hwss_dsc_disable(union block_sequence_params *params)
2882 {
2883 struct display_stream_compressor *dsc = params->dsc_disable_params.dsc;
2884
2885 if (!params->dsc_disable_params.is_ungated)
2886 return;
2887 if (*params->dsc_disable_params.is_ungated == false)
2888 return;
2889
2890 if (dsc && dsc->funcs->dsc_disable)
2891 dsc->funcs->dsc_disable(dsc);
2892 }
2893
hwss_dccg_set_ref_dscclk(union block_sequence_params * params)2894 void hwss_dccg_set_ref_dscclk(union block_sequence_params *params)
2895 {
2896 struct dccg *dccg = params->dccg_set_ref_dscclk_params.dccg;
2897 int dsc_inst = params->dccg_set_ref_dscclk_params.dsc_inst;
2898
2899 if (!params->dccg_set_ref_dscclk_params.is_ungated)
2900 return;
2901 if (*params->dccg_set_ref_dscclk_params.is_ungated == false)
2902 return;
2903
2904 if (dccg && dccg->funcs->set_ref_dscclk)
2905 dccg->funcs->set_ref_dscclk(dccg, dsc_inst);
2906 }
2907
hwss_dpp_pg_control(union block_sequence_params * params)2908 void hwss_dpp_pg_control(union block_sequence_params *params)
2909 {
2910 struct dce_hwseq *hws = params->dpp_pg_control_params.hws;
2911 unsigned int dpp_inst = params->dpp_pg_control_params.dpp_inst;
2912 bool power_on = params->dpp_pg_control_params.power_on;
2913
2914 if (hws->funcs.dpp_pg_control)
2915 hws->funcs.dpp_pg_control(hws, dpp_inst, power_on);
2916 }
2917
hwss_hubp_pg_control(union block_sequence_params * params)2918 void hwss_hubp_pg_control(union block_sequence_params *params)
2919 {
2920 struct dce_hwseq *hws = params->hubp_pg_control_params.hws;
2921 unsigned int hubp_inst = params->hubp_pg_control_params.hubp_inst;
2922 bool power_on = params->hubp_pg_control_params.power_on;
2923
2924 if (hws->funcs.hubp_pg_control)
2925 hws->funcs.hubp_pg_control(hws, hubp_inst, power_on);
2926 }
2927
hwss_hubp_reset(union block_sequence_params * params)2928 void hwss_hubp_reset(union block_sequence_params *params)
2929 {
2930 struct hubp *hubp = params->hubp_reset_params.hubp;
2931
2932 if (hubp && hubp->funcs->hubp_reset)
2933 hubp->funcs->hubp_reset(hubp);
2934 }
2935
hwss_dpp_reset(union block_sequence_params * params)2936 void hwss_dpp_reset(union block_sequence_params *params)
2937 {
2938 struct dpp *dpp = params->dpp_reset_params.dpp;
2939
2940 if (dpp && dpp->funcs->dpp_reset)
2941 dpp->funcs->dpp_reset(dpp);
2942 }
2943
hwss_dpp_root_clock_control(union block_sequence_params * params)2944 void hwss_dpp_root_clock_control(union block_sequence_params *params)
2945 {
2946 struct dce_hwseq *hws = params->dpp_root_clock_control_params.hws;
2947 unsigned int dpp_inst = params->dpp_root_clock_control_params.dpp_inst;
2948 bool clock_on = params->dpp_root_clock_control_params.clock_on;
2949
2950 if (hws->funcs.dpp_root_clock_control)
2951 hws->funcs.dpp_root_clock_control(hws, dpp_inst, clock_on);
2952 }
2953
hwss_dc_ip_request_cntl(union block_sequence_params * params)2954 void hwss_dc_ip_request_cntl(union block_sequence_params *params)
2955 {
2956 struct dc *dc = params->dc_ip_request_cntl_params.dc;
2957 bool enable = params->dc_ip_request_cntl_params.enable;
2958 struct dce_hwseq *hws = dc->hwseq;
2959
2960 if (hws->funcs.dc_ip_request_cntl)
2961 hws->funcs.dc_ip_request_cntl(dc, enable);
2962 }
2963
hwss_dccg_update_dpp_dto(union block_sequence_params * params)2964 void hwss_dccg_update_dpp_dto(union block_sequence_params *params)
2965 {
2966 struct dccg *dccg = params->dccg_update_dpp_dto_params.dccg;
2967 int dpp_inst = params->dccg_update_dpp_dto_params.dpp_inst;
2968 int dppclk_khz = params->dccg_update_dpp_dto_params.dppclk_khz;
2969
2970 if (dccg && dccg->funcs->update_dpp_dto)
2971 dccg->funcs->update_dpp_dto(dccg, dpp_inst, dppclk_khz);
2972 }
2973
hwss_hubp_vtg_sel(union block_sequence_params * params)2974 void hwss_hubp_vtg_sel(union block_sequence_params *params)
2975 {
2976 struct hubp *hubp = params->hubp_vtg_sel_params.hubp;
2977 uint32_t otg_inst = params->hubp_vtg_sel_params.otg_inst;
2978
2979 if (hubp && hubp->funcs->hubp_vtg_sel)
2980 hubp->funcs->hubp_vtg_sel(hubp, otg_inst);
2981 }
2982
hwss_hubp_setup2(union block_sequence_params * params)2983 void hwss_hubp_setup2(union block_sequence_params *params)
2984 {
2985 struct hubp *hubp = params->hubp_setup2_params.hubp;
2986 struct dml2_dchub_per_pipe_register_set *hubp_regs = params->hubp_setup2_params.hubp_regs;
2987 union dml2_global_sync_programming *global_sync = params->hubp_setup2_params.global_sync;
2988 struct dc_crtc_timing *timing = params->hubp_setup2_params.timing;
2989
2990 if (hubp && hubp->funcs->hubp_setup2)
2991 hubp->funcs->hubp_setup2(hubp, hubp_regs, global_sync, timing);
2992 }
2993
hwss_hubp_setup(union block_sequence_params * params)2994 void hwss_hubp_setup(union block_sequence_params *params)
2995 {
2996 struct hubp *hubp = params->hubp_setup_params.hubp;
2997 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = params->hubp_setup_params.dlg_regs;
2998 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = params->hubp_setup_params.ttu_regs;
2999 struct _vcs_dpi_display_rq_regs_st *rq_regs = params->hubp_setup_params.rq_regs;
3000 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest = params->hubp_setup_params.pipe_dest;
3001
3002 if (hubp && hubp->funcs->hubp_setup)
3003 hubp->funcs->hubp_setup(hubp, dlg_regs, ttu_regs, rq_regs, pipe_dest);
3004 }
3005
hwss_hubp_set_unbounded_requesting(union block_sequence_params * params)3006 void hwss_hubp_set_unbounded_requesting(union block_sequence_params *params)
3007 {
3008 struct hubp *hubp = params->hubp_set_unbounded_requesting_params.hubp;
3009 bool unbounded_req = params->hubp_set_unbounded_requesting_params.unbounded_req;
3010
3011 if (hubp && hubp->funcs->set_unbounded_requesting)
3012 hubp->funcs->set_unbounded_requesting(hubp, unbounded_req);
3013 }
3014
hwss_hubp_setup_interdependent2(union block_sequence_params * params)3015 void hwss_hubp_setup_interdependent2(union block_sequence_params *params)
3016 {
3017 struct hubp *hubp = params->hubp_setup_interdependent2_params.hubp;
3018 struct dml2_dchub_per_pipe_register_set *hubp_regs = params->hubp_setup_interdependent2_params.hubp_regs;
3019
3020 if (hubp && hubp->funcs->hubp_setup_interdependent2)
3021 hubp->funcs->hubp_setup_interdependent2(hubp, hubp_regs);
3022 }
3023
hwss_hubp_setup_interdependent(union block_sequence_params * params)3024 void hwss_hubp_setup_interdependent(union block_sequence_params *params)
3025 {
3026 struct hubp *hubp = params->hubp_setup_interdependent_params.hubp;
3027 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = params->hubp_setup_interdependent_params.dlg_regs;
3028 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = params->hubp_setup_interdependent_params.ttu_regs;
3029
3030 if (hubp && hubp->funcs->hubp_setup_interdependent)
3031 hubp->funcs->hubp_setup_interdependent(hubp, dlg_regs, ttu_regs);
3032 }
3033
hwss_dpp_set_cursor_matrix(union block_sequence_params * params)3034 void hwss_dpp_set_cursor_matrix(union block_sequence_params *params)
3035 {
3036 struct dpp *dpp = params->dpp_set_cursor_matrix_params.dpp;
3037 enum dc_color_space color_space = params->dpp_set_cursor_matrix_params.color_space;
3038 struct dc_csc_transform *cursor_csc_color_matrix = params->dpp_set_cursor_matrix_params.cursor_csc_color_matrix;
3039
3040 if (dpp && dpp->funcs->set_cursor_matrix)
3041 dpp->funcs->set_cursor_matrix(dpp, color_space, *cursor_csc_color_matrix);
3042 }
3043
hwss_mpc_update_mpcc(union block_sequence_params * params)3044 void hwss_mpc_update_mpcc(union block_sequence_params *params)
3045 {
3046 struct dc *dc = params->mpc_update_mpcc_params.dc;
3047 struct pipe_ctx *pipe_ctx = params->mpc_update_mpcc_params.pipe_ctx;
3048 struct dce_hwseq *hws = dc->hwseq;
3049
3050 if (hws->funcs.update_mpcc)
3051 hws->funcs.update_mpcc(dc, pipe_ctx);
3052 }
3053
hwss_mpc_update_blending(union block_sequence_params * params)3054 void hwss_mpc_update_blending(union block_sequence_params *params)
3055 {
3056 struct mpc *mpc = params->mpc_update_blending_params.mpc;
3057 struct mpcc_blnd_cfg *blnd_cfg = ¶ms->mpc_update_blending_params.blnd_cfg;
3058 int mpcc_id = params->mpc_update_blending_params.mpcc_id;
3059
3060 if (mpc && mpc->funcs->update_blending)
3061 mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id);
3062 }
3063
hwss_mpc_assert_idle_mpcc(union block_sequence_params * params)3064 void hwss_mpc_assert_idle_mpcc(union block_sequence_params *params)
3065 {
3066 struct mpc *mpc = params->mpc_assert_idle_mpcc_params.mpc;
3067 int mpcc_id = params->mpc_assert_idle_mpcc_params.mpcc_id;
3068
3069 if (mpc && mpc->funcs->wait_for_idle)
3070 mpc->funcs->wait_for_idle(mpc, mpcc_id);
3071 }
3072
hwss_mpc_insert_plane(union block_sequence_params * params)3073 void hwss_mpc_insert_plane(union block_sequence_params *params)
3074 {
3075 struct mpc *mpc = params->mpc_insert_plane_params.mpc;
3076 struct mpc_tree *tree = params->mpc_insert_plane_params.mpc_tree_params;
3077 struct mpcc_blnd_cfg *blnd_cfg = ¶ms->mpc_insert_plane_params.blnd_cfg;
3078 struct mpcc_sm_cfg *sm_cfg = params->mpc_insert_plane_params.sm_cfg;
3079 struct mpcc *insert_above_mpcc = params->mpc_insert_plane_params.insert_above_mpcc;
3080 int mpcc_id = params->mpc_insert_plane_params.mpcc_id;
3081 int dpp_id = params->mpc_insert_plane_params.dpp_id;
3082
3083 if (mpc && mpc->funcs->insert_plane)
3084 mpc->funcs->insert_plane(mpc, tree, blnd_cfg, sm_cfg, insert_above_mpcc,
3085 dpp_id, mpcc_id);
3086 }
3087
hwss_dpp_set_scaler(union block_sequence_params * params)3088 void hwss_dpp_set_scaler(union block_sequence_params *params)
3089 {
3090 struct dpp *dpp = params->dpp_set_scaler_params.dpp;
3091 const struct scaler_data *scl_data = params->dpp_set_scaler_params.scl_data;
3092
3093 if (dpp && dpp->funcs->dpp_set_scaler)
3094 dpp->funcs->dpp_set_scaler(dpp, scl_data);
3095 }
3096
hwss_hubp_mem_program_viewport(union block_sequence_params * params)3097 void hwss_hubp_mem_program_viewport(union block_sequence_params *params)
3098 {
3099 struct hubp *hubp = params->hubp_mem_program_viewport_params.hubp;
3100 const struct rect *viewport = params->hubp_mem_program_viewport_params.viewport;
3101 const struct rect *viewport_c = params->hubp_mem_program_viewport_params.viewport_c;
3102
3103 if (hubp && hubp->funcs->mem_program_viewport)
3104 hubp->funcs->mem_program_viewport(hubp, viewport, viewport_c);
3105 }
3106
hwss_abort_cursor_offload_update(union block_sequence_params * params)3107 void hwss_abort_cursor_offload_update(union block_sequence_params *params)
3108 {
3109 struct dc *dc = params->abort_cursor_offload_update_params.dc;
3110 struct pipe_ctx *pipe_ctx = params->abort_cursor_offload_update_params.pipe_ctx;
3111
3112 if (dc && dc->hwss.abort_cursor_offload_update)
3113 dc->hwss.abort_cursor_offload_update(dc, pipe_ctx);
3114 }
3115
hwss_set_cursor_attribute(union block_sequence_params * params)3116 void hwss_set_cursor_attribute(union block_sequence_params *params)
3117 {
3118 struct dc *dc = params->set_cursor_attribute_params.dc;
3119 struct pipe_ctx *pipe_ctx = params->set_cursor_attribute_params.pipe_ctx;
3120
3121 if (dc && dc->hwss.set_cursor_attribute)
3122 dc->hwss.set_cursor_attribute(pipe_ctx);
3123 }
3124
hwss_set_cursor_position(union block_sequence_params * params)3125 void hwss_set_cursor_position(union block_sequence_params *params)
3126 {
3127 struct dc *dc = params->set_cursor_position_params.dc;
3128 struct pipe_ctx *pipe_ctx = params->set_cursor_position_params.pipe_ctx;
3129
3130 if (dc && dc->hwss.set_cursor_position)
3131 dc->hwss.set_cursor_position(pipe_ctx);
3132 }
3133
hwss_set_cursor_sdr_white_level(union block_sequence_params * params)3134 void hwss_set_cursor_sdr_white_level(union block_sequence_params *params)
3135 {
3136 struct dc *dc = params->set_cursor_sdr_white_level_params.dc;
3137 struct pipe_ctx *pipe_ctx = params->set_cursor_sdr_white_level_params.pipe_ctx;
3138
3139 if (dc && dc->hwss.set_cursor_sdr_white_level)
3140 dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
3141 }
3142
hwss_program_output_csc(union block_sequence_params * params)3143 void hwss_program_output_csc(union block_sequence_params *params)
3144 {
3145 struct dc *dc = params->program_output_csc_params.dc;
3146 struct pipe_ctx *pipe_ctx = params->program_output_csc_params.pipe_ctx;
3147 enum dc_color_space colorspace = params->program_output_csc_params.colorspace;
3148 uint16_t *matrix = params->program_output_csc_params.matrix;
3149 int opp_id = params->program_output_csc_params.opp_id;
3150
3151 if (dc && dc->hwss.program_output_csc)
3152 dc->hwss.program_output_csc(dc, pipe_ctx, colorspace, matrix, opp_id);
3153 }
3154
hwss_hubp_set_blank(union block_sequence_params * params)3155 void hwss_hubp_set_blank(union block_sequence_params *params)
3156 {
3157 struct hubp *hubp = params->hubp_set_blank_params.hubp;
3158 bool blank = params->hubp_set_blank_params.blank;
3159
3160 if (hubp && hubp->funcs->set_blank)
3161 hubp->funcs->set_blank(hubp, blank);
3162 }
3163
hwss_phantom_hubp_post_enable(union block_sequence_params * params)3164 void hwss_phantom_hubp_post_enable(union block_sequence_params *params)
3165 {
3166 struct hubp *hubp = params->phantom_hubp_post_enable_params.hubp;
3167
3168 if (hubp && hubp->funcs->phantom_hubp_post_enable)
3169 hubp->funcs->phantom_hubp_post_enable(hubp);
3170 }
3171
hwss_add_dccg_set_dto_dscclk(struct block_sequence_state * seq_state,struct dccg * dccg,int inst,int num_slices_h)3172 void hwss_add_dccg_set_dto_dscclk(struct block_sequence_state *seq_state,
3173 struct dccg *dccg, int inst, int num_slices_h)
3174 {
3175 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3176 seq_state->steps[*seq_state->num_steps].func = DCCG_SET_DTO_DSCCLK;
3177 seq_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.dccg = dccg;
3178 seq_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.inst = inst;
3179 seq_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.num_slices_h = num_slices_h;
3180 (*seq_state->num_steps)++;
3181 }
3182 }
3183
hwss_add_dsc_calculate_and_set_config(struct block_sequence_state * seq_state,struct pipe_ctx * pipe_ctx,bool enable,int opp_cnt)3184 void hwss_add_dsc_calculate_and_set_config(struct block_sequence_state *seq_state,
3185 struct pipe_ctx *pipe_ctx, bool enable, int opp_cnt)
3186 {
3187 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3188 seq_state->steps[*seq_state->num_steps].func = DSC_CALCULATE_AND_SET_CONFIG;
3189 seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.pipe_ctx = pipe_ctx;
3190 seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.enable = enable;
3191 seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.opp_cnt = opp_cnt;
3192 (*seq_state->num_steps)++;
3193 }
3194 }
3195
hwss_add_mpc_remove_mpcc(struct block_sequence_state * seq_state,struct mpc * mpc,struct mpc_tree * mpc_tree_params,struct mpcc * mpcc_to_remove)3196 void hwss_add_mpc_remove_mpcc(struct block_sequence_state *seq_state,
3197 struct mpc *mpc, struct mpc_tree *mpc_tree_params, struct mpcc *mpcc_to_remove)
3198 {
3199 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3200 seq_state->steps[*seq_state->num_steps].func = MPC_REMOVE_MPCC;
3201 seq_state->steps[*seq_state->num_steps].params.mpc_remove_mpcc_params.mpc = mpc;
3202 seq_state->steps[*seq_state->num_steps].params.mpc_remove_mpcc_params.mpc_tree_params = mpc_tree_params;
3203 seq_state->steps[*seq_state->num_steps].params.mpc_remove_mpcc_params.mpcc_to_remove = mpcc_to_remove;
3204 (*seq_state->num_steps)++;
3205 }
3206 }
3207
hwss_add_opp_set_mpcc_disconnect_pending(struct block_sequence_state * seq_state,struct output_pixel_processor * opp,int mpcc_inst,bool pending)3208 void hwss_add_opp_set_mpcc_disconnect_pending(struct block_sequence_state *seq_state,
3209 struct output_pixel_processor *opp, int mpcc_inst, bool pending)
3210 {
3211 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3212 seq_state->steps[*seq_state->num_steps].func = OPP_SET_MPCC_DISCONNECT_PENDING;
3213 seq_state->steps[*seq_state->num_steps].params.opp_set_mpcc_disconnect_pending_params.opp = opp;
3214 seq_state->steps[*seq_state->num_steps].params.opp_set_mpcc_disconnect_pending_params.mpcc_inst = mpcc_inst;
3215 seq_state->steps[*seq_state->num_steps].params.opp_set_mpcc_disconnect_pending_params.pending = pending;
3216 (*seq_state->num_steps)++;
3217 }
3218 }
3219
hwss_add_hubp_disconnect(struct block_sequence_state * seq_state,struct hubp * hubp)3220 void hwss_add_hubp_disconnect(struct block_sequence_state *seq_state,
3221 struct hubp *hubp)
3222 {
3223 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3224 seq_state->steps[*seq_state->num_steps].func = HUBP_DISCONNECT;
3225 seq_state->steps[*seq_state->num_steps].params.hubp_disconnect_params.hubp = hubp;
3226 (*seq_state->num_steps)++;
3227 }
3228 }
3229
hwss_add_dsc_enable_with_opp(struct block_sequence_state * seq_state,struct pipe_ctx * pipe_ctx)3230 void hwss_add_dsc_enable_with_opp(struct block_sequence_state *seq_state,
3231 struct pipe_ctx *pipe_ctx)
3232 {
3233 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3234 seq_state->steps[*seq_state->num_steps].func = DSC_ENABLE_WITH_OPP;
3235 seq_state->steps[*seq_state->num_steps].params.dsc_enable_with_opp_params.pipe_ctx = pipe_ctx;
3236 (*seq_state->num_steps)++;
3237 }
3238 }
3239
hwss_add_tg_set_dsc_config(struct block_sequence_state * seq_state,struct timing_generator * tg,struct dsc_optc_config * dsc_optc_cfg,bool enable)3240 void hwss_add_tg_set_dsc_config(struct block_sequence_state *seq_state,
3241 struct timing_generator *tg, struct dsc_optc_config *dsc_optc_cfg, bool enable)
3242 {
3243 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3244 seq_state->steps[*seq_state->num_steps].func = TG_SET_DSC_CONFIG;
3245 seq_state->steps[*seq_state->num_steps].params.tg_set_dsc_config_params.tg = tg;
3246 seq_state->steps[*seq_state->num_steps].params.tg_set_dsc_config_params.dsc_optc_cfg = dsc_optc_cfg;
3247 seq_state->steps[*seq_state->num_steps].params.tg_set_dsc_config_params.enable = enable;
3248 (*seq_state->num_steps)++;
3249 }
3250 }
3251
hwss_add_dsc_disconnect(struct block_sequence_state * seq_state,struct display_stream_compressor * dsc)3252 void hwss_add_dsc_disconnect(struct block_sequence_state *seq_state,
3253 struct display_stream_compressor *dsc)
3254 {
3255 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3256 seq_state->steps[*seq_state->num_steps].func = DSC_DISCONNECT;
3257 seq_state->steps[*seq_state->num_steps].params.dsc_disconnect_params.dsc = dsc;
3258 (*seq_state->num_steps)++;
3259 }
3260 }
3261
hwss_add_dc_set_optimized_required(struct block_sequence_state * seq_state,struct dc * dc,bool optimized_required)3262 void hwss_add_dc_set_optimized_required(struct block_sequence_state *seq_state,
3263 struct dc *dc, bool optimized_required)
3264 {
3265 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3266 seq_state->steps[*seq_state->num_steps].func = DC_SET_OPTIMIZED_REQUIRED;
3267 seq_state->steps[*seq_state->num_steps].params.dc_set_optimized_required_params.dc = dc;
3268 seq_state->steps[*seq_state->num_steps].params.dc_set_optimized_required_params.optimized_required = optimized_required;
3269 (*seq_state->num_steps)++;
3270 }
3271 }
3272
hwss_add_abm_set_immediate_disable(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx)3273 void hwss_add_abm_set_immediate_disable(struct block_sequence_state *seq_state,
3274 struct dc *dc, struct pipe_ctx *pipe_ctx)
3275 {
3276 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3277 seq_state->steps[*seq_state->num_steps].func = ABM_SET_IMMEDIATE_DISABLE;
3278 seq_state->steps[*seq_state->num_steps].params.set_abm_immediate_disable_params.dc = dc;
3279 seq_state->steps[*seq_state->num_steps].params.set_abm_immediate_disable_params.pipe_ctx = pipe_ctx;
3280 (*seq_state->num_steps)++;
3281 }
3282 }
3283
hwss_add_opp_set_disp_pattern_generator(struct block_sequence_state * seq_state,struct output_pixel_processor * opp,enum controller_dp_test_pattern test_pattern,enum controller_dp_color_space color_space,enum dc_color_depth color_depth,struct tg_color solid_color,bool use_solid_color,int width,int height,int offset)3284 void hwss_add_opp_set_disp_pattern_generator(struct block_sequence_state *seq_state,
3285 struct output_pixel_processor *opp,
3286 enum controller_dp_test_pattern test_pattern,
3287 enum controller_dp_color_space color_space,
3288 enum dc_color_depth color_depth,
3289 struct tg_color solid_color,
3290 bool use_solid_color,
3291 int width,
3292 int height,
3293 int offset)
3294 {
3295 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3296 seq_state->steps[*seq_state->num_steps].func = OPP_SET_DISP_PATTERN_GENERATOR;
3297 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.opp = opp;
3298 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.test_pattern = test_pattern;
3299 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.color_space = color_space;
3300 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.color_depth = color_depth;
3301 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.solid_color = solid_color;
3302 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.use_solid_color = use_solid_color;
3303 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.width = width;
3304 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.height = height;
3305 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.offset = offset;
3306 (*seq_state->num_steps)++;
3307 }
3308 }
3309
3310 /*
3311 * Helper function to add MPC update blending to block sequence
3312 */
hwss_add_mpc_update_blending(struct block_sequence_state * seq_state,struct mpc * mpc,struct mpcc_blnd_cfg blnd_cfg,int mpcc_id)3313 void hwss_add_mpc_update_blending(struct block_sequence_state *seq_state,
3314 struct mpc *mpc,
3315 struct mpcc_blnd_cfg blnd_cfg,
3316 int mpcc_id)
3317 {
3318 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3319 seq_state->steps[*seq_state->num_steps].func = MPC_UPDATE_BLENDING;
3320 seq_state->steps[*seq_state->num_steps].params.mpc_update_blending_params.mpc = mpc;
3321 seq_state->steps[*seq_state->num_steps].params.mpc_update_blending_params.blnd_cfg = blnd_cfg;
3322 seq_state->steps[*seq_state->num_steps].params.mpc_update_blending_params.mpcc_id = mpcc_id;
3323 (*seq_state->num_steps)++;
3324 }
3325 }
3326
3327 /*
3328 * Helper function to add MPC insert plane to block sequence
3329 */
hwss_add_mpc_insert_plane(struct block_sequence_state * seq_state,struct mpc * mpc,struct mpc_tree * mpc_tree_params,struct mpcc_blnd_cfg blnd_cfg,struct mpcc_sm_cfg * sm_cfg,struct mpcc * insert_above_mpcc,int dpp_id,int mpcc_id)3330 void hwss_add_mpc_insert_plane(struct block_sequence_state *seq_state,
3331 struct mpc *mpc,
3332 struct mpc_tree *mpc_tree_params,
3333 struct mpcc_blnd_cfg blnd_cfg,
3334 struct mpcc_sm_cfg *sm_cfg,
3335 struct mpcc *insert_above_mpcc,
3336 int dpp_id,
3337 int mpcc_id)
3338 {
3339 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3340 seq_state->steps[*seq_state->num_steps].func = MPC_INSERT_PLANE;
3341 seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.mpc = mpc;
3342 seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.mpc_tree_params = mpc_tree_params;
3343 seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.blnd_cfg = blnd_cfg;
3344 seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.sm_cfg = sm_cfg;
3345 seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.insert_above_mpcc = insert_above_mpcc;
3346 seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.dpp_id = dpp_id;
3347 seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.mpcc_id = mpcc_id;
3348 (*seq_state->num_steps)++;
3349 }
3350 }
3351
3352 /*
3353 * Helper function to add MPC assert idle MPCC to block sequence
3354 */
hwss_add_mpc_assert_idle_mpcc(struct block_sequence_state * seq_state,struct mpc * mpc,int mpcc_id)3355 void hwss_add_mpc_assert_idle_mpcc(struct block_sequence_state *seq_state,
3356 struct mpc *mpc,
3357 int mpcc_id)
3358 {
3359 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3360 seq_state->steps[*seq_state->num_steps].func = MPC_ASSERT_IDLE_MPCC;
3361 seq_state->steps[*seq_state->num_steps].params.mpc_assert_idle_mpcc_params.mpc = mpc;
3362 seq_state->steps[*seq_state->num_steps].params.mpc_assert_idle_mpcc_params.mpcc_id = mpcc_id;
3363 (*seq_state->num_steps)++;
3364 }
3365 }
3366
3367 /*
3368 * Helper function to add HUBP set blank to block sequence
3369 */
hwss_add_hubp_set_blank(struct block_sequence_state * seq_state,struct hubp * hubp,bool blank)3370 void hwss_add_hubp_set_blank(struct block_sequence_state *seq_state,
3371 struct hubp *hubp,
3372 bool blank)
3373 {
3374 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3375 seq_state->steps[*seq_state->num_steps].func = HUBP_SET_BLANK;
3376 seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_params.hubp = hubp;
3377 seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_params.blank = blank;
3378 (*seq_state->num_steps)++;
3379 }
3380 }
3381
hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state * seq_state,struct output_pixel_processor * opp,bool use_default_params,struct pipe_ctx * pipe_ctx)3382 void hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state *seq_state,
3383 struct output_pixel_processor *opp,
3384 bool use_default_params,
3385 struct pipe_ctx *pipe_ctx)
3386 {
3387 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3388 seq_state->steps[*seq_state->num_steps].func = OPP_PROGRAM_BIT_DEPTH_REDUCTION;
3389 seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.opp = opp;
3390 seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.use_default_params = use_default_params;
3391 seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.pipe_ctx = pipe_ctx;
3392 (*seq_state->num_steps)++;
3393 }
3394 }
3395
hwss_add_dpp_program_cm_hist(struct block_sequence_state * seq_state,struct dpp * dpp,struct cm_hist_control cm_hist_control,enum dc_color_space color_space)3396 void hwss_add_dpp_program_cm_hist(struct block_sequence_state *seq_state,
3397 struct dpp *dpp,
3398 struct cm_hist_control cm_hist_control,
3399 enum dc_color_space color_space)
3400 {
3401 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3402 seq_state->steps[*seq_state->num_steps].func = DPP_PROGRAM_CM_HIST;
3403 seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.dpp = dpp;
3404 seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.cm_hist_control = cm_hist_control;
3405 seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.color_space = color_space;
3406 (*seq_state->num_steps)++;
3407 }
3408 }
3409
hwss_add_dc_ip_request_cntl(struct block_sequence_state * seq_state,struct dc * dc,bool enable)3410 void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state,
3411 struct dc *dc,
3412 bool enable)
3413 {
3414 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3415 seq_state->steps[*seq_state->num_steps].func = DC_IP_REQUEST_CNTL;
3416 seq_state->steps[*seq_state->num_steps].params.dc_ip_request_cntl_params.dc = dc;
3417 seq_state->steps[*seq_state->num_steps].params.dc_ip_request_cntl_params.enable = enable;
3418 (*seq_state->num_steps)++;
3419 }
3420 }
3421
hwss_add_dwbc_update(struct block_sequence_state * seq_state,struct dwbc * dwb,struct dc_dwb_params * dwb_params)3422 void hwss_add_dwbc_update(struct block_sequence_state *seq_state,
3423 struct dwbc *dwb,
3424 struct dc_dwb_params *dwb_params)
3425 {
3426 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3427 seq_state->steps[*seq_state->num_steps].func = DWBC_UPDATE;
3428 seq_state->steps[*seq_state->num_steps].params.dwbc_update_params.dwb = dwb;
3429 seq_state->steps[*seq_state->num_steps].params.dwbc_update_params.dwb_params = dwb_params;
3430 (*seq_state->num_steps)++;
3431 }
3432 }
3433
hwss_add_mcif_wb_config_buf(struct block_sequence_state * seq_state,struct mcif_wb * mcif_wb,struct mcif_buf_params * mcif_buf_params,unsigned int dest_height)3434 void hwss_add_mcif_wb_config_buf(struct block_sequence_state *seq_state,
3435 struct mcif_wb *mcif_wb,
3436 struct mcif_buf_params *mcif_buf_params,
3437 unsigned int dest_height)
3438 {
3439 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3440 seq_state->steps[*seq_state->num_steps].func = MCIF_WB_CONFIG_BUF;
3441 seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_buf_params.mcif_wb = mcif_wb;
3442 seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_buf_params.mcif_buf_params = mcif_buf_params;
3443 seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_buf_params.dest_height = dest_height;
3444 (*seq_state->num_steps)++;
3445 }
3446 }
3447
hwss_add_mcif_wb_config_arb(struct block_sequence_state * seq_state,struct mcif_wb * mcif_wb,struct mcif_arb_params * mcif_arb_params)3448 void hwss_add_mcif_wb_config_arb(struct block_sequence_state *seq_state,
3449 struct mcif_wb *mcif_wb,
3450 struct mcif_arb_params *mcif_arb_params)
3451 {
3452 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3453 seq_state->steps[*seq_state->num_steps].func = MCIF_WB_CONFIG_ARB;
3454 seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_arb_params.mcif_wb = mcif_wb;
3455 seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_arb_params.mcif_arb_params = mcif_arb_params;
3456 (*seq_state->num_steps)++;
3457 }
3458 }
3459
hwss_add_mcif_wb_enable(struct block_sequence_state * seq_state,struct mcif_wb * mcif_wb)3460 void hwss_add_mcif_wb_enable(struct block_sequence_state *seq_state,
3461 struct mcif_wb *mcif_wb)
3462 {
3463 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3464 seq_state->steps[*seq_state->num_steps].func = MCIF_WB_ENABLE;
3465 seq_state->steps[*seq_state->num_steps].params.mcif_wb_enable_params.mcif_wb = mcif_wb;
3466 (*seq_state->num_steps)++;
3467 }
3468 }
3469
hwss_add_mcif_wb_disable(struct block_sequence_state * seq_state,struct mcif_wb * mcif_wb)3470 void hwss_add_mcif_wb_disable(struct block_sequence_state *seq_state,
3471 struct mcif_wb *mcif_wb)
3472 {
3473 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3474 seq_state->steps[*seq_state->num_steps].func = MCIF_WB_DISABLE;
3475 seq_state->steps[*seq_state->num_steps].params.mcif_wb_disable_params.mcif_wb = mcif_wb;
3476 (*seq_state->num_steps)++;
3477 }
3478 }
3479
hwss_add_mpc_set_dwb_mux(struct block_sequence_state * seq_state,struct mpc * mpc,int dwb_id,int mpcc_id)3480 void hwss_add_mpc_set_dwb_mux(struct block_sequence_state *seq_state,
3481 struct mpc *mpc,
3482 int dwb_id,
3483 int mpcc_id)
3484 {
3485 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3486 seq_state->steps[*seq_state->num_steps].func = MPC_SET_DWB_MUX;
3487 seq_state->steps[*seq_state->num_steps].params.mpc_set_dwb_mux_params.mpc = mpc;
3488 seq_state->steps[*seq_state->num_steps].params.mpc_set_dwb_mux_params.dwb_id = dwb_id;
3489 seq_state->steps[*seq_state->num_steps].params.mpc_set_dwb_mux_params.mpcc_id = mpcc_id;
3490 (*seq_state->num_steps)++;
3491 }
3492 }
3493
hwss_add_mpc_disable_dwb_mux(struct block_sequence_state * seq_state,struct mpc * mpc,unsigned int dwb_id)3494 void hwss_add_mpc_disable_dwb_mux(struct block_sequence_state *seq_state,
3495 struct mpc *mpc,
3496 unsigned int dwb_id)
3497 {
3498 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3499 seq_state->steps[*seq_state->num_steps].func = MPC_DISABLE_DWB_MUX;
3500 seq_state->steps[*seq_state->num_steps].params.mpc_disable_dwb_mux_params.mpc = mpc;
3501 seq_state->steps[*seq_state->num_steps].params.mpc_disable_dwb_mux_params.dwb_id = dwb_id;
3502 (*seq_state->num_steps)++;
3503 }
3504 }
3505
hwss_add_dwbc_enable(struct block_sequence_state * seq_state,struct dwbc * dwb,struct dc_dwb_params * dwb_params)3506 void hwss_add_dwbc_enable(struct block_sequence_state *seq_state,
3507 struct dwbc *dwb,
3508 struct dc_dwb_params *dwb_params)
3509 {
3510 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3511 seq_state->steps[*seq_state->num_steps].func = DWBC_ENABLE;
3512 seq_state->steps[*seq_state->num_steps].params.dwbc_enable_params.dwb = dwb;
3513 seq_state->steps[*seq_state->num_steps].params.dwbc_enable_params.dwb_params = dwb_params;
3514 (*seq_state->num_steps)++;
3515 }
3516 }
3517
hwss_add_dwbc_disable(struct block_sequence_state * seq_state,struct dwbc * dwb)3518 void hwss_add_dwbc_disable(struct block_sequence_state *seq_state,
3519 struct dwbc *dwb)
3520 {
3521 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3522 seq_state->steps[*seq_state->num_steps].func = DWBC_DISABLE;
3523 seq_state->steps[*seq_state->num_steps].params.dwbc_disable_params.dwb = dwb;
3524 (*seq_state->num_steps)++;
3525 }
3526 }
3527
hwss_add_tg_set_gsl(struct block_sequence_state * seq_state,struct timing_generator * tg,struct gsl_params gsl)3528 void hwss_add_tg_set_gsl(struct block_sequence_state *seq_state,
3529 struct timing_generator *tg,
3530 struct gsl_params gsl)
3531 {
3532 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3533 seq_state->steps[*seq_state->num_steps].func = TG_SET_GSL;
3534 seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_params.tg = tg;
3535 seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_params.gsl = gsl;
3536 (*seq_state->num_steps)++;
3537 }
3538 }
3539
hwss_add_tg_set_gsl_source_select(struct block_sequence_state * seq_state,struct timing_generator * tg,int group_idx,uint32_t gsl_ready_signal)3540 void hwss_add_tg_set_gsl_source_select(struct block_sequence_state *seq_state,
3541 struct timing_generator *tg,
3542 int group_idx,
3543 uint32_t gsl_ready_signal)
3544 {
3545 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3546 seq_state->steps[*seq_state->num_steps].func = TG_SET_GSL_SOURCE_SELECT;
3547 seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_source_select_params.tg = tg;
3548 seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_source_select_params.group_idx = group_idx;
3549 seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_source_select_params.gsl_ready_signal = gsl_ready_signal;
3550 (*seq_state->num_steps)++;
3551 }
3552 }
3553
hwss_add_hubp_update_mall_sel(struct block_sequence_state * seq_state,struct hubp * hubp,uint32_t mall_sel,bool cache_cursor)3554 void hwss_add_hubp_update_mall_sel(struct block_sequence_state *seq_state,
3555 struct hubp *hubp,
3556 uint32_t mall_sel,
3557 bool cache_cursor)
3558 {
3559 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3560 seq_state->steps[*seq_state->num_steps].func = HUBP_UPDATE_MALL_SEL;
3561 seq_state->steps[*seq_state->num_steps].params.hubp_update_mall_sel_params.hubp = hubp;
3562 seq_state->steps[*seq_state->num_steps].params.hubp_update_mall_sel_params.mall_sel = mall_sel;
3563 seq_state->steps[*seq_state->num_steps].params.hubp_update_mall_sel_params.cache_cursor = cache_cursor;
3564 (*seq_state->num_steps)++;
3565 }
3566 }
3567
hwss_add_hubp_prepare_subvp_buffering(struct block_sequence_state * seq_state,struct hubp * hubp,bool enable)3568 void hwss_add_hubp_prepare_subvp_buffering(struct block_sequence_state *seq_state,
3569 struct hubp *hubp,
3570 bool enable)
3571 {
3572 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3573 seq_state->steps[*seq_state->num_steps].func = HUBP_PREPARE_SUBVP_BUFFERING;
3574 seq_state->steps[*seq_state->num_steps].params.hubp_prepare_subvp_buffering_params.hubp = hubp;
3575 seq_state->steps[*seq_state->num_steps].params.hubp_prepare_subvp_buffering_params.enable = enable;
3576 (*seq_state->num_steps)++;
3577 }
3578 }
3579
hwss_add_hubp_set_blank_en(struct block_sequence_state * seq_state,struct hubp * hubp,bool enable)3580 void hwss_add_hubp_set_blank_en(struct block_sequence_state *seq_state,
3581 struct hubp *hubp,
3582 bool enable)
3583 {
3584 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3585 seq_state->steps[*seq_state->num_steps].func = HUBP_SET_BLANK_EN;
3586 seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_en_params.hubp = hubp;
3587 seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_en_params.enable = enable;
3588 (*seq_state->num_steps)++;
3589 }
3590 }
3591
hwss_add_hubp_disable_control(struct block_sequence_state * seq_state,struct hubp * hubp,bool disable)3592 void hwss_add_hubp_disable_control(struct block_sequence_state *seq_state,
3593 struct hubp *hubp,
3594 bool disable)
3595 {
3596 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3597 seq_state->steps[*seq_state->num_steps].func = HUBP_DISABLE_CONTROL;
3598 seq_state->steps[*seq_state->num_steps].params.hubp_disable_control_params.hubp = hubp;
3599 seq_state->steps[*seq_state->num_steps].params.hubp_disable_control_params.disable = disable;
3600 (*seq_state->num_steps)++;
3601 }
3602 }
3603
hwss_add_hubbub_soft_reset(struct block_sequence_state * seq_state,struct hubbub * hubbub,void (* hubbub_soft_reset)(struct hubbub * hubbub,bool reset),bool reset)3604 void hwss_add_hubbub_soft_reset(struct block_sequence_state *seq_state,
3605 struct hubbub *hubbub,
3606 void (*hubbub_soft_reset)(struct hubbub *hubbub, bool reset),
3607 bool reset)
3608 {
3609 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3610 seq_state->steps[*seq_state->num_steps].func = HUBBUB_SOFT_RESET;
3611 seq_state->steps[*seq_state->num_steps].params.hubbub_soft_reset_params.hubbub = hubbub;
3612 seq_state->steps[*seq_state->num_steps].params.hubbub_soft_reset_params.hubbub_soft_reset = hubbub_soft_reset;
3613 seq_state->steps[*seq_state->num_steps].params.hubbub_soft_reset_params.reset = reset;
3614 (*seq_state->num_steps)++;
3615 }
3616 }
3617
hwss_add_hubp_clk_cntl(struct block_sequence_state * seq_state,struct hubp * hubp,bool enable)3618 void hwss_add_hubp_clk_cntl(struct block_sequence_state *seq_state,
3619 struct hubp *hubp,
3620 bool enable)
3621 {
3622 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3623 seq_state->steps[*seq_state->num_steps].func = HUBP_CLK_CNTL;
3624 seq_state->steps[*seq_state->num_steps].params.hubp_clk_cntl_params.hubp = hubp;
3625 seq_state->steps[*seq_state->num_steps].params.hubp_clk_cntl_params.enable = enable;
3626 (*seq_state->num_steps)++;
3627 }
3628 }
3629
hwss_add_dpp_dppclk_control(struct block_sequence_state * seq_state,struct dpp * dpp,bool dppclk_div,bool enable)3630 void hwss_add_dpp_dppclk_control(struct block_sequence_state *seq_state,
3631 struct dpp *dpp,
3632 bool dppclk_div,
3633 bool enable)
3634 {
3635 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3636 seq_state->steps[*seq_state->num_steps].func = DPP_DPPCLK_CONTROL;
3637 seq_state->steps[*seq_state->num_steps].params.dpp_dppclk_control_params.dpp = dpp;
3638 seq_state->steps[*seq_state->num_steps].params.dpp_dppclk_control_params.dppclk_div = dppclk_div;
3639 seq_state->steps[*seq_state->num_steps].params.dpp_dppclk_control_params.enable = enable;
3640 (*seq_state->num_steps)++;
3641 }
3642 }
3643
hwss_add_disable_phantom_crtc(struct block_sequence_state * seq_state,struct timing_generator * tg)3644 void hwss_add_disable_phantom_crtc(struct block_sequence_state *seq_state,
3645 struct timing_generator *tg)
3646 {
3647 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3648 seq_state->steps[*seq_state->num_steps].func = DISABLE_PHANTOM_CRTC;
3649 seq_state->steps[*seq_state->num_steps].params.disable_phantom_crtc_params.tg = tg;
3650 (*seq_state->num_steps)++;
3651 }
3652 }
3653
hwss_add_dsc_pg_status(struct block_sequence_state * seq_state,struct dce_hwseq * hws,int dsc_inst,bool is_ungated)3654 void hwss_add_dsc_pg_status(struct block_sequence_state *seq_state,
3655 struct dce_hwseq *hws,
3656 int dsc_inst,
3657 bool is_ungated)
3658 {
3659 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3660 seq_state->steps[*seq_state->num_steps].func = DSC_PG_STATUS;
3661 seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.hws = hws;
3662 seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.dsc_inst = dsc_inst;
3663 seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.is_ungated = is_ungated;
3664 (*seq_state->num_steps)++;
3665 }
3666 }
3667
hwss_add_dsc_wait_disconnect_pending_clear(struct block_sequence_state * seq_state,struct display_stream_compressor * dsc,bool * is_ungated)3668 void hwss_add_dsc_wait_disconnect_pending_clear(struct block_sequence_state *seq_state,
3669 struct display_stream_compressor *dsc,
3670 bool *is_ungated)
3671 {
3672 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3673 seq_state->steps[*seq_state->num_steps].func = DSC_WAIT_DISCONNECT_PENDING_CLEAR;
3674 seq_state->steps[*seq_state->num_steps].params.dsc_wait_disconnect_pending_clear_params.dsc = dsc;
3675 seq_state->steps[*seq_state->num_steps].params.dsc_wait_disconnect_pending_clear_params.is_ungated = is_ungated;
3676 (*seq_state->num_steps)++;
3677 }
3678 }
3679
hwss_add_dsc_disable(struct block_sequence_state * seq_state,struct display_stream_compressor * dsc,bool * is_ungated)3680 void hwss_add_dsc_disable(struct block_sequence_state *seq_state,
3681 struct display_stream_compressor *dsc,
3682 bool *is_ungated)
3683 {
3684 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3685 seq_state->steps[*seq_state->num_steps].func = DSC_DISABLE;
3686 seq_state->steps[*seq_state->num_steps].params.dsc_disable_params.dsc = dsc;
3687 seq_state->steps[*seq_state->num_steps].params.dsc_disable_params.is_ungated = is_ungated;
3688 (*seq_state->num_steps)++;
3689 }
3690 }
3691
hwss_add_dccg_set_ref_dscclk(struct block_sequence_state * seq_state,struct dccg * dccg,int dsc_inst,bool * is_ungated)3692 void hwss_add_dccg_set_ref_dscclk(struct block_sequence_state *seq_state,
3693 struct dccg *dccg,
3694 int dsc_inst,
3695 bool *is_ungated)
3696 {
3697 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3698 seq_state->steps[*seq_state->num_steps].func = DCCG_SET_REF_DSCCLK;
3699 seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.dccg = dccg;
3700 seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.dsc_inst = dsc_inst;
3701 seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.is_ungated = is_ungated;
3702 (*seq_state->num_steps)++;
3703 }
3704 }
3705
hwss_add_dpp_root_clock_control(struct block_sequence_state * seq_state,struct dce_hwseq * hws,unsigned int dpp_inst,bool clock_on)3706 void hwss_add_dpp_root_clock_control(struct block_sequence_state *seq_state,
3707 struct dce_hwseq *hws,
3708 unsigned int dpp_inst,
3709 bool clock_on)
3710 {
3711 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3712 seq_state->steps[*seq_state->num_steps].func = DPP_ROOT_CLOCK_CONTROL;
3713 seq_state->steps[*seq_state->num_steps].params.dpp_root_clock_control_params.hws = hws;
3714 seq_state->steps[*seq_state->num_steps].params.dpp_root_clock_control_params.dpp_inst = dpp_inst;
3715 seq_state->steps[*seq_state->num_steps].params.dpp_root_clock_control_params.clock_on = clock_on;
3716 (*seq_state->num_steps)++;
3717 }
3718 }
3719
hwss_add_dpp_pg_control(struct block_sequence_state * seq_state,struct dce_hwseq * hws,unsigned int dpp_inst,bool power_on)3720 void hwss_add_dpp_pg_control(struct block_sequence_state *seq_state,
3721 struct dce_hwseq *hws,
3722 unsigned int dpp_inst,
3723 bool power_on)
3724 {
3725 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3726 seq_state->steps[*seq_state->num_steps].func = DPP_PG_CONTROL;
3727 seq_state->steps[*seq_state->num_steps].params.dpp_pg_control_params.hws = hws;
3728 seq_state->steps[*seq_state->num_steps].params.dpp_pg_control_params.dpp_inst = dpp_inst;
3729 seq_state->steps[*seq_state->num_steps].params.dpp_pg_control_params.power_on = power_on;
3730 (*seq_state->num_steps)++;
3731 }
3732 }
3733
hwss_add_hubp_pg_control(struct block_sequence_state * seq_state,struct dce_hwseq * hws,unsigned int hubp_inst,bool power_on)3734 void hwss_add_hubp_pg_control(struct block_sequence_state *seq_state,
3735 struct dce_hwseq *hws,
3736 unsigned int hubp_inst,
3737 bool power_on)
3738 {
3739 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3740 seq_state->steps[*seq_state->num_steps].func = HUBP_PG_CONTROL;
3741 seq_state->steps[*seq_state->num_steps].params.hubp_pg_control_params.hws = hws;
3742 seq_state->steps[*seq_state->num_steps].params.hubp_pg_control_params.hubp_inst = hubp_inst;
3743 seq_state->steps[*seq_state->num_steps].params.hubp_pg_control_params.power_on = power_on;
3744 (*seq_state->num_steps)++;
3745 }
3746 }
3747
hwss_add_hubp_init(struct block_sequence_state * seq_state,struct hubp * hubp)3748 void hwss_add_hubp_init(struct block_sequence_state *seq_state,
3749 struct hubp *hubp)
3750 {
3751 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3752 seq_state->steps[*seq_state->num_steps].func = HUBP_INIT;
3753 seq_state->steps[*seq_state->num_steps].params.hubp_init_params.hubp = hubp;
3754 (*seq_state->num_steps)++;
3755 }
3756 }
3757
hwss_add_hubp_reset(struct block_sequence_state * seq_state,struct hubp * hubp)3758 void hwss_add_hubp_reset(struct block_sequence_state *seq_state,
3759 struct hubp *hubp)
3760 {
3761 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3762 seq_state->steps[*seq_state->num_steps].func = HUBP_RESET;
3763 seq_state->steps[*seq_state->num_steps].params.hubp_reset_params.hubp = hubp;
3764 (*seq_state->num_steps)++;
3765 }
3766 }
3767
hwss_add_dpp_reset(struct block_sequence_state * seq_state,struct dpp * dpp)3768 void hwss_add_dpp_reset(struct block_sequence_state *seq_state,
3769 struct dpp *dpp)
3770 {
3771 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3772 seq_state->steps[*seq_state->num_steps].func = DPP_RESET;
3773 seq_state->steps[*seq_state->num_steps].params.dpp_reset_params.dpp = dpp;
3774 (*seq_state->num_steps)++;
3775 }
3776 }
3777
hwss_add_opp_pipe_clock_control(struct block_sequence_state * seq_state,struct output_pixel_processor * opp,bool enable)3778 void hwss_add_opp_pipe_clock_control(struct block_sequence_state *seq_state,
3779 struct output_pixel_processor *opp,
3780 bool enable)
3781 {
3782 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3783 seq_state->steps[*seq_state->num_steps].func = OPP_PIPE_CLOCK_CONTROL;
3784 seq_state->steps[*seq_state->num_steps].params.opp_pipe_clock_control_params.opp = opp;
3785 seq_state->steps[*seq_state->num_steps].params.opp_pipe_clock_control_params.enable = enable;
3786 (*seq_state->num_steps)++;
3787 }
3788 }
3789
hwss_add_hubp_set_vm_system_aperture_settings(struct block_sequence_state * seq_state,struct hubp * hubp,uint64_t sys_default,uint64_t sys_low,uint64_t sys_high)3790 void hwss_add_hubp_set_vm_system_aperture_settings(struct block_sequence_state *seq_state,
3791 struct hubp *hubp,
3792 uint64_t sys_default,
3793 uint64_t sys_low,
3794 uint64_t sys_high)
3795 {
3796 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3797 seq_state->steps[*seq_state->num_steps].func = HUBP_SET_VM_SYSTEM_APERTURE_SETTINGS;
3798 seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.hubp = hubp;
3799 seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_default.quad_part = sys_default;
3800 seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_low.quad_part = sys_low;
3801 seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_high.quad_part = sys_high;
3802 (*seq_state->num_steps)++;
3803 }
3804 }
3805
hwss_add_hubp_set_flip_int(struct block_sequence_state * seq_state,struct hubp * hubp)3806 void hwss_add_hubp_set_flip_int(struct block_sequence_state *seq_state,
3807 struct hubp *hubp)
3808 {
3809 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3810 seq_state->steps[*seq_state->num_steps].func = HUBP_SET_FLIP_INT;
3811 seq_state->steps[*seq_state->num_steps].params.hubp_set_flip_int_params.hubp = hubp;
3812 (*seq_state->num_steps)++;
3813 }
3814 }
3815
hwss_add_dccg_update_dpp_dto(struct block_sequence_state * seq_state,struct dccg * dccg,int dpp_inst,int dppclk_khz)3816 void hwss_add_dccg_update_dpp_dto(struct block_sequence_state *seq_state,
3817 struct dccg *dccg,
3818 int dpp_inst,
3819 int dppclk_khz)
3820 {
3821 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3822 seq_state->steps[*seq_state->num_steps].func = DCCG_UPDATE_DPP_DTO;
3823 seq_state->steps[*seq_state->num_steps].params.dccg_update_dpp_dto_params.dccg = dccg;
3824 seq_state->steps[*seq_state->num_steps].params.dccg_update_dpp_dto_params.dpp_inst = dpp_inst;
3825 seq_state->steps[*seq_state->num_steps].params.dccg_update_dpp_dto_params.dppclk_khz = dppclk_khz;
3826 (*seq_state->num_steps)++;
3827 }
3828 }
3829
hwss_add_hubp_vtg_sel(struct block_sequence_state * seq_state,struct hubp * hubp,uint32_t otg_inst)3830 void hwss_add_hubp_vtg_sel(struct block_sequence_state *seq_state,
3831 struct hubp *hubp,
3832 uint32_t otg_inst)
3833 {
3834 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3835 seq_state->steps[*seq_state->num_steps].func = HUBP_VTG_SEL;
3836 seq_state->steps[*seq_state->num_steps].params.hubp_vtg_sel_params.hubp = hubp;
3837 seq_state->steps[*seq_state->num_steps].params.hubp_vtg_sel_params.otg_inst = otg_inst;
3838 (*seq_state->num_steps)++;
3839 }
3840 }
3841
hwss_add_hubp_setup2(struct block_sequence_state * seq_state,struct hubp * hubp,struct dml2_dchub_per_pipe_register_set * hubp_regs,union dml2_global_sync_programming * global_sync,struct dc_crtc_timing * timing)3842 void hwss_add_hubp_setup2(struct block_sequence_state *seq_state,
3843 struct hubp *hubp,
3844 struct dml2_dchub_per_pipe_register_set *hubp_regs,
3845 union dml2_global_sync_programming *global_sync,
3846 struct dc_crtc_timing *timing)
3847 {
3848 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3849 seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP2;
3850 seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.hubp = hubp;
3851 seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.hubp_regs = hubp_regs;
3852 seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.global_sync = global_sync;
3853 seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.timing = timing;
3854 (*seq_state->num_steps)++;
3855 }
3856 }
3857
hwss_add_hubp_setup(struct block_sequence_state * seq_state,struct hubp * hubp,struct _vcs_dpi_display_dlg_regs_st * dlg_regs,struct _vcs_dpi_display_ttu_regs_st * ttu_regs,struct _vcs_dpi_display_rq_regs_st * rq_regs,struct _vcs_dpi_display_pipe_dest_params_st * pipe_dest)3858 void hwss_add_hubp_setup(struct block_sequence_state *seq_state,
3859 struct hubp *hubp,
3860 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
3861 struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
3862 struct _vcs_dpi_display_rq_regs_st *rq_regs,
3863 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
3864 {
3865 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3866 seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP;
3867 seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.hubp = hubp;
3868 seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.dlg_regs = dlg_regs;
3869 seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.ttu_regs = ttu_regs;
3870 seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.rq_regs = rq_regs;
3871 seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.pipe_dest = pipe_dest;
3872 (*seq_state->num_steps)++;
3873 }
3874 }
3875
hwss_add_hubp_set_unbounded_requesting(struct block_sequence_state * seq_state,struct hubp * hubp,bool unbounded_req)3876 void hwss_add_hubp_set_unbounded_requesting(struct block_sequence_state *seq_state,
3877 struct hubp *hubp,
3878 bool unbounded_req)
3879 {
3880 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3881 seq_state->steps[*seq_state->num_steps].func = HUBP_SET_UNBOUNDED_REQUESTING;
3882 seq_state->steps[*seq_state->num_steps].params.hubp_set_unbounded_requesting_params.hubp = hubp;
3883 seq_state->steps[*seq_state->num_steps].params.hubp_set_unbounded_requesting_params.unbounded_req = unbounded_req;
3884 (*seq_state->num_steps)++;
3885 }
3886 }
3887
hwss_add_hubp_setup_interdependent2(struct block_sequence_state * seq_state,struct hubp * hubp,struct dml2_dchub_per_pipe_register_set * hubp_regs)3888 void hwss_add_hubp_setup_interdependent2(struct block_sequence_state *seq_state,
3889 struct hubp *hubp,
3890 struct dml2_dchub_per_pipe_register_set *hubp_regs)
3891 {
3892 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3893 seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP_INTERDEPENDENT2;
3894 seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent2_params.hubp = hubp;
3895 seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent2_params.hubp_regs = hubp_regs;
3896 (*seq_state->num_steps)++;
3897 }
3898 }
3899
hwss_add_hubp_setup_interdependent(struct block_sequence_state * seq_state,struct hubp * hubp,struct _vcs_dpi_display_dlg_regs_st * dlg_regs,struct _vcs_dpi_display_ttu_regs_st * ttu_regs)3900 void hwss_add_hubp_setup_interdependent(struct block_sequence_state *seq_state,
3901 struct hubp *hubp,
3902 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
3903 struct _vcs_dpi_display_ttu_regs_st *ttu_regs)
3904 {
3905 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3906 seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP_INTERDEPENDENT;
3907 seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.hubp = hubp;
3908 seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.dlg_regs = dlg_regs;
3909 seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.ttu_regs = ttu_regs;
3910 (*seq_state->num_steps)++;
3911 }
3912 }
3913
hwss_add_hubp_program_surface_config(struct block_sequence_state * seq_state,struct hubp * hubp,enum surface_pixel_format format,struct dc_tiling_info * tiling_info,struct plane_size plane_size,enum dc_rotation_angle rotation,struct dc_plane_dcc_param * dcc,bool horizontal_mirror,int compat_level)3914 void hwss_add_hubp_program_surface_config(struct block_sequence_state *seq_state,
3915 struct hubp *hubp,
3916 enum surface_pixel_format format,
3917 struct dc_tiling_info *tiling_info,
3918 struct plane_size plane_size,
3919 enum dc_rotation_angle rotation,
3920 struct dc_plane_dcc_param *dcc,
3921 bool horizontal_mirror,
3922 int compat_level)
3923 {
3924 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3925 seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_SURFACE_CONFIG;
3926 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.hubp = hubp;
3927 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.format = format;
3928 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.tiling_info = tiling_info;
3929 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.plane_size = plane_size;
3930 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.rotation = rotation;
3931 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.dcc = dcc;
3932 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.horizontal_mirror = horizontal_mirror;
3933 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.compat_level = compat_level;
3934 (*seq_state->num_steps)++;
3935 }
3936 }
3937
hwss_add_dpp_setup_dpp(struct block_sequence_state * seq_state,struct pipe_ctx * pipe_ctx)3938 void hwss_add_dpp_setup_dpp(struct block_sequence_state *seq_state,
3939 struct pipe_ctx *pipe_ctx)
3940 {
3941 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3942 seq_state->steps[*seq_state->num_steps].func = DPP_SETUP_DPP;
3943 seq_state->steps[*seq_state->num_steps].params.setup_dpp_params.pipe_ctx = pipe_ctx;
3944 (*seq_state->num_steps)++;
3945 }
3946 }
3947
hwss_add_dpp_set_cursor_matrix(struct block_sequence_state * seq_state,struct dpp * dpp,enum dc_color_space color_space,struct dc_csc_transform * cursor_csc_color_matrix)3948 void hwss_add_dpp_set_cursor_matrix(struct block_sequence_state *seq_state,
3949 struct dpp *dpp,
3950 enum dc_color_space color_space,
3951 struct dc_csc_transform *cursor_csc_color_matrix)
3952 {
3953 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3954 seq_state->steps[*seq_state->num_steps].func = DPP_SET_CURSOR_MATRIX;
3955 seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_matrix_params.dpp = dpp;
3956 seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_matrix_params.color_space = color_space;
3957 seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_matrix_params.cursor_csc_color_matrix = cursor_csc_color_matrix;
3958 (*seq_state->num_steps)++;
3959 }
3960 }
3961
hwss_add_dpp_set_scaler(struct block_sequence_state * seq_state,struct dpp * dpp,const struct scaler_data * scl_data)3962 void hwss_add_dpp_set_scaler(struct block_sequence_state *seq_state,
3963 struct dpp *dpp,
3964 const struct scaler_data *scl_data)
3965 {
3966 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3967 seq_state->steps[*seq_state->num_steps].func = DPP_SET_SCALER;
3968 seq_state->steps[*seq_state->num_steps].params.dpp_set_scaler_params.dpp = dpp;
3969 seq_state->steps[*seq_state->num_steps].params.dpp_set_scaler_params.scl_data = scl_data;
3970 (*seq_state->num_steps)++;
3971 }
3972 }
3973
hwss_add_hubp_mem_program_viewport(struct block_sequence_state * seq_state,struct hubp * hubp,const struct rect * viewport,const struct rect * viewport_c)3974 void hwss_add_hubp_mem_program_viewport(struct block_sequence_state *seq_state,
3975 struct hubp *hubp,
3976 const struct rect *viewport,
3977 const struct rect *viewport_c)
3978 {
3979 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3980 seq_state->steps[*seq_state->num_steps].func = HUBP_MEM_PROGRAM_VIEWPORT;
3981 seq_state->steps[*seq_state->num_steps].params.hubp_mem_program_viewport_params.hubp = hubp;
3982 seq_state->steps[*seq_state->num_steps].params.hubp_mem_program_viewport_params.viewport = viewport;
3983 seq_state->steps[*seq_state->num_steps].params.hubp_mem_program_viewport_params.viewport_c = viewport_c;
3984 (*seq_state->num_steps)++;
3985 }
3986 }
3987
hwss_add_abort_cursor_offload_update(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx)3988 void hwss_add_abort_cursor_offload_update(struct block_sequence_state *seq_state,
3989 struct dc *dc,
3990 struct pipe_ctx *pipe_ctx)
3991 {
3992 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3993 seq_state->steps[*seq_state->num_steps].func = ABORT_CURSOR_OFFLOAD_UPDATE;
3994 seq_state->steps[*seq_state->num_steps].params.abort_cursor_offload_update_params.dc = dc;
3995 seq_state->steps[*seq_state->num_steps].params.abort_cursor_offload_update_params.pipe_ctx = pipe_ctx;
3996 (*seq_state->num_steps)++;
3997 }
3998 }
3999
hwss_add_set_cursor_attribute(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx)4000 void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state,
4001 struct dc *dc,
4002 struct pipe_ctx *pipe_ctx)
4003 {
4004 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
4005 seq_state->steps[*seq_state->num_steps].func = SET_CURSOR_ATTRIBUTE;
4006 seq_state->steps[*seq_state->num_steps].params.set_cursor_attribute_params.dc = dc;
4007 seq_state->steps[*seq_state->num_steps].params.set_cursor_attribute_params.pipe_ctx = pipe_ctx;
4008 (*seq_state->num_steps)++;
4009 }
4010 }
4011
hwss_add_set_cursor_position(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx)4012 void hwss_add_set_cursor_position(struct block_sequence_state *seq_state,
4013 struct dc *dc,
4014 struct pipe_ctx *pipe_ctx)
4015 {
4016 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
4017 seq_state->steps[*seq_state->num_steps].func = SET_CURSOR_POSITION;
4018 seq_state->steps[*seq_state->num_steps].params.set_cursor_position_params.dc = dc;
4019 seq_state->steps[*seq_state->num_steps].params.set_cursor_position_params.pipe_ctx = pipe_ctx;
4020 (*seq_state->num_steps)++;
4021 }
4022 }
4023
hwss_add_set_cursor_sdr_white_level(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx)4024 void hwss_add_set_cursor_sdr_white_level(struct block_sequence_state *seq_state,
4025 struct dc *dc,
4026 struct pipe_ctx *pipe_ctx)
4027 {
4028 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
4029 seq_state->steps[*seq_state->num_steps].func = SET_CURSOR_SDR_WHITE_LEVEL;
4030 seq_state->steps[*seq_state->num_steps].params.set_cursor_sdr_white_level_params.dc = dc;
4031 seq_state->steps[*seq_state->num_steps].params.set_cursor_sdr_white_level_params.pipe_ctx = pipe_ctx;
4032 (*seq_state->num_steps)++;
4033 }
4034 }
4035
hwss_add_program_output_csc(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx,enum dc_color_space colorspace,uint16_t * matrix,int opp_id)4036 void hwss_add_program_output_csc(struct block_sequence_state *seq_state,
4037 struct dc *dc,
4038 struct pipe_ctx *pipe_ctx,
4039 enum dc_color_space colorspace,
4040 uint16_t *matrix,
4041 int opp_id)
4042 {
4043 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
4044 seq_state->steps[*seq_state->num_steps].func = PROGRAM_OUTPUT_CSC;
4045 seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.dc = dc;
4046 seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.pipe_ctx = pipe_ctx;
4047 seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.colorspace = colorspace;
4048 seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.matrix = matrix;
4049 seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.opp_id = opp_id;
4050 (*seq_state->num_steps)++;
4051 }
4052 }
4053
hwss_add_phantom_hubp_post_enable(struct block_sequence_state * seq_state,struct hubp * hubp)4054 void hwss_add_phantom_hubp_post_enable(struct block_sequence_state *seq_state,
4055 struct hubp *hubp)
4056 {
4057 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
4058 seq_state->steps[*seq_state->num_steps].func = PHANTOM_HUBP_POST_ENABLE;
4059 seq_state->steps[*seq_state->num_steps].params.phantom_hubp_post_enable_params.hubp = hubp;
4060 (*seq_state->num_steps)++;
4061 }
4062 }
4063
hwss_add_update_force_pstate(struct block_sequence_state * seq_state,struct dc * dc,struct dc_state * context)4064 void hwss_add_update_force_pstate(struct block_sequence_state *seq_state,
4065 struct dc *dc,
4066 struct dc_state *context)
4067 {
4068 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
4069 seq_state->steps[*seq_state->num_steps].func = UPDATE_FORCE_PSTATE;
4070 seq_state->steps[*seq_state->num_steps].params.update_force_pstate_params.dc = dc;
4071 seq_state->steps[*seq_state->num_steps].params.update_force_pstate_params.context = context;
4072 (*seq_state->num_steps)++;
4073 }
4074 }
4075
hwss_add_hubbub_apply_dedcn21_147_wa(struct block_sequence_state * seq_state,struct hubbub * hubbub)4076 void hwss_add_hubbub_apply_dedcn21_147_wa(struct block_sequence_state *seq_state,
4077 struct hubbub *hubbub)
4078 {
4079 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
4080 seq_state->steps[*seq_state->num_steps].func = HUBBUB_APPLY_DEDCN21_147_WA;
4081 seq_state->steps[*seq_state->num_steps].params.hubbub_apply_dedcn21_147_wa_params.hubbub = hubbub;
4082 (*seq_state->num_steps)++;
4083 }
4084 }
4085
hwss_add_hubbub_allow_self_refresh_control(struct block_sequence_state * seq_state,struct hubbub * hubbub,bool allow,bool * disallow_self_refresh_applied)4086 void hwss_add_hubbub_allow_self_refresh_control(struct block_sequence_state *seq_state,
4087 struct hubbub *hubbub,
4088 bool allow,
4089 bool *disallow_self_refresh_applied)
4090 {
4091 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
4092 seq_state->steps[*seq_state->num_steps].func = HUBBUB_ALLOW_SELF_REFRESH_CONTROL;
4093 seq_state->steps[*seq_state->num_steps].params.hubbub_allow_self_refresh_control_params.hubbub = hubbub;
4094 seq_state->steps[*seq_state->num_steps].params.hubbub_allow_self_refresh_control_params.allow = allow;
4095 seq_state->steps[*seq_state->num_steps].params.hubbub_allow_self_refresh_control_params.disallow_self_refresh_applied = disallow_self_refresh_applied;
4096 (*seq_state->num_steps)++;
4097 }
4098 }
4099
hwss_add_tg_get_frame_count(struct block_sequence_state * seq_state,struct timing_generator * tg,unsigned int * frame_count)4100 void hwss_add_tg_get_frame_count(struct block_sequence_state *seq_state,
4101 struct timing_generator *tg,
4102 unsigned int *frame_count)
4103 {
4104 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
4105 seq_state->steps[*seq_state->num_steps].func = TG_GET_FRAME_COUNT;
4106 seq_state->steps[*seq_state->num_steps].params.tg_get_frame_count_params.tg = tg;
4107 seq_state->steps[*seq_state->num_steps].params.tg_get_frame_count_params.frame_count = frame_count;
4108 (*seq_state->num_steps)++;
4109 }
4110 }
4111
4112
get_refresh_rate_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)4113 void get_refresh_rate_confirm_color(struct pipe_ctx *pipe_ctx, struct tg_color *color)
4114 {
4115 uint32_t color_value = MAX_TG_COLOR_VALUE;
4116 unsigned int refresh_rate = 0;
4117 uint32_t scaling_factor = 0;
4118 if (pipe_ctx && pipe_ctx->stream && color) {
4119 refresh_rate = (pipe_ctx->stream->timing.pix_clk_100hz * 100) / (pipe_ctx->stream->adjust.v_total_max * pipe_ctx->stream->timing.h_total);
4120
4121 uint32_t min_refresh_rate = pipe_ctx->stream->timing.min_refresh_in_uhz / 1000000;
4122 uint32_t max_refresh_rate = pipe_ctx->stream->timing.max_refresh_in_uhz / 1000000;
4123
4124 if (max_refresh_rate - min_refresh_rate)
4125 scaling_factor = MAX_TG_COLOR_VALUE * (refresh_rate - min_refresh_rate) / (max_refresh_rate - min_refresh_rate);
4126
4127 pipe_ctx->visual_confirm_color.color_r_cr = color_value;
4128 pipe_ctx->visual_confirm_color.color_g_y = scaling_factor;
4129 pipe_ctx->visual_confirm_color.color_b_cb = color_value;
4130 }
4131 }
4132