1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
4 *
5 * SPEAr13xx PCIe Glue Layer Source Code
6 *
7 * Copyright (C) 2010-2014 ST Microelectronics
8 * Pratyush Anand <pratyush.anand@gmail.com>
9 * Mohit Kumar <mohit.kumar.dhaka@gmail.com>
10 */
11
12 #include <linux/clk.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/of.h>
17 #include <linux/pci.h>
18 #include <linux/phy/phy.h>
19 #include <linux/platform_device.h>
20 #include <linux/resource.h>
21
22 #include "pcie-designware.h"
23
24 struct spear13xx_pcie {
25 struct dw_pcie *pci;
26 void __iomem *app_base;
27 struct phy *phy;
28 struct clk *clk;
29 };
30
31 struct pcie_app_reg {
32 u32 app_ctrl_0; /* cr0 */
33 u32 app_ctrl_1; /* cr1 */
34 u32 app_status_0; /* cr2 */
35 u32 app_status_1; /* cr3 */
36 u32 msg_status; /* cr4 */
37 u32 msg_payload; /* cr5 */
38 u32 int_sts; /* cr6 */
39 u32 int_clr; /* cr7 */
40 u32 int_mask; /* cr8 */
41 u32 mst_bmisc; /* cr9 */
42 u32 phy_ctrl; /* cr10 */
43 u32 phy_status; /* cr11 */
44 u32 cxpl_debug_info_0; /* cr12 */
45 u32 cxpl_debug_info_1; /* cr13 */
46 u32 ven_msg_ctrl_0; /* cr14 */
47 u32 ven_msg_ctrl_1; /* cr15 */
48 u32 ven_msg_data_0; /* cr16 */
49 u32 ven_msg_data_1; /* cr17 */
50 u32 ven_msi_0; /* cr18 */
51 u32 ven_msi_1; /* cr19 */
52 u32 mst_rmisc; /* cr20 */
53 };
54
55 /* CR0 ID */
56 #define APP_LTSSM_ENABLE_ID 3
57 #define DEVICE_TYPE_RC (4 << 25)
58 #define MISCTRL_EN_ID 30
59 #define REG_TRANSLATION_ENABLE 31
60
61 /* CR3 ID */
62 #define XMLH_LINK_UP (1 << 6)
63
64 /* CR6 */
65 #define MSI_CTRL_INT (1 << 26)
66
67 #define to_spear13xx_pcie(x) dev_get_drvdata((x)->dev)
68
spear13xx_pcie_start_link(struct dw_pcie * pci)69 static int spear13xx_pcie_start_link(struct dw_pcie *pci)
70 {
71 struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
72 struct pcie_app_reg __iomem *app_reg = spear13xx_pcie->app_base;
73
74 /* enable ltssm */
75 writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
76 | (1 << APP_LTSSM_ENABLE_ID)
77 | ((u32)1 << REG_TRANSLATION_ENABLE),
78 &app_reg->app_ctrl_0);
79
80 return 0;
81 }
82
spear13xx_pcie_irq_handler(int irq,void * arg)83 static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
84 {
85 struct spear13xx_pcie *spear13xx_pcie = arg;
86 struct pcie_app_reg __iomem *app_reg = spear13xx_pcie->app_base;
87 struct dw_pcie *pci = spear13xx_pcie->pci;
88 struct dw_pcie_rp *pp = &pci->pp;
89 unsigned int status;
90
91 status = readl(&app_reg->int_sts);
92
93 if (status & MSI_CTRL_INT) {
94 BUG_ON(!IS_ENABLED(CONFIG_PCI_MSI));
95 dw_handle_msi_irq(pp);
96 }
97
98 writel(status, &app_reg->int_clr);
99
100 return IRQ_HANDLED;
101 }
102
spear13xx_pcie_enable_interrupts(struct spear13xx_pcie * spear13xx_pcie)103 static void spear13xx_pcie_enable_interrupts(struct spear13xx_pcie *spear13xx_pcie)
104 {
105 struct pcie_app_reg __iomem *app_reg = spear13xx_pcie->app_base;
106
107 /* Enable MSI interrupt */
108 if (IS_ENABLED(CONFIG_PCI_MSI))
109 writel(readl(&app_reg->int_mask) |
110 MSI_CTRL_INT, &app_reg->int_mask);
111 }
112
spear13xx_pcie_link_up(struct dw_pcie * pci)113 static bool spear13xx_pcie_link_up(struct dw_pcie *pci)
114 {
115 struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
116 struct pcie_app_reg __iomem *app_reg = spear13xx_pcie->app_base;
117
118 return readl(&app_reg->app_status_1) & XMLH_LINK_UP;
119 }
120
spear13xx_pcie_host_init(struct dw_pcie_rp * pp)121 static int spear13xx_pcie_host_init(struct dw_pcie_rp *pp)
122 {
123 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
124 struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
125 u32 exp_cap_off = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
126 u32 val;
127
128 spear13xx_pcie->app_base = pci->dbi_base + 0x2000;
129
130 /*
131 * this controller support only 128 bytes read size, however its
132 * default value in capability register is 512 bytes. So force
133 * it to 128 here.
134 */
135 val = dw_pcie_readw_dbi(pci, exp_cap_off + PCI_EXP_DEVCTL);
136 val &= ~PCI_EXP_DEVCTL_READRQ;
137 dw_pcie_writew_dbi(pci, exp_cap_off + PCI_EXP_DEVCTL, val);
138
139 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, 0x104A);
140 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, 0xCD80);
141
142 spear13xx_pcie_enable_interrupts(spear13xx_pcie);
143
144 return 0;
145 }
146
147 static const struct dw_pcie_host_ops spear13xx_pcie_host_ops = {
148 .init = spear13xx_pcie_host_init,
149 };
150
spear13xx_add_pcie_port(struct spear13xx_pcie * spear13xx_pcie,struct platform_device * pdev)151 static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie,
152 struct platform_device *pdev)
153 {
154 struct dw_pcie *pci = spear13xx_pcie->pci;
155 struct dw_pcie_rp *pp = &pci->pp;
156 struct device *dev = &pdev->dev;
157 int ret;
158
159 pp->irq = platform_get_irq(pdev, 0);
160 if (pp->irq < 0)
161 return pp->irq;
162
163 ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
164 IRQF_SHARED | IRQF_NO_THREAD,
165 "spear1340-pcie", spear13xx_pcie);
166 if (ret) {
167 dev_err(dev, "failed to request irq %d\n", pp->irq);
168 return ret;
169 }
170
171 pp->ops = &spear13xx_pcie_host_ops;
172 pp->msi_irq[0] = -ENODEV;
173
174 ret = dw_pcie_host_init(pp);
175 if (ret) {
176 dev_err(dev, "failed to initialize host\n");
177 return ret;
178 }
179
180 return 0;
181 }
182
183 static const struct dw_pcie_ops dw_pcie_ops = {
184 .link_up = spear13xx_pcie_link_up,
185 .start_link = spear13xx_pcie_start_link,
186 };
187
spear13xx_pcie_probe(struct platform_device * pdev)188 static int spear13xx_pcie_probe(struct platform_device *pdev)
189 {
190 struct device *dev = &pdev->dev;
191 struct dw_pcie *pci;
192 struct spear13xx_pcie *spear13xx_pcie;
193 struct device_node *np = dev->of_node;
194 int ret;
195
196 spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
197 if (!spear13xx_pcie)
198 return -ENOMEM;
199
200 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
201 if (!pci)
202 return -ENOMEM;
203
204 pci->dev = dev;
205 pci->ops = &dw_pcie_ops;
206
207 spear13xx_pcie->pci = pci;
208
209 spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
210 if (IS_ERR(spear13xx_pcie->phy)) {
211 ret = PTR_ERR(spear13xx_pcie->phy);
212 if (ret == -EPROBE_DEFER)
213 dev_info(dev, "probe deferred\n");
214 else
215 dev_err(dev, "couldn't get pcie-phy\n");
216 return ret;
217 }
218
219 phy_init(spear13xx_pcie->phy);
220
221 spear13xx_pcie->clk = devm_clk_get(dev, NULL);
222 if (IS_ERR(spear13xx_pcie->clk)) {
223 dev_err(dev, "couldn't get clk for pcie\n");
224 return PTR_ERR(spear13xx_pcie->clk);
225 }
226 ret = clk_prepare_enable(spear13xx_pcie->clk);
227 if (ret) {
228 dev_err(dev, "couldn't enable clk for pcie\n");
229 return ret;
230 }
231
232 if (of_property_read_bool(np, "st,pcie-is-gen1"))
233 pci->max_link_speed = 1;
234
235 platform_set_drvdata(pdev, spear13xx_pcie);
236
237 ret = spear13xx_add_pcie_port(spear13xx_pcie, pdev);
238 if (ret < 0)
239 goto fail_clk;
240
241 return 0;
242
243 fail_clk:
244 clk_disable_unprepare(spear13xx_pcie->clk);
245
246 return ret;
247 }
248
249 static const struct of_device_id spear13xx_pcie_of_match[] = {
250 { .compatible = "st,spear1340-pcie", },
251 {},
252 };
253
254 static struct platform_driver spear13xx_pcie_driver = {
255 .probe = spear13xx_pcie_probe,
256 .driver = {
257 .name = "spear-pcie",
258 .of_match_table = spear13xx_pcie_of_match,
259 .suppress_bind_attrs = true,
260 },
261 };
262
263 builtin_platform_driver(spear13xx_pcie_driver);
264