1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7#include <dt-bindings/interconnect/qcom,icc.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 12#include <dt-bindings/clock/qcom,sa8775p-gcc.h> 13#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 14#include <dt-bindings/clock/qcom,sa8775p-videocc.h> 15#include <dt-bindings/clock/qcom,sa8775p-camcc.h> 16#include <dt-bindings/dma/qcom-gpi.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> 19#include <dt-bindings/mailbox/qcom-ipcc.h> 20#include <dt-bindings/firmware/qcom,scm.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/soc/qcom,gpr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 clocks { 32 xo_board_clk: xo-board-clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 }; 36 37 sleep_clk: sleep-clk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 cpu0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "qcom,kryo"; 50 reg = <0x0 0x0>; 51 enable-method = "psci"; 52 power-domains = <&cpu_pd0>; 53 power-domain-names = "psci"; 54 qcom,freq-domain = <&cpufreq_hw 0>; 55 next-level-cache = <&l2_0>; 56 capacity-dmips-mhz = <1024>; 57 dynamic-power-coefficient = <100>; 58 operating-points-v2 = <&cpu0_opp_table>; 59 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 60 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 61 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 62 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 63 l2_0: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 cache-unified; 67 next-level-cache = <&l3_0>; 68 l3_0: l3-cache { 69 compatible = "cache"; 70 cache-level = <3>; 71 cache-unified; 72 }; 73 }; 74 }; 75 76 cpu1: cpu@100 { 77 device_type = "cpu"; 78 compatible = "qcom,kryo"; 79 reg = <0x0 0x100>; 80 enable-method = "psci"; 81 power-domains = <&cpu_pd1>; 82 power-domain-names = "psci"; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 next-level-cache = <&l2_1>; 85 capacity-dmips-mhz = <1024>; 86 dynamic-power-coefficient = <100>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 89 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 90 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 91 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 92 l2_1: l2-cache { 93 compatible = "cache"; 94 cache-level = <2>; 95 cache-unified; 96 next-level-cache = <&l3_0>; 97 }; 98 }; 99 100 cpu2: cpu@200 { 101 device_type = "cpu"; 102 compatible = "qcom,kryo"; 103 reg = <0x0 0x200>; 104 enable-method = "psci"; 105 power-domains = <&cpu_pd2>; 106 power-domain-names = "psci"; 107 qcom,freq-domain = <&cpufreq_hw 0>; 108 next-level-cache = <&l2_2>; 109 capacity-dmips-mhz = <1024>; 110 dynamic-power-coefficient = <100>; 111 operating-points-v2 = <&cpu0_opp_table>; 112 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 113 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 114 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 115 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 116 l2_2: l2-cache { 117 compatible = "cache"; 118 cache-level = <2>; 119 cache-unified; 120 next-level-cache = <&l3_0>; 121 }; 122 }; 123 124 cpu3: cpu@300 { 125 device_type = "cpu"; 126 compatible = "qcom,kryo"; 127 reg = <0x0 0x300>; 128 enable-method = "psci"; 129 power-domains = <&cpu_pd3>; 130 power-domain-names = "psci"; 131 qcom,freq-domain = <&cpufreq_hw 0>; 132 next-level-cache = <&l2_3>; 133 capacity-dmips-mhz = <1024>; 134 dynamic-power-coefficient = <100>; 135 operating-points-v2 = <&cpu0_opp_table>; 136 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 137 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 138 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 139 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 140 l2_3: l2-cache { 141 compatible = "cache"; 142 cache-level = <2>; 143 cache-unified; 144 next-level-cache = <&l3_0>; 145 }; 146 }; 147 148 cpu4: cpu@10000 { 149 device_type = "cpu"; 150 compatible = "qcom,kryo"; 151 reg = <0x0 0x10000>; 152 enable-method = "psci"; 153 power-domains = <&cpu_pd4>; 154 power-domain-names = "psci"; 155 qcom,freq-domain = <&cpufreq_hw 1>; 156 next-level-cache = <&l2_4>; 157 capacity-dmips-mhz = <1024>; 158 dynamic-power-coefficient = <100>; 159 operating-points-v2 = <&cpu4_opp_table>; 160 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 161 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 162 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 163 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 164 l2_4: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 cache-unified; 168 next-level-cache = <&l3_1>; 169 l3_1: l3-cache { 170 compatible = "cache"; 171 cache-level = <3>; 172 cache-unified; 173 }; 174 175 }; 176 }; 177 178 cpu5: cpu@10100 { 179 device_type = "cpu"; 180 compatible = "qcom,kryo"; 181 reg = <0x0 0x10100>; 182 enable-method = "psci"; 183 power-domains = <&cpu_pd5>; 184 power-domain-names = "psci"; 185 qcom,freq-domain = <&cpufreq_hw 1>; 186 next-level-cache = <&l2_5>; 187 capacity-dmips-mhz = <1024>; 188 dynamic-power-coefficient = <100>; 189 operating-points-v2 = <&cpu4_opp_table>; 190 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 191 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 192 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 193 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 194 l2_5: l2-cache { 195 compatible = "cache"; 196 cache-level = <2>; 197 cache-unified; 198 next-level-cache = <&l3_1>; 199 }; 200 }; 201 202 cpu6: cpu@10200 { 203 device_type = "cpu"; 204 compatible = "qcom,kryo"; 205 reg = <0x0 0x10200>; 206 enable-method = "psci"; 207 power-domains = <&cpu_pd6>; 208 power-domain-names = "psci"; 209 qcom,freq-domain = <&cpufreq_hw 1>; 210 next-level-cache = <&l2_6>; 211 capacity-dmips-mhz = <1024>; 212 dynamic-power-coefficient = <100>; 213 operating-points-v2 = <&cpu4_opp_table>; 214 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 215 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 216 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 217 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 218 l2_6: l2-cache { 219 compatible = "cache"; 220 cache-level = <2>; 221 cache-unified; 222 next-level-cache = <&l3_1>; 223 }; 224 }; 225 226 cpu7: cpu@10300 { 227 device_type = "cpu"; 228 compatible = "qcom,kryo"; 229 reg = <0x0 0x10300>; 230 enable-method = "psci"; 231 power-domains = <&cpu_pd7>; 232 power-domain-names = "psci"; 233 qcom,freq-domain = <&cpufreq_hw 1>; 234 next-level-cache = <&l2_7>; 235 capacity-dmips-mhz = <1024>; 236 dynamic-power-coefficient = <100>; 237 operating-points-v2 = <&cpu4_opp_table>; 238 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 239 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 240 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 241 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 242 l2_7: l2-cache { 243 compatible = "cache"; 244 cache-level = <2>; 245 cache-unified; 246 next-level-cache = <&l3_1>; 247 }; 248 }; 249 250 cpu-map { 251 cluster0 { 252 core0 { 253 cpu = <&cpu0>; 254 }; 255 256 core1 { 257 cpu = <&cpu1>; 258 }; 259 260 core2 { 261 cpu = <&cpu2>; 262 }; 263 264 core3 { 265 cpu = <&cpu3>; 266 }; 267 }; 268 269 cluster1 { 270 core0 { 271 cpu = <&cpu4>; 272 }; 273 274 core1 { 275 cpu = <&cpu5>; 276 }; 277 278 core2 { 279 cpu = <&cpu6>; 280 }; 281 282 core3 { 283 cpu = <&cpu7>; 284 }; 285 }; 286 }; 287 288 idle-states { 289 entry-method = "psci"; 290 291 gold_cpu_sleep_0: cpu-sleep-0 { 292 compatible = "arm,idle-state"; 293 idle-state-name = "gold-power-collapse"; 294 arm,psci-suspend-param = <0x40000003>; 295 entry-latency-us = <549>; 296 exit-latency-us = <901>; 297 min-residency-us = <1774>; 298 local-timer-stop; 299 }; 300 301 gold_rail_cpu_sleep_0: cpu-sleep-1 { 302 compatible = "arm,idle-state"; 303 idle-state-name = "gold-rail-power-collapse"; 304 arm,psci-suspend-param = <0x40000004>; 305 entry-latency-us = <702>; 306 exit-latency-us = <1061>; 307 min-residency-us = <4488>; 308 local-timer-stop; 309 }; 310 }; 311 312 domain-idle-states { 313 cluster_sleep_gold: cluster-sleep-0 { 314 compatible = "domain-idle-state"; 315 arm,psci-suspend-param = <0x41000044>; 316 entry-latency-us = <2752>; 317 exit-latency-us = <3048>; 318 min-residency-us = <6118>; 319 }; 320 321 cluster_sleep_apss_rsc_pc: cluster-sleep-1 { 322 compatible = "domain-idle-state"; 323 arm,psci-suspend-param = <0x42000144>; 324 entry-latency-us = <3263>; 325 exit-latency-us = <6562>; 326 min-residency-us = <9987>; 327 }; 328 }; 329 }; 330 331 cpu0_opp_table: opp-table-cpu0 { 332 compatible = "operating-points-v2"; 333 opp-shared; 334 335 opp-1267200000 { 336 opp-hz = /bits/ 64 <1267200000>; 337 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 338 }; 339 340 opp-1363200000 { 341 opp-hz = /bits/ 64 <1363200000>; 342 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 343 }; 344 345 opp-1459200000 { 346 opp-hz = /bits/ 64 <1459200000>; 347 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 348 }; 349 350 opp-1536000000 { 351 opp-hz = /bits/ 64 <1536000000>; 352 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 353 }; 354 355 opp-1632000000 { 356 opp-hz = /bits/ 64 <1632000000>; 357 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 358 }; 359 360 opp-1708800000 { 361 opp-hz = /bits/ 64 <1708800000>; 362 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 363 }; 364 365 opp-1785600000 { 366 opp-hz = /bits/ 64 <1785600000>; 367 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 368 }; 369 370 opp-1862400000 { 371 opp-hz = /bits/ 64 <1862400000>; 372 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 373 }; 374 375 opp-1939200000 { 376 opp-hz = /bits/ 64 <1939200000>; 377 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 378 }; 379 380 opp-2016000000 { 381 opp-hz = /bits/ 64 <2016000000>; 382 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 383 }; 384 385 opp-2112000000 { 386 opp-hz = /bits/ 64 <2112000000>; 387 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 388 }; 389 390 opp-2188800000 { 391 opp-hz = /bits/ 64 <2188800000>; 392 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 393 }; 394 395 opp-2265600000 { 396 opp-hz = /bits/ 64 <2265600000>; 397 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 398 }; 399 400 opp-2361600000 { 401 opp-hz = /bits/ 64 <2361600000>; 402 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 403 }; 404 405 opp-2457600000 { 406 opp-hz = /bits/ 64 <2457600000>; 407 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 408 }; 409 410 opp-2553600000 { 411 opp-hz = /bits/ 64 <2553600000>; 412 opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>; 413 }; 414 }; 415 416 cpu4_opp_table: opp-table-cpu4 { 417 compatible = "operating-points-v2"; 418 opp-shared; 419 420 opp-1267200000 { 421 opp-hz = /bits/ 64 <1267200000>; 422 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 423 }; 424 425 opp-1363200000 { 426 opp-hz = /bits/ 64 <1363200000>; 427 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 428 }; 429 430 opp-1459200000 { 431 opp-hz = /bits/ 64 <1459200000>; 432 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 433 }; 434 435 opp-1536000000 { 436 opp-hz = /bits/ 64 <1536000000>; 437 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 438 }; 439 440 opp-1632000000 { 441 opp-hz = /bits/ 64 <1632000000>; 442 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 443 }; 444 445 opp-1708800000 { 446 opp-hz = /bits/ 64 <1708800000>; 447 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 448 }; 449 450 opp-1785600000 { 451 opp-hz = /bits/ 64 <1785600000>; 452 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 453 }; 454 455 opp-1862400000 { 456 opp-hz = /bits/ 64 <1862400000>; 457 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 458 }; 459 460 opp-1939200000 { 461 opp-hz = /bits/ 64 <1939200000>; 462 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 463 }; 464 465 opp-2016000000 { 466 opp-hz = /bits/ 64 <2016000000>; 467 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 468 }; 469 470 opp-2112000000 { 471 opp-hz = /bits/ 64 <2112000000>; 472 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 473 }; 474 475 opp-2188800000 { 476 opp-hz = /bits/ 64 <2188800000>; 477 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 478 }; 479 480 opp-2265600000 { 481 opp-hz = /bits/ 64 <2265600000>; 482 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 483 }; 484 485 opp-2361600000 { 486 opp-hz = /bits/ 64 <2361600000>; 487 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 488 }; 489 490 opp-2457600000 { 491 opp-hz = /bits/ 64 <2457600000>; 492 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 493 }; 494 495 opp-2553600000 { 496 opp-hz = /bits/ 64 <2553600000>; 497 opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>; 498 }; 499 }; 500 501 dummy-sink { 502 compatible = "arm,coresight-dummy-sink"; 503 504 in-ports { 505 port { 506 eud_in: endpoint { 507 remote-endpoint = 508 <&swao_rep_out1>; 509 }; 510 }; 511 }; 512 }; 513 514 firmware { 515 scm { 516 compatible = "qcom,scm-sa8775p", "qcom,scm"; 517 qcom,dload-mode = <&tcsr 0x13000>; 518 }; 519 }; 520 521 aggre1_noc: interconnect-aggre1-noc { 522 compatible = "qcom,sa8775p-aggre1-noc"; 523 #interconnect-cells = <2>; 524 qcom,bcm-voters = <&apps_bcm_voter>; 525 }; 526 527 aggre2_noc: interconnect-aggre2-noc { 528 compatible = "qcom,sa8775p-aggre2-noc"; 529 #interconnect-cells = <2>; 530 qcom,bcm-voters = <&apps_bcm_voter>; 531 }; 532 533 clk_virt: interconnect-clk-virt { 534 compatible = "qcom,sa8775p-clk-virt"; 535 #interconnect-cells = <2>; 536 qcom,bcm-voters = <&apps_bcm_voter>; 537 }; 538 539 config_noc: interconnect-config-noc { 540 compatible = "qcom,sa8775p-config-noc"; 541 #interconnect-cells = <2>; 542 qcom,bcm-voters = <&apps_bcm_voter>; 543 }; 544 545 dc_noc: interconnect-dc-noc { 546 compatible = "qcom,sa8775p-dc-noc"; 547 #interconnect-cells = <2>; 548 qcom,bcm-voters = <&apps_bcm_voter>; 549 }; 550 551 gem_noc: interconnect-gem-noc { 552 compatible = "qcom,sa8775p-gem-noc"; 553 #interconnect-cells = <2>; 554 qcom,bcm-voters = <&apps_bcm_voter>; 555 }; 556 557 gpdsp_anoc: interconnect-gpdsp-anoc { 558 compatible = "qcom,sa8775p-gpdsp-anoc"; 559 #interconnect-cells = <2>; 560 qcom,bcm-voters = <&apps_bcm_voter>; 561 }; 562 563 lpass_ag_noc: interconnect-lpass-ag-noc { 564 compatible = "qcom,sa8775p-lpass-ag-noc"; 565 #interconnect-cells = <2>; 566 qcom,bcm-voters = <&apps_bcm_voter>; 567 }; 568 569 mc_virt: interconnect-mc-virt { 570 compatible = "qcom,sa8775p-mc-virt"; 571 #interconnect-cells = <2>; 572 qcom,bcm-voters = <&apps_bcm_voter>; 573 }; 574 575 mmss_noc: interconnect-mmss-noc { 576 compatible = "qcom,sa8775p-mmss-noc"; 577 #interconnect-cells = <2>; 578 qcom,bcm-voters = <&apps_bcm_voter>; 579 }; 580 581 nspa_noc: interconnect-nspa-noc { 582 compatible = "qcom,sa8775p-nspa-noc"; 583 #interconnect-cells = <2>; 584 qcom,bcm-voters = <&apps_bcm_voter>; 585 }; 586 587 nspb_noc: interconnect-nspb-noc { 588 compatible = "qcom,sa8775p-nspb-noc"; 589 #interconnect-cells = <2>; 590 qcom,bcm-voters = <&apps_bcm_voter>; 591 }; 592 593 pcie_anoc: interconnect-pcie-anoc { 594 compatible = "qcom,sa8775p-pcie-anoc"; 595 #interconnect-cells = <2>; 596 qcom,bcm-voters = <&apps_bcm_voter>; 597 }; 598 599 system_noc: interconnect-system-noc { 600 compatible = "qcom,sa8775p-system-noc"; 601 #interconnect-cells = <2>; 602 qcom,bcm-voters = <&apps_bcm_voter>; 603 }; 604 605 /* Will be updated by the bootloader. */ 606 memory@80000000 { 607 device_type = "memory"; 608 reg = <0x0 0x80000000 0x0 0x0>; 609 }; 610 611 qup_opp_table_100mhz: opp-table-qup100mhz { 612 compatible = "operating-points-v2"; 613 614 opp-100000000 { 615 opp-hz = /bits/ 64 <100000000>; 616 required-opps = <&rpmhpd_opp_svs_l1>; 617 }; 618 }; 619 620 pmu { 621 compatible = "arm,armv8-pmuv3"; 622 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 623 }; 624 625 psci { 626 compatible = "arm,psci-1.0"; 627 method = "smc"; 628 629 cpu_pd0: power-domain-cpu0 { 630 #power-domain-cells = <0>; 631 power-domains = <&cluster_0_pd>; 632 domain-idle-states = <&gold_cpu_sleep_0>, 633 <&gold_rail_cpu_sleep_0>; 634 }; 635 636 cpu_pd1: power-domain-cpu1 { 637 #power-domain-cells = <0>; 638 power-domains = <&cluster_0_pd>; 639 domain-idle-states = <&gold_cpu_sleep_0>, 640 <&gold_rail_cpu_sleep_0>; 641 }; 642 643 cpu_pd2: power-domain-cpu2 { 644 #power-domain-cells = <0>; 645 power-domains = <&cluster_0_pd>; 646 domain-idle-states = <&gold_cpu_sleep_0>, 647 <&gold_rail_cpu_sleep_0>; 648 }; 649 650 cpu_pd3: power-domain-cpu3 { 651 #power-domain-cells = <0>; 652 power-domains = <&cluster_0_pd>; 653 domain-idle-states = <&gold_cpu_sleep_0>, 654 <&gold_rail_cpu_sleep_0>; 655 }; 656 657 cpu_pd4: power-domain-cpu4 { 658 #power-domain-cells = <0>; 659 power-domains = <&cluster_1_pd>; 660 domain-idle-states = <&gold_cpu_sleep_0>, 661 <&gold_rail_cpu_sleep_0>; 662 }; 663 664 cpu_pd5: power-domain-cpu5 { 665 #power-domain-cells = <0>; 666 power-domains = <&cluster_1_pd>; 667 domain-idle-states = <&gold_cpu_sleep_0>, 668 <&gold_rail_cpu_sleep_0>; 669 }; 670 671 cpu_pd6: power-domain-cpu6 { 672 #power-domain-cells = <0>; 673 power-domains = <&cluster_1_pd>; 674 domain-idle-states = <&gold_cpu_sleep_0>, 675 <&gold_rail_cpu_sleep_0>; 676 }; 677 678 cpu_pd7: power-domain-cpu7 { 679 #power-domain-cells = <0>; 680 power-domains = <&cluster_1_pd>; 681 domain-idle-states = <&gold_cpu_sleep_0>, 682 <&gold_rail_cpu_sleep_0>; 683 }; 684 685 cluster_0_pd: power-domain-cluster0 { 686 #power-domain-cells = <0>; 687 domain-idle-states = <&cluster_sleep_gold>; 688 power-domains = <&system_pd>; 689 }; 690 691 cluster_1_pd: power-domain-cluster1 { 692 #power-domain-cells = <0>; 693 domain-idle-states = <&cluster_sleep_gold>; 694 power-domains = <&system_pd>; 695 }; 696 697 system_pd: power-domain-system { 698 #power-domain-cells = <0>; 699 domain-idle-states = <&cluster_sleep_apss_rsc_pc>; 700 }; 701 }; 702 703 reserved-memory { 704 #address-cells = <2>; 705 #size-cells = <2>; 706 ranges; 707 708 sail_ss_mem: sail-ss@80000000 { 709 reg = <0x0 0x80000000 0x0 0x10000000>; 710 no-map; 711 }; 712 713 hyp_mem: hyp@90000000 { 714 reg = <0x0 0x90000000 0x0 0x600000>; 715 no-map; 716 }; 717 718 xbl_boot_mem: xbl-boot@90600000 { 719 reg = <0x0 0x90600000 0x0 0x200000>; 720 no-map; 721 }; 722 723 aop_image_mem: aop-image@90800000 { 724 reg = <0x0 0x90800000 0x0 0x60000>; 725 no-map; 726 }; 727 728 aop_cmd_db_mem: aop-cmd-db@90860000 { 729 compatible = "qcom,cmd-db"; 730 reg = <0x0 0x90860000 0x0 0x20000>; 731 no-map; 732 }; 733 734 uefi_log: uefi-log@908b0000 { 735 reg = <0x0 0x908b0000 0x0 0x10000>; 736 no-map; 737 }; 738 739 ddr_training_checksum: ddr-training-checksum@908c0000 { 740 reg = <0x0 0x908c0000 0x0 0x1000>; 741 no-map; 742 }; 743 744 reserved_mem: reserved@908f0000 { 745 reg = <0x0 0x908f0000 0x0 0xe000>; 746 no-map; 747 }; 748 749 secdata_apss_mem: secdata-apss@908fe000 { 750 reg = <0x0 0x908fe000 0x0 0x2000>; 751 no-map; 752 }; 753 754 smem_mem: smem@90900000 { 755 compatible = "qcom,smem"; 756 reg = <0x0 0x90900000 0x0 0x200000>; 757 no-map; 758 hwlocks = <&tcsr_mutex 3>; 759 }; 760 761 tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { 762 reg = <0x0 0x90c00000 0x0 0x100000>; 763 no-map; 764 }; 765 766 sail_mailbox_mem: sail-ss@90d00000 { 767 reg = <0x0 0x90d00000 0x0 0x100000>; 768 no-map; 769 }; 770 771 sail_ota_mem: sail-ss@90e00000 { 772 reg = <0x0 0x90e00000 0x0 0x300000>; 773 no-map; 774 }; 775 776 gunyah_md_mem: gunyah-md@91a80000 { 777 reg = <0x0 0x91a80000 0x0 0x80000>; 778 no-map; 779 }; 780 781 aoss_backup_mem: aoss-backup@91b00000 { 782 reg = <0x0 0x91b00000 0x0 0x40000>; 783 no-map; 784 }; 785 786 cpucp_backup_mem: cpucp-backup@91b40000 { 787 reg = <0x0 0x91b40000 0x0 0x40000>; 788 no-map; 789 }; 790 791 tz_config_backup_mem: tz-config-backup@91b80000 { 792 reg = <0x0 0x91b80000 0x0 0x10000>; 793 no-map; 794 }; 795 796 ddr_training_data_mem: ddr-training-data@91b90000 { 797 reg = <0x0 0x91b90000 0x0 0x10000>; 798 no-map; 799 }; 800 801 cdt_data_backup_mem: cdt-data-backup@91ba0000 { 802 reg = <0x0 0x91ba0000 0x0 0x1000>; 803 no-map; 804 }; 805 806 lpass_machine_learning_mem: lpass-machine-learning@93b00000 { 807 reg = <0x0 0x93b00000 0x0 0xf00000>; 808 no-map; 809 }; 810 811 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { 812 reg = <0x0 0x94a00000 0x0 0x800000>; 813 no-map; 814 }; 815 816 pil_camera_mem: pil-camera@95200000 { 817 reg = <0x0 0x95200000 0x0 0x700000>; 818 no-map; 819 }; 820 821 pil_adsp_mem: pil-adsp@95900000 { 822 reg = <0x0 0x95900000 0x0 0x1e00000>; 823 no-map; 824 }; 825 826 q6_adsp_dtb_mem: q6-adsp-dtb@97700000 { 827 reg = <0x0 0x97700000 0x0 0x80000>; 828 no-map; 829 }; 830 831 q6_gdsp0_dtb_mem: q6-gdsp0-dtb@97780000 { 832 reg = <0x0 0x97780000 0x0 0x80000>; 833 no-map; 834 }; 835 836 pil_gdsp0_mem: pil-gdsp0@97800000 { 837 reg = <0x0 0x97800000 0x0 0x1e00000>; 838 no-map; 839 }; 840 841 pil_gdsp1_mem: pil-gdsp1@99600000 { 842 reg = <0x0 0x99600000 0x0 0x1e00000>; 843 no-map; 844 }; 845 846 q6_gdsp1_dtb_mem: q6-gdsp1-dtb@9b400000 { 847 reg = <0x0 0x9b400000 0x0 0x80000>; 848 no-map; 849 }; 850 851 q6_cdsp0_dtb_mem: q6-cdsp0-dtb@9b480000 { 852 reg = <0x0 0x9b480000 0x0 0x80000>; 853 no-map; 854 }; 855 856 pil_cdsp0_mem: pil-cdsp0@9b500000 { 857 reg = <0x0 0x9b500000 0x0 0x1e00000>; 858 no-map; 859 }; 860 861 pil_gpu_mem: pil-gpu@9d300000 { 862 reg = <0x0 0x9d300000 0x0 0x2000>; 863 no-map; 864 }; 865 866 q6_cdsp1_dtb_mem: q6-cdsp1-dtb@9d380000 { 867 reg = <0x0 0x9d380000 0x0 0x80000>; 868 no-map; 869 }; 870 871 pil_cdsp1_mem: pil-cdsp1@9d400000 { 872 reg = <0x0 0x9d400000 0x0 0x1e00000>; 873 no-map; 874 }; 875 876 pil_cvp_mem: pil-cvp@9f200000 { 877 reg = <0x0 0x9f200000 0x0 0x700000>; 878 no-map; 879 }; 880 881 pil_video_mem: pil-video@9f900000 { 882 reg = <0x0 0x9f900000 0x0 0x1000000>; 883 no-map; 884 }; 885 886 firmware_mem: firmware-region@b0000000 { 887 reg = <0x0 0xb0000000 0x0 0x800000>; 888 no-map; 889 }; 890 891 scmi_mem: scmi-region@d0000000 { 892 reg = <0x0 0xd0000000 0x0 0x40000>; 893 no-map; 894 }; 895 896 firmware_logs_mem: firmware-logs@d0040000 { 897 reg = <0x0 0xd0040000 0x0 0x10000>; 898 no-map; 899 }; 900 901 firmware_audio_mem: firmware-audio@d0050000 { 902 reg = <0x0 0xd0050000 0x0 0x4000>; 903 no-map; 904 }; 905 906 firmware_reserved_mem: firmware-reserved@d0054000 { 907 reg = <0x0 0xd0054000 0x0 0x9c000>; 908 no-map; 909 }; 910 911 firmware_quantum_test_mem: firmware-quantum-test@d00f0000 { 912 reg = <0x0 0xd00f0000 0x0 0x10000>; 913 no-map; 914 }; 915 916 tags_mem: tags@d0100000 { 917 reg = <0x0 0xd0100000 0x0 0x1200000>; 918 no-map; 919 }; 920 921 qtee_mem: qtee@d1300000 { 922 reg = <0x0 0xd1300000 0x0 0x500000>; 923 no-map; 924 }; 925 926 deepsleep_backup_mem: deepsleep-backup@d1800000 { 927 reg = <0x0 0xd1800000 0x0 0x100000>; 928 no-map; 929 }; 930 931 trusted_apps_mem: trusted-apps@d1900000 { 932 reg = <0x0 0xd1900000 0x0 0x1c00000>; 933 no-map; 934 }; 935 936 tz_stat_mem: tz-stat@db100000 { 937 reg = <0x0 0xdb100000 0x0 0x100000>; 938 no-map; 939 }; 940 941 cpucp_fw_mem: cpucp-fw@db200000 { 942 reg = <0x0 0xdb200000 0x0 0x100000>; 943 no-map; 944 }; 945 }; 946 947 smp2p-adsp { 948 compatible = "qcom,smp2p"; 949 qcom,smem = <443>, <429>; 950 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 951 IPCC_MPROC_SIGNAL_SMP2P 952 IRQ_TYPE_EDGE_RISING>; 953 mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>; 954 955 qcom,local-pid = <0>; 956 qcom,remote-pid = <2>; 957 958 smp2p_adsp_out: master-kernel { 959 qcom,entry-name = "master-kernel"; 960 #qcom,smem-state-cells = <1>; 961 }; 962 963 smp2p_adsp_in: slave-kernel { 964 qcom,entry-name = "slave-kernel"; 965 interrupt-controller; 966 #interrupt-cells = <2>; 967 }; 968 }; 969 970 smp2p-cdsp0 { 971 compatible = "qcom,smp2p"; 972 qcom,smem = <94>, <432>; 973 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 974 IPCC_MPROC_SIGNAL_SMP2P 975 IRQ_TYPE_EDGE_RISING>; 976 mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; 977 978 qcom,local-pid = <0>; 979 qcom,remote-pid = <5>; 980 981 smp2p_cdsp0_out: master-kernel { 982 qcom,entry-name = "master-kernel"; 983 #qcom,smem-state-cells = <1>; 984 }; 985 986 smp2p_cdsp0_in: slave-kernel { 987 qcom,entry-name = "slave-kernel"; 988 interrupt-controller; 989 #interrupt-cells = <2>; 990 }; 991 }; 992 993 smp2p-cdsp1 { 994 compatible = "qcom,smp2p"; 995 qcom,smem = <617>, <616>; 996 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 997 IPCC_MPROC_SIGNAL_SMP2P 998 IRQ_TYPE_EDGE_RISING>; 999 mboxes = <&ipcc IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_SMP2P>; 1000 1001 qcom,local-pid = <0>; 1002 qcom,remote-pid = <12>; 1003 1004 smp2p_cdsp1_out: master-kernel { 1005 qcom,entry-name = "master-kernel"; 1006 #qcom,smem-state-cells = <1>; 1007 }; 1008 1009 smp2p_cdsp1_in: slave-kernel { 1010 qcom,entry-name = "slave-kernel"; 1011 interrupt-controller; 1012 #interrupt-cells = <2>; 1013 }; 1014 }; 1015 1016 smp2p-gpdsp0 { 1017 compatible = "qcom,smp2p"; 1018 qcom,smem = <617>, <616>; 1019 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 1020 IPCC_MPROC_SIGNAL_SMP2P 1021 IRQ_TYPE_EDGE_RISING>; 1022 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_SMP2P>; 1023 1024 qcom,local-pid = <0>; 1025 qcom,remote-pid = <17>; 1026 1027 smp2p_gpdsp0_out: master-kernel { 1028 qcom,entry-name = "master-kernel"; 1029 #qcom,smem-state-cells = <1>; 1030 }; 1031 1032 smp2p_gpdsp0_in: slave-kernel { 1033 qcom,entry-name = "slave-kernel"; 1034 interrupt-controller; 1035 #interrupt-cells = <2>; 1036 }; 1037 }; 1038 1039 smp2p-gpdsp1 { 1040 compatible = "qcom,smp2p"; 1041 qcom,smem = <617>, <616>; 1042 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 1043 IPCC_MPROC_SIGNAL_SMP2P 1044 IRQ_TYPE_EDGE_RISING>; 1045 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 IPCC_MPROC_SIGNAL_SMP2P>; 1046 1047 qcom,local-pid = <0>; 1048 qcom,remote-pid = <18>; 1049 1050 smp2p_gpdsp1_out: master-kernel { 1051 qcom,entry-name = "master-kernel"; 1052 #qcom,smem-state-cells = <1>; 1053 }; 1054 1055 smp2p_gpdsp1_in: slave-kernel { 1056 qcom,entry-name = "slave-kernel"; 1057 interrupt-controller; 1058 #interrupt-cells = <2>; 1059 }; 1060 }; 1061 1062 soc: soc@0 { 1063 compatible = "simple-bus"; 1064 #address-cells = <2>; 1065 #size-cells = <2>; 1066 ranges = <0 0 0 0 0x10 0>; 1067 1068 gcc: clock-controller@100000 { 1069 compatible = "qcom,sa8775p-gcc"; 1070 reg = <0x0 0x00100000 0x0 0xc7018>; 1071 #clock-cells = <1>; 1072 #reset-cells = <1>; 1073 #power-domain-cells = <1>; 1074 clocks = <&rpmhcc RPMH_CXO_CLK>, 1075 <&sleep_clk>, 1076 <0>, 1077 <0>, 1078 <0>, 1079 <&usb_0_qmpphy>, 1080 <&usb_1_qmpphy>, 1081 <0>, 1082 <0>, 1083 <0>, 1084 <&pcie0_phy>, 1085 <&pcie1_phy>, 1086 <0>, 1087 <0>, 1088 <0>; 1089 power-domains = <&rpmhpd SA8775P_CX>; 1090 }; 1091 1092 ipcc: mailbox@408000 { 1093 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; 1094 reg = <0x0 0x00408000 0x0 0x1000>; 1095 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1096 interrupt-controller; 1097 #interrupt-cells = <3>; 1098 #mbox-cells = <2>; 1099 }; 1100 1101 gpi_dma2: dma-controller@800000 { 1102 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 1103 reg = <0x0 0x00800000 0x0 0x60000>; 1104 #dma-cells = <3>; 1105 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 1117 dma-channels = <12>; 1118 dma-channel-mask = <0xfff>; 1119 iommus = <&apps_smmu 0x5b6 0x0>; 1120 status = "disabled"; 1121 }; 1122 1123 qupv3_id_2: geniqup@8c0000 { 1124 compatible = "qcom,geni-se-qup"; 1125 reg = <0x0 0x008c0000 0x0 0x6000>; 1126 ranges; 1127 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1128 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1129 clock-names = "m-ahb", "s-ahb"; 1130 iommus = <&apps_smmu 0x5a3 0x0>; 1131 #address-cells = <2>; 1132 #size-cells = <2>; 1133 status = "disabled"; 1134 1135 i2c14: i2c@880000 { 1136 compatible = "qcom,geni-i2c"; 1137 reg = <0x0 0x880000 0x0 0x4000>; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1141 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1142 clock-names = "se"; 1143 pinctrl-0 = <&qup_i2c14_default>; 1144 pinctrl-names = "default"; 1145 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1146 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1147 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1148 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1149 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1150 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1151 interconnect-names = "qup-core", 1152 "qup-config", 1153 "qup-memory"; 1154 power-domains = <&rpmhpd SA8775P_CX>; 1155 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1156 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1157 dma-names = "tx", 1158 "rx"; 1159 status = "disabled"; 1160 }; 1161 1162 spi14: spi@880000 { 1163 compatible = "qcom,geni-spi"; 1164 reg = <0x0 0x880000 0x0 0x4000>; 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1168 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1169 clock-names = "se"; 1170 pinctrl-0 = <&qup_spi14_default>; 1171 pinctrl-names = "default"; 1172 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1173 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1174 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1175 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1176 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1177 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1178 interconnect-names = "qup-core", 1179 "qup-config", 1180 "qup-memory"; 1181 power-domains = <&rpmhpd SA8775P_CX>; 1182 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1183 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1184 dma-names = "tx", 1185 "rx"; 1186 status = "disabled"; 1187 }; 1188 1189 uart14: serial@880000 { 1190 compatible = "qcom,geni-uart"; 1191 reg = <0x0 0x00880000 0x0 0x4000>; 1192 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1193 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1194 clock-names = "se"; 1195 pinctrl-0 = <&qup_uart14_default>; 1196 pinctrl-names = "default"; 1197 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1198 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1199 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1200 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1201 interconnect-names = "qup-core", "qup-config"; 1202 power-domains = <&rpmhpd SA8775P_CX>; 1203 status = "disabled"; 1204 }; 1205 1206 i2c15: i2c@884000 { 1207 compatible = "qcom,geni-i2c"; 1208 reg = <0x0 0x884000 0x0 0x4000>; 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1212 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1213 clock-names = "se"; 1214 pinctrl-0 = <&qup_i2c15_default>; 1215 pinctrl-names = "default"; 1216 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1217 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1218 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1219 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1220 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1221 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1222 interconnect-names = "qup-core", 1223 "qup-config", 1224 "qup-memory"; 1225 power-domains = <&rpmhpd SA8775P_CX>; 1226 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1227 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1228 dma-names = "tx", 1229 "rx"; 1230 status = "disabled"; 1231 }; 1232 1233 spi15: spi@884000 { 1234 compatible = "qcom,geni-spi"; 1235 reg = <0x0 0x884000 0x0 0x4000>; 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1239 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1240 clock-names = "se"; 1241 pinctrl-0 = <&qup_spi15_default>; 1242 pinctrl-names = "default"; 1243 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1244 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1245 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1246 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1247 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1248 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1249 interconnect-names = "qup-core", 1250 "qup-config", 1251 "qup-memory"; 1252 power-domains = <&rpmhpd SA8775P_CX>; 1253 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1254 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1255 dma-names = "tx", 1256 "rx"; 1257 status = "disabled"; 1258 }; 1259 1260 uart15: serial@884000 { 1261 compatible = "qcom,geni-uart"; 1262 reg = <0x0 0x00884000 0x0 0x4000>; 1263 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1264 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1265 clock-names = "se"; 1266 pinctrl-0 = <&qup_uart15_default>; 1267 pinctrl-names = "default"; 1268 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1269 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1270 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1271 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1272 interconnect-names = "qup-core", "qup-config"; 1273 power-domains = <&rpmhpd SA8775P_CX>; 1274 status = "disabled"; 1275 }; 1276 1277 i2c16: i2c@888000 { 1278 compatible = "qcom,geni-i2c"; 1279 reg = <0x0 0x888000 0x0 0x4000>; 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1283 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1284 clock-names = "se"; 1285 pinctrl-0 = <&qup_i2c16_default>; 1286 pinctrl-names = "default"; 1287 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1288 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1289 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1290 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1291 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1292 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1293 interconnect-names = "qup-core", 1294 "qup-config", 1295 "qup-memory"; 1296 power-domains = <&rpmhpd SA8775P_CX>; 1297 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1298 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1299 dma-names = "tx", 1300 "rx"; 1301 status = "disabled"; 1302 }; 1303 1304 spi16: spi@888000 { 1305 compatible = "qcom,geni-spi"; 1306 reg = <0x0 0x00888000 0x0 0x4000>; 1307 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1308 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1309 clock-names = "se"; 1310 pinctrl-0 = <&qup_spi16_default>; 1311 pinctrl-names = "default"; 1312 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1313 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1314 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1315 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1316 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1317 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1318 interconnect-names = "qup-core", 1319 "qup-config", 1320 "qup-memory"; 1321 power-domains = <&rpmhpd SA8775P_CX>; 1322 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1323 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1324 dma-names = "tx", 1325 "rx"; 1326 #address-cells = <1>; 1327 #size-cells = <0>; 1328 status = "disabled"; 1329 }; 1330 1331 uart16: serial@888000 { 1332 compatible = "qcom,geni-uart"; 1333 reg = <0x0 0x00888000 0x0 0x4000>; 1334 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1335 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1336 clock-names = "se"; 1337 pinctrl-0 = <&qup_uart16_default>; 1338 pinctrl-names = "default"; 1339 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1340 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1341 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1342 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1343 interconnect-names = "qup-core", "qup-config"; 1344 power-domains = <&rpmhpd SA8775P_CX>; 1345 status = "disabled"; 1346 }; 1347 1348 i2c17: i2c@88c000 { 1349 compatible = "qcom,geni-i2c"; 1350 reg = <0x0 0x88c000 0x0 0x4000>; 1351 #address-cells = <1>; 1352 #size-cells = <0>; 1353 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1354 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1355 clock-names = "se"; 1356 pinctrl-0 = <&qup_i2c17_default>; 1357 pinctrl-names = "default"; 1358 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1359 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1360 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1361 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1362 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1363 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1364 interconnect-names = "qup-core", 1365 "qup-config", 1366 "qup-memory"; 1367 power-domains = <&rpmhpd SA8775P_CX>; 1368 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1369 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1370 dma-names = "tx", 1371 "rx"; 1372 status = "disabled"; 1373 }; 1374 1375 spi17: spi@88c000 { 1376 compatible = "qcom,geni-spi"; 1377 reg = <0x0 0x88c000 0x0 0x4000>; 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1381 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1382 clock-names = "se"; 1383 pinctrl-0 = <&qup_spi17_default>; 1384 pinctrl-names = "default"; 1385 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1386 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1387 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1388 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1389 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1390 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1391 interconnect-names = "qup-core", 1392 "qup-config", 1393 "qup-memory"; 1394 power-domains = <&rpmhpd SA8775P_CX>; 1395 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1396 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1397 dma-names = "tx", 1398 "rx"; 1399 status = "disabled"; 1400 }; 1401 1402 uart17: serial@88c000 { 1403 compatible = "qcom,geni-uart"; 1404 reg = <0x0 0x0088c000 0x0 0x4000>; 1405 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1406 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1407 clock-names = "se"; 1408 pinctrl-0 = <&qup_uart17_default>; 1409 pinctrl-names = "default"; 1410 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1411 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1412 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1413 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1414 interconnect-names = "qup-core", "qup-config"; 1415 power-domains = <&rpmhpd SA8775P_CX>; 1416 status = "disabled"; 1417 }; 1418 1419 i2c18: i2c@890000 { 1420 compatible = "qcom,geni-i2c"; 1421 reg = <0x0 0x00890000 0x0 0x4000>; 1422 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1423 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1424 clock-names = "se"; 1425 pinctrl-0 = <&qup_i2c18_default>; 1426 pinctrl-names = "default"; 1427 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1428 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1429 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1430 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1431 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1432 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1433 interconnect-names = "qup-core", 1434 "qup-config", 1435 "qup-memory"; 1436 power-domains = <&rpmhpd SA8775P_CX>; 1437 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1438 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1439 dma-names = "tx", 1440 "rx"; 1441 #address-cells = <1>; 1442 #size-cells = <0>; 1443 status = "disabled"; 1444 }; 1445 1446 spi18: spi@890000 { 1447 compatible = "qcom,geni-spi"; 1448 reg = <0x0 0x890000 0x0 0x4000>; 1449 #address-cells = <1>; 1450 #size-cells = <0>; 1451 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1452 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1453 clock-names = "se"; 1454 pinctrl-0 = <&qup_spi18_default>; 1455 pinctrl-names = "default"; 1456 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1457 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1458 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1459 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1460 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1461 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1462 interconnect-names = "qup-core", 1463 "qup-config", 1464 "qup-memory"; 1465 power-domains = <&rpmhpd SA8775P_CX>; 1466 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1467 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1468 dma-names = "tx", 1469 "rx"; 1470 status = "disabled"; 1471 }; 1472 1473 uart18: serial@890000 { 1474 compatible = "qcom,geni-uart"; 1475 reg = <0x0 0x00890000 0x0 0x4000>; 1476 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1477 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1478 clock-names = "se"; 1479 pinctrl-0 = <&qup_uart18_default>; 1480 pinctrl-names = "default"; 1481 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1482 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1483 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1484 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1485 interconnect-names = "qup-core", "qup-config"; 1486 power-domains = <&rpmhpd SA8775P_CX>; 1487 status = "disabled"; 1488 }; 1489 1490 i2c19: i2c@894000 { 1491 compatible = "qcom,geni-i2c"; 1492 reg = <0x0 0x894000 0x0 0x4000>; 1493 #address-cells = <1>; 1494 #size-cells = <0>; 1495 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1496 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1497 clock-names = "se"; 1498 pinctrl-0 = <&qup_i2c19_default>; 1499 pinctrl-names = "default"; 1500 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1501 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1502 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1503 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1504 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1505 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1506 interconnect-names = "qup-core", 1507 "qup-config", 1508 "qup-memory"; 1509 power-domains = <&rpmhpd SA8775P_CX>; 1510 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1511 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1512 dma-names = "tx", 1513 "rx"; 1514 status = "disabled"; 1515 }; 1516 1517 spi19: spi@894000 { 1518 compatible = "qcom,geni-spi"; 1519 reg = <0x0 0x894000 0x0 0x4000>; 1520 #address-cells = <1>; 1521 #size-cells = <0>; 1522 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1523 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1524 clock-names = "se"; 1525 pinctrl-0 = <&qup_spi19_default>; 1526 pinctrl-names = "default"; 1527 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1528 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1529 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1530 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1531 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1532 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1533 interconnect-names = "qup-core", 1534 "qup-config", 1535 "qup-memory"; 1536 power-domains = <&rpmhpd SA8775P_CX>; 1537 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1538 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1539 dma-names = "tx", 1540 "rx"; 1541 status = "disabled"; 1542 }; 1543 1544 uart19: serial@894000 { 1545 compatible = "qcom,geni-uart"; 1546 reg = <0x0 0x00894000 0x0 0x4000>; 1547 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1548 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1549 clock-names = "se"; 1550 pinctrl-0 = <&qup_uart19_default>; 1551 pinctrl-names = "default"; 1552 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1553 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1554 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1555 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1556 interconnect-names = "qup-core", "qup-config"; 1557 power-domains = <&rpmhpd SA8775P_CX>; 1558 status = "disabled"; 1559 }; 1560 1561 i2c20: i2c@898000 { 1562 compatible = "qcom,geni-i2c"; 1563 reg = <0x0 0x898000 0x0 0x4000>; 1564 #address-cells = <1>; 1565 #size-cells = <0>; 1566 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1567 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1568 clock-names = "se"; 1569 pinctrl-0 = <&qup_i2c20_default>; 1570 pinctrl-names = "default"; 1571 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1572 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1573 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1574 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1575 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1576 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1577 interconnect-names = "qup-core", 1578 "qup-config", 1579 "qup-memory"; 1580 power-domains = <&rpmhpd SA8775P_CX>; 1581 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1582 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1583 dma-names = "tx", 1584 "rx"; 1585 status = "disabled"; 1586 }; 1587 1588 spi20: spi@898000 { 1589 compatible = "qcom,geni-spi"; 1590 reg = <0x0 0x898000 0x0 0x4000>; 1591 #address-cells = <1>; 1592 #size-cells = <0>; 1593 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1594 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1595 clock-names = "se"; 1596 pinctrl-0 = <&qup_spi20_default>; 1597 pinctrl-names = "default"; 1598 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1599 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1600 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1601 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1602 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1603 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1604 interconnect-names = "qup-core", 1605 "qup-config", 1606 "qup-memory"; 1607 power-domains = <&rpmhpd SA8775P_CX>; 1608 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1609 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1610 dma-names = "tx", 1611 "rx"; 1612 status = "disabled"; 1613 }; 1614 1615 uart20: serial@898000 { 1616 compatible = "qcom,geni-uart"; 1617 reg = <0x0 0x00898000 0x0 0x4000>; 1618 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1619 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1620 clock-names = "se"; 1621 pinctrl-0 = <&qup_uart20_default>; 1622 pinctrl-names = "default"; 1623 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1624 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1625 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1626 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1627 interconnect-names = "qup-core", "qup-config"; 1628 power-domains = <&rpmhpd SA8775P_CX>; 1629 status = "disabled"; 1630 }; 1631 1632 }; 1633 1634 gpi_dma0: dma-controller@900000 { 1635 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 1636 reg = <0x0 0x00900000 0x0 0x60000>; 1637 #dma-cells = <3>; 1638 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1650 dma-channels = <12>; 1651 dma-channel-mask = <0xfff>; 1652 iommus = <&apps_smmu 0x416 0x0>; 1653 status = "disabled"; 1654 }; 1655 1656 qupv3_id_0: geniqup@9c0000 { 1657 compatible = "qcom,geni-se-qup"; 1658 reg = <0x0 0x9c0000 0x0 0x6000>; 1659 #address-cells = <2>; 1660 #size-cells = <2>; 1661 ranges; 1662 clock-names = "m-ahb", "s-ahb"; 1663 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1664 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1665 iommus = <&apps_smmu 0x403 0x0>; 1666 status = "disabled"; 1667 1668 i2c0: i2c@980000 { 1669 compatible = "qcom,geni-i2c"; 1670 reg = <0x0 0x980000 0x0 0x4000>; 1671 #address-cells = <1>; 1672 #size-cells = <0>; 1673 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1674 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1675 clock-names = "se"; 1676 pinctrl-0 = <&qup_i2c0_default>; 1677 pinctrl-names = "default"; 1678 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1679 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1680 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1681 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1682 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1683 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1684 interconnect-names = "qup-core", 1685 "qup-config", 1686 "qup-memory"; 1687 power-domains = <&rpmhpd SA8775P_CX>; 1688 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1689 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1690 dma-names = "tx", 1691 "rx"; 1692 status = "disabled"; 1693 }; 1694 1695 spi0: spi@980000 { 1696 compatible = "qcom,geni-spi"; 1697 reg = <0x0 0x980000 0x0 0x4000>; 1698 #address-cells = <1>; 1699 #size-cells = <0>; 1700 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1701 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1702 clock-names = "se"; 1703 pinctrl-0 = <&qup_spi0_default>; 1704 pinctrl-names = "default"; 1705 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1706 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1707 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1708 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1709 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1710 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1711 interconnect-names = "qup-core", 1712 "qup-config", 1713 "qup-memory"; 1714 power-domains = <&rpmhpd SA8775P_CX>; 1715 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1716 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1717 dma-names = "tx", 1718 "rx"; 1719 status = "disabled"; 1720 }; 1721 1722 uart0: serial@980000 { 1723 compatible = "qcom,geni-uart"; 1724 reg = <0x0 0x980000 0x0 0x4000>; 1725 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1726 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1727 clock-names = "se"; 1728 pinctrl-0 = <&qup_uart0_default>; 1729 pinctrl-names = "default"; 1730 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1731 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1732 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1733 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1734 interconnect-names = "qup-core", "qup-config"; 1735 power-domains = <&rpmhpd SA8775P_CX>; 1736 status = "disabled"; 1737 }; 1738 1739 i2c1: i2c@984000 { 1740 compatible = "qcom,geni-i2c"; 1741 reg = <0x0 0x984000 0x0 0x4000>; 1742 #address-cells = <1>; 1743 #size-cells = <0>; 1744 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1745 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1746 clock-names = "se"; 1747 pinctrl-0 = <&qup_i2c1_default>; 1748 pinctrl-names = "default"; 1749 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1750 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1751 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1752 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1753 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1754 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1755 interconnect-names = "qup-core", 1756 "qup-config", 1757 "qup-memory"; 1758 power-domains = <&rpmhpd SA8775P_CX>; 1759 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1760 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1761 dma-names = "tx", 1762 "rx"; 1763 status = "disabled"; 1764 }; 1765 1766 spi1: spi@984000 { 1767 compatible = "qcom,geni-spi"; 1768 reg = <0x0 0x984000 0x0 0x4000>; 1769 #address-cells = <1>; 1770 #size-cells = <0>; 1771 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1772 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1773 clock-names = "se"; 1774 pinctrl-0 = <&qup_spi1_default>; 1775 pinctrl-names = "default"; 1776 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1777 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1778 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1779 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1780 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1781 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1782 interconnect-names = "qup-core", 1783 "qup-config", 1784 "qup-memory"; 1785 power-domains = <&rpmhpd SA8775P_CX>; 1786 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1787 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1788 dma-names = "tx", 1789 "rx"; 1790 status = "disabled"; 1791 }; 1792 1793 uart1: serial@984000 { 1794 compatible = "qcom,geni-uart"; 1795 reg = <0x0 0x984000 0x0 0x4000>; 1796 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1797 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1798 clock-names = "se"; 1799 pinctrl-0 = <&qup_uart1_default>; 1800 pinctrl-names = "default"; 1801 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1802 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1803 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1804 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1805 interconnect-names = "qup-core", "qup-config"; 1806 power-domains = <&rpmhpd SA8775P_CX>; 1807 status = "disabled"; 1808 }; 1809 1810 i2c2: i2c@988000 { 1811 compatible = "qcom,geni-i2c"; 1812 reg = <0x0 0x988000 0x0 0x4000>; 1813 #address-cells = <1>; 1814 #size-cells = <0>; 1815 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1816 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1817 clock-names = "se"; 1818 pinctrl-0 = <&qup_i2c2_default>; 1819 pinctrl-names = "default"; 1820 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1821 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1822 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1823 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1824 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1825 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1826 interconnect-names = "qup-core", 1827 "qup-config", 1828 "qup-memory"; 1829 power-domains = <&rpmhpd SA8775P_CX>; 1830 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1831 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1832 dma-names = "tx", 1833 "rx"; 1834 status = "disabled"; 1835 }; 1836 1837 spi2: spi@988000 { 1838 compatible = "qcom,geni-spi"; 1839 reg = <0x0 0x988000 0x0 0x4000>; 1840 #address-cells = <1>; 1841 #size-cells = <0>; 1842 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1843 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1844 clock-names = "se"; 1845 pinctrl-0 = <&qup_spi2_default>; 1846 pinctrl-names = "default"; 1847 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1848 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1849 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1850 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1851 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1852 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1853 interconnect-names = "qup-core", 1854 "qup-config", 1855 "qup-memory"; 1856 power-domains = <&rpmhpd SA8775P_CX>; 1857 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1858 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1859 dma-names = "tx", 1860 "rx"; 1861 status = "disabled"; 1862 }; 1863 1864 uart2: serial@988000 { 1865 compatible = "qcom,geni-uart"; 1866 reg = <0x0 0x988000 0x0 0x4000>; 1867 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1868 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1869 clock-names = "se"; 1870 pinctrl-0 = <&qup_uart2_default>; 1871 pinctrl-names = "default"; 1872 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1873 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1874 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1875 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1876 interconnect-names = "qup-core", "qup-config"; 1877 power-domains = <&rpmhpd SA8775P_CX>; 1878 status = "disabled"; 1879 }; 1880 1881 i2c3: i2c@98c000 { 1882 compatible = "qcom,geni-i2c"; 1883 reg = <0x0 0x98c000 0x0 0x4000>; 1884 #address-cells = <1>; 1885 #size-cells = <0>; 1886 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1887 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1888 clock-names = "se"; 1889 pinctrl-0 = <&qup_i2c3_default>; 1890 pinctrl-names = "default"; 1891 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1892 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1893 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1894 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1895 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1896 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1897 interconnect-names = "qup-core", 1898 "qup-config", 1899 "qup-memory"; 1900 power-domains = <&rpmhpd SA8775P_CX>; 1901 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1902 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1903 dma-names = "tx", 1904 "rx"; 1905 status = "disabled"; 1906 }; 1907 1908 spi3: spi@98c000 { 1909 compatible = "qcom,geni-spi"; 1910 reg = <0x0 0x98c000 0x0 0x4000>; 1911 #address-cells = <1>; 1912 #size-cells = <0>; 1913 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1914 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1915 clock-names = "se"; 1916 pinctrl-0 = <&qup_spi3_default>; 1917 pinctrl-names = "default"; 1918 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1919 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1920 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1921 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1922 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1923 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1924 interconnect-names = "qup-core", 1925 "qup-config", 1926 "qup-memory"; 1927 power-domains = <&rpmhpd SA8775P_CX>; 1928 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1929 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1930 dma-names = "tx", 1931 "rx"; 1932 status = "disabled"; 1933 }; 1934 1935 uart3: serial@98c000 { 1936 compatible = "qcom,geni-uart"; 1937 reg = <0x0 0x98c000 0x0 0x4000>; 1938 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1939 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1940 clock-names = "se"; 1941 pinctrl-0 = <&qup_uart3_default>; 1942 pinctrl-names = "default"; 1943 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1944 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1945 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1946 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1947 interconnect-names = "qup-core", "qup-config"; 1948 power-domains = <&rpmhpd SA8775P_CX>; 1949 status = "disabled"; 1950 }; 1951 1952 i2c4: i2c@990000 { 1953 compatible = "qcom,geni-i2c"; 1954 reg = <0x0 0x990000 0x0 0x4000>; 1955 #address-cells = <1>; 1956 #size-cells = <0>; 1957 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1958 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1959 clock-names = "se"; 1960 pinctrl-0 = <&qup_i2c4_default>; 1961 pinctrl-names = "default"; 1962 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1963 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1964 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1965 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1966 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1967 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1968 interconnect-names = "qup-core", 1969 "qup-config", 1970 "qup-memory"; 1971 power-domains = <&rpmhpd SA8775P_CX>; 1972 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1973 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1974 dma-names = "tx", 1975 "rx"; 1976 status = "disabled"; 1977 }; 1978 1979 spi4: spi@990000 { 1980 compatible = "qcom,geni-spi"; 1981 reg = <0x0 0x990000 0x0 0x4000>; 1982 #address-cells = <1>; 1983 #size-cells = <0>; 1984 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1985 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1986 clock-names = "se"; 1987 pinctrl-0 = <&qup_spi4_default>; 1988 pinctrl-names = "default"; 1989 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1990 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1991 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1992 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1993 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1994 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1995 interconnect-names = "qup-core", 1996 "qup-config", 1997 "qup-memory"; 1998 power-domains = <&rpmhpd SA8775P_CX>; 1999 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2000 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2001 dma-names = "tx", 2002 "rx"; 2003 status = "disabled"; 2004 }; 2005 2006 uart4: serial@990000 { 2007 compatible = "qcom,geni-uart"; 2008 reg = <0x0 0x990000 0x0 0x4000>; 2009 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 2010 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2011 clock-names = "se"; 2012 pinctrl-0 = <&qup_uart4_default>; 2013 pinctrl-names = "default"; 2014 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2015 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2016 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2017 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 2018 interconnect-names = "qup-core", "qup-config"; 2019 power-domains = <&rpmhpd SA8775P_CX>; 2020 status = "disabled"; 2021 }; 2022 2023 i2c5: i2c@994000 { 2024 compatible = "qcom,geni-i2c"; 2025 reg = <0x0 0x994000 0x0 0x4000>; 2026 #address-cells = <1>; 2027 #size-cells = <0>; 2028 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 2029 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2030 clock-names = "se"; 2031 pinctrl-0 = <&qup_i2c5_default>; 2032 pinctrl-names = "default"; 2033 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2034 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2035 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2036 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2037 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2038 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2039 interconnect-names = "qup-core", 2040 "qup-config", 2041 "qup-memory"; 2042 power-domains = <&rpmhpd SA8775P_CX>; 2043 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2044 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2045 dma-names = "tx", 2046 "rx"; 2047 status = "disabled"; 2048 }; 2049 2050 spi5: spi@994000 { 2051 compatible = "qcom,geni-spi"; 2052 reg = <0x0 0x994000 0x0 0x4000>; 2053 #address-cells = <1>; 2054 #size-cells = <0>; 2055 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 2056 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2057 clock-names = "se"; 2058 pinctrl-0 = <&qup_spi5_default>; 2059 pinctrl-names = "default"; 2060 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2061 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2062 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2063 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2064 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2065 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2066 interconnect-names = "qup-core", 2067 "qup-config", 2068 "qup-memory"; 2069 power-domains = <&rpmhpd SA8775P_CX>; 2070 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2071 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2072 dma-names = "tx", 2073 "rx"; 2074 status = "disabled"; 2075 }; 2076 2077 uart5: serial@994000 { 2078 compatible = "qcom,geni-uart"; 2079 reg = <0x0 0x994000 0x0 0x4000>; 2080 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 2081 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2082 clock-names = "se"; 2083 pinctrl-0 = <&qup_uart5_default>; 2084 pinctrl-names = "default"; 2085 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2086 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2087 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2088 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 2089 interconnect-names = "qup-core", "qup-config"; 2090 power-domains = <&rpmhpd SA8775P_CX>; 2091 status = "disabled"; 2092 }; 2093 }; 2094 2095 gpi_dma1: dma-controller@a00000 { 2096 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 2097 reg = <0x0 0x00a00000 0x0 0x60000>; 2098 #dma-cells = <3>; 2099 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 2100 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2111 iommus = <&apps_smmu 0x456 0x0>; 2112 dma-channels = <12>; 2113 dma-channel-mask = <0xfff>; 2114 status = "disabled"; 2115 }; 2116 2117 qupv3_id_1: geniqup@ac0000 { 2118 compatible = "qcom,geni-se-qup"; 2119 reg = <0x0 0x00ac0000 0x0 0x6000>; 2120 #address-cells = <2>; 2121 #size-cells = <2>; 2122 ranges; 2123 clock-names = "m-ahb", "s-ahb"; 2124 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 2125 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 2126 iommus = <&apps_smmu 0x443 0x0>; 2127 status = "disabled"; 2128 2129 i2c7: i2c@a80000 { 2130 compatible = "qcom,geni-i2c"; 2131 reg = <0x0 0xa80000 0x0 0x4000>; 2132 #address-cells = <1>; 2133 #size-cells = <0>; 2134 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2135 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2136 clock-names = "se"; 2137 pinctrl-0 = <&qup_i2c7_default>; 2138 pinctrl-names = "default"; 2139 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2140 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2141 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2142 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2143 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2144 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2145 interconnect-names = "qup-core", 2146 "qup-config", 2147 "qup-memory"; 2148 power-domains = <&rpmhpd SA8775P_CX>; 2149 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 2150 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 2151 dma-names = "tx", 2152 "rx"; 2153 status = "disabled"; 2154 }; 2155 2156 spi7: spi@a80000 { 2157 compatible = "qcom,geni-spi"; 2158 reg = <0x0 0xa80000 0x0 0x4000>; 2159 #address-cells = <1>; 2160 #size-cells = <0>; 2161 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2162 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2163 clock-names = "se"; 2164 pinctrl-0 = <&qup_spi7_default>; 2165 pinctrl-names = "default"; 2166 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2167 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2168 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2169 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2170 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2171 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2172 interconnect-names = "qup-core", 2173 "qup-config", 2174 "qup-memory"; 2175 power-domains = <&rpmhpd SA8775P_CX>; 2176 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 2177 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 2178 dma-names = "tx", 2179 "rx"; 2180 status = "disabled"; 2181 }; 2182 2183 uart7: serial@a80000 { 2184 compatible = "qcom,geni-uart"; 2185 reg = <0x0 0x00a80000 0x0 0x4000>; 2186 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2187 clock-names = "se"; 2188 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2189 pinctrl-0 = <&qup_uart7_default>; 2190 pinctrl-names = "default"; 2191 interconnect-names = "qup-core", "qup-config"; 2192 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2193 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2194 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2195 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2196 power-domains = <&rpmhpd SA8775P_CX>; 2197 operating-points-v2 = <&qup_opp_table_100mhz>; 2198 status = "disabled"; 2199 }; 2200 2201 i2c8: i2c@a84000 { 2202 compatible = "qcom,geni-i2c"; 2203 reg = <0x0 0xa84000 0x0 0x4000>; 2204 #address-cells = <1>; 2205 #size-cells = <0>; 2206 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2207 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2208 clock-names = "se"; 2209 pinctrl-0 = <&qup_i2c8_default>; 2210 pinctrl-names = "default"; 2211 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2212 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2213 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2214 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2215 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2216 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2217 interconnect-names = "qup-core", 2218 "qup-config", 2219 "qup-memory"; 2220 power-domains = <&rpmhpd SA8775P_CX>; 2221 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 2222 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 2223 dma-names = "tx", 2224 "rx"; 2225 status = "disabled"; 2226 }; 2227 2228 spi8: spi@a84000 { 2229 compatible = "qcom,geni-spi"; 2230 reg = <0x0 0xa84000 0x0 0x4000>; 2231 #address-cells = <1>; 2232 #size-cells = <0>; 2233 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2234 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2235 clock-names = "se"; 2236 pinctrl-0 = <&qup_spi8_default>; 2237 pinctrl-names = "default"; 2238 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2239 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2240 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2241 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2242 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2243 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2244 interconnect-names = "qup-core", 2245 "qup-config", 2246 "qup-memory"; 2247 power-domains = <&rpmhpd SA8775P_CX>; 2248 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 2249 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 2250 dma-names = "tx", 2251 "rx"; 2252 status = "disabled"; 2253 }; 2254 2255 uart8: serial@a84000 { 2256 compatible = "qcom,geni-uart"; 2257 reg = <0x0 0x00a84000 0x0 0x4000>; 2258 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2259 clock-names = "se"; 2260 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2261 pinctrl-0 = <&qup_uart8_default>; 2262 pinctrl-names = "default"; 2263 interconnect-names = "qup-core", "qup-config"; 2264 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2265 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2266 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2267 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2268 power-domains = <&rpmhpd SA8775P_CX>; 2269 operating-points-v2 = <&qup_opp_table_100mhz>; 2270 status = "disabled"; 2271 }; 2272 2273 i2c9: i2c@a88000 { 2274 compatible = "qcom,geni-i2c"; 2275 reg = <0x0 0xa88000 0x0 0x4000>; 2276 #address-cells = <1>; 2277 #size-cells = <0>; 2278 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2279 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 2280 clock-names = "se"; 2281 pinctrl-0 = <&qup_i2c9_default>; 2282 pinctrl-names = "default"; 2283 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2284 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2285 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2286 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2287 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2288 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2289 interconnect-names = "qup-core", 2290 "qup-config", 2291 "qup-memory"; 2292 power-domains = <&rpmhpd SA8775P_CX>; 2293 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 2294 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 2295 dma-names = "tx", 2296 "rx"; 2297 status = "disabled"; 2298 }; 2299 2300 spi9: spi@a88000 { 2301 compatible = "qcom,geni-spi"; 2302 reg = <0x0 0xa88000 0x0 0x4000>; 2303 #address-cells = <1>; 2304 #size-cells = <0>; 2305 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2306 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 2307 clock-names = "se"; 2308 pinctrl-0 = <&qup_spi9_default>; 2309 pinctrl-names = "default"; 2310 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2311 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2312 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2313 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2314 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2315 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2316 interconnect-names = "qup-core", 2317 "qup-config", 2318 "qup-memory"; 2319 power-domains = <&rpmhpd SA8775P_CX>; 2320 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 2321 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 2322 dma-names = "tx", 2323 "rx"; 2324 status = "disabled"; 2325 }; 2326 2327 uart9: serial@a88000 { 2328 compatible = "qcom,geni-uart"; 2329 reg = <0x0 0xa88000 0x0 0x4000>; 2330 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2331 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 2332 clock-names = "se"; 2333 pinctrl-0 = <&qup_uart9_default>; 2334 pinctrl-names = "default"; 2335 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2336 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2337 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2338 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2339 interconnect-names = "qup-core", "qup-config"; 2340 power-domains = <&rpmhpd SA8775P_CX>; 2341 status = "disabled"; 2342 }; 2343 2344 i2c10: i2c@a8c000 { 2345 compatible = "qcom,geni-i2c"; 2346 reg = <0x0 0xa8c000 0x0 0x4000>; 2347 #address-cells = <1>; 2348 #size-cells = <0>; 2349 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2350 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2351 clock-names = "se"; 2352 pinctrl-0 = <&qup_i2c10_default>; 2353 pinctrl-names = "default"; 2354 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2355 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2356 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2357 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2358 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2359 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2360 interconnect-names = "qup-core", 2361 "qup-config", 2362 "qup-memory"; 2363 power-domains = <&rpmhpd SA8775P_CX>; 2364 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 2365 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 2366 dma-names = "tx", 2367 "rx"; 2368 status = "disabled"; 2369 }; 2370 2371 spi10: spi@a8c000 { 2372 compatible = "qcom,geni-spi"; 2373 reg = <0x0 0xa8c000 0x0 0x4000>; 2374 #address-cells = <1>; 2375 #size-cells = <0>; 2376 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2377 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2378 clock-names = "se"; 2379 pinctrl-0 = <&qup_spi10_default>; 2380 pinctrl-names = "default"; 2381 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2382 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2383 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2384 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2385 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2386 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2387 interconnect-names = "qup-core", 2388 "qup-config", 2389 "qup-memory"; 2390 power-domains = <&rpmhpd SA8775P_CX>; 2391 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 2392 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 2393 dma-names = "tx", 2394 "rx"; 2395 status = "disabled"; 2396 }; 2397 2398 uart10: serial@a8c000 { 2399 compatible = "qcom,geni-uart"; 2400 reg = <0x0 0x00a8c000 0x0 0x4000>; 2401 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2402 clock-names = "se"; 2403 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2404 pinctrl-0 = <&qup_uart10_default>; 2405 pinctrl-names = "default"; 2406 interconnect-names = "qup-core", "qup-config"; 2407 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 2408 &clk_virt SLAVE_QUP_CORE_1 0>, 2409 <&gem_noc MASTER_APPSS_PROC 0 2410 &config_noc SLAVE_QUP_1 0>; 2411 power-domains = <&rpmhpd SA8775P_CX>; 2412 operating-points-v2 = <&qup_opp_table_100mhz>; 2413 status = "disabled"; 2414 }; 2415 2416 i2c11: i2c@a90000 { 2417 compatible = "qcom,geni-i2c"; 2418 reg = <0x0 0xa90000 0x0 0x4000>; 2419 #address-cells = <1>; 2420 #size-cells = <0>; 2421 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2422 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2423 clock-names = "se"; 2424 pinctrl-0 = <&qup_i2c11_default>; 2425 pinctrl-names = "default"; 2426 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2427 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2428 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2429 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2430 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2431 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2432 interconnect-names = "qup-core", 2433 "qup-config", 2434 "qup-memory"; 2435 power-domains = <&rpmhpd SA8775P_CX>; 2436 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 2437 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 2438 dma-names = "tx", 2439 "rx"; 2440 status = "disabled"; 2441 }; 2442 2443 spi11: spi@a90000 { 2444 compatible = "qcom,geni-spi"; 2445 reg = <0x0 0xa90000 0x0 0x4000>; 2446 #address-cells = <1>; 2447 #size-cells = <0>; 2448 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2449 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2450 clock-names = "se"; 2451 pinctrl-0 = <&qup_spi11_default>; 2452 pinctrl-names = "default"; 2453 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2454 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2455 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2456 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2457 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2458 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2459 interconnect-names = "qup-core", 2460 "qup-config", 2461 "qup-memory"; 2462 power-domains = <&rpmhpd SA8775P_CX>; 2463 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2464 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2465 dma-names = "tx", 2466 "rx"; 2467 status = "disabled"; 2468 }; 2469 2470 uart11: serial@a90000 { 2471 compatible = "qcom,geni-uart"; 2472 reg = <0x0 0x00a90000 0x0 0x4000>; 2473 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2474 clock-names = "se"; 2475 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2476 pinctrl-0 = <&qup_uart11_default>; 2477 pinctrl-names = "default"; 2478 interconnect-names = "qup-core", "qup-config"; 2479 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2480 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2481 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2482 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2483 power-domains = <&rpmhpd SA8775P_CX>; 2484 operating-points-v2 = <&qup_opp_table_100mhz>; 2485 status = "disabled"; 2486 }; 2487 2488 i2c12: i2c@a94000 { 2489 compatible = "qcom,geni-i2c"; 2490 reg = <0x0 0xa94000 0x0 0x4000>; 2491 #address-cells = <1>; 2492 #size-cells = <0>; 2493 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2494 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2495 clock-names = "se"; 2496 pinctrl-0 = <&qup_i2c12_default>; 2497 pinctrl-names = "default"; 2498 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2499 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2500 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2501 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2502 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2503 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2504 interconnect-names = "qup-core", 2505 "qup-config", 2506 "qup-memory"; 2507 power-domains = <&rpmhpd SA8775P_CX>; 2508 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2509 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2510 dma-names = "tx", 2511 "rx"; 2512 status = "disabled"; 2513 }; 2514 2515 spi12: spi@a94000 { 2516 compatible = "qcom,geni-spi"; 2517 reg = <0x0 0xa94000 0x0 0x4000>; 2518 #address-cells = <1>; 2519 #size-cells = <0>; 2520 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2521 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2522 clock-names = "se"; 2523 pinctrl-0 = <&qup_spi12_default>; 2524 pinctrl-names = "default"; 2525 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2526 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2527 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2528 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2529 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2530 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2531 interconnect-names = "qup-core", 2532 "qup-config", 2533 "qup-memory"; 2534 power-domains = <&rpmhpd SA8775P_CX>; 2535 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2536 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2537 dma-names = "tx", 2538 "rx"; 2539 status = "disabled"; 2540 }; 2541 2542 uart12: serial@a94000 { 2543 compatible = "qcom,geni-uart"; 2544 reg = <0x0 0x00a94000 0x0 0x4000>; 2545 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2546 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2547 clock-names = "se"; 2548 pinctrl-0 = <&qup_uart12_default>; 2549 pinctrl-names = "default"; 2550 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2551 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2552 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2553 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2554 interconnect-names = "qup-core", "qup-config"; 2555 power-domains = <&rpmhpd SA8775P_CX>; 2556 status = "disabled"; 2557 }; 2558 2559 i2c13: i2c@a98000 { 2560 compatible = "qcom,geni-i2c"; 2561 reg = <0x0 0xa98000 0x0 0x4000>; 2562 #address-cells = <1>; 2563 #size-cells = <0>; 2564 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 2565 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2566 clock-names = "se"; 2567 pinctrl-0 = <&qup_i2c13_default>; 2568 pinctrl-names = "default"; 2569 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2570 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2571 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2572 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2573 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2574 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2575 interconnect-names = "qup-core", 2576 "qup-config", 2577 "qup-memory"; 2578 power-domains = <&rpmhpd SA8775P_CX>; 2579 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2580 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2581 dma-names = "tx", 2582 "rx"; 2583 status = "disabled"; 2584 2585 }; 2586 }; 2587 2588 gpi_dma3: dma-controller@b00000 { 2589 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 2590 reg = <0x0 0x00b00000 0x0 0x58000>; 2591 #dma-cells = <3>; 2592 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2593 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 2594 <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 2595 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>; 2596 iommus = <&apps_smmu 0x056 0x0>; 2597 dma-channels = <4>; 2598 dma-channel-mask = <0xf>; 2599 status = "disabled"; 2600 }; 2601 2602 qupv3_id_3: geniqup@bc0000 { 2603 compatible = "qcom,geni-se-qup"; 2604 reg = <0x0 0xbc0000 0x0 0x6000>; 2605 #address-cells = <2>; 2606 #size-cells = <2>; 2607 ranges; 2608 clock-names = "m-ahb", "s-ahb"; 2609 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 2610 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 2611 iommus = <&apps_smmu 0x43 0x0>; 2612 status = "disabled"; 2613 2614 i2c21: i2c@b80000 { 2615 compatible = "qcom,geni-i2c"; 2616 reg = <0x0 0xb80000 0x0 0x4000>; 2617 #address-cells = <1>; 2618 #size-cells = <0>; 2619 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2620 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2621 clock-names = "se"; 2622 pinctrl-0 = <&qup_i2c21_default>; 2623 pinctrl-names = "default"; 2624 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2625 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2626 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2627 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2628 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2629 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2630 interconnect-names = "qup-core", 2631 "qup-config", 2632 "qup-memory"; 2633 power-domains = <&rpmhpd SA8775P_CX>; 2634 dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, 2635 <&gpi_dma3 1 0 QCOM_GPI_I2C>; 2636 dma-names = "tx", 2637 "rx"; 2638 status = "disabled"; 2639 }; 2640 2641 spi21: spi@b80000 { 2642 compatible = "qcom,geni-spi"; 2643 reg = <0x0 0xb80000 0x0 0x4000>; 2644 #address-cells = <1>; 2645 #size-cells = <0>; 2646 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2647 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2648 clock-names = "se"; 2649 pinctrl-0 = <&qup_spi21_default>; 2650 pinctrl-names = "default"; 2651 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2652 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2653 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2654 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2655 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2656 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2657 interconnect-names = "qup-core", 2658 "qup-config", 2659 "qup-memory"; 2660 power-domains = <&rpmhpd SA8775P_CX>; 2661 dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>, 2662 <&gpi_dma3 1 0 QCOM_GPI_SPI>; 2663 dma-names = "tx", 2664 "rx"; 2665 status = "disabled"; 2666 }; 2667 2668 uart21: serial@b80000 { 2669 compatible = "qcom,geni-uart"; 2670 reg = <0x0 0x00b80000 0x0 0x4000>; 2671 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2672 clock-names = "se"; 2673 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2674 interconnect-names = "qup-core", "qup-config"; 2675 pinctrl-0 = <&qup_uart21_default>; 2676 pinctrl-names = "default"; 2677 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2678 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2679 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2680 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2681 power-domains = <&rpmhpd SA8775P_CX>; 2682 operating-points-v2 = <&qup_opp_table_100mhz>; 2683 status = "disabled"; 2684 }; 2685 }; 2686 2687 rng: rng@10d2000 { 2688 compatible = "qcom,sa8775p-trng", "qcom,trng"; 2689 reg = <0 0x010d2000 0 0x1000>; 2690 }; 2691 2692 ufs_mem_hc: ufshc@1d84000 { 2693 compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 2694 reg = <0x0 0x01d84000 0x0 0x3000>; 2695 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2696 phys = <&ufs_mem_phy>; 2697 phy-names = "ufsphy"; 2698 lanes-per-direction = <2>; 2699 #reset-cells = <1>; 2700 resets = <&gcc GCC_UFS_PHY_BCR>; 2701 reset-names = "rst"; 2702 power-domains = <&gcc UFS_PHY_GDSC>; 2703 required-opps = <&rpmhpd_opp_nom>; 2704 iommus = <&apps_smmu 0x100 0x0>; 2705 dma-coherent; 2706 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2707 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2708 <&gcc GCC_UFS_PHY_AHB_CLK>, 2709 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2710 <&rpmhcc RPMH_CXO_CLK>, 2711 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2712 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2713 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2714 clock-names = "core_clk", 2715 "bus_aggr_clk", 2716 "iface_clk", 2717 "core_clk_unipro", 2718 "ref_clk", 2719 "tx_lane0_sync_clk", 2720 "rx_lane0_sync_clk", 2721 "rx_lane1_sync_clk"; 2722 freq-table-hz = <75000000 300000000>, 2723 <0 0>, 2724 <0 0>, 2725 <75000000 300000000>, 2726 <0 0>, 2727 <0 0>, 2728 <0 0>, 2729 <0 0>; 2730 qcom,ice = <&ice>; 2731 status = "disabled"; 2732 }; 2733 2734 ufs_mem_phy: phy@1d87000 { 2735 compatible = "qcom,sa8775p-qmp-ufs-phy"; 2736 reg = <0x0 0x01d87000 0x0 0xe10>; 2737 /* 2738 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 2739 * enables the CXO clock to eDP *and* UFS PHY. 2740 */ 2741 clocks = <&rpmhcc RPMH_CXO_CLK>, 2742 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2743 <&gcc GCC_EDP_REF_CLKREF_EN>; 2744 clock-names = "ref", "ref_aux", "qref"; 2745 power-domains = <&gcc UFS_PHY_GDSC>; 2746 resets = <&ufs_mem_hc 0>; 2747 reset-names = "ufsphy"; 2748 #phy-cells = <0>; 2749 status = "disabled"; 2750 }; 2751 2752 ice: crypto@1d88000 { 2753 compatible = "qcom,sa8775p-inline-crypto-engine", 2754 "qcom,inline-crypto-engine"; 2755 reg = <0x0 0x01d88000 0x0 0x18000>; 2756 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2757 }; 2758 2759 cryptobam: dma-controller@1dc4000 { 2760 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2761 reg = <0x0 0x01dc4000 0x0 0x28000>; 2762 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2763 #dma-cells = <1>; 2764 qcom,ee = <0>; 2765 qcom,num-ees = <4>; 2766 num-channels = <20>; 2767 qcom,controlled-remotely; 2768 iommus = <&apps_smmu 0x480 0x00>, 2769 <&apps_smmu 0x481 0x00>; 2770 }; 2771 2772 ctcu@4001000 { 2773 compatible = "qcom,sa8775p-ctcu"; 2774 reg = <0x0 0x04001000 0x0 0x1000>; 2775 2776 clocks = <&aoss_qmp>; 2777 clock-names = "apb"; 2778 2779 in-ports { 2780 #address-cells = <1>; 2781 #size-cells = <0>; 2782 2783 port@0 { 2784 reg = <0>; 2785 2786 ctcu_in0: endpoint { 2787 remote-endpoint = <&etr0_out>; 2788 }; 2789 }; 2790 2791 port@1 { 2792 reg = <1>; 2793 2794 ctcu_in1: endpoint { 2795 remote-endpoint = <&etr1_out>; 2796 }; 2797 }; 2798 }; 2799 }; 2800 2801 stm: stm@4002000 { 2802 compatible = "arm,coresight-stm", "arm,primecell"; 2803 reg = <0x0 0x4002000 0x0 0x1000>, 2804 <0x0 0x16280000 0x0 0x180000>; 2805 reg-names = "stm-base", "stm-stimulus-base"; 2806 2807 clocks = <&aoss_qmp>; 2808 clock-names = "apb_pclk"; 2809 2810 out-ports { 2811 port { 2812 stm_out: endpoint { 2813 remote-endpoint = 2814 <&funnel0_in7>; 2815 }; 2816 }; 2817 }; 2818 }; 2819 2820 tpdm@4003000 { 2821 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2822 reg = <0x0 0x4003000 0x0 0x1000>; 2823 2824 clocks = <&aoss_qmp>; 2825 clock-names = "apb_pclk"; 2826 2827 qcom,cmb-element-bits = <32>; 2828 qcom,cmb-msrs-num = <32>; 2829 status = "disabled"; 2830 2831 out-ports { 2832 port { 2833 qdss_tpdm0_out: endpoint { 2834 remote-endpoint = 2835 <&qdss_tpda_in0>; 2836 }; 2837 }; 2838 }; 2839 }; 2840 2841 tpda@4004000 { 2842 compatible = "qcom,coresight-tpda", "arm,primecell"; 2843 reg = <0x0 0x4004000 0x0 0x1000>; 2844 2845 clocks = <&aoss_qmp>; 2846 clock-names = "apb_pclk"; 2847 2848 out-ports { 2849 port { 2850 qdss_tpda_out: endpoint { 2851 remote-endpoint = 2852 <&funnel0_in6>; 2853 }; 2854 }; 2855 }; 2856 2857 in-ports { 2858 #address-cells = <1>; 2859 #size-cells = <0>; 2860 2861 port@0 { 2862 reg = <0>; 2863 qdss_tpda_in0: endpoint { 2864 remote-endpoint = 2865 <&qdss_tpdm0_out>; 2866 }; 2867 }; 2868 2869 port@1 { 2870 reg = <1>; 2871 qdss_tpda_in1: endpoint { 2872 remote-endpoint = 2873 <&qdss_tpdm1_out>; 2874 }; 2875 }; 2876 }; 2877 }; 2878 2879 tpdm@400f000 { 2880 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2881 reg = <0x0 0x400f000 0x0 0x1000>; 2882 2883 clocks = <&aoss_qmp>; 2884 clock-names = "apb_pclk"; 2885 2886 qcom,cmb-element-bits = <32>; 2887 qcom,cmb-msrs-num = <32>; 2888 2889 out-ports { 2890 port { 2891 qdss_tpdm1_out: endpoint { 2892 remote-endpoint = 2893 <&qdss_tpda_in1>; 2894 }; 2895 }; 2896 }; 2897 }; 2898 2899 funnel@4041000 { 2900 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2901 reg = <0x0 0x4041000 0x0 0x1000>; 2902 2903 clocks = <&aoss_qmp>; 2904 clock-names = "apb_pclk"; 2905 2906 out-ports { 2907 port { 2908 funnel0_out: endpoint { 2909 remote-endpoint = 2910 <&qdss_funnel_in0>; 2911 }; 2912 }; 2913 }; 2914 2915 in-ports { 2916 #address-cells = <1>; 2917 #size-cells = <0>; 2918 2919 port@6 { 2920 reg = <6>; 2921 funnel0_in6: endpoint { 2922 remote-endpoint = 2923 <&qdss_tpda_out>; 2924 }; 2925 }; 2926 2927 port@7 { 2928 reg = <7>; 2929 funnel0_in7: endpoint { 2930 remote-endpoint = 2931 <&stm_out>; 2932 }; 2933 }; 2934 }; 2935 }; 2936 2937 funnel@4042000 { 2938 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2939 reg = <0x0 0x4042000 0x0 0x1000>; 2940 2941 clocks = <&aoss_qmp>; 2942 clock-names = "apb_pclk"; 2943 2944 out-ports { 2945 port { 2946 funnel1_out: endpoint { 2947 remote-endpoint = 2948 <&qdss_funnel_in1>; 2949 }; 2950 }; 2951 }; 2952 2953 in-ports { 2954 #address-cells = <1>; 2955 #size-cells = <0>; 2956 2957 port@4 { 2958 reg = <4>; 2959 funnel1_in4: endpoint { 2960 remote-endpoint = 2961 <&apss_funnel1_out>; 2962 }; 2963 }; 2964 }; 2965 }; 2966 2967 funnel@4045000 { 2968 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2969 reg = <0x0 0x4045000 0x0 0x1000>; 2970 2971 clocks = <&aoss_qmp>; 2972 clock-names = "apb_pclk"; 2973 2974 out-ports { 2975 port { 2976 qdss_funnel_out: endpoint { 2977 remote-endpoint = 2978 <&aoss_funnel_in7>; 2979 }; 2980 }; 2981 }; 2982 2983 in-ports { 2984 #address-cells = <1>; 2985 #size-cells = <0>; 2986 2987 port@0 { 2988 reg = <0>; 2989 qdss_funnel_in0: endpoint { 2990 remote-endpoint = 2991 <&funnel0_out>; 2992 }; 2993 }; 2994 2995 port@1 { 2996 reg = <1>; 2997 qdss_funnel_in1: endpoint { 2998 remote-endpoint = 2999 <&funnel1_out>; 3000 }; 3001 }; 3002 }; 3003 }; 3004 3005 replicator@4046000 { 3006 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3007 reg = <0x0 0x04046000 0x0 0x1000>; 3008 3009 clocks = <&aoss_qmp>; 3010 clock-names = "apb_pclk"; 3011 3012 in-ports { 3013 port { 3014 qdss_rep_in: endpoint { 3015 remote-endpoint = <&swao_rep_out0>; 3016 }; 3017 }; 3018 }; 3019 3020 out-ports { 3021 port { 3022 qdss_rep_out0: endpoint { 3023 remote-endpoint = <&etr_rep_in>; 3024 }; 3025 }; 3026 }; 3027 }; 3028 3029 tmc_etr: tmc@4048000 { 3030 compatible = "arm,coresight-tmc", "arm,primecell"; 3031 reg = <0x0 0x04048000 0x0 0x1000>; 3032 3033 clocks = <&aoss_qmp>; 3034 clock-names = "apb_pclk"; 3035 iommus = <&apps_smmu 0x04c0 0x00>; 3036 3037 arm,scatter-gather; 3038 3039 in-ports { 3040 port { 3041 etr0_in: endpoint { 3042 remote-endpoint = <&etr_rep_out0>; 3043 }; 3044 }; 3045 }; 3046 3047 out-ports { 3048 port { 3049 etr0_out: endpoint { 3050 remote-endpoint = <&ctcu_in0>; 3051 }; 3052 }; 3053 }; 3054 }; 3055 3056 replicator@404e000 { 3057 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3058 reg = <0x0 0x0404e000 0x0 0x1000>; 3059 3060 clocks = <&aoss_qmp>; 3061 clock-names = "apb_pclk"; 3062 3063 in-ports { 3064 port { 3065 etr_rep_in: endpoint { 3066 remote-endpoint = <&qdss_rep_out0>; 3067 }; 3068 }; 3069 }; 3070 3071 out-ports { 3072 #address-cells = <1>; 3073 #size-cells = <0>; 3074 3075 port@0 { 3076 reg = <0>; 3077 3078 etr_rep_out0: endpoint { 3079 remote-endpoint = <&etr0_in>; 3080 }; 3081 }; 3082 3083 port@1 { 3084 reg = <1>; 3085 3086 etr_rep_out1: endpoint { 3087 remote-endpoint = <&etr1_in>; 3088 }; 3089 }; 3090 }; 3091 }; 3092 3093 tmc_etr1: tmc@404f000 { 3094 compatible = "arm,coresight-tmc", "arm,primecell"; 3095 reg = <0x0 0x0404f000 0x0 0x1000>; 3096 3097 clocks = <&aoss_qmp>; 3098 clock-names = "apb_pclk"; 3099 iommus = <&apps_smmu 0x04a0 0x40>; 3100 3101 arm,scatter-gather; 3102 arm,buffer-size = <0x400000>; 3103 3104 in-ports { 3105 port { 3106 etr1_in: endpoint { 3107 remote-endpoint = <&etr_rep_out1>; 3108 }; 3109 }; 3110 }; 3111 3112 out-ports { 3113 port { 3114 etr1_out: endpoint { 3115 remote-endpoint = <&ctcu_in1>; 3116 }; 3117 }; 3118 }; 3119 }; 3120 3121 funnel@4b04000 { 3122 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3123 reg = <0x0 0x4b04000 0x0 0x1000>; 3124 3125 clocks = <&aoss_qmp>; 3126 clock-names = "apb_pclk"; 3127 3128 out-ports { 3129 port { 3130 aoss_funnel_out: endpoint { 3131 remote-endpoint = 3132 <&etf0_in>; 3133 }; 3134 }; 3135 }; 3136 3137 in-ports { 3138 #address-cells = <1>; 3139 #size-cells = <0>; 3140 3141 port@6 { 3142 reg = <6>; 3143 aoss_funnel_in6: endpoint { 3144 remote-endpoint = 3145 <&aoss_tpda_out>; 3146 }; 3147 }; 3148 3149 port@7 { 3150 reg = <7>; 3151 aoss_funnel_in7: endpoint { 3152 remote-endpoint = 3153 <&qdss_funnel_out>; 3154 }; 3155 }; 3156 }; 3157 }; 3158 3159 tmc_etf: tmc@4b05000 { 3160 compatible = "arm,coresight-tmc", "arm,primecell"; 3161 reg = <0x0 0x4b05000 0x0 0x1000>; 3162 3163 clocks = <&aoss_qmp>; 3164 clock-names = "apb_pclk"; 3165 3166 out-ports { 3167 port { 3168 etf0_out: endpoint { 3169 remote-endpoint = 3170 <&swao_rep_in>; 3171 }; 3172 }; 3173 }; 3174 3175 in-ports { 3176 port { 3177 etf0_in: endpoint { 3178 remote-endpoint = 3179 <&aoss_funnel_out>; 3180 }; 3181 }; 3182 }; 3183 }; 3184 3185 replicator@4b06000 { 3186 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3187 reg = <0x0 0x4b06000 0x0 0x1000>; 3188 3189 clocks = <&aoss_qmp>; 3190 clock-names = "apb_pclk"; 3191 3192 out-ports { 3193 #address-cells = <1>; 3194 #size-cells = <0>; 3195 3196 port@0 { 3197 reg = <0>; 3198 3199 swao_rep_out0: endpoint { 3200 remote-endpoint = <&qdss_rep_in>; 3201 }; 3202 }; 3203 3204 port@1 { 3205 reg = <1>; 3206 swao_rep_out1: endpoint { 3207 remote-endpoint = 3208 <&eud_in>; 3209 }; 3210 }; 3211 }; 3212 3213 in-ports { 3214 port { 3215 swao_rep_in: endpoint { 3216 remote-endpoint = 3217 <&etf0_out>; 3218 }; 3219 }; 3220 }; 3221 }; 3222 3223 tpda@4b08000 { 3224 compatible = "qcom,coresight-tpda", "arm,primecell"; 3225 reg = <0x0 0x4b08000 0x0 0x1000>; 3226 3227 clocks = <&aoss_qmp>; 3228 clock-names = "apb_pclk"; 3229 3230 out-ports { 3231 port { 3232 aoss_tpda_out: endpoint { 3233 remote-endpoint = 3234 <&aoss_funnel_in6>; 3235 }; 3236 }; 3237 }; 3238 3239 in-ports { 3240 #address-cells = <1>; 3241 #size-cells = <0>; 3242 3243 port@0 { 3244 reg = <0>; 3245 aoss_tpda_in0: endpoint { 3246 remote-endpoint = 3247 <&aoss_tpdm0_out>; 3248 }; 3249 }; 3250 3251 port@1 { 3252 reg = <1>; 3253 aoss_tpda_in1: endpoint { 3254 remote-endpoint = 3255 <&aoss_tpdm1_out>; 3256 }; 3257 }; 3258 3259 port@2 { 3260 reg = <2>; 3261 aoss_tpda_in2: endpoint { 3262 remote-endpoint = 3263 <&aoss_tpdm2_out>; 3264 }; 3265 }; 3266 3267 port@3 { 3268 reg = <3>; 3269 aoss_tpda_in3: endpoint { 3270 remote-endpoint = 3271 <&aoss_tpdm3_out>; 3272 }; 3273 }; 3274 3275 port@4 { 3276 reg = <4>; 3277 aoss_tpda_in4: endpoint { 3278 remote-endpoint = 3279 <&aoss_tpdm4_out>; 3280 }; 3281 }; 3282 }; 3283 }; 3284 3285 tpdm@4b09000 { 3286 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3287 reg = <0x0 0x4b09000 0x0 0x1000>; 3288 3289 clocks = <&aoss_qmp>; 3290 clock-names = "apb_pclk"; 3291 3292 qcom,cmb-element-bits = <64>; 3293 qcom,cmb-msrs-num = <32>; 3294 3295 out-ports { 3296 port { 3297 aoss_tpdm0_out: endpoint { 3298 remote-endpoint = 3299 <&aoss_tpda_in0>; 3300 }; 3301 }; 3302 }; 3303 }; 3304 3305 tpdm@4b0a000 { 3306 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3307 reg = <0x0 0x4b0a000 0x0 0x1000>; 3308 3309 clocks = <&aoss_qmp>; 3310 clock-names = "apb_pclk"; 3311 3312 qcom,cmb-element-bits = <64>; 3313 qcom,cmb-msrs-num = <32>; 3314 3315 out-ports { 3316 port { 3317 aoss_tpdm1_out: endpoint { 3318 remote-endpoint = 3319 <&aoss_tpda_in1>; 3320 }; 3321 }; 3322 }; 3323 }; 3324 3325 tpdm@4b0b000 { 3326 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3327 reg = <0x0 0x4b0b000 0x0 0x1000>; 3328 3329 clocks = <&aoss_qmp>; 3330 clock-names = "apb_pclk"; 3331 3332 qcom,cmb-element-bits = <64>; 3333 qcom,cmb-msrs-num = <32>; 3334 3335 out-ports { 3336 port { 3337 aoss_tpdm2_out: endpoint { 3338 remote-endpoint = 3339 <&aoss_tpda_in2>; 3340 }; 3341 }; 3342 }; 3343 }; 3344 3345 tpdm@4b0c000 { 3346 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3347 reg = <0x0 0x4b0c000 0x0 0x1000>; 3348 3349 clocks = <&aoss_qmp>; 3350 clock-names = "apb_pclk"; 3351 3352 qcom,cmb-element-bits = <64>; 3353 qcom,cmb-msrs-num = <32>; 3354 3355 out-ports { 3356 port { 3357 aoss_tpdm3_out: endpoint { 3358 remote-endpoint = 3359 <&aoss_tpda_in3>; 3360 }; 3361 }; 3362 }; 3363 }; 3364 3365 tpdm@4b0d000 { 3366 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3367 reg = <0x0 0x4b0d000 0x0 0x1000>; 3368 3369 clocks = <&aoss_qmp>; 3370 clock-names = "apb_pclk"; 3371 3372 qcom,dsb-element-bits = <32>; 3373 qcom,dsb-msrs-num = <32>; 3374 3375 out-ports { 3376 port { 3377 aoss_tpdm4_out: endpoint { 3378 remote-endpoint = 3379 <&aoss_tpda_in4>; 3380 }; 3381 }; 3382 }; 3383 }; 3384 3385 aoss_cti: cti@4b13000 { 3386 compatible = "arm,coresight-cti", "arm,primecell"; 3387 reg = <0x0 0x4b13000 0x0 0x1000>; 3388 3389 clocks = <&aoss_qmp>; 3390 clock-names = "apb_pclk"; 3391 }; 3392 3393 etm@6040000 { 3394 compatible = "arm,primecell"; 3395 reg = <0x0 0x6040000 0x0 0x1000>; 3396 cpu = <&cpu0>; 3397 3398 clocks = <&aoss_qmp>; 3399 clock-names = "apb_pclk"; 3400 arm,coresight-loses-context-with-cpu; 3401 qcom,skip-power-up; 3402 3403 out-ports { 3404 port { 3405 etm0_out: endpoint { 3406 remote-endpoint = 3407 <&apss_funnel0_in0>; 3408 }; 3409 }; 3410 }; 3411 }; 3412 3413 etm@6140000 { 3414 compatible = "arm,primecell"; 3415 reg = <0x0 0x6140000 0x0 0x1000>; 3416 cpu = <&cpu1>; 3417 3418 clocks = <&aoss_qmp>; 3419 clock-names = "apb_pclk"; 3420 arm,coresight-loses-context-with-cpu; 3421 qcom,skip-power-up; 3422 3423 out-ports { 3424 port { 3425 etm1_out: endpoint { 3426 remote-endpoint = 3427 <&apss_funnel0_in1>; 3428 }; 3429 }; 3430 }; 3431 }; 3432 3433 etm@6240000 { 3434 compatible = "arm,primecell"; 3435 reg = <0x0 0x6240000 0x0 0x1000>; 3436 cpu = <&cpu2>; 3437 3438 clocks = <&aoss_qmp>; 3439 clock-names = "apb_pclk"; 3440 arm,coresight-loses-context-with-cpu; 3441 qcom,skip-power-up; 3442 3443 out-ports { 3444 port { 3445 etm2_out: endpoint { 3446 remote-endpoint = 3447 <&apss_funnel0_in2>; 3448 }; 3449 }; 3450 }; 3451 }; 3452 3453 etm@6340000 { 3454 compatible = "arm,primecell"; 3455 reg = <0x0 0x6340000 0x0 0x1000>; 3456 cpu = <&cpu3>; 3457 3458 clocks = <&aoss_qmp>; 3459 clock-names = "apb_pclk"; 3460 arm,coresight-loses-context-with-cpu; 3461 qcom,skip-power-up; 3462 3463 out-ports { 3464 port { 3465 etm3_out: endpoint { 3466 remote-endpoint = 3467 <&apss_funnel0_in3>; 3468 }; 3469 }; 3470 }; 3471 }; 3472 3473 etm@6440000 { 3474 compatible = "arm,primecell"; 3475 reg = <0x0 0x6440000 0x0 0x1000>; 3476 cpu = <&cpu4>; 3477 3478 clocks = <&aoss_qmp>; 3479 clock-names = "apb_pclk"; 3480 arm,coresight-loses-context-with-cpu; 3481 qcom,skip-power-up; 3482 3483 out-ports { 3484 port { 3485 etm4_out: endpoint { 3486 remote-endpoint = 3487 <&apss_funnel0_in4>; 3488 }; 3489 }; 3490 }; 3491 }; 3492 3493 etm@6540000 { 3494 compatible = "arm,primecell"; 3495 reg = <0x0 0x6540000 0x0 0x1000>; 3496 cpu = <&cpu5>; 3497 3498 clocks = <&aoss_qmp>; 3499 clock-names = "apb_pclk"; 3500 arm,coresight-loses-context-with-cpu; 3501 qcom,skip-power-up; 3502 3503 out-ports { 3504 port { 3505 etm5_out: endpoint { 3506 remote-endpoint = 3507 <&apss_funnel0_in5>; 3508 }; 3509 }; 3510 }; 3511 }; 3512 3513 etm@6640000 { 3514 compatible = "arm,primecell"; 3515 reg = <0x0 0x6640000 0x0 0x1000>; 3516 cpu = <&cpu6>; 3517 3518 clocks = <&aoss_qmp>; 3519 clock-names = "apb_pclk"; 3520 arm,coresight-loses-context-with-cpu; 3521 qcom,skip-power-up; 3522 3523 out-ports { 3524 port { 3525 etm6_out: endpoint { 3526 remote-endpoint = 3527 <&apss_funnel0_in6>; 3528 }; 3529 }; 3530 }; 3531 }; 3532 3533 etm@6740000 { 3534 compatible = "arm,primecell"; 3535 reg = <0x0 0x6740000 0x0 0x1000>; 3536 cpu = <&cpu7>; 3537 3538 clocks = <&aoss_qmp>; 3539 clock-names = "apb_pclk"; 3540 arm,coresight-loses-context-with-cpu; 3541 qcom,skip-power-up; 3542 3543 out-ports { 3544 port { 3545 etm7_out: endpoint { 3546 remote-endpoint = 3547 <&apss_funnel0_in7>; 3548 }; 3549 }; 3550 }; 3551 }; 3552 3553 funnel@6800000 { 3554 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3555 reg = <0x0 0x6800000 0x0 0x1000>; 3556 3557 clocks = <&aoss_qmp>; 3558 clock-names = "apb_pclk"; 3559 3560 out-ports { 3561 port { 3562 apss_funnel0_out: endpoint { 3563 remote-endpoint = 3564 <&apss_funnel1_in0>; 3565 }; 3566 }; 3567 }; 3568 3569 in-ports { 3570 #address-cells = <1>; 3571 #size-cells = <0>; 3572 3573 port@0 { 3574 reg = <0>; 3575 apss_funnel0_in0: endpoint { 3576 remote-endpoint = 3577 <&etm0_out>; 3578 }; 3579 }; 3580 3581 port@1 { 3582 reg = <1>; 3583 apss_funnel0_in1: endpoint { 3584 remote-endpoint = 3585 <&etm1_out>; 3586 }; 3587 }; 3588 3589 port@2 { 3590 reg = <2>; 3591 apss_funnel0_in2: endpoint { 3592 remote-endpoint = 3593 <&etm2_out>; 3594 }; 3595 }; 3596 3597 port@3 { 3598 reg = <3>; 3599 apss_funnel0_in3: endpoint { 3600 remote-endpoint = 3601 <&etm3_out>; 3602 }; 3603 }; 3604 3605 port@4 { 3606 reg = <4>; 3607 apss_funnel0_in4: endpoint { 3608 remote-endpoint = 3609 <&etm4_out>; 3610 }; 3611 }; 3612 3613 port@5 { 3614 reg = <5>; 3615 apss_funnel0_in5: endpoint { 3616 remote-endpoint = 3617 <&etm5_out>; 3618 }; 3619 }; 3620 3621 port@6 { 3622 reg = <6>; 3623 apss_funnel0_in6: endpoint { 3624 remote-endpoint = 3625 <&etm6_out>; 3626 }; 3627 }; 3628 3629 port@7 { 3630 reg = <7>; 3631 apss_funnel0_in7: endpoint { 3632 remote-endpoint = 3633 <&etm7_out>; 3634 }; 3635 }; 3636 }; 3637 }; 3638 3639 funnel@6810000 { 3640 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3641 reg = <0x0 0x6810000 0x0 0x1000>; 3642 3643 clocks = <&aoss_qmp>; 3644 clock-names = "apb_pclk"; 3645 3646 out-ports { 3647 port { 3648 apss_funnel1_out: endpoint { 3649 remote-endpoint = 3650 <&funnel1_in4>; 3651 }; 3652 }; 3653 }; 3654 3655 in-ports { 3656 #address-cells = <1>; 3657 #size-cells = <0>; 3658 3659 port@0 { 3660 reg = <0>; 3661 apss_funnel1_in0: endpoint { 3662 remote-endpoint = 3663 <&apss_funnel0_out>; 3664 }; 3665 }; 3666 3667 port@3 { 3668 reg = <3>; 3669 apss_funnel1_in3: endpoint { 3670 remote-endpoint = 3671 <&apss_tpda_out>; 3672 }; 3673 }; 3674 }; 3675 }; 3676 3677 tpdm@6860000 { 3678 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3679 reg = <0x0 0x6860000 0x0 0x1000>; 3680 3681 clocks = <&aoss_qmp>; 3682 clock-names = "apb_pclk"; 3683 3684 qcom,cmb-element-bits = <64>; 3685 qcom,cmb-msrs-num = <32>; 3686 3687 out-ports { 3688 port { 3689 apss_tpdm3_out: endpoint { 3690 remote-endpoint = 3691 <&apss_tpda_in3>; 3692 }; 3693 }; 3694 }; 3695 }; 3696 3697 tpdm@6861000 { 3698 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3699 reg = <0x0 0x6861000 0x0 0x1000>; 3700 3701 clocks = <&aoss_qmp>; 3702 clock-names = "apb_pclk"; 3703 3704 qcom,dsb-element-bits = <32>; 3705 qcom,dsb-msrs-num = <32>; 3706 3707 out-ports { 3708 port { 3709 apss_tpdm4_out: endpoint { 3710 remote-endpoint = 3711 <&apss_tpda_in4>; 3712 }; 3713 }; 3714 }; 3715 }; 3716 3717 tpda@6863000 { 3718 compatible = "qcom,coresight-tpda", "arm,primecell"; 3719 reg = <0x0 0x6863000 0x0 0x1000>; 3720 3721 clocks = <&aoss_qmp>; 3722 clock-names = "apb_pclk"; 3723 3724 out-ports { 3725 port { 3726 apss_tpda_out: endpoint { 3727 remote-endpoint = 3728 <&apss_funnel1_in3>; 3729 }; 3730 }; 3731 }; 3732 3733 in-ports { 3734 #address-cells = <1>; 3735 #size-cells = <0>; 3736 3737 port@0 { 3738 reg = <0>; 3739 apss_tpda_in0: endpoint { 3740 remote-endpoint = 3741 <&apss_tpdm0_out>; 3742 }; 3743 }; 3744 3745 port@1 { 3746 reg = <1>; 3747 apss_tpda_in1: endpoint { 3748 remote-endpoint = 3749 <&apss_tpdm1_out>; 3750 }; 3751 }; 3752 3753 port@2 { 3754 reg = <2>; 3755 apss_tpda_in2: endpoint { 3756 remote-endpoint = 3757 <&apss_tpdm2_out>; 3758 }; 3759 }; 3760 3761 port@3 { 3762 reg = <3>; 3763 apss_tpda_in3: endpoint { 3764 remote-endpoint = 3765 <&apss_tpdm3_out>; 3766 }; 3767 }; 3768 3769 port@4 { 3770 reg = <4>; 3771 apss_tpda_in4: endpoint { 3772 remote-endpoint = 3773 <&apss_tpdm4_out>; 3774 }; 3775 }; 3776 }; 3777 }; 3778 3779 tpdm@68a0000 { 3780 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3781 reg = <0x0 0x68a0000 0x0 0x1000>; 3782 3783 clocks = <&aoss_qmp>; 3784 clock-names = "apb_pclk"; 3785 3786 qcom,cmb-element-bits = <32>; 3787 qcom,cmb-msrs-num = <32>; 3788 3789 out-ports { 3790 port { 3791 apss_tpdm0_out: endpoint { 3792 remote-endpoint = 3793 <&apss_tpda_in0>; 3794 }; 3795 }; 3796 }; 3797 }; 3798 3799 tpdm@68b0000 { 3800 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3801 reg = <0x0 0x68b0000 0x0 0x1000>; 3802 3803 clocks = <&aoss_qmp>; 3804 clock-names = "apb_pclk"; 3805 3806 qcom,cmb-element-bits = <32>; 3807 qcom,cmb-msrs-num = <32>; 3808 3809 out-ports { 3810 port { 3811 apss_tpdm1_out: endpoint { 3812 remote-endpoint = 3813 <&apss_tpda_in1>; 3814 }; 3815 }; 3816 }; 3817 }; 3818 3819 tpdm@68c0000 { 3820 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3821 reg = <0x0 0x68c0000 0x0 0x1000>; 3822 3823 clocks = <&aoss_qmp>; 3824 clock-names = "apb_pclk"; 3825 3826 qcom,dsb-element-bits = <32>; 3827 qcom,dsb-msrs-num = <32>; 3828 3829 out-ports { 3830 port { 3831 apss_tpdm2_out: endpoint { 3832 remote-endpoint = 3833 <&apss_tpda_in2>; 3834 }; 3835 }; 3836 }; 3837 }; 3838 3839 sdhc: mmc@87c4000 { 3840 compatible = "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5"; 3841 reg = <0x0 0x087c4000 0x0 0x1000>; 3842 3843 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 3844 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>; 3845 interrupt-names = "hc_irq", 3846 "pwr_irq"; 3847 3848 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 3849 <&gcc GCC_SDCC1_APPS_CLK>; 3850 clock-names = "iface", 3851 "core"; 3852 3853 interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS 3854 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3855 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3856 &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3857 interconnect-names = "sdhc-ddr", 3858 "cpu-sdhc"; 3859 3860 iommus = <&apps_smmu 0x0 0x0>; 3861 dma-coherent; 3862 3863 operating-points-v2 = <&sdhc_opp_table>; 3864 power-domains = <&rpmhpd SA8775P_CX>; 3865 resets = <&gcc GCC_SDCC1_BCR>; 3866 3867 qcom,dll-config = <0x0007642c>; 3868 qcom,ddr-config = <0x80040868>; 3869 3870 status = "disabled"; 3871 3872 sdhc_opp_table: opp-table { 3873 compatible = "operating-points-v2"; 3874 3875 opp-100000000 { 3876 opp-hz = /bits/ 64 <100000000>; 3877 required-opps = <&rpmhpd_opp_low_svs>; 3878 opp-peak-kBps = <1800000 400000>; 3879 opp-avg-kBps = <100000 0>; 3880 }; 3881 3882 opp-384000000 { 3883 opp-hz = /bits/ 64 <384000000>; 3884 required-opps = <&rpmhpd_opp_nom>; 3885 opp-peak-kBps = <5400000 1600000>; 3886 opp-avg-kBps = <390000 0>; 3887 }; 3888 }; 3889 }; 3890 3891 usb_0_hsphy: phy@88e4000 { 3892 compatible = "qcom,sa8775p-usb-hs-phy", 3893 "qcom,usb-snps-hs-5nm-phy"; 3894 reg = <0 0x088e4000 0 0x120>; 3895 clocks = <&rpmhcc RPMH_CXO_CLK>; 3896 clock-names = "ref"; 3897 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 3898 3899 #phy-cells = <0>; 3900 3901 status = "disabled"; 3902 }; 3903 3904 usb_1_hsphy: phy@88e6000 { 3905 compatible = "qcom,sa8775p-usb-hs-phy", 3906 "qcom,usb-snps-hs-5nm-phy"; 3907 reg = <0 0x088e6000 0 0x120>; 3908 clocks = <&gcc GCC_USB_CLKREF_EN>; 3909 clock-names = "ref"; 3910 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 3911 3912 #phy-cells = <0>; 3913 3914 status = "disabled"; 3915 }; 3916 3917 usb_2_hsphy: phy@88e7000 { 3918 compatible = "qcom,sa8775p-usb-hs-phy", 3919 "qcom,usb-snps-hs-5nm-phy"; 3920 reg = <0 0x088e7000 0 0x120>; 3921 clocks = <&gcc GCC_USB_CLKREF_EN>; 3922 clock-names = "ref"; 3923 resets = <&gcc GCC_USB3_PHY_TERT_BCR>; 3924 3925 #phy-cells = <0>; 3926 3927 status = "disabled"; 3928 }; 3929 3930 usb_0_qmpphy: phy@88e8000 { 3931 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 3932 reg = <0 0x088e8000 0 0x2000>; 3933 3934 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3935 <&gcc GCC_USB_CLKREF_EN>, 3936 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3937 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3938 clock-names = "aux", "ref", "com_aux", "pipe"; 3939 3940 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3941 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 3942 reset-names = "phy", "phy_phy"; 3943 3944 power-domains = <&gcc USB30_PRIM_GDSC>; 3945 3946 #clock-cells = <0>; 3947 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 3948 3949 #phy-cells = <0>; 3950 3951 status = "disabled"; 3952 }; 3953 3954 usb_1_qmpphy: phy@88ea000 { 3955 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 3956 reg = <0 0x088ea000 0 0x2000>; 3957 3958 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3959 <&gcc GCC_USB_CLKREF_EN>, 3960 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3961 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3962 clock-names = "aux", "ref", "com_aux", "pipe"; 3963 3964 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3965 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 3966 reset-names = "phy", "phy_phy"; 3967 3968 power-domains = <&gcc USB30_SEC_GDSC>; 3969 3970 #clock-cells = <0>; 3971 clock-output-names = "usb3_sec_phy_pipe_clk_src"; 3972 3973 #phy-cells = <0>; 3974 3975 status = "disabled"; 3976 }; 3977 3978 refgen: regulator@891c000 { 3979 compatible = "qcom,sa8775p-refgen-regulator", 3980 "qcom,sm8250-refgen-regulator"; 3981 reg = <0x0 0x0891c000 0x0 0x84>; 3982 }; 3983 3984 usb_0: usb@a600000 { 3985 compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; 3986 reg = <0 0x0a600000 0 0xfc100>; 3987 3988 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3989 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3990 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3991 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3992 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3993 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 3994 3995 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3996 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3997 assigned-clock-rates = <19200000>, <200000000>; 3998 3999 interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 4000 <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 4001 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 4002 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4003 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4004 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 4005 interrupt-names = "dwc_usb3", 4006 "pwr_event", 4007 "hs_phy_irq", 4008 "dp_hs_phy_irq", 4009 "dm_hs_phy_irq", 4010 "ss_phy_irq"; 4011 4012 power-domains = <&gcc USB30_PRIM_GDSC>; 4013 required-opps = <&rpmhpd_opp_nom>; 4014 4015 resets = <&gcc GCC_USB30_PRIM_BCR>; 4016 4017 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4018 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4019 interconnect-names = "usb-ddr", "apps-usb"; 4020 4021 wakeup-source; 4022 4023 iommus = <&apps_smmu 0x080 0x0>; 4024 phys = <&usb_0_hsphy>, <&usb_0_qmpphy>; 4025 phy-names = "usb2-phy", "usb3-phy"; 4026 snps,dis-u1-entry-quirk; 4027 snps,dis-u2-entry-quirk; 4028 4029 status = "disabled"; 4030 }; 4031 4032 usb_1: usb@a800000 { 4033 compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; 4034 reg = <0 0x0a800000 0 0xfc100>; 4035 4036 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4037 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4038 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4039 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4040 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 4041 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 4042 4043 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4044 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4045 assigned-clock-rates = <19200000>, <200000000>; 4046 4047 interrupts-extended = <&intc GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 4048 <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 4049 <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 4050 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 4051 <&pdc 7 IRQ_TYPE_EDGE_BOTH>, 4052 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; 4053 interrupt-names = "dwc_usb3", 4054 "pwr_event", 4055 "hs_phy_irq", 4056 "dp_hs_phy_irq", 4057 "dm_hs_phy_irq", 4058 "ss_phy_irq"; 4059 4060 power-domains = <&gcc USB30_SEC_GDSC>; 4061 required-opps = <&rpmhpd_opp_nom>; 4062 4063 resets = <&gcc GCC_USB30_SEC_BCR>; 4064 4065 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 4066 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 4067 interconnect-names = "usb-ddr", "apps-usb"; 4068 4069 wakeup-source; 4070 4071 iommus = <&apps_smmu 0x0a0 0x0>; 4072 phys = <&usb_1_hsphy>, <&usb_1_qmpphy>; 4073 phy-names = "usb2-phy", "usb3-phy"; 4074 snps,dis-u1-entry-quirk; 4075 snps,dis-u2-entry-quirk; 4076 4077 status = "disabled"; 4078 }; 4079 4080 usb_2: usb@a400000 { 4081 compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; 4082 reg = <0 0x0a400000 0 0xfc100>; 4083 4084 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4085 <&gcc GCC_USB20_MASTER_CLK>, 4086 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4087 <&gcc GCC_USB20_SLEEP_CLK>, 4088 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 4089 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 4090 4091 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4092 <&gcc GCC_USB20_MASTER_CLK>; 4093 assigned-clock-rates = <19200000>, <200000000>; 4094 4095 interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 4096 <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 4097 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 4098 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 4099 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 4100 interrupt-names = "dwc_usb3", 4101 "pwr_event", 4102 "hs_phy_irq", 4103 "dp_hs_phy_irq", 4104 "dm_hs_phy_irq"; 4105 4106 power-domains = <&gcc USB20_PRIM_GDSC>; 4107 required-opps = <&rpmhpd_opp_nom>; 4108 4109 resets = <&gcc GCC_USB20_PRIM_BCR>; 4110 4111 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 4112 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>; 4113 interconnect-names = "usb-ddr", "apps-usb"; 4114 4115 qcom,select-utmi-as-pipe-clk; 4116 wakeup-source; 4117 4118 iommus = <&apps_smmu 0x020 0x0>; 4119 phys = <&usb_2_hsphy>; 4120 phy-names = "usb2-phy"; 4121 snps,dis-u1-entry-quirk; 4122 snps,dis-u2-entry-quirk; 4123 4124 status = "disabled"; 4125 }; 4126 4127 tcsr_mutex: hwlock@1f40000 { 4128 compatible = "qcom,tcsr-mutex"; 4129 reg = <0x0 0x01f40000 0x0 0x20000>; 4130 #hwlock-cells = <1>; 4131 }; 4132 4133 tcsr: syscon@1fc0000 { 4134 compatible = "qcom,sa8775p-tcsr", "syscon"; 4135 reg = <0x0 0x1fc0000 0x0 0x30000>; 4136 }; 4137 4138 gpucc: clock-controller@3d90000 { 4139 compatible = "qcom,sa8775p-gpucc"; 4140 reg = <0x0 0x03d90000 0x0 0xa000>; 4141 clocks = <&rpmhcc RPMH_CXO_CLK>, 4142 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 4143 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 4144 clock-names = "bi_tcxo", 4145 "gcc_gpu_gpll0_clk_src", 4146 "gcc_gpu_gpll0_div_clk_src"; 4147 #clock-cells = <1>; 4148 #reset-cells = <1>; 4149 #power-domain-cells = <1>; 4150 }; 4151 4152 adreno_smmu: iommu@3da0000 { 4153 compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", 4154 "qcom,smmu-500", "arm,mmu-500"; 4155 reg = <0x0 0x03da0000 0x0 0x20000>; 4156 #iommu-cells = <2>; 4157 #global-interrupts = <2>; 4158 dma-coherent; 4159 power-domains = <&gpucc GPU_CC_CX_GDSC>; 4160 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4161 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 4162 <&gpucc GPU_CC_AHB_CLK>, 4163 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 4164 <&gpucc GPU_CC_CX_GMU_CLK>, 4165 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4166 <&gpucc GPU_CC_HUB_AON_CLK>; 4167 clock-names = "gcc_gpu_memnoc_gfx_clk", 4168 "gcc_gpu_snoc_dvm_gfx_clk", 4169 "gpu_cc_ahb_clk", 4170 "gpu_cc_hlos1_vote_gpu_smmu_clk", 4171 "gpu_cc_cx_gmu_clk", 4172 "gpu_cc_hub_cx_int_clk", 4173 "gpu_cc_hub_aon_clk"; 4174 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 4175 <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 4176 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 4177 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 4178 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 4179 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 4180 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 4181 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 4182 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 4183 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 4184 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 4185 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 4186 }; 4187 4188 serdes0: phy@8901000 { 4189 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 4190 reg = <0x0 0x08901000 0x0 0xe10>; 4191 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 4192 clock-names = "sgmi_ref"; 4193 #phy-cells = <0>; 4194 status = "disabled"; 4195 }; 4196 4197 serdes1: phy@8902000 { 4198 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 4199 reg = <0x0 0x08902000 0x0 0xe10>; 4200 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 4201 clock-names = "sgmi_ref"; 4202 #phy-cells = <0>; 4203 status = "disabled"; 4204 }; 4205 4206 pmu@9091000 { 4207 compatible = "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4208 reg = <0x0 0x9091000 0x0 0x1000>; 4209 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>; 4210 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 4211 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 4212 4213 operating-points-v2 = <&llcc_bwmon_opp_table>; 4214 4215 llcc_bwmon_opp_table: opp-table { 4216 compatible = "operating-points-v2"; 4217 4218 opp-0 { 4219 opp-peak-kBps = <762000>; 4220 }; 4221 4222 opp-1 { 4223 opp-peak-kBps = <1720000>; 4224 }; 4225 4226 opp-2 { 4227 opp-peak-kBps = <2086000>; 4228 }; 4229 4230 opp-3 { 4231 opp-peak-kBps = <2601000>; 4232 }; 4233 4234 opp-4 { 4235 opp-peak-kBps = <2929000>; 4236 }; 4237 4238 opp-5 { 4239 opp-peak-kBps = <5931000>; 4240 }; 4241 4242 opp-6 { 4243 opp-peak-kBps = <6515000>; 4244 }; 4245 4246 opp-7 { 4247 opp-peak-kBps = <7984000>; 4248 }; 4249 4250 opp-8 { 4251 opp-peak-kBps = <10437000>; 4252 }; 4253 4254 opp-9 { 4255 opp-peak-kBps = <12195000>; 4256 }; 4257 }; 4258 }; 4259 4260 pmu@90b5400 { 4261 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; 4262 reg = <0x0 0x90b5400 0x0 0x600>; 4263 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4264 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4265 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4266 4267 operating-points-v2 = <&cpu_bwmon_opp_table>; 4268 4269 cpu_bwmon_opp_table: opp-table { 4270 compatible = "operating-points-v2"; 4271 4272 opp-0 { 4273 opp-peak-kBps = <9155000>; 4274 }; 4275 4276 opp-1 { 4277 opp-peak-kBps = <12298000>; 4278 }; 4279 4280 opp-2 { 4281 opp-peak-kBps = <14236000>; 4282 }; 4283 4284 opp-3 { 4285 opp-peak-kBps = <16265000>; 4286 }; 4287 }; 4288 4289 }; 4290 4291 pmu@90b6400 { 4292 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; 4293 reg = <0x0 0x90b6400 0x0 0x600>; 4294 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4295 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4296 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4297 4298 operating-points-v2 = <&cpu_bwmon_opp_table>; 4299 }; 4300 4301 llcc: system-cache-controller@9200000 { 4302 compatible = "qcom,sa8775p-llcc"; 4303 reg = <0x0 0x09200000 0x0 0x80000>, 4304 <0x0 0x09300000 0x0 0x80000>, 4305 <0x0 0x09400000 0x0 0x80000>, 4306 <0x0 0x09500000 0x0 0x80000>, 4307 <0x0 0x09600000 0x0 0x80000>, 4308 <0x0 0x09700000 0x0 0x80000>, 4309 <0x0 0x09a00000 0x0 0x80000>; 4310 reg-names = "llcc0_base", 4311 "llcc1_base", 4312 "llcc2_base", 4313 "llcc3_base", 4314 "llcc4_base", 4315 "llcc5_base", 4316 "llcc_broadcast_base"; 4317 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 4318 }; 4319 4320 iris: video-codec@aa00000 { 4321 compatible = "qcom,sa8775p-iris", "qcom,sm8550-iris"; 4322 4323 reg = <0x0 0x0aa00000 0x0 0xf0000>; 4324 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4325 4326 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 4327 <&videocc VIDEO_CC_MVS0_GDSC>, 4328 <&rpmhpd SA8775P_MX>, 4329 <&rpmhpd SA8775P_MMCX>; 4330 power-domain-names = "venus", 4331 "vcodec0", 4332 "mxc", 4333 "mmcx"; 4334 operating-points-v2 = <&iris_opp_table>; 4335 4336 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 4337 <&videocc VIDEO_CC_MVS0C_CLK>, 4338 <&videocc VIDEO_CC_MVS0_CLK>; 4339 clock-names = "iface", 4340 "core", 4341 "vcodec0_core"; 4342 4343 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4344 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4345 <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 4346 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4347 interconnect-names = "cpu-cfg", 4348 "video-mem"; 4349 4350 memory-region = <&pil_video_mem>; 4351 4352 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 4353 reset-names = "bus"; 4354 4355 iommus = <&apps_smmu 0x0880 0x0400>, 4356 <&apps_smmu 0x0887 0x0400>; 4357 dma-coherent; 4358 4359 status = "disabled"; 4360 4361 iris_opp_table: opp-table { 4362 compatible = "operating-points-v2"; 4363 4364 opp-366000000 { 4365 opp-hz = /bits/ 64 <366000000>; 4366 required-opps = <&rpmhpd_opp_svs_l1>, 4367 <&rpmhpd_opp_svs_l1>; 4368 }; 4369 4370 opp-444000000 { 4371 opp-hz = /bits/ 64 <444000000>; 4372 required-opps = <&rpmhpd_opp_nom>, 4373 <&rpmhpd_opp_nom>; 4374 }; 4375 4376 opp-533000000 { 4377 opp-hz = /bits/ 64 <533000000>; 4378 required-opps = <&rpmhpd_opp_turbo>, 4379 <&rpmhpd_opp_turbo>; 4380 }; 4381 4382 opp-560000000 { 4383 opp-hz = /bits/ 64 <560000000>; 4384 required-opps = <&rpmhpd_opp_turbo_l1>, 4385 <&rpmhpd_opp_turbo_l1>; 4386 }; 4387 }; 4388 }; 4389 4390 videocc: clock-controller@abf0000 { 4391 compatible = "qcom,sa8775p-videocc"; 4392 reg = <0x0 0x0abf0000 0x0 0x10000>; 4393 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 4394 <&rpmhcc RPMH_CXO_CLK>, 4395 <&rpmhcc RPMH_CXO_CLK_A>, 4396 <&sleep_clk>; 4397 power-domains = <&rpmhpd SA8775P_MMCX>; 4398 #clock-cells = <1>; 4399 #reset-cells = <1>; 4400 #power-domain-cells = <1>; 4401 }; 4402 4403 cci0: cci@ac13000 { 4404 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 4405 reg = <0x0 0x0ac13000 0x0 0x1000>; 4406 4407 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4408 4409 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4410 4411 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4412 <&camcc CAM_CC_CPAS_AHB_CLK>, 4413 <&camcc CAM_CC_CCI_0_CLK>; 4414 clock-names = "camnoc_axi", 4415 "cpas_ahb", 4416 "cci"; 4417 4418 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 4419 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 4420 pinctrl-names = "default", "sleep"; 4421 4422 #address-cells = <1>; 4423 #size-cells = <0>; 4424 4425 status = "disabled"; 4426 4427 cci0_i2c0: i2c-bus@0 { 4428 reg = <0>; 4429 clock-frequency = <1000000>; 4430 #address-cells = <1>; 4431 #size-cells = <0>; 4432 }; 4433 4434 cci0_i2c1: i2c-bus@1 { 4435 reg = <1>; 4436 clock-frequency = <1000000>; 4437 #address-cells = <1>; 4438 #size-cells = <0>; 4439 }; 4440 }; 4441 4442 cci1: cci@ac14000 { 4443 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 4444 reg = <0x0 0x0ac14000 0x0 0x1000>; 4445 4446 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4447 4448 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4449 4450 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4451 <&camcc CAM_CC_CPAS_AHB_CLK>, 4452 <&camcc CAM_CC_CCI_1_CLK>; 4453 clock-names = "camnoc_axi", 4454 "cpas_ahb", 4455 "cci"; 4456 4457 pinctrl-0 = <&cci1_0_default &cci1_1_default>; 4458 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; 4459 pinctrl-names = "default", "sleep"; 4460 4461 #address-cells = <1>; 4462 #size-cells = <0>; 4463 4464 status = "disabled"; 4465 4466 cci1_i2c0: i2c-bus@0 { 4467 reg = <0>; 4468 clock-frequency = <1000000>; 4469 #address-cells = <1>; 4470 #size-cells = <0>; 4471 }; 4472 4473 cci1_i2c1: i2c-bus@1 { 4474 reg = <1>; 4475 clock-frequency = <1000000>; 4476 #address-cells = <1>; 4477 #size-cells = <0>; 4478 }; 4479 }; 4480 4481 cci2: cci@ac15000 { 4482 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 4483 reg = <0x0 0x0ac15000 0x0 0x1000>; 4484 4485 interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>; 4486 4487 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4488 4489 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4490 <&camcc CAM_CC_CPAS_AHB_CLK>, 4491 <&camcc CAM_CC_CCI_2_CLK>; 4492 clock-names = "camnoc_axi", 4493 "cpas_ahb", 4494 "cci"; 4495 4496 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 4497 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 4498 pinctrl-names = "default", "sleep"; 4499 4500 #address-cells = <1>; 4501 #size-cells = <0>; 4502 4503 status = "disabled"; 4504 4505 cci2_i2c0: i2c-bus@0 { 4506 reg = <0>; 4507 clock-frequency = <1000000>; 4508 #address-cells = <1>; 4509 #size-cells = <0>; 4510 }; 4511 4512 cci2_i2c1: i2c-bus@1 { 4513 reg = <1>; 4514 clock-frequency = <1000000>; 4515 #address-cells = <1>; 4516 #size-cells = <0>; 4517 }; 4518 }; 4519 4520 cci3: cci@ac16000 { 4521 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 4522 reg = <0x0 0x0ac16000 0x0 0x1000>; 4523 4524 interrupts = <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>; 4525 4526 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4527 4528 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4529 <&camcc CAM_CC_CPAS_AHB_CLK>, 4530 <&camcc CAM_CC_CCI_3_CLK>; 4531 clock-names = "camnoc_axi", 4532 "cpas_ahb", 4533 "cci"; 4534 4535 pinctrl-0 = <&cci3_0_default &cci3_1_default>; 4536 pinctrl-1 = <&cci3_0_sleep &cci3_1_sleep>; 4537 pinctrl-names = "default", "sleep"; 4538 4539 #address-cells = <1>; 4540 #size-cells = <0>; 4541 4542 status = "disabled"; 4543 4544 cci3_i2c0: i2c-bus@0 { 4545 reg = <0>; 4546 clock-frequency = <1000000>; 4547 #address-cells = <1>; 4548 #size-cells = <0>; 4549 }; 4550 4551 cci3_i2c1: i2c-bus@1 { 4552 reg = <1>; 4553 clock-frequency = <1000000>; 4554 #address-cells = <1>; 4555 #size-cells = <0>; 4556 }; 4557 }; 4558 4559 camss: isp@ac78000 { 4560 compatible = "qcom,sa8775p-camss"; 4561 4562 reg = <0x0 0xac78000 0x0 0x1000>, 4563 <0x0 0xac7a000 0x0 0x0f00>, 4564 <0x0 0xac7c000 0x0 0x0f00>, 4565 <0x0 0xac84000 0x0 0x0f00>, 4566 <0x0 0xac88000 0x0 0x0f00>, 4567 <0x0 0xac8c000 0x0 0x0f00>, 4568 <0x0 0xac90000 0x0 0x0f00>, 4569 <0x0 0xac94000 0x0 0x0f00>, 4570 <0x0 0xac9c000 0x0 0x2000>, 4571 <0x0 0xac9e000 0x0 0x2000>, 4572 <0x0 0xaca0000 0x0 0x2000>, 4573 <0x0 0xaca2000 0x0 0x2000>, 4574 <0x0 0xacac000 0x0 0x0400>, 4575 <0x0 0xacad000 0x0 0x0400>, 4576 <0x0 0xacae000 0x0 0x0400>, 4577 <0x0 0xac4d000 0x0 0xd000>, 4578 <0x0 0xac5a000 0x0 0xd000>, 4579 <0x0 0xac85000 0x0 0x0d00>, 4580 <0x0 0xac89000 0x0 0x0d00>, 4581 <0x0 0xac8d000 0x0 0x0d00>, 4582 <0x0 0xac91000 0x0 0x0d00>, 4583 <0x0 0xac95000 0x0 0x0d00>; 4584 reg-names = "csid_wrapper", 4585 "csid0", 4586 "csid1", 4587 "csid_lite0", 4588 "csid_lite1", 4589 "csid_lite2", 4590 "csid_lite3", 4591 "csid_lite4", 4592 "csiphy0", 4593 "csiphy1", 4594 "csiphy2", 4595 "csiphy3", 4596 "tpg0", 4597 "tpg1", 4598 "tpg2", 4599 "vfe0", 4600 "vfe1", 4601 "vfe_lite0", 4602 "vfe_lite1", 4603 "vfe_lite2", 4604 "vfe_lite3", 4605 "vfe_lite4"; 4606 4607 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4608 <&camcc CAM_CC_CORE_AHB_CLK>, 4609 <&camcc CAM_CC_CPAS_AHB_CLK>, 4610 <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, 4611 <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, 4612 <&camcc CAM_CC_CPAS_IFE_0_CLK>, 4613 <&camcc CAM_CC_CPAS_IFE_1_CLK>, 4614 <&camcc CAM_CC_CSID_CLK>, 4615 <&camcc CAM_CC_CSIPHY0_CLK>, 4616 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 4617 <&camcc CAM_CC_CSIPHY1_CLK>, 4618 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 4619 <&camcc CAM_CC_CSIPHY2_CLK>, 4620 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 4621 <&camcc CAM_CC_CSIPHY3_CLK>, 4622 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 4623 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, 4624 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4625 <&gcc GCC_CAMERA_SF_AXI_CLK>, 4626 <&camcc CAM_CC_ICP_AHB_CLK>, 4627 <&camcc CAM_CC_IFE_0_CLK>, 4628 <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, 4629 <&camcc CAM_CC_IFE_1_CLK>, 4630 <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, 4631 <&camcc CAM_CC_IFE_LITE_CLK>, 4632 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 4633 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4634 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 4635 clock-names = "camnoc_axi", 4636 "core_ahb", 4637 "cpas_ahb", 4638 "cpas_fast_ahb_clk", 4639 "cpas_vfe_lite", 4640 "cpas_vfe0", 4641 "cpas_vfe1", 4642 "csid", 4643 "csiphy0", 4644 "csiphy0_timer", 4645 "csiphy1", 4646 "csiphy1_timer", 4647 "csiphy2", 4648 "csiphy2_timer", 4649 "csiphy3", 4650 "csiphy3_timer", 4651 "csiphy_rx", 4652 "gcc_axi_hf", 4653 "gcc_axi_sf", 4654 "icp_ahb", 4655 "vfe0", 4656 "vfe0_fast_ahb", 4657 "vfe1", 4658 "vfe1_fast_ahb", 4659 "vfe_lite", 4660 "vfe_lite_ahb", 4661 "vfe_lite_cphy_rx", 4662 "vfe_lite_csid"; 4663 4664 interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>, 4665 <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>, 4666 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 4667 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 4668 <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, 4669 <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, 4670 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, 4671 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 4672 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 4673 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 4674 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 4675 <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>, 4676 <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>, 4677 <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>, 4678 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 4679 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 4680 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 4681 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, 4682 <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, 4683 <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, 4684 <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>; 4685 interrupt-names = "csid0", 4686 "csid1", 4687 "csid_lite0", 4688 "csid_lite1", 4689 "csid_lite2", 4690 "csid_lite3", 4691 "csid_lite4", 4692 "csiphy0", 4693 "csiphy1", 4694 "csiphy2", 4695 "csiphy3", 4696 "tpg0", 4697 "tpg1", 4698 "tpg2", 4699 "vfe0", 4700 "vfe1", 4701 "vfe_lite0", 4702 "vfe_lite1", 4703 "vfe_lite2", 4704 "vfe_lite3", 4705 "vfe_lite4"; 4706 4707 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4708 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4709 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 4710 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4711 interconnect-names = "ahb", 4712 "hf_0"; 4713 4714 iommus = <&apps_smmu 0x3400 0x20>; 4715 4716 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4717 power-domain-names = "top"; 4718 4719 status = "disabled"; 4720 4721 ports { 4722 #address-cells = <1>; 4723 #size-cells = <0>; 4724 4725 port@0 { 4726 reg = <0>; 4727 }; 4728 4729 port@1 { 4730 reg = <1>; 4731 }; 4732 4733 port@2 { 4734 reg = <2>; 4735 }; 4736 4737 port@3 { 4738 reg = <3>; 4739 }; 4740 }; 4741 }; 4742 4743 camcc: clock-controller@ade0000 { 4744 compatible = "qcom,sa8775p-camcc"; 4745 reg = <0x0 0x0ade0000 0x0 0x20000>; 4746 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4747 <&rpmhcc RPMH_CXO_CLK>, 4748 <&rpmhcc RPMH_CXO_CLK_A>, 4749 <&sleep_clk>; 4750 power-domains = <&rpmhpd SA8775P_MMCX>; 4751 #clock-cells = <1>; 4752 #reset-cells = <1>; 4753 #power-domain-cells = <1>; 4754 }; 4755 4756 mdss0: display-subsystem@ae00000 { 4757 compatible = "qcom,sa8775p-mdss"; 4758 reg = <0x0 0x0ae00000 0x0 0x1000>; 4759 reg-names = "mdss"; 4760 4761 /* same path used twice */ 4762 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 4763 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4764 <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS 4765 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4766 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4767 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4768 interconnect-names = "mdp0-mem", 4769 "mdp1-mem", 4770 "cpu-cfg"; 4771 4772 resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>; 4773 4774 power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>; 4775 4776 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 4777 <&gcc GCC_DISP_HF_AXI_CLK>, 4778 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>; 4779 4780 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 4781 interrupt-controller; 4782 #interrupt-cells = <1>; 4783 4784 iommus = <&apps_smmu 0x1000 0x402>; 4785 4786 #address-cells = <2>; 4787 #size-cells = <2>; 4788 ranges; 4789 4790 status = "disabled"; 4791 4792 mdss0_mdp: display-controller@ae01000 { 4793 compatible = "qcom,sa8775p-dpu"; 4794 reg = <0x0 0x0ae01000 0x0 0x8f000>, 4795 <0x0 0x0aeb0000 0x0 0x3000>; 4796 reg-names = "mdp", "vbif"; 4797 4798 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4799 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 4800 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, 4801 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, 4802 <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; 4803 clock-names = "nrt_bus", 4804 "iface", 4805 "lut", 4806 "core", 4807 "vsync"; 4808 4809 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; 4810 assigned-clock-rates = <19200000>; 4811 4812 operating-points-v2 = <&mdss0_mdp_opp_table>; 4813 power-domains = <&rpmhpd SA8775P_MMCX>; 4814 4815 interrupt-parent = <&mdss0>; 4816 interrupts = <0>; 4817 4818 ports { 4819 #address-cells = <1>; 4820 #size-cells = <0>; 4821 4822 port@0 { 4823 reg = <0>; 4824 4825 dpu_intf0_out: endpoint { 4826 remote-endpoint = <&mdss0_dp0_in>; 4827 }; 4828 }; 4829 4830 port@1 { 4831 reg = <1>; 4832 4833 dpu_intf4_out: endpoint { 4834 remote-endpoint = <&mdss0_dp1_in>; 4835 }; 4836 }; 4837 4838 port@2 { 4839 reg = <2>; 4840 4841 dpu_intf1_out: endpoint { 4842 remote-endpoint = <&mdss0_dsi0_in>; 4843 }; 4844 }; 4845 4846 port@3 { 4847 reg = <3>; 4848 4849 dpu_intf2_out: endpoint { 4850 remote-endpoint = <&mdss0_dsi1_in>; 4851 }; 4852 }; 4853 }; 4854 4855 mdss0_mdp_opp_table: opp-table { 4856 compatible = "operating-points-v2"; 4857 4858 opp-375000000 { 4859 opp-hz = /bits/ 64 <375000000>; 4860 required-opps = <&rpmhpd_opp_svs_l1>; 4861 }; 4862 4863 opp-500000000 { 4864 opp-hz = /bits/ 64 <500000000>; 4865 required-opps = <&rpmhpd_opp_nom>; 4866 }; 4867 4868 opp-575000000 { 4869 opp-hz = /bits/ 64 <575000000>; 4870 required-opps = <&rpmhpd_opp_turbo>; 4871 }; 4872 4873 opp-650000000 { 4874 opp-hz = /bits/ 64 <650000000>; 4875 required-opps = <&rpmhpd_opp_turbo_l1>; 4876 }; 4877 }; 4878 }; 4879 4880 mdss0_dsi0: dsi@ae94000 { 4881 compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 4882 reg = <0x0 0x0ae94000 0x0 0x400>; 4883 reg-names = "dsi_ctrl"; 4884 4885 interrupt-parent = <&mdss0>; 4886 interrupts = <4>; 4887 4888 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK>, 4889 <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>, 4890 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK>, 4891 <&dispcc0 MDSS_DISP_CC_MDSS_ESC0_CLK>, 4892 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 4893 <&gcc GCC_DISP_HF_AXI_CLK>; 4894 clock-names = "byte", 4895 "byte_intf", 4896 "pixel", 4897 "core", 4898 "iface", 4899 "bus"; 4900 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>, 4901 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>; 4902 assigned-clock-parents = <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, 4903 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>; 4904 phys = <&mdss0_dsi0_phy>; 4905 4906 operating-points-v2 = <&mdss_dsi_opp_table>; 4907 power-domains = <&rpmhpd SA8775P_MMCX>; 4908 4909 refgen-supply = <&refgen>; 4910 4911 #address-cells = <1>; 4912 #size-cells = <0>; 4913 4914 status = "disabled"; 4915 4916 ports { 4917 #address-cells = <1>; 4918 #size-cells = <0>; 4919 4920 port@0 { 4921 reg = <0>; 4922 4923 mdss0_dsi0_in: endpoint { 4924 remote-endpoint = <&dpu_intf1_out>; 4925 }; 4926 }; 4927 4928 port@1 { 4929 reg = <1>; 4930 4931 mdss0_dsi0_out: endpoint{ }; 4932 }; 4933 }; 4934 4935 mdss_dsi_opp_table: opp-table { 4936 compatible = "operating-points-v2"; 4937 4938 opp-358000000 { 4939 opp-hz = /bits/ 64 <358000000>; 4940 required-opps = <&rpmhpd_opp_svs_l1>; 4941 }; 4942 }; 4943 }; 4944 4945 mdss0_dsi0_phy: phy@ae94400 { 4946 compatible = "qcom,sa8775p-dsi-phy-5nm"; 4947 reg = <0x0 0x0ae94400 0x0 0x200>, 4948 <0x0 0x0ae94600 0x0 0x280>, 4949 <0x0 0x0ae94900 0x0 0x27c>; 4950 reg-names = "dsi_phy", 4951 "dsi_phy_lane", 4952 "dsi_pll"; 4953 4954 #clock-cells = <1>; 4955 #phy-cells = <0>; 4956 4957 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 4958 <&rpmhcc RPMH_CXO_CLK>; 4959 clock-names = "iface", "ref"; 4960 4961 status = "disabled"; 4962 }; 4963 4964 mdss0_dsi1: dsi@ae96000 { 4965 compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 4966 reg = <0x0 0x0ae96000 0x0 0x400>; 4967 reg-names = "dsi_ctrl"; 4968 4969 interrupt-parent = <&mdss0>; 4970 interrupts = <5>; 4971 4972 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK>, 4973 <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK>, 4974 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK>, 4975 <&dispcc0 MDSS_DISP_CC_MDSS_ESC1_CLK>, 4976 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 4977 <&gcc GCC_DISP_HF_AXI_CLK>; 4978 clock-names = "byte", 4979 "byte_intf", 4980 "pixel", 4981 "core", 4982 "iface", 4983 "bus"; 4984 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC>, 4985 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC>; 4986 assigned-clock-parents = <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, 4987 <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; 4988 phys = <&mdss0_dsi1_phy>; 4989 4990 operating-points-v2 = <&mdss_dsi_opp_table>; 4991 power-domains = <&rpmhpd SA8775P_MMCX>; 4992 4993 refgen-supply = <&refgen>; 4994 4995 #address-cells = <1>; 4996 #size-cells = <0>; 4997 4998 status = "disabled"; 4999 5000 ports { 5001 #address-cells = <1>; 5002 #size-cells = <0>; 5003 5004 port@0 { 5005 reg = <0>; 5006 5007 mdss0_dsi1_in: endpoint { 5008 remote-endpoint = <&dpu_intf2_out>; 5009 }; 5010 }; 5011 5012 port@1 { 5013 reg = <1>; 5014 5015 mdss0_dsi1_out: endpoint { }; 5016 }; 5017 }; 5018 }; 5019 5020 mdss0_dsi1_phy: phy@ae96400 { 5021 compatible = "qcom,sa8775p-dsi-phy-5nm"; 5022 reg = <0x0 0x0ae96400 0x0 0x200>, 5023 <0x0 0x0ae96600 0x0 0x280>, 5024 <0x0 0x0ae96900 0x0 0x27c>; 5025 reg-names = "dsi_phy", 5026 "dsi_phy_lane", 5027 "dsi_pll"; 5028 5029 #clock-cells = <1>; 5030 #phy-cells = <0>; 5031 5032 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5033 <&rpmhcc RPMH_CXO_CLK>; 5034 clock-names = "iface", "ref"; 5035 5036 status = "disabled"; 5037 }; 5038 5039 mdss0_dp0_phy: phy@aec2a00 { 5040 compatible = "qcom,sa8775p-edp-phy"; 5041 5042 reg = <0x0 0x0aec2a00 0x0 0x200>, 5043 <0x0 0x0aec2200 0x0 0xd0>, 5044 <0x0 0x0aec2600 0x0 0xd0>, 5045 <0x0 0x0aec2000 0x0 0x1c8>; 5046 5047 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 5048 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; 5049 clock-names = "aux", 5050 "cfg_ahb"; 5051 5052 #clock-cells = <1>; 5053 #phy-cells = <0>; 5054 5055 status = "disabled"; 5056 }; 5057 5058 mdss0_dp1_phy: phy@aec5a00 { 5059 compatible = "qcom,sa8775p-edp-phy"; 5060 5061 reg = <0x0 0x0aec5a00 0x0 0x200>, 5062 <0x0 0x0aec5200 0x0 0xd0>, 5063 <0x0 0x0aec5600 0x0 0xd0>, 5064 <0x0 0x0aec5000 0x0 0x1c8>; 5065 5066 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, 5067 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; 5068 clock-names = "aux", 5069 "cfg_ahb"; 5070 5071 #clock-cells = <1>; 5072 #phy-cells = <0>; 5073 5074 status = "disabled"; 5075 }; 5076 5077 mdss0_dp0: displayport-controller@af54000 { 5078 compatible = "qcom,sa8775p-dp"; 5079 5080 reg = <0x0 0x0af54000 0x0 0x104>, 5081 <0x0 0x0af54200 0x0 0x0c0>, 5082 <0x0 0x0af55000 0x0 0x770>, 5083 <0x0 0x0af56000 0x0 0x09c>, 5084 <0x0 0x0af57000 0x0 0x09c>, 5085 <0x0 0x0af58000 0x0 0x09c>, 5086 <0x0 0x0af59000 0x0 0x09c>, 5087 <0x0 0x0af5a000 0x0 0x23c>, 5088 <0x0 0x0af5b000 0x0 0x23c>; 5089 5090 interrupt-parent = <&mdss0>; 5091 interrupts = <12>; 5092 5093 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5094 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 5095 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, 5096 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5097 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 5098 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, 5099 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, 5100 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; 5101 clock-names = "core_iface", 5102 "core_aux", 5103 "ctrl_link", 5104 "ctrl_link_iface", 5105 "stream_pixel", 5106 "stream_1_pixel", 5107 "stream_2_pixel", 5108 "stream_3_pixel"; 5109 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5110 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 5111 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, 5112 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, 5113 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; 5114 assigned-clock-parents = <&mdss0_dp0_phy 0>, 5115 <&mdss0_dp0_phy 1>, 5116 <&mdss0_dp0_phy 1>, 5117 <&mdss0_dp0_phy 1>, 5118 <&mdss0_dp0_phy 1>; 5119 phys = <&mdss0_dp0_phy>; 5120 phy-names = "dp"; 5121 5122 operating-points-v2 = <&dp_opp_table>; 5123 power-domains = <&rpmhpd SA8775P_MMCX>; 5124 5125 #sound-dai-cells = <0>; 5126 5127 status = "disabled"; 5128 5129 ports { 5130 #address-cells = <1>; 5131 #size-cells = <0>; 5132 5133 port@0 { 5134 reg = <0>; 5135 5136 mdss0_dp0_in: endpoint { 5137 remote-endpoint = <&dpu_intf0_out>; 5138 }; 5139 }; 5140 5141 port@1 { 5142 reg = <1>; 5143 5144 mdss0_dp0_out: endpoint { }; 5145 }; 5146 }; 5147 5148 dp_opp_table: opp-table { 5149 compatible = "operating-points-v2"; 5150 5151 opp-160000000 { 5152 opp-hz = /bits/ 64 <160000000>; 5153 required-opps = <&rpmhpd_opp_low_svs>; 5154 }; 5155 5156 opp-270000000 { 5157 opp-hz = /bits/ 64 <270000000>; 5158 required-opps = <&rpmhpd_opp_svs>; 5159 }; 5160 5161 opp-540000000 { 5162 opp-hz = /bits/ 64 <540000000>; 5163 required-opps = <&rpmhpd_opp_svs_l1>; 5164 }; 5165 5166 opp-810000000 { 5167 opp-hz = /bits/ 64 <810000000>; 5168 required-opps = <&rpmhpd_opp_nom>; 5169 }; 5170 }; 5171 }; 5172 5173 mdss0_dp1: displayport-controller@af5c000 { 5174 compatible = "qcom,sa8775p-dp"; 5175 5176 reg = <0x0 0x0af5c000 0x0 0x104>, 5177 <0x0 0x0af5c200 0x0 0x0c0>, 5178 <0x0 0x0af5d000 0x0 0x770>, 5179 <0x0 0x0af5e000 0x0 0x09c>, 5180 <0x0 0x0af5f000 0x0 0x09c>, 5181 <0x0 0x0af60000 0x0 0x09c>, 5182 <0x0 0x0af61000 0x0 0x09c>, 5183 <0x0 0x0af62000 0x0 0x23c>, 5184 <0x0 0x0af63000 0x0 0x23c>; 5185 5186 interrupt-parent = <&mdss0>; 5187 interrupts = <13>; 5188 5189 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5190 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, 5191 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, 5192 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5193 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 5194 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 5195 clock-names = "core_iface", 5196 "core_aux", 5197 "ctrl_link", 5198 "ctrl_link_iface", 5199 "stream_pixel", 5200 "stream_1_pixel"; 5201 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5202 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 5203 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 5204 assigned-clock-parents = <&mdss0_dp1_phy 0>, 5205 <&mdss0_dp1_phy 1>, 5206 <&mdss0_dp1_phy 1>; 5207 phys = <&mdss0_dp1_phy>; 5208 phy-names = "dp"; 5209 5210 operating-points-v2 = <&dp1_opp_table>; 5211 power-domains = <&rpmhpd SA8775P_MMCX>; 5212 5213 #sound-dai-cells = <0>; 5214 5215 status = "disabled"; 5216 5217 ports { 5218 #address-cells = <1>; 5219 #size-cells = <0>; 5220 5221 port@0 { 5222 reg = <0>; 5223 5224 mdss0_dp1_in: endpoint { 5225 remote-endpoint = <&dpu_intf4_out>; 5226 }; 5227 }; 5228 5229 port@1 { 5230 reg = <1>; 5231 5232 mdss0_dp1_out: endpoint { }; 5233 }; 5234 }; 5235 5236 dp1_opp_table: opp-table { 5237 compatible = "operating-points-v2"; 5238 5239 opp-160000000 { 5240 opp-hz = /bits/ 64 <160000000>; 5241 required-opps = <&rpmhpd_opp_low_svs>; 5242 }; 5243 5244 opp-270000000 { 5245 opp-hz = /bits/ 64 <270000000>; 5246 required-opps = <&rpmhpd_opp_svs>; 5247 }; 5248 5249 opp-540000000 { 5250 opp-hz = /bits/ 64 <540000000>; 5251 required-opps = <&rpmhpd_opp_svs_l1>; 5252 }; 5253 5254 opp-810000000 { 5255 opp-hz = /bits/ 64 <810000000>; 5256 required-opps = <&rpmhpd_opp_nom>; 5257 }; 5258 }; 5259 }; 5260 }; 5261 5262 dispcc0: clock-controller@af00000 { 5263 compatible = "qcom,sa8775p-dispcc0"; 5264 reg = <0x0 0x0af00000 0x0 0x20000>; 5265 clocks = <&gcc GCC_DISP_AHB_CLK>, 5266 <&rpmhcc RPMH_CXO_CLK>, 5267 <&rpmhcc RPMH_CXO_CLK_A>, 5268 <&sleep_clk>, 5269 <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>, 5270 <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>, 5271 <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, 5272 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>, 5273 <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, 5274 <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; 5275 power-domains = <&rpmhpd SA8775P_MMCX>; 5276 #clock-cells = <1>; 5277 #reset-cells = <1>; 5278 #power-domain-cells = <1>; 5279 }; 5280 5281 pdc: interrupt-controller@b220000 { 5282 compatible = "qcom,sa8775p-pdc", "qcom,pdc"; 5283 reg = <0x0 0x0b220000 0x0 0x30000>, 5284 <0x0 0x17c000f0 0x0 0x64>; 5285 qcom,pdc-ranges = <0 480 40>, 5286 <40 140 14>, 5287 <54 263 1>, 5288 <55 306 4>, 5289 <59 312 3>, 5290 <62 374 2>, 5291 <64 434 2>, 5292 <66 438 2>, 5293 <70 520 1>, 5294 <73 523 1>, 5295 <118 568 6>, 5296 <124 609 3>, 5297 <159 638 1>, 5298 <160 720 3>, 5299 <169 728 30>, 5300 <199 416 2>, 5301 <201 449 1>, 5302 <202 89 1>, 5303 <203 451 1>, 5304 <204 462 1>, 5305 <205 264 1>, 5306 <206 579 1>, 5307 <207 653 1>, 5308 <208 656 1>, 5309 <209 659 1>, 5310 <210 122 1>, 5311 <211 699 1>, 5312 <212 705 1>, 5313 <213 450 1>, 5314 <214 643 2>, 5315 <216 646 5>, 5316 <221 390 5>, 5317 <226 700 2>, 5318 <228 440 1>, 5319 <229 663 1>, 5320 <230 524 2>, 5321 <232 612 3>, 5322 <235 723 5>; 5323 #interrupt-cells = <2>; 5324 interrupt-parent = <&intc>; 5325 interrupt-controller; 5326 }; 5327 5328 tsens2: thermal-sensor@c251000 { 5329 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5330 reg = <0x0 0x0c251000 0x0 0x1ff>, 5331 <0x0 0x0c224000 0x0 0x8>; 5332 interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, 5333 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 5334 #qcom,sensors = <13>; 5335 interrupt-names = "uplow", "critical"; 5336 #thermal-sensor-cells = <1>; 5337 }; 5338 5339 tsens3: thermal-sensor@c252000 { 5340 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5341 reg = <0x0 0x0c252000 0x0 0x1ff>, 5342 <0x0 0x0c225000 0x0 0x8>; 5343 interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, 5344 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 5345 #qcom,sensors = <13>; 5346 interrupt-names = "uplow", "critical"; 5347 #thermal-sensor-cells = <1>; 5348 }; 5349 5350 tsens0: thermal-sensor@c263000 { 5351 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5352 reg = <0x0 0x0c263000 0x0 0x1ff>, 5353 <0x0 0x0c222000 0x0 0x8>; 5354 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5355 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5356 #qcom,sensors = <12>; 5357 interrupt-names = "uplow", "critical"; 5358 #thermal-sensor-cells = <1>; 5359 }; 5360 5361 tsens1: thermal-sensor@c265000 { 5362 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5363 reg = <0x0 0x0c265000 0x0 0x1ff>, 5364 <0x0 0x0c223000 0x0 0x8>; 5365 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5366 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5367 #qcom,sensors = <12>; 5368 interrupt-names = "uplow", "critical"; 5369 #thermal-sensor-cells = <1>; 5370 }; 5371 5372 aoss_qmp: power-management@c300000 { 5373 compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp"; 5374 reg = <0x0 0x0c300000 0x0 0x400>; 5375 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 5376 IPCC_MPROC_SIGNAL_GLINK_QMP 5377 IRQ_TYPE_EDGE_RISING>; 5378 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5379 #clock-cells = <0>; 5380 }; 5381 5382 sram@c3f0000 { 5383 compatible = "qcom,rpmh-stats"; 5384 reg = <0x0 0x0c3f0000 0x0 0x400>; 5385 }; 5386 5387 spmi_bus: spmi@c440000 { 5388 compatible = "qcom,spmi-pmic-arb"; 5389 reg = <0x0 0x0c440000 0x0 0x1100>, 5390 <0x0 0x0c600000 0x0 0x2000000>, 5391 <0x0 0x0e600000 0x0 0x100000>, 5392 <0x0 0x0e700000 0x0 0xa0000>, 5393 <0x0 0x0c40a000 0x0 0x26000>; 5394 reg-names = "core", 5395 "chnls", 5396 "obsrvr", 5397 "intr", 5398 "cnfg"; 5399 qcom,channel = <0>; 5400 qcom,ee = <0>; 5401 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5402 interrupt-names = "periph_irq"; 5403 interrupt-controller; 5404 #interrupt-cells = <4>; 5405 #address-cells = <2>; 5406 #size-cells = <0>; 5407 }; 5408 5409 tlmm: pinctrl@f000000 { 5410 compatible = "qcom,sa8775p-tlmm"; 5411 reg = <0x0 0x0f000000 0x0 0x1000000>; 5412 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5413 gpio-controller; 5414 #gpio-cells = <2>; 5415 interrupt-controller; 5416 #interrupt-cells = <2>; 5417 gpio-ranges = <&tlmm 0 0 149>; 5418 wakeup-parent = <&pdc>; 5419 5420 dp0_hot_plug_det: dp0-hot-plug-det-state { 5421 pins = "gpio101"; 5422 function = "edp0_hot"; 5423 bias-disable; 5424 }; 5425 5426 dp1_hot_plug_det: dp1-hot-plug-det-state { 5427 pins = "gpio102"; 5428 function = "edp1_hot"; 5429 bias-disable; 5430 }; 5431 5432 hs0_mi2s_active: hs0-mi2s-active-state { 5433 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 5434 function = "hs0_mi2s"; 5435 drive-strength = <8>; 5436 bias-disable; 5437 }; 5438 5439 hs2_mi2s_active: hs2-mi2s-active-state { 5440 pins = "gpio122", "gpio123", "gpio124", "gpio125"; 5441 function = "hs2_mi2s"; 5442 drive-strength = <8>; 5443 bias-disable; 5444 }; 5445 5446 cci0_0_default: cci0-0-default-state { 5447 pins = "gpio60", "gpio61"; 5448 function = "cci_i2c"; 5449 drive-strength = <2>; 5450 bias-pull-up = <2200>; 5451 }; 5452 5453 cci0_0_sleep: cci0-0-sleep-state { 5454 pins = "gpio60", "gpio61"; 5455 function = "cci_i2c"; 5456 drive-strength = <2>; 5457 bias-pull-down; 5458 }; 5459 5460 cci0_1_default: cci0-1-default-state { 5461 pins = "gpio52", "gpio53"; 5462 function = "cci_i2c"; 5463 drive-strength = <2>; 5464 bias-pull-up = <2200>; 5465 }; 5466 5467 cci0_1_sleep: cci0-1-sleep-state { 5468 pins = "gpio52", "gpio53"; 5469 function = "cci_i2c"; 5470 drive-strength = <2>; 5471 bias-pull-down; 5472 }; 5473 5474 cci1_0_default: cci1-0-default-state { 5475 pins = "gpio62", "gpio63"; 5476 function = "cci_i2c"; 5477 drive-strength = <2>; 5478 bias-pull-up = <2200>; 5479 }; 5480 5481 cci1_0_sleep: cci1-0-sleep-state { 5482 pins = "gpio62", "gpio63"; 5483 function = "cci_i2c"; 5484 drive-strength = <2>; 5485 bias-pull-down; 5486 }; 5487 5488 cci1_1_default: cci1-1-default-state { 5489 pins = "gpio54", "gpio55"; 5490 function = "cci_i2c"; 5491 drive-strength = <2>; 5492 bias-pull-up = <2200>; 5493 }; 5494 5495 cci1_1_sleep: cci1-1-sleep-state { 5496 pins = "gpio54", "gpio55"; 5497 function = "cci_i2c"; 5498 drive-strength = <2>; 5499 bias-pull-down; 5500 }; 5501 5502 cci2_0_default: cci2-0-default-state { 5503 pins = "gpio64", "gpio65"; 5504 function = "cci_i2c"; 5505 drive-strength = <2>; 5506 bias-pull-up = <2200>; 5507 }; 5508 5509 cci2_0_sleep: cci2-0-sleep-state { 5510 pins = "gpio64", "gpio65"; 5511 function = "cci_i2c"; 5512 drive-strength = <2>; 5513 bias-pull-down; 5514 }; 5515 5516 cci2_1_default: cci2-1-default-state { 5517 pins = "gpio56", "gpio57"; 5518 function = "cci_i2c"; 5519 drive-strength = <2>; 5520 bias-pull-up = <2200>; 5521 }; 5522 5523 cci2_1_sleep: cci2-1-sleep-state { 5524 pins = "gpio56", "gpio57"; 5525 function = "cci_i2c"; 5526 drive-strength = <2>; 5527 bias-pull-down; 5528 }; 5529 5530 cci3_0_default: cci3-0-default-state { 5531 pins = "gpio66", "gpio67"; 5532 function = "cci_i2c"; 5533 drive-strength = <2>; 5534 bias-pull-up = <2200>; 5535 }; 5536 5537 cci3_0_sleep: cci3-0-sleep-state { 5538 pins = "gpio66", "gpio67"; 5539 function = "cci_i2c"; 5540 drive-strength = <2>; 5541 bias-pull-down; 5542 }; 5543 5544 cci3_1_default: cci3-1-default-state { 5545 pins = "gpio58", "gpio59"; 5546 function = "cci_i2c"; 5547 drive-strength = <2>; 5548 bias-pull-up = <2200>; 5549 }; 5550 5551 cci3_1_sleep: cci3-1-sleep-state { 5552 pins = "gpio58", "gpio59"; 5553 function = "cci_i2c"; 5554 drive-strength = <2>; 5555 bias-pull-down; 5556 }; 5557 5558 qup_i2c0_default: qup-i2c0-state { 5559 pins = "gpio20", "gpio21"; 5560 function = "qup0_se0"; 5561 }; 5562 5563 qup_i2c1_default: qup-i2c1-state { 5564 pins = "gpio24", "gpio25"; 5565 function = "qup0_se1"; 5566 }; 5567 5568 qup_i2c2_default: qup-i2c2-state { 5569 pins = "gpio36", "gpio37"; 5570 function = "qup0_se2"; 5571 }; 5572 5573 qup_i2c3_default: qup-i2c3-state { 5574 pins = "gpio28", "gpio29"; 5575 function = "qup0_se3"; 5576 }; 5577 5578 qup_i2c4_default: qup-i2c4-state { 5579 pins = "gpio32", "gpio33"; 5580 function = "qup0_se4"; 5581 }; 5582 5583 qup_i2c5_default: qup-i2c5-state { 5584 pins = "gpio36", "gpio37"; 5585 function = "qup0_se5"; 5586 }; 5587 5588 qup_i2c7_default: qup-i2c7-state { 5589 pins = "gpio40", "gpio41"; 5590 function = "qup1_se0"; 5591 }; 5592 5593 qup_i2c8_default: qup-i2c8-state { 5594 pins = "gpio42", "gpio43"; 5595 function = "qup1_se1"; 5596 }; 5597 5598 qup_i2c9_default: qup-i2c9-state { 5599 pins = "gpio46", "gpio47"; 5600 function = "qup1_se2"; 5601 }; 5602 5603 qup_i2c10_default: qup-i2c10-state { 5604 pins = "gpio44", "gpio45"; 5605 function = "qup1_se3"; 5606 }; 5607 5608 qup_i2c11_default: qup-i2c11-state { 5609 pins = "gpio48", "gpio49"; 5610 function = "qup1_se4"; 5611 }; 5612 5613 qup_i2c12_default: qup-i2c12-state { 5614 pins = "gpio52", "gpio53"; 5615 function = "qup1_se5"; 5616 }; 5617 5618 qup_i2c13_default: qup-i2c13-state { 5619 pins = "gpio56", "gpio57"; 5620 function = "qup1_se6"; 5621 }; 5622 5623 qup_i2c14_default: qup-i2c14-state { 5624 pins = "gpio80", "gpio81"; 5625 function = "qup2_se0"; 5626 }; 5627 5628 qup_i2c15_default: qup-i2c15-state { 5629 pins = "gpio84", "gpio85"; 5630 function = "qup2_se1"; 5631 }; 5632 5633 qup_i2c16_default: qup-i2c16-state { 5634 pins = "gpio86", "gpio87"; 5635 function = "qup2_se2"; 5636 }; 5637 5638 qup_i2c17_default: qup-i2c17-state { 5639 pins = "gpio91", "gpio92"; 5640 function = "qup2_se3"; 5641 }; 5642 5643 qup_i2c18_default: qup-i2c18-state { 5644 pins = "gpio95", "gpio96"; 5645 function = "qup2_se4"; 5646 }; 5647 5648 qup_i2c19_default: qup-i2c19-state { 5649 pins = "gpio99", "gpio100"; 5650 function = "qup2_se5"; 5651 }; 5652 5653 qup_i2c20_default: qup-i2c20-state { 5654 pins = "gpio97", "gpio98"; 5655 function = "qup2_se6"; 5656 }; 5657 5658 qup_i2c21_default: qup-i2c21-state { 5659 pins = "gpio13", "gpio14"; 5660 function = "qup3_se0"; 5661 }; 5662 5663 qup_spi0_default: qup-spi0-state { 5664 pins = "gpio20", "gpio21", "gpio22", "gpio23"; 5665 function = "qup0_se0"; 5666 }; 5667 5668 qup_spi1_default: qup-spi1-state { 5669 pins = "gpio24", "gpio25", "gpio26", "gpio27"; 5670 function = "qup0_se1"; 5671 }; 5672 5673 qup_spi2_default: qup-spi2-state { 5674 pins = "gpio36", "gpio37", "gpio38", "gpio39"; 5675 function = "qup0_se2"; 5676 }; 5677 5678 qup_spi3_default: qup-spi3-state { 5679 pins = "gpio28", "gpio29", "gpio30", "gpio31"; 5680 function = "qup0_se3"; 5681 }; 5682 5683 qup_spi4_default: qup-spi4-state { 5684 pins = "gpio32", "gpio33", "gpio34", "gpio35"; 5685 function = "qup0_se4"; 5686 }; 5687 5688 qup_spi5_default: qup-spi5-state { 5689 pins = "gpio36", "gpio37", "gpio38", "gpio39"; 5690 function = "qup0_se5"; 5691 }; 5692 5693 qup_spi7_default: qup-spi7-state { 5694 pins = "gpio40", "gpio41", "gpio42", "gpio43"; 5695 function = "qup1_se0"; 5696 }; 5697 5698 qup_spi8_default: qup-spi8-state { 5699 pins = "gpio42", "gpio43", "gpio40", "gpio41"; 5700 function = "qup1_se1"; 5701 }; 5702 5703 qup_spi9_default: qup-spi9-state { 5704 pins = "gpio46", "gpio47", "gpio44", "gpio45"; 5705 function = "qup1_se2"; 5706 }; 5707 5708 qup_spi10_default: qup-spi10-state { 5709 pins = "gpio44", "gpio45", "gpio46", "gpio47"; 5710 function = "qup1_se3"; 5711 }; 5712 5713 qup_spi11_default: qup-spi11-state { 5714 pins = "gpio48", "gpio49", "gpio50", "gpio51"; 5715 function = "qup1_se4"; 5716 }; 5717 5718 qup_spi12_default: qup-spi12-state { 5719 pins = "gpio52", "gpio53", "gpio54", "gpio55"; 5720 function = "qup1_se5"; 5721 }; 5722 5723 qup_spi14_default: qup-spi14-state { 5724 pins = "gpio80", "gpio81", "gpio82", "gpio83"; 5725 function = "qup2_se0"; 5726 }; 5727 5728 qup_spi15_default: qup-spi15-state { 5729 pins = "gpio84", "gpio85", "gpio99", "gpio100"; 5730 function = "qup2_se1"; 5731 }; 5732 5733 qup_spi16_default: qup-spi16-state { 5734 pins = "gpio86", "gpio87", "gpio88", "gpio89"; 5735 function = "qup2_se2"; 5736 }; 5737 5738 qup_spi17_default: qup-spi17-state { 5739 pins = "gpio91", "gpio92", "gpio93", "gpio94"; 5740 function = "qup2_se3"; 5741 }; 5742 5743 qup_spi18_default: qup-spi18-state { 5744 pins = "gpio95", "gpio96", "gpio97", "gpio98"; 5745 function = "qup2_se4"; 5746 }; 5747 5748 qup_spi19_default: qup-spi19-state { 5749 pins = "gpio99", "gpio100", "gpio84", "gpio85"; 5750 function = "qup2_se5"; 5751 }; 5752 5753 qup_spi20_default: qup-spi20-state { 5754 pins = "gpio97", "gpio98", "gpio95", "gpio96"; 5755 function = "qup2_se6"; 5756 }; 5757 5758 qup_spi21_default: qup-spi21-state { 5759 pins = "gpio13", "gpio14", "gpio15", "gpio16"; 5760 function = "qup3_se0"; 5761 }; 5762 5763 qup_uart0_default: qup-uart0-state { 5764 qup_uart0_cts: qup-uart0-cts-pins { 5765 pins = "gpio20"; 5766 function = "qup0_se0"; 5767 }; 5768 5769 qup_uart0_rts: qup-uart0-rts-pins { 5770 pins = "gpio21"; 5771 function = "qup0_se0"; 5772 }; 5773 5774 qup_uart0_tx: qup-uart0-tx-pins { 5775 pins = "gpio22"; 5776 function = "qup0_se0"; 5777 }; 5778 5779 qup_uart0_rx: qup-uart0-rx-pins { 5780 pins = "gpio23"; 5781 function = "qup0_se0"; 5782 }; 5783 }; 5784 5785 qup_uart1_default: qup-uart1-state { 5786 qup_uart1_cts: qup-uart1-cts-pins { 5787 pins = "gpio24"; 5788 function = "qup0_se1"; 5789 }; 5790 5791 qup_uart1_rts: qup-uart1-rts-pins { 5792 pins = "gpio25"; 5793 function = "qup0_se1"; 5794 }; 5795 5796 qup_uart1_tx: qup-uart1-tx-pins { 5797 pins = "gpio26"; 5798 function = "qup0_se1"; 5799 }; 5800 5801 qup_uart1_rx: qup-uart1-rx-pins { 5802 pins = "gpio27"; 5803 function = "qup0_se1"; 5804 }; 5805 }; 5806 5807 qup_uart2_default: qup-uart2-state { 5808 qup_uart2_cts: qup-uart2-cts-pins { 5809 pins = "gpio36"; 5810 function = "qup0_se2"; 5811 }; 5812 5813 qup_uart2_rts: qup-uart2-rts-pins { 5814 pins = "gpio37"; 5815 function = "qup0_se2"; 5816 }; 5817 5818 qup_uart2_tx: qup-uart2-tx-pins { 5819 pins = "gpio38"; 5820 function = "qup0_se2"; 5821 }; 5822 5823 qup_uart2_rx: qup-uart2-rx-pins { 5824 pins = "gpio39"; 5825 function = "qup0_se2"; 5826 }; 5827 }; 5828 5829 qup_uart3_default: qup-uart3-state { 5830 qup_uart3_cts: qup-uart3-cts-pins { 5831 pins = "gpio28"; 5832 function = "qup0_se3"; 5833 }; 5834 5835 qup_uart3_rts: qup-uart3-rts-pins { 5836 pins = "gpio29"; 5837 function = "qup0_se3"; 5838 }; 5839 5840 qup_uart3_tx: qup-uart3-tx-pins { 5841 pins = "gpio30"; 5842 function = "qup0_se3"; 5843 }; 5844 5845 qup_uart3_rx: qup-uart3-rx-pins { 5846 pins = "gpio31"; 5847 function = "qup0_se3"; 5848 }; 5849 }; 5850 5851 qup_uart4_default: qup-uart4-state { 5852 qup_uart4_cts: qup-uart4-cts-pins { 5853 pins = "gpio32"; 5854 function = "qup0_se4"; 5855 }; 5856 5857 qup_uart4_rts: qup-uart4-rts-pins { 5858 pins = "gpio33"; 5859 function = "qup0_se4"; 5860 }; 5861 5862 qup_uart4_tx: qup-uart4-tx-pins { 5863 pins = "gpio34"; 5864 function = "qup0_se4"; 5865 }; 5866 5867 qup_uart4_rx: qup-uart4-rx-pins { 5868 pins = "gpio35"; 5869 function = "qup0_se4"; 5870 }; 5871 }; 5872 5873 qup_uart5_default: qup-uart5-state { 5874 qup_uart5_cts: qup-uart5-cts-pins { 5875 pins = "gpio36"; 5876 function = "qup0_se5"; 5877 }; 5878 5879 qup_uart5_rts: qup-uart5-rts-pins { 5880 pins = "gpio37"; 5881 function = "qup0_se5"; 5882 }; 5883 5884 qup_uart5_tx: qup-uart5-tx-pins { 5885 pins = "gpio38"; 5886 function = "qup0_se5"; 5887 }; 5888 5889 qup_uart5_rx: qup-uart5-rx-pins { 5890 pins = "gpio39"; 5891 function = "qup0_se5"; 5892 }; 5893 }; 5894 5895 qup_uart7_default: qup-uart7-state { 5896 qup_uart7_cts: qup-uart7-cts-pins { 5897 pins = "gpio40"; 5898 function = "qup1_se0"; 5899 }; 5900 5901 qup_uart7_rts: qup-uart7-rts-pins { 5902 pins = "gpio41"; 5903 function = "qup1_se0"; 5904 }; 5905 5906 qup_uart7_tx: qup-uart7-tx-pins { 5907 pins = "gpio42"; 5908 function = "qup1_se0"; 5909 }; 5910 5911 qup_uart7_rx: qup-uart7-rx-pins { 5912 pins = "gpio43"; 5913 function = "qup1_se0"; 5914 }; 5915 }; 5916 5917 qup_uart8_default: qup-uart8-state { 5918 qup_uart8_cts: qup-uart8-cts-pins { 5919 pins = "gpio42"; 5920 function = "qup1_se1"; 5921 }; 5922 5923 qup_uart8_rts: qup-uart8-rts-pins { 5924 pins = "gpio43"; 5925 function = "qup1_se1"; 5926 }; 5927 5928 qup_uart8_tx: qup-uart8-tx-pins { 5929 pins = "gpio40"; 5930 function = "qup1_se1"; 5931 }; 5932 5933 qup_uart8_rx: qup-uart8-rx-pins { 5934 pins = "gpio41"; 5935 function = "qup1_se1"; 5936 }; 5937 }; 5938 5939 qup_uart9_default: qup-uart9-state { 5940 qup_uart9_cts: qup-uart9-cts-pins { 5941 pins = "gpio46"; 5942 function = "qup1_se2"; 5943 }; 5944 5945 qup_uart9_rts: qup-uart9-rts-pins { 5946 pins = "gpio47"; 5947 function = "qup1_se2"; 5948 }; 5949 5950 qup_uart9_tx: qup-uart9-tx-pins { 5951 pins = "gpio44"; 5952 function = "qup1_se2"; 5953 }; 5954 5955 qup_uart9_rx: qup-uart9-rx-pins { 5956 pins = "gpio45"; 5957 function = "qup1_se2"; 5958 }; 5959 }; 5960 5961 qup_uart10_default: qup-uart10-state { 5962 pins = "gpio46", "gpio47"; 5963 function = "qup1_se3"; 5964 }; 5965 5966 qup_uart11_default: qup-uart11-state { 5967 qup_uart11_cts: qup-uart11-cts-pins { 5968 pins = "gpio48"; 5969 function = "qup1_se4"; 5970 }; 5971 5972 qup_uart11_rts: qup-uart11-rts-pins { 5973 pins = "gpio49"; 5974 function = "qup1_se4"; 5975 }; 5976 5977 qup_uart11_tx: qup-uart11-tx-pins { 5978 pins = "gpio50"; 5979 function = "qup1_se4"; 5980 }; 5981 5982 qup_uart11_rx: qup-uart11-rx-pins { 5983 pins = "gpio51"; 5984 function = "qup1_se4"; 5985 }; 5986 }; 5987 5988 qup_uart12_default: qup-uart12-state { 5989 qup_uart12_cts: qup-uart12-cts-pins { 5990 pins = "gpio52"; 5991 function = "qup1_se5"; 5992 }; 5993 5994 qup_uart12_rts: qup-uart12-rts-pins { 5995 pins = "gpio53"; 5996 function = "qup1_se5"; 5997 }; 5998 5999 qup_uart12_tx: qup-uart12-tx-pins { 6000 pins = "gpio54"; 6001 function = "qup1_se5"; 6002 }; 6003 6004 qup_uart12_rx: qup-uart12-rx-pins { 6005 pins = "gpio55"; 6006 function = "qup1_se5"; 6007 }; 6008 }; 6009 6010 qup_uart14_default: qup-uart14-state { 6011 qup_uart14_cts: qup-uart14-cts-pins { 6012 pins = "gpio80"; 6013 function = "qup2_se0"; 6014 }; 6015 6016 qup_uart14_rts: qup-uart14-rts-pins { 6017 pins = "gpio81"; 6018 function = "qup2_se0"; 6019 }; 6020 6021 qup_uart14_tx: qup-uart14-tx-pins { 6022 pins = "gpio82"; 6023 function = "qup2_se0"; 6024 }; 6025 6026 qup_uart14_rx: qup-uart14-rx-pins { 6027 pins = "gpio83"; 6028 function = "qup2_se0"; 6029 }; 6030 }; 6031 6032 qup_uart15_default: qup-uart15-state { 6033 qup_uart15_cts: qup-uart15-cts-pins { 6034 pins = "gpio84"; 6035 function = "qup2_se1"; 6036 }; 6037 6038 qup_uart15_rts: qup-uart15-rts-pins { 6039 pins = "gpio85"; 6040 function = "qup2_se1"; 6041 }; 6042 6043 qup_uart15_tx: qup-uart15-tx-pins { 6044 pins = "gpio99"; 6045 function = "qup2_se1"; 6046 }; 6047 6048 qup_uart15_rx: qup-uart15-rx-pins { 6049 pins = "gpio100"; 6050 function = "qup2_se1"; 6051 }; 6052 }; 6053 6054 qup_uart16_default: qup-uart16-state { 6055 qup_uart16_cts: qup-uart16-cts-pins { 6056 pins = "gpio86"; 6057 function = "qup2_se2"; 6058 }; 6059 6060 qup_uart16_rts: qup-uart16-rts-pins { 6061 pins = "gpio87"; 6062 function = "qup2_se2"; 6063 }; 6064 6065 qup_uart16_tx: qup-uart16-tx-pins { 6066 pins = "gpio88"; 6067 function = "qup2_se2"; 6068 }; 6069 6070 qup_uart16_rx: qup-uart16-rx-pins { 6071 pins = "gpio89"; 6072 function = "qup2_se2"; 6073 }; 6074 }; 6075 6076 qup_uart17_default: qup-uart17-state { 6077 qup_uart17_cts: qup-uart17-cts-pins { 6078 pins = "gpio91"; 6079 function = "qup2_se3"; 6080 }; 6081 6082 qup_uart17_rts: qup0-uart17-rts-pins { 6083 pins = "gpio92"; 6084 function = "qup2_se3"; 6085 }; 6086 6087 qup_uart17_tx: qup0-uart17-tx-pins { 6088 pins = "gpio93"; 6089 function = "qup2_se3"; 6090 }; 6091 6092 qup_uart17_rx: qup0-uart17-rx-pins { 6093 pins = "gpio94"; 6094 function = "qup2_se3"; 6095 }; 6096 }; 6097 6098 qup_uart18_default: qup-uart18-state { 6099 qup_uart18_cts: qup-uart18-cts-pins { 6100 pins = "gpio95"; 6101 function = "qup2_se4"; 6102 }; 6103 6104 qup_uart18_rts: qup-uart18-rts-pins { 6105 pins = "gpio96"; 6106 function = "qup2_se4"; 6107 }; 6108 6109 qup_uart18_tx: qup-uart18-tx-pins { 6110 pins = "gpio97"; 6111 function = "qup2_se4"; 6112 }; 6113 6114 qup_uart18_rx: qup-uart18-rx-pins { 6115 pins = "gpio98"; 6116 function = "qup2_se4"; 6117 }; 6118 }; 6119 6120 qup_uart19_default: qup-uart19-state { 6121 qup_uart19_cts: qup-uart19-cts-pins { 6122 pins = "gpio99"; 6123 function = "qup2_se5"; 6124 }; 6125 6126 qup_uart19_rts: qup-uart19-rts-pins { 6127 pins = "gpio100"; 6128 function = "qup2_se5"; 6129 }; 6130 6131 qup_uart19_tx: qup-uart19-tx-pins { 6132 pins = "gpio84"; 6133 function = "qup2_se5"; 6134 }; 6135 6136 qup_uart19_rx: qup-uart19-rx-pins { 6137 pins = "gpio85"; 6138 function = "qup2_se5"; 6139 }; 6140 }; 6141 6142 qup_uart20_default: qup-uart20-state { 6143 qup_uart20_cts: qup-uart20-cts-pins { 6144 pins = "gpio97"; 6145 function = "qup2_se6"; 6146 }; 6147 6148 qup_uart20_rts: qup-uart20-rts-pins { 6149 pins = "gpio98"; 6150 function = "qup2_se6"; 6151 }; 6152 6153 qup_uart20_tx: qup-uart20-tx-pins { 6154 pins = "gpio95"; 6155 function = "qup2_se6"; 6156 }; 6157 6158 qup_uart20_rx: qup-uart20-rx-pins { 6159 pins = "gpio96"; 6160 function = "qup2_se6"; 6161 }; 6162 }; 6163 6164 qup_uart21_default: qup-uart21-state { 6165 qup_uart21_cts: qup-uart21-cts-pins { 6166 pins = "gpio13"; 6167 function = "qup3_se0"; 6168 }; 6169 6170 qup_uart21_rts: qup-uart21-rts-pins { 6171 pins = "gpio14"; 6172 function = "qup3_se0"; 6173 }; 6174 6175 qup_uart21_tx: qup-uart21-tx-pins { 6176 pins = "gpio15"; 6177 function = "qup3_se0"; 6178 }; 6179 6180 qup_uart21_rx: qup-uart21-rx-pins { 6181 pins = "gpio16"; 6182 function = "qup3_se0"; 6183 }; 6184 }; 6185 6186 sdc_default: sdc-default-state { 6187 clk-pins { 6188 pins = "sdc1_clk"; 6189 drive-strength = <16>; 6190 bias-disable; 6191 }; 6192 6193 cmd-pins { 6194 pins = "sdc1_cmd"; 6195 drive-strength = <10>; 6196 bias-pull-up; 6197 }; 6198 6199 data-pins { 6200 pins = "sdc1_data"; 6201 drive-strength = <10>; 6202 bias-pull-up; 6203 }; 6204 }; 6205 6206 sdc_sleep: sdc-sleep-state { 6207 clk-pins { 6208 pins = "sdc1_clk"; 6209 drive-strength = <2>; 6210 bias-bus-hold; 6211 }; 6212 6213 cmd-pins { 6214 pins = "sdc1_cmd"; 6215 drive-strength = <2>; 6216 bias-bus-hold; 6217 }; 6218 6219 data-pins { 6220 pins = "sdc1_data"; 6221 drive-strength = <2>; 6222 bias-bus-hold; 6223 }; 6224 }; 6225 }; 6226 6227 sram: sram@146d8000 { 6228 compatible = "qcom,sa8775p-imem", "syscon", "simple-mfd"; 6229 reg = <0x0 0x146d8000 0x0 0x1000>; 6230 ranges = <0x0 0x0 0x146d8000 0x1000>; 6231 6232 #address-cells = <1>; 6233 #size-cells = <1>; 6234 6235 pil-reloc@94c { 6236 compatible = "qcom,pil-reloc-info"; 6237 reg = <0x94c 0xc8>; 6238 }; 6239 }; 6240 6241 apps_smmu: iommu@15000000 { 6242 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 6243 reg = <0x0 0x15000000 0x0 0x100000>; 6244 #iommu-cells = <2>; 6245 #global-interrupts = <2>; 6246 dma-coherent; 6247 6248 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 6249 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 6250 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 6251 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 6252 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 6253 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 6254 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 6255 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 6256 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 6257 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 6258 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 6259 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 6260 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 6261 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 6262 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 6263 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 6264 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 6265 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 6266 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 6267 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 6268 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 6269 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 6270 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 6271 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 6272 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 6273 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 6274 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 6275 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 6276 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 6277 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 6278 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 6279 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 6280 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 6281 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 6282 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 6283 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 6284 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 6285 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 6286 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 6287 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 6288 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 6289 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 6290 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 6291 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 6292 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 6293 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 6294 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 6295 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 6296 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 6297 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 6298 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 6299 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 6300 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 6301 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 6302 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 6303 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 6304 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 6305 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 6306 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 6307 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 6308 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 6309 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 6310 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 6311 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 6312 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 6313 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 6314 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 6315 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 6316 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 6317 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 6318 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 6319 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 6320 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 6321 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 6322 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 6323 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 6324 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 6325 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 6326 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 6327 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 6328 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 6329 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 6330 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 6331 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 6332 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 6333 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 6334 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 6335 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 6336 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 6337 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 6338 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 6339 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 6340 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 6341 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 6342 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 6343 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 6344 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 6345 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 6346 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 6347 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 6348 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 6349 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 6350 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 6351 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 6352 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 6353 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 6354 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 6355 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 6356 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 6357 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 6358 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 6359 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 6360 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 6361 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 6362 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 6363 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 6364 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 6365 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 6366 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 6367 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 6368 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 6369 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 6370 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 6371 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 6372 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 6373 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 6374 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 6375 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 6376 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 6377 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; 6378 }; 6379 6380 pcie_smmu: iommu@15200000 { 6381 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 6382 reg = <0x0 0x15200000 0x0 0x80000>; 6383 #iommu-cells = <2>; 6384 #global-interrupts = <2>; 6385 dma-coherent; 6386 6387 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, 6388 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, 6389 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, 6390 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, 6391 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, 6392 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, 6393 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 6394 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 6395 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, 6396 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, 6397 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, 6398 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, 6399 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, 6400 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, 6401 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, 6402 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 6403 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, 6404 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 6405 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, 6406 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, 6407 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, 6408 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, 6409 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 6410 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 6411 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 6412 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 6413 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 6414 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 6415 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 6416 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 6417 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 6418 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 6419 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 6420 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 6421 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 6422 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 6423 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 6424 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 6425 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 6426 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 6427 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 6428 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 6429 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 6430 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 6431 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 6432 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 6433 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 6434 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, 6435 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, 6436 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 6437 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 6438 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 6439 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 6440 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 6441 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 6442 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 6443 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 6444 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 6445 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 6446 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 6447 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 6448 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 6449 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 6450 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, 6451 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 6452 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 6453 }; 6454 6455 intc: interrupt-controller@17a00000 { 6456 compatible = "arm,gic-v3"; 6457 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 6458 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 6459 interrupt-controller; 6460 #address-cells = <0>; 6461 #interrupt-cells = <3>; 6462 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 6463 #redistributor-regions = <1>; 6464 redistributor-stride = <0x0 0x20000>; 6465 }; 6466 6467 watchdog@17c10000 { 6468 compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt"; 6469 reg = <0x0 0x17c10000 0x0 0x1000>; 6470 clocks = <&sleep_clk>; 6471 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 6472 }; 6473 6474 memtimer: timer@17c20000 { 6475 compatible = "arm,armv7-timer-mem"; 6476 reg = <0x0 0x17c20000 0x0 0x1000>; 6477 ranges = <0x0 0x0 0x0 0x20000000>; 6478 #address-cells = <1>; 6479 #size-cells = <1>; 6480 6481 frame@17c21000 { 6482 reg = <0x17c21000 0x1000>, 6483 <0x17c22000 0x1000>; 6484 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6485 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6486 frame-number = <0>; 6487 }; 6488 6489 frame@17c23000 { 6490 reg = <0x17c23000 0x1000>; 6491 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6492 frame-number = <1>; 6493 status = "disabled"; 6494 }; 6495 6496 frame@17c25000 { 6497 reg = <0x17c25000 0x1000>; 6498 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6499 frame-number = <2>; 6500 status = "disabled"; 6501 }; 6502 6503 frame@17c27000 { 6504 reg = <0x17c27000 0x1000>; 6505 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6506 frame-number = <3>; 6507 status = "disabled"; 6508 }; 6509 6510 frame@17c29000 { 6511 reg = <0x17c29000 0x1000>; 6512 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6513 frame-number = <4>; 6514 status = "disabled"; 6515 }; 6516 6517 frame@17c2b000 { 6518 reg = <0x17c2b000 0x1000>; 6519 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6520 frame-number = <5>; 6521 status = "disabled"; 6522 }; 6523 6524 frame@17c2d000 { 6525 reg = <0x17c2d000 0x1000>; 6526 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6527 frame-number = <6>; 6528 status = "disabled"; 6529 }; 6530 }; 6531 6532 apps_rsc: rsc@18200000 { 6533 compatible = "qcom,rpmh-rsc"; 6534 reg = <0x0 0x18200000 0x0 0x10000>, 6535 <0x0 0x18210000 0x0 0x10000>, 6536 <0x0 0x18220000 0x0 0x10000>; 6537 reg-names = "drv-0", "drv-1", "drv-2"; 6538 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 6539 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 6540 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 6541 qcom,tcs-offset = <0xd00>; 6542 qcom,drv-id = <2>; 6543 qcom,tcs-config = <ACTIVE_TCS 2>, 6544 <SLEEP_TCS 3>, 6545 <WAKE_TCS 3>, 6546 <CONTROL_TCS 0>; 6547 label = "apps_rsc"; 6548 power-domains = <&system_pd>; 6549 6550 apps_bcm_voter: bcm-voter { 6551 compatible = "qcom,bcm-voter"; 6552 }; 6553 6554 rpmhcc: clock-controller { 6555 compatible = "qcom,sa8775p-rpmh-clk"; 6556 #clock-cells = <1>; 6557 clock-names = "xo"; 6558 clocks = <&xo_board_clk>; 6559 }; 6560 6561 rpmhpd: power-controller { 6562 compatible = "qcom,sa8775p-rpmhpd"; 6563 #power-domain-cells = <1>; 6564 operating-points-v2 = <&rpmhpd_opp_table>; 6565 6566 rpmhpd_opp_table: opp-table { 6567 compatible = "operating-points-v2"; 6568 6569 rpmhpd_opp_ret: opp-0 { 6570 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 6571 }; 6572 6573 rpmhpd_opp_min_svs: opp-1 { 6574 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 6575 }; 6576 6577 rpmhpd_opp_low_svs: opp2 { 6578 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 6579 }; 6580 6581 rpmhpd_opp_svs: opp3 { 6582 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 6583 }; 6584 6585 rpmhpd_opp_svs_l1: opp-4 { 6586 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 6587 }; 6588 6589 rpmhpd_opp_nom: opp-5 { 6590 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 6591 }; 6592 6593 rpmhpd_opp_nom_l1: opp-6 { 6594 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 6595 }; 6596 6597 rpmhpd_opp_nom_l2: opp-7 { 6598 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 6599 }; 6600 6601 rpmhpd_opp_turbo: opp-8 { 6602 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6603 }; 6604 6605 rpmhpd_opp_turbo_l1: opp-9 { 6606 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6607 }; 6608 }; 6609 }; 6610 }; 6611 6612 epss_l3_cl0: interconnect@18590000 { 6613 compatible = "qcom,sa8775p-epss-l3", 6614 "qcom,epss-l3"; 6615 reg = <0x0 0x18590000 0x0 0x1000>; 6616 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6617 clock-names = "xo", "alternate"; 6618 #interconnect-cells = <1>; 6619 }; 6620 6621 cpufreq_hw: cpufreq@18591000 { 6622 compatible = "qcom,sa8775p-cpufreq-epss", 6623 "qcom,cpufreq-epss"; 6624 reg = <0x0 0x18591000 0x0 0x1000>, 6625 <0x0 0x18593000 0x0 0x1000>; 6626 reg-names = "freq-domain0", "freq-domain1"; 6627 6628 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 6629 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 6630 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; 6631 6632 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6633 clock-names = "xo", "alternate"; 6634 6635 #freq-domain-cells = <1>; 6636 }; 6637 6638 epss_l3_cl1: interconnect@18592000 { 6639 compatible = "qcom,sa8775p-epss-l3", 6640 "qcom,epss-l3"; 6641 reg = <0x0 0x18592000 0x0 0x1000>; 6642 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6643 clock-names = "xo", "alternate"; 6644 #interconnect-cells = <1>; 6645 }; 6646 6647 remoteproc_gpdsp0: remoteproc@20c00000 { 6648 compatible = "qcom,sa8775p-gpdsp0-pas"; 6649 reg = <0x0 0x20c00000 0x0 0x10000>; 6650 6651 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 6652 <&smp2p_gpdsp0_in 0 0>, 6653 <&smp2p_gpdsp0_in 1 0>, 6654 <&smp2p_gpdsp0_in 2 0>, 6655 <&smp2p_gpdsp0_in 3 0>; 6656 interrupt-names = "wdog", "fatal", "ready", 6657 "handover", "stop-ack"; 6658 6659 clocks = <&rpmhcc RPMH_CXO_CLK>; 6660 clock-names = "xo"; 6661 6662 power-domains = <&rpmhpd SA8775P_CX>, 6663 <&rpmhpd SA8775P_MXC>; 6664 power-domain-names = "cx", "mxc"; 6665 6666 interconnects = <&gpdsp_anoc MASTER_DSP0 0 6667 &config_noc SLAVE_CLK_CTL 0>; 6668 6669 memory-region = <&pil_gdsp0_mem>; 6670 6671 qcom,qmp = <&aoss_qmp>; 6672 6673 qcom,smem-states = <&smp2p_gpdsp0_out 0>; 6674 qcom,smem-state-names = "stop"; 6675 6676 status = "disabled"; 6677 6678 glink-edge { 6679 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 6680 IPCC_MPROC_SIGNAL_GLINK_QMP 6681 IRQ_TYPE_EDGE_RISING>; 6682 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 6683 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6684 6685 label = "gpdsp0"; 6686 qcom,remote-pid = <17>; 6687 6688 fastrpc { 6689 compatible = "qcom,fastrpc"; 6690 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6691 label = "gdsp0"; 6692 #address-cells = <1>; 6693 #size-cells = <0>; 6694 6695 compute-cb@1 { 6696 compatible = "qcom,fastrpc-compute-cb"; 6697 reg = <1>; 6698 iommus = <&apps_smmu 0x38a1 0x0>; 6699 dma-coherent; 6700 }; 6701 6702 compute-cb@2 { 6703 compatible = "qcom,fastrpc-compute-cb"; 6704 reg = <2>; 6705 iommus = <&apps_smmu 0x38a2 0x0>; 6706 dma-coherent; 6707 }; 6708 6709 compute-cb@3 { 6710 compatible = "qcom,fastrpc-compute-cb"; 6711 reg = <3>; 6712 iommus = <&apps_smmu 0x38a3 0x0>; 6713 dma-coherent; 6714 }; 6715 }; 6716 }; 6717 }; 6718 6719 remoteproc_gpdsp1: remoteproc@21c00000 { 6720 compatible = "qcom,sa8775p-gpdsp1-pas"; 6721 reg = <0x0 0x21c00000 0x0 0x10000>; 6722 6723 interrupts-extended = <&intc GIC_SPI 624 IRQ_TYPE_EDGE_RISING>, 6724 <&smp2p_gpdsp1_in 0 0>, 6725 <&smp2p_gpdsp1_in 1 0>, 6726 <&smp2p_gpdsp1_in 2 0>, 6727 <&smp2p_gpdsp1_in 3 0>; 6728 interrupt-names = "wdog", "fatal", "ready", 6729 "handover", "stop-ack"; 6730 6731 clocks = <&rpmhcc RPMH_CXO_CLK>; 6732 clock-names = "xo"; 6733 6734 power-domains = <&rpmhpd SA8775P_CX>, 6735 <&rpmhpd SA8775P_MXC>; 6736 power-domain-names = "cx", "mxc"; 6737 6738 interconnects = <&gpdsp_anoc MASTER_DSP1 0 6739 &config_noc SLAVE_CLK_CTL 0>; 6740 6741 memory-region = <&pil_gdsp1_mem>; 6742 6743 qcom,qmp = <&aoss_qmp>; 6744 6745 qcom,smem-states = <&smp2p_gpdsp1_out 0>; 6746 qcom,smem-state-names = "stop"; 6747 6748 status = "disabled"; 6749 6750 glink-edge { 6751 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 6752 IPCC_MPROC_SIGNAL_GLINK_QMP 6753 IRQ_TYPE_EDGE_RISING>; 6754 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 6755 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6756 6757 label = "gpdsp1"; 6758 qcom,remote-pid = <18>; 6759 6760 fastrpc { 6761 compatible = "qcom,fastrpc"; 6762 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6763 label = "gdsp1"; 6764 #address-cells = <1>; 6765 #size-cells = <0>; 6766 6767 compute-cb@1 { 6768 compatible = "qcom,fastrpc-compute-cb"; 6769 reg = <1>; 6770 iommus = <&apps_smmu 0x38c1 0x0>; 6771 dma-coherent; 6772 }; 6773 6774 compute-cb@2 { 6775 compatible = "qcom,fastrpc-compute-cb"; 6776 reg = <2>; 6777 iommus = <&apps_smmu 0x38c2 0x0>; 6778 dma-coherent; 6779 }; 6780 6781 compute-cb@3 { 6782 compatible = "qcom,fastrpc-compute-cb"; 6783 reg = <3>; 6784 iommus = <&apps_smmu 0x38c3 0x0>; 6785 dma-coherent; 6786 }; 6787 }; 6788 }; 6789 }; 6790 6791 dispcc1: clock-controller@22100000 { 6792 compatible = "qcom,sa8775p-dispcc1"; 6793 reg = <0x0 0x22100000 0x0 0x20000>; 6794 clocks = <&gcc GCC_DISP_AHB_CLK>, 6795 <&rpmhcc RPMH_CXO_CLK>, 6796 <&rpmhcc RPMH_CXO_CLK_A>, 6797 <&sleep_clk>, 6798 <0>, <0>, <0>, <0>, 6799 <0>, <0>, <0>, <0>; 6800 power-domains = <&rpmhpd SA8775P_MMCX>; 6801 #clock-cells = <1>; 6802 #reset-cells = <1>; 6803 #power-domain-cells = <1>; 6804 status = "disabled"; 6805 }; 6806 6807 ethernet1: ethernet@23000000 { 6808 compatible = "qcom,sa8775p-ethqos"; 6809 reg = <0x0 0x23000000 0x0 0x10000>, 6810 <0x0 0x23016000 0x0 0x100>; 6811 reg-names = "stmmaceth", "rgmii"; 6812 6813 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 6814 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>; 6815 interrupt-names = "macirq", "sfty"; 6816 6817 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 6818 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 6819 <&gcc GCC_EMAC1_PTP_CLK>, 6820 <&gcc GCC_EMAC1_PHY_AUX_CLK>; 6821 clock-names = "stmmaceth", 6822 "pclk", 6823 "ptp_ref", 6824 "phyaux"; 6825 6826 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 6827 &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>, 6828 <&aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS 6829 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 6830 interconnect-names = "cpu-mac", 6831 "mac-mem"; 6832 6833 power-domains = <&gcc EMAC1_GDSC>; 6834 6835 phys = <&serdes1>; 6836 phy-names = "serdes"; 6837 6838 iommus = <&apps_smmu 0x140 0xf>; 6839 dma-coherent; 6840 6841 snps,tso; 6842 snps,pbl = <32>; 6843 rx-fifo-depth = <16384>; 6844 tx-fifo-depth = <16384>; 6845 6846 status = "disabled"; 6847 }; 6848 6849 ethernet0: ethernet@23040000 { 6850 compatible = "qcom,sa8775p-ethqos"; 6851 reg = <0x0 0x23040000 0x0 0x10000>, 6852 <0x0 0x23056000 0x0 0x100>; 6853 reg-names = "stmmaceth", "rgmii"; 6854 6855 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 6856 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>; 6857 interrupt-names = "macirq", "sfty"; 6858 6859 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 6860 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 6861 <&gcc GCC_EMAC0_PTP_CLK>, 6862 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 6863 clock-names = "stmmaceth", 6864 "pclk", 6865 "ptp_ref", 6866 "phyaux"; 6867 6868 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 6869 &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>, 6870 <&aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS 6871 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 6872 interconnect-names = "cpu-mac", 6873 "mac-mem"; 6874 6875 power-domains = <&gcc EMAC0_GDSC>; 6876 6877 phys = <&serdes0>; 6878 phy-names = "serdes"; 6879 6880 iommus = <&apps_smmu 0x120 0xf>; 6881 dma-coherent; 6882 6883 snps,tso; 6884 snps,pbl = <32>; 6885 rx-fifo-depth = <16384>; 6886 tx-fifo-depth = <16384>; 6887 6888 status = "disabled"; 6889 }; 6890 6891 remoteproc_cdsp0: remoteproc@26300000 { 6892 compatible = "qcom,sa8775p-cdsp0-pas"; 6893 reg = <0x0 0x26300000 0x0 0x10000>; 6894 6895 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 6896 <&smp2p_cdsp0_in 0 IRQ_TYPE_EDGE_RISING>, 6897 <&smp2p_cdsp0_in 1 IRQ_TYPE_EDGE_RISING>, 6898 <&smp2p_cdsp0_in 2 IRQ_TYPE_EDGE_RISING>, 6899 <&smp2p_cdsp0_in 3 IRQ_TYPE_EDGE_RISING>; 6900 interrupt-names = "wdog", "fatal", "ready", 6901 "handover", "stop-ack"; 6902 6903 clocks = <&rpmhcc RPMH_CXO_CLK>; 6904 clock-names = "xo"; 6905 6906 power-domains = <&rpmhpd SA8775P_CX>, 6907 <&rpmhpd SA8775P_MXC>, 6908 <&rpmhpd SA8775P_NSP0>; 6909 power-domain-names = "cx", "mxc", "nsp"; 6910 6911 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 6912 &mc_virt SLAVE_EBI1 0>; 6913 6914 memory-region = <&pil_cdsp0_mem>; 6915 6916 qcom,qmp = <&aoss_qmp>; 6917 6918 qcom,smem-states = <&smp2p_cdsp0_out 0>; 6919 qcom,smem-state-names = "stop"; 6920 6921 status = "disabled"; 6922 6923 glink-edge { 6924 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 6925 IPCC_MPROC_SIGNAL_GLINK_QMP 6926 IRQ_TYPE_EDGE_RISING>; 6927 mboxes = <&ipcc IPCC_CLIENT_CDSP 6928 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6929 6930 label = "cdsp"; 6931 qcom,remote-pid = <5>; 6932 6933 fastrpc { 6934 compatible = "qcom,fastrpc"; 6935 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6936 label = "cdsp"; 6937 #address-cells = <1>; 6938 #size-cells = <0>; 6939 6940 compute-cb@1 { 6941 compatible = "qcom,fastrpc-compute-cb"; 6942 reg = <1>; 6943 iommus = <&apps_smmu 0x2141 0x04a0>, 6944 <&apps_smmu 0x2181 0x0400>; 6945 dma-coherent; 6946 }; 6947 6948 compute-cb@2 { 6949 compatible = "qcom,fastrpc-compute-cb"; 6950 reg = <2>; 6951 iommus = <&apps_smmu 0x2142 0x04a0>, 6952 <&apps_smmu 0x2182 0x0400>; 6953 dma-coherent; 6954 }; 6955 6956 compute-cb@3 { 6957 compatible = "qcom,fastrpc-compute-cb"; 6958 reg = <3>; 6959 iommus = <&apps_smmu 0x2143 0x04a0>, 6960 <&apps_smmu 0x2183 0x0400>; 6961 dma-coherent; 6962 }; 6963 6964 compute-cb@4 { 6965 compatible = "qcom,fastrpc-compute-cb"; 6966 reg = <4>; 6967 iommus = <&apps_smmu 0x2144 0x04a0>, 6968 <&apps_smmu 0x2184 0x0400>; 6969 dma-coherent; 6970 }; 6971 6972 compute-cb@5 { 6973 compatible = "qcom,fastrpc-compute-cb"; 6974 reg = <5>; 6975 iommus = <&apps_smmu 0x2145 0x04a0>, 6976 <&apps_smmu 0x2185 0x0400>; 6977 dma-coherent; 6978 }; 6979 6980 compute-cb@6 { 6981 compatible = "qcom,fastrpc-compute-cb"; 6982 reg = <6>; 6983 iommus = <&apps_smmu 0x2146 0x04a0>, 6984 <&apps_smmu 0x2186 0x0400>; 6985 dma-coherent; 6986 }; 6987 6988 compute-cb@7 { 6989 compatible = "qcom,fastrpc-compute-cb"; 6990 reg = <7>; 6991 iommus = <&apps_smmu 0x2147 0x04a0>, 6992 <&apps_smmu 0x2187 0x0400>; 6993 dma-coherent; 6994 }; 6995 6996 compute-cb@8 { 6997 compatible = "qcom,fastrpc-compute-cb"; 6998 reg = <8>; 6999 iommus = <&apps_smmu 0x2148 0x04a0>, 7000 <&apps_smmu 0x2188 0x0400>; 7001 dma-coherent; 7002 }; 7003 7004 compute-cb@9 { 7005 compatible = "qcom,fastrpc-compute-cb"; 7006 reg = <9>; 7007 iommus = <&apps_smmu 0x2149 0x04a0>, 7008 <&apps_smmu 0x2189 0x0400>; 7009 dma-coherent; 7010 }; 7011 7012 compute-cb@11 { 7013 compatible = "qcom,fastrpc-compute-cb"; 7014 reg = <11>; 7015 iommus = <&apps_smmu 0x214b 0x04a0>, 7016 <&apps_smmu 0x218b 0x0400>; 7017 dma-coherent; 7018 }; 7019 }; 7020 }; 7021 }; 7022 7023 remoteproc_cdsp1: remoteproc@2a300000 { 7024 compatible = "qcom,sa8775p-cdsp1-pas"; 7025 reg = <0x0 0x2A300000 0x0 0x10000>; 7026 7027 interrupts-extended = <&intc GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 7028 <&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>, 7029 <&smp2p_cdsp1_in 1 IRQ_TYPE_EDGE_RISING>, 7030 <&smp2p_cdsp1_in 2 IRQ_TYPE_EDGE_RISING>, 7031 <&smp2p_cdsp1_in 3 IRQ_TYPE_EDGE_RISING>; 7032 interrupt-names = "wdog", "fatal", "ready", 7033 "handover", "stop-ack"; 7034 7035 clocks = <&rpmhcc RPMH_CXO_CLK>; 7036 clock-names = "xo"; 7037 7038 power-domains = <&rpmhpd SA8775P_CX>, 7039 <&rpmhpd SA8775P_MXC>, 7040 <&rpmhpd SA8775P_NSP1>; 7041 power-domain-names = "cx", "mxc", "nsp"; 7042 7043 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 7044 &mc_virt SLAVE_EBI1 0>; 7045 7046 memory-region = <&pil_cdsp1_mem>; 7047 7048 qcom,qmp = <&aoss_qmp>; 7049 7050 qcom,smem-states = <&smp2p_cdsp1_out 0>; 7051 qcom,smem-state-names = "stop"; 7052 7053 status = "disabled"; 7054 7055 glink-edge { 7056 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 7057 IPCC_MPROC_SIGNAL_GLINK_QMP 7058 IRQ_TYPE_EDGE_RISING>; 7059 mboxes = <&ipcc IPCC_CLIENT_NSP1 7060 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7061 7062 label = "cdsp"; 7063 qcom,remote-pid = <12>; 7064 7065 fastrpc { 7066 compatible = "qcom,fastrpc"; 7067 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7068 label = "cdsp1"; 7069 #address-cells = <1>; 7070 #size-cells = <0>; 7071 7072 compute-cb@1 { 7073 compatible = "qcom,fastrpc-compute-cb"; 7074 reg = <1>; 7075 iommus = <&apps_smmu 0x2941 0x04a0>, 7076 <&apps_smmu 0x2981 0x0400>; 7077 dma-coherent; 7078 }; 7079 7080 compute-cb@2 { 7081 compatible = "qcom,fastrpc-compute-cb"; 7082 reg = <2>; 7083 iommus = <&apps_smmu 0x2942 0x04a0>, 7084 <&apps_smmu 0x2982 0x0400>; 7085 dma-coherent; 7086 }; 7087 7088 compute-cb@3 { 7089 compatible = "qcom,fastrpc-compute-cb"; 7090 reg = <3>; 7091 iommus = <&apps_smmu 0x2943 0x04a0>, 7092 <&apps_smmu 0x2983 0x0400>; 7093 dma-coherent; 7094 }; 7095 7096 compute-cb@4 { 7097 compatible = "qcom,fastrpc-compute-cb"; 7098 reg = <4>; 7099 iommus = <&apps_smmu 0x2944 0x04a0>, 7100 <&apps_smmu 0x2984 0x0400>; 7101 dma-coherent; 7102 }; 7103 7104 compute-cb@5 { 7105 compatible = "qcom,fastrpc-compute-cb"; 7106 reg = <5>; 7107 iommus = <&apps_smmu 0x2945 0x04a0>, 7108 <&apps_smmu 0x2985 0x0400>; 7109 dma-coherent; 7110 }; 7111 7112 compute-cb@6 { 7113 compatible = "qcom,fastrpc-compute-cb"; 7114 reg = <6>; 7115 iommus = <&apps_smmu 0x2946 0x04a0>, 7116 <&apps_smmu 0x2986 0x0400>; 7117 dma-coherent; 7118 }; 7119 7120 compute-cb@7 { 7121 compatible = "qcom,fastrpc-compute-cb"; 7122 reg = <7>; 7123 iommus = <&apps_smmu 0x2947 0x04a0>, 7124 <&apps_smmu 0x2987 0x0400>; 7125 dma-coherent; 7126 }; 7127 7128 compute-cb@8 { 7129 compatible = "qcom,fastrpc-compute-cb"; 7130 reg = <8>; 7131 iommus = <&apps_smmu 0x2948 0x04a0>, 7132 <&apps_smmu 0x2988 0x0400>; 7133 dma-coherent; 7134 }; 7135 7136 compute-cb@9 { 7137 compatible = "qcom,fastrpc-compute-cb"; 7138 reg = <9>; 7139 iommus = <&apps_smmu 0x2949 0x04a0>, 7140 <&apps_smmu 0x2989 0x0400>; 7141 dma-coherent; 7142 }; 7143 7144 compute-cb@10 { 7145 compatible = "qcom,fastrpc-compute-cb"; 7146 reg = <10>; 7147 iommus = <&apps_smmu 0x294a 0x04a0>, 7148 <&apps_smmu 0x298a 0x0400>; 7149 dma-coherent; 7150 }; 7151 7152 compute-cb@11 { 7153 compatible = "qcom,fastrpc-compute-cb"; 7154 reg = <11>; 7155 iommus = <&apps_smmu 0x294b 0x04a0>, 7156 <&apps_smmu 0x298b 0x0400>; 7157 dma-coherent; 7158 }; 7159 7160 compute-cb@12 { 7161 compatible = "qcom,fastrpc-compute-cb"; 7162 reg = <12>; 7163 iommus = <&apps_smmu 0x294c 0x04a0>, 7164 <&apps_smmu 0x298c 0x0400>; 7165 dma-coherent; 7166 }; 7167 7168 compute-cb@13 { 7169 compatible = "qcom,fastrpc-compute-cb"; 7170 reg = <13>; 7171 iommus = <&apps_smmu 0x294d 0x04a0>, 7172 <&apps_smmu 0x298d 0x0400>; 7173 dma-coherent; 7174 }; 7175 }; 7176 }; 7177 }; 7178 7179 remoteproc_adsp: remoteproc@30000000 { 7180 compatible = "qcom,sa8775p-adsp-pas"; 7181 reg = <0x0 0x30000000 0x0 0x100>; 7182 7183 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 7184 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 7185 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 7186 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 7187 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 7188 interrupt-names = "wdog", "fatal", "ready", "handover", 7189 "stop-ack"; 7190 7191 clocks = <&rpmhcc RPMH_CXO_CLK>; 7192 clock-names = "xo"; 7193 7194 power-domains = <&rpmhpd SA8775P_LCX>, 7195 <&rpmhpd SA8775P_LMX>; 7196 power-domain-names = "lcx", "lmx"; 7197 7198 interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 7199 7200 memory-region = <&pil_adsp_mem>; 7201 7202 qcom,qmp = <&aoss_qmp>; 7203 7204 qcom,smem-states = <&smp2p_adsp_out 0>; 7205 qcom,smem-state-names = "stop"; 7206 7207 status = "disabled"; 7208 7209 remoteproc_adsp_glink: glink-edge { 7210 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 7211 IPCC_MPROC_SIGNAL_GLINK_QMP 7212 IRQ_TYPE_EDGE_RISING>; 7213 mboxes = <&ipcc IPCC_CLIENT_LPASS 7214 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7215 7216 label = "lpass"; 7217 qcom,remote-pid = <2>; 7218 7219 fastrpc { 7220 compatible = "qcom,fastrpc"; 7221 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7222 label = "adsp"; 7223 memory-region = <&adsp_rpc_remote_heap_mem>; 7224 qcom,vmids = <QCOM_SCM_VMID_LPASS 7225 QCOM_SCM_VMID_ADSP_HEAP>; 7226 #address-cells = <1>; 7227 #size-cells = <0>; 7228 7229 compute-cb@3 { 7230 compatible = "qcom,fastrpc-compute-cb"; 7231 reg = <3>; 7232 iommus = <&apps_smmu 0x3003 0x0>; 7233 dma-coherent; 7234 }; 7235 7236 compute-cb@4 { 7237 compatible = "qcom,fastrpc-compute-cb"; 7238 reg = <4>; 7239 iommus = <&apps_smmu 0x3004 0x0>; 7240 dma-coherent; 7241 }; 7242 7243 compute-cb@5 { 7244 compatible = "qcom,fastrpc-compute-cb"; 7245 reg = <5>; 7246 iommus = <&apps_smmu 0x3005 0x0>; 7247 qcom,nsessions = <5>; 7248 dma-coherent; 7249 }; 7250 }; 7251 7252 gpr { 7253 compatible = "qcom,gpr"; 7254 qcom,glink-channels = "adsp_apps"; 7255 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 7256 qcom,intents = <512 20>; 7257 #address-cells = <1>; 7258 #size-cells = <0>; 7259 7260 q6apm: service@1 { 7261 compatible = "qcom,q6apm"; 7262 reg = <GPR_APM_MODULE_IID>; 7263 #sound-dai-cells = <0>; 7264 qcom,protection-domain = "avs/audio", 7265 "msm/adsp/audio_pd"; 7266 7267 q6apmbedai: bedais { 7268 compatible = "qcom,q6apm-lpass-dais"; 7269 #sound-dai-cells = <1>; 7270 }; 7271 7272 q6apmdai: dais { 7273 compatible = "qcom,q6apm-dais"; 7274 iommus = <&apps_smmu 0x3001 0x0>; 7275 }; 7276 }; 7277 7278 q6prm: service@2 { 7279 compatible = "qcom,q6prm"; 7280 reg = <GPR_PRM_MODULE_IID>; 7281 qcom,protection-domain = "avs/audio", 7282 "msm/adsp/audio_pd"; 7283 7284 q6prmcc: clock-controller { 7285 compatible = "qcom,q6prm-lpass-clocks"; 7286 #clock-cells = <2>; 7287 }; 7288 }; 7289 }; 7290 }; 7291 }; 7292 }; 7293 7294 thermal-zones { 7295 aoss-0-thermal { 7296 thermal-sensors = <&tsens0 0>; 7297 7298 trips { 7299 trip-point0 { 7300 temperature = <105000>; 7301 hysteresis = <5000>; 7302 type = "passive"; 7303 }; 7304 7305 trip-point1 { 7306 temperature = <115000>; 7307 hysteresis = <5000>; 7308 type = "passive"; 7309 }; 7310 }; 7311 }; 7312 7313 cpu-0-0-0-thermal { 7314 polling-delay-passive = <10>; 7315 7316 thermal-sensors = <&tsens0 1>; 7317 7318 trips { 7319 trip-point0 { 7320 temperature = <105000>; 7321 hysteresis = <5000>; 7322 type = "passive"; 7323 }; 7324 7325 trip-point1 { 7326 temperature = <115000>; 7327 hysteresis = <5000>; 7328 type = "passive"; 7329 }; 7330 }; 7331 }; 7332 7333 cpu-0-1-0-thermal { 7334 polling-delay-passive = <10>; 7335 7336 thermal-sensors = <&tsens0 2>; 7337 7338 trips { 7339 trip-point0 { 7340 temperature = <105000>; 7341 hysteresis = <5000>; 7342 type = "passive"; 7343 }; 7344 7345 trip-point1 { 7346 temperature = <115000>; 7347 hysteresis = <5000>; 7348 type = "passive"; 7349 }; 7350 }; 7351 }; 7352 7353 cpu-0-2-0-thermal { 7354 polling-delay-passive = <10>; 7355 7356 thermal-sensors = <&tsens0 3>; 7357 7358 trips { 7359 trip-point0 { 7360 temperature = <105000>; 7361 hysteresis = <5000>; 7362 type = "passive"; 7363 }; 7364 7365 trip-point1 { 7366 temperature = <115000>; 7367 hysteresis = <5000>; 7368 type = "passive"; 7369 }; 7370 }; 7371 }; 7372 7373 cpu-0-3-0-thermal { 7374 polling-delay-passive = <10>; 7375 7376 thermal-sensors = <&tsens0 4>; 7377 7378 trips { 7379 trip-point0 { 7380 temperature = <105000>; 7381 hysteresis = <5000>; 7382 type = "passive"; 7383 }; 7384 7385 trip-point1 { 7386 temperature = <115000>; 7387 hysteresis = <5000>; 7388 type = "passive"; 7389 }; 7390 }; 7391 }; 7392 7393 gpuss-0-thermal { 7394 polling-delay-passive = <10>; 7395 7396 thermal-sensors = <&tsens0 5>; 7397 7398 trips { 7399 trip-point0 { 7400 temperature = <105000>; 7401 hysteresis = <5000>; 7402 type = "passive"; 7403 }; 7404 7405 trip-point1 { 7406 temperature = <115000>; 7407 hysteresis = <5000>; 7408 type = "passive"; 7409 }; 7410 }; 7411 }; 7412 7413 gpuss-1-thermal { 7414 polling-delay-passive = <10>; 7415 7416 thermal-sensors = <&tsens0 6>; 7417 7418 trips { 7419 trip-point0 { 7420 temperature = <105000>; 7421 hysteresis = <5000>; 7422 type = "passive"; 7423 }; 7424 7425 trip-point1 { 7426 temperature = <115000>; 7427 hysteresis = <5000>; 7428 type = "passive"; 7429 }; 7430 }; 7431 }; 7432 7433 gpuss-2-thermal { 7434 polling-delay-passive = <10>; 7435 7436 thermal-sensors = <&tsens0 7>; 7437 7438 trips { 7439 trip-point0 { 7440 temperature = <105000>; 7441 hysteresis = <5000>; 7442 type = "passive"; 7443 }; 7444 7445 trip-point1 { 7446 temperature = <115000>; 7447 hysteresis = <5000>; 7448 type = "passive"; 7449 }; 7450 }; 7451 }; 7452 7453 audio-thermal { 7454 thermal-sensors = <&tsens0 8>; 7455 7456 trips { 7457 trip-point0 { 7458 temperature = <105000>; 7459 hysteresis = <5000>; 7460 type = "passive"; 7461 }; 7462 7463 trip-point1 { 7464 temperature = <115000>; 7465 hysteresis = <5000>; 7466 type = "passive"; 7467 }; 7468 }; 7469 }; 7470 7471 camss-0-thermal { 7472 thermal-sensors = <&tsens0 9>; 7473 7474 trips { 7475 trip-point0 { 7476 temperature = <105000>; 7477 hysteresis = <5000>; 7478 type = "passive"; 7479 }; 7480 7481 trip-point1 { 7482 temperature = <115000>; 7483 hysteresis = <5000>; 7484 type = "passive"; 7485 }; 7486 }; 7487 }; 7488 7489 pcie-0-thermal { 7490 thermal-sensors = <&tsens0 10>; 7491 7492 trips { 7493 trip-point0 { 7494 temperature = <105000>; 7495 hysteresis = <5000>; 7496 type = "passive"; 7497 }; 7498 7499 trip-point1 { 7500 temperature = <115000>; 7501 hysteresis = <5000>; 7502 type = "passive"; 7503 }; 7504 }; 7505 }; 7506 7507 cpuss-0-0-thermal { 7508 thermal-sensors = <&tsens0 11>; 7509 7510 trips { 7511 trip-point0 { 7512 temperature = <105000>; 7513 hysteresis = <5000>; 7514 type = "passive"; 7515 }; 7516 7517 trip-point1 { 7518 temperature = <115000>; 7519 hysteresis = <5000>; 7520 type = "passive"; 7521 }; 7522 }; 7523 }; 7524 7525 aoss-1-thermal { 7526 thermal-sensors = <&tsens1 0>; 7527 7528 trips { 7529 trip-point0 { 7530 temperature = <105000>; 7531 hysteresis = <5000>; 7532 type = "passive"; 7533 }; 7534 7535 trip-point1 { 7536 temperature = <115000>; 7537 hysteresis = <5000>; 7538 type = "passive"; 7539 }; 7540 }; 7541 }; 7542 7543 cpu-0-0-1-thermal { 7544 polling-delay-passive = <10>; 7545 7546 thermal-sensors = <&tsens1 1>; 7547 7548 trips { 7549 trip-point0 { 7550 temperature = <105000>; 7551 hysteresis = <5000>; 7552 type = "passive"; 7553 }; 7554 7555 trip-point1 { 7556 temperature = <115000>; 7557 hysteresis = <5000>; 7558 type = "passive"; 7559 }; 7560 }; 7561 }; 7562 7563 cpu-0-1-1-thermal { 7564 polling-delay-passive = <10>; 7565 7566 thermal-sensors = <&tsens1 2>; 7567 7568 trips { 7569 trip-point0 { 7570 temperature = <105000>; 7571 hysteresis = <5000>; 7572 type = "passive"; 7573 }; 7574 7575 trip-point1 { 7576 temperature = <115000>; 7577 hysteresis = <5000>; 7578 type = "passive"; 7579 }; 7580 }; 7581 }; 7582 7583 cpu-0-2-1-thermal { 7584 polling-delay-passive = <10>; 7585 7586 thermal-sensors = <&tsens1 3>; 7587 7588 trips { 7589 trip-point0 { 7590 temperature = <105000>; 7591 hysteresis = <5000>; 7592 type = "passive"; 7593 }; 7594 7595 trip-point1 { 7596 temperature = <115000>; 7597 hysteresis = <5000>; 7598 type = "passive"; 7599 }; 7600 }; 7601 }; 7602 7603 cpu-0-3-1-thermal { 7604 polling-delay-passive = <10>; 7605 7606 thermal-sensors = <&tsens1 4>; 7607 7608 trips { 7609 trip-point0 { 7610 temperature = <105000>; 7611 hysteresis = <5000>; 7612 type = "passive"; 7613 }; 7614 7615 trip-point1 { 7616 temperature = <115000>; 7617 hysteresis = <5000>; 7618 type = "passive"; 7619 }; 7620 }; 7621 }; 7622 7623 gpuss-3-thermal { 7624 polling-delay-passive = <10>; 7625 7626 thermal-sensors = <&tsens1 5>; 7627 7628 trips { 7629 trip-point0 { 7630 temperature = <105000>; 7631 hysteresis = <5000>; 7632 type = "passive"; 7633 }; 7634 7635 trip-point1 { 7636 temperature = <115000>; 7637 hysteresis = <5000>; 7638 type = "passive"; 7639 }; 7640 }; 7641 }; 7642 7643 gpuss-4-thermal { 7644 polling-delay-passive = <10>; 7645 7646 thermal-sensors = <&tsens1 6>; 7647 7648 trips { 7649 trip-point0 { 7650 temperature = <105000>; 7651 hysteresis = <5000>; 7652 type = "passive"; 7653 }; 7654 7655 trip-point1 { 7656 temperature = <115000>; 7657 hysteresis = <5000>; 7658 type = "passive"; 7659 }; 7660 }; 7661 }; 7662 7663 gpuss-5-thermal { 7664 polling-delay-passive = <10>; 7665 7666 thermal-sensors = <&tsens1 7>; 7667 7668 trips { 7669 trip-point0 { 7670 temperature = <105000>; 7671 hysteresis = <5000>; 7672 type = "passive"; 7673 }; 7674 7675 trip-point1 { 7676 temperature = <115000>; 7677 hysteresis = <5000>; 7678 type = "passive"; 7679 }; 7680 }; 7681 }; 7682 7683 video-thermal { 7684 thermal-sensors = <&tsens1 8>; 7685 7686 trips { 7687 trip-point0 { 7688 temperature = <105000>; 7689 hysteresis = <5000>; 7690 type = "passive"; 7691 }; 7692 7693 trip-point1 { 7694 temperature = <115000>; 7695 hysteresis = <5000>; 7696 type = "passive"; 7697 }; 7698 }; 7699 }; 7700 7701 camss-1-thermal { 7702 thermal-sensors = <&tsens1 9>; 7703 7704 trips { 7705 trip-point0 { 7706 temperature = <105000>; 7707 hysteresis = <5000>; 7708 type = "passive"; 7709 }; 7710 7711 trip-point1 { 7712 temperature = <115000>; 7713 hysteresis = <5000>; 7714 type = "passive"; 7715 }; 7716 }; 7717 }; 7718 7719 pcie-1-thermal { 7720 thermal-sensors = <&tsens1 10>; 7721 7722 trips { 7723 trip-point0 { 7724 temperature = <105000>; 7725 hysteresis = <5000>; 7726 type = "passive"; 7727 }; 7728 7729 trip-point1 { 7730 temperature = <115000>; 7731 hysteresis = <5000>; 7732 type = "passive"; 7733 }; 7734 }; 7735 }; 7736 7737 cpuss-0-1-thermal { 7738 thermal-sensors = <&tsens1 11>; 7739 7740 trips { 7741 trip-point0 { 7742 temperature = <105000>; 7743 hysteresis = <5000>; 7744 type = "passive"; 7745 }; 7746 7747 trip-point1 { 7748 temperature = <115000>; 7749 hysteresis = <5000>; 7750 type = "passive"; 7751 }; 7752 }; 7753 }; 7754 7755 aoss-2-thermal { 7756 thermal-sensors = <&tsens2 0>; 7757 7758 trips { 7759 trip-point0 { 7760 temperature = <105000>; 7761 hysteresis = <5000>; 7762 type = "passive"; 7763 }; 7764 7765 trip-point1 { 7766 temperature = <115000>; 7767 hysteresis = <5000>; 7768 type = "passive"; 7769 }; 7770 }; 7771 }; 7772 7773 cpu-1-0-0-thermal { 7774 polling-delay-passive = <10>; 7775 7776 thermal-sensors = <&tsens2 1>; 7777 7778 trips { 7779 trip-point0 { 7780 temperature = <105000>; 7781 hysteresis = <5000>; 7782 type = "passive"; 7783 }; 7784 7785 trip-point1 { 7786 temperature = <115000>; 7787 hysteresis = <5000>; 7788 type = "passive"; 7789 }; 7790 }; 7791 }; 7792 7793 cpu-1-1-0-thermal { 7794 polling-delay-passive = <10>; 7795 7796 thermal-sensors = <&tsens2 2>; 7797 7798 trips { 7799 trip-point0 { 7800 temperature = <105000>; 7801 hysteresis = <5000>; 7802 type = "passive"; 7803 }; 7804 7805 trip-point1 { 7806 temperature = <115000>; 7807 hysteresis = <5000>; 7808 type = "passive"; 7809 }; 7810 }; 7811 }; 7812 7813 cpu-1-2-0-thermal { 7814 polling-delay-passive = <10>; 7815 7816 thermal-sensors = <&tsens2 3>; 7817 7818 trips { 7819 trip-point0 { 7820 temperature = <105000>; 7821 hysteresis = <5000>; 7822 type = "passive"; 7823 }; 7824 7825 trip-point1 { 7826 temperature = <115000>; 7827 hysteresis = <5000>; 7828 type = "passive"; 7829 }; 7830 }; 7831 }; 7832 7833 cpu-1-3-0-thermal { 7834 polling-delay-passive = <10>; 7835 7836 thermal-sensors = <&tsens2 4>; 7837 7838 trips { 7839 trip-point0 { 7840 temperature = <105000>; 7841 hysteresis = <5000>; 7842 type = "passive"; 7843 }; 7844 7845 trip-point1 { 7846 temperature = <115000>; 7847 hysteresis = <5000>; 7848 type = "passive"; 7849 }; 7850 }; 7851 }; 7852 7853 nsp-0-0-0-thermal { 7854 polling-delay-passive = <10>; 7855 7856 thermal-sensors = <&tsens2 5>; 7857 7858 trips { 7859 trip-point0 { 7860 temperature = <105000>; 7861 hysteresis = <5000>; 7862 type = "passive"; 7863 }; 7864 7865 trip-point1 { 7866 temperature = <115000>; 7867 hysteresis = <5000>; 7868 type = "passive"; 7869 }; 7870 }; 7871 }; 7872 7873 nsp-0-1-0-thermal { 7874 polling-delay-passive = <10>; 7875 7876 thermal-sensors = <&tsens2 6>; 7877 7878 trips { 7879 trip-point0 { 7880 temperature = <105000>; 7881 hysteresis = <5000>; 7882 type = "passive"; 7883 }; 7884 7885 trip-point1 { 7886 temperature = <115000>; 7887 hysteresis = <5000>; 7888 type = "passive"; 7889 }; 7890 }; 7891 }; 7892 7893 nsp-0-2-0-thermal { 7894 polling-delay-passive = <10>; 7895 7896 thermal-sensors = <&tsens2 7>; 7897 7898 trips { 7899 trip-point0 { 7900 temperature = <105000>; 7901 hysteresis = <5000>; 7902 type = "passive"; 7903 }; 7904 7905 trip-point1 { 7906 temperature = <115000>; 7907 hysteresis = <5000>; 7908 type = "passive"; 7909 }; 7910 }; 7911 }; 7912 7913 nsp-1-0-0-thermal { 7914 polling-delay-passive = <10>; 7915 7916 thermal-sensors = <&tsens2 8>; 7917 7918 trips { 7919 trip-point0 { 7920 temperature = <105000>; 7921 hysteresis = <5000>; 7922 type = "passive"; 7923 }; 7924 7925 trip-point1 { 7926 temperature = <115000>; 7927 hysteresis = <5000>; 7928 type = "passive"; 7929 }; 7930 }; 7931 }; 7932 7933 nsp-1-1-0-thermal { 7934 polling-delay-passive = <10>; 7935 7936 thermal-sensors = <&tsens2 9>; 7937 7938 trips { 7939 trip-point0 { 7940 temperature = <105000>; 7941 hysteresis = <5000>; 7942 type = "passive"; 7943 }; 7944 7945 trip-point1 { 7946 temperature = <115000>; 7947 hysteresis = <5000>; 7948 type = "passive"; 7949 }; 7950 }; 7951 }; 7952 7953 nsp-1-2-0-thermal { 7954 polling-delay-passive = <10>; 7955 7956 thermal-sensors = <&tsens2 10>; 7957 7958 trips { 7959 trip-point0 { 7960 temperature = <105000>; 7961 hysteresis = <5000>; 7962 type = "passive"; 7963 }; 7964 7965 trip-point1 { 7966 temperature = <115000>; 7967 hysteresis = <5000>; 7968 type = "passive"; 7969 }; 7970 }; 7971 }; 7972 7973 ddrss-0-thermal { 7974 thermal-sensors = <&tsens2 11>; 7975 7976 trips { 7977 trip-point0 { 7978 temperature = <105000>; 7979 hysteresis = <5000>; 7980 type = "passive"; 7981 }; 7982 7983 trip-point1 { 7984 temperature = <115000>; 7985 hysteresis = <5000>; 7986 type = "passive"; 7987 }; 7988 }; 7989 }; 7990 7991 cpuss-1-0-thermal { 7992 thermal-sensors = <&tsens2 12>; 7993 7994 trips { 7995 trip-point0 { 7996 temperature = <105000>; 7997 hysteresis = <5000>; 7998 type = "passive"; 7999 }; 8000 8001 trip-point1 { 8002 temperature = <115000>; 8003 hysteresis = <5000>; 8004 type = "passive"; 8005 }; 8006 }; 8007 }; 8008 8009 aoss-3-thermal { 8010 thermal-sensors = <&tsens3 0>; 8011 8012 trips { 8013 trip-point0 { 8014 temperature = <105000>; 8015 hysteresis = <5000>; 8016 type = "passive"; 8017 }; 8018 8019 trip-point1 { 8020 temperature = <115000>; 8021 hysteresis = <5000>; 8022 type = "passive"; 8023 }; 8024 }; 8025 }; 8026 8027 cpu-1-0-1-thermal { 8028 polling-delay-passive = <10>; 8029 8030 thermal-sensors = <&tsens3 1>; 8031 8032 trips { 8033 trip-point0 { 8034 temperature = <105000>; 8035 hysteresis = <5000>; 8036 type = "passive"; 8037 }; 8038 8039 trip-point1 { 8040 temperature = <115000>; 8041 hysteresis = <5000>; 8042 type = "passive"; 8043 }; 8044 }; 8045 }; 8046 8047 cpu-1-1-1-thermal { 8048 polling-delay-passive = <10>; 8049 8050 thermal-sensors = <&tsens3 2>; 8051 8052 trips { 8053 trip-point0 { 8054 temperature = <105000>; 8055 hysteresis = <5000>; 8056 type = "passive"; 8057 }; 8058 8059 trip-point1 { 8060 temperature = <115000>; 8061 hysteresis = <5000>; 8062 type = "passive"; 8063 }; 8064 }; 8065 }; 8066 8067 cpu-1-2-1-thermal { 8068 polling-delay-passive = <10>; 8069 8070 thermal-sensors = <&tsens3 3>; 8071 8072 trips { 8073 trip-point0 { 8074 temperature = <105000>; 8075 hysteresis = <5000>; 8076 type = "passive"; 8077 }; 8078 8079 trip-point1 { 8080 temperature = <115000>; 8081 hysteresis = <5000>; 8082 type = "passive"; 8083 }; 8084 }; 8085 }; 8086 8087 cpu-1-3-1-thermal { 8088 polling-delay-passive = <10>; 8089 8090 thermal-sensors = <&tsens3 4>; 8091 8092 trips { 8093 trip-point0 { 8094 temperature = <105000>; 8095 hysteresis = <5000>; 8096 type = "passive"; 8097 }; 8098 8099 trip-point1 { 8100 temperature = <115000>; 8101 hysteresis = <5000>; 8102 type = "passive"; 8103 }; 8104 }; 8105 }; 8106 8107 nsp-0-0-1-thermal { 8108 polling-delay-passive = <10>; 8109 8110 thermal-sensors = <&tsens3 5>; 8111 8112 trips { 8113 trip-point0 { 8114 temperature = <105000>; 8115 hysteresis = <5000>; 8116 type = "passive"; 8117 }; 8118 8119 trip-point1 { 8120 temperature = <115000>; 8121 hysteresis = <5000>; 8122 type = "passive"; 8123 }; 8124 }; 8125 }; 8126 8127 nsp-0-1-1-thermal { 8128 polling-delay-passive = <10>; 8129 8130 thermal-sensors = <&tsens3 6>; 8131 8132 trips { 8133 trip-point0 { 8134 temperature = <105000>; 8135 hysteresis = <5000>; 8136 type = "passive"; 8137 }; 8138 8139 trip-point1 { 8140 temperature = <115000>; 8141 hysteresis = <5000>; 8142 type = "passive"; 8143 }; 8144 }; 8145 }; 8146 8147 nsp-0-2-1-thermal { 8148 polling-delay-passive = <10>; 8149 8150 thermal-sensors = <&tsens3 7>; 8151 8152 trips { 8153 trip-point0 { 8154 temperature = <105000>; 8155 hysteresis = <5000>; 8156 type = "passive"; 8157 }; 8158 8159 trip-point1 { 8160 temperature = <115000>; 8161 hysteresis = <5000>; 8162 type = "passive"; 8163 }; 8164 }; 8165 }; 8166 8167 nsp-1-0-1-thermal { 8168 polling-delay-passive = <10>; 8169 8170 thermal-sensors = <&tsens3 8>; 8171 8172 trips { 8173 trip-point0 { 8174 temperature = <105000>; 8175 hysteresis = <5000>; 8176 type = "passive"; 8177 }; 8178 8179 trip-point1 { 8180 temperature = <115000>; 8181 hysteresis = <5000>; 8182 type = "passive"; 8183 }; 8184 }; 8185 }; 8186 8187 nsp-1-1-1-thermal { 8188 polling-delay-passive = <10>; 8189 8190 thermal-sensors = <&tsens3 9>; 8191 8192 trips { 8193 trip-point0 { 8194 temperature = <105000>; 8195 hysteresis = <5000>; 8196 type = "passive"; 8197 }; 8198 8199 trip-point1 { 8200 temperature = <115000>; 8201 hysteresis = <5000>; 8202 type = "passive"; 8203 }; 8204 }; 8205 }; 8206 8207 nsp-1-2-1-thermal { 8208 polling-delay-passive = <10>; 8209 8210 thermal-sensors = <&tsens3 10>; 8211 8212 trips { 8213 trip-point0 { 8214 temperature = <105000>; 8215 hysteresis = <5000>; 8216 type = "passive"; 8217 }; 8218 8219 trip-point1 { 8220 temperature = <115000>; 8221 hysteresis = <5000>; 8222 type = "passive"; 8223 }; 8224 }; 8225 }; 8226 8227 ddrss-1-thermal { 8228 thermal-sensors = <&tsens3 11>; 8229 8230 trips { 8231 trip-point0 { 8232 temperature = <105000>; 8233 hysteresis = <5000>; 8234 type = "passive"; 8235 }; 8236 8237 trip-point1 { 8238 temperature = <115000>; 8239 hysteresis = <5000>; 8240 type = "passive"; 8241 }; 8242 }; 8243 }; 8244 8245 cpuss-1-1-thermal { 8246 thermal-sensors = <&tsens3 12>; 8247 8248 trips { 8249 trip-point0 { 8250 temperature = <105000>; 8251 hysteresis = <5000>; 8252 type = "passive"; 8253 }; 8254 8255 trip-point1 { 8256 temperature = <115000>; 8257 hysteresis = <5000>; 8258 type = "passive"; 8259 }; 8260 }; 8261 }; 8262 }; 8263 8264 arch_timer: timer { 8265 compatible = "arm,armv8-timer"; 8266 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 8267 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 8268 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 8269 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 8270 }; 8271 8272 pcie0: pcie@1c00000 { 8273 compatible = "qcom,pcie-sa8775p"; 8274 reg = <0x0 0x01c00000 0x0 0x3000>, 8275 <0x0 0x40000000 0x0 0xf20>, 8276 <0x0 0x40000f20 0x0 0xa8>, 8277 <0x0 0x40001000 0x0 0x4000>, 8278 <0x0 0x40100000 0x0 0x100000>, 8279 <0x0 0x01c03000 0x0 0x1000>; 8280 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 8281 device_type = "pci"; 8282 8283 #address-cells = <3>; 8284 #size-cells = <2>; 8285 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 8286 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 8287 bus-range = <0x00 0xff>; 8288 8289 dma-coherent; 8290 8291 linux,pci-domain = <0>; 8292 num-lanes = <2>; 8293 8294 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 8295 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 8296 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 8297 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 8298 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 8299 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 8300 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 8301 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 8302 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 8303 interrupt-names = "msi0", 8304 "msi1", 8305 "msi2", 8306 "msi3", 8307 "msi4", 8308 "msi5", 8309 "msi6", 8310 "msi7", 8311 "global"; 8312 #interrupt-cells = <1>; 8313 interrupt-map-mask = <0 0 0 0x7>; 8314 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 8315 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 8316 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 8317 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 8318 8319 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 8320 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 8321 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 8322 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 8323 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 8324 8325 clock-names = "aux", 8326 "cfg", 8327 "bus_master", 8328 "bus_slave", 8329 "slave_q2a"; 8330 8331 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 8332 assigned-clock-rates = <19200000>; 8333 8334 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 8335 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 8336 interconnect-names = "pcie-mem", "cpu-pcie"; 8337 8338 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, 8339 <0x100 &pcie_smmu 0x0001 0x1>; 8340 8341 resets = <&gcc GCC_PCIE_0_BCR>, 8342 <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; 8343 reset-names = "pci", 8344 "link_down"; 8345 8346 power-domains = <&gcc PCIE_0_GDSC>; 8347 8348 phys = <&pcie0_phy>; 8349 phy-names = "pciephy"; 8350 8351 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 8352 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 8353 8354 status = "disabled"; 8355 8356 pcieport0: pcie@0 { 8357 device_type = "pci"; 8358 reg = <0x0 0x0 0x0 0x0 0x0>; 8359 bus-range = <0x01 0xff>; 8360 8361 #address-cells = <3>; 8362 #size-cells = <2>; 8363 ranges; 8364 }; 8365 }; 8366 8367 pcie0_ep: pcie-ep@1c00000 { 8368 compatible = "qcom,sa8775p-pcie-ep"; 8369 reg = <0x0 0x01c00000 0x0 0x3000>, 8370 <0x0 0x40000000 0x0 0xf20>, 8371 <0x0 0x40000f20 0x0 0xa8>, 8372 <0x0 0x40001000 0x0 0x4000>, 8373 <0x0 0x40200000 0x0 0x1fe00000>, 8374 <0x0 0x01c03000 0x0 0x1000>, 8375 <0x0 0x40005000 0x0 0x2000>; 8376 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 8377 "mmio", "dma"; 8378 8379 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 8380 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 8381 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 8382 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 8383 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 8384 8385 clock-names = "aux", 8386 "cfg", 8387 "bus_master", 8388 "bus_slave", 8389 "slave_q2a"; 8390 8391 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 8392 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 8393 <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>; 8394 8395 interrupt-names = "global", "doorbell", "dma"; 8396 8397 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 8398 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 8399 interconnect-names = "pcie-mem", "cpu-pcie"; 8400 8401 dma-coherent; 8402 iommus = <&pcie_smmu 0x0000 0x7f>; 8403 resets = <&gcc GCC_PCIE_0_BCR>; 8404 reset-names = "core"; 8405 power-domains = <&gcc PCIE_0_GDSC>; 8406 phys = <&pcie0_phy>; 8407 phy-names = "pciephy"; 8408 num-lanes = <2>; 8409 linux,pci-domain = <0>; 8410 8411 status = "disabled"; 8412 }; 8413 8414 pcie0_phy: phy@1c04000 { 8415 compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; 8416 reg = <0x0 0x1c04000 0x0 0x2000>; 8417 8418 clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, 8419 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 8420 <&gcc GCC_PCIE_CLKREF_EN>, 8421 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 8422 <&gcc GCC_PCIE_0_PIPE_CLK>, 8423 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; 8424 clock-names = "aux", 8425 "cfg_ahb", 8426 "ref", 8427 "rchng", 8428 "pipe", 8429 "pipediv2"; 8430 8431 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 8432 assigned-clock-rates = <100000000>; 8433 8434 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 8435 reset-names = "phy"; 8436 8437 #clock-cells = <0>; 8438 clock-output-names = "pcie_0_pipe_clk"; 8439 8440 #phy-cells = <0>; 8441 8442 status = "disabled"; 8443 }; 8444 8445 pcie1: pcie@1c10000 { 8446 compatible = "qcom,pcie-sa8775p"; 8447 reg = <0x0 0x01c10000 0x0 0x3000>, 8448 <0x0 0x60000000 0x0 0xf20>, 8449 <0x0 0x60000f20 0x0 0xa8>, 8450 <0x0 0x60001000 0x0 0x4000>, 8451 <0x0 0x60100000 0x0 0x100000>, 8452 <0x0 0x01c13000 0x0 0x1000>; 8453 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 8454 device_type = "pci"; 8455 8456 #address-cells = <3>; 8457 #size-cells = <2>; 8458 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 8459 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; 8460 bus-range = <0x00 0xff>; 8461 8462 dma-coherent; 8463 8464 linux,pci-domain = <1>; 8465 num-lanes = <4>; 8466 8467 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 8468 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 8469 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 8470 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 8471 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 8472 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 8473 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 8474 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 8475 <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>; 8476 interrupt-names = "msi0", 8477 "msi1", 8478 "msi2", 8479 "msi3", 8480 "msi4", 8481 "msi5", 8482 "msi6", 8483 "msi7", 8484 "global"; 8485 #interrupt-cells = <1>; 8486 interrupt-map-mask = <0 0 0 0x7>; 8487 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 8488 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 8489 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 8490 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 8491 8492 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 8493 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 8494 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 8495 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 8496 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 8497 8498 clock-names = "aux", 8499 "cfg", 8500 "bus_master", 8501 "bus_slave", 8502 "slave_q2a"; 8503 8504 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 8505 assigned-clock-rates = <19200000>; 8506 8507 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 8508 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 8509 interconnect-names = "pcie-mem", "cpu-pcie"; 8510 8511 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, 8512 <0x100 &pcie_smmu 0x0081 0x1>; 8513 8514 resets = <&gcc GCC_PCIE_1_BCR>, 8515 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 8516 reset-names = "pci", 8517 "link_down"; 8518 8519 power-domains = <&gcc PCIE_1_GDSC>; 8520 8521 phys = <&pcie1_phy>; 8522 phy-names = "pciephy"; 8523 8524 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 8525 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 8526 8527 status = "disabled"; 8528 8529 pcie@0 { 8530 device_type = "pci"; 8531 reg = <0x0 0x0 0x0 0x0 0x0>; 8532 bus-range = <0x01 0xff>; 8533 8534 #address-cells = <3>; 8535 #size-cells = <2>; 8536 ranges; 8537 }; 8538 }; 8539 8540 pcie1_ep: pcie-ep@1c10000 { 8541 compatible = "qcom,sa8775p-pcie-ep"; 8542 reg = <0x0 0x01c10000 0x0 0x3000>, 8543 <0x0 0x60000000 0x0 0xf20>, 8544 <0x0 0x60000f20 0x0 0xa8>, 8545 <0x0 0x60001000 0x0 0x4000>, 8546 <0x0 0x60200000 0x0 0x1fe00000>, 8547 <0x0 0x01c13000 0x0 0x1000>, 8548 <0x0 0x60005000 0x0 0x2000>; 8549 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 8550 "mmio", "dma"; 8551 8552 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 8553 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 8554 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 8555 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 8556 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 8557 8558 clock-names = "aux", 8559 "cfg", 8560 "bus_master", 8561 "bus_slave", 8562 "slave_q2a"; 8563 8564 interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 8565 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 8566 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 8567 8568 interrupt-names = "global", "doorbell", "dma"; 8569 8570 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 8571 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 8572 interconnect-names = "pcie-mem", "cpu-pcie"; 8573 8574 dma-coherent; 8575 iommus = <&pcie_smmu 0x80 0x7f>; 8576 resets = <&gcc GCC_PCIE_1_BCR>; 8577 reset-names = "core"; 8578 power-domains = <&gcc PCIE_1_GDSC>; 8579 phys = <&pcie1_phy>; 8580 phy-names = "pciephy"; 8581 num-lanes = <4>; 8582 linux,pci-domain = <1>; 8583 8584 status = "disabled"; 8585 }; 8586 8587 pcie1_phy: phy@1c14000 { 8588 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; 8589 reg = <0x0 0x1c14000 0x0 0x4000>; 8590 8591 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 8592 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 8593 <&gcc GCC_PCIE_CLKREF_EN>, 8594 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 8595 <&gcc GCC_PCIE_1_PIPE_CLK>, 8596 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; 8597 clock-names = "aux", 8598 "cfg_ahb", 8599 "ref", 8600 "rchng", 8601 "pipe", 8602 "pipediv2"; 8603 8604 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 8605 assigned-clock-rates = <100000000>; 8606 8607 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 8608 reset-names = "phy"; 8609 8610 #clock-cells = <0>; 8611 clock-output-names = "pcie_1_pipe_clk"; 8612 8613 #phy-cells = <0>; 8614 8615 status = "disabled"; 8616 }; 8617}; 8618