1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved.
4 *
5 */
6 #include <linux/gcd.h>
7 #include <linux/gpio/consumer.h>
8 #include <linux/i2c.h>
9 #include <linux/interrupt.h>
10 #include <linux/iopoll.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/mutex.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/slab.h>
17 #include <linux/types.h>
18 #include <linux/workqueue.h>
19
20 #include <linux/of_graph.h>
21 #include <linux/of_platform.h>
22
23 #include <drm/display/drm_dp_aux_bus.h>
24 #include <drm/display/drm_dp_helper.h>
25 #include <drm/display/drm_hdcp_helper.h>
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_bridge.h>
28 #include <drm/drm_edid.h>
29 #include <drm/drm_mipi_dsi.h>
30 #include <drm/drm_of.h>
31 #include <drm/drm_panel.h>
32 #include <drm/drm_print.h>
33 #include <drm/drm_probe_helper.h>
34
35 #include <media/v4l2-fwnode.h>
36 #include <sound/hdmi-codec.h>
37 #include <video/display_timing.h>
38
39 #include "anx7625.h"
40
41 /*
42 * There is a sync issue while access I2C register between AP(CPU) and
43 * internal firmware(OCM), to avoid the race condition, AP should access
44 * the reserved slave address before slave address occurs changes.
45 */
i2c_access_workaround(struct anx7625_data * ctx,struct i2c_client * client)46 static int i2c_access_workaround(struct anx7625_data *ctx,
47 struct i2c_client *client)
48 {
49 u8 offset;
50 struct device *dev = &client->dev;
51 int ret;
52
53 if (client == ctx->last_client)
54 return 0;
55
56 ctx->last_client = client;
57
58 if (client == ctx->i2c.tcpc_client)
59 offset = RSVD_00_ADDR;
60 else if (client == ctx->i2c.tx_p0_client)
61 offset = RSVD_D1_ADDR;
62 else if (client == ctx->i2c.tx_p1_client)
63 offset = RSVD_60_ADDR;
64 else if (client == ctx->i2c.rx_p0_client)
65 offset = RSVD_39_ADDR;
66 else if (client == ctx->i2c.rx_p1_client)
67 offset = RSVD_7F_ADDR;
68 else
69 offset = RSVD_00_ADDR;
70
71 ret = i2c_smbus_write_byte_data(client, offset, 0x00);
72 if (ret < 0)
73 DRM_DEV_ERROR(dev,
74 "fail to access i2c id=%x\n:%x",
75 client->addr, offset);
76
77 return ret;
78 }
79
anx7625_reg_read(struct anx7625_data * ctx,struct i2c_client * client,u8 reg_addr)80 static int anx7625_reg_read(struct anx7625_data *ctx,
81 struct i2c_client *client, u8 reg_addr)
82 {
83 int ret;
84 struct device *dev = &client->dev;
85
86 i2c_access_workaround(ctx, client);
87
88 ret = i2c_smbus_read_byte_data(client, reg_addr);
89 if (ret < 0)
90 DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n",
91 client->addr, reg_addr);
92
93 return ret;
94 }
95
anx7625_reg_block_read(struct anx7625_data * ctx,struct i2c_client * client,u8 reg_addr,u8 len,u8 * buf)96 static int anx7625_reg_block_read(struct anx7625_data *ctx,
97 struct i2c_client *client,
98 u8 reg_addr, u8 len, u8 *buf)
99 {
100 int ret;
101 struct device *dev = &client->dev;
102
103 i2c_access_workaround(ctx, client);
104
105 ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf);
106 if (ret < 0)
107 DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n",
108 client->addr, reg_addr);
109
110 return ret;
111 }
112
anx7625_reg_write(struct anx7625_data * ctx,struct i2c_client * client,u8 reg_addr,u8 reg_val)113 static int anx7625_reg_write(struct anx7625_data *ctx,
114 struct i2c_client *client,
115 u8 reg_addr, u8 reg_val)
116 {
117 int ret;
118 struct device *dev = &client->dev;
119
120 i2c_access_workaround(ctx, client);
121
122 ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val);
123
124 if (ret < 0)
125 DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x",
126 client->addr, reg_addr);
127
128 return ret;
129 }
130
anx7625_reg_block_write(struct anx7625_data * ctx,struct i2c_client * client,u8 reg_addr,u8 len,u8 * buf)131 static int anx7625_reg_block_write(struct anx7625_data *ctx,
132 struct i2c_client *client,
133 u8 reg_addr, u8 len, u8 *buf)
134 {
135 int ret;
136 struct device *dev = &client->dev;
137
138 i2c_access_workaround(ctx, client);
139
140 ret = i2c_smbus_write_i2c_block_data(client, reg_addr, len, buf);
141 if (ret < 0)
142 dev_err(dev, "write i2c block failed id=%x\n:%x",
143 client->addr, reg_addr);
144
145 return ret;
146 }
147
anx7625_write_or(struct anx7625_data * ctx,struct i2c_client * client,u8 offset,u8 mask)148 static int anx7625_write_or(struct anx7625_data *ctx,
149 struct i2c_client *client,
150 u8 offset, u8 mask)
151 {
152 int val;
153
154 val = anx7625_reg_read(ctx, client, offset);
155 if (val < 0)
156 return val;
157
158 return anx7625_reg_write(ctx, client, offset, (val | (mask)));
159 }
160
anx7625_write_and(struct anx7625_data * ctx,struct i2c_client * client,u8 offset,u8 mask)161 static int anx7625_write_and(struct anx7625_data *ctx,
162 struct i2c_client *client,
163 u8 offset, u8 mask)
164 {
165 int val;
166
167 val = anx7625_reg_read(ctx, client, offset);
168 if (val < 0)
169 return val;
170
171 return anx7625_reg_write(ctx, client, offset, (val & (mask)));
172 }
173
anx7625_write_and_or(struct anx7625_data * ctx,struct i2c_client * client,u8 offset,u8 and_mask,u8 or_mask)174 static int anx7625_write_and_or(struct anx7625_data *ctx,
175 struct i2c_client *client,
176 u8 offset, u8 and_mask, u8 or_mask)
177 {
178 int val;
179
180 val = anx7625_reg_read(ctx, client, offset);
181 if (val < 0)
182 return val;
183
184 return anx7625_reg_write(ctx, client,
185 offset, (val & and_mask) | (or_mask));
186 }
187
anx7625_config_bit_matrix(struct anx7625_data * ctx)188 static int anx7625_config_bit_matrix(struct anx7625_data *ctx)
189 {
190 int i, ret;
191
192 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client,
193 AUDIO_CONTROL_REGISTER, 0x80);
194 for (i = 0; i < 13; i++)
195 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
196 VIDEO_BIT_MATRIX_12 + i,
197 0x18 + i);
198
199 return ret;
200 }
201
anx7625_read_ctrl_status_p0(struct anx7625_data * ctx)202 static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx)
203 {
204 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS);
205 }
206
wait_aux_op_finish(struct anx7625_data * ctx)207 static int wait_aux_op_finish(struct anx7625_data *ctx)
208 {
209 struct device *dev = ctx->dev;
210 int val;
211 int ret;
212
213 ret = readx_poll_timeout(anx7625_read_ctrl_status_p0,
214 ctx, val,
215 (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)),
216 2000,
217 2000 * 150);
218 if (ret) {
219 DRM_DEV_ERROR(dev, "aux operation fail!\n");
220 return -EIO;
221 }
222
223 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
224 AP_AUX_CTRL_STATUS);
225 if (val < 0 || (val & 0x0F)) {
226 DRM_DEV_ERROR(dev, "aux status %02x\n", val);
227 return -EIO;
228 }
229
230 return 0;
231 }
232
anx7625_aux_trans(struct anx7625_data * ctx,u8 op,u32 address,u8 len,u8 * buf)233 static int anx7625_aux_trans(struct anx7625_data *ctx, u8 op, u32 address,
234 u8 len, u8 *buf)
235 {
236 struct device *dev = ctx->dev;
237 int ret;
238 u8 addrh, addrm, addrl;
239 u8 cmd;
240 bool is_write = !(op & DP_AUX_I2C_READ);
241
242 if (len > DP_AUX_MAX_PAYLOAD_BYTES) {
243 dev_err(dev, "exceed aux buffer len.\n");
244 return -EINVAL;
245 }
246
247 if (!len)
248 return len;
249
250 addrl = address & 0xFF;
251 addrm = (address >> 8) & 0xFF;
252 addrh = (address >> 16) & 0xFF;
253
254 if (!is_write)
255 op &= ~DP_AUX_I2C_MOT;
256 cmd = DPCD_CMD(len, op);
257
258 /* Set command and length */
259 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
260 AP_AUX_COMMAND, cmd);
261
262 /* Set aux access address */
263 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
264 AP_AUX_ADDR_7_0, addrl);
265 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
266 AP_AUX_ADDR_15_8, addrm);
267 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
268 AP_AUX_ADDR_19_16, addrh);
269
270 if (is_write)
271 ret |= anx7625_reg_block_write(ctx, ctx->i2c.rx_p0_client,
272 AP_AUX_BUFF_START, len, buf);
273 /* Enable aux access */
274 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
275 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
276
277 if (ret < 0) {
278 dev_err(dev, "cannot access aux related register.\n");
279 return -EIO;
280 }
281
282 ret = wait_aux_op_finish(ctx);
283 if (ret < 0) {
284 dev_err(dev, "aux IO error: wait aux op finish.\n");
285 return ret;
286 }
287
288 /* Write done */
289 if (is_write)
290 return len;
291
292 /* Read done, read out dpcd data */
293 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
294 AP_AUX_BUFF_START, len, buf);
295 if (ret < 0) {
296 dev_err(dev, "read dpcd register failed\n");
297 return -EIO;
298 }
299
300 return len;
301 }
302
anx7625_video_mute_control(struct anx7625_data * ctx,u8 status)303 static int anx7625_video_mute_control(struct anx7625_data *ctx,
304 u8 status)
305 {
306 int ret;
307
308 if (status) {
309 /* Set mute on flag */
310 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
311 AP_AV_STATUS, AP_MIPI_MUTE);
312 /* Clear mipi RX en */
313 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
314 AP_AV_STATUS, (u8)~AP_MIPI_RX_EN);
315 } else {
316 /* Mute off flag */
317 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
318 AP_AV_STATUS, (u8)~AP_MIPI_MUTE);
319 /* Set MIPI RX EN */
320 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
321 AP_AV_STATUS, AP_MIPI_RX_EN);
322 }
323
324 return ret;
325 }
326
327 /* Reduction of fraction a/b */
anx7625_reduction_of_a_fraction(unsigned long * a,unsigned long * b)328 static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b)
329 {
330 unsigned long gcd_num;
331 unsigned long tmp_a, tmp_b;
332 u32 i = 1;
333
334 gcd_num = gcd(*a, *b);
335 *a /= gcd_num;
336 *b /= gcd_num;
337
338 tmp_a = *a;
339 tmp_b = *b;
340
341 while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) {
342 i++;
343 *a = tmp_a / i;
344 *b = tmp_b / i;
345 }
346
347 /*
348 * In the end, make a, b larger to have higher ODFC PLL
349 * output frequency accuracy
350 */
351 while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) {
352 *a <<= 1;
353 *b <<= 1;
354 }
355
356 *a >>= 1;
357 *b >>= 1;
358 }
359
anx7625_calculate_m_n(u32 pixelclock,unsigned long * m,unsigned long * n,u8 * post_divider)360 static int anx7625_calculate_m_n(u32 pixelclock,
361 unsigned long *m,
362 unsigned long *n,
363 u8 *post_divider)
364 {
365 if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) {
366 /* Pixel clock frequency is too high */
367 DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n",
368 pixelclock,
369 PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN);
370 return -EINVAL;
371 }
372
373 if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) {
374 /* Pixel clock frequency is too low */
375 DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n",
376 pixelclock,
377 PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX);
378 return -EINVAL;
379 }
380
381 for (*post_divider = 1;
382 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));)
383 *post_divider += 1;
384
385 if (*post_divider > POST_DIVIDER_MAX) {
386 for (*post_divider = 1;
387 (pixelclock <
388 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));)
389 *post_divider += 1;
390
391 if (*post_divider > POST_DIVIDER_MAX) {
392 DRM_ERROR("cannot find property post_divider(%d)\n",
393 *post_divider);
394 return -EDOM;
395 }
396 }
397
398 /* Patch to improve the accuracy */
399 if (*post_divider == 7) {
400 /* 27,000,000 is not divisible by 7 */
401 *post_divider = 8;
402 } else if (*post_divider == 11) {
403 /* 27,000,000 is not divisible by 11 */
404 *post_divider = 12;
405 } else if ((*post_divider == 13) || (*post_divider == 14)) {
406 /* 27,000,000 is not divisible by 13 or 14 */
407 *post_divider = 15;
408 }
409
410 if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) {
411 DRM_ERROR("act clock(%u) large than maximum(%lu)\n",
412 pixelclock * (*post_divider),
413 PLL_OUT_FREQ_ABS_MAX);
414 return -EDOM;
415 }
416
417 *m = pixelclock;
418 *n = XTAL_FRQ / (*post_divider);
419
420 anx7625_reduction_of_a_fraction(m, n);
421
422 return 0;
423 }
424
anx7625_odfc_config(struct anx7625_data * ctx,u8 post_divider)425 static int anx7625_odfc_config(struct anx7625_data *ctx,
426 u8 post_divider)
427 {
428 int ret;
429 struct device *dev = ctx->dev;
430
431 /* Config input reference clock frequency 27MHz/19.2MHz */
432 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16,
433 ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND));
434 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16,
435 (REF_CLK_27000KHZ << MIPI_FREF_D_IND));
436 /* Post divider */
437 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client,
438 MIPI_DIGITAL_PLL_8, 0x0f);
439 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8,
440 post_divider << 4);
441
442 /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */
443 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
444 ~MIPI_PLL_VCO_TUNE_REG_VAL);
445
446 /* Reset ODFC PLL */
447 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
448 ~MIPI_PLL_RESET_N);
449 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
450 MIPI_PLL_RESET_N);
451
452 if (ret < 0)
453 DRM_DEV_ERROR(dev, "IO error.\n");
454
455 return ret;
456 }
457
458 /*
459 * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz),
460 * anx7625 defined K ratio for matching MIPI input video clock and
461 * DP output video clock. Increase K value can match bigger video data
462 * variation. IVO panel has small variation than DP CTS spec, need
463 * decrease the K value.
464 */
anx7625_set_k_value(struct anx7625_data * ctx)465 static int anx7625_set_k_value(struct anx7625_data *ctx)
466 {
467 struct drm_edid_product_id id;
468
469 drm_edid_get_product_id(ctx->cached_drm_edid, &id);
470
471 if (be16_to_cpu(id.manufacturer_name) == IVO_MID)
472 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
473 MIPI_DIGITAL_ADJ_1, 0x3B);
474
475 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
476 MIPI_DIGITAL_ADJ_1, 0x3D);
477 }
478
anx7625_dsi_video_timing_config(struct anx7625_data * ctx)479 static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx)
480 {
481 struct device *dev = ctx->dev;
482 unsigned long m, n;
483 u16 htotal;
484 int ret;
485 u8 post_divider = 0;
486
487 ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000,
488 &m, &n, &post_divider);
489
490 if (ret) {
491 DRM_DEV_ERROR(dev, "cannot get property m n value.\n");
492 return ret;
493 }
494
495 DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n",
496 m, n, post_divider);
497
498 /* Configure pixel clock */
499 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L,
500 (ctx->dt.pixelclock.min / 1000) & 0xFF);
501 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H,
502 (ctx->dt.pixelclock.min / 1000) >> 8);
503 /* Lane count */
504 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client,
505 MIPI_LANE_CTRL_0, 0xfc);
506 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client,
507 MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1);
508
509 /* Htotal */
510 htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min +
511 ctx->dt.hback_porch.min + ctx->dt.hsync_len.min;
512 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
513 HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF);
514 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
515 HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8);
516 /* Hactive */
517 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
518 HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF);
519 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
520 HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8);
521 /* HFP */
522 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
523 HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min);
524 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
525 HORIZONTAL_FRONT_PORCH_H,
526 ctx->dt.hfront_porch.min >> 8);
527 /* HWS */
528 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
529 HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min);
530 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
531 HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8);
532 /* HBP */
533 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
534 HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min);
535 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
536 HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8);
537 /* Vactive */
538 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L,
539 ctx->dt.vactive.min);
540 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H,
541 ctx->dt.vactive.min >> 8);
542 /* VFP */
543 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
544 VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min);
545 /* VWS */
546 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
547 VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min);
548 /* VBP */
549 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
550 VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min);
551 /* M value */
552 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
553 MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff);
554 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
555 MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff);
556 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
557 MIPI_PLL_M_NUM_7_0, (m & 0xff));
558 /* N value */
559 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
560 MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff);
561 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
562 MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff);
563 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0,
564 (n & 0xff));
565
566 anx7625_set_k_value(ctx);
567
568 ret |= anx7625_odfc_config(ctx, post_divider - 1);
569
570 if (ret < 0)
571 DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n");
572
573 return ret;
574 }
575
anx7625_swap_dsi_lane3(struct anx7625_data * ctx)576 static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx)
577 {
578 int val;
579 struct device *dev = ctx->dev;
580
581 /* Swap MIPI-DSI data lane 3 P and N */
582 val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP);
583 if (val < 0) {
584 DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n");
585 return -EIO;
586 }
587
588 val |= (1 << MIPI_SWAP_CH3);
589 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val);
590 }
591
anx7625_api_dsi_config(struct anx7625_data * ctx)592 static int anx7625_api_dsi_config(struct anx7625_data *ctx)
593
594 {
595 int val, ret;
596 struct device *dev = ctx->dev;
597
598 /* Swap MIPI-DSI data lane 3 P and N */
599 ret = anx7625_swap_dsi_lane3(ctx);
600 if (ret < 0) {
601 DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n");
602 return ret;
603 }
604
605 /* DSI clock settings */
606 val = (0 << MIPI_HS_PWD_CLK) |
607 (0 << MIPI_HS_RT_CLK) |
608 (0 << MIPI_PD_CLK) |
609 (1 << MIPI_CLK_RT_MANUAL_PD_EN) |
610 (1 << MIPI_CLK_HS_MANUAL_PD_EN) |
611 (0 << MIPI_CLK_DET_DET_BYPASS) |
612 (0 << MIPI_CLK_MISS_CTRL) |
613 (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN);
614 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
615 MIPI_PHY_CONTROL_3, val);
616
617 /*
618 * Decreased HS prepare timing delay from 160ns to 80ns work with
619 * a) Dragon board 810 series (Qualcomm AP)
620 * b) Moving Pixel DSI source (PG3A pattern generator +
621 * P332 D-PHY Probe) default D-PHY timing
622 * 5ns/step
623 */
624 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
625 MIPI_TIME_HS_PRPR, 0x10);
626
627 /* Enable DSI mode*/
628 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18,
629 SELECT_DSI << MIPI_DPI_SELECT);
630
631 ret |= anx7625_dsi_video_timing_config(ctx);
632 if (ret < 0) {
633 DRM_DEV_ERROR(dev, "dsi video timing config fail\n");
634 return ret;
635 }
636
637 /* Toggle m, n ready */
638 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6,
639 ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY));
640 usleep_range(1000, 1100);
641 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6,
642 MIPI_M_NUM_READY | MIPI_N_NUM_READY);
643
644 /* Configure integer stable register */
645 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
646 MIPI_VIDEO_STABLE_CNT, 0x02);
647 /* Power on MIPI RX */
648 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
649 MIPI_LANE_CTRL_10, 0x00);
650 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
651 MIPI_LANE_CTRL_10, 0x80);
652
653 if (ret < 0)
654 DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n");
655
656 return ret;
657 }
658
anx7625_dsi_config(struct anx7625_data * ctx)659 static int anx7625_dsi_config(struct anx7625_data *ctx)
660 {
661 struct device *dev = ctx->dev;
662 int ret;
663
664 DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n");
665
666 /* DSC disable */
667 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
668 R_DSC_CTRL_0, ~DSC_EN);
669
670 ret |= anx7625_api_dsi_config(ctx);
671
672 if (ret < 0) {
673 DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n");
674 return ret;
675 }
676
677 /* Set MIPI RX EN */
678 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
679 AP_AV_STATUS, AP_MIPI_RX_EN);
680 /* Clear mute flag */
681 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
682 AP_AV_STATUS, (u8)~AP_MIPI_MUTE);
683 if (ret < 0)
684 DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n");
685 else
686 DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n");
687
688 return ret;
689 }
690
anx7625_api_dpi_config(struct anx7625_data * ctx)691 static int anx7625_api_dpi_config(struct anx7625_data *ctx)
692 {
693 struct device *dev = ctx->dev;
694 u16 freq = ctx->dt.pixelclock.min / 1000;
695 int ret;
696
697 /* configure pixel clock */
698 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
699 PIXEL_CLOCK_L, freq & 0xFF);
700 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
701 PIXEL_CLOCK_H, (freq >> 8));
702
703 /* set DPI mode */
704 /* set to DPI PLL module sel */
705 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
706 MIPI_DIGITAL_PLL_9, 0x20);
707 /* power down MIPI */
708 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
709 MIPI_LANE_CTRL_10, 0x08);
710 /* enable DPI mode */
711 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
712 MIPI_DIGITAL_PLL_18, 0x1C);
713 /* set first edge */
714 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
715 VIDEO_CONTROL_0, 0x06);
716 if (ret < 0)
717 DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n");
718
719 return ret;
720 }
721
anx7625_dpi_config(struct anx7625_data * ctx)722 static int anx7625_dpi_config(struct anx7625_data *ctx)
723 {
724 struct device *dev = ctx->dev;
725 int ret;
726
727 DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n");
728
729 /* DSC disable */
730 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
731 R_DSC_CTRL_0, ~DSC_EN);
732 if (ret < 0) {
733 DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n");
734 return ret;
735 }
736
737 ret = anx7625_config_bit_matrix(ctx);
738 if (ret < 0) {
739 DRM_DEV_ERROR(dev, "config bit matrix failed.\n");
740 return ret;
741 }
742
743 ret = anx7625_api_dpi_config(ctx);
744 if (ret < 0) {
745 DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n");
746 return ret;
747 }
748
749 /* set MIPI RX EN */
750 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
751 AP_AV_STATUS, AP_MIPI_RX_EN);
752 /* clear mute flag */
753 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
754 AP_AV_STATUS, (u8)~AP_MIPI_MUTE);
755 if (ret < 0)
756 DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n");
757
758 return ret;
759 }
760
anx7625_read_flash_status(struct anx7625_data * ctx)761 static int anx7625_read_flash_status(struct anx7625_data *ctx)
762 {
763 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL);
764 }
765
anx7625_hdcp_key_probe(struct anx7625_data * ctx)766 static int anx7625_hdcp_key_probe(struct anx7625_data *ctx)
767 {
768 int ret, val;
769 struct device *dev = ctx->dev;
770 u8 ident[FLASH_BUF_LEN];
771
772 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
773 FLASH_ADDR_HIGH, 0x91);
774 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
775 FLASH_ADDR_LOW, 0xA0);
776 if (ret < 0) {
777 dev_err(dev, "IO error : set key flash address.\n");
778 return ret;
779 }
780
781 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
782 FLASH_LEN_HIGH, (FLASH_BUF_LEN - 1) >> 8);
783 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
784 FLASH_LEN_LOW, (FLASH_BUF_LEN - 1) & 0xFF);
785 if (ret < 0) {
786 dev_err(dev, "IO error : set key flash len.\n");
787 return ret;
788 }
789
790 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
791 R_FLASH_RW_CTRL, FLASH_READ);
792 ret |= readx_poll_timeout(anx7625_read_flash_status,
793 ctx, val,
794 ((val & FLASH_DONE) || (val < 0)),
795 2000,
796 2000 * 150);
797 if (ret) {
798 dev_err(dev, "flash read access fail!\n");
799 return -EIO;
800 }
801
802 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
803 FLASH_BUF_BASE_ADDR,
804 FLASH_BUF_LEN, ident);
805 if (ret < 0) {
806 dev_err(dev, "read flash data fail!\n");
807 return -EIO;
808 }
809
810 if (ident[29] == 0xFF && ident[30] == 0xFF && ident[31] == 0xFF)
811 return -EINVAL;
812
813 return 0;
814 }
815
anx7625_hdcp_key_load(struct anx7625_data * ctx)816 static int anx7625_hdcp_key_load(struct anx7625_data *ctx)
817 {
818 int ret;
819 struct device *dev = ctx->dev;
820
821 /* Select HDCP 1.4 KEY */
822 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
823 R_BOOT_RETRY, 0x12);
824 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
825 FLASH_ADDR_HIGH, HDCP14KEY_START_ADDR >> 8);
826 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
827 FLASH_ADDR_LOW, HDCP14KEY_START_ADDR & 0xFF);
828 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
829 R_RAM_LEN_H, HDCP14KEY_SIZE >> 12);
830 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
831 R_RAM_LEN_L, HDCP14KEY_SIZE >> 4);
832
833 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
834 R_RAM_ADDR_H, 0);
835 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
836 R_RAM_ADDR_L, 0);
837 /* Enable HDCP 1.4 KEY load */
838 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
839 R_RAM_CTRL, DECRYPT_EN | LOAD_START);
840 dev_dbg(dev, "load HDCP 1.4 key done\n");
841 return ret;
842 }
843
anx7625_hdcp_disable(struct anx7625_data * ctx)844 static int anx7625_hdcp_disable(struct anx7625_data *ctx)
845 {
846 int ret;
847 struct device *dev = ctx->dev;
848
849 dev_dbg(dev, "disable HDCP 1.4\n");
850
851 /* Disable HDCP */
852 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
853 /* Try auth flag */
854 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
855 /* Interrupt for DRM */
856 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
857 if (ret < 0)
858 dev_err(dev, "fail to disable HDCP\n");
859
860 return anx7625_write_and(ctx, ctx->i2c.tx_p0_client,
861 TX_HDCP_CTRL0, ~HARD_AUTH_EN & 0xFF);
862 }
863
anx7625_hdcp_enable(struct anx7625_data * ctx)864 static int anx7625_hdcp_enable(struct anx7625_data *ctx)
865 {
866 u8 bcap;
867 int ret;
868 struct device *dev = ctx->dev;
869
870 ret = anx7625_hdcp_key_probe(ctx);
871 if (ret) {
872 dev_dbg(dev, "no key found, not to do hdcp\n");
873 return ret;
874 }
875
876 /* Read downstream capability */
877 ret = anx7625_aux_trans(ctx, DP_AUX_NATIVE_READ, DP_AUX_HDCP_BCAPS, 1, &bcap);
878 if (ret < 0)
879 return ret;
880
881 if (!(bcap & DP_BCAPS_HDCP_CAPABLE)) {
882 pr_warn("downstream not support HDCP 1.4, cap(%x).\n", bcap);
883 return 0;
884 }
885
886 dev_dbg(dev, "enable HDCP 1.4\n");
887
888 /* First clear HDCP state */
889 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
890 TX_HDCP_CTRL0,
891 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN);
892 usleep_range(1000, 1100);
893 /* Second clear HDCP state */
894 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
895 TX_HDCP_CTRL0,
896 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN);
897
898 /* Set time for waiting KSVR */
899 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
900 SP_TX_WAIT_KSVR_TIME, 0xc8);
901 /* Set time for waiting R0 */
902 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
903 SP_TX_WAIT_R0_TIME, 0xb0);
904 ret |= anx7625_hdcp_key_load(ctx);
905 if (ret) {
906 pr_warn("prepare HDCP key failed.\n");
907 return ret;
908 }
909
910 ret = anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20);
911
912 /* Try auth flag */
913 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
914 /* Interrupt for DRM */
915 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
916 if (ret < 0)
917 dev_err(dev, "fail to enable HDCP\n");
918
919 return anx7625_write_or(ctx, ctx->i2c.tx_p0_client,
920 TX_HDCP_CTRL0, HARD_AUTH_EN);
921 }
922
anx7625_dp_start(struct anx7625_data * ctx)923 static void anx7625_dp_start(struct anx7625_data *ctx)
924 {
925 int ret;
926 struct device *dev = ctx->dev;
927 u8 data;
928
929 if (!ctx->display_timing_valid) {
930 DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n");
931 return;
932 }
933
934 dev_dbg(dev, "set downstream sink into normal\n");
935 /* Downstream sink enter into normal mode */
936 data = DP_SET_POWER_D0;
937 ret = anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, DP_SET_POWER, 1, &data);
938 if (ret < 0)
939 dev_err(dev, "IO error : set sink into normal mode fail\n");
940
941 /* Disable HDCP */
942 anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
943
944 if (ctx->pdata.is_dpi)
945 ret = anx7625_dpi_config(ctx);
946 else
947 ret = anx7625_dsi_config(ctx);
948
949 if (ret < 0)
950 DRM_DEV_ERROR(dev, "MIPI phy setup error.\n");
951
952 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
953
954 ctx->dp_en = 1;
955 }
956
anx7625_dp_stop(struct anx7625_data * ctx)957 static void anx7625_dp_stop(struct anx7625_data *ctx)
958 {
959 struct device *dev = ctx->dev;
960 int ret;
961 u8 data;
962
963 DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n");
964
965 /*
966 * Video disable: 0x72:08 bit 7 = 0;
967 * Audio disable: 0x70:87 bit 0 = 0;
968 */
969 ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe);
970 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f);
971
972 ret |= anx7625_video_mute_control(ctx, 1);
973
974 dev_dbg(dev, "notify downstream enter into standby\n");
975 /* Downstream monitor enter into standby mode */
976 data = DP_SET_POWER_D3;
977 ret |= anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, DP_SET_POWER, 1, &data);
978 if (ret < 0)
979 DRM_DEV_ERROR(dev, "IO error : mute video fail\n");
980
981 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
982
983 ctx->dp_en = 0;
984 }
985
sp_tx_rst_aux(struct anx7625_data * ctx)986 static int sp_tx_rst_aux(struct anx7625_data *ctx)
987 {
988 int ret;
989
990 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2,
991 AUX_RST);
992 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2,
993 ~AUX_RST);
994 return ret;
995 }
996
sp_tx_aux_wr(struct anx7625_data * ctx,u8 offset)997 static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset)
998 {
999 int ret;
1000
1001 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1002 AP_AUX_BUFF_START, offset);
1003 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1004 AP_AUX_COMMAND, 0x04);
1005 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
1006 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
1007 return (ret | wait_aux_op_finish(ctx));
1008 }
1009
sp_tx_aux_rd(struct anx7625_data * ctx,u8 len_cmd)1010 static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd)
1011 {
1012 int ret;
1013
1014 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1015 AP_AUX_COMMAND, len_cmd);
1016 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
1017 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
1018 return (ret | wait_aux_op_finish(ctx));
1019 }
1020
sp_tx_get_edid_block(struct anx7625_data * ctx)1021 static int sp_tx_get_edid_block(struct anx7625_data *ctx)
1022 {
1023 int c = 0;
1024 struct device *dev = ctx->dev;
1025
1026 sp_tx_aux_wr(ctx, 0x7e);
1027 sp_tx_aux_rd(ctx, 0x01);
1028 c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START);
1029 if (c < 0) {
1030 DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n");
1031 return -EIO;
1032 }
1033
1034 DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1);
1035
1036 if (c > MAX_EDID_BLOCK)
1037 c = 1;
1038
1039 return c;
1040 }
1041
edid_read(struct anx7625_data * ctx,u8 offset,u8 * pblock_buf)1042 static int edid_read(struct anx7625_data *ctx,
1043 u8 offset, u8 *pblock_buf)
1044 {
1045 int ret, cnt;
1046 struct device *dev = ctx->dev;
1047
1048 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) {
1049 sp_tx_aux_wr(ctx, offset);
1050 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */
1051 ret = sp_tx_aux_rd(ctx, 0xf1);
1052
1053 if (ret) {
1054 ret = sp_tx_rst_aux(ctx);
1055 DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n");
1056 } else {
1057 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
1058 AP_AUX_BUFF_START,
1059 MAX_DPCD_BUFFER_SIZE,
1060 pblock_buf);
1061 if (ret > 0)
1062 break;
1063 }
1064 }
1065
1066 if (cnt > EDID_TRY_CNT)
1067 return -EIO;
1068
1069 return ret;
1070 }
1071
segments_edid_read(struct anx7625_data * ctx,u8 segment,u8 * buf,u8 offset)1072 static int segments_edid_read(struct anx7625_data *ctx,
1073 u8 segment, u8 *buf, u8 offset)
1074 {
1075 u8 cnt;
1076 int ret;
1077 struct device *dev = ctx->dev;
1078
1079 /* Write address only */
1080 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1081 AP_AUX_ADDR_7_0, 0x30);
1082 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1083 AP_AUX_COMMAND, 0x04);
1084 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1085 AP_AUX_CTRL_STATUS,
1086 AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN);
1087
1088 ret |= wait_aux_op_finish(ctx);
1089 /* Write segment address */
1090 ret |= sp_tx_aux_wr(ctx, segment);
1091 /* Data read */
1092 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1093 AP_AUX_ADDR_7_0, 0x50);
1094 if (ret) {
1095 DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n");
1096 return ret;
1097 }
1098
1099 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) {
1100 sp_tx_aux_wr(ctx, offset);
1101 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */
1102 ret = sp_tx_aux_rd(ctx, 0xf1);
1103
1104 if (ret) {
1105 ret = sp_tx_rst_aux(ctx);
1106 DRM_DEV_ERROR(dev, "segment read fail, reset!\n");
1107 } else {
1108 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
1109 AP_AUX_BUFF_START,
1110 MAX_DPCD_BUFFER_SIZE, buf);
1111 if (ret > 0)
1112 break;
1113 }
1114 }
1115
1116 if (cnt > EDID_TRY_CNT)
1117 return -EIO;
1118
1119 return ret;
1120 }
1121
sp_tx_edid_read(struct anx7625_data * ctx,u8 * pedid_blocks_buf)1122 static int sp_tx_edid_read(struct anx7625_data *ctx,
1123 u8 *pedid_blocks_buf)
1124 {
1125 u8 offset;
1126 int edid_pos;
1127 int count, blocks_num;
1128 u8 pblock_buf[MAX_DPCD_BUFFER_SIZE];
1129 u8 i, j;
1130 int g_edid_break = 0;
1131 int ret;
1132 struct device *dev = ctx->dev;
1133
1134 /* Address initial */
1135 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1136 AP_AUX_ADDR_7_0, 0x50);
1137 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1138 AP_AUX_ADDR_15_8, 0);
1139 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
1140 AP_AUX_ADDR_19_16, 0xf0);
1141 if (ret < 0) {
1142 DRM_DEV_ERROR(dev, "access aux channel IO error.\n");
1143 return -EIO;
1144 }
1145
1146 blocks_num = sp_tx_get_edid_block(ctx);
1147 if (blocks_num < 0)
1148 return blocks_num;
1149
1150 count = 0;
1151
1152 do {
1153 switch (count) {
1154 case 0:
1155 case 1:
1156 for (i = 0; i < 8; i++) {
1157 offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE;
1158 g_edid_break = edid_read(ctx, offset,
1159 pblock_buf);
1160
1161 if (g_edid_break < 0)
1162 break;
1163
1164 memcpy(&pedid_blocks_buf[offset],
1165 pblock_buf,
1166 MAX_DPCD_BUFFER_SIZE);
1167 }
1168
1169 break;
1170 case 2:
1171 offset = 0x00;
1172
1173 for (j = 0; j < 8; j++) {
1174 edid_pos = (j + count * 8) *
1175 MAX_DPCD_BUFFER_SIZE;
1176
1177 if (g_edid_break == 1)
1178 break;
1179
1180 ret = segments_edid_read(ctx, count / 2,
1181 pblock_buf, offset);
1182 if (ret < 0)
1183 return ret;
1184
1185 memcpy(&pedid_blocks_buf[edid_pos],
1186 pblock_buf,
1187 MAX_DPCD_BUFFER_SIZE);
1188 offset = offset + 0x10;
1189 }
1190
1191 break;
1192 case 3:
1193 offset = 0x80;
1194
1195 for (j = 0; j < 8; j++) {
1196 edid_pos = (j + count * 8) *
1197 MAX_DPCD_BUFFER_SIZE;
1198 if (g_edid_break == 1)
1199 break;
1200
1201 ret = segments_edid_read(ctx, count / 2,
1202 pblock_buf, offset);
1203 if (ret < 0)
1204 return ret;
1205
1206 memcpy(&pedid_blocks_buf[edid_pos],
1207 pblock_buf,
1208 MAX_DPCD_BUFFER_SIZE);
1209 offset = offset + 0x10;
1210 }
1211
1212 break;
1213 default:
1214 break;
1215 }
1216
1217 count++;
1218
1219 } while (blocks_num >= count);
1220
1221 /* Check edid data */
1222 if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) {
1223 DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n");
1224 return -EINVAL;
1225 }
1226
1227 /* Reset aux channel */
1228 ret = sp_tx_rst_aux(ctx);
1229 if (ret < 0) {
1230 DRM_DEV_ERROR(dev, "Failed to reset aux channel!\n");
1231 return ret;
1232 }
1233
1234 return (blocks_num + 1);
1235 }
1236
anx7625_power_on(struct anx7625_data * ctx)1237 static void anx7625_power_on(struct anx7625_data *ctx)
1238 {
1239 struct device *dev = ctx->dev;
1240 int ret, i;
1241
1242 if (!ctx->pdata.low_power_mode) {
1243 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n");
1244 return;
1245 }
1246
1247 for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) {
1248 ret = regulator_enable(ctx->pdata.supplies[i].consumer);
1249 if (ret < 0) {
1250 DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n",
1251 i, ret);
1252 goto reg_err;
1253 }
1254 usleep_range(2000, 2100);
1255 }
1256
1257 usleep_range(11000, 12000);
1258
1259 /* Power on pin enable */
1260 gpiod_set_value(ctx->pdata.gpio_p_on, 1);
1261 usleep_range(10000, 11000);
1262 /* Power reset pin enable */
1263 gpiod_set_value(ctx->pdata.gpio_reset, 1);
1264 usleep_range(10000, 11000);
1265
1266 DRM_DEV_DEBUG_DRIVER(dev, "power on !\n");
1267 return;
1268 reg_err:
1269 for (--i; i >= 0; i--)
1270 regulator_disable(ctx->pdata.supplies[i].consumer);
1271 }
1272
anx7625_power_standby(struct anx7625_data * ctx)1273 static void anx7625_power_standby(struct anx7625_data *ctx)
1274 {
1275 struct device *dev = ctx->dev;
1276 int ret;
1277
1278 if (!ctx->pdata.low_power_mode) {
1279 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n");
1280 return;
1281 }
1282
1283 gpiod_set_value(ctx->pdata.gpio_reset, 0);
1284 usleep_range(1000, 1100);
1285 gpiod_set_value(ctx->pdata.gpio_p_on, 0);
1286 usleep_range(1000, 1100);
1287
1288 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies),
1289 ctx->pdata.supplies);
1290 if (ret < 0)
1291 DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret);
1292
1293 DRM_DEV_DEBUG_DRIVER(dev, "power down\n");
1294 }
1295
1296 /* Basic configurations of ANX7625 */
anx7625_config(struct anx7625_data * ctx)1297 static void anx7625_config(struct anx7625_data *ctx)
1298 {
1299 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1300 XTAL_FRQ_SEL, XTAL_FRQ_27M);
1301 }
1302
anx7625_hpd_timer_config(struct anx7625_data * ctx)1303 static int anx7625_hpd_timer_config(struct anx7625_data *ctx)
1304 {
1305 int ret;
1306
1307 /* Set irq detect window to 2ms */
1308 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
1309 HPD_DET_TIMER_BIT0_7, HPD_TIME & 0xFF);
1310 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
1311 HPD_DET_TIMER_BIT8_15,
1312 (HPD_TIME >> 8) & 0xFF);
1313 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
1314 HPD_DET_TIMER_BIT16_23,
1315 (HPD_TIME >> 16) & 0xFF);
1316
1317 return ret;
1318 }
1319
anx7625_read_hpd_gpio_config_status(struct anx7625_data * ctx)1320 static int anx7625_read_hpd_gpio_config_status(struct anx7625_data *ctx)
1321 {
1322 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, GPIO_CTRL_2);
1323 }
1324
anx7625_disable_pd_protocol(struct anx7625_data * ctx)1325 static void anx7625_disable_pd_protocol(struct anx7625_data *ctx)
1326 {
1327 struct device *dev = ctx->dev;
1328 int ret, val;
1329
1330 /* Reset main ocm */
1331 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40);
1332 /* Disable PD */
1333 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1334 AP_AV_STATUS, AP_DISABLE_PD);
1335 /* Release main ocm */
1336 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00);
1337
1338 if (ret < 0)
1339 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n");
1340 else
1341 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n");
1342
1343 /*
1344 * Make sure the HPD GPIO already be configured after OCM release before
1345 * setting HPD detect window register. Here we poll the status register
1346 * at maximum 40ms, then config HPD irq detect window register
1347 */
1348 readx_poll_timeout(anx7625_read_hpd_gpio_config_status,
1349 ctx, val,
1350 ((val & HPD_SOURCE) || (val < 0)),
1351 2000, 2000 * 20);
1352
1353 /* Set HPD irq detect window to 2ms */
1354 anx7625_hpd_timer_config(ctx);
1355 }
1356
anx7625_ocm_loading_check(struct anx7625_data * ctx)1357 static int anx7625_ocm_loading_check(struct anx7625_data *ctx)
1358 {
1359 int ret;
1360 struct device *dev = ctx->dev;
1361
1362 /* Check interface workable */
1363 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
1364 FLASH_LOAD_STA);
1365 if (ret < 0) {
1366 DRM_DEV_ERROR(dev, "IO error : access flash load.\n");
1367 return ret;
1368 }
1369 if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK)
1370 return -ENODEV;
1371
1372 anx7625_disable_pd_protocol(ctx);
1373
1374 DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,",
1375 anx7625_reg_read(ctx,
1376 ctx->i2c.rx_p0_client,
1377 OCM_FW_VERSION),
1378 anx7625_reg_read(ctx,
1379 ctx->i2c.rx_p0_client,
1380 OCM_FW_REVERSION));
1381 DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n",
1382 ANX7625_DRV_VERSION);
1383
1384 return 0;
1385 }
1386
anx7625_power_on_init(struct anx7625_data * ctx)1387 static void anx7625_power_on_init(struct anx7625_data *ctx)
1388 {
1389 int retry_count, i;
1390
1391 for (retry_count = 0; retry_count < 3; retry_count++) {
1392 anx7625_power_on(ctx);
1393 anx7625_config(ctx);
1394
1395 for (i = 0; i < OCM_LOADING_TIME; i++) {
1396 if (!anx7625_ocm_loading_check(ctx))
1397 return;
1398 usleep_range(1000, 1100);
1399 }
1400 anx7625_power_standby(ctx);
1401 }
1402 }
1403
anx7625_init_gpio(struct anx7625_data * platform)1404 static void anx7625_init_gpio(struct anx7625_data *platform)
1405 {
1406 struct device *dev = platform->dev;
1407
1408 DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n");
1409
1410 /* Gpio for chip power enable */
1411 platform->pdata.gpio_p_on =
1412 devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW);
1413 if (IS_ERR_OR_NULL(platform->pdata.gpio_p_on)) {
1414 DRM_DEV_DEBUG_DRIVER(dev, "no enable gpio found\n");
1415 platform->pdata.gpio_p_on = NULL;
1416 }
1417
1418 /* Gpio for chip reset */
1419 platform->pdata.gpio_reset =
1420 devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1421 if (IS_ERR_OR_NULL(platform->pdata.gpio_reset)) {
1422 DRM_DEV_DEBUG_DRIVER(dev, "no reset gpio found\n");
1423 platform->pdata.gpio_reset = NULL;
1424 }
1425
1426 if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) {
1427 platform->pdata.low_power_mode = 1;
1428 DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n",
1429 desc_to_gpio(platform->pdata.gpio_p_on),
1430 desc_to_gpio(platform->pdata.gpio_reset));
1431 } else {
1432 platform->pdata.low_power_mode = 0;
1433 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n");
1434 }
1435 }
1436
anx7625_stop_dp_work(struct anx7625_data * ctx)1437 static void anx7625_stop_dp_work(struct anx7625_data *ctx)
1438 {
1439 ctx->hpd_status = 0;
1440 ctx->hpd_high_cnt = 0;
1441 }
1442
anx7625_start_dp_work(struct anx7625_data * ctx)1443 static void anx7625_start_dp_work(struct anx7625_data *ctx)
1444 {
1445 int ret;
1446 struct device *dev = ctx->dev;
1447
1448 if (ctx->hpd_high_cnt >= 2) {
1449 DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n");
1450 return;
1451 }
1452
1453 ctx->hpd_status = 1;
1454 ctx->hpd_high_cnt++;
1455
1456 /* Not support HDCP */
1457 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
1458
1459 /* Try auth flag */
1460 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
1461 /* Interrupt for DRM */
1462 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
1463 if (ret < 0) {
1464 DRM_DEV_ERROR(dev, "fail to setting HDCP/auth\n");
1465 return;
1466 }
1467
1468 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86);
1469 if (ret < 0)
1470 return;
1471
1472 DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret);
1473 }
1474
anx7625_read_hpd_status_p0(struct anx7625_data * ctx)1475 static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx)
1476 {
1477 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS);
1478 }
1479
_anx7625_hpd_polling(struct anx7625_data * ctx,unsigned long wait_us)1480 static int _anx7625_hpd_polling(struct anx7625_data *ctx,
1481 unsigned long wait_us)
1482 {
1483 int ret, val;
1484 struct device *dev = ctx->dev;
1485
1486 /* Interrupt mode, no need poll HPD status, just return */
1487 if (ctx->pdata.intp_irq)
1488 return 0;
1489
1490 ret = readx_poll_timeout(anx7625_read_hpd_status_p0,
1491 ctx, val,
1492 ((val & HPD_STATUS) || (val < 0)),
1493 wait_us / 100,
1494 wait_us);
1495 if (ret) {
1496 DRM_DEV_ERROR(dev, "no hpd.\n");
1497 return ret;
1498 }
1499
1500 DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val);
1501 anx7625_reg_write(ctx, ctx->i2c.tcpc_client,
1502 INTR_ALERT_1, 0xFF);
1503 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1504 INTERFACE_CHANGE_INT, 0);
1505
1506 anx7625_start_dp_work(ctx);
1507
1508 if (!ctx->pdata.panel_bridge && ctx->bridge_attached)
1509 drm_helper_hpd_irq_event(ctx->bridge.dev);
1510
1511 return 0;
1512 }
1513
anx7625_wait_hpd_asserted(struct drm_dp_aux * aux,unsigned long wait_us)1514 static int anx7625_wait_hpd_asserted(struct drm_dp_aux *aux,
1515 unsigned long wait_us)
1516 {
1517 struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux);
1518 struct device *dev = ctx->dev;
1519 int ret;
1520
1521 pm_runtime_get_sync(dev);
1522 ret = _anx7625_hpd_polling(ctx, wait_us);
1523 pm_runtime_mark_last_busy(dev);
1524 pm_runtime_put_autosuspend(dev);
1525
1526 return ret;
1527 }
1528
anx7625_remove_edid(struct anx7625_data * ctx)1529 static void anx7625_remove_edid(struct anx7625_data *ctx)
1530 {
1531 drm_edid_free(ctx->cached_drm_edid);
1532 ctx->cached_drm_edid = NULL;
1533 }
1534
anx7625_dp_adjust_swing(struct anx7625_data * ctx)1535 static void anx7625_dp_adjust_swing(struct anx7625_data *ctx)
1536 {
1537 int i;
1538
1539 for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++)
1540 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client,
1541 DP_TX_LANE0_SWING_REG0 + i,
1542 ctx->pdata.lane0_reg_data[i]);
1543
1544 for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++)
1545 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client,
1546 DP_TX_LANE1_SWING_REG0 + i,
1547 ctx->pdata.lane1_reg_data[i]);
1548 }
1549
dp_hpd_change_handler(struct anx7625_data * ctx,bool on)1550 static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on)
1551 {
1552 struct device *dev = ctx->dev;
1553
1554 /* HPD changed */
1555 DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n",
1556 (u32)on);
1557
1558 if (on == 0) {
1559 DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n");
1560 anx7625_remove_edid(ctx);
1561 anx7625_stop_dp_work(ctx);
1562 } else {
1563 DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n");
1564 anx7625_start_dp_work(ctx);
1565 anx7625_dp_adjust_swing(ctx);
1566 }
1567 }
1568
anx7625_hpd_change_detect(struct anx7625_data * ctx)1569 static int anx7625_hpd_change_detect(struct anx7625_data *ctx)
1570 {
1571 int intr_vector, status;
1572 struct device *dev = ctx->dev;
1573
1574 status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client,
1575 INTR_ALERT_1, 0xFF);
1576 if (status < 0) {
1577 DRM_DEV_ERROR(dev, "cannot clear alert reg.\n");
1578 return status;
1579 }
1580
1581 intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
1582 INTERFACE_CHANGE_INT);
1583 if (intr_vector < 0) {
1584 DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n");
1585 return intr_vector;
1586 }
1587 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector);
1588 status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1589 INTERFACE_CHANGE_INT,
1590 intr_vector & (~intr_vector));
1591 if (status < 0) {
1592 DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n");
1593 return status;
1594 }
1595
1596 if (!(intr_vector & HPD_STATUS_CHANGE))
1597 return -ENOENT;
1598
1599 status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
1600 SYSTEM_STSTUS);
1601 if (status < 0) {
1602 DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n");
1603 return status;
1604 }
1605
1606 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status);
1607 dp_hpd_change_handler(ctx, status & HPD_STATUS);
1608
1609 return 0;
1610 }
1611
anx7625_work_func(struct work_struct * work)1612 static void anx7625_work_func(struct work_struct *work)
1613 {
1614 int event;
1615 struct anx7625_data *ctx = container_of(work,
1616 struct anx7625_data, work);
1617
1618 mutex_lock(&ctx->lock);
1619
1620 if (pm_runtime_suspended(ctx->dev)) {
1621 mutex_unlock(&ctx->lock);
1622 return;
1623 }
1624
1625 event = anx7625_hpd_change_detect(ctx);
1626
1627 mutex_unlock(&ctx->lock);
1628
1629 if (event < 0)
1630 return;
1631
1632 if (ctx->bridge_attached)
1633 drm_helper_hpd_irq_event(ctx->bridge.dev);
1634 }
1635
anx7625_intr_hpd_isr(int irq,void * data)1636 static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data)
1637 {
1638 struct anx7625_data *ctx = (struct anx7625_data *)data;
1639
1640 queue_work(ctx->workqueue, &ctx->work);
1641
1642 return IRQ_HANDLED;
1643 }
1644
anx7625_get_swing_setting(struct device * dev,struct anx7625_platform_data * pdata)1645 static int anx7625_get_swing_setting(struct device *dev,
1646 struct anx7625_platform_data *pdata)
1647 {
1648 int num_regs;
1649
1650 num_regs = of_property_read_variable_u8_array(dev->of_node, "analogix,lane0-swing",
1651 pdata->lane0_reg_data, 1, DP_TX_SWING_REG_CNT);
1652 if (num_regs > 0)
1653 pdata->dp_lane0_swing_reg_cnt = num_regs;
1654
1655 num_regs = of_property_read_variable_u8_array(dev->of_node, "analogix,lane1-swing",
1656 pdata->lane1_reg_data, 1, DP_TX_SWING_REG_CNT);
1657 if (num_regs > 0)
1658 pdata->dp_lane1_swing_reg_cnt = num_regs;
1659
1660 return 0;
1661 }
1662
anx7625_parse_dt(struct device * dev,struct anx7625_platform_data * pdata)1663 static int anx7625_parse_dt(struct device *dev,
1664 struct anx7625_platform_data *pdata)
1665 {
1666 struct device_node *np = dev->of_node, *ep0;
1667 int bus_type, mipi_lanes;
1668
1669 anx7625_get_swing_setting(dev, pdata);
1670
1671 pdata->is_dpi = 0; /* default dsi mode */
1672 of_node_put(pdata->mipi_host_node);
1673 pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0);
1674 if (!pdata->mipi_host_node) {
1675 DRM_DEV_ERROR(dev, "fail to get internal panel.\n");
1676 return -ENODEV;
1677 }
1678
1679 bus_type = 0;
1680 mipi_lanes = MAX_LANES_SUPPORT;
1681 ep0 = of_graph_get_endpoint_by_regs(np, 0, 0);
1682 if (ep0) {
1683 if (of_property_read_u32(ep0, "bus-type", &bus_type))
1684 bus_type = 0;
1685
1686 mipi_lanes = drm_of_get_data_lanes_count(ep0, 1, MAX_LANES_SUPPORT);
1687 of_node_put(ep0);
1688 }
1689
1690 if (bus_type == V4L2_FWNODE_BUS_TYPE_DPI) /* bus type is DPI */
1691 pdata->is_dpi = 1;
1692
1693 pdata->mipi_lanes = MAX_LANES_SUPPORT;
1694 if (mipi_lanes > 0)
1695 pdata->mipi_lanes = mipi_lanes;
1696
1697 if (pdata->is_dpi)
1698 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DPI host node.\n");
1699 else
1700 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DSI host node.\n");
1701
1702 if (of_property_read_bool(np, "analogix,audio-enable"))
1703 pdata->audio_en = 1;
1704
1705 return 0;
1706 }
1707
anx7625_parse_dt_panel(struct device * dev,struct anx7625_platform_data * pdata)1708 static int anx7625_parse_dt_panel(struct device *dev,
1709 struct anx7625_platform_data *pdata)
1710 {
1711 struct device_node *np = dev->of_node;
1712
1713 pdata->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0);
1714 if (IS_ERR(pdata->panel_bridge)) {
1715 if (PTR_ERR(pdata->panel_bridge) == -ENODEV) {
1716 pdata->panel_bridge = NULL;
1717 return 0;
1718 }
1719
1720 return PTR_ERR(pdata->panel_bridge);
1721 }
1722
1723 DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n");
1724
1725 return 0;
1726 }
1727
anx7625_of_panel_on_aux_bus(struct device * dev)1728 static bool anx7625_of_panel_on_aux_bus(struct device *dev)
1729 {
1730 struct device_node *bus, *panel;
1731
1732 bus = of_get_child_by_name(dev->of_node, "aux-bus");
1733 if (!bus)
1734 return false;
1735
1736 panel = of_get_child_by_name(bus, "panel");
1737 of_node_put(bus);
1738 if (!panel)
1739 return false;
1740 of_node_put(panel);
1741
1742 return true;
1743 }
1744
bridge_to_anx7625(struct drm_bridge * bridge)1745 static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge)
1746 {
1747 return container_of(bridge, struct anx7625_data, bridge);
1748 }
1749
anx7625_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)1750 static ssize_t anx7625_aux_transfer(struct drm_dp_aux *aux,
1751 struct drm_dp_aux_msg *msg)
1752 {
1753 struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux);
1754 struct device *dev = ctx->dev;
1755 u8 request = msg->request & ~DP_AUX_I2C_MOT;
1756 int ret = 0;
1757
1758 mutex_lock(&ctx->aux_lock);
1759 pm_runtime_get_sync(dev);
1760 msg->reply = 0;
1761 switch (request) {
1762 case DP_AUX_NATIVE_WRITE:
1763 case DP_AUX_I2C_WRITE:
1764 case DP_AUX_NATIVE_READ:
1765 case DP_AUX_I2C_READ:
1766 break;
1767 default:
1768 ret = -EINVAL;
1769 }
1770 if (!ret)
1771 ret = anx7625_aux_trans(ctx, msg->request, msg->address,
1772 msg->size, msg->buffer);
1773 pm_runtime_mark_last_busy(dev);
1774 pm_runtime_put_autosuspend(dev);
1775 mutex_unlock(&ctx->aux_lock);
1776
1777 return ret;
1778 }
1779
anx7625_edid_read(struct anx7625_data * ctx)1780 static const struct drm_edid *anx7625_edid_read(struct anx7625_data *ctx)
1781 {
1782 struct device *dev = ctx->dev;
1783 u8 *edid_buf;
1784 int edid_num;
1785
1786 if (ctx->cached_drm_edid)
1787 goto out;
1788
1789 edid_buf = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL);
1790 if (!edid_buf)
1791 return NULL;
1792
1793 pm_runtime_get_sync(dev);
1794 _anx7625_hpd_polling(ctx, 5000 * 100);
1795 edid_num = sp_tx_edid_read(ctx, edid_buf);
1796 pm_runtime_put_sync(dev);
1797
1798 if (edid_num < 1) {
1799 DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num);
1800 kfree(edid_buf);
1801 return NULL;
1802 }
1803
1804 ctx->cached_drm_edid = drm_edid_alloc(edid_buf, FOUR_BLOCK_SIZE);
1805 kfree(edid_buf);
1806
1807 out:
1808 return drm_edid_dup(ctx->cached_drm_edid);
1809 }
1810
anx7625_sink_detect(struct anx7625_data * ctx)1811 static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx)
1812 {
1813 struct device *dev = ctx->dev;
1814
1815 DRM_DEV_DEBUG_DRIVER(dev, "sink detect\n");
1816
1817 if (ctx->pdata.panel_bridge)
1818 return connector_status_connected;
1819
1820 return ctx->hpd_status ? connector_status_connected :
1821 connector_status_disconnected;
1822 }
1823
anx7625_audio_hw_params(struct device * dev,void * data,struct hdmi_codec_daifmt * fmt,struct hdmi_codec_params * params)1824 static int anx7625_audio_hw_params(struct device *dev, void *data,
1825 struct hdmi_codec_daifmt *fmt,
1826 struct hdmi_codec_params *params)
1827 {
1828 struct anx7625_data *ctx = dev_get_drvdata(dev);
1829 int wl, ch, rate;
1830 int ret = 0;
1831
1832 if (anx7625_sink_detect(ctx) == connector_status_disconnected) {
1833 DRM_DEV_DEBUG_DRIVER(dev, "DP not connected\n");
1834 return 0;
1835 }
1836
1837 if (fmt->fmt != HDMI_DSP_A && fmt->fmt != HDMI_I2S) {
1838 DRM_DEV_ERROR(dev, "only supports DSP_A & I2S\n");
1839 return -EINVAL;
1840 }
1841
1842 DRM_DEV_DEBUG_DRIVER(dev, "setting %d Hz, %d bit, %d channels\n",
1843 params->sample_rate, params->sample_width,
1844 params->cea.channels);
1845
1846 if (fmt->fmt == HDMI_DSP_A)
1847 ret = anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1848 AUDIO_CHANNEL_STATUS_6,
1849 ~I2S_SLAVE_MODE,
1850 TDM_SLAVE_MODE);
1851 else
1852 ret = anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1853 AUDIO_CHANNEL_STATUS_6,
1854 ~TDM_SLAVE_MODE,
1855 I2S_SLAVE_MODE);
1856
1857 /* Word length */
1858 switch (params->sample_width) {
1859 case 16:
1860 wl = AUDIO_W_LEN_16_20MAX;
1861 break;
1862 case 18:
1863 wl = AUDIO_W_LEN_18_20MAX;
1864 break;
1865 case 20:
1866 wl = AUDIO_W_LEN_20_20MAX;
1867 break;
1868 case 24:
1869 wl = AUDIO_W_LEN_24_24MAX;
1870 break;
1871 default:
1872 DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support",
1873 params->sample_width);
1874 return -EINVAL;
1875 }
1876 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1877 AUDIO_CHANNEL_STATUS_5,
1878 0xf0, wl);
1879
1880 /* Channel num */
1881 switch (params->cea.channels) {
1882 case 2:
1883 ch = I2S_CH_2;
1884 break;
1885 case 4:
1886 ch = TDM_CH_4;
1887 break;
1888 case 6:
1889 ch = TDM_CH_6;
1890 break;
1891 case 8:
1892 ch = TDM_CH_8;
1893 break;
1894 default:
1895 DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support",
1896 params->cea.channels);
1897 return -EINVAL;
1898 }
1899 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1900 AUDIO_CHANNEL_STATUS_6, 0x1f, ch << 5);
1901 if (ch > I2S_CH_2)
1902 ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client,
1903 AUDIO_CHANNEL_STATUS_6, AUDIO_LAYOUT);
1904 else
1905 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client,
1906 AUDIO_CHANNEL_STATUS_6, ~AUDIO_LAYOUT);
1907
1908 /* FS */
1909 switch (params->sample_rate) {
1910 case 32000:
1911 rate = AUDIO_FS_32K;
1912 break;
1913 case 44100:
1914 rate = AUDIO_FS_441K;
1915 break;
1916 case 48000:
1917 rate = AUDIO_FS_48K;
1918 break;
1919 case 88200:
1920 rate = AUDIO_FS_882K;
1921 break;
1922 case 96000:
1923 rate = AUDIO_FS_96K;
1924 break;
1925 case 176400:
1926 rate = AUDIO_FS_1764K;
1927 break;
1928 case 192000:
1929 rate = AUDIO_FS_192K;
1930 break;
1931 default:
1932 DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d not support",
1933 params->sample_rate);
1934 return -EINVAL;
1935 }
1936 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1937 AUDIO_CHANNEL_STATUS_4,
1938 0xf0, rate);
1939 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
1940 AP_AV_STATUS, AP_AUDIO_CHG);
1941 if (ret < 0) {
1942 DRM_DEV_ERROR(dev, "IO error : config audio.\n");
1943 return -EIO;
1944 }
1945
1946 return 0;
1947 }
1948
anx7625_audio_shutdown(struct device * dev,void * data)1949 static void anx7625_audio_shutdown(struct device *dev, void *data)
1950 {
1951 DRM_DEV_DEBUG_DRIVER(dev, "stop audio\n");
1952 }
1953
anx7625_hdmi_i2s_get_dai_id(struct snd_soc_component * component,struct device_node * endpoint)1954 static int anx7625_hdmi_i2s_get_dai_id(struct snd_soc_component *component,
1955 struct device_node *endpoint)
1956 {
1957 struct of_endpoint of_ep;
1958 int ret;
1959
1960 ret = of_graph_parse_endpoint(endpoint, &of_ep);
1961 if (ret < 0)
1962 return ret;
1963
1964 /*
1965 * HDMI sound should be located at external DPI port
1966 * Didn't have good way to check where is internal(DSI)
1967 * or external(DPI) bridge
1968 */
1969 return 0;
1970 }
1971
1972 static void
anx7625_audio_update_connector_status(struct anx7625_data * ctx,enum drm_connector_status status)1973 anx7625_audio_update_connector_status(struct anx7625_data *ctx,
1974 enum drm_connector_status status)
1975 {
1976 if (ctx->plugged_cb && ctx->codec_dev) {
1977 ctx->plugged_cb(ctx->codec_dev,
1978 status == connector_status_connected);
1979 }
1980 }
1981
anx7625_audio_hook_plugged_cb(struct device * dev,void * data,hdmi_codec_plugged_cb fn,struct device * codec_dev)1982 static int anx7625_audio_hook_plugged_cb(struct device *dev, void *data,
1983 hdmi_codec_plugged_cb fn,
1984 struct device *codec_dev)
1985 {
1986 struct anx7625_data *ctx = data;
1987
1988 ctx->plugged_cb = fn;
1989 ctx->codec_dev = codec_dev;
1990 anx7625_audio_update_connector_status(ctx, anx7625_sink_detect(ctx));
1991
1992 return 0;
1993 }
1994
anx7625_audio_get_eld(struct device * dev,void * data,u8 * buf,size_t len)1995 static int anx7625_audio_get_eld(struct device *dev, void *data,
1996 u8 *buf, size_t len)
1997 {
1998 struct anx7625_data *ctx = dev_get_drvdata(dev);
1999
2000 if (!ctx->connector) {
2001 /* Pass en empty ELD if connector not available */
2002 memset(buf, 0, len);
2003 } else {
2004 dev_dbg(dev, "audio copy eld\n");
2005 memcpy(buf, ctx->connector->eld,
2006 min(sizeof(ctx->connector->eld), len));
2007 }
2008
2009 return 0;
2010 }
2011
2012 static const struct hdmi_codec_ops anx7625_codec_ops = {
2013 .hw_params = anx7625_audio_hw_params,
2014 .audio_shutdown = anx7625_audio_shutdown,
2015 .get_eld = anx7625_audio_get_eld,
2016 .get_dai_id = anx7625_hdmi_i2s_get_dai_id,
2017 .hook_plugged_cb = anx7625_audio_hook_plugged_cb,
2018 };
2019
anx7625_unregister_audio(struct anx7625_data * ctx)2020 static void anx7625_unregister_audio(struct anx7625_data *ctx)
2021 {
2022 struct device *dev = ctx->dev;
2023
2024 if (ctx->audio_pdev) {
2025 platform_device_unregister(ctx->audio_pdev);
2026 ctx->audio_pdev = NULL;
2027 }
2028
2029 DRM_DEV_DEBUG_DRIVER(dev, "unbound to %s", HDMI_CODEC_DRV_NAME);
2030 }
2031
anx7625_register_audio(struct device * dev,struct anx7625_data * ctx)2032 static int anx7625_register_audio(struct device *dev, struct anx7625_data *ctx)
2033 {
2034 struct hdmi_codec_pdata codec_data = {
2035 .ops = &anx7625_codec_ops,
2036 .max_i2s_channels = 8,
2037 .i2s = 1,
2038 .data = ctx,
2039 };
2040
2041 ctx->audio_pdev = platform_device_register_data(dev,
2042 HDMI_CODEC_DRV_NAME,
2043 PLATFORM_DEVID_AUTO,
2044 &codec_data,
2045 sizeof(codec_data));
2046
2047 if (IS_ERR(ctx->audio_pdev))
2048 return PTR_ERR(ctx->audio_pdev);
2049
2050 DRM_DEV_DEBUG_DRIVER(dev, "bound to %s", HDMI_CODEC_DRV_NAME);
2051
2052 return 0;
2053 }
2054
anx7625_setup_dsi_device(struct anx7625_data * ctx)2055 static int anx7625_setup_dsi_device(struct anx7625_data *ctx)
2056 {
2057 struct mipi_dsi_device *dsi;
2058 struct device *dev = ctx->dev;
2059 struct mipi_dsi_host *host;
2060 const struct mipi_dsi_device_info info = {
2061 .type = "anx7625",
2062 .channel = 0,
2063 .node = NULL,
2064 };
2065
2066 host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node);
2067 if (!host)
2068 return dev_err_probe(dev, -EPROBE_DEFER, "fail to find dsi host.\n");
2069
2070 dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
2071 if (IS_ERR(dsi)) {
2072 DRM_DEV_ERROR(dev, "fail to create dsi device.\n");
2073 return -EINVAL;
2074 }
2075
2076 dsi->lanes = ctx->pdata.mipi_lanes;
2077 dsi->format = MIPI_DSI_FMT_RGB888;
2078 dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
2079 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
2080 MIPI_DSI_MODE_VIDEO_HSE |
2081 MIPI_DSI_HS_PKT_END_ALIGNED;
2082
2083 ctx->dsi = dsi;
2084
2085 return 0;
2086 }
2087
anx7625_attach_dsi(struct anx7625_data * ctx)2088 static int anx7625_attach_dsi(struct anx7625_data *ctx)
2089 {
2090 struct device *dev = ctx->dev;
2091 int ret;
2092
2093 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n");
2094
2095 ret = devm_mipi_dsi_attach(dev, ctx->dsi);
2096 if (ret) {
2097 DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n");
2098 return ret;
2099 }
2100
2101 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n");
2102
2103 return 0;
2104 }
2105
hdcp_check_work_func(struct work_struct * work)2106 static void hdcp_check_work_func(struct work_struct *work)
2107 {
2108 u8 status;
2109 struct delayed_work *dwork;
2110 struct anx7625_data *ctx;
2111 struct device *dev;
2112 struct drm_device *drm_dev;
2113
2114 dwork = to_delayed_work(work);
2115 ctx = container_of(dwork, struct anx7625_data, hdcp_work);
2116 dev = ctx->dev;
2117
2118 if (!ctx->connector) {
2119 dev_err(dev, "HDCP connector is null!");
2120 return;
2121 }
2122
2123 drm_dev = ctx->connector->dev;
2124 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2125 mutex_lock(&ctx->hdcp_wq_lock);
2126
2127 status = anx7625_reg_read(ctx, ctx->i2c.tx_p0_client, 0);
2128 dev_dbg(dev, "sink HDCP status check: %.02x\n", status);
2129 if (status & BIT(1)) {
2130 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_ENABLED;
2131 drm_hdcp_update_content_protection(ctx->connector,
2132 ctx->hdcp_cp);
2133 dev_dbg(dev, "update CP to ENABLE\n");
2134 }
2135
2136 mutex_unlock(&ctx->hdcp_wq_lock);
2137 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2138 }
2139
anx7625_connector_atomic_check(struct anx7625_data * ctx,struct drm_connector_state * state)2140 static int anx7625_connector_atomic_check(struct anx7625_data *ctx,
2141 struct drm_connector_state *state)
2142 {
2143 struct device *dev = ctx->dev;
2144 int cp;
2145
2146 dev_dbg(dev, "hdcp state check\n");
2147 cp = state->content_protection;
2148
2149 if (cp == ctx->hdcp_cp)
2150 return 0;
2151
2152 if (cp == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
2153 if (ctx->dp_en) {
2154 dev_dbg(dev, "enable HDCP\n");
2155 anx7625_hdcp_enable(ctx);
2156
2157 queue_delayed_work(ctx->hdcp_workqueue,
2158 &ctx->hdcp_work,
2159 msecs_to_jiffies(2000));
2160 }
2161 }
2162
2163 if (cp == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
2164 if (ctx->hdcp_cp != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
2165 dev_err(dev, "current CP is not ENABLED\n");
2166 return -EINVAL;
2167 }
2168 anx7625_hdcp_disable(ctx);
2169 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
2170 drm_hdcp_update_content_protection(ctx->connector,
2171 ctx->hdcp_cp);
2172 dev_dbg(dev, "update CP to UNDESIRE\n");
2173 }
2174
2175 if (cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
2176 dev_err(dev, "Userspace illegal set to PROTECTION ENABLE\n");
2177 return -EINVAL;
2178 }
2179
2180 return 0;
2181 }
2182
anx7625_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)2183 static int anx7625_bridge_attach(struct drm_bridge *bridge,
2184 enum drm_bridge_attach_flags flags)
2185 {
2186 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2187 int err;
2188 struct device *dev = ctx->dev;
2189
2190 DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n");
2191 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
2192 return -EINVAL;
2193
2194 ctx->aux.drm_dev = bridge->dev;
2195 err = drm_dp_aux_register(&ctx->aux);
2196 if (err) {
2197 dev_err(dev, "failed to register aux channel: %d\n", err);
2198 return err;
2199 }
2200
2201 if (ctx->pdata.panel_bridge) {
2202 err = drm_bridge_attach(bridge->encoder,
2203 ctx->pdata.panel_bridge,
2204 &ctx->bridge, flags);
2205 if (err)
2206 return err;
2207 }
2208
2209 ctx->bridge_attached = 1;
2210
2211 return 0;
2212 }
2213
anx7625_bridge_detach(struct drm_bridge * bridge)2214 static void anx7625_bridge_detach(struct drm_bridge *bridge)
2215 {
2216 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2217
2218 drm_dp_aux_unregister(&ctx->aux);
2219 }
2220
2221 static enum drm_mode_status
anx7625_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)2222 anx7625_bridge_mode_valid(struct drm_bridge *bridge,
2223 const struct drm_display_info *info,
2224 const struct drm_display_mode *mode)
2225 {
2226 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2227 struct device *dev = ctx->dev;
2228
2229 DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n");
2230
2231 /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */
2232 if (mode->clock > SUPPORT_PIXEL_CLOCK) {
2233 DRM_DEV_DEBUG_DRIVER(dev,
2234 "drm mode invalid, pixelclock too high.\n");
2235 return MODE_CLOCK_HIGH;
2236 }
2237
2238 DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n");
2239
2240 return MODE_OK;
2241 }
2242
anx7625_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * old_mode,const struct drm_display_mode * mode)2243 static void anx7625_bridge_mode_set(struct drm_bridge *bridge,
2244 const struct drm_display_mode *old_mode,
2245 const struct drm_display_mode *mode)
2246 {
2247 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2248 struct device *dev = ctx->dev;
2249
2250 DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n");
2251
2252 ctx->dt.pixelclock.min = mode->clock;
2253 ctx->dt.hactive.min = mode->hdisplay;
2254 ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start;
2255 ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay;
2256 ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end;
2257 ctx->dt.vactive.min = mode->vdisplay;
2258 ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start;
2259 ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay;
2260 ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end;
2261
2262 ctx->display_timing_valid = 1;
2263
2264 DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min);
2265 DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n",
2266 ctx->dt.hactive.min,
2267 ctx->dt.hsync_len.min,
2268 ctx->dt.hfront_porch.min,
2269 ctx->dt.hback_porch.min);
2270 DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n",
2271 ctx->dt.vactive.min,
2272 ctx->dt.vsync_len.min,
2273 ctx->dt.vfront_porch.min,
2274 ctx->dt.vback_porch.min);
2275 DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n",
2276 mode->hdisplay,
2277 mode->hsync_start);
2278 DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n",
2279 mode->hsync_end,
2280 mode->htotal);
2281 DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n",
2282 mode->vdisplay,
2283 mode->vsync_start);
2284 DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n",
2285 mode->vsync_end,
2286 mode->vtotal);
2287 }
2288
anx7625_bridge_mode_fixup(struct drm_bridge * bridge,const struct drm_display_mode * mode,struct drm_display_mode * adj)2289 static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge,
2290 const struct drm_display_mode *mode,
2291 struct drm_display_mode *adj)
2292 {
2293 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2294 struct device *dev = ctx->dev;
2295 u32 hsync, hfp, hbp, hblanking;
2296 u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj;
2297 u32 vref, adj_clock;
2298
2299 DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n");
2300
2301 /* No need fixup for external monitor */
2302 if (!ctx->pdata.panel_bridge)
2303 return true;
2304
2305 hsync = mode->hsync_end - mode->hsync_start;
2306 hfp = mode->hsync_start - mode->hdisplay;
2307 hbp = mode->htotal - mode->hsync_end;
2308 hblanking = mode->htotal - mode->hdisplay;
2309
2310 DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n");
2311 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n",
2312 hsync, hfp, hbp, adj->clock);
2313 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n",
2314 adj->hsync_start, adj->hsync_end, adj->htotal);
2315
2316 adj_hfp = hfp;
2317 adj_hsync = hsync;
2318 adj_hbp = hbp;
2319 adj_hblanking = hblanking;
2320
2321 /* HFP needs to be even */
2322 if (hfp & 0x1) {
2323 adj_hfp += 1;
2324 adj_hblanking += 1;
2325 }
2326
2327 /* HBP needs to be even */
2328 if (hbp & 0x1) {
2329 adj_hbp -= 1;
2330 adj_hblanking -= 1;
2331 }
2332
2333 /* HSYNC needs to be even */
2334 if (hsync & 0x1) {
2335 if (adj_hblanking < hblanking)
2336 adj_hsync += 1;
2337 else
2338 adj_hsync -= 1;
2339 }
2340
2341 /*
2342 * Once illegal timing detected, use default HFP, HSYNC, HBP
2343 * This adjusting made for built-in eDP panel, for the externel
2344 * DP monitor, may need return false.
2345 */
2346 if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) {
2347 adj_hsync = SYNC_LEN_DEF;
2348 adj_hfp = HFP_HBP_DEF;
2349 adj_hbp = HFP_HBP_DEF;
2350 vref = adj->clock * 1000 / (adj->htotal * adj->vtotal);
2351 if (hblanking < HBLANKING_MIN) {
2352 delta_adj = HBLANKING_MIN - hblanking;
2353 adj_clock = vref * delta_adj * adj->vtotal;
2354 adj->clock += DIV_ROUND_UP(adj_clock, 1000);
2355 } else {
2356 delta_adj = hblanking - HBLANKING_MIN;
2357 adj_clock = vref * delta_adj * adj->vtotal;
2358 adj->clock -= DIV_ROUND_UP(adj_clock, 1000);
2359 }
2360
2361 DRM_WARN("illegal hblanking timing, use default.\n");
2362 DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync);
2363 } else if (adj_hfp < HP_MIN) {
2364 /* Adjust hfp if hfp less than HP_MIN */
2365 delta_adj = HP_MIN - adj_hfp;
2366 adj_hfp = HP_MIN;
2367
2368 /*
2369 * Balance total HBlanking pixel, if HBP does not have enough
2370 * space, adjust HSYNC length, otherwise adjust HBP
2371 */
2372 if ((adj_hbp - delta_adj) < HP_MIN)
2373 /* HBP not enough space */
2374 adj_hsync -= delta_adj;
2375 else
2376 adj_hbp -= delta_adj;
2377 } else if (adj_hbp < HP_MIN) {
2378 delta_adj = HP_MIN - adj_hbp;
2379 adj_hbp = HP_MIN;
2380
2381 /*
2382 * Balance total HBlanking pixel, if HBP hasn't enough space,
2383 * adjust HSYNC length, otherwize adjust HBP
2384 */
2385 if ((adj_hfp - delta_adj) < HP_MIN)
2386 /* HFP not enough space */
2387 adj_hsync -= delta_adj;
2388 else
2389 adj_hfp -= delta_adj;
2390 }
2391
2392 DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n");
2393 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n",
2394 adj_hsync, adj_hfp, adj_hbp, adj->clock);
2395
2396 /* Reconstruct timing */
2397 adj->hsync_start = adj->hdisplay + adj_hfp;
2398 adj->hsync_end = adj->hsync_start + adj_hsync;
2399 adj->htotal = adj->hsync_end + adj_hbp;
2400 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n",
2401 adj->hsync_start, adj->hsync_end, adj->htotal);
2402
2403 return true;
2404 }
2405
anx7625_bridge_atomic_check(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)2406 static int anx7625_bridge_atomic_check(struct drm_bridge *bridge,
2407 struct drm_bridge_state *bridge_state,
2408 struct drm_crtc_state *crtc_state,
2409 struct drm_connector_state *conn_state)
2410 {
2411 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2412 struct device *dev = ctx->dev;
2413
2414 dev_dbg(dev, "drm bridge atomic check\n");
2415
2416 anx7625_bridge_mode_fixup(bridge, &crtc_state->mode,
2417 &crtc_state->adjusted_mode);
2418
2419 return anx7625_connector_atomic_check(ctx, conn_state);
2420 }
2421
anx7625_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * state)2422 static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge,
2423 struct drm_bridge_state *state)
2424 {
2425 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2426 struct device *dev = ctx->dev;
2427 struct drm_connector *connector;
2428
2429 dev_dbg(dev, "drm atomic enable\n");
2430
2431 connector = drm_atomic_get_new_connector_for_encoder(state->base.state,
2432 bridge->encoder);
2433 if (!connector)
2434 return;
2435
2436 ctx->connector = connector;
2437
2438 pm_runtime_get_sync(dev);
2439 _anx7625_hpd_polling(ctx, 5000 * 100);
2440
2441 anx7625_dp_start(ctx);
2442 }
2443
anx7625_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_bridge_state * old)2444 static void anx7625_bridge_atomic_disable(struct drm_bridge *bridge,
2445 struct drm_bridge_state *old)
2446 {
2447 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2448 struct device *dev = ctx->dev;
2449
2450 dev_dbg(dev, "drm atomic disable\n");
2451
2452 ctx->connector = NULL;
2453 anx7625_dp_stop(ctx);
2454
2455 mutex_lock(&ctx->aux_lock);
2456 pm_runtime_put_sync_suspend(dev);
2457 mutex_unlock(&ctx->aux_lock);
2458 }
2459
2460 static void
2461 anx7625_audio_update_connector_status(struct anx7625_data *ctx,
2462 enum drm_connector_status status);
2463
2464 static enum drm_connector_status
anx7625_bridge_detect(struct drm_bridge * bridge)2465 anx7625_bridge_detect(struct drm_bridge *bridge)
2466 {
2467 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2468 struct device *dev = ctx->dev;
2469 enum drm_connector_status status;
2470
2471 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n");
2472
2473 status = anx7625_sink_detect(ctx);
2474 anx7625_audio_update_connector_status(ctx, status);
2475 return status;
2476 }
2477
anx7625_bridge_edid_read(struct drm_bridge * bridge,struct drm_connector * connector)2478 static const struct drm_edid *anx7625_bridge_edid_read(struct drm_bridge *bridge,
2479 struct drm_connector *connector)
2480 {
2481 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2482 struct device *dev = ctx->dev;
2483
2484 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n");
2485
2486 return anx7625_edid_read(ctx);
2487 }
2488
2489 static const struct drm_bridge_funcs anx7625_bridge_funcs = {
2490 .attach = anx7625_bridge_attach,
2491 .detach = anx7625_bridge_detach,
2492 .mode_valid = anx7625_bridge_mode_valid,
2493 .mode_set = anx7625_bridge_mode_set,
2494 .atomic_check = anx7625_bridge_atomic_check,
2495 .atomic_enable = anx7625_bridge_atomic_enable,
2496 .atomic_disable = anx7625_bridge_atomic_disable,
2497 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
2498 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
2499 .atomic_reset = drm_atomic_helper_bridge_reset,
2500 .detect = anx7625_bridge_detect,
2501 .edid_read = anx7625_bridge_edid_read,
2502 };
2503
anx7625_register_i2c_dummy_clients(struct anx7625_data * ctx,struct i2c_client * client)2504 static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx,
2505 struct i2c_client *client)
2506 {
2507 struct device *dev = ctx->dev;
2508
2509 ctx->i2c.tx_p0_client = devm_i2c_new_dummy_device(dev, client->adapter,
2510 TX_P0_ADDR >> 1);
2511 if (IS_ERR(ctx->i2c.tx_p0_client))
2512 return PTR_ERR(ctx->i2c.tx_p0_client);
2513
2514 ctx->i2c.tx_p1_client = devm_i2c_new_dummy_device(dev, client->adapter,
2515 TX_P1_ADDR >> 1);
2516 if (IS_ERR(ctx->i2c.tx_p1_client))
2517 return PTR_ERR(ctx->i2c.tx_p1_client);
2518
2519 ctx->i2c.tx_p2_client = devm_i2c_new_dummy_device(dev, client->adapter,
2520 TX_P2_ADDR >> 1);
2521 if (IS_ERR(ctx->i2c.tx_p2_client))
2522 return PTR_ERR(ctx->i2c.tx_p2_client);
2523
2524 ctx->i2c.rx_p0_client = devm_i2c_new_dummy_device(dev, client->adapter,
2525 RX_P0_ADDR >> 1);
2526 if (IS_ERR(ctx->i2c.rx_p0_client))
2527 return PTR_ERR(ctx->i2c.rx_p0_client);
2528
2529 ctx->i2c.rx_p1_client = devm_i2c_new_dummy_device(dev, client->adapter,
2530 RX_P1_ADDR >> 1);
2531 if (IS_ERR(ctx->i2c.rx_p1_client))
2532 return PTR_ERR(ctx->i2c.rx_p1_client);
2533
2534 ctx->i2c.rx_p2_client = devm_i2c_new_dummy_device(dev, client->adapter,
2535 RX_P2_ADDR >> 1);
2536 if (IS_ERR(ctx->i2c.rx_p2_client))
2537 return PTR_ERR(ctx->i2c.rx_p2_client);
2538
2539 ctx->i2c.tcpc_client = devm_i2c_new_dummy_device(dev, client->adapter,
2540 TCPC_INTERFACE_ADDR >> 1);
2541 if (IS_ERR(ctx->i2c.tcpc_client))
2542 return PTR_ERR(ctx->i2c.tcpc_client);
2543
2544 return 0;
2545 }
2546
anx7625_runtime_pm_suspend(struct device * dev)2547 static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev)
2548 {
2549 struct anx7625_data *ctx = dev_get_drvdata(dev);
2550
2551 mutex_lock(&ctx->lock);
2552
2553 anx7625_stop_dp_work(ctx);
2554 anx7625_power_standby(ctx);
2555
2556 mutex_unlock(&ctx->lock);
2557
2558 return 0;
2559 }
2560
anx7625_runtime_pm_resume(struct device * dev)2561 static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev)
2562 {
2563 struct anx7625_data *ctx = dev_get_drvdata(dev);
2564
2565 mutex_lock(&ctx->lock);
2566
2567 anx7625_power_on_init(ctx);
2568
2569 mutex_unlock(&ctx->lock);
2570
2571 return 0;
2572 }
2573
2574 static const struct dev_pm_ops anx7625_pm_ops = {
2575 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2576 pm_runtime_force_resume)
2577 SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend,
2578 anx7625_runtime_pm_resume, NULL)
2579 };
2580
anx7625_runtime_disable(void * data)2581 static void anx7625_runtime_disable(void *data)
2582 {
2583 pm_runtime_dont_use_autosuspend(data);
2584 pm_runtime_disable(data);
2585 }
2586
anx7625_link_bridge(struct drm_dp_aux * aux)2587 static int anx7625_link_bridge(struct drm_dp_aux *aux)
2588 {
2589 struct anx7625_data *platform = container_of(aux, struct anx7625_data, aux);
2590 struct device *dev = aux->dev;
2591 int ret;
2592
2593 ret = anx7625_parse_dt_panel(dev, &platform->pdata);
2594 if (ret) {
2595 DRM_DEV_ERROR(dev, "fail to parse DT for panel : %d\n", ret);
2596 return ret;
2597 }
2598
2599 platform->bridge.funcs = &anx7625_bridge_funcs;
2600 platform->bridge.of_node = dev->of_node;
2601 if (!anx7625_of_panel_on_aux_bus(dev))
2602 platform->bridge.ops |= DRM_BRIDGE_OP_EDID;
2603 if (!platform->pdata.panel_bridge)
2604 platform->bridge.ops |= DRM_BRIDGE_OP_HPD |
2605 DRM_BRIDGE_OP_DETECT;
2606 platform->bridge.type = platform->pdata.panel_bridge ?
2607 DRM_MODE_CONNECTOR_eDP :
2608 DRM_MODE_CONNECTOR_DisplayPort;
2609
2610 drm_bridge_add(&platform->bridge);
2611
2612 if (!platform->pdata.is_dpi) {
2613 ret = anx7625_attach_dsi(platform);
2614 if (ret)
2615 drm_bridge_remove(&platform->bridge);
2616 }
2617
2618 return ret;
2619 }
2620
anx7625_i2c_probe(struct i2c_client * client)2621 static int anx7625_i2c_probe(struct i2c_client *client)
2622 {
2623 struct anx7625_data *platform;
2624 struct anx7625_platform_data *pdata;
2625 int ret = 0;
2626 struct device *dev = &client->dev;
2627
2628 if (!i2c_check_functionality(client->adapter,
2629 I2C_FUNC_SMBUS_I2C_BLOCK)) {
2630 DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n");
2631 return -ENODEV;
2632 }
2633
2634 platform = devm_kzalloc(dev, sizeof(*platform), GFP_KERNEL);
2635 if (!platform) {
2636 DRM_DEV_ERROR(dev, "fail to allocate driver data\n");
2637 return -ENOMEM;
2638 }
2639
2640 pdata = &platform->pdata;
2641
2642 platform->dev = &client->dev;
2643 i2c_set_clientdata(client, platform);
2644
2645 pdata->supplies[0].supply = "vdd10";
2646 pdata->supplies[1].supply = "vdd18";
2647 pdata->supplies[2].supply = "vdd33";
2648 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies),
2649 pdata->supplies);
2650 if (ret) {
2651 DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret);
2652 return ret;
2653 }
2654 anx7625_init_gpio(platform);
2655
2656 mutex_init(&platform->lock);
2657 mutex_init(&platform->hdcp_wq_lock);
2658 mutex_init(&platform->aux_lock);
2659
2660 INIT_DELAYED_WORK(&platform->hdcp_work, hdcp_check_work_func);
2661 platform->hdcp_workqueue = create_workqueue("hdcp workqueue");
2662 if (!platform->hdcp_workqueue) {
2663 dev_err(dev, "fail to create work queue\n");
2664 ret = -ENOMEM;
2665 return ret;
2666 }
2667
2668 platform->pdata.intp_irq = client->irq;
2669 if (platform->pdata.intp_irq) {
2670 INIT_WORK(&platform->work, anx7625_work_func);
2671 platform->workqueue = alloc_workqueue("anx7625_work",
2672 WQ_FREEZABLE | WQ_MEM_RECLAIM, 1);
2673 if (!platform->workqueue) {
2674 DRM_DEV_ERROR(dev, "fail to create work queue\n");
2675 ret = -ENOMEM;
2676 goto free_hdcp_wq;
2677 }
2678
2679 ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq,
2680 NULL, anx7625_intr_hpd_isr,
2681 IRQF_TRIGGER_FALLING |
2682 IRQF_ONESHOT,
2683 "anx7625-intp", platform);
2684 if (ret) {
2685 DRM_DEV_ERROR(dev, "fail to request irq\n");
2686 goto free_wq;
2687 }
2688 }
2689
2690 platform->aux.name = "anx7625-aux";
2691 platform->aux.dev = dev;
2692 platform->aux.transfer = anx7625_aux_transfer;
2693 platform->aux.wait_hpd_asserted = anx7625_wait_hpd_asserted;
2694 drm_dp_aux_init(&platform->aux);
2695
2696 ret = anx7625_parse_dt(dev, pdata);
2697 if (ret) {
2698 if (ret != -EPROBE_DEFER)
2699 DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret);
2700 goto free_wq;
2701 }
2702
2703 if (!platform->pdata.is_dpi) {
2704 ret = anx7625_setup_dsi_device(platform);
2705 if (ret < 0)
2706 goto free_wq;
2707 }
2708
2709 /*
2710 * Registering the i2c devices will retrigger deferred probe, so it
2711 * needs to be done after calls that might return EPROBE_DEFER,
2712 * otherwise we can get an infinite loop.
2713 */
2714 if (anx7625_register_i2c_dummy_clients(platform, client) != 0) {
2715 ret = -ENOMEM;
2716 DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n");
2717 goto free_wq;
2718 }
2719
2720 pm_runtime_enable(dev);
2721 pm_runtime_set_autosuspend_delay(dev, 1000);
2722 pm_runtime_use_autosuspend(dev);
2723 pm_suspend_ignore_children(dev, true);
2724 ret = devm_add_action_or_reset(dev, anx7625_runtime_disable, dev);
2725 if (ret)
2726 goto free_wq;
2727
2728 /*
2729 * Populating the aux bus will retrigger deferred probe, so it needs to
2730 * be done after calls that might return EPROBE_DEFER, otherwise we can
2731 * get an infinite loop.
2732 */
2733 ret = devm_of_dp_aux_populate_bus(&platform->aux, anx7625_link_bridge);
2734 if (ret) {
2735 if (ret != -ENODEV) {
2736 DRM_DEV_ERROR(dev, "failed to populate aux bus : %d\n", ret);
2737 goto free_wq;
2738 }
2739
2740 ret = anx7625_link_bridge(&platform->aux);
2741 if (ret)
2742 goto free_wq;
2743 }
2744
2745 if (!platform->pdata.low_power_mode) {
2746 anx7625_disable_pd_protocol(platform);
2747 pm_runtime_get_sync(dev);
2748 _anx7625_hpd_polling(platform, 5000 * 100);
2749 }
2750
2751 /* Add work function */
2752 if (platform->pdata.intp_irq)
2753 queue_work(platform->workqueue, &platform->work);
2754
2755 if (platform->pdata.audio_en)
2756 anx7625_register_audio(dev, platform);
2757
2758 DRM_DEV_DEBUG_DRIVER(dev, "probe done\n");
2759
2760 return 0;
2761
2762 free_wq:
2763 if (platform->workqueue)
2764 destroy_workqueue(platform->workqueue);
2765
2766 free_hdcp_wq:
2767 if (platform->hdcp_workqueue)
2768 destroy_workqueue(platform->hdcp_workqueue);
2769
2770 return ret;
2771 }
2772
anx7625_i2c_remove(struct i2c_client * client)2773 static void anx7625_i2c_remove(struct i2c_client *client)
2774 {
2775 struct anx7625_data *platform = i2c_get_clientdata(client);
2776
2777 drm_bridge_remove(&platform->bridge);
2778
2779 if (platform->pdata.intp_irq)
2780 destroy_workqueue(platform->workqueue);
2781
2782 if (platform->hdcp_workqueue) {
2783 cancel_delayed_work(&platform->hdcp_work);
2784 flush_workqueue(platform->hdcp_workqueue);
2785 destroy_workqueue(platform->hdcp_workqueue);
2786 }
2787
2788 if (!platform->pdata.low_power_mode)
2789 pm_runtime_put_sync_suspend(&client->dev);
2790
2791 if (platform->pdata.audio_en)
2792 anx7625_unregister_audio(platform);
2793 }
2794
2795 static const struct i2c_device_id anx7625_id[] = {
2796 {"anx7625", 0},
2797 {}
2798 };
2799
2800 MODULE_DEVICE_TABLE(i2c, anx7625_id);
2801
2802 static const struct of_device_id anx_match_table[] = {
2803 {.compatible = "analogix,anx7625",},
2804 {},
2805 };
2806 MODULE_DEVICE_TABLE(of, anx_match_table);
2807
2808 static struct i2c_driver anx7625_driver = {
2809 .driver = {
2810 .name = "anx7625",
2811 .of_match_table = anx_match_table,
2812 .pm = &anx7625_pm_ops,
2813 },
2814 .probe = anx7625_i2c_probe,
2815 .remove = anx7625_i2c_remove,
2816
2817 .id_table = anx7625_id,
2818 };
2819
2820 module_i2c_driver(anx7625_driver);
2821
2822 MODULE_DESCRIPTION("MIPI2DP anx7625 driver");
2823 MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>");
2824 MODULE_LICENSE("GPL v2");
2825 MODULE_VERSION(ANX7625_DRV_VERSION);
2826