1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
4 */
5 #ifndef _ASM_INST_H
6 #define _ASM_INST_H
7
8 #include <linux/bitops.h>
9 #include <linux/types.h>
10 #include <asm/asm.h>
11 #include <asm/ptrace.h>
12
13 #define INSN_NOP 0x03400000
14 #define INSN_BREAK 0x002a0000
15 #define INSN_HVCL 0x002b8000
16
17 #define ADDR_IMMMASK_LU52ID 0xFFF0000000000000
18 #define ADDR_IMMMASK_LU32ID 0x000FFFFF00000000
19 #define ADDR_IMMMASK_LU12IW 0x00000000FFFFF000
20 #define ADDR_IMMMASK_ORI 0x0000000000000FFF
21 #define ADDR_IMMMASK_ADDU16ID 0x00000000FFFF0000
22
23 #define ADDR_IMMSHIFT_LU52ID 52
24 #define ADDR_IMMSBIDX_LU52ID 11
25 #define ADDR_IMMSHIFT_LU32ID 32
26 #define ADDR_IMMSBIDX_LU32ID 19
27 #define ADDR_IMMSHIFT_LU12IW 12
28 #define ADDR_IMMSBIDX_LU12IW 19
29 #define ADDR_IMMSHIFT_ORI 0
30 #define ADDR_IMMSBIDX_ORI 63
31 #define ADDR_IMMSHIFT_ADDU16ID 16
32 #define ADDR_IMMSBIDX_ADDU16ID 15
33
34 #define ADDR_IMM(addr, INSN) \
35 (sign_extend64(((addr & ADDR_IMMMASK_##INSN) >> ADDR_IMMSHIFT_##INSN), ADDR_IMMSBIDX_##INSN))
36
37 enum reg0i15_op {
38 break_op = 0x54,
39 dbar_op = 0x70e4,
40 };
41
42 enum reg0i26_op {
43 b_op = 0x14,
44 bl_op = 0x15,
45 };
46
47 enum reg1i20_op {
48 lu12iw_op = 0x0a,
49 lu32id_op = 0x0b,
50 pcaddi_op = 0x0c,
51 pcalau12i_op = 0x0d,
52 pcaddu12i_op = 0x0e,
53 pcaddu18i_op = 0x0f,
54 };
55
56 enum reg1i21_op {
57 beqz_op = 0x10,
58 bnez_op = 0x11,
59 bceqz_op = 0x12, /* bits[9:8] = 0x00 */
60 bcnez_op = 0x12, /* bits[9:8] = 0x01 */
61 };
62
63 enum reg2_op {
64 revb2h_op = 0x0c,
65 revb4h_op = 0x0d,
66 revb2w_op = 0x0e,
67 revbd_op = 0x0f,
68 revh2w_op = 0x10,
69 revhd_op = 0x11,
70 extwh_op = 0x16,
71 extwb_op = 0x17,
72 cpucfg_op = 0x1b,
73 iocsrrdb_op = 0x19200,
74 iocsrrdh_op = 0x19201,
75 iocsrrdw_op = 0x19202,
76 iocsrrdd_op = 0x19203,
77 iocsrwrb_op = 0x19204,
78 iocsrwrh_op = 0x19205,
79 iocsrwrw_op = 0x19206,
80 iocsrwrd_op = 0x19207,
81 llacqw_op = 0xe15e0,
82 screlw_op = 0xe15e1,
83 llacqd_op = 0xe15e2,
84 screld_op = 0xe15e3,
85 };
86
87 enum reg2i5_op {
88 slliw_op = 0x81,
89 srliw_op = 0x89,
90 sraiw_op = 0x91,
91 };
92
93 enum reg2i6_op {
94 sllid_op = 0x41,
95 srlid_op = 0x45,
96 sraid_op = 0x49,
97 };
98
99 enum reg2i12_op {
100 addiw_op = 0x0a,
101 addid_op = 0x0b,
102 lu52id_op = 0x0c,
103 andi_op = 0x0d,
104 ori_op = 0x0e,
105 xori_op = 0x0f,
106 ldb_op = 0xa0,
107 ldh_op = 0xa1,
108 ldw_op = 0xa2,
109 ldd_op = 0xa3,
110 stb_op = 0xa4,
111 sth_op = 0xa5,
112 stw_op = 0xa6,
113 std_op = 0xa7,
114 ldbu_op = 0xa8,
115 ldhu_op = 0xa9,
116 ldwu_op = 0xaa,
117 flds_op = 0xac,
118 fsts_op = 0xad,
119 fldd_op = 0xae,
120 fstd_op = 0xaf,
121 };
122
123 enum reg2i14_op {
124 llw_op = 0x20,
125 scw_op = 0x21,
126 lld_op = 0x22,
127 scd_op = 0x23,
128 ldptrw_op = 0x24,
129 stptrw_op = 0x25,
130 ldptrd_op = 0x26,
131 stptrd_op = 0x27,
132 };
133
134 enum reg2i16_op {
135 jirl_op = 0x13,
136 beq_op = 0x16,
137 bne_op = 0x17,
138 blt_op = 0x18,
139 bge_op = 0x19,
140 bltu_op = 0x1a,
141 bgeu_op = 0x1b,
142 };
143
144 enum reg2bstrd_op {
145 bstrinsd_op = 0x2,
146 bstrpickd_op = 0x3,
147 };
148
149 enum reg3_op {
150 asrtle_op = 0x02,
151 asrtgt_op = 0x03,
152 addw_op = 0x20,
153 addd_op = 0x21,
154 subw_op = 0x22,
155 subd_op = 0x23,
156 nor_op = 0x28,
157 and_op = 0x29,
158 or_op = 0x2a,
159 xor_op = 0x2b,
160 orn_op = 0x2c,
161 andn_op = 0x2d,
162 sllw_op = 0x2e,
163 srlw_op = 0x2f,
164 sraw_op = 0x30,
165 slld_op = 0x31,
166 srld_op = 0x32,
167 srad_op = 0x33,
168 mulw_op = 0x38,
169 mulhw_op = 0x39,
170 mulhwu_op = 0x3a,
171 muld_op = 0x3b,
172 mulhd_op = 0x3c,
173 mulhdu_op = 0x3d,
174 divw_op = 0x40,
175 modw_op = 0x41,
176 divwu_op = 0x42,
177 modwu_op = 0x43,
178 divd_op = 0x44,
179 modd_op = 0x45,
180 divdu_op = 0x46,
181 moddu_op = 0x47,
182 ldxb_op = 0x7000,
183 ldxh_op = 0x7008,
184 ldxw_op = 0x7010,
185 ldxd_op = 0x7018,
186 stxb_op = 0x7020,
187 stxh_op = 0x7028,
188 stxw_op = 0x7030,
189 stxd_op = 0x7038,
190 ldxbu_op = 0x7040,
191 ldxhu_op = 0x7048,
192 ldxwu_op = 0x7050,
193 fldxs_op = 0x7060,
194 fldxd_op = 0x7068,
195 fstxs_op = 0x7070,
196 fstxd_op = 0x7078,
197 scq_op = 0x70ae,
198 amswapb_op = 0x70b8,
199 amswaph_op = 0x70b9,
200 amaddb_op = 0x70ba,
201 amaddh_op = 0x70bb,
202 amswapw_op = 0x70c0,
203 amswapd_op = 0x70c1,
204 amaddw_op = 0x70c2,
205 amaddd_op = 0x70c3,
206 amandw_op = 0x70c4,
207 amandd_op = 0x70c5,
208 amorw_op = 0x70c6,
209 amord_op = 0x70c7,
210 amxorw_op = 0x70c8,
211 amxord_op = 0x70c9,
212 ammaxw_op = 0x70ca,
213 ammaxd_op = 0x70cb,
214 amminw_op = 0x70cc,
215 ammind_op = 0x70cd,
216 ammaxwu_op = 0x70ce,
217 ammaxdu_op = 0x70cf,
218 amminwu_op = 0x70d0,
219 ammindu_op = 0x70d1,
220 amswapdbw_op = 0x70d2,
221 amswapdbd_op = 0x70d3,
222 amadddbw_op = 0x70d4,
223 amadddbd_op = 0x70d5,
224 amanddbw_op = 0x70d6,
225 amanddbd_op = 0x70d7,
226 amordbw_op = 0x70d8,
227 amordbd_op = 0x70d9,
228 amxordbw_op = 0x70da,
229 amxordbd_op = 0x70db,
230 ammaxdbw_op = 0x70dc,
231 ammaxdbd_op = 0x70dd,
232 ammindbw_op = 0x70de,
233 ammindbd_op = 0x70df,
234 ammaxdbwu_op = 0x70e0,
235 ammaxdbdu_op = 0x70e1,
236 ammindbwu_op = 0x70e2,
237 ammindbdu_op = 0x70e3,
238 fldgts_op = 0x70e8,
239 fldgtd_op = 0x70e9,
240 fldles_op = 0x70ea,
241 fldled_op = 0x70eb,
242 fstgts_op = 0x70ec,
243 fstgtd_op = 0x70ed,
244 fstles_op = 0x70ee,
245 fstled_op = 0x70ef,
246 ldgtb_op = 0x70f0,
247 ldgth_op = 0x70f1,
248 ldgtw_op = 0x70f2,
249 ldgtd_op = 0x70f3,
250 ldleb_op = 0x70f4,
251 ldleh_op = 0x70f5,
252 ldlew_op = 0x70f6,
253 ldled_op = 0x70f7,
254 stgtb_op = 0x70f8,
255 stgth_op = 0x70f9,
256 stgtw_op = 0x70fa,
257 stgtd_op = 0x70fb,
258 stleb_op = 0x70fc,
259 stleh_op = 0x70fd,
260 stlew_op = 0x70fe,
261 stled_op = 0x70ff,
262 };
263
264 enum reg3sa2_op {
265 alslw_op = 0x02,
266 alslwu_op = 0x03,
267 alsld_op = 0x16,
268 };
269
270 struct reg0i15_format {
271 unsigned int immediate : 15;
272 unsigned int opcode : 17;
273 };
274
275 struct reg0i26_format {
276 unsigned int immediate_h : 10;
277 unsigned int immediate_l : 16;
278 unsigned int opcode : 6;
279 };
280
281 struct reg1i20_format {
282 unsigned int rd : 5;
283 unsigned int immediate : 20;
284 unsigned int opcode : 7;
285 };
286
287 struct reg1i21_format {
288 unsigned int immediate_h : 5;
289 unsigned int rj : 5;
290 unsigned int immediate_l : 16;
291 unsigned int opcode : 6;
292 };
293
294 struct reg2_format {
295 unsigned int rd : 5;
296 unsigned int rj : 5;
297 unsigned int opcode : 22;
298 };
299
300 struct reg2i5_format {
301 unsigned int rd : 5;
302 unsigned int rj : 5;
303 unsigned int immediate : 5;
304 unsigned int opcode : 17;
305 };
306
307 struct reg2i6_format {
308 unsigned int rd : 5;
309 unsigned int rj : 5;
310 unsigned int immediate : 6;
311 unsigned int opcode : 16;
312 };
313
314 struct reg2i12_format {
315 unsigned int rd : 5;
316 unsigned int rj : 5;
317 unsigned int immediate : 12;
318 unsigned int opcode : 10;
319 };
320
321 struct reg2i14_format {
322 unsigned int rd : 5;
323 unsigned int rj : 5;
324 unsigned int immediate : 14;
325 unsigned int opcode : 8;
326 };
327
328 struct reg2i16_format {
329 unsigned int rd : 5;
330 unsigned int rj : 5;
331 unsigned int immediate : 16;
332 unsigned int opcode : 6;
333 };
334
335 struct reg2bstrd_format {
336 unsigned int rd : 5;
337 unsigned int rj : 5;
338 unsigned int lsbd : 6;
339 unsigned int msbd : 6;
340 unsigned int opcode : 10;
341 };
342
343 struct reg2csr_format {
344 unsigned int rd : 5;
345 unsigned int rj : 5;
346 unsigned int csr : 14;
347 unsigned int opcode : 8;
348 };
349
350 struct reg3_format {
351 unsigned int rd : 5;
352 unsigned int rj : 5;
353 unsigned int rk : 5;
354 unsigned int opcode : 17;
355 };
356
357 struct reg3sa2_format {
358 unsigned int rd : 5;
359 unsigned int rj : 5;
360 unsigned int rk : 5;
361 unsigned int immediate : 2;
362 unsigned int opcode : 15;
363 };
364
365 union loongarch_instruction {
366 unsigned int word;
367 struct reg0i15_format reg0i15_format;
368 struct reg0i26_format reg0i26_format;
369 struct reg1i20_format reg1i20_format;
370 struct reg1i21_format reg1i21_format;
371 struct reg2_format reg2_format;
372 struct reg2i5_format reg2i5_format;
373 struct reg2i6_format reg2i6_format;
374 struct reg2i12_format reg2i12_format;
375 struct reg2i14_format reg2i14_format;
376 struct reg2i16_format reg2i16_format;
377 struct reg2bstrd_format reg2bstrd_format;
378 struct reg2csr_format reg2csr_format;
379 struct reg3_format reg3_format;
380 struct reg3sa2_format reg3sa2_format;
381 };
382
383 #define LOONGARCH_INSN_SIZE sizeof(union loongarch_instruction)
384
385 enum loongarch_gpr {
386 LOONGARCH_GPR_ZERO = 0,
387 LOONGARCH_GPR_RA = 1,
388 LOONGARCH_GPR_TP = 2,
389 LOONGARCH_GPR_SP = 3,
390 LOONGARCH_GPR_A0 = 4, /* Reused as V0 for return value */
391 LOONGARCH_GPR_A1, /* Reused as V1 for return value */
392 LOONGARCH_GPR_A2,
393 LOONGARCH_GPR_A3,
394 LOONGARCH_GPR_A4,
395 LOONGARCH_GPR_A5,
396 LOONGARCH_GPR_A6,
397 LOONGARCH_GPR_A7,
398 LOONGARCH_GPR_T0 = 12,
399 LOONGARCH_GPR_T1,
400 LOONGARCH_GPR_T2,
401 LOONGARCH_GPR_T3,
402 LOONGARCH_GPR_T4,
403 LOONGARCH_GPR_T5,
404 LOONGARCH_GPR_T6,
405 LOONGARCH_GPR_T7,
406 LOONGARCH_GPR_T8,
407 LOONGARCH_GPR_FP = 22,
408 LOONGARCH_GPR_S0 = 23,
409 LOONGARCH_GPR_S1,
410 LOONGARCH_GPR_S2,
411 LOONGARCH_GPR_S3,
412 LOONGARCH_GPR_S4,
413 LOONGARCH_GPR_S5,
414 LOONGARCH_GPR_S6,
415 LOONGARCH_GPR_S7,
416 LOONGARCH_GPR_S8,
417 LOONGARCH_GPR_MAX
418 };
419
420 #define is_imm12_negative(val) is_imm_negative(val, 12)
421
is_imm_negative(unsigned long val,unsigned int bit)422 static inline bool is_imm_negative(unsigned long val, unsigned int bit)
423 {
424 return val & (1UL << (bit - 1));
425 }
426
is_break_ins(union loongarch_instruction * ip)427 static inline bool is_break_ins(union loongarch_instruction *ip)
428 {
429 return ip->reg0i15_format.opcode == break_op;
430 }
431
is_pc_ins(union loongarch_instruction * ip)432 static inline bool is_pc_ins(union loongarch_instruction *ip)
433 {
434 return ip->reg1i20_format.opcode >= pcaddi_op &&
435 ip->reg1i20_format.opcode <= pcaddu18i_op;
436 }
437
is_branch_ins(union loongarch_instruction * ip)438 static inline bool is_branch_ins(union loongarch_instruction *ip)
439 {
440 return ip->reg1i21_format.opcode >= beqz_op &&
441 ip->reg1i21_format.opcode <= bgeu_op;
442 }
443
is_ra_save_ins(union loongarch_instruction * ip)444 static inline bool is_ra_save_ins(union loongarch_instruction *ip)
445 {
446 const u32 opcode = IS_ENABLED(CONFIG_32BIT) ? stw_op : std_op;
447
448 /* st.w / st.d $ra, $sp, offset */
449 return ip->reg2i12_format.opcode == opcode &&
450 ip->reg2i12_format.rj == LOONGARCH_GPR_SP &&
451 ip->reg2i12_format.rd == LOONGARCH_GPR_RA &&
452 !is_imm12_negative(ip->reg2i12_format.immediate);
453 }
454
is_stack_alloc_ins(union loongarch_instruction * ip)455 static inline bool is_stack_alloc_ins(union loongarch_instruction *ip)
456 {
457 const u32 opcode = IS_ENABLED(CONFIG_32BIT) ? addiw_op : addid_op;
458
459 /* addi.w / addi.d $sp, $sp, -imm */
460 return ip->reg2i12_format.opcode == opcode &&
461 ip->reg2i12_format.rj == LOONGARCH_GPR_SP &&
462 ip->reg2i12_format.rd == LOONGARCH_GPR_SP &&
463 is_imm12_negative(ip->reg2i12_format.immediate);
464 }
465
is_self_loop_ins(union loongarch_instruction * ip,struct pt_regs * regs)466 static inline bool is_self_loop_ins(union loongarch_instruction *ip, struct pt_regs *regs)
467 {
468 switch (ip->reg0i26_format.opcode) {
469 case b_op:
470 case bl_op:
471 if (ip->reg0i26_format.immediate_l == 0
472 && ip->reg0i26_format.immediate_h == 0)
473 return true;
474 }
475
476 switch (ip->reg1i21_format.opcode) {
477 case beqz_op:
478 case bnez_op:
479 case bceqz_op:
480 if (ip->reg1i21_format.immediate_l == 0
481 && ip->reg1i21_format.immediate_h == 0)
482 return true;
483 }
484
485 switch (ip->reg2i16_format.opcode) {
486 case beq_op:
487 case bne_op:
488 case blt_op:
489 case bge_op:
490 case bltu_op:
491 case bgeu_op:
492 if (ip->reg2i16_format.immediate == 0)
493 return true;
494 break;
495 case jirl_op:
496 if (regs->regs[ip->reg2i16_format.rj] +
497 ((unsigned long)ip->reg2i16_format.immediate << 2) == (unsigned long)ip)
498 return true;
499 }
500
501 return false;
502 }
503
504 void simu_pc(struct pt_regs *regs, union loongarch_instruction insn);
505 void simu_branch(struct pt_regs *regs, union loongarch_instruction insn);
506
507 bool insns_not_supported(union loongarch_instruction insn);
508 bool insns_need_simulation(union loongarch_instruction insn);
509 void arch_simulate_insn(union loongarch_instruction insn, struct pt_regs *regs);
510
511 int larch_insn_read(void *addr, u32 *insnp);
512 int larch_insn_write(void *addr, u32 insn);
513 int larch_insn_patch_text(void *addr, u32 insn);
514 int larch_insn_text_copy(void *dst, void *src, size_t len);
515
516 u32 larch_insn_gen_nop(void);
517 u32 larch_insn_gen_b(unsigned long pc, unsigned long dest);
518 u32 larch_insn_gen_bl(unsigned long pc, unsigned long dest);
519
520 u32 larch_insn_gen_break(int imm);
521
522 u32 larch_insn_gen_or(enum loongarch_gpr rd, enum loongarch_gpr rj, enum loongarch_gpr rk);
523 u32 larch_insn_gen_move(enum loongarch_gpr rd, enum loongarch_gpr rj);
524
525 u32 larch_insn_gen_lu12iw(enum loongarch_gpr rd, int imm);
526 u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm);
527 u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
528 u32 larch_insn_gen_beq(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
529 u32 larch_insn_gen_bne(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
530 u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
531
signed_imm_check(long val,unsigned int bit)532 static inline bool signed_imm_check(long val, unsigned int bit)
533 {
534 return -(1L << (bit - 1)) <= val && val < (1L << (bit - 1));
535 }
536
unsigned_imm_check(unsigned long val,unsigned int bit)537 static inline bool unsigned_imm_check(unsigned long val, unsigned int bit)
538 {
539 return val < (1UL << bit);
540 }
541
542 #define DEF_EMIT_REG0I15_FORMAT(NAME, OP) \
543 static inline void emit_##NAME(union loongarch_instruction *insn, \
544 int imm) \
545 { \
546 insn->reg0i15_format.opcode = OP; \
547 insn->reg0i15_format.immediate = imm; \
548 }
549
DEF_EMIT_REG0I15_FORMAT(break,break_op)550 DEF_EMIT_REG0I15_FORMAT(break, break_op)
551 DEF_EMIT_REG0I15_FORMAT(dbar, dbar_op)
552
553 /* like emit_break(imm) but returns a constant expression */
554 #define __emit_break(imm) ((u32)((imm) | (break_op << 15)))
555
556 #define DEF_EMIT_REG0I26_FORMAT(NAME, OP) \
557 static inline void emit_##NAME(union loongarch_instruction *insn, \
558 int offset) \
559 { \
560 unsigned int immediate_l, immediate_h; \
561 \
562 immediate_l = offset & 0xffff; \
563 offset >>= 16; \
564 immediate_h = offset & 0x3ff; \
565 \
566 insn->reg0i26_format.opcode = OP; \
567 insn->reg0i26_format.immediate_l = immediate_l; \
568 insn->reg0i26_format.immediate_h = immediate_h; \
569 }
570
571 DEF_EMIT_REG0I26_FORMAT(b, b_op)
572 DEF_EMIT_REG0I26_FORMAT(bl, bl_op)
573
574 #define DEF_EMIT_REG1I20_FORMAT(NAME, OP) \
575 static inline void emit_##NAME(union loongarch_instruction *insn, \
576 enum loongarch_gpr rd, int imm) \
577 { \
578 insn->reg1i20_format.opcode = OP; \
579 insn->reg1i20_format.immediate = imm; \
580 insn->reg1i20_format.rd = rd; \
581 }
582
583 DEF_EMIT_REG1I20_FORMAT(lu12iw, lu12iw_op)
584 DEF_EMIT_REG1I20_FORMAT(lu32id, lu32id_op)
585 DEF_EMIT_REG1I20_FORMAT(pcaddu18i, pcaddu18i_op)
586
587 #define DEF_EMIT_REG2_FORMAT(NAME, OP) \
588 static inline void emit_##NAME(union loongarch_instruction *insn, \
589 enum loongarch_gpr rd, \
590 enum loongarch_gpr rj) \
591 { \
592 insn->reg2_format.opcode = OP; \
593 insn->reg2_format.rd = rd; \
594 insn->reg2_format.rj = rj; \
595 }
596
597 DEF_EMIT_REG2_FORMAT(revb2h, revb2h_op)
598 DEF_EMIT_REG2_FORMAT(revb2w, revb2w_op)
599 DEF_EMIT_REG2_FORMAT(revbd, revbd_op)
600 DEF_EMIT_REG2_FORMAT(extwh, extwh_op)
601 DEF_EMIT_REG2_FORMAT(extwb, extwb_op)
602
603 #define DEF_EMIT_REG2I5_FORMAT(NAME, OP) \
604 static inline void emit_##NAME(union loongarch_instruction *insn, \
605 enum loongarch_gpr rd, \
606 enum loongarch_gpr rj, \
607 int imm) \
608 { \
609 insn->reg2i5_format.opcode = OP; \
610 insn->reg2i5_format.immediate = imm; \
611 insn->reg2i5_format.rd = rd; \
612 insn->reg2i5_format.rj = rj; \
613 }
614
615 DEF_EMIT_REG2I5_FORMAT(slliw, slliw_op)
616 DEF_EMIT_REG2I5_FORMAT(srliw, srliw_op)
617 DEF_EMIT_REG2I5_FORMAT(sraiw, sraiw_op)
618
619 #define DEF_EMIT_REG2I6_FORMAT(NAME, OP) \
620 static inline void emit_##NAME(union loongarch_instruction *insn, \
621 enum loongarch_gpr rd, \
622 enum loongarch_gpr rj, \
623 int imm) \
624 { \
625 insn->reg2i6_format.opcode = OP; \
626 insn->reg2i6_format.immediate = imm; \
627 insn->reg2i6_format.rd = rd; \
628 insn->reg2i6_format.rj = rj; \
629 }
630
631 DEF_EMIT_REG2I6_FORMAT(sllid, sllid_op)
632 DEF_EMIT_REG2I6_FORMAT(srlid, srlid_op)
633 DEF_EMIT_REG2I6_FORMAT(sraid, sraid_op)
634
635 #define DEF_EMIT_REG2I12_FORMAT(NAME, OP) \
636 static inline void emit_##NAME(union loongarch_instruction *insn, \
637 enum loongarch_gpr rd, \
638 enum loongarch_gpr rj, \
639 int imm) \
640 { \
641 insn->reg2i12_format.opcode = OP; \
642 insn->reg2i12_format.immediate = imm; \
643 insn->reg2i12_format.rd = rd; \
644 insn->reg2i12_format.rj = rj; \
645 }
646
647 DEF_EMIT_REG2I12_FORMAT(addiw, addiw_op)
648 DEF_EMIT_REG2I12_FORMAT(addid, addid_op)
649 DEF_EMIT_REG2I12_FORMAT(lu52id, lu52id_op)
650 DEF_EMIT_REG2I12_FORMAT(andi, andi_op)
651 DEF_EMIT_REG2I12_FORMAT(ori, ori_op)
652 DEF_EMIT_REG2I12_FORMAT(xori, xori_op)
653 DEF_EMIT_REG2I12_FORMAT(ldb, ldb_op)
654 DEF_EMIT_REG2I12_FORMAT(ldh, ldh_op)
655 DEF_EMIT_REG2I12_FORMAT(ldw, ldw_op)
656 DEF_EMIT_REG2I12_FORMAT(ldbu, ldbu_op)
657 DEF_EMIT_REG2I12_FORMAT(ldhu, ldhu_op)
658 DEF_EMIT_REG2I12_FORMAT(ldwu, ldwu_op)
659 DEF_EMIT_REG2I12_FORMAT(ldd, ldd_op)
660 DEF_EMIT_REG2I12_FORMAT(stb, stb_op)
661 DEF_EMIT_REG2I12_FORMAT(sth, sth_op)
662 DEF_EMIT_REG2I12_FORMAT(stw, stw_op)
663 DEF_EMIT_REG2I12_FORMAT(std, std_op)
664
665 #define DEF_EMIT_REG2I14_FORMAT(NAME, OP) \
666 static inline void emit_##NAME(union loongarch_instruction *insn, \
667 enum loongarch_gpr rd, \
668 enum loongarch_gpr rj, \
669 int imm) \
670 { \
671 insn->reg2i14_format.opcode = OP; \
672 insn->reg2i14_format.immediate = imm; \
673 insn->reg2i14_format.rd = rd; \
674 insn->reg2i14_format.rj = rj; \
675 }
676
677 DEF_EMIT_REG2I14_FORMAT(llw, llw_op)
678 DEF_EMIT_REG2I14_FORMAT(scw, scw_op)
679 DEF_EMIT_REG2I14_FORMAT(lld, lld_op)
680 DEF_EMIT_REG2I14_FORMAT(scd, scd_op)
681 DEF_EMIT_REG2I14_FORMAT(ldptrw, ldptrw_op)
682 DEF_EMIT_REG2I14_FORMAT(stptrw, stptrw_op)
683 DEF_EMIT_REG2I14_FORMAT(ldptrd, ldptrd_op)
684 DEF_EMIT_REG2I14_FORMAT(stptrd, stptrd_op)
685
686 #define DEF_EMIT_REG2I16_FORMAT(NAME, OP) \
687 static inline void emit_##NAME(union loongarch_instruction *insn, \
688 enum loongarch_gpr rj, \
689 enum loongarch_gpr rd, \
690 int offset) \
691 { \
692 insn->reg2i16_format.opcode = OP; \
693 insn->reg2i16_format.immediate = offset; \
694 insn->reg2i16_format.rj = rj; \
695 insn->reg2i16_format.rd = rd; \
696 }
697
698 DEF_EMIT_REG2I16_FORMAT(beq, beq_op)
699 DEF_EMIT_REG2I16_FORMAT(bne, bne_op)
700 DEF_EMIT_REG2I16_FORMAT(blt, blt_op)
701 DEF_EMIT_REG2I16_FORMAT(bge, bge_op)
702 DEF_EMIT_REG2I16_FORMAT(bltu, bltu_op)
703 DEF_EMIT_REG2I16_FORMAT(bgeu, bgeu_op)
704
705 static inline void emit_jirl(union loongarch_instruction *insn,
706 enum loongarch_gpr rd,
707 enum loongarch_gpr rj,
708 int offset)
709 {
710 insn->reg2i16_format.opcode = jirl_op;
711 insn->reg2i16_format.immediate = offset;
712 insn->reg2i16_format.rd = rd;
713 insn->reg2i16_format.rj = rj;
714 }
715
716 #define DEF_EMIT_REG2BSTRD_FORMAT(NAME, OP) \
717 static inline void emit_##NAME(union loongarch_instruction *insn, \
718 enum loongarch_gpr rd, \
719 enum loongarch_gpr rj, \
720 int msbd, \
721 int lsbd) \
722 { \
723 insn->reg2bstrd_format.opcode = OP; \
724 insn->reg2bstrd_format.msbd = msbd; \
725 insn->reg2bstrd_format.lsbd = lsbd; \
726 insn->reg2bstrd_format.rj = rj; \
727 insn->reg2bstrd_format.rd = rd; \
728 }
729
730 DEF_EMIT_REG2BSTRD_FORMAT(bstrpickd, bstrpickd_op)
731
732 #define DEF_EMIT_REG3_FORMAT(NAME, OP) \
733 static inline void emit_##NAME(union loongarch_instruction *insn, \
734 enum loongarch_gpr rd, \
735 enum loongarch_gpr rj, \
736 enum loongarch_gpr rk) \
737 { \
738 insn->reg3_format.opcode = OP; \
739 insn->reg3_format.rd = rd; \
740 insn->reg3_format.rj = rj; \
741 insn->reg3_format.rk = rk; \
742 }
743
744 DEF_EMIT_REG3_FORMAT(addw, addw_op)
745 DEF_EMIT_REG3_FORMAT(addd, addd_op)
746 DEF_EMIT_REG3_FORMAT(subd, subd_op)
747 DEF_EMIT_REG3_FORMAT(muld, muld_op)
748 DEF_EMIT_REG3_FORMAT(divd, divd_op)
749 DEF_EMIT_REG3_FORMAT(modd, modd_op)
750 DEF_EMIT_REG3_FORMAT(divdu, divdu_op)
751 DEF_EMIT_REG3_FORMAT(moddu, moddu_op)
752 DEF_EMIT_REG3_FORMAT(and, and_op)
753 DEF_EMIT_REG3_FORMAT(or, or_op)
754 DEF_EMIT_REG3_FORMAT(xor, xor_op)
755 DEF_EMIT_REG3_FORMAT(sllw, sllw_op)
756 DEF_EMIT_REG3_FORMAT(slld, slld_op)
757 DEF_EMIT_REG3_FORMAT(srlw, srlw_op)
758 DEF_EMIT_REG3_FORMAT(srld, srld_op)
759 DEF_EMIT_REG3_FORMAT(sraw, sraw_op)
760 DEF_EMIT_REG3_FORMAT(srad, srad_op)
761 DEF_EMIT_REG3_FORMAT(ldxb, ldxb_op)
762 DEF_EMIT_REG3_FORMAT(ldxh, ldxh_op)
763 DEF_EMIT_REG3_FORMAT(ldxw, ldxw_op)
764 DEF_EMIT_REG3_FORMAT(ldxbu, ldxbu_op)
765 DEF_EMIT_REG3_FORMAT(ldxhu, ldxhu_op)
766 DEF_EMIT_REG3_FORMAT(ldxwu, ldxwu_op)
767 DEF_EMIT_REG3_FORMAT(ldxd, ldxd_op)
768 DEF_EMIT_REG3_FORMAT(stxb, stxb_op)
769 DEF_EMIT_REG3_FORMAT(stxh, stxh_op)
770 DEF_EMIT_REG3_FORMAT(stxw, stxw_op)
771 DEF_EMIT_REG3_FORMAT(stxd, stxd_op)
772 DEF_EMIT_REG3_FORMAT(amaddb, amaddb_op)
773 DEF_EMIT_REG3_FORMAT(amaddh, amaddh_op)
774 DEF_EMIT_REG3_FORMAT(amaddw, amaddw_op)
775 DEF_EMIT_REG3_FORMAT(amaddd, amaddd_op)
776 DEF_EMIT_REG3_FORMAT(amandw, amandw_op)
777 DEF_EMIT_REG3_FORMAT(amandd, amandd_op)
778 DEF_EMIT_REG3_FORMAT(amorw, amorw_op)
779 DEF_EMIT_REG3_FORMAT(amord, amord_op)
780 DEF_EMIT_REG3_FORMAT(amxorw, amxorw_op)
781 DEF_EMIT_REG3_FORMAT(amxord, amxord_op)
782 DEF_EMIT_REG3_FORMAT(amswapb, amswapb_op)
783 DEF_EMIT_REG3_FORMAT(amswaph, amswaph_op)
784 DEF_EMIT_REG3_FORMAT(amswapw, amswapw_op)
785 DEF_EMIT_REG3_FORMAT(amswapd, amswapd_op)
786
787 #define DEF_EMIT_REG3SA2_FORMAT(NAME, OP) \
788 static inline void emit_##NAME(union loongarch_instruction *insn, \
789 enum loongarch_gpr rd, \
790 enum loongarch_gpr rj, \
791 enum loongarch_gpr rk, \
792 int imm) \
793 { \
794 insn->reg3sa2_format.opcode = OP; \
795 insn->reg3sa2_format.immediate = imm; \
796 insn->reg3sa2_format.rd = rd; \
797 insn->reg3sa2_format.rj = rj; \
798 insn->reg3sa2_format.rk = rk; \
799 }
800
801 DEF_EMIT_REG3SA2_FORMAT(alsld, alsld_op)
802
803 struct pt_regs;
804
805 void emulate_load_store_insn(struct pt_regs *regs, void __user *addr, unsigned int *pc);
806 unsigned long unaligned_read(void __user *addr, void *value, unsigned long n, bool sign);
807 unsigned long unaligned_write(void __user *addr, unsigned long value, unsigned long n);
808
809 #endif /* _ASM_INST_H */
810