1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christian König
23 */
24 #ifndef __AMDGPU_VM_H__
25 #define __AMDGPU_VM_H__
26
27 #include <linux/idr.h>
28 #include <linux/kfifo.h>
29 #include <linux/rbtree.h>
30 #include <drm/gpu_scheduler.h>
31 #include <drm/drm_file.h>
32 #include <drm/ttm/ttm_bo.h>
33 #include <linux/sched/mm.h>
34
35 #include "amdgpu_sync.h"
36 #include "amdgpu_ring.h"
37 #include "amdgpu_ids.h"
38 #include "amdgpu_ttm.h"
39
40 struct drm_exec;
41
42 struct amdgpu_bo_va;
43 struct amdgpu_job;
44 struct amdgpu_bo_list_entry;
45 struct amdgpu_bo_vm;
46
47 /*
48 * GPUVM handling
49 */
50
51 /* Maximum number of PTEs the hardware can write with one command */
52 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
53
54 /* number of entries in page table */
55 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
56
57 #define AMDGPU_PTE_VALID (1ULL << 0)
58 #define AMDGPU_PTE_SYSTEM (1ULL << 1)
59 #define AMDGPU_PTE_SNOOPED (1ULL << 2)
60
61 /* RV+ */
62 #define AMDGPU_PTE_TMZ (1ULL << 3)
63
64 /* VI only */
65 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4)
66
67 #define AMDGPU_PTE_READABLE (1ULL << 5)
68 #define AMDGPU_PTE_WRITEABLE (1ULL << 6)
69
70 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
71
72 /* TILED for VEGA10, reserved for older ASICs */
73 #define AMDGPU_PTE_PRT (1ULL << 51)
74
75 /* PDE is handled as PTE for VEGA10 */
76 #define AMDGPU_PDE_PTE (1ULL << 54)
77
78 #define AMDGPU_PTE_LOG (1ULL << 55)
79
80 /* PTE is handled as PDE for VEGA10 (Translate Further) */
81 #define AMDGPU_PTE_TF (1ULL << 56)
82
83 /* MALL noalloc for sienna_cichlid, reserved for older ASICs */
84 #define AMDGPU_PTE_NOALLOC (1ULL << 58)
85
86 /* PDE Block Fragment Size for VEGA10 */
87 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59)
88
89 /* Flag combination to set no-retry with TF disabled */
90 #define AMDGPU_VM_NORETRY_FLAGS (AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE | \
91 AMDGPU_PTE_TF)
92
93 /* Flag combination to set no-retry with TF enabled */
94 #define AMDGPU_VM_NORETRY_FLAGS_TF (AMDGPU_PTE_VALID | AMDGPU_PTE_SYSTEM | \
95 AMDGPU_PTE_PRT)
96 /* For GFX9 */
97 #define AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype) ((uint64_t)(mtype) << 57)
98 #define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10_SHIFT(3ULL)
99 #define AMDGPU_PTE_MTYPE_VG10(flags, mtype) \
100 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_VG10_MASK)) | \
101 AMDGPU_PTE_MTYPE_VG10_SHIFT(mtype))
102
103 #define AMDGPU_MTYPE_NC 0
104 #define AMDGPU_MTYPE_CC 2
105
106 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \
107 | AMDGPU_PTE_SNOOPED \
108 | AMDGPU_PTE_EXECUTABLE \
109 | AMDGPU_PTE_READABLE \
110 | AMDGPU_PTE_WRITEABLE \
111 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC))
112
113 /* gfx10 */
114 #define AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype) ((uint64_t)(mtype) << 48)
115 #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10_SHIFT(7ULL)
116 #define AMDGPU_PTE_MTYPE_NV10(flags, mtype) \
117 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_NV10_MASK)) | \
118 AMDGPU_PTE_MTYPE_NV10_SHIFT(mtype))
119
120 /* gfx12 */
121 #define AMDGPU_PTE_PRT_GFX12 (1ULL << 56)
122 #define AMDGPU_PTE_PRT_FLAG(adev) \
123 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PTE_PRT_GFX12 : AMDGPU_PTE_PRT)
124
125 #define AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype) ((uint64_t)(mtype) << 54)
126 #define AMDGPU_PTE_MTYPE_GFX12_MASK AMDGPU_PTE_MTYPE_GFX12_SHIFT(3ULL)
127 #define AMDGPU_PTE_MTYPE_GFX12(flags, mtype) \
128 (((uint64_t)(flags) & (~AMDGPU_PTE_MTYPE_GFX12_MASK)) | \
129 AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype))
130
131 #define AMDGPU_PTE_DCC (1ULL << 58)
132 #define AMDGPU_PTE_BUS_ATOMICS (1ULL << 59)
133 #define AMDGPU_PTE_IS_PTE (1ULL << 63)
134
135 /* PDE Block Fragment Size for gfx v12 */
136 #define AMDGPU_PDE_BFS_GFX12(a) ((uint64_t)((a) & 0x1fULL) << 58)
137 #define AMDGPU_PDE_BFS_FLAG(adev, a) \
138 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_BFS_GFX12(a) : AMDGPU_PDE_BFS(a))
139 /* PDE is handled as PTE for gfx v12 */
140 #define AMDGPU_PDE_PTE_GFX12 (1ULL << 63)
141 #define AMDGPU_PDE_PTE_FLAG(adev) \
142 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_PTE_GFX12 : AMDGPU_PDE_PTE)
143
144 /* How to program VM fault handling */
145 #define AMDGPU_VM_FAULT_STOP_NEVER 0
146 #define AMDGPU_VM_FAULT_STOP_FIRST 1
147 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
148
149 /* How much VRAM be reserved for page tables */
150 #define AMDGPU_VM_RESERVED_VRAM (8ULL << 20)
151
152 /*
153 * max number of VMHUB
154 * layout: max 8 GFXHUB + 4 MMHUB0 + 1 MMHUB1
155 */
156 #define AMDGPU_MAX_VMHUBS 13
157 #define AMDGPU_GFXHUB_START 0
158 #define AMDGPU_MMHUB0_START 8
159 #define AMDGPU_MMHUB1_START 12
160 #define AMDGPU_GFXHUB(x) (AMDGPU_GFXHUB_START + (x))
161 #define AMDGPU_MMHUB0(x) (AMDGPU_MMHUB0_START + (x))
162 #define AMDGPU_MMHUB1(x) (AMDGPU_MMHUB1_START + (x))
163
164 #define AMDGPU_IS_GFXHUB(x) ((x) >= AMDGPU_GFXHUB_START && (x) < AMDGPU_MMHUB0_START)
165 #define AMDGPU_IS_MMHUB0(x) ((x) >= AMDGPU_MMHUB0_START && (x) < AMDGPU_MMHUB1_START)
166 #define AMDGPU_IS_MMHUB1(x) ((x) >= AMDGPU_MMHUB1_START && (x) < AMDGPU_MAX_VMHUBS)
167
168 /* Reserve space at top/bottom of address space for kernel use */
169 #define AMDGPU_VA_RESERVED_CSA_SIZE (2ULL << 20)
170 #define AMDGPU_VA_RESERVED_CSA_START(adev) (((adev)->vm_manager.max_pfn \
171 << AMDGPU_GPU_PAGE_SHIFT) \
172 - AMDGPU_VA_RESERVED_CSA_SIZE)
173 #define AMDGPU_VA_RESERVED_SEQ64_SIZE (2ULL << 20)
174 #define AMDGPU_VA_RESERVED_SEQ64_START(adev) (AMDGPU_VA_RESERVED_CSA_START(adev) \
175 - AMDGPU_VA_RESERVED_SEQ64_SIZE)
176 #define AMDGPU_VA_RESERVED_TRAP_SIZE (2ULL << 12)
177 #define AMDGPU_VA_RESERVED_TRAP_START(adev) (AMDGPU_VA_RESERVED_SEQ64_START(adev) \
178 - AMDGPU_VA_RESERVED_TRAP_SIZE)
179 #define AMDGPU_VA_RESERVED_BOTTOM (1ULL << 16)
180 #define AMDGPU_VA_RESERVED_TOP (AMDGPU_VA_RESERVED_TRAP_SIZE + \
181 AMDGPU_VA_RESERVED_SEQ64_SIZE + \
182 AMDGPU_VA_RESERVED_CSA_SIZE)
183
184 /* See vm_update_mode */
185 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
186 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
187
188 /* VMPT level enumerate, and the hiberachy is:
189 * PDB3->PDB2->PDB1->PDB0->PTB
190 */
191 enum amdgpu_vm_level {
192 AMDGPU_VM_PDB3,
193 AMDGPU_VM_PDB2,
194 AMDGPU_VM_PDB1,
195 AMDGPU_VM_PDB0,
196 AMDGPU_VM_PTB
197 };
198
199 /* base structure for tracking BO usage in a VM */
200 struct amdgpu_vm_bo_base {
201 /* constant after initialization */
202 struct amdgpu_vm *vm;
203 struct amdgpu_bo *bo;
204
205 /* protected by bo being reserved */
206 struct amdgpu_vm_bo_base *next;
207
208 /* protected by vm status_lock */
209 struct list_head vm_status;
210
211 /* if the bo is counted as shared in mem stats
212 * protected by vm status_lock */
213 bool shared;
214
215 /* protected by the BO being reserved */
216 bool moved;
217 };
218
219 /* provided by hw blocks that can write ptes, e.g., sdma */
220 struct amdgpu_vm_pte_funcs {
221 /* number of dw to reserve per operation */
222 unsigned copy_pte_num_dw;
223
224 /* copy pte entries from GART */
225 void (*copy_pte)(struct amdgpu_ib *ib,
226 uint64_t pe, uint64_t src,
227 unsigned count);
228
229 /* write pte one entry at a time with addr mapping */
230 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
231 uint64_t value, unsigned count,
232 uint32_t incr);
233 /* for linear pte/pde updates without addr mapping */
234 void (*set_pte_pde)(struct amdgpu_ib *ib,
235 uint64_t pe,
236 uint64_t addr, unsigned count,
237 uint32_t incr, uint64_t flags);
238 };
239
240 struct amdgpu_task_info {
241 struct drm_wedge_task_info task;
242 char process_name[TASK_COMM_LEN];
243 pid_t tgid;
244 struct kref refcount;
245 };
246
247 /**
248 * struct amdgpu_vm_update_params
249 *
250 * Encapsulate some VM table update parameters to reduce
251 * the number of function parameters
252 *
253 */
254 struct amdgpu_vm_update_params {
255
256 /**
257 * @adev: amdgpu device we do this update for
258 */
259 struct amdgpu_device *adev;
260
261 /**
262 * @vm: optional amdgpu_vm we do this update for
263 */
264 struct amdgpu_vm *vm;
265
266 /**
267 * @immediate: if changes should be made immediately
268 */
269 bool immediate;
270
271 /**
272 * @unlocked: true if the root BO is not locked
273 */
274 bool unlocked;
275
276 /**
277 * @pages_addr:
278 *
279 * DMA addresses to use for mapping
280 */
281 dma_addr_t *pages_addr;
282
283 /**
284 * @job: job to used for hw submission
285 */
286 struct amdgpu_job *job;
287
288 /**
289 * @num_dw_left: number of dw left for the IB
290 */
291 unsigned int num_dw_left;
292
293 /**
294 * @needs_flush: true whenever we need to invalidate the TLB
295 */
296 bool needs_flush;
297
298 /**
299 * @allow_override: true for memory that is not uncached: allows MTYPE
300 * to be overridden for NUMA local memory.
301 */
302 bool allow_override;
303
304 /**
305 * @tlb_flush_waitlist: temporary storage for BOs until tlb_flush
306 */
307 struct list_head tlb_flush_waitlist;
308 };
309
310 struct amdgpu_vm_update_funcs {
311 int (*map_table)(struct amdgpu_bo_vm *bo);
312 int (*prepare)(struct amdgpu_vm_update_params *p,
313 struct amdgpu_sync *sync, u64 k_job_id);
314 int (*update)(struct amdgpu_vm_update_params *p,
315 struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr,
316 unsigned count, uint32_t incr, uint64_t flags);
317 int (*commit)(struct amdgpu_vm_update_params *p,
318 struct dma_fence **fence);
319 };
320
321 struct amdgpu_vm_fault_info {
322 /* fault address */
323 uint64_t addr;
324 /* fault status register */
325 uint32_t status;
326 /* which vmhub? gfxhub, mmhub, etc. */
327 unsigned int vmhub;
328 };
329
330 struct amdgpu_mem_stats {
331 struct drm_memory_stats drm;
332
333 /* buffers that requested this placement but are currently evicted */
334 uint64_t evicted;
335 };
336
337 struct amdgpu_vm {
338 /* tree of virtual addresses mapped */
339 struct rb_root_cached va;
340
341 /* Lock to prevent eviction while we are updating page tables
342 * use vm_eviction_lock/unlock(vm)
343 */
344 struct mutex eviction_lock;
345 bool evicting;
346 unsigned int saved_flags;
347
348 /* Lock to protect vm_bo add/del/move on all lists of vm */
349 spinlock_t status_lock;
350
351 /* Memory statistics for this vm, protected by status_lock */
352 struct amdgpu_mem_stats stats[__AMDGPU_PL_NUM];
353
354 /*
355 * The following lists contain amdgpu_vm_bo_base objects for either
356 * PDs, PTs or per VM BOs. The state transits are:
357 *
358 * evicted -> relocated (PDs, PTs) or moved (per VM BOs) -> idle
359 */
360
361 /* Per-VM and PT BOs who needs a validation */
362 struct list_head evicted;
363
364 /* PT BOs which relocated and their parent need an update */
365 struct list_head relocated;
366
367 /* per VM BOs moved, but not yet updated in the PT */
368 struct list_head moved;
369
370 /* All BOs of this VM not currently in the state machine */
371 struct list_head idle;
372
373 /*
374 * The following lists contain amdgpu_vm_bo_base objects for BOs which
375 * have their own dma_resv object and not depend on the root PD. Their
376 * state transits are:
377 *
378 * evicted_user or invalidated -> done
379 */
380
381 /* BOs for user mode queues that need a validation */
382 struct list_head evicted_user;
383
384 /* regular invalidated BOs, but not yet updated in the PT */
385 struct list_head invalidated;
386
387 /* BOs which are invalidated, has been updated in the PTs */
388 struct list_head done;
389
390 /*
391 * This list contains amdgpu_bo_va_mapping objects which have been freed
392 * but not updated in the PTs
393 */
394 struct list_head freed;
395
396 /* contains the page directory */
397 struct amdgpu_vm_bo_base root;
398 struct dma_fence *last_update;
399
400 /* Scheduler entities for page table updates */
401 struct drm_sched_entity immediate;
402 struct drm_sched_entity delayed;
403
404 /* Last finished delayed update */
405 atomic64_t tlb_seq;
406 struct dma_fence *last_tlb_flush;
407 atomic64_t kfd_last_flushed_seq;
408 uint64_t tlb_fence_context;
409
410 /* How many times we had to re-generate the page tables */
411 uint64_t generation;
412
413 /* Last unlocked submission to the scheduler entities */
414 struct dma_fence *last_unlocked;
415
416 unsigned int pasid;
417 struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS];
418
419 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
420 bool use_cpu_for_update;
421
422 /* Functions to use for VM table updates */
423 const struct amdgpu_vm_update_funcs *update_funcs;
424
425 /* Up to 128 pending retry page faults */
426 DECLARE_KFIFO(faults, u64, 128);
427
428 /* Points to the KFD process VM info */
429 struct amdkfd_process_info *process_info;
430
431 /* List node in amdkfd_process_info.vm_list_head */
432 struct list_head vm_list_node;
433
434 /* Valid while the PD is reserved or fenced */
435 uint64_t pd_phys_addr;
436
437 /* Some basic info about the task */
438 struct amdgpu_task_info *task_info;
439
440 /* Store positions of group of BOs */
441 struct ttm_lru_bulk_move lru_bulk_move;
442 /* Flag to indicate if VM is used for compute */
443 bool is_compute_context;
444
445 /* Memory partition number, -1 means any partition */
446 int8_t mem_id;
447
448 /* cached fault info */
449 struct amdgpu_vm_fault_info fault_info;
450 };
451
452 struct amdgpu_vm_manager {
453 /* Handling of VMIDs */
454 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS];
455 unsigned int first_kfd_vmid;
456 bool concurrent_flush;
457
458 uint64_t max_pfn;
459 uint32_t max_level;
460 uint32_t num_level;
461 uint32_t block_size;
462 uint32_t fragment_size;
463 enum amdgpu_vm_level root_level;
464 /* vram base address for page table entry */
465 u64 vram_base_offset;
466 /* vm pte handling */
467 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
468 struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS];
469 unsigned vm_pte_num_scheds;
470 struct amdgpu_ring *page_fault;
471
472 /* partial resident texture handling */
473 spinlock_t prt_lock;
474 atomic_t num_prt_users;
475
476 /* controls how VM page tables are updated for Graphics and Compute.
477 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU
478 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU
479 */
480 int vm_update_mode;
481
482 /* PASID to VM mapping, will be used in interrupt context to
483 * look up VM of a page fault
484 */
485 struct xarray pasids;
486 /* Global registration of recent page fault information */
487 struct amdgpu_vm_fault_info fault_info;
488 };
489
490 struct amdgpu_bo_va_mapping;
491
492 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
493 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
494 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
495
496 extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs;
497 extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs;
498
499 void amdgpu_vm_manager_init(struct amdgpu_device *adev);
500 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
501
502 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout);
503 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id, uint32_t pasid);
504 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
505 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
506 int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec,
507 unsigned int num_fences);
508 int amdgpu_vm_lock_done_list(struct amdgpu_vm *vm, struct drm_exec *exec,
509 unsigned int num_fences);
510 bool amdgpu_vm_ready(struct amdgpu_vm *vm);
511 uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm);
512 int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm,
513 struct ww_acquire_ctx *ticket,
514 int (*callback)(void *p, struct amdgpu_bo *bo),
515 void *param);
516 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
517 int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
518 struct amdgpu_vm *vm, bool immediate);
519 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
520 struct amdgpu_vm *vm,
521 struct dma_fence **fence);
522 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
523 struct amdgpu_vm *vm,
524 struct ww_acquire_ctx *ticket);
525 int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev,
526 struct amdgpu_vm *vm,
527 uint32_t flush_type,
528 uint32_t xcc_mask);
529 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
530 struct amdgpu_vm *vm, struct amdgpu_bo *bo);
531 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
532 bool immediate, bool unlocked, bool flush_tlb,
533 bool allow_override, struct amdgpu_sync *sync,
534 uint64_t start, uint64_t last, uint64_t flags,
535 uint64_t offset, uint64_t vram_base,
536 struct ttm_resource *res, dma_addr_t *pages_addr,
537 struct dma_fence **fence);
538 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
539 struct amdgpu_bo_va *bo_va,
540 bool clear);
541 bool amdgpu_vm_evictable(struct amdgpu_bo *bo);
542 void amdgpu_vm_bo_invalidate(struct amdgpu_bo *bo, bool evicted);
543 void amdgpu_vm_update_stats(struct amdgpu_vm_bo_base *base,
544 struct ttm_resource *new_res, int sign);
545 void amdgpu_vm_bo_update_shared(struct amdgpu_bo *bo);
546 void amdgpu_vm_bo_move(struct amdgpu_bo *bo, struct ttm_resource *new_mem,
547 bool evicted);
548 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
549 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
550 struct amdgpu_bo *bo);
551 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
552 struct amdgpu_vm *vm,
553 struct amdgpu_bo *bo);
554 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
555 struct amdgpu_bo_va *bo_va,
556 uint64_t addr, uint64_t offset,
557 uint64_t size, uint32_t flags);
558 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
559 struct amdgpu_bo_va *bo_va,
560 uint64_t addr, uint64_t offset,
561 uint64_t size, uint32_t flags);
562 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
563 struct amdgpu_bo_va *bo_va,
564 uint64_t addr);
565 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
566 struct amdgpu_vm *vm,
567 uint64_t saddr, uint64_t size);
568 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
569 uint64_t addr);
570 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket);
571 void amdgpu_vm_bo_del(struct amdgpu_device *adev,
572 struct amdgpu_bo_va *bo_va);
573 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
574 uint32_t fragment_size_default, unsigned max_level,
575 unsigned max_bits);
576 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
577 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
578 struct amdgpu_job *job);
579 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
580
581 struct amdgpu_task_info *
582 amdgpu_vm_get_task_info_pasid(struct amdgpu_device *adev, u32 pasid);
583
584 struct amdgpu_task_info *
585 amdgpu_vm_get_task_info_vm(struct amdgpu_vm *vm);
586
587 void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info);
588
589 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
590 u32 vmid, u32 node_id, uint64_t addr, uint64_t ts,
591 bool write_fault);
592
593 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);
594
595 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
596 struct amdgpu_vm *vm);
597 void amdgpu_vm_get_memory(struct amdgpu_vm *vm,
598 struct amdgpu_mem_stats stats[__AMDGPU_PL_NUM]);
599
600 int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm,
601 struct amdgpu_bo_vm *vmbo, bool immediate);
602 int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm,
603 int level, bool immediate, struct amdgpu_bo_vm **vmbo,
604 int32_t xcp_id);
605 void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm);
606
607 int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params,
608 struct amdgpu_vm_bo_base *entry);
609 int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params,
610 uint64_t start, uint64_t end,
611 uint64_t dst, uint64_t flags);
612 void amdgpu_vm_pt_free_work(struct work_struct *work);
613 void amdgpu_vm_pt_free_list(struct amdgpu_device *adev,
614 struct amdgpu_vm_update_params *params);
615
616 #if defined(CONFIG_DEBUG_FS)
617 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m);
618 #endif
619
620 int amdgpu_vm_pt_map_tables(struct amdgpu_device *adev, struct amdgpu_vm *vm);
621
622 bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo);
623
624 /**
625 * amdgpu_vm_tlb_seq - return tlb flush sequence number
626 * @vm: the amdgpu_vm structure to query
627 *
628 * Returns the tlb flush sequence number which indicates that the VM TLBs needs
629 * to be invalidated whenever the sequence number change.
630 */
amdgpu_vm_tlb_seq(struct amdgpu_vm * vm)631 static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm)
632 {
633 unsigned long flags;
634 spinlock_t *lock;
635
636 /*
637 * Workaround to stop racing between the fence signaling and handling
638 * the cb. The lock is static after initially setting it up, just make
639 * sure that the dma_fence structure isn't freed up.
640 */
641 rcu_read_lock();
642 lock = vm->last_tlb_flush->lock;
643 rcu_read_unlock();
644
645 spin_lock_irqsave(lock, flags);
646 spin_unlock_irqrestore(lock, flags);
647
648 return atomic64_read(&vm->tlb_seq);
649 }
650
651 /*
652 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
653 * happens while holding this lock anywhere to prevent deadlocks when
654 * an MMU notifier runs in reclaim-FS context.
655 */
amdgpu_vm_eviction_lock(struct amdgpu_vm * vm)656 static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
657 {
658 mutex_lock(&vm->eviction_lock);
659 vm->saved_flags = memalloc_noreclaim_save();
660 }
661
amdgpu_vm_eviction_trylock(struct amdgpu_vm * vm)662 static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
663 {
664 if (mutex_trylock(&vm->eviction_lock)) {
665 vm->saved_flags = memalloc_noreclaim_save();
666 return true;
667 }
668 return false;
669 }
670
amdgpu_vm_eviction_unlock(struct amdgpu_vm * vm)671 static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
672 {
673 memalloc_noreclaim_restore(vm->saved_flags);
674 mutex_unlock(&vm->eviction_lock);
675 }
676
677 void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev,
678 unsigned int pasid,
679 uint64_t addr,
680 uint32_t status,
681 unsigned int vmhub);
682 void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev,
683 struct amdgpu_vm *vm,
684 struct dma_fence **fence);
685
686 void amdgpu_vm_print_task_info(struct amdgpu_device *adev,
687 struct amdgpu_task_info *task_info);
688
689 #define amdgpu_vm_bo_va_for_each_valid_mapping(bo_va, mapping) \
690 list_for_each_entry(mapping, &(bo_va)->valids, list)
691 #define amdgpu_vm_bo_va_for_each_invalid_mapping(bo_va, mapping) \
692 list_for_each_entry(mapping, &(bo_va)->invalids, list)
693
694 #endif
695