1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2023 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/kref.h> 26 #include <linux/slab.h> 27 #include <linux/dma-fence-unwrap.h> 28 29 #include <drm/drm_exec.h> 30 #include <drm/drm_syncobj.h> 31 32 #include "amdgpu.h" 33 #include "amdgpu_userq_fence.h" 34 35 static const struct dma_fence_ops amdgpu_userq_fence_ops; 36 static struct kmem_cache *amdgpu_userq_fence_slab; 37 38 int amdgpu_userq_fence_slab_init(void) 39 { 40 amdgpu_userq_fence_slab = kmem_cache_create("amdgpu_userq_fence", 41 sizeof(struct amdgpu_userq_fence), 42 0, 43 SLAB_HWCACHE_ALIGN, 44 NULL); 45 if (!amdgpu_userq_fence_slab) 46 return -ENOMEM; 47 48 return 0; 49 } 50 51 void amdgpu_userq_fence_slab_fini(void) 52 { 53 rcu_barrier(); 54 kmem_cache_destroy(amdgpu_userq_fence_slab); 55 } 56 57 static inline struct amdgpu_userq_fence *to_amdgpu_userq_fence(struct dma_fence *f) 58 { 59 if (!f || f->ops != &amdgpu_userq_fence_ops) 60 return NULL; 61 62 return container_of(f, struct amdgpu_userq_fence, base); 63 } 64 65 static u64 amdgpu_userq_fence_read(struct amdgpu_userq_fence_driver *fence_drv) 66 { 67 return le64_to_cpu(*fence_drv->cpu_addr); 68 } 69 70 static void 71 amdgpu_userq_fence_write(struct amdgpu_userq_fence_driver *fence_drv, 72 u64 seq) 73 { 74 if (fence_drv->cpu_addr) 75 *fence_drv->cpu_addr = cpu_to_le64(seq); 76 } 77 78 int amdgpu_userq_fence_driver_alloc(struct amdgpu_device *adev, 79 struct amdgpu_usermode_queue *userq) 80 { 81 struct amdgpu_userq_fence_driver *fence_drv; 82 unsigned long flags; 83 int r; 84 85 fence_drv = kzalloc(sizeof(*fence_drv), GFP_KERNEL); 86 if (!fence_drv) 87 return -ENOMEM; 88 89 /* Acquire seq64 memory */ 90 r = amdgpu_seq64_alloc(adev, &fence_drv->va, &fence_drv->gpu_addr, 91 &fence_drv->cpu_addr); 92 if (r) 93 goto free_fence_drv; 94 95 memset(fence_drv->cpu_addr, 0, sizeof(u64)); 96 97 kref_init(&fence_drv->refcount); 98 INIT_LIST_HEAD(&fence_drv->fences); 99 spin_lock_init(&fence_drv->fence_list_lock); 100 101 fence_drv->adev = adev; 102 fence_drv->context = dma_fence_context_alloc(1); 103 get_task_comm(fence_drv->timeline_name, current); 104 105 xa_lock_irqsave(&adev->userq_xa, flags); 106 r = xa_err(__xa_store(&adev->userq_xa, userq->doorbell_index, 107 fence_drv, GFP_KERNEL)); 108 xa_unlock_irqrestore(&adev->userq_xa, flags); 109 if (r) 110 goto free_seq64; 111 112 userq->fence_drv = fence_drv; 113 114 return 0; 115 116 free_seq64: 117 amdgpu_seq64_free(adev, fence_drv->va); 118 free_fence_drv: 119 kfree(fence_drv); 120 121 return r; 122 } 123 124 static void amdgpu_userq_walk_and_drop_fence_drv(struct xarray *xa) 125 { 126 struct amdgpu_userq_fence_driver *fence_drv; 127 unsigned long index; 128 129 if (xa_empty(xa)) 130 return; 131 132 xa_lock(xa); 133 xa_for_each(xa, index, fence_drv) { 134 __xa_erase(xa, index); 135 amdgpu_userq_fence_driver_put(fence_drv); 136 } 137 138 xa_unlock(xa); 139 } 140 141 void 142 amdgpu_userq_fence_driver_free(struct amdgpu_usermode_queue *userq) 143 { 144 amdgpu_userq_walk_and_drop_fence_drv(&userq->fence_drv_xa); 145 xa_destroy(&userq->fence_drv_xa); 146 /* Drop the fence_drv reference held by user queue */ 147 amdgpu_userq_fence_driver_put(userq->fence_drv); 148 } 149 150 void amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_drv) 151 { 152 struct amdgpu_userq_fence *userq_fence, *tmp; 153 struct dma_fence *fence; 154 unsigned long flags; 155 u64 rptr; 156 int i; 157 158 if (!fence_drv) 159 return; 160 161 spin_lock_irqsave(&fence_drv->fence_list_lock, flags); 162 rptr = amdgpu_userq_fence_read(fence_drv); 163 164 list_for_each_entry_safe(userq_fence, tmp, &fence_drv->fences, link) { 165 fence = &userq_fence->base; 166 167 if (rptr < fence->seqno) 168 break; 169 170 dma_fence_signal(fence); 171 172 for (i = 0; i < userq_fence->fence_drv_array_count; i++) 173 amdgpu_userq_fence_driver_put(userq_fence->fence_drv_array[i]); 174 175 list_del(&userq_fence->link); 176 dma_fence_put(fence); 177 } 178 spin_unlock_irqrestore(&fence_drv->fence_list_lock, flags); 179 } 180 181 void amdgpu_userq_fence_driver_destroy(struct kref *ref) 182 { 183 struct amdgpu_userq_fence_driver *fence_drv = container_of(ref, 184 struct amdgpu_userq_fence_driver, 185 refcount); 186 struct amdgpu_userq_fence_driver *xa_fence_drv; 187 struct amdgpu_device *adev = fence_drv->adev; 188 struct amdgpu_userq_fence *fence, *tmp; 189 struct xarray *xa = &adev->userq_xa; 190 unsigned long index, flags; 191 struct dma_fence *f; 192 193 spin_lock_irqsave(&fence_drv->fence_list_lock, flags); 194 list_for_each_entry_safe(fence, tmp, &fence_drv->fences, link) { 195 f = &fence->base; 196 197 if (!dma_fence_is_signaled(f)) { 198 dma_fence_set_error(f, -ECANCELED); 199 dma_fence_signal(f); 200 } 201 202 list_del(&fence->link); 203 dma_fence_put(f); 204 } 205 spin_unlock_irqrestore(&fence_drv->fence_list_lock, flags); 206 207 xa_lock_irqsave(xa, flags); 208 xa_for_each(xa, index, xa_fence_drv) 209 if (xa_fence_drv == fence_drv) 210 __xa_erase(xa, index); 211 xa_unlock_irqrestore(xa, flags); 212 213 /* Free seq64 memory */ 214 amdgpu_seq64_free(adev, fence_drv->va); 215 kfree(fence_drv); 216 } 217 218 void amdgpu_userq_fence_driver_get(struct amdgpu_userq_fence_driver *fence_drv) 219 { 220 kref_get(&fence_drv->refcount); 221 } 222 223 void amdgpu_userq_fence_driver_put(struct amdgpu_userq_fence_driver *fence_drv) 224 { 225 kref_put(&fence_drv->refcount, amdgpu_userq_fence_driver_destroy); 226 } 227 228 static int amdgpu_userq_fence_alloc(struct amdgpu_userq_fence **userq_fence) 229 { 230 *userq_fence = kmem_cache_alloc(amdgpu_userq_fence_slab, GFP_ATOMIC); 231 return *userq_fence ? 0 : -ENOMEM; 232 } 233 234 static int amdgpu_userq_fence_create(struct amdgpu_usermode_queue *userq, 235 struct amdgpu_userq_fence *userq_fence, 236 u64 seq, struct dma_fence **f) 237 { 238 struct amdgpu_userq_fence_driver *fence_drv; 239 struct dma_fence *fence; 240 unsigned long flags; 241 242 fence_drv = userq->fence_drv; 243 if (!fence_drv) 244 return -EINVAL; 245 246 spin_lock_init(&userq_fence->lock); 247 INIT_LIST_HEAD(&userq_fence->link); 248 fence = &userq_fence->base; 249 userq_fence->fence_drv = fence_drv; 250 251 dma_fence_init64(fence, &amdgpu_userq_fence_ops, &userq_fence->lock, 252 fence_drv->context, seq); 253 254 amdgpu_userq_fence_driver_get(fence_drv); 255 dma_fence_get(fence); 256 257 if (!xa_empty(&userq->fence_drv_xa)) { 258 struct amdgpu_userq_fence_driver *stored_fence_drv; 259 unsigned long index, count = 0; 260 int i = 0; 261 262 xa_lock(&userq->fence_drv_xa); 263 xa_for_each(&userq->fence_drv_xa, index, stored_fence_drv) 264 count++; 265 266 userq_fence->fence_drv_array = 267 kvmalloc_array(count, 268 sizeof(struct amdgpu_userq_fence_driver *), 269 GFP_ATOMIC); 270 271 if (userq_fence->fence_drv_array) { 272 xa_for_each(&userq->fence_drv_xa, index, stored_fence_drv) { 273 userq_fence->fence_drv_array[i] = stored_fence_drv; 274 __xa_erase(&userq->fence_drv_xa, index); 275 i++; 276 } 277 } 278 279 userq_fence->fence_drv_array_count = i; 280 xa_unlock(&userq->fence_drv_xa); 281 } else { 282 userq_fence->fence_drv_array = NULL; 283 userq_fence->fence_drv_array_count = 0; 284 } 285 286 /* Check if hardware has already processed the job */ 287 spin_lock_irqsave(&fence_drv->fence_list_lock, flags); 288 if (!dma_fence_is_signaled(fence)) 289 list_add_tail(&userq_fence->link, &fence_drv->fences); 290 else 291 dma_fence_put(fence); 292 293 spin_unlock_irqrestore(&fence_drv->fence_list_lock, flags); 294 295 *f = fence; 296 297 return 0; 298 } 299 300 static const char *amdgpu_userq_fence_get_driver_name(struct dma_fence *f) 301 { 302 return "amdgpu_userq_fence"; 303 } 304 305 static const char *amdgpu_userq_fence_get_timeline_name(struct dma_fence *f) 306 { 307 struct amdgpu_userq_fence *fence = to_amdgpu_userq_fence(f); 308 309 return fence->fence_drv->timeline_name; 310 } 311 312 static bool amdgpu_userq_fence_signaled(struct dma_fence *f) 313 { 314 struct amdgpu_userq_fence *fence = to_amdgpu_userq_fence(f); 315 struct amdgpu_userq_fence_driver *fence_drv = fence->fence_drv; 316 u64 rptr, wptr; 317 318 rptr = amdgpu_userq_fence_read(fence_drv); 319 wptr = fence->base.seqno; 320 321 if (rptr >= wptr) 322 return true; 323 324 return false; 325 } 326 327 static void amdgpu_userq_fence_free(struct rcu_head *rcu) 328 { 329 struct dma_fence *fence = container_of(rcu, struct dma_fence, rcu); 330 struct amdgpu_userq_fence *userq_fence = to_amdgpu_userq_fence(fence); 331 struct amdgpu_userq_fence_driver *fence_drv = userq_fence->fence_drv; 332 333 /* Release the fence driver reference */ 334 amdgpu_userq_fence_driver_put(fence_drv); 335 336 kvfree(userq_fence->fence_drv_array); 337 kmem_cache_free(amdgpu_userq_fence_slab, userq_fence); 338 } 339 340 static void amdgpu_userq_fence_release(struct dma_fence *f) 341 { 342 call_rcu(&f->rcu, amdgpu_userq_fence_free); 343 } 344 345 static const struct dma_fence_ops amdgpu_userq_fence_ops = { 346 .get_driver_name = amdgpu_userq_fence_get_driver_name, 347 .get_timeline_name = amdgpu_userq_fence_get_timeline_name, 348 .signaled = amdgpu_userq_fence_signaled, 349 .release = amdgpu_userq_fence_release, 350 }; 351 352 /** 353 * amdgpu_userq_fence_read_wptr - Read the userq wptr value 354 * 355 * @queue: user mode queue structure pointer 356 * @wptr: write pointer value 357 * 358 * Read the wptr value from userq's MQD. The userq signal IOCTL 359 * creates a dma_fence for the shared buffers that expects the 360 * RPTR value written to seq64 memory >= WPTR. 361 * 362 * Returns wptr value on success, error on failure. 363 */ 364 static int amdgpu_userq_fence_read_wptr(struct amdgpu_usermode_queue *queue, 365 u64 *wptr) 366 { 367 struct amdgpu_bo_va_mapping *mapping; 368 struct amdgpu_bo *bo; 369 u64 addr, *ptr; 370 int r; 371 372 r = amdgpu_bo_reserve(queue->vm->root.bo, false); 373 if (r) 374 return r; 375 376 addr = queue->userq_prop->wptr_gpu_addr; 377 addr &= AMDGPU_GMC_HOLE_MASK; 378 379 mapping = amdgpu_vm_bo_lookup_mapping(queue->vm, addr >> PAGE_SHIFT); 380 if (!mapping) { 381 amdgpu_bo_unreserve(queue->vm->root.bo); 382 DRM_ERROR("Failed to lookup amdgpu_bo_va_mapping\n"); 383 return -EINVAL; 384 } 385 386 bo = amdgpu_bo_ref(mapping->bo_va->base.bo); 387 amdgpu_bo_unreserve(queue->vm->root.bo); 388 r = amdgpu_bo_reserve(bo, true); 389 if (r) { 390 amdgpu_bo_unref(&bo); 391 DRM_ERROR("Failed to reserve userqueue wptr bo"); 392 return r; 393 } 394 395 r = amdgpu_bo_kmap(bo, (void **)&ptr); 396 if (r) { 397 DRM_ERROR("Failed mapping the userqueue wptr bo"); 398 goto map_error; 399 } 400 401 *wptr = le64_to_cpu(*ptr); 402 403 amdgpu_bo_kunmap(bo); 404 amdgpu_bo_unreserve(bo); 405 amdgpu_bo_unref(&bo); 406 407 return 0; 408 409 map_error: 410 amdgpu_bo_unreserve(bo); 411 amdgpu_bo_unref(&bo); 412 413 return r; 414 } 415 416 static void amdgpu_userq_fence_cleanup(struct dma_fence *fence) 417 { 418 dma_fence_put(fence); 419 } 420 421 static void 422 amdgpu_userq_fence_driver_set_error(struct amdgpu_userq_fence *fence, 423 int error) 424 { 425 struct amdgpu_userq_fence_driver *fence_drv = fence->fence_drv; 426 unsigned long flags; 427 struct dma_fence *f; 428 429 spin_lock_irqsave(&fence_drv->fence_list_lock, flags); 430 431 f = rcu_dereference_protected(&fence->base, 432 lockdep_is_held(&fence_drv->fence_list_lock)); 433 if (f && !dma_fence_is_signaled_locked(f)) 434 dma_fence_set_error(f, error); 435 spin_unlock_irqrestore(&fence_drv->fence_list_lock, flags); 436 } 437 438 void 439 amdgpu_userq_fence_driver_force_completion(struct amdgpu_usermode_queue *userq) 440 { 441 struct dma_fence *f = userq->last_fence; 442 443 if (f) { 444 struct amdgpu_userq_fence *fence = to_amdgpu_userq_fence(f); 445 struct amdgpu_userq_fence_driver *fence_drv = fence->fence_drv; 446 u64 wptr = fence->base.seqno; 447 448 amdgpu_userq_fence_driver_set_error(fence, -ECANCELED); 449 amdgpu_userq_fence_write(fence_drv, wptr); 450 amdgpu_userq_fence_driver_process(fence_drv); 451 452 } 453 } 454 455 int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, 456 struct drm_file *filp) 457 { 458 struct amdgpu_fpriv *fpriv = filp->driver_priv; 459 struct amdgpu_userq_mgr *userq_mgr = &fpriv->userq_mgr; 460 struct drm_amdgpu_userq_signal *args = data; 461 struct drm_gem_object **gobj_write = NULL; 462 struct drm_gem_object **gobj_read = NULL; 463 struct amdgpu_usermode_queue *queue; 464 struct amdgpu_userq_fence *userq_fence; 465 struct drm_syncobj **syncobj = NULL; 466 u32 *bo_handles_write, num_write_bo_handles; 467 u32 *syncobj_handles, num_syncobj_handles; 468 u32 *bo_handles_read, num_read_bo_handles; 469 int r, i, entry, rentry, wentry; 470 struct dma_fence *fence; 471 struct drm_exec exec; 472 u64 wptr; 473 474 num_syncobj_handles = args->num_syncobj_handles; 475 syncobj_handles = memdup_user(u64_to_user_ptr(args->syncobj_handles), 476 size_mul(sizeof(u32), num_syncobj_handles)); 477 if (IS_ERR(syncobj_handles)) 478 return PTR_ERR(syncobj_handles); 479 480 /* Array of pointers to the looked up syncobjs */ 481 syncobj = kmalloc_array(num_syncobj_handles, sizeof(*syncobj), GFP_KERNEL); 482 if (!syncobj) { 483 r = -ENOMEM; 484 goto free_syncobj_handles; 485 } 486 487 for (entry = 0; entry < num_syncobj_handles; entry++) { 488 syncobj[entry] = drm_syncobj_find(filp, syncobj_handles[entry]); 489 if (!syncobj[entry]) { 490 r = -ENOENT; 491 goto free_syncobj; 492 } 493 } 494 495 num_read_bo_handles = args->num_bo_read_handles; 496 bo_handles_read = memdup_user(u64_to_user_ptr(args->bo_read_handles), 497 sizeof(u32) * num_read_bo_handles); 498 if (IS_ERR(bo_handles_read)) { 499 r = PTR_ERR(bo_handles_read); 500 goto free_syncobj; 501 } 502 503 /* Array of pointers to the GEM read objects */ 504 gobj_read = kmalloc_array(num_read_bo_handles, sizeof(*gobj_read), GFP_KERNEL); 505 if (!gobj_read) { 506 r = -ENOMEM; 507 goto free_bo_handles_read; 508 } 509 510 for (rentry = 0; rentry < num_read_bo_handles; rentry++) { 511 gobj_read[rentry] = drm_gem_object_lookup(filp, bo_handles_read[rentry]); 512 if (!gobj_read[rentry]) { 513 r = -ENOENT; 514 goto put_gobj_read; 515 } 516 } 517 518 num_write_bo_handles = args->num_bo_write_handles; 519 bo_handles_write = memdup_user(u64_to_user_ptr(args->bo_write_handles), 520 sizeof(u32) * num_write_bo_handles); 521 if (IS_ERR(bo_handles_write)) { 522 r = PTR_ERR(bo_handles_write); 523 goto put_gobj_read; 524 } 525 526 /* Array of pointers to the GEM write objects */ 527 gobj_write = kmalloc_array(num_write_bo_handles, sizeof(*gobj_write), GFP_KERNEL); 528 if (!gobj_write) { 529 r = -ENOMEM; 530 goto free_bo_handles_write; 531 } 532 533 for (wentry = 0; wentry < num_write_bo_handles; wentry++) { 534 gobj_write[wentry] = drm_gem_object_lookup(filp, bo_handles_write[wentry]); 535 if (!gobj_write[wentry]) { 536 r = -ENOENT; 537 goto put_gobj_write; 538 } 539 } 540 541 /* Retrieve the user queue */ 542 queue = xa_load(&userq_mgr->userq_mgr_xa, args->queue_id); 543 if (!queue) { 544 r = -ENOENT; 545 goto put_gobj_write; 546 } 547 548 r = amdgpu_userq_fence_read_wptr(queue, &wptr); 549 if (r) 550 goto put_gobj_write; 551 552 r = amdgpu_userq_fence_alloc(&userq_fence); 553 if (r) 554 goto put_gobj_write; 555 556 /* We are here means UQ is active, make sure the eviction fence is valid */ 557 amdgpu_userq_ensure_ev_fence(&fpriv->userq_mgr, &fpriv->evf_mgr); 558 559 /* Create a new fence */ 560 r = amdgpu_userq_fence_create(queue, userq_fence, wptr, &fence); 561 if (r) { 562 mutex_unlock(&userq_mgr->userq_mutex); 563 kmem_cache_free(amdgpu_userq_fence_slab, userq_fence); 564 goto put_gobj_write; 565 } 566 567 dma_fence_put(queue->last_fence); 568 queue->last_fence = dma_fence_get(fence); 569 mutex_unlock(&userq_mgr->userq_mutex); 570 571 drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 572 (num_read_bo_handles + num_write_bo_handles)); 573 574 /* Lock all BOs with retry handling */ 575 drm_exec_until_all_locked(&exec) { 576 r = drm_exec_prepare_array(&exec, gobj_read, num_read_bo_handles, 1); 577 drm_exec_retry_on_contention(&exec); 578 if (r) { 579 amdgpu_userq_fence_cleanup(fence); 580 goto exec_fini; 581 } 582 583 r = drm_exec_prepare_array(&exec, gobj_write, num_write_bo_handles, 1); 584 drm_exec_retry_on_contention(&exec); 585 if (r) { 586 amdgpu_userq_fence_cleanup(fence); 587 goto exec_fini; 588 } 589 } 590 591 for (i = 0; i < num_read_bo_handles; i++) { 592 if (!gobj_read || !gobj_read[i]->resv) 593 continue; 594 595 dma_resv_add_fence(gobj_read[i]->resv, fence, 596 DMA_RESV_USAGE_READ); 597 } 598 599 for (i = 0; i < num_write_bo_handles; i++) { 600 if (!gobj_write || !gobj_write[i]->resv) 601 continue; 602 603 dma_resv_add_fence(gobj_write[i]->resv, fence, 604 DMA_RESV_USAGE_WRITE); 605 } 606 607 /* Add the created fence to syncobj/BO's */ 608 for (i = 0; i < num_syncobj_handles; i++) 609 drm_syncobj_replace_fence(syncobj[i], fence); 610 611 /* drop the reference acquired in fence creation function */ 612 dma_fence_put(fence); 613 614 exec_fini: 615 drm_exec_fini(&exec); 616 put_gobj_write: 617 while (wentry-- > 0) 618 drm_gem_object_put(gobj_write[wentry]); 619 kfree(gobj_write); 620 free_bo_handles_write: 621 kfree(bo_handles_write); 622 put_gobj_read: 623 while (rentry-- > 0) 624 drm_gem_object_put(gobj_read[rentry]); 625 kfree(gobj_read); 626 free_bo_handles_read: 627 kfree(bo_handles_read); 628 free_syncobj: 629 while (entry-- > 0) 630 if (syncobj[entry]) 631 drm_syncobj_put(syncobj[entry]); 632 kfree(syncobj); 633 free_syncobj_handles: 634 kfree(syncobj_handles); 635 636 return r; 637 } 638 639 int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, 640 struct drm_file *filp) 641 { 642 u32 *syncobj_handles, *timeline_points, *timeline_handles, *bo_handles_read, *bo_handles_write; 643 u32 num_syncobj, num_read_bo_handles, num_write_bo_handles; 644 struct drm_amdgpu_userq_fence_info *fence_info = NULL; 645 struct drm_amdgpu_userq_wait *wait_info = data; 646 struct amdgpu_fpriv *fpriv = filp->driver_priv; 647 struct amdgpu_userq_mgr *userq_mgr = &fpriv->userq_mgr; 648 struct amdgpu_usermode_queue *waitq; 649 struct drm_gem_object **gobj_write; 650 struct drm_gem_object **gobj_read; 651 struct dma_fence **fences = NULL; 652 u16 num_points, num_fences = 0; 653 int r, i, rentry, wentry, cnt; 654 struct drm_exec exec; 655 656 num_read_bo_handles = wait_info->num_bo_read_handles; 657 bo_handles_read = memdup_user(u64_to_user_ptr(wait_info->bo_read_handles), 658 size_mul(sizeof(u32), num_read_bo_handles)); 659 if (IS_ERR(bo_handles_read)) 660 return PTR_ERR(bo_handles_read); 661 662 num_write_bo_handles = wait_info->num_bo_write_handles; 663 bo_handles_write = memdup_user(u64_to_user_ptr(wait_info->bo_write_handles), 664 size_mul(sizeof(u32), num_write_bo_handles)); 665 if (IS_ERR(bo_handles_write)) { 666 r = PTR_ERR(bo_handles_write); 667 goto free_bo_handles_read; 668 } 669 670 num_syncobj = wait_info->num_syncobj_handles; 671 syncobj_handles = memdup_user(u64_to_user_ptr(wait_info->syncobj_handles), 672 size_mul(sizeof(u32), num_syncobj)); 673 if (IS_ERR(syncobj_handles)) { 674 r = PTR_ERR(syncobj_handles); 675 goto free_bo_handles_write; 676 } 677 678 num_points = wait_info->num_syncobj_timeline_handles; 679 timeline_handles = memdup_user(u64_to_user_ptr(wait_info->syncobj_timeline_handles), 680 sizeof(u32) * num_points); 681 if (IS_ERR(timeline_handles)) { 682 r = PTR_ERR(timeline_handles); 683 goto free_syncobj_handles; 684 } 685 686 timeline_points = memdup_user(u64_to_user_ptr(wait_info->syncobj_timeline_points), 687 sizeof(u32) * num_points); 688 if (IS_ERR(timeline_points)) { 689 r = PTR_ERR(timeline_points); 690 goto free_timeline_handles; 691 } 692 693 gobj_read = kmalloc_array(num_read_bo_handles, sizeof(*gobj_read), GFP_KERNEL); 694 if (!gobj_read) { 695 r = -ENOMEM; 696 goto free_timeline_points; 697 } 698 699 for (rentry = 0; rentry < num_read_bo_handles; rentry++) { 700 gobj_read[rentry] = drm_gem_object_lookup(filp, bo_handles_read[rentry]); 701 if (!gobj_read[rentry]) { 702 r = -ENOENT; 703 goto put_gobj_read; 704 } 705 } 706 707 gobj_write = kmalloc_array(num_write_bo_handles, sizeof(*gobj_write), GFP_KERNEL); 708 if (!gobj_write) { 709 r = -ENOMEM; 710 goto put_gobj_read; 711 } 712 713 for (wentry = 0; wentry < num_write_bo_handles; wentry++) { 714 gobj_write[wentry] = drm_gem_object_lookup(filp, bo_handles_write[wentry]); 715 if (!gobj_write[wentry]) { 716 r = -ENOENT; 717 goto put_gobj_write; 718 } 719 } 720 721 drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 722 (num_read_bo_handles + num_write_bo_handles)); 723 724 /* Lock all BOs with retry handling */ 725 drm_exec_until_all_locked(&exec) { 726 r = drm_exec_prepare_array(&exec, gobj_read, num_read_bo_handles, 1); 727 drm_exec_retry_on_contention(&exec); 728 if (r) { 729 drm_exec_fini(&exec); 730 goto put_gobj_write; 731 } 732 733 r = drm_exec_prepare_array(&exec, gobj_write, num_write_bo_handles, 1); 734 drm_exec_retry_on_contention(&exec); 735 if (r) { 736 drm_exec_fini(&exec); 737 goto put_gobj_write; 738 } 739 } 740 741 if (!wait_info->num_fences) { 742 if (num_points) { 743 struct dma_fence_unwrap iter; 744 struct dma_fence *fence; 745 struct dma_fence *f; 746 747 for (i = 0; i < num_points; i++) { 748 r = drm_syncobj_find_fence(filp, timeline_handles[i], 749 timeline_points[i], 750 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, 751 &fence); 752 if (r) 753 goto exec_fini; 754 755 dma_fence_unwrap_for_each(f, &iter, fence) 756 num_fences++; 757 758 dma_fence_put(fence); 759 } 760 } 761 762 /* Count syncobj's fence */ 763 for (i = 0; i < num_syncobj; i++) { 764 struct dma_fence *fence; 765 766 r = drm_syncobj_find_fence(filp, syncobj_handles[i], 767 0, 768 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, 769 &fence); 770 if (r) 771 goto exec_fini; 772 773 num_fences++; 774 dma_fence_put(fence); 775 } 776 777 /* Count GEM objects fence */ 778 for (i = 0; i < num_read_bo_handles; i++) { 779 struct dma_resv_iter resv_cursor; 780 struct dma_fence *fence; 781 782 dma_resv_for_each_fence(&resv_cursor, gobj_read[i]->resv, 783 DMA_RESV_USAGE_READ, fence) 784 num_fences++; 785 } 786 787 for (i = 0; i < num_write_bo_handles; i++) { 788 struct dma_resv_iter resv_cursor; 789 struct dma_fence *fence; 790 791 dma_resv_for_each_fence(&resv_cursor, gobj_write[i]->resv, 792 DMA_RESV_USAGE_WRITE, fence) 793 num_fences++; 794 } 795 796 /* 797 * Passing num_fences = 0 means that userspace doesn't want to 798 * retrieve userq_fence_info. If num_fences = 0 we skip filling 799 * userq_fence_info and return the actual number of fences on 800 * args->num_fences. 801 */ 802 wait_info->num_fences = num_fences; 803 } else { 804 /* Array of fence info */ 805 fence_info = kmalloc_array(wait_info->num_fences, sizeof(*fence_info), GFP_KERNEL); 806 if (!fence_info) { 807 r = -ENOMEM; 808 goto exec_fini; 809 } 810 811 /* Array of fences */ 812 fences = kmalloc_array(wait_info->num_fences, sizeof(*fences), GFP_KERNEL); 813 if (!fences) { 814 r = -ENOMEM; 815 goto free_fence_info; 816 } 817 818 /* Retrieve GEM read objects fence */ 819 for (i = 0; i < num_read_bo_handles; i++) { 820 struct dma_resv_iter resv_cursor; 821 struct dma_fence *fence; 822 823 dma_resv_for_each_fence(&resv_cursor, gobj_read[i]->resv, 824 DMA_RESV_USAGE_READ, fence) { 825 if (WARN_ON_ONCE(num_fences >= wait_info->num_fences)) { 826 r = -EINVAL; 827 goto free_fences; 828 } 829 830 fences[num_fences++] = fence; 831 dma_fence_get(fence); 832 } 833 } 834 835 /* Retrieve GEM write objects fence */ 836 for (i = 0; i < num_write_bo_handles; i++) { 837 struct dma_resv_iter resv_cursor; 838 struct dma_fence *fence; 839 840 dma_resv_for_each_fence(&resv_cursor, gobj_write[i]->resv, 841 DMA_RESV_USAGE_WRITE, fence) { 842 if (WARN_ON_ONCE(num_fences >= wait_info->num_fences)) { 843 r = -EINVAL; 844 goto free_fences; 845 } 846 847 fences[num_fences++] = fence; 848 dma_fence_get(fence); 849 } 850 } 851 852 if (num_points) { 853 struct dma_fence_unwrap iter; 854 struct dma_fence *fence; 855 struct dma_fence *f; 856 857 for (i = 0; i < num_points; i++) { 858 r = drm_syncobj_find_fence(filp, timeline_handles[i], 859 timeline_points[i], 860 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, 861 &fence); 862 if (r) 863 goto free_fences; 864 865 dma_fence_unwrap_for_each(f, &iter, fence) { 866 if (WARN_ON_ONCE(num_fences >= wait_info->num_fences)) { 867 r = -EINVAL; 868 goto free_fences; 869 } 870 871 dma_fence_get(f); 872 fences[num_fences++] = f; 873 } 874 875 dma_fence_put(fence); 876 } 877 } 878 879 /* Retrieve syncobj's fence */ 880 for (i = 0; i < num_syncobj; i++) { 881 struct dma_fence *fence; 882 883 r = drm_syncobj_find_fence(filp, syncobj_handles[i], 884 0, 885 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, 886 &fence); 887 if (r) 888 goto free_fences; 889 890 if (WARN_ON_ONCE(num_fences >= wait_info->num_fences)) { 891 r = -EINVAL; 892 goto free_fences; 893 } 894 895 fences[num_fences++] = fence; 896 } 897 898 /* 899 * Keep only the latest fences to reduce the number of values 900 * given back to userspace. 901 */ 902 num_fences = dma_fence_dedup_array(fences, num_fences); 903 904 waitq = xa_load(&userq_mgr->userq_mgr_xa, wait_info->waitq_id); 905 if (!waitq) { 906 r = -EINVAL; 907 goto free_fences; 908 } 909 910 for (i = 0, cnt = 0; i < num_fences; i++) { 911 struct amdgpu_userq_fence_driver *fence_drv; 912 struct amdgpu_userq_fence *userq_fence; 913 u32 index; 914 915 userq_fence = to_amdgpu_userq_fence(fences[i]); 916 if (!userq_fence) { 917 /* 918 * Just waiting on other driver fences should 919 * be good for now 920 */ 921 r = dma_fence_wait(fences[i], true); 922 if (r) { 923 dma_fence_put(fences[i]); 924 goto free_fences; 925 } 926 927 dma_fence_put(fences[i]); 928 continue; 929 } 930 931 fence_drv = userq_fence->fence_drv; 932 /* 933 * We need to make sure the user queue release their reference 934 * to the fence drivers at some point before queue destruction. 935 * Otherwise, we would gather those references until we don't 936 * have any more space left and crash. 937 */ 938 r = xa_alloc(&waitq->fence_drv_xa, &index, fence_drv, 939 xa_limit_32b, GFP_KERNEL); 940 if (r) 941 goto free_fences; 942 943 amdgpu_userq_fence_driver_get(fence_drv); 944 945 /* Store drm syncobj's gpu va address and value */ 946 fence_info[cnt].va = fence_drv->va; 947 fence_info[cnt].value = fences[i]->seqno; 948 949 dma_fence_put(fences[i]); 950 /* Increment the actual userq fence count */ 951 cnt++; 952 } 953 954 wait_info->num_fences = cnt; 955 /* Copy userq fence info to user space */ 956 if (copy_to_user(u64_to_user_ptr(wait_info->out_fences), 957 fence_info, wait_info->num_fences * sizeof(*fence_info))) { 958 r = -EFAULT; 959 goto free_fences; 960 } 961 962 kfree(fences); 963 kfree(fence_info); 964 } 965 966 drm_exec_fini(&exec); 967 for (i = 0; i < num_read_bo_handles; i++) 968 drm_gem_object_put(gobj_read[i]); 969 kfree(gobj_read); 970 971 for (i = 0; i < num_write_bo_handles; i++) 972 drm_gem_object_put(gobj_write[i]); 973 kfree(gobj_write); 974 975 kfree(timeline_points); 976 kfree(timeline_handles); 977 kfree(syncobj_handles); 978 kfree(bo_handles_write); 979 kfree(bo_handles_read); 980 981 return 0; 982 983 free_fences: 984 while (num_fences-- > 0) 985 dma_fence_put(fences[num_fences]); 986 kfree(fences); 987 free_fence_info: 988 kfree(fence_info); 989 exec_fini: 990 drm_exec_fini(&exec); 991 put_gobj_write: 992 while (wentry-- > 0) 993 drm_gem_object_put(gobj_write[wentry]); 994 kfree(gobj_write); 995 put_gobj_read: 996 while (rentry-- > 0) 997 drm_gem_object_put(gobj_read[rentry]); 998 kfree(gobj_read); 999 free_timeline_points: 1000 kfree(timeline_points); 1001 free_timeline_handles: 1002 kfree(timeline_handles); 1003 free_syncobj_handles: 1004 kfree(syncobj_handles); 1005 free_bo_handles_write: 1006 kfree(bo_handles_write); 1007 free_bo_handles_read: 1008 kfree(bo_handles_read); 1009 1010 return r; 1011 } 1012