1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Christian König
23 */
24 #ifndef __AMDGPU_RING_H__
25 #define __AMDGPU_RING_H__
26
27 #include <drm/amdgpu_drm.h>
28 #include <drm/gpu_scheduler.h>
29 #include <drm/drm_print.h>
30 #include <drm/drm_suballoc.h>
31
32 struct amdgpu_device;
33 struct amdgpu_ring;
34 struct amdgpu_ib;
35 struct amdgpu_cs_parser;
36 struct amdgpu_job;
37 struct amdgpu_vm;
38
39 /* max number of rings */
40 #define AMDGPU_MAX_RINGS 149
41 #define AMDGPU_MAX_HWIP_RINGS 64
42 #define AMDGPU_MAX_GFX_RINGS 2
43 #define AMDGPU_MAX_SW_GFX_RINGS 2
44 #define AMDGPU_MAX_COMPUTE_RINGS 8
45 #define AMDGPU_MAX_VCE_RINGS 3
46 #define AMDGPU_MAX_UVD_ENC_RINGS 2
47 #define AMDGPU_MAX_VPE_RINGS 2
48
49 enum amdgpu_ring_priority_level {
50 AMDGPU_RING_PRIO_0,
51 AMDGPU_RING_PRIO_1,
52 AMDGPU_RING_PRIO_DEFAULT = 1,
53 AMDGPU_RING_PRIO_2,
54 AMDGPU_RING_PRIO_MAX
55 };
56
57 /* some special values for the owner field */
58 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul)
59 #define AMDGPU_FENCE_OWNER_VM ((void *)1ul)
60 #define AMDGPU_FENCE_OWNER_KFD ((void *)2ul)
61
62 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
63 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
64 #define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2)
65 #define AMDGPU_FENCE_FLAG_EXEC (1 << 3)
66
67 #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
68
69 #define AMDGPU_IB_POOL_SIZE (1024 * 1024)
70
71 enum amdgpu_ring_type {
72 AMDGPU_RING_TYPE_GFX = AMDGPU_HW_IP_GFX,
73 AMDGPU_RING_TYPE_COMPUTE = AMDGPU_HW_IP_COMPUTE,
74 AMDGPU_RING_TYPE_SDMA = AMDGPU_HW_IP_DMA,
75 AMDGPU_RING_TYPE_UVD = AMDGPU_HW_IP_UVD,
76 AMDGPU_RING_TYPE_VCE = AMDGPU_HW_IP_VCE,
77 AMDGPU_RING_TYPE_UVD_ENC = AMDGPU_HW_IP_UVD_ENC,
78 AMDGPU_RING_TYPE_VCN_DEC = AMDGPU_HW_IP_VCN_DEC,
79 AMDGPU_RING_TYPE_VCN_ENC = AMDGPU_HW_IP_VCN_ENC,
80 AMDGPU_RING_TYPE_VCN_JPEG = AMDGPU_HW_IP_VCN_JPEG,
81 AMDGPU_RING_TYPE_VPE = AMDGPU_HW_IP_VPE,
82 AMDGPU_RING_TYPE_KIQ,
83 AMDGPU_RING_TYPE_MES,
84 AMDGPU_RING_TYPE_UMSCH_MM,
85 AMDGPU_RING_TYPE_CPER,
86 };
87
88 enum amdgpu_ib_pool_type {
89 /* Normal submissions to the top of the pipeline. */
90 AMDGPU_IB_POOL_DELAYED,
91 /* Immediate submissions to the bottom of the pipeline. */
92 AMDGPU_IB_POOL_IMMEDIATE,
93 /* Direct submission to the ring buffer during init and reset. */
94 AMDGPU_IB_POOL_DIRECT,
95
96 AMDGPU_IB_POOL_MAX
97 };
98
99 struct amdgpu_ib {
100 struct drm_suballoc *sa_bo;
101 uint32_t length_dw;
102 uint64_t gpu_addr;
103 uint32_t *ptr;
104 uint32_t flags;
105 };
106
107 struct amdgpu_sched {
108 u32 num_scheds;
109 struct drm_gpu_scheduler *sched[AMDGPU_MAX_HWIP_RINGS];
110 };
111
112 /*
113 * Fences.
114 */
115 struct amdgpu_fence_driver {
116 uint64_t gpu_addr;
117 volatile uint32_t *cpu_addr;
118 /* sync_seq is protected by ring emission lock */
119 uint32_t sync_seq;
120 atomic_t last_seq;
121 u64 signalled_wptr;
122 bool initialized;
123 struct amdgpu_irq_src *irq_src;
124 unsigned irq_type;
125 struct timer_list fallback_timer;
126 unsigned num_fences_mask;
127 spinlock_t lock;
128 struct dma_fence **fences;
129 };
130
131 /*
132 * Fences mark an event in the GPUs pipeline and are used
133 * for GPU/CPU synchronization. When the fence is written,
134 * it is expected that all buffers associated with that fence
135 * are no longer in use by the associated ring on the GPU and
136 * that the relevant GPU caches have been flushed.
137 */
138
139 struct amdgpu_fence {
140 struct dma_fence base;
141
142 /* RB, DMA, etc. */
143 struct amdgpu_ring *ring;
144 ktime_t start_timestamp;
145
146 /* wptr for the fence for resets */
147 u64 wptr;
148 /* fence context for resets */
149 u64 context;
150 uint32_t seq;
151 };
152
153 extern const struct drm_sched_backend_ops amdgpu_sched_ops;
154
155 void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring);
156 void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error);
157 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
158 void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *fence);
159 void amdgpu_fence_save_wptr(struct dma_fence *fence);
160
161 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
162 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
163 struct amdgpu_irq_src *irq_src,
164 unsigned irq_type);
165 void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev);
166 void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev);
167 int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev);
168 void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev);
169 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f,
170 struct amdgpu_fence *af, unsigned int flags);
171 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
172 uint32_t timeout);
173 bool amdgpu_fence_process(struct amdgpu_ring *ring);
174 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
175 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
176 uint32_t wait_seq,
177 signed long timeout);
178 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
179
180 void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop);
181
182 u64 amdgpu_fence_last_unsignaled_time_us(struct amdgpu_ring *ring);
183 void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq,
184 ktime_t timestamp);
185
186 /*
187 * Rings.
188 */
189
190 /* provided by hw blocks that expose a ring buffer for commands */
191 struct amdgpu_ring_funcs {
192 /**
193 * @type:
194 *
195 * GFX, Compute, SDMA, UVD, VCE, VCN, VPE, KIQ, MES, UMSCH, and CPER
196 * use ring buffers. The type field just identifies which component the
197 * ring buffer is associated with.
198 */
199 enum amdgpu_ring_type type;
200 uint32_t align_mask;
201
202 /**
203 * @nop:
204 *
205 * Every block in the amdgpu has no-op instructions (e.g., GFX 10
206 * uses PACKET3(PACKET3_NOP, 0x3FFF), VCN 5 uses VCN_ENC_CMD_NO_OP,
207 * etc). This field receives the specific no-op for the component
208 * that initializes the ring.
209 */
210 u32 nop;
211 bool support_64bit_ptrs;
212 bool no_user_fence;
213 bool secure_submission_supported;
214 unsigned extra_dw;
215
216 /* ring read/write ptr handling */
217 u64 (*get_rptr)(struct amdgpu_ring *ring);
218 u64 (*get_wptr)(struct amdgpu_ring *ring);
219 void (*set_wptr)(struct amdgpu_ring *ring);
220 /* validating and patching of IBs */
221 int (*parse_cs)(struct amdgpu_cs_parser *p,
222 struct amdgpu_job *job,
223 struct amdgpu_ib *ib);
224 int (*patch_cs_in_place)(struct amdgpu_cs_parser *p,
225 struct amdgpu_job *job,
226 struct amdgpu_ib *ib);
227 /* constants to calculate how many DW are needed for an emit */
228 unsigned emit_frame_size;
229 unsigned emit_ib_size;
230 /* command emit functions */
231 void (*emit_ib)(struct amdgpu_ring *ring,
232 struct amdgpu_job *job,
233 struct amdgpu_ib *ib,
234 uint32_t flags);
235 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
236 uint64_t seq, unsigned flags);
237 void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
238 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
239 uint64_t pd_addr);
240 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
241 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
242 uint32_t gds_base, uint32_t gds_size,
243 uint32_t gws_base, uint32_t gws_size,
244 uint32_t oa_base, uint32_t oa_size);
245 /* testing functions */
246 int (*test_ring)(struct amdgpu_ring *ring);
247 int (*test_ib)(struct amdgpu_ring *ring, long timeout);
248 /* insert NOP packets */
249 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
250 void (*insert_start)(struct amdgpu_ring *ring);
251 void (*insert_end)(struct amdgpu_ring *ring);
252 /* pad the indirect buffer to the necessary number of dw */
253 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
254 unsigned (*init_cond_exec)(struct amdgpu_ring *ring, uint64_t addr);
255 /* note usage for clock and power gating */
256 void (*begin_use)(struct amdgpu_ring *ring);
257 void (*end_use)(struct amdgpu_ring *ring);
258 void (*emit_switch_buffer) (struct amdgpu_ring *ring);
259 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
260 void (*emit_gfx_shadow)(struct amdgpu_ring *ring, u64 shadow_va, u64 csa_va,
261 u64 gds_va, bool init_shadow, int vmid);
262 void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg,
263 uint32_t reg_val_offs);
264 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
265 void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
266 uint32_t val, uint32_t mask);
267 void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
268 uint32_t reg0, uint32_t reg1,
269 uint32_t ref, uint32_t mask);
270 void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start,
271 bool secure);
272 /* Try to soft recover the ring to make the fence signal */
273 void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
274 int (*preempt_ib)(struct amdgpu_ring *ring);
275 void (*emit_mem_sync)(struct amdgpu_ring *ring);
276 void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable);
277 void (*patch_cntl)(struct amdgpu_ring *ring, unsigned offset);
278 void (*patch_ce)(struct amdgpu_ring *ring, unsigned offset);
279 void (*patch_de)(struct amdgpu_ring *ring, unsigned offset);
280 int (*reset)(struct amdgpu_ring *ring, unsigned int vmid,
281 struct amdgpu_fence *timedout_fence);
282 void (*emit_cleaner_shader)(struct amdgpu_ring *ring);
283 };
284
285 /**
286 * amdgpu_ring - Holds ring information
287 */
288 struct amdgpu_ring {
289 struct amdgpu_device *adev;
290 const struct amdgpu_ring_funcs *funcs;
291 struct amdgpu_fence_driver fence_drv;
292 struct drm_gpu_scheduler sched;
293
294 struct amdgpu_bo *ring_obj;
295 uint32_t *ring;
296 /* backups for resets */
297 uint32_t *ring_backup;
298 unsigned int ring_backup_entries_to_copy;
299 unsigned rptr_offs;
300 u64 rptr_gpu_addr;
301 volatile u32 *rptr_cpu_addr;
302
303 /**
304 * @wptr:
305 *
306 * This is part of the Ring buffer implementation and represents the
307 * write pointer. The wptr determines where the host has written.
308 */
309 u64 wptr;
310
311 /**
312 * @wptr_old:
313 *
314 * Before update wptr with the new value, usually the old value is
315 * stored in the wptr_old.
316 */
317 u64 wptr_old;
318 unsigned ring_size;
319
320 /**
321 * @max_dw:
322 *
323 * Maximum number of DWords for ring allocation. This information is
324 * provided at the ring initialization time, and each IP block can
325 * specify a specific value. Check places that invoke
326 * amdgpu_ring_init() to see the maximum size per block.
327 */
328 unsigned max_dw;
329
330 /**
331 * @count_dw:
332 *
333 * This value starts with the maximum amount of DWords supported by the
334 * ring. This value is updated based on the ring manipulation.
335 */
336 int count_dw;
337 uint64_t gpu_addr;
338
339 /**
340 * @ptr_mask:
341 *
342 * Some IPs provide support for 64-bit pointers and others for 32-bit
343 * only; this behavior is component-specific and defined by the field
344 * support_64bit_ptr. If the IP block supports 64-bits, the mask
345 * 0xffffffffffffffff is set; otherwise, this value assumes buf_mask.
346 * Notice that this field is used to keep wptr under a valid range.
347 */
348 uint64_t ptr_mask;
349
350 /**
351 * @buf_mask:
352 *
353 * Buffer mask is a value used to keep wptr count under its
354 * thresholding. Buffer mask initialized during the ring buffer
355 * initialization time, and it is defined as (ring_size / 4) -1.
356 */
357 uint32_t buf_mask;
358 u32 idx;
359 u32 xcc_id;
360 u32 xcp_id;
361 u32 me;
362 u32 pipe;
363 u32 queue;
364 struct amdgpu_bo *mqd_obj;
365 uint64_t mqd_gpu_addr;
366 void *mqd_ptr;
367 unsigned mqd_size;
368 uint64_t eop_gpu_addr;
369 u32 doorbell_index;
370 bool use_doorbell;
371 bool use_pollmem;
372 unsigned wptr_offs;
373 u64 wptr_gpu_addr;
374
375 /**
376 * @wptr_cpu_addr:
377 *
378 * This is the CPU address pointer in the writeback slot. This is used
379 * to commit changes to the GPU.
380 */
381 volatile u32 *wptr_cpu_addr;
382 unsigned fence_offs;
383 u64 fence_gpu_addr;
384 volatile u32 *fence_cpu_addr;
385 uint64_t current_ctx;
386 char name[16];
387 u32 trail_seq;
388 unsigned trail_fence_offs;
389 u64 trail_fence_gpu_addr;
390 volatile u32 *trail_fence_cpu_addr;
391 unsigned cond_exe_offs;
392 u64 cond_exe_gpu_addr;
393 volatile u32 *cond_exe_cpu_addr;
394 unsigned int set_q_mode_offs;
395 u32 *set_q_mode_ptr;
396 u64 set_q_mode_token;
397 unsigned vm_hub;
398 unsigned vm_inv_eng;
399 struct dma_fence *vmid_wait;
400 bool has_compute_vm_bug;
401 bool no_scheduler;
402 bool no_user_submission;
403 int hw_prio;
404 unsigned num_hw_submission;
405 atomic_t *sched_score;
406
407 bool is_sw_ring;
408 unsigned int entry_index;
409 /* store the cached rptr to restore after reset */
410 uint64_t cached_rptr;
411 };
412
413 #define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib)))
414 #define amdgpu_ring_patch_cs_in_place(r, p, job, ib) ((r)->funcs->patch_cs_in_place((p), (job), (ib)))
415 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
416 #define amdgpu_ring_test_ib(r, t) ((r)->funcs->test_ib ? (r)->funcs->test_ib((r), (t)) : 0)
417 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
418 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
419 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
420 #define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags)))
421 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
422 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
423 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
424 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
425 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
426 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
427 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
428 #define amdgpu_ring_emit_gfx_shadow(r, s, c, g, i, v) ((r)->funcs->emit_gfx_shadow((r), (s), (c), (g), (i), (v)))
429 #define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o))
430 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
431 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
432 #define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
433 #define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s))
434 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
435 #define amdgpu_ring_init_cond_exec(r, a) (r)->funcs->init_cond_exec((r), (a))
436 #define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)
437 #define amdgpu_ring_patch_cntl(r, o) ((r)->funcs->patch_cntl((r), (o)))
438 #define amdgpu_ring_patch_ce(r, o) ((r)->funcs->patch_ce((r), (o)))
439 #define amdgpu_ring_patch_de(r, o) ((r)->funcs->patch_de((r), (o)))
440 #define amdgpu_ring_reset(r, v, f) (r)->funcs->reset((r), (v), (f))
441
442 unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type);
443 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
444 void amdgpu_ring_ib_begin(struct amdgpu_ring *ring);
445 void amdgpu_ring_ib_end(struct amdgpu_ring *ring);
446 void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring);
447 void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring);
448 void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring);
449
450 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
451 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
452 void amdgpu_ring_commit(struct amdgpu_ring *ring);
453 void amdgpu_ring_undo(struct amdgpu_ring *ring);
454 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
455 unsigned int max_dw, struct amdgpu_irq_src *irq_src,
456 unsigned int irq_type, unsigned int hw_prio,
457 atomic_t *sched_score);
458 void amdgpu_ring_fini(struct amdgpu_ring *ring);
459 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
460 uint32_t reg0, uint32_t val0,
461 uint32_t reg1, uint32_t val1);
462 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
463 struct dma_fence *fence);
464
amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring * ring,bool cond_exec)465 static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring,
466 bool cond_exec)
467 {
468 *ring->cond_exe_cpu_addr = cond_exec;
469 }
470
amdgpu_ring_clear_ring(struct amdgpu_ring * ring)471 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
472 {
473 int i = 0;
474 while (i <= ring->buf_mask)
475 ring->ring[i++] = ring->funcs->nop;
476
477 }
478
amdgpu_ring_write(struct amdgpu_ring * ring,uint32_t v)479 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
480 {
481 ring->ring[ring->wptr++ & ring->buf_mask] = v;
482 ring->wptr &= ring->ptr_mask;
483 ring->count_dw--;
484 }
485
amdgpu_ring_write_multiple(struct amdgpu_ring * ring,void * src,int count_dw)486 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
487 void *src, int count_dw)
488 {
489 unsigned occupied, chunk1, chunk2;
490
491 occupied = ring->wptr & ring->buf_mask;
492 chunk1 = ring->buf_mask + 1 - occupied;
493 chunk1 = (chunk1 >= count_dw) ? count_dw : chunk1;
494 chunk2 = count_dw - chunk1;
495 chunk1 <<= 2;
496 chunk2 <<= 2;
497
498 if (chunk1)
499 memcpy(&ring->ring[occupied], src, chunk1);
500
501 if (chunk2) {
502 src += chunk1;
503 memcpy(ring->ring, src, chunk2);
504 }
505
506 ring->wptr += count_dw;
507 ring->wptr &= ring->ptr_mask;
508 ring->count_dw -= count_dw;
509 }
510
511 /**
512 * amdgpu_ring_patch_cond_exec - patch dw count of conditional execute
513 * @ring: amdgpu_ring structure
514 * @offset: offset returned by amdgpu_ring_init_cond_exec
515 *
516 * Calculate the dw count and patch it into a cond_exec command.
517 */
amdgpu_ring_patch_cond_exec(struct amdgpu_ring * ring,unsigned int offset)518 static inline void amdgpu_ring_patch_cond_exec(struct amdgpu_ring *ring,
519 unsigned int offset)
520 {
521 unsigned cur;
522
523 if (!ring->funcs->init_cond_exec)
524 return;
525
526 WARN_ON(offset > ring->buf_mask);
527 WARN_ON(ring->ring[offset] != 0);
528
529 cur = (ring->wptr - 1) & ring->buf_mask;
530 if (cur < offset)
531 cur += ring->ring_size >> 2;
532 ring->ring[offset] = cur - offset;
533 }
534
535 int amdgpu_ring_test_helper(struct amdgpu_ring *ring);
536
537 void amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
538 struct amdgpu_ring *ring);
539
540 int amdgpu_ring_init_mqd(struct amdgpu_ring *ring);
541
amdgpu_ib_get_value(struct amdgpu_ib * ib,int idx)542 static inline u32 amdgpu_ib_get_value(struct amdgpu_ib *ib, int idx)
543 {
544 return ib->ptr[idx];
545 }
546
amdgpu_ib_set_value(struct amdgpu_ib * ib,int idx,uint32_t value)547 static inline void amdgpu_ib_set_value(struct amdgpu_ib *ib, int idx,
548 uint32_t value)
549 {
550 ib->ptr[idx] = value;
551 }
552
553 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
554 unsigned size,
555 enum amdgpu_ib_pool_type pool,
556 struct amdgpu_ib *ib);
557 void amdgpu_ib_free(struct amdgpu_ib *ib, struct dma_fence *f);
558 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
559 struct amdgpu_ib *ibs, struct amdgpu_job *job,
560 struct dma_fence **f);
561 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
562 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
563 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
564 bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring);
565 void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring,
566 struct amdgpu_fence *guilty_fence);
567 void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring,
568 struct amdgpu_fence *guilty_fence);
569 int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring,
570 struct amdgpu_fence *guilty_fence);
571 bool amdgpu_ring_is_reset_type_supported(struct amdgpu_ring *ring,
572 u32 reset_type);
573 #endif
574