1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/clients/drm_client_setup.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_fbdev_ttm.h> 29 #include <drm/drm_gem.h> 30 #include <drm/drm_managed.h> 31 #include <drm/drm_pciids.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/drm_vblank.h> 34 35 #include <linux/cc_platform.h> 36 #include <linux/dynamic_debug.h> 37 #include <linux/module.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/suspend.h> 41 #include <linux/vga_switcheroo.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_amdkfd.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_drv.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_irq.h" 49 #include "amdgpu_psp.h" 50 #include "amdgpu_ras.h" 51 #include "amdgpu_reset.h" 52 #include "amdgpu_sched.h" 53 #include "amdgpu_xgmi.h" 54 #include "amdgpu_userq.h" 55 #include "amdgpu_userq_fence.h" 56 #include "../amdxcp/amdgpu_xcp_drv.h" 57 58 /* 59 * KMS wrapper. 60 * - 3.0.0 - initial driver 61 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 62 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 63 * at the end of IBs. 64 * - 3.3.0 - Add VM support for UVD on supported hardware. 65 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 66 * - 3.5.0 - Add support for new UVD_NO_OP register. 67 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 68 * - 3.7.0 - Add support for VCE clock list packet 69 * - 3.8.0 - Add support raster config init in the kernel 70 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 71 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 72 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 73 * - 3.12.0 - Add query for double offchip LDS buffers 74 * - 3.13.0 - Add PRT support 75 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 76 * - 3.15.0 - Export more gpu info for gfx9 77 * - 3.16.0 - Add reserved vmid support 78 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 79 * - 3.18.0 - Export gpu always on cu bitmap 80 * - 3.19.0 - Add support for UVD MJPEG decode 81 * - 3.20.0 - Add support for local BOs 82 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 83 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 84 * - 3.23.0 - Add query for VRAM lost counter 85 * - 3.24.0 - Add high priority compute support for gfx9 86 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 87 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 88 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 89 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 90 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 91 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 92 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 93 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 94 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 95 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 96 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 97 * - 3.36.0 - Allow reading more status registers on si/cik 98 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 99 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 100 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 101 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 102 * - 3.41.0 - Add video codec query 103 * - 3.42.0 - Add 16bpc fixed point display support 104 * - 3.43.0 - Add device hot plug/unplug support 105 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 106 * - 3.45.0 - Add context ioctl stable pstate interface 107 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 108 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 109 * - 3.48.0 - Add IP discovery version info to HW INFO 110 * - 3.49.0 - Add gang submit into CS IOCTL 111 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 112 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 113 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 114 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 115 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 116 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 117 * 3.53.0 - Support for GFX11 CP GFX shadowing 118 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 119 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 120 * - 3.56.0 - Update IB start address and size alignment for decode and encode 121 * - 3.57.0 - Compute tunneling on GFX10+ 122 * - 3.58.0 - Add GFX12 DCC support 123 * - 3.59.0 - Cleared VRAM 124 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement) 125 * - 3.61.0 - Contains fix for RV/PCO compute queues 126 * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT 127 * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size 128 * - 3.64.0 - Userq IP support query 129 */ 130 #define KMS_DRIVER_MAJOR 3 131 #define KMS_DRIVER_MINOR 64 132 #define KMS_DRIVER_PATCHLEVEL 0 133 134 /* 135 * amdgpu.debug module options. Are all disabled by default 136 */ 137 enum AMDGPU_DEBUG_MASK { 138 AMDGPU_DEBUG_VM = BIT(0), 139 AMDGPU_DEBUG_LARGEBAR = BIT(1), 140 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 141 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 142 AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4), 143 AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5), 144 AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6), 145 AMDGPU_DEBUG_SMU_POOL = BIT(7), 146 AMDGPU_DEBUG_VM_USERPTR = BIT(8), 147 AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9), 148 AMDGPU_DEBUG_ENABLE_CE_CS = BIT(10) 149 }; 150 151 unsigned int amdgpu_vram_limit = UINT_MAX; 152 int amdgpu_vis_vram_limit; 153 int amdgpu_gart_size = -1; /* auto */ 154 int amdgpu_gtt_size = -1; /* auto */ 155 int amdgpu_moverate = -1; /* auto */ 156 int amdgpu_audio = -1; 157 int amdgpu_disp_priority; 158 int amdgpu_hw_i2c; 159 int amdgpu_pcie_gen2 = -1; 160 int amdgpu_msi = -1; 161 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 162 int amdgpu_dpm = -1; 163 int amdgpu_fw_load_type = -1; 164 int amdgpu_aspm = -1; 165 int amdgpu_runtime_pm = -1; 166 uint amdgpu_ip_block_mask = 0xffffffff; 167 int amdgpu_bapm = -1; 168 int amdgpu_deep_color; 169 int amdgpu_vm_size = -1; 170 int amdgpu_vm_fragment_size = -1; 171 int amdgpu_vm_block_size = -1; 172 int amdgpu_vm_fault_stop; 173 int amdgpu_vm_update_mode = -1; 174 int amdgpu_exp_hw_support; 175 int amdgpu_dc = -1; 176 int amdgpu_sched_jobs = 32; 177 int amdgpu_sched_hw_submission = 2; 178 uint amdgpu_pcie_gen_cap; 179 uint amdgpu_pcie_lane_cap; 180 u64 amdgpu_cg_mask = 0xffffffffffffffff; 181 uint amdgpu_pg_mask = 0xffffffff; 182 uint amdgpu_sdma_phase_quantum = 32; 183 char *amdgpu_disable_cu; 184 char *amdgpu_virtual_display; 185 int amdgpu_enforce_isolation = -1; 186 int amdgpu_modeset = -1; 187 188 /* Specifies the default granularity for SVM, used in buffer 189 * migration and restoration of backing memory when handling 190 * recoverable page faults. 191 * 192 * The value is given as log(numPages(buffer)); for a 2 MiB 193 * buffer it computes to be 9 194 */ 195 uint amdgpu_svm_default_granularity = 9; 196 197 /* 198 * OverDrive(bit 14) disabled by default 199 * GFX DCS(bit 19) disabled by default 200 */ 201 uint amdgpu_pp_feature_mask = 0xfff7bfff; 202 uint amdgpu_force_long_training; 203 int amdgpu_lbpw = -1; 204 int amdgpu_compute_multipipe = -1; 205 int amdgpu_gpu_recovery = -1; /* auto */ 206 int amdgpu_emu_mode; 207 uint amdgpu_smu_memory_pool_size; 208 int amdgpu_smu_pptable_id = -1; 209 /* 210 * FBC (bit 0) disabled by default 211 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 212 * - With this, for multiple monitors in sync(e.g. with the same model), 213 * mclk switching will be allowed. And the mclk will be not foced to the 214 * highest. That helps saving some idle power. 215 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 216 * PSR (bit 3) disabled by default 217 * EDP NO POWER SEQUENCING (bit 4) disabled by default 218 */ 219 uint amdgpu_dc_feature_mask = 2; 220 uint amdgpu_dc_debug_mask; 221 uint amdgpu_dc_visual_confirm; 222 int amdgpu_async_gfx_ring = 1; 223 int amdgpu_mcbp = -1; 224 int amdgpu_discovery = -1; 225 int amdgpu_mes; 226 int amdgpu_mes_log_enable = 0; 227 int amdgpu_mes_kiq; 228 int amdgpu_uni_mes = 1; 229 int amdgpu_noretry = -1; 230 int amdgpu_force_asic_type = -1; 231 int amdgpu_tmz = -1; /* auto */ 232 uint amdgpu_freesync_vid_mode; 233 int amdgpu_reset_method = -1; /* auto */ 234 int amdgpu_num_kcq = -1; 235 int amdgpu_smartshift_bias; 236 int amdgpu_use_xgmi_p2p = 1; 237 int amdgpu_vcnfw_log; 238 int amdgpu_sg_display = -1; /* auto */ 239 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 240 int amdgpu_umsch_mm; 241 int amdgpu_seamless = -1; /* auto */ 242 uint amdgpu_debug_mask; 243 int amdgpu_agp = -1; /* auto */ 244 int amdgpu_wbrf = -1; 245 int amdgpu_damage_clips = -1; /* auto */ 246 int amdgpu_umsch_mm_fwlog; 247 int amdgpu_rebar = -1; /* auto */ 248 int amdgpu_user_queue = -1; 249 250 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 251 "DRM_UT_CORE", 252 "DRM_UT_DRIVER", 253 "DRM_UT_KMS", 254 "DRM_UT_PRIME", 255 "DRM_UT_ATOMIC", 256 "DRM_UT_VBL", 257 "DRM_UT_STATE", 258 "DRM_UT_LEASE", 259 "DRM_UT_DP", 260 "DRM_UT_DRMRES"); 261 262 struct amdgpu_mgpu_info mgpu_info = { 263 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 264 }; 265 int amdgpu_ras_enable = -1; 266 uint amdgpu_ras_mask = 0xffffffff; 267 int amdgpu_bad_page_threshold = -1; 268 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 269 .timeout_fatal_disable = false, 270 .period = 0x0, /* default to 0x0 (timeout disable) */ 271 }; 272 273 /** 274 * DOC: vramlimit (int) 275 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 276 */ 277 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 278 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 279 280 /** 281 * DOC: vis_vramlimit (int) 282 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 283 */ 284 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 285 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 286 287 /** 288 * DOC: gartsize (uint) 289 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 290 * The default is -1 (The size depends on asic). 291 */ 292 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 293 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 294 295 /** 296 * DOC: gttsize (int) 297 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 298 * The default is -1 (Use value specified by TTM). 299 * This parameter is deprecated and will be removed in the future. 300 */ 301 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 302 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 303 304 /** 305 * DOC: moverate (int) 306 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 307 */ 308 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 309 module_param_named(moverate, amdgpu_moverate, int, 0600); 310 311 /** 312 * DOC: audio (int) 313 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 314 */ 315 MODULE_PARM_DESC(audio, "HDMI/DP Audio enable for non DC displays (-1 = auto, 0 = disable, 1 = enable)"); 316 module_param_named(audio, amdgpu_audio, int, 0444); 317 318 /** 319 * DOC: disp_priority (int) 320 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 321 */ 322 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 323 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 324 325 /** 326 * DOC: hw_i2c (int) 327 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 328 */ 329 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 330 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 331 332 /** 333 * DOC: pcie_gen2 (int) 334 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 335 */ 336 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 337 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 338 339 /** 340 * DOC: msi (int) 341 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 342 */ 343 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 344 module_param_named(msi, amdgpu_msi, int, 0444); 345 346 /** 347 * DOC: svm_default_granularity (uint) 348 * Used in buffer migration and handling of recoverable page faults 349 */ 350 MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB"); 351 module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644); 352 353 /** 354 * DOC: lockup_timeout (string) 355 * Set GPU scheduler timeout value in ms. 356 * 357 * The format can be [single value] for setting all timeouts at once or 358 * [GFX,Compute,SDMA,Video] to set individual timeouts. 359 * Negative values mean infinity. 360 * 361 * By default(with no lockup_timeout settings), the timeout for all queues is 2000. 362 */ 363 MODULE_PARM_DESC(lockup_timeout, 364 "GPU lockup timeout in ms (default: 2000. 0: keep default value. negative: infinity timeout), format: [single value for all] or [GFX,Compute,SDMA,Video]."); 365 module_param_string(lockup_timeout, amdgpu_lockup_timeout, 366 sizeof(amdgpu_lockup_timeout), 0444); 367 368 /** 369 * DOC: dpm (int) 370 * Override for dynamic power management setting 371 * (0 = disable, 1 = enable) 372 * The default is -1 (auto). 373 */ 374 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 375 module_param_named(dpm, amdgpu_dpm, int, 0444); 376 377 /** 378 * DOC: fw_load_type (int) 379 * Set different firmware loading type for debugging, if supported. 380 * Set to 0 to force direct loading if supported by the ASIC. Set 381 * to -1 to select the default loading mode for the ASIC, as defined 382 * by the driver. The default is -1 (auto). 383 */ 384 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 385 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 386 387 /** 388 * DOC: aspm (int) 389 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 390 */ 391 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 392 module_param_named(aspm, amdgpu_aspm, int, 0444); 393 394 /** 395 * DOC: runpm (int) 396 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 397 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 398 * Setting the value to 0 disables this functionality. 399 * Setting the value to -2 is auto enabled with power down when displays are attached. 400 */ 401 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 402 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 403 404 /** 405 * DOC: ip_block_mask (uint) 406 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 407 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 408 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 409 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 410 */ 411 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 412 module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 413 414 /** 415 * DOC: bapm (int) 416 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 417 * The default -1 (auto, enabled) 418 */ 419 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 420 module_param_named(bapm, amdgpu_bapm, int, 0444); 421 422 /** 423 * DOC: deep_color (int) 424 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 425 */ 426 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 427 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 428 429 /** 430 * DOC: vm_size (int) 431 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 432 */ 433 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 434 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 435 436 /** 437 * DOC: vm_fragment_size (int) 438 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 439 */ 440 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 441 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 442 443 /** 444 * DOC: vm_block_size (int) 445 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 446 */ 447 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 448 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 449 450 /** 451 * DOC: vm_fault_stop (int) 452 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 453 */ 454 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 455 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 456 457 /** 458 * DOC: vm_update_mode (int) 459 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 460 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 461 */ 462 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 463 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 464 465 /** 466 * DOC: exp_hw_support (int) 467 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 468 */ 469 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 470 module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 471 472 /** 473 * DOC: dc (int) 474 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 475 */ 476 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 477 module_param_named(dc, amdgpu_dc, int, 0444); 478 479 /** 480 * DOC: sched_jobs (int) 481 * Override the max number of jobs supported in the sw queue. The default is 32. 482 */ 483 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 484 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 485 486 /** 487 * DOC: sched_hw_submission (int) 488 * Override the max number of HW submissions. The default is 2. 489 */ 490 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 491 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 492 493 /** 494 * DOC: ppfeaturemask (hexint) 495 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 496 * The default is the current set of stable power features. 497 */ 498 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 499 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 500 501 /** 502 * DOC: forcelongtraining (uint) 503 * Force long memory training in resume. 504 * The default is zero, indicates short training in resume. 505 */ 506 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 507 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 508 509 /** 510 * DOC: pcie_gen_cap (uint) 511 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 512 * The default is 0 (automatic for each asic). 513 */ 514 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 515 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 516 517 /** 518 * DOC: pcie_lane_cap (uint) 519 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 520 * The default is 0 (automatic for each asic). 521 */ 522 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 523 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 524 525 /** 526 * DOC: cg_mask (ullong) 527 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 528 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 529 */ 530 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 531 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 532 533 /** 534 * DOC: pg_mask (uint) 535 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 536 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 537 */ 538 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 539 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 540 541 /** 542 * DOC: sdma_phase_quantum (uint) 543 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 544 */ 545 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 546 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 547 548 /** 549 * DOC: disable_cu (charp) 550 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 551 */ 552 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 553 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 554 555 /** 556 * DOC: virtual_display (charp) 557 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 558 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 559 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 560 * device at 26:00.0. The default is NULL. 561 */ 562 MODULE_PARM_DESC(virtual_display, 563 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 564 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 565 566 /** 567 * DOC: lbpw (int) 568 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 569 */ 570 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 571 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 572 573 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 574 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 575 576 /** 577 * DOC: gpu_recovery (int) 578 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 579 */ 580 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 581 module_param_named_unsafe(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 582 583 /** 584 * DOC: emu_mode (int) 585 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 586 */ 587 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 588 module_param_named_unsafe(emu_mode, amdgpu_emu_mode, int, 0444); 589 590 /** 591 * DOC: ras_enable (int) 592 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 593 */ 594 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 595 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 596 597 /** 598 * DOC: ras_mask (uint) 599 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 600 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 601 */ 602 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 603 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 604 605 /** 606 * DOC: timeout_fatal_disable (bool) 607 * Disable Watchdog timeout fatal error event 608 */ 609 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 610 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 611 612 /** 613 * DOC: timeout_period (uint) 614 * Modify the watchdog timeout max_cycles as (1 << period) 615 */ 616 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 617 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 618 619 /** 620 * DOC: si_support (int) 621 * 1 = enabled, 0 = disabled, -1 = default 622 * 623 * SI (Southern Islands) are first generation GCN GPUs, supported by both 624 * drivers: radeon (old) and amdgpu (new). This parameter controls whether 625 * amdgpu should support SI. 626 * By default, SI dedicated GPUs are supported by amdgpu. 627 * Only relevant when CONFIG_DRM_AMDGPU_SI is enabled to build SI support in amdgpu. 628 * See also radeon.si_support which should be disabled when amdgpu.si_support is 629 * enabled, and vice versa. 630 */ 631 int amdgpu_si_support = -1; 632 #ifdef CONFIG_DRM_AMDGPU_SI 633 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled, -1 = default)"); 634 module_param_named(si_support, amdgpu_si_support, int, 0444); 635 #endif 636 637 /** 638 * DOC: cik_support (int) 639 * 1 = enabled, 0 = disabled, -1 = default 640 * 641 * CIK (Sea Islands) are second generation GCN GPUs, supported by both 642 * drivers: radeon (old) and amdgpu (new). This parameter controls whether 643 * amdgpu should support CIK. 644 * By default: 645 * - CIK dedicated GPUs are supported by amdgpu. 646 * - CIK APUs are supported by radeon (except when radeon is not built). 647 * Only relevant when CONFIG_DRM_AMDGPU_CIK is enabled to build CIK support in amdgpu. 648 * See also radeon.cik_support which should be disabled when amdgpu.cik_support is 649 * enabled, and vice versa. 650 */ 651 int amdgpu_cik_support = -1; 652 #ifdef CONFIG_DRM_AMDGPU_CIK 653 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled, -1 = default)"); 654 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 655 #endif 656 657 /** 658 * DOC: smu_memory_pool_size (uint) 659 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 660 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 661 */ 662 MODULE_PARM_DESC(smu_memory_pool_size, 663 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 664 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 665 666 /** 667 * DOC: async_gfx_ring (int) 668 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 669 */ 670 MODULE_PARM_DESC(async_gfx_ring, 671 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 672 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 673 674 /** 675 * DOC: mcbp (int) 676 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 677 */ 678 MODULE_PARM_DESC(mcbp, 679 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 680 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 681 682 /** 683 * DOC: discovery (int) 684 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 685 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 686 */ 687 MODULE_PARM_DESC(discovery, 688 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 689 module_param_named(discovery, amdgpu_discovery, int, 0444); 690 691 /** 692 * DOC: mes (int) 693 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 694 * (0 = disabled (default), 1 = enabled) 695 */ 696 MODULE_PARM_DESC(mes, 697 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 698 module_param_named(mes, amdgpu_mes, int, 0444); 699 700 /** 701 * DOC: mes_log_enable (int) 702 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. 703 * (0 = disabled (default), 1 = enabled) 704 */ 705 MODULE_PARM_DESC(mes_log_enable, 706 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); 707 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); 708 709 /** 710 * DOC: mes_kiq (int) 711 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 712 * (0 = disabled (default), 1 = enabled) 713 */ 714 MODULE_PARM_DESC(mes_kiq, 715 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 716 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 717 718 /** 719 * DOC: uni_mes (int) 720 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. 721 * (0 = disabled (default), 1 = enabled) 722 */ 723 MODULE_PARM_DESC(uni_mes, 724 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)"); 725 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444); 726 727 /** 728 * DOC: noretry (int) 729 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 730 * do not support per-process XNACK this also disables retry page faults. 731 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 732 */ 733 MODULE_PARM_DESC(noretry, 734 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 735 module_param_named(noretry, amdgpu_noretry, int, 0644); 736 737 /** 738 * DOC: force_asic_type (int) 739 * A non negative value used to specify the asic type for all supported GPUs. 740 */ 741 MODULE_PARM_DESC(force_asic_type, 742 "A non negative value used to specify the asic type for all supported GPUs"); 743 module_param_named_unsafe(force_asic_type, amdgpu_force_asic_type, int, 0444); 744 745 /** 746 * DOC: use_xgmi_p2p (int) 747 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 748 */ 749 MODULE_PARM_DESC(use_xgmi_p2p, 750 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 751 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 752 753 754 #ifdef CONFIG_HSA_AMD 755 /** 756 * DOC: sched_policy (int) 757 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 758 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 759 * assigns queues to HQDs. 760 */ 761 int sched_policy = KFD_SCHED_POLICY_HWS; 762 module_param_unsafe(sched_policy, int, 0444); 763 MODULE_PARM_DESC(sched_policy, 764 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 765 766 /** 767 * DOC: hws_max_conc_proc (int) 768 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 769 * number of VMIDs assigned to the HWS, which is also the default. 770 */ 771 int hws_max_conc_proc = -1; 772 module_param(hws_max_conc_proc, int, 0444); 773 MODULE_PARM_DESC(hws_max_conc_proc, 774 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 775 776 /** 777 * DOC: cwsr_enable (int) 778 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 779 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 780 * disables it. 781 */ 782 int cwsr_enable = 1; 783 module_param(cwsr_enable, int, 0444); 784 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 785 786 /** 787 * DOC: max_num_of_queues_per_device (int) 788 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 789 * is 4096. 790 */ 791 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 792 module_param(max_num_of_queues_per_device, int, 0444); 793 MODULE_PARM_DESC(max_num_of_queues_per_device, 794 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 795 796 /** 797 * DOC: send_sigterm (int) 798 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 799 * but just print errors on dmesg. Setting 1 enables sending sigterm. 800 */ 801 int send_sigterm; 802 module_param(send_sigterm, int, 0444); 803 MODULE_PARM_DESC(send_sigterm, 804 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 805 806 /** 807 * DOC: halt_if_hws_hang (int) 808 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 809 * Setting 1 enables halt on hang. 810 */ 811 int halt_if_hws_hang; 812 module_param_unsafe(halt_if_hws_hang, int, 0644); 813 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 814 815 /** 816 * DOC: hws_gws_support(bool) 817 * Assume that HWS supports GWS barriers regardless of what firmware version 818 * check says. Default value: false (rely on MEC2 firmware version check). 819 */ 820 bool hws_gws_support; 821 module_param_unsafe(hws_gws_support, bool, 0444); 822 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 823 824 /** 825 * DOC: queue_preemption_timeout_ms (int) 826 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 827 */ 828 int queue_preemption_timeout_ms = 9000; 829 module_param(queue_preemption_timeout_ms, int, 0644); 830 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 831 832 /** 833 * DOC: debug_evictions(bool) 834 * Enable extra debug messages to help determine the cause of evictions 835 */ 836 bool debug_evictions; 837 module_param(debug_evictions, bool, 0644); 838 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 839 840 /** 841 * DOC: no_system_mem_limit(bool) 842 * Disable system memory limit, to support multiple process shared memory 843 */ 844 bool no_system_mem_limit; 845 module_param(no_system_mem_limit, bool, 0644); 846 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 847 848 /** 849 * DOC: no_queue_eviction_on_vm_fault (int) 850 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 851 */ 852 int amdgpu_no_queue_eviction_on_vm_fault; 853 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 854 module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 855 #endif 856 857 /** 858 * DOC: mtype_local (int) 859 */ 860 int amdgpu_mtype_local; 861 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 862 module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444); 863 864 /** 865 * DOC: pcie_p2p (bool) 866 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 867 */ 868 #ifdef CONFIG_HSA_AMD_P2P 869 bool pcie_p2p = true; 870 module_param(pcie_p2p, bool, 0444); 871 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 872 #endif 873 874 /** 875 * DOC: dcfeaturemask (uint) 876 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 877 * The default is the current set of stable display features. 878 */ 879 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 880 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 881 882 /** 883 * DOC: dcdebugmask (uint) 884 * Display debug options. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 885 */ 886 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 887 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 888 889 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 890 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 891 892 /** 893 * DOC: abmlevel (uint) 894 * Override the default ABM (Adaptive Backlight Management) level used for DC 895 * enabled hardware. Requires DMCU to be supported and loaded. 896 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 897 * default. Values 1-4 control the maximum allowable brightness reduction via 898 * the ABM algorithm, with 1 being the least reduction and 4 being the most 899 * reduction. 900 * 901 * Defaults to -1, or auto. Userspace can only override this level after 902 * boot if it's set to auto. 903 */ 904 int amdgpu_dm_abm_level = -1; 905 MODULE_PARM_DESC(abmlevel, 906 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 907 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 908 909 int amdgpu_backlight = -1; 910 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 911 module_param_named(backlight, amdgpu_backlight, bint, 0444); 912 913 /** 914 * DOC: damageclips (int) 915 * Enable or disable damage clips support. If damage clips support is disabled, 916 * we will force full frame updates, irrespective of what user space sends to 917 * us. 918 * 919 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 920 */ 921 MODULE_PARM_DESC(damageclips, 922 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 923 module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 924 925 /** 926 * DOC: tmz (int) 927 * Trusted Memory Zone (TMZ) is a method to protect data being written 928 * to or read from memory. 929 * 930 * The default value: 0 (off). TODO: change to auto till it is completed. 931 */ 932 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 933 module_param_named(tmz, amdgpu_tmz, int, 0444); 934 935 /** 936 * DOC: freesync_video (uint) 937 * Enable the optimization to adjust front porch timing to achieve seamless 938 * mode change experience when setting a freesync supported mode for which full 939 * modeset is not needed. 940 * 941 * The Display Core will add a set of modes derived from the base FreeSync 942 * video mode into the corresponding connector's mode list based on commonly 943 * used refresh rates and VRR range of the connected display, when users enable 944 * this feature. From the userspace perspective, they can see a seamless mode 945 * change experience when the change between different refresh rates under the 946 * same resolution. Additionally, userspace applications such as Video playback 947 * can read this modeset list and change the refresh rate based on the video 948 * frame rate. Finally, the userspace can also derive an appropriate mode for a 949 * particular refresh rate based on the FreeSync Mode and add it to the 950 * connector's mode list. 951 * 952 * Note: This is an experimental feature. 953 * 954 * The default value: 0 (off). 955 */ 956 MODULE_PARM_DESC( 957 freesync_video, 958 "Adds additional modes via VRR for refresh changes without a full modeset (0 = off (default), 1 = on)"); 959 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 960 961 /** 962 * DOC: reset_method (int) 963 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 964 */ 965 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 966 module_param_named_unsafe(reset_method, amdgpu_reset_method, int, 0644); 967 968 /** 969 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 970 * threshold value of faulty pages detected by RAS ECC, which may 971 * result in the GPU entering bad status when the number of total 972 * faulty pages by ECC exceeds the threshold value. 973 */ 974 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = threshold determined by a formula, 0 < threshold < max records, user-defined threshold)"); 975 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 976 977 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 978 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 979 980 /** 981 * DOC: vcnfw_log (int) 982 * Enable vcnfw log output for debugging, the default is disabled. 983 */ 984 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 985 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 986 987 /** 988 * DOC: sg_display (int) 989 * Disable S/G (scatter/gather) display (i.e., display from system memory). 990 * This option is only relevant on APUs. Set this option to 0 to disable 991 * S/G display if you experience flickering or other issues under memory 992 * pressure and report the issue. 993 */ 994 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 995 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 996 997 /** 998 * DOC: umsch_mm (int) 999 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 1000 * (0 = disabled (default), 1 = enabled) 1001 */ 1002 MODULE_PARM_DESC(umsch_mm, 1003 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 1004 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 1005 1006 /** 1007 * DOC: umsch_mm_fwlog (int) 1008 * Enable umschfw log output for debugging, the default is disabled. 1009 */ 1010 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)"); 1011 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444); 1012 1013 /** 1014 * DOC: smu_pptable_id (int) 1015 * Used to override pptable id. id = 0 use VBIOS pptable. 1016 * id > 0 use the soft pptable with specicfied id. 1017 */ 1018 MODULE_PARM_DESC(smu_pptable_id, 1019 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 1020 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 1021 1022 /** 1023 * DOC: partition_mode (int) 1024 * Used to override the default SPX mode. 1025 */ 1026 MODULE_PARM_DESC( 1027 user_partt_mode, 1028 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 1029 0 = AMDGPU_SPX_PARTITION_MODE, \ 1030 1 = AMDGPU_DPX_PARTITION_MODE, \ 1031 2 = AMDGPU_TPX_PARTITION_MODE, \ 1032 3 = AMDGPU_QPX_PARTITION_MODE, \ 1033 4 = AMDGPU_CPX_PARTITION_MODE)"); 1034 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 1035 1036 1037 /** 1038 * DOC: enforce_isolation (int) 1039 * enforce process isolation between graphics and compute. 1040 * (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader) 1041 */ 1042 module_param_named(enforce_isolation, amdgpu_enforce_isolation, int, 0444); 1043 MODULE_PARM_DESC(enforce_isolation, 1044 "enforce process isolation between graphics and compute. (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader)"); 1045 1046 /** 1047 * DOC: modeset (int) 1048 * Override nomodeset (1 = override, -1 = auto). The default is -1 (auto). 1049 */ 1050 MODULE_PARM_DESC(modeset, "Override nomodeset (1 = enable, -1 = auto)"); 1051 module_param_named(modeset, amdgpu_modeset, int, 0444); 1052 1053 /** 1054 * DOC: seamless (int) 1055 * Seamless boot will keep the image on the screen during the boot process. 1056 */ 1057 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 1058 module_param_named(seamless, amdgpu_seamless, int, 0444); 1059 1060 /** 1061 * DOC: debug_mask (uint) 1062 * Debug options for amdgpu, work as a binary mask with the following options: 1063 * 1064 * - 0x1: Debug VM handling 1065 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1066 * limits the VRAM size reported to ROCm applications to the visible 1067 * size, usually 256MB. 1068 * - 0x4: Disable GPU soft recovery, always do a full reset 1069 * - 0x8: Use VRAM for firmware loading 1070 * - 0x10: Enable ACA based RAS logging 1071 * - 0x20: Enable experimental resets 1072 * - 0x40: Disable ring resets 1073 * - 0x80: Use VRAM for SMU pool 1074 */ 1075 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1076 module_param_named_unsafe(debug_mask, amdgpu_debug_mask, uint, 0444); 1077 1078 /** 1079 * DOC: agp (int) 1080 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1081 * address space for direct access to system memory. Note that these accesses 1082 * are non-snooped, so they are only used for access to uncached memory. 1083 */ 1084 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1085 module_param_named(agp, amdgpu_agp, int, 0444); 1086 1087 /** 1088 * DOC: wbrf (int) 1089 * Enable Wifi RFI interference mitigation feature. 1090 * Due to electrical and mechanical constraints there may be likely interference of 1091 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1092 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1093 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1094 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1095 * P-state transition. However, there may be potential performance impact with this 1096 * feature enabled. 1097 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1098 */ 1099 MODULE_PARM_DESC(wbrf, 1100 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1101 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1102 1103 /** 1104 * DOC: rebar (int) 1105 * Allow BAR resizing. Disable this to prevent the driver from attempting 1106 * to resize the BAR if the GPU supports it and there is available MMIO space. 1107 * Note that this just prevents the driver from resizing the BAR. The BIOS 1108 * may have already resized the BAR at boot time. 1109 */ 1110 MODULE_PARM_DESC(rebar, "Resizable BAR (-1 = auto (default), 0 = disable, 1 = enable)"); 1111 module_param_named(rebar, amdgpu_rebar, int, 0444); 1112 1113 /** 1114 * DOC: user_queue (int) 1115 * Enable user queues on systems that support user queues. Possible values: 1116 * 1117 * - -1 = auto (ASIC specific default) 1118 * - 0 = user queues disabled 1119 * - 1 = user queues enabled and kernel queues enabled (if supported) 1120 * - 2 = user queues enabled and kernel queues disabled 1121 */ 1122 MODULE_PARM_DESC(user_queue, "Enable user queues (-1 = auto (default), 0 = disable, 1 = enable, 2 = enable UQs and disable KQs)"); 1123 module_param_named(user_queue, amdgpu_user_queue, int, 0444); 1124 1125 /* These devices are not supported by amdgpu. 1126 * They are supported by the mach64, r128, radeon drivers 1127 */ 1128 static const u16 amdgpu_unsupported_pciidlist[] = { 1129 /* mach64 */ 1130 0x4354, 1131 0x4358, 1132 0x4554, 1133 0x4742, 1134 0x4744, 1135 0x4749, 1136 0x474C, 1137 0x474D, 1138 0x474E, 1139 0x474F, 1140 0x4750, 1141 0x4751, 1142 0x4752, 1143 0x4753, 1144 0x4754, 1145 0x4755, 1146 0x4756, 1147 0x4757, 1148 0x4758, 1149 0x4759, 1150 0x475A, 1151 0x4C42, 1152 0x4C44, 1153 0x4C47, 1154 0x4C49, 1155 0x4C4D, 1156 0x4C4E, 1157 0x4C50, 1158 0x4C51, 1159 0x4C52, 1160 0x4C53, 1161 0x5654, 1162 0x5655, 1163 0x5656, 1164 /* r128 */ 1165 0x4c45, 1166 0x4c46, 1167 0x4d46, 1168 0x4d4c, 1169 0x5041, 1170 0x5042, 1171 0x5043, 1172 0x5044, 1173 0x5045, 1174 0x5046, 1175 0x5047, 1176 0x5048, 1177 0x5049, 1178 0x504A, 1179 0x504B, 1180 0x504C, 1181 0x504D, 1182 0x504E, 1183 0x504F, 1184 0x5050, 1185 0x5051, 1186 0x5052, 1187 0x5053, 1188 0x5054, 1189 0x5055, 1190 0x5056, 1191 0x5057, 1192 0x5058, 1193 0x5245, 1194 0x5246, 1195 0x5247, 1196 0x524b, 1197 0x524c, 1198 0x534d, 1199 0x5446, 1200 0x544C, 1201 0x5452, 1202 /* radeon */ 1203 0x3150, 1204 0x3151, 1205 0x3152, 1206 0x3154, 1207 0x3155, 1208 0x3E50, 1209 0x3E54, 1210 0x4136, 1211 0x4137, 1212 0x4144, 1213 0x4145, 1214 0x4146, 1215 0x4147, 1216 0x4148, 1217 0x4149, 1218 0x414A, 1219 0x414B, 1220 0x4150, 1221 0x4151, 1222 0x4152, 1223 0x4153, 1224 0x4154, 1225 0x4155, 1226 0x4156, 1227 0x4237, 1228 0x4242, 1229 0x4336, 1230 0x4337, 1231 0x4437, 1232 0x4966, 1233 0x4967, 1234 0x4A48, 1235 0x4A49, 1236 0x4A4A, 1237 0x4A4B, 1238 0x4A4C, 1239 0x4A4D, 1240 0x4A4E, 1241 0x4A4F, 1242 0x4A50, 1243 0x4A54, 1244 0x4B48, 1245 0x4B49, 1246 0x4B4A, 1247 0x4B4B, 1248 0x4B4C, 1249 0x4C57, 1250 0x4C58, 1251 0x4C59, 1252 0x4C5A, 1253 0x4C64, 1254 0x4C66, 1255 0x4C67, 1256 0x4E44, 1257 0x4E45, 1258 0x4E46, 1259 0x4E47, 1260 0x4E48, 1261 0x4E49, 1262 0x4E4A, 1263 0x4E4B, 1264 0x4E50, 1265 0x4E51, 1266 0x4E52, 1267 0x4E53, 1268 0x4E54, 1269 0x4E56, 1270 0x5144, 1271 0x5145, 1272 0x5146, 1273 0x5147, 1274 0x5148, 1275 0x514C, 1276 0x514D, 1277 0x5157, 1278 0x5158, 1279 0x5159, 1280 0x515A, 1281 0x515E, 1282 0x5460, 1283 0x5462, 1284 0x5464, 1285 0x5548, 1286 0x5549, 1287 0x554A, 1288 0x554B, 1289 0x554C, 1290 0x554D, 1291 0x554E, 1292 0x554F, 1293 0x5550, 1294 0x5551, 1295 0x5552, 1296 0x5554, 1297 0x564A, 1298 0x564B, 1299 0x564F, 1300 0x5652, 1301 0x5653, 1302 0x5657, 1303 0x5834, 1304 0x5835, 1305 0x5954, 1306 0x5955, 1307 0x5974, 1308 0x5975, 1309 0x5960, 1310 0x5961, 1311 0x5962, 1312 0x5964, 1313 0x5965, 1314 0x5969, 1315 0x5a41, 1316 0x5a42, 1317 0x5a61, 1318 0x5a62, 1319 0x5b60, 1320 0x5b62, 1321 0x5b63, 1322 0x5b64, 1323 0x5b65, 1324 0x5c61, 1325 0x5c63, 1326 0x5d48, 1327 0x5d49, 1328 0x5d4a, 1329 0x5d4c, 1330 0x5d4d, 1331 0x5d4e, 1332 0x5d4f, 1333 0x5d50, 1334 0x5d52, 1335 0x5d57, 1336 0x5e48, 1337 0x5e4a, 1338 0x5e4b, 1339 0x5e4c, 1340 0x5e4d, 1341 0x5e4f, 1342 0x6700, 1343 0x6701, 1344 0x6702, 1345 0x6703, 1346 0x6704, 1347 0x6705, 1348 0x6706, 1349 0x6707, 1350 0x6708, 1351 0x6709, 1352 0x6718, 1353 0x6719, 1354 0x671c, 1355 0x671d, 1356 0x671f, 1357 0x6720, 1358 0x6721, 1359 0x6722, 1360 0x6723, 1361 0x6724, 1362 0x6725, 1363 0x6726, 1364 0x6727, 1365 0x6728, 1366 0x6729, 1367 0x6738, 1368 0x6739, 1369 0x673e, 1370 0x6740, 1371 0x6741, 1372 0x6742, 1373 0x6743, 1374 0x6744, 1375 0x6745, 1376 0x6746, 1377 0x6747, 1378 0x6748, 1379 0x6749, 1380 0x674A, 1381 0x6750, 1382 0x6751, 1383 0x6758, 1384 0x6759, 1385 0x675B, 1386 0x675D, 1387 0x675F, 1388 0x6760, 1389 0x6761, 1390 0x6762, 1391 0x6763, 1392 0x6764, 1393 0x6765, 1394 0x6766, 1395 0x6767, 1396 0x6768, 1397 0x6770, 1398 0x6771, 1399 0x6772, 1400 0x6778, 1401 0x6779, 1402 0x677B, 1403 0x6840, 1404 0x6841, 1405 0x6842, 1406 0x6843, 1407 0x6849, 1408 0x684C, 1409 0x6850, 1410 0x6858, 1411 0x6859, 1412 0x6880, 1413 0x6888, 1414 0x6889, 1415 0x688A, 1416 0x688C, 1417 0x688D, 1418 0x6898, 1419 0x6899, 1420 0x689b, 1421 0x689c, 1422 0x689d, 1423 0x689e, 1424 0x68a0, 1425 0x68a1, 1426 0x68a8, 1427 0x68a9, 1428 0x68b0, 1429 0x68b8, 1430 0x68b9, 1431 0x68ba, 1432 0x68be, 1433 0x68bf, 1434 0x68c0, 1435 0x68c1, 1436 0x68c7, 1437 0x68c8, 1438 0x68c9, 1439 0x68d8, 1440 0x68d9, 1441 0x68da, 1442 0x68de, 1443 0x68e0, 1444 0x68e1, 1445 0x68e4, 1446 0x68e5, 1447 0x68e8, 1448 0x68e9, 1449 0x68f1, 1450 0x68f2, 1451 0x68f8, 1452 0x68f9, 1453 0x68fa, 1454 0x68fe, 1455 0x7100, 1456 0x7101, 1457 0x7102, 1458 0x7103, 1459 0x7104, 1460 0x7105, 1461 0x7106, 1462 0x7108, 1463 0x7109, 1464 0x710A, 1465 0x710B, 1466 0x710C, 1467 0x710E, 1468 0x710F, 1469 0x7140, 1470 0x7141, 1471 0x7142, 1472 0x7143, 1473 0x7144, 1474 0x7145, 1475 0x7146, 1476 0x7147, 1477 0x7149, 1478 0x714A, 1479 0x714B, 1480 0x714C, 1481 0x714D, 1482 0x714E, 1483 0x714F, 1484 0x7151, 1485 0x7152, 1486 0x7153, 1487 0x715E, 1488 0x715F, 1489 0x7180, 1490 0x7181, 1491 0x7183, 1492 0x7186, 1493 0x7187, 1494 0x7188, 1495 0x718A, 1496 0x718B, 1497 0x718C, 1498 0x718D, 1499 0x718F, 1500 0x7193, 1501 0x7196, 1502 0x719B, 1503 0x719F, 1504 0x71C0, 1505 0x71C1, 1506 0x71C2, 1507 0x71C3, 1508 0x71C4, 1509 0x71C5, 1510 0x71C6, 1511 0x71C7, 1512 0x71CD, 1513 0x71CE, 1514 0x71D2, 1515 0x71D4, 1516 0x71D5, 1517 0x71D6, 1518 0x71DA, 1519 0x71DE, 1520 0x7200, 1521 0x7210, 1522 0x7211, 1523 0x7240, 1524 0x7243, 1525 0x7244, 1526 0x7245, 1527 0x7246, 1528 0x7247, 1529 0x7248, 1530 0x7249, 1531 0x724A, 1532 0x724B, 1533 0x724C, 1534 0x724D, 1535 0x724E, 1536 0x724F, 1537 0x7280, 1538 0x7281, 1539 0x7283, 1540 0x7284, 1541 0x7287, 1542 0x7288, 1543 0x7289, 1544 0x728B, 1545 0x728C, 1546 0x7290, 1547 0x7291, 1548 0x7293, 1549 0x7297, 1550 0x7834, 1551 0x7835, 1552 0x791e, 1553 0x791f, 1554 0x793f, 1555 0x7941, 1556 0x7942, 1557 0x796c, 1558 0x796d, 1559 0x796e, 1560 0x796f, 1561 0x9400, 1562 0x9401, 1563 0x9402, 1564 0x9403, 1565 0x9405, 1566 0x940A, 1567 0x940B, 1568 0x940F, 1569 0x94A0, 1570 0x94A1, 1571 0x94A3, 1572 0x94B1, 1573 0x94B3, 1574 0x94B4, 1575 0x94B5, 1576 0x94B9, 1577 0x9440, 1578 0x9441, 1579 0x9442, 1580 0x9443, 1581 0x9444, 1582 0x9446, 1583 0x944A, 1584 0x944B, 1585 0x944C, 1586 0x944E, 1587 0x9450, 1588 0x9452, 1589 0x9456, 1590 0x945A, 1591 0x945B, 1592 0x945E, 1593 0x9460, 1594 0x9462, 1595 0x946A, 1596 0x946B, 1597 0x947A, 1598 0x947B, 1599 0x9480, 1600 0x9487, 1601 0x9488, 1602 0x9489, 1603 0x948A, 1604 0x948F, 1605 0x9490, 1606 0x9491, 1607 0x9495, 1608 0x9498, 1609 0x949C, 1610 0x949E, 1611 0x949F, 1612 0x94C0, 1613 0x94C1, 1614 0x94C3, 1615 0x94C4, 1616 0x94C5, 1617 0x94C6, 1618 0x94C7, 1619 0x94C8, 1620 0x94C9, 1621 0x94CB, 1622 0x94CC, 1623 0x94CD, 1624 0x9500, 1625 0x9501, 1626 0x9504, 1627 0x9505, 1628 0x9506, 1629 0x9507, 1630 0x9508, 1631 0x9509, 1632 0x950F, 1633 0x9511, 1634 0x9515, 1635 0x9517, 1636 0x9519, 1637 0x9540, 1638 0x9541, 1639 0x9542, 1640 0x954E, 1641 0x954F, 1642 0x9552, 1643 0x9553, 1644 0x9555, 1645 0x9557, 1646 0x955f, 1647 0x9580, 1648 0x9581, 1649 0x9583, 1650 0x9586, 1651 0x9587, 1652 0x9588, 1653 0x9589, 1654 0x958A, 1655 0x958B, 1656 0x958C, 1657 0x958D, 1658 0x958E, 1659 0x958F, 1660 0x9590, 1661 0x9591, 1662 0x9593, 1663 0x9595, 1664 0x9596, 1665 0x9597, 1666 0x9598, 1667 0x9599, 1668 0x959B, 1669 0x95C0, 1670 0x95C2, 1671 0x95C4, 1672 0x95C5, 1673 0x95C6, 1674 0x95C7, 1675 0x95C9, 1676 0x95CC, 1677 0x95CD, 1678 0x95CE, 1679 0x95CF, 1680 0x9610, 1681 0x9611, 1682 0x9612, 1683 0x9613, 1684 0x9614, 1685 0x9615, 1686 0x9616, 1687 0x9640, 1688 0x9641, 1689 0x9642, 1690 0x9643, 1691 0x9644, 1692 0x9645, 1693 0x9647, 1694 0x9648, 1695 0x9649, 1696 0x964a, 1697 0x964b, 1698 0x964c, 1699 0x964e, 1700 0x964f, 1701 0x9710, 1702 0x9711, 1703 0x9712, 1704 0x9713, 1705 0x9714, 1706 0x9715, 1707 0x9802, 1708 0x9803, 1709 0x9804, 1710 0x9805, 1711 0x9806, 1712 0x9807, 1713 0x9808, 1714 0x9809, 1715 0x980A, 1716 0x9900, 1717 0x9901, 1718 0x9903, 1719 0x9904, 1720 0x9905, 1721 0x9906, 1722 0x9907, 1723 0x9908, 1724 0x9909, 1725 0x990A, 1726 0x990B, 1727 0x990C, 1728 0x990D, 1729 0x990E, 1730 0x990F, 1731 0x9910, 1732 0x9913, 1733 0x9917, 1734 0x9918, 1735 0x9919, 1736 0x9990, 1737 0x9991, 1738 0x9992, 1739 0x9993, 1740 0x9994, 1741 0x9995, 1742 0x9996, 1743 0x9997, 1744 0x9998, 1745 0x9999, 1746 0x999A, 1747 0x999B, 1748 0x999C, 1749 0x999D, 1750 0x99A0, 1751 0x99A2, 1752 0x99A4, 1753 /* radeon secondary ids */ 1754 0x3171, 1755 0x3e70, 1756 0x4164, 1757 0x4165, 1758 0x4166, 1759 0x4168, 1760 0x4170, 1761 0x4171, 1762 0x4172, 1763 0x4173, 1764 0x496e, 1765 0x4a69, 1766 0x4a6a, 1767 0x4a6b, 1768 0x4a70, 1769 0x4a74, 1770 0x4b69, 1771 0x4b6b, 1772 0x4b6c, 1773 0x4c6e, 1774 0x4e64, 1775 0x4e65, 1776 0x4e66, 1777 0x4e67, 1778 0x4e68, 1779 0x4e69, 1780 0x4e6a, 1781 0x4e71, 1782 0x4f73, 1783 0x5569, 1784 0x556b, 1785 0x556d, 1786 0x556f, 1787 0x5571, 1788 0x5854, 1789 0x5874, 1790 0x5940, 1791 0x5941, 1792 0x5b70, 1793 0x5b72, 1794 0x5b73, 1795 0x5b74, 1796 0x5b75, 1797 0x5d44, 1798 0x5d45, 1799 0x5d6d, 1800 0x5d6f, 1801 0x5d72, 1802 0x5d77, 1803 0x5e6b, 1804 0x5e6d, 1805 0x7120, 1806 0x7124, 1807 0x7129, 1808 0x712e, 1809 0x712f, 1810 0x7162, 1811 0x7163, 1812 0x7166, 1813 0x7167, 1814 0x7172, 1815 0x7173, 1816 0x71a0, 1817 0x71a1, 1818 0x71a3, 1819 0x71a7, 1820 0x71bb, 1821 0x71e0, 1822 0x71e1, 1823 0x71e2, 1824 0x71e6, 1825 0x71e7, 1826 0x71f2, 1827 0x7269, 1828 0x726b, 1829 0x726e, 1830 0x72a0, 1831 0x72a8, 1832 0x72b1, 1833 0x72b3, 1834 0x793f, 1835 }; 1836 1837 static const struct pci_device_id pciidlist[] = { 1838 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1839 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1840 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1841 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1842 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1843 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1844 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1845 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1846 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1847 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1848 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1849 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1850 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1851 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1852 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1853 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1854 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1855 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1856 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1857 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1858 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1859 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1860 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1861 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1862 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1863 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1864 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1865 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1866 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1867 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1868 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1869 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1870 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1871 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1872 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1873 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1874 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1875 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1876 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1877 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1878 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1879 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1880 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1881 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1882 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1883 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1884 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1885 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1886 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1887 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1888 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1889 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1890 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1891 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1892 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1893 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1894 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1895 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1896 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1897 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1898 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1899 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1900 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1901 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1902 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1903 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1904 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1905 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1906 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1907 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1908 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1909 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1910 /* Kaveri */ 1911 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1912 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1913 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1914 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1915 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1916 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1917 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1918 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1919 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1920 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1921 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1922 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1923 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1924 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1925 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1926 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1927 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1928 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1929 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1930 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1931 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1932 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1933 /* Bonaire */ 1934 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1935 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1936 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1937 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1938 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1939 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1940 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1941 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1942 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1943 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1944 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1945 /* Hawaii */ 1946 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1947 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1948 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1949 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1950 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1951 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1952 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1953 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1954 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1955 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1956 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1957 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1958 /* Kabini */ 1959 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1960 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1961 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1962 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1963 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1964 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1965 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1966 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1967 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1968 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1969 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1970 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1971 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1972 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1973 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1974 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1975 /* mullins */ 1976 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1977 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1978 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1979 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1980 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1981 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1982 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1983 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1984 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1985 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1986 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1987 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1988 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1989 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1990 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1991 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1992 /* topaz */ 1993 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1994 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1995 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1996 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1997 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1998 /* tonga */ 1999 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2000 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2001 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2002 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2003 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2004 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2005 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2006 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2007 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 2008 /* fiji */ 2009 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 2010 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 2011 /* carrizo */ 2012 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2013 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2014 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2015 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2016 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 2017 /* stoney */ 2018 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 2019 /* Polaris11 */ 2020 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2021 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2022 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2023 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2024 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2025 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2026 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2027 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2028 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2029 /* Polaris10 */ 2030 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2031 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2032 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2033 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2034 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2035 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2036 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2037 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2038 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2039 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2040 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2041 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2042 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2043 /* Polaris12 */ 2044 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2045 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2046 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2047 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2048 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2049 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2050 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2051 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2052 /* VEGAM */ 2053 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2054 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2055 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2056 /* Vega 10 */ 2057 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2058 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2059 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2060 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2061 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2062 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2063 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2064 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2065 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2066 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2067 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2068 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2069 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2070 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2071 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2072 /* Vega 12 */ 2073 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2074 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2075 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2076 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2077 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2078 /* Vega 20 */ 2079 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2080 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2081 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2082 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2083 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2084 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2085 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2086 /* Raven */ 2087 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2088 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2089 /* Arcturus */ 2090 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2091 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2092 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2093 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2094 /* Navi10 */ 2095 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2096 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2097 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2098 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2099 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2100 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2101 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2102 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2103 /* Navi14 */ 2104 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2105 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2106 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2107 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2108 2109 /* Renoir */ 2110 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2111 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2112 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2113 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2114 2115 /* Navi12 */ 2116 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2117 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2118 2119 /* Sienna_Cichlid */ 2120 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2121 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2122 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2123 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2124 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2125 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2126 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2127 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2128 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2129 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2130 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2131 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2132 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2133 2134 /* Yellow Carp */ 2135 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2136 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2137 2138 /* Navy_Flounder */ 2139 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2140 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2141 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2142 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2143 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2144 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2145 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2146 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2147 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2148 2149 /* DIMGREY_CAVEFISH */ 2150 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2151 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2152 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2153 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2154 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2155 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2156 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2157 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2158 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2159 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2160 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2161 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2162 2163 /* Aldebaran */ 2164 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2165 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2166 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2167 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2168 2169 /* CYAN_SKILLFISH */ 2170 {0x1002, 0x13DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2171 {0x1002, 0x13F9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2172 {0x1002, 0x13FA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2173 {0x1002, 0x13FB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2174 {0x1002, 0x13FC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2175 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2176 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2177 2178 /* BEIGE_GOBY */ 2179 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2180 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2181 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2182 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2183 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2184 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2185 2186 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2187 .class = PCI_CLASS_DISPLAY_VGA << 8, 2188 .class_mask = 0xffffff, 2189 .driver_data = CHIP_IP_DISCOVERY }, 2190 2191 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2192 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2193 .class_mask = 0xffffff, 2194 .driver_data = CHIP_IP_DISCOVERY }, 2195 2196 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2197 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2198 .class_mask = 0xffffff, 2199 .driver_data = CHIP_IP_DISCOVERY }, 2200 2201 {0, 0, 0} 2202 }; 2203 2204 MODULE_DEVICE_TABLE(pci, pciidlist); 2205 2206 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2207 /* differentiate between P10 and P11 asics with the same DID */ 2208 {0x67FF, 0xE3, CHIP_POLARIS10}, 2209 {0x67FF, 0xE7, CHIP_POLARIS10}, 2210 {0x67FF, 0xF3, CHIP_POLARIS10}, 2211 {0x67FF, 0xF7, CHIP_POLARIS10}, 2212 }; 2213 2214 static const struct drm_driver amdgpu_kms_driver; 2215 2216 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2217 { 2218 struct pci_dev *p = NULL; 2219 int i; 2220 2221 /* 0 - GPU 2222 * 1 - audio 2223 * 2 - USB 2224 * 3 - UCSI 2225 */ 2226 for (i = 1; i < 4; i++) { 2227 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2228 adev->pdev->bus->number, i); 2229 if (p) { 2230 pm_runtime_get_sync(&p->dev); 2231 pm_runtime_put_autosuspend(&p->dev); 2232 pci_dev_put(p); 2233 } 2234 } 2235 } 2236 2237 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2238 { 2239 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2240 pr_info("debug: VM handling debug enabled\n"); 2241 adev->debug_vm = true; 2242 } 2243 2244 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2245 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2246 adev->debug_largebar = true; 2247 } 2248 2249 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2250 pr_info("debug: soft reset for GPU recovery disabled\n"); 2251 adev->debug_disable_soft_recovery = true; 2252 } 2253 2254 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2255 pr_info("debug: place fw in vram for frontdoor loading\n"); 2256 adev->debug_use_vram_fw_buf = true; 2257 } 2258 2259 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) { 2260 pr_info("debug: enable RAS ACA\n"); 2261 adev->debug_enable_ras_aca = true; 2262 } 2263 2264 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) { 2265 pr_info("debug: enable experimental reset features\n"); 2266 adev->debug_exp_resets = true; 2267 } 2268 2269 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_RING_RESET) { 2270 pr_info("debug: ring reset disabled\n"); 2271 adev->debug_disable_gpu_ring_reset = true; 2272 } 2273 if (amdgpu_debug_mask & AMDGPU_DEBUG_SMU_POOL) { 2274 pr_info("debug: use vram for smu pool\n"); 2275 adev->pm.smu_debug_mask |= SMU_DEBUG_POOL_USE_VRAM; 2276 } 2277 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM_USERPTR) { 2278 pr_info("debug: VM mode debug for userptr is enabled\n"); 2279 adev->debug_vm_userptr = true; 2280 } 2281 2282 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_RAS_CE_LOG) { 2283 pr_info("debug: disable kernel logs of correctable errors\n"); 2284 adev->debug_disable_ce_logs = true; 2285 } 2286 2287 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_CE_CS) { 2288 pr_info("debug: allowing command submission to CE engine\n"); 2289 adev->debug_enable_ce_cs = true; 2290 } 2291 } 2292 2293 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2294 { 2295 int i; 2296 2297 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2298 if (pdev->device == asic_type_quirks[i].device && 2299 pdev->revision == asic_type_quirks[i].revision) { 2300 flags &= ~AMD_ASIC_MASK; 2301 flags |= asic_type_quirks[i].type; 2302 break; 2303 } 2304 } 2305 2306 return flags; 2307 } 2308 2309 static bool amdgpu_support_enabled(struct device *dev, 2310 const enum amd_asic_type family) 2311 { 2312 const char *gen; 2313 const char *param; 2314 int module_param = -1; 2315 bool radeon_support_built = IS_ENABLED(CONFIG_DRM_RADEON); 2316 bool amdgpu_support_built = false; 2317 bool support_by_default = false; 2318 2319 switch (family) { 2320 case CHIP_TAHITI: 2321 case CHIP_PITCAIRN: 2322 case CHIP_VERDE: 2323 case CHIP_OLAND: 2324 case CHIP_HAINAN: 2325 gen = "SI"; 2326 param = "si_support"; 2327 module_param = amdgpu_si_support; 2328 amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_SI); 2329 support_by_default = true; 2330 break; 2331 2332 case CHIP_BONAIRE: 2333 case CHIP_HAWAII: 2334 support_by_default = true; 2335 fallthrough; 2336 case CHIP_KAVERI: 2337 case CHIP_KABINI: 2338 case CHIP_MULLINS: 2339 gen = "CIK"; 2340 param = "cik_support"; 2341 module_param = amdgpu_cik_support; 2342 amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_CIK); 2343 break; 2344 2345 default: 2346 /* All other chips are supported by amdgpu only */ 2347 return true; 2348 } 2349 2350 if (!amdgpu_support_built) { 2351 dev_info(dev, "amdgpu built without %s support\n", gen); 2352 return false; 2353 } 2354 2355 if ((module_param == -1 && (support_by_default || !radeon_support_built)) || 2356 module_param == 1) { 2357 if (radeon_support_built) 2358 dev_info(dev, "%s support provided by amdgpu.\n" 2359 "Use radeon.%s=1 amdgpu.%s=0 to override.\n", 2360 gen, param, param); 2361 2362 return true; 2363 } 2364 2365 if (radeon_support_built) 2366 dev_info(dev, "%s support provided by radeon.\n" 2367 "Use radeon.%s=0 amdgpu.%s=1 to override.\n", 2368 gen, param, param); 2369 else if (module_param == 0) 2370 dev_info(dev, "%s support disabled by module param\n", gen); 2371 2372 return false; 2373 } 2374 2375 static int amdgpu_pci_probe(struct pci_dev *pdev, 2376 const struct pci_device_id *ent) 2377 { 2378 struct drm_device *ddev; 2379 struct amdgpu_device *adev; 2380 unsigned long flags = ent->driver_data; 2381 int ret, retry = 0, i; 2382 bool supports_atomic = false; 2383 2384 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA || 2385 (pdev->class >> 8) == PCI_CLASS_DISPLAY_OTHER) { 2386 if (drm_firmware_drivers_only() && amdgpu_modeset == -1) 2387 return -EINVAL; 2388 } 2389 2390 /* skip devices which are owned by radeon */ 2391 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2392 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2393 return -ENODEV; 2394 } 2395 2396 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2397 amdgpu_aspm = 0; 2398 2399 if (amdgpu_virtual_display || 2400 amdgpu_device_asic_has_dc_support(pdev, flags & AMD_ASIC_MASK)) 2401 supports_atomic = true; 2402 2403 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2404 DRM_INFO("This hardware requires experimental hardware support.\n" 2405 "See modparam exp_hw_support\n"); 2406 return -ENODEV; 2407 } 2408 2409 flags = amdgpu_fix_asic_type(pdev, flags); 2410 2411 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2412 * however, SME requires an indirect IOMMU mapping because the encryption 2413 * bit is beyond the DMA mask of the chip. 2414 */ 2415 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2416 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2417 dev_info(&pdev->dev, 2418 "SME is not compatible with RAVEN\n"); 2419 return -ENOTSUPP; 2420 } 2421 2422 if (!amdgpu_support_enabled(&pdev->dev, flags & AMD_ASIC_MASK)) 2423 return -ENODEV; 2424 2425 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2426 if (IS_ERR(adev)) 2427 return PTR_ERR(adev); 2428 2429 adev->dev = &pdev->dev; 2430 adev->pdev = pdev; 2431 ddev = adev_to_drm(adev); 2432 2433 if (!supports_atomic) 2434 ddev->driver_features &= ~DRIVER_ATOMIC; 2435 2436 ret = pci_enable_device(pdev); 2437 if (ret) 2438 return ret; 2439 2440 pci_set_drvdata(pdev, ddev); 2441 2442 amdgpu_init_debug_options(adev); 2443 2444 ret = amdgpu_driver_load_kms(adev, flags); 2445 if (ret) 2446 goto err_pci; 2447 2448 retry_init: 2449 ret = drm_dev_register(ddev, flags); 2450 if (ret == -EAGAIN && ++retry <= 3) { 2451 DRM_INFO("retry init %d\n", retry); 2452 /* Don't request EX mode too frequently which is attacking */ 2453 msleep(5000); 2454 goto retry_init; 2455 } else if (ret) { 2456 goto err_pci; 2457 } 2458 2459 ret = amdgpu_xcp_dev_register(adev, ent); 2460 if (ret) 2461 goto err_pci; 2462 2463 ret = amdgpu_amdkfd_drm_client_create(adev); 2464 if (ret) 2465 goto err_pci; 2466 2467 /* 2468 * 1. don't init fbdev on hw without DCE 2469 * 2. don't init fbdev if there are no connectors 2470 */ 2471 if (adev->mode_info.mode_config_initialized && 2472 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2473 const struct drm_format_info *format; 2474 2475 /* select 8 bpp console on low vram cards */ 2476 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2477 format = drm_format_info(DRM_FORMAT_C8); 2478 else 2479 format = NULL; 2480 2481 drm_client_setup(adev_to_drm(adev), format); 2482 } 2483 2484 ret = amdgpu_debugfs_init(adev); 2485 if (ret) 2486 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2487 2488 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2489 /* only need to skip on ATPX */ 2490 if (amdgpu_device_supports_px(adev)) 2491 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2492 /* we want direct complete for BOCO */ 2493 if (amdgpu_device_supports_boco(adev)) 2494 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2495 DPM_FLAG_SMART_SUSPEND | 2496 DPM_FLAG_MAY_SKIP_RESUME); 2497 pm_runtime_use_autosuspend(ddev->dev); 2498 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2499 2500 pm_runtime_allow(ddev->dev); 2501 2502 pm_runtime_put_autosuspend(ddev->dev); 2503 2504 pci_wake_from_d3(pdev, TRUE); 2505 2506 /* 2507 * For runpm implemented via BACO, PMFW will handle the 2508 * timing for BACO in and out: 2509 * - put ASIC into BACO state only when both video and 2510 * audio functions are in D3 state. 2511 * - pull ASIC out of BACO state when either video or 2512 * audio function is in D0 state. 2513 * Also, at startup, PMFW assumes both functions are in 2514 * D0 state. 2515 * 2516 * So if snd driver was loaded prior to amdgpu driver 2517 * and audio function was put into D3 state, there will 2518 * be no PMFW-aware D-state transition(D0->D3) on runpm 2519 * suspend. Thus the BACO will be not correctly kicked in. 2520 * 2521 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2522 * into D0 state. Then there will be a PMFW-aware D-state 2523 * transition(D0->D3) on runpm suspend. 2524 */ 2525 if (amdgpu_device_supports_baco(adev) && 2526 !(adev->flags & AMD_IS_APU) && 2527 adev->asic_type >= CHIP_NAVI10) 2528 amdgpu_get_secondary_funcs(adev); 2529 } 2530 2531 return 0; 2532 2533 err_pci: 2534 pci_disable_device(pdev); 2535 return ret; 2536 } 2537 2538 static void 2539 amdgpu_pci_remove(struct pci_dev *pdev) 2540 { 2541 struct drm_device *dev = pci_get_drvdata(pdev); 2542 struct amdgpu_device *adev = drm_to_adev(dev); 2543 2544 amdgpu_ras_eeprom_check_and_recover(adev); 2545 amdgpu_xcp_dev_unplug(adev); 2546 amdgpu_gmc_prepare_nps_mode_change(adev); 2547 drm_dev_unplug(dev); 2548 2549 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2550 pm_runtime_get_sync(dev->dev); 2551 pm_runtime_forbid(dev->dev); 2552 } 2553 2554 amdgpu_driver_unload_kms(dev); 2555 2556 /* 2557 * Flush any in flight DMA operations from device. 2558 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2559 * StatusTransactions Pending bit. 2560 */ 2561 pci_disable_device(pdev); 2562 pci_wait_for_pending_transaction(pdev); 2563 } 2564 2565 static void 2566 amdgpu_pci_shutdown(struct pci_dev *pdev) 2567 { 2568 struct drm_device *dev = pci_get_drvdata(pdev); 2569 struct amdgpu_device *adev = drm_to_adev(dev); 2570 2571 if (amdgpu_ras_intr_triggered()) 2572 return; 2573 2574 /* device maybe not resumed here, return immediately in this case */ 2575 if (adev->in_s4 && adev->in_suspend) 2576 return; 2577 2578 /* if we are running in a VM, make sure the device 2579 * torn down properly on reboot/shutdown. 2580 * unfortunately we can't detect certain 2581 * hypervisors so just do this all the time. 2582 */ 2583 if (!amdgpu_passthrough(adev)) 2584 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2585 amdgpu_device_prepare(dev); 2586 amdgpu_device_suspend(dev, true); 2587 adev->mp1_state = PP_MP1_STATE_NONE; 2588 } 2589 2590 static int amdgpu_pmops_prepare(struct device *dev) 2591 { 2592 struct drm_device *drm_dev = dev_get_drvdata(dev); 2593 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2594 2595 /* device maybe not resumed here, return immediately in this case */ 2596 if (adev->in_s4 && adev->in_suspend) 2597 return 0; 2598 2599 /* Return a positive number here so 2600 * DPM_FLAG_SMART_SUSPEND works properly 2601 */ 2602 if (amdgpu_device_supports_boco(adev) && pm_runtime_suspended(dev)) 2603 return 1; 2604 2605 /* if we will not support s3 or s2i for the device 2606 * then skip suspend 2607 */ 2608 if (!amdgpu_acpi_is_s0ix_active(adev) && 2609 !amdgpu_acpi_is_s3_active(adev)) 2610 return 1; 2611 2612 return amdgpu_device_prepare(drm_dev); 2613 } 2614 2615 static void amdgpu_pmops_complete(struct device *dev) 2616 { 2617 amdgpu_device_complete(dev_get_drvdata(dev)); 2618 } 2619 2620 static int amdgpu_pmops_suspend(struct device *dev) 2621 { 2622 struct drm_device *drm_dev = dev_get_drvdata(dev); 2623 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2624 2625 if (amdgpu_acpi_is_s0ix_active(adev)) 2626 adev->in_s0ix = true; 2627 else if (amdgpu_acpi_is_s3_active(adev)) 2628 adev->in_s3 = true; 2629 if (!adev->in_s0ix && !adev->in_s3) { 2630 #if IS_ENABLED(CONFIG_SUSPEND) 2631 /* don't allow going deep first time followed by s2idle the next time */ 2632 if (adev->last_suspend_state != PM_SUSPEND_ON && 2633 adev->last_suspend_state != pm_suspend_target_state) { 2634 drm_err_once(drm_dev, "Unsupported suspend state %d\n", 2635 pm_suspend_target_state); 2636 return -EINVAL; 2637 } 2638 #endif 2639 return 0; 2640 } 2641 2642 #if IS_ENABLED(CONFIG_SUSPEND) 2643 /* cache the state last used for suspend */ 2644 adev->last_suspend_state = pm_suspend_target_state; 2645 #endif 2646 2647 return amdgpu_device_suspend(drm_dev, true); 2648 } 2649 2650 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2651 { 2652 struct drm_device *drm_dev = dev_get_drvdata(dev); 2653 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2654 int r; 2655 2656 if (amdgpu_acpi_should_gpu_reset(adev)) { 2657 amdgpu_device_lock_reset_domain(adev->reset_domain); 2658 r = amdgpu_asic_reset(adev); 2659 amdgpu_device_unlock_reset_domain(adev->reset_domain); 2660 return r; 2661 } 2662 2663 return 0; 2664 } 2665 2666 static int amdgpu_pmops_resume(struct device *dev) 2667 { 2668 struct drm_device *drm_dev = dev_get_drvdata(dev); 2669 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2670 int r; 2671 2672 if (!adev->in_s0ix && !adev->in_s3) 2673 return 0; 2674 2675 /* Avoids registers access if device is physically gone */ 2676 if (!pci_device_is_present(adev->pdev)) 2677 adev->no_hw_access = true; 2678 2679 r = amdgpu_device_resume(drm_dev, true); 2680 if (amdgpu_acpi_is_s0ix_active(adev)) 2681 adev->in_s0ix = false; 2682 else 2683 adev->in_s3 = false; 2684 return r; 2685 } 2686 2687 static int amdgpu_pmops_freeze(struct device *dev) 2688 { 2689 struct drm_device *drm_dev = dev_get_drvdata(dev); 2690 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2691 int r; 2692 2693 r = amdgpu_device_suspend(drm_dev, true); 2694 if (r) 2695 return r; 2696 2697 if (amdgpu_acpi_should_gpu_reset(adev)) 2698 return amdgpu_asic_reset(adev); 2699 return 0; 2700 } 2701 2702 static int amdgpu_pmops_thaw(struct device *dev) 2703 { 2704 struct drm_device *drm_dev = dev_get_drvdata(dev); 2705 2706 /* do not resume device if it's normal hibernation */ 2707 if (!pm_hibernate_is_recovering() && !pm_hibernation_mode_is_suspend()) 2708 return 0; 2709 2710 return amdgpu_device_resume(drm_dev, true); 2711 } 2712 2713 static int amdgpu_pmops_poweroff(struct device *dev) 2714 { 2715 struct drm_device *drm_dev = dev_get_drvdata(dev); 2716 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2717 2718 /* device maybe not resumed here, return immediately in this case */ 2719 if (adev->in_s4 && adev->in_suspend) 2720 return 0; 2721 2722 return amdgpu_device_suspend(drm_dev, true); 2723 } 2724 2725 static int amdgpu_pmops_restore(struct device *dev) 2726 { 2727 struct drm_device *drm_dev = dev_get_drvdata(dev); 2728 2729 return amdgpu_device_resume(drm_dev, true); 2730 } 2731 2732 static int amdgpu_runtime_idle_check_display(struct device *dev) 2733 { 2734 struct pci_dev *pdev = to_pci_dev(dev); 2735 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2736 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2737 2738 if (adev->mode_info.num_crtc) { 2739 struct drm_connector *list_connector; 2740 struct drm_connector_list_iter iter; 2741 int ret = 0; 2742 2743 if (amdgpu_runtime_pm != -2) { 2744 /* XXX: Return busy if any displays are connected to avoid 2745 * possible display wakeups after runtime resume due to 2746 * hotplug events in case any displays were connected while 2747 * the GPU was in suspend. Remove this once that is fixed. 2748 */ 2749 mutex_lock(&drm_dev->mode_config.mutex); 2750 drm_connector_list_iter_begin(drm_dev, &iter); 2751 drm_for_each_connector_iter(list_connector, &iter) { 2752 if (list_connector->status == connector_status_connected) { 2753 ret = -EBUSY; 2754 break; 2755 } 2756 } 2757 drm_connector_list_iter_end(&iter); 2758 mutex_unlock(&drm_dev->mode_config.mutex); 2759 2760 if (ret) 2761 return ret; 2762 } 2763 2764 if (adev->dc_enabled) { 2765 struct drm_crtc *crtc; 2766 2767 drm_for_each_crtc(crtc, drm_dev) { 2768 drm_modeset_lock(&crtc->mutex, NULL); 2769 if (crtc->state->active) 2770 ret = -EBUSY; 2771 drm_modeset_unlock(&crtc->mutex); 2772 if (ret < 0) 2773 break; 2774 } 2775 } else { 2776 mutex_lock(&drm_dev->mode_config.mutex); 2777 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2778 2779 drm_connector_list_iter_begin(drm_dev, &iter); 2780 drm_for_each_connector_iter(list_connector, &iter) { 2781 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2782 ret = -EBUSY; 2783 break; 2784 } 2785 } 2786 2787 drm_connector_list_iter_end(&iter); 2788 2789 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2790 mutex_unlock(&drm_dev->mode_config.mutex); 2791 } 2792 if (ret) 2793 return ret; 2794 } 2795 2796 return 0; 2797 } 2798 2799 static int amdgpu_runtime_idle_check_userq(struct device *dev) 2800 { 2801 struct pci_dev *pdev = to_pci_dev(dev); 2802 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2803 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2804 2805 return xa_empty(&adev->userq_doorbell_xa) ? 0 : -EBUSY; 2806 } 2807 2808 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2809 { 2810 struct pci_dev *pdev = to_pci_dev(dev); 2811 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2812 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2813 int ret, i; 2814 2815 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2816 pm_runtime_forbid(dev); 2817 return -EBUSY; 2818 } 2819 2820 ret = amdgpu_runtime_idle_check_display(dev); 2821 if (ret) 2822 return ret; 2823 ret = amdgpu_runtime_idle_check_userq(dev); 2824 if (ret) 2825 return ret; 2826 2827 /* wait for all rings to drain before suspending */ 2828 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2829 struct amdgpu_ring *ring = adev->rings[i]; 2830 2831 if (ring && ring->sched.ready) { 2832 ret = amdgpu_fence_wait_empty(ring); 2833 if (ret) 2834 return -EBUSY; 2835 } 2836 } 2837 2838 adev->in_runpm = true; 2839 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2840 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2841 2842 /* 2843 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2844 * proper cleanups and put itself into a state ready for PNP. That 2845 * can address some random resuming failure observed on BOCO capable 2846 * platforms. 2847 * TODO: this may be also needed for PX capable platform. 2848 */ 2849 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2850 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2851 2852 ret = amdgpu_device_prepare(drm_dev); 2853 if (ret) 2854 return ret; 2855 ret = amdgpu_device_suspend(drm_dev, false); 2856 if (ret) { 2857 adev->in_runpm = false; 2858 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2859 adev->mp1_state = PP_MP1_STATE_NONE; 2860 return ret; 2861 } 2862 2863 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2864 adev->mp1_state = PP_MP1_STATE_NONE; 2865 2866 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2867 /* Only need to handle PCI state in the driver for ATPX 2868 * PCI core handles it for _PR3. 2869 */ 2870 amdgpu_device_cache_pci_state(pdev); 2871 pci_disable_device(pdev); 2872 pci_ignore_hotplug(pdev); 2873 pci_set_power_state(pdev, PCI_D3cold); 2874 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2875 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2876 /* nothing to do */ 2877 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2878 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2879 amdgpu_device_baco_enter(adev); 2880 } 2881 2882 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2883 2884 return 0; 2885 } 2886 2887 static int amdgpu_pmops_runtime_resume(struct device *dev) 2888 { 2889 struct pci_dev *pdev = to_pci_dev(dev); 2890 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2891 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2892 int ret; 2893 2894 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2895 return -EINVAL; 2896 2897 /* Avoids registers access if device is physically gone */ 2898 if (!pci_device_is_present(adev->pdev)) 2899 adev->no_hw_access = true; 2900 2901 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2902 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2903 2904 /* Only need to handle PCI state in the driver for ATPX 2905 * PCI core handles it for _PR3. 2906 */ 2907 pci_set_power_state(pdev, PCI_D0); 2908 amdgpu_device_load_pci_state(pdev); 2909 ret = pci_enable_device(pdev); 2910 if (ret) 2911 return ret; 2912 pci_set_master(pdev); 2913 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2914 /* Only need to handle PCI state in the driver for ATPX 2915 * PCI core handles it for _PR3. 2916 */ 2917 pci_set_master(pdev); 2918 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2919 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2920 amdgpu_device_baco_exit(adev); 2921 } 2922 ret = amdgpu_device_resume(drm_dev, false); 2923 if (ret) { 2924 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2925 pci_disable_device(pdev); 2926 return ret; 2927 } 2928 2929 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2930 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2931 adev->in_runpm = false; 2932 return 0; 2933 } 2934 2935 static int amdgpu_pmops_runtime_idle(struct device *dev) 2936 { 2937 struct drm_device *drm_dev = dev_get_drvdata(dev); 2938 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2939 int ret; 2940 2941 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2942 pm_runtime_forbid(dev); 2943 return -EBUSY; 2944 } 2945 2946 ret = amdgpu_runtime_idle_check_display(dev); 2947 if (ret) 2948 goto done; 2949 2950 ret = amdgpu_runtime_idle_check_userq(dev); 2951 done: 2952 pm_runtime_autosuspend(dev); 2953 return ret; 2954 } 2955 2956 static int amdgpu_drm_release(struct inode *inode, struct file *filp) 2957 { 2958 struct drm_file *file_priv = filp->private_data; 2959 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2960 struct drm_device *dev = file_priv->minor->dev; 2961 int idx; 2962 2963 if (fpriv && drm_dev_enter(dev, &idx)) { 2964 fpriv->evf_mgr.fd_closing = true; 2965 amdgpu_eviction_fence_destroy(&fpriv->evf_mgr); 2966 amdgpu_userq_mgr_fini(&fpriv->userq_mgr); 2967 drm_dev_exit(idx); 2968 } 2969 2970 return drm_release(inode, filp); 2971 } 2972 2973 long amdgpu_drm_ioctl(struct file *filp, 2974 unsigned int cmd, unsigned long arg) 2975 { 2976 struct drm_file *file_priv = filp->private_data; 2977 struct drm_device *dev; 2978 long ret; 2979 2980 dev = file_priv->minor->dev; 2981 ret = pm_runtime_get_sync(dev->dev); 2982 if (ret < 0) 2983 goto out; 2984 2985 ret = drm_ioctl(filp, cmd, arg); 2986 2987 out: 2988 pm_runtime_put_autosuspend(dev->dev); 2989 return ret; 2990 } 2991 2992 static const struct dev_pm_ops amdgpu_pm_ops = { 2993 .prepare = pm_sleep_ptr(amdgpu_pmops_prepare), 2994 .complete = pm_sleep_ptr(amdgpu_pmops_complete), 2995 .suspend = pm_sleep_ptr(amdgpu_pmops_suspend), 2996 .suspend_noirq = pm_sleep_ptr(amdgpu_pmops_suspend_noirq), 2997 .resume = pm_sleep_ptr(amdgpu_pmops_resume), 2998 .freeze = pm_sleep_ptr(amdgpu_pmops_freeze), 2999 .thaw = pm_sleep_ptr(amdgpu_pmops_thaw), 3000 .poweroff = pm_sleep_ptr(amdgpu_pmops_poweroff), 3001 .restore = pm_sleep_ptr(amdgpu_pmops_restore), 3002 .runtime_suspend = amdgpu_pmops_runtime_suspend, 3003 .runtime_resume = amdgpu_pmops_runtime_resume, 3004 .runtime_idle = amdgpu_pmops_runtime_idle, 3005 }; 3006 3007 static int amdgpu_flush(struct file *f, fl_owner_t id) 3008 { 3009 struct drm_file *file_priv = f->private_data; 3010 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 3011 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 3012 3013 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 3014 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 3015 3016 return timeout >= 0 ? 0 : timeout; 3017 } 3018 3019 static const struct file_operations amdgpu_driver_kms_fops = { 3020 .owner = THIS_MODULE, 3021 .open = drm_open, 3022 .flush = amdgpu_flush, 3023 .release = amdgpu_drm_release, 3024 .unlocked_ioctl = amdgpu_drm_ioctl, 3025 .mmap = drm_gem_mmap, 3026 .poll = drm_poll, 3027 .read = drm_read, 3028 #ifdef CONFIG_COMPAT 3029 .compat_ioctl = amdgpu_kms_compat_ioctl, 3030 #endif 3031 #ifdef CONFIG_PROC_FS 3032 .show_fdinfo = drm_show_fdinfo, 3033 #endif 3034 .fop_flags = FOP_UNSIGNED_OFFSET, 3035 }; 3036 3037 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 3038 { 3039 struct drm_file *file; 3040 3041 if (!filp) 3042 return -EINVAL; 3043 3044 if (filp->f_op != &amdgpu_driver_kms_fops) 3045 return -EINVAL; 3046 3047 file = filp->private_data; 3048 *fpriv = file->driver_priv; 3049 return 0; 3050 } 3051 3052 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 3053 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3054 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3055 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3056 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 3057 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3058 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3059 /* KMS */ 3060 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3061 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3062 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3063 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3064 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3065 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3066 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3067 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3068 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3069 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3070 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ, amdgpu_userq_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3071 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3072 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3073 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3074 }; 3075 3076 static const struct drm_driver amdgpu_kms_driver = { 3077 .driver_features = 3078 DRIVER_ATOMIC | 3079 DRIVER_GEM | 3080 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 3081 DRIVER_SYNCOBJ_TIMELINE, 3082 .open = amdgpu_driver_open_kms, 3083 .postclose = amdgpu_driver_postclose_kms, 3084 .ioctls = amdgpu_ioctls_kms, 3085 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 3086 .dumb_create = amdgpu_mode_dumb_create, 3087 .dumb_map_offset = amdgpu_mode_dumb_mmap, 3088 DRM_FBDEV_TTM_DRIVER_OPS, 3089 .fops = &amdgpu_driver_kms_fops, 3090 .release = &amdgpu_driver_release_kms, 3091 #ifdef CONFIG_PROC_FS 3092 .show_fdinfo = amdgpu_show_fdinfo, 3093 #endif 3094 3095 .gem_prime_import = amdgpu_gem_prime_import, 3096 3097 .name = DRIVER_NAME, 3098 .desc = DRIVER_DESC, 3099 .major = KMS_DRIVER_MAJOR, 3100 .minor = KMS_DRIVER_MINOR, 3101 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3102 }; 3103 3104 const struct drm_driver amdgpu_partition_driver = { 3105 .driver_features = 3106 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 3107 DRIVER_SYNCOBJ_TIMELINE, 3108 .open = amdgpu_driver_open_kms, 3109 .postclose = amdgpu_driver_postclose_kms, 3110 .ioctls = amdgpu_ioctls_kms, 3111 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 3112 .dumb_create = amdgpu_mode_dumb_create, 3113 .dumb_map_offset = amdgpu_mode_dumb_mmap, 3114 DRM_FBDEV_TTM_DRIVER_OPS, 3115 .fops = &amdgpu_driver_kms_fops, 3116 .release = &amdgpu_driver_release_kms, 3117 3118 .gem_prime_import = amdgpu_gem_prime_import, 3119 3120 .name = DRIVER_NAME, 3121 .desc = DRIVER_DESC, 3122 .major = KMS_DRIVER_MAJOR, 3123 .minor = KMS_DRIVER_MINOR, 3124 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3125 }; 3126 3127 static struct pci_error_handlers amdgpu_pci_err_handler = { 3128 .error_detected = amdgpu_pci_error_detected, 3129 .mmio_enabled = amdgpu_pci_mmio_enabled, 3130 .slot_reset = amdgpu_pci_slot_reset, 3131 .resume = amdgpu_pci_resume, 3132 }; 3133 3134 static const struct attribute_group *amdgpu_sysfs_groups[] = { 3135 &amdgpu_vram_mgr_attr_group, 3136 &amdgpu_gtt_mgr_attr_group, 3137 &amdgpu_flash_attr_group, 3138 NULL, 3139 }; 3140 3141 static struct pci_driver amdgpu_kms_pci_driver = { 3142 .name = DRIVER_NAME, 3143 .id_table = pciidlist, 3144 .probe = amdgpu_pci_probe, 3145 .remove = amdgpu_pci_remove, 3146 .shutdown = amdgpu_pci_shutdown, 3147 .driver.pm = pm_ptr(&amdgpu_pm_ops), 3148 .err_handler = &amdgpu_pci_err_handler, 3149 .dev_groups = amdgpu_sysfs_groups, 3150 }; 3151 3152 static int __init amdgpu_init(void) 3153 { 3154 int r; 3155 3156 r = amdgpu_sync_init(); 3157 if (r) 3158 goto error_sync; 3159 3160 r = amdgpu_userq_fence_slab_init(); 3161 if (r) 3162 goto error_fence; 3163 3164 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 3165 amdgpu_register_atpx_handler(); 3166 amdgpu_acpi_detect(); 3167 3168 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 3169 amdgpu_amdkfd_init(); 3170 3171 if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) { 3172 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 3173 pr_crit("Overdrive is enabled, please disable it before " 3174 "reporting any bugs unrelated to overdrive.\n"); 3175 } 3176 3177 /* let modprobe override vga console setting */ 3178 return pci_register_driver(&amdgpu_kms_pci_driver); 3179 3180 error_fence: 3181 amdgpu_sync_fini(); 3182 3183 error_sync: 3184 return r; 3185 } 3186 3187 static void __exit amdgpu_exit(void) 3188 { 3189 amdgpu_amdkfd_fini(); 3190 pci_unregister_driver(&amdgpu_kms_pci_driver); 3191 amdgpu_unregister_atpx_handler(); 3192 amdgpu_acpi_release(); 3193 amdgpu_sync_fini(); 3194 amdgpu_userq_fence_slab_fini(); 3195 mmu_notifier_synchronize(); 3196 amdgpu_xcp_drv_release(); 3197 } 3198 3199 module_init(amdgpu_init); 3200 module_exit(amdgpu_exit); 3201 3202 MODULE_AUTHOR(DRIVER_AUTHOR); 3203 MODULE_DESCRIPTION(DRIVER_DESC); 3204 MODULE_LICENSE("GPL and additional rights"); 3205