1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ip.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_ucode.h" 33 #include "amdgpu_xgmi.h" 34 #include "soc15_common.h" 35 #include "psp_v3_1.h" 36 #include "psp_v10_0.h" 37 #include "psp_v11_0.h" 38 #include "psp_v11_0_8.h" 39 #include "psp_v12_0.h" 40 #include "psp_v13_0.h" 41 #include "psp_v13_0_4.h" 42 #include "psp_v14_0.h" 43 #include "psp_v15_0.h" 44 #include "psp_v15_0_3.h" 45 #include "psp_v15_0_8.h" 46 47 #include "amdgpu_ras.h" 48 #include "amdgpu_securedisplay.h" 49 #include "amdgpu_atomfirmware.h" 50 51 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*16) 52 53 #define PSP_IRQ_DEFAULT_HANDLER_ID 0xFFFFFFFF 54 55 static int psp_load_smu_fw(struct psp_context *psp); 56 static int psp_rap_terminate(struct psp_context *psp); 57 static int psp_securedisplay_terminate(struct psp_context *psp); 58 59 static const char * const amdgpu_ptl_fmt_str[] = { 60 [AMDGPU_PTL_FMT_I8] = "I8", 61 [AMDGPU_PTL_FMT_F16] = "F16", 62 [AMDGPU_PTL_FMT_BF16] = "BF16", 63 [AMDGPU_PTL_FMT_F32] = "F32", 64 [AMDGPU_PTL_FMT_F64] = "F64", 65 [AMDGPU_PTL_FMT_F8] = "F8", 66 [AMDGPU_PTL_FMT_VECTOR] = "VECTOR", 67 [AMDGPU_PTL_FMT_INVALID] = "INVALID", 68 }; 69 70 static int psp_ring_init(struct psp_context *psp, 71 enum psp_ring_type ring_type) 72 { 73 int ret = 0; 74 struct psp_ring *ring; 75 struct amdgpu_device *adev = psp->adev; 76 77 ring = &psp->km_ring; 78 79 ring->ring_type = ring_type; 80 81 /* allocate 4k Page of Local Frame Buffer memory for ring */ 82 ring->ring_size = 0x1000; 83 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 84 AMDGPU_GEM_DOMAIN_VRAM | 85 AMDGPU_GEM_DOMAIN_GTT, 86 &adev->firmware.rbuf, 87 &ring->ring_mem_mc_addr, 88 (void **)&ring->ring_mem); 89 if (ret) { 90 ring->ring_size = 0; 91 return ret; 92 } 93 94 return 0; 95 } 96 97 /* 98 * Due to DF Cstate management centralized to PMFW, the firmware 99 * loading sequence will be updated as below: 100 * - Load KDB 101 * - Load SYS_DRV 102 * - Load tOS 103 * - Load PMFW 104 * - Setup TMR 105 * - Load other non-psp fw 106 * - Load ASD 107 * - Load XGMI/RAS/HDCP/DTM TA if any 108 * 109 * This new sequence is required for 110 * - Arcturus and onwards 111 */ 112 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 113 { 114 struct amdgpu_device *adev = psp->adev; 115 116 if (amdgpu_sriov_vf(adev)) { 117 psp->pmfw_centralized_cstate_management = false; 118 return; 119 } 120 121 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 122 case IP_VERSION(11, 0, 0): 123 case IP_VERSION(11, 0, 4): 124 case IP_VERSION(11, 0, 5): 125 case IP_VERSION(11, 0, 7): 126 case IP_VERSION(11, 0, 9): 127 case IP_VERSION(11, 0, 11): 128 case IP_VERSION(11, 0, 12): 129 case IP_VERSION(11, 0, 13): 130 case IP_VERSION(13, 0, 0): 131 case IP_VERSION(13, 0, 2): 132 case IP_VERSION(13, 0, 7): 133 psp->pmfw_centralized_cstate_management = true; 134 break; 135 default: 136 psp->pmfw_centralized_cstate_management = false; 137 break; 138 } 139 } 140 141 static int psp_init_sriov_microcode(struct psp_context *psp) 142 { 143 struct amdgpu_device *adev = psp->adev; 144 char ucode_prefix[30]; 145 int ret = 0; 146 147 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 148 149 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 150 case IP_VERSION(9, 0, 0): 151 case IP_VERSION(11, 0, 7): 152 case IP_VERSION(11, 0, 9): 153 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 154 ret = psp_init_cap_microcode(psp, ucode_prefix); 155 break; 156 case IP_VERSION(13, 0, 2): 157 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 158 ret = psp_init_cap_microcode(psp, ucode_prefix); 159 ret &= psp_init_ta_microcode(psp, ucode_prefix); 160 break; 161 case IP_VERSION(13, 0, 0): 162 adev->virt.autoload_ucode_id = 0; 163 break; 164 case IP_VERSION(13, 0, 6): 165 case IP_VERSION(13, 0, 14): 166 case IP_VERSION(13, 0, 15): 167 ret = psp_init_cap_microcode(psp, ucode_prefix); 168 ret &= psp_init_ta_microcode(psp, ucode_prefix); 169 break; 170 case IP_VERSION(13, 0, 10): 171 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 172 ret = psp_init_cap_microcode(psp, ucode_prefix); 173 break; 174 case IP_VERSION(13, 0, 12): 175 ret = psp_init_ta_microcode(psp, ucode_prefix); 176 break; 177 case IP_VERSION(15, 0, 3): 178 case IP_VERSION(15, 0, 8): 179 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 180 break; 181 default: 182 return -EINVAL; 183 } 184 return ret; 185 } 186 187 static int psp_early_init(struct amdgpu_ip_block *ip_block) 188 { 189 struct amdgpu_device *adev = ip_block->adev; 190 struct psp_context *psp = &adev->psp; 191 192 psp->autoload_supported = true; 193 psp->boot_time_tmr = true; 194 195 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 196 case IP_VERSION(9, 0, 0): 197 psp_v3_1_set_psp_funcs(psp); 198 psp->autoload_supported = false; 199 psp->boot_time_tmr = false; 200 break; 201 case IP_VERSION(10, 0, 0): 202 case IP_VERSION(10, 0, 1): 203 psp_v10_0_set_psp_funcs(psp); 204 psp->autoload_supported = false; 205 psp->boot_time_tmr = false; 206 break; 207 case IP_VERSION(11, 0, 2): 208 case IP_VERSION(11, 0, 4): 209 psp_v11_0_set_psp_funcs(psp); 210 psp->autoload_supported = false; 211 psp->boot_time_tmr = false; 212 break; 213 case IP_VERSION(11, 0, 0): 214 case IP_VERSION(11, 0, 7): 215 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev); 216 fallthrough; 217 case IP_VERSION(11, 0, 5): 218 case IP_VERSION(11, 0, 9): 219 case IP_VERSION(11, 0, 11): 220 case IP_VERSION(11, 5, 0): 221 case IP_VERSION(11, 5, 2): 222 case IP_VERSION(11, 0, 12): 223 case IP_VERSION(11, 0, 13): 224 psp_v11_0_set_psp_funcs(psp); 225 psp->boot_time_tmr = false; 226 break; 227 case IP_VERSION(11, 0, 3): 228 case IP_VERSION(12, 0, 1): 229 psp_v12_0_set_psp_funcs(psp); 230 psp->autoload_supported = false; 231 psp->boot_time_tmr = false; 232 break; 233 case IP_VERSION(13, 0, 2): 234 psp->boot_time_tmr = false; 235 fallthrough; 236 case IP_VERSION(13, 0, 6): 237 case IP_VERSION(13, 0, 14): 238 psp_v13_0_set_psp_funcs(psp); 239 psp->autoload_supported = false; 240 break; 241 case IP_VERSION(13, 0, 12): 242 case IP_VERSION(13, 0, 15): 243 psp_v13_0_set_psp_funcs(psp); 244 psp->autoload_supported = false; 245 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 246 break; 247 case IP_VERSION(13, 0, 1): 248 case IP_VERSION(13, 0, 3): 249 case IP_VERSION(13, 0, 5): 250 case IP_VERSION(13, 0, 8): 251 case IP_VERSION(13, 0, 11): 252 case IP_VERSION(14, 0, 0): 253 case IP_VERSION(14, 0, 1): 254 case IP_VERSION(14, 0, 4): 255 psp_v13_0_set_psp_funcs(psp); 256 psp->boot_time_tmr = false; 257 break; 258 case IP_VERSION(11, 0, 8): 259 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 260 psp_v11_0_8_set_psp_funcs(psp); 261 } 262 psp->autoload_supported = false; 263 psp->boot_time_tmr = false; 264 break; 265 case IP_VERSION(13, 0, 0): 266 case IP_VERSION(13, 0, 7): 267 case IP_VERSION(13, 0, 10): 268 psp_v13_0_set_psp_funcs(psp); 269 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 270 psp->boot_time_tmr = false; 271 break; 272 case IP_VERSION(13, 0, 4): 273 psp_v13_0_4_set_psp_funcs(psp); 274 psp->boot_time_tmr = false; 275 break; 276 case IP_VERSION(14, 0, 2): 277 case IP_VERSION(14, 0, 3): 278 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); 279 psp_v14_0_set_psp_funcs(psp); 280 break; 281 case IP_VERSION(14, 0, 5): 282 psp_v14_0_set_psp_funcs(psp); 283 psp->boot_time_tmr = false; 284 break; 285 case IP_VERSION(15, 0, 0): 286 case IP_VERSION(15, 0, 5): 287 case IP_VERSION(15, 0, 9): 288 psp_v15_0_0_set_psp_funcs(psp); 289 psp->boot_time_tmr = false; 290 break; 291 case IP_VERSION(15, 0, 3): 292 psp_v15_0_3_set_psp_funcs(psp); 293 break; 294 case IP_VERSION(15, 0, 8): 295 psp_v15_0_8_set_psp_funcs(psp); 296 break; 297 default: 298 return -EINVAL; 299 } 300 301 psp->adev = adev; 302 303 adev->psp_timeout = 20000; 304 305 psp_check_pmfw_centralized_cstate_management(psp); 306 307 if (amdgpu_sriov_vf(adev)) 308 return psp_init_sriov_microcode(psp); 309 else 310 return psp_init_microcode(psp); 311 } 312 313 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 314 { 315 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 316 &mem_ctx->shared_buf); 317 mem_ctx->shared_bo = NULL; 318 } 319 320 static void psp_free_shared_bufs(struct psp_context *psp) 321 { 322 void *tmr_buf; 323 void **pptr; 324 325 /* free TMR memory buffer */ 326 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 327 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 328 psp->tmr_bo = NULL; 329 330 /* free xgmi shared memory */ 331 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 332 333 /* free ras shared memory */ 334 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 335 336 /* free hdcp shared memory */ 337 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 338 339 /* free dtm shared memory */ 340 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 341 342 /* free rap shared memory */ 343 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 344 345 /* free securedisplay shared memory */ 346 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 347 348 349 } 350 351 static void psp_memory_training_fini(struct psp_context *psp) 352 { 353 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 354 355 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 356 kfree(ctx->sys_cache); 357 ctx->sys_cache = NULL; 358 } 359 360 static int psp_memory_training_init(struct psp_context *psp) 361 { 362 int ret; 363 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 364 365 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 366 dev_dbg(psp->adev->dev, "memory training is not supported!\n"); 367 return 0; 368 } 369 370 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 371 if (ctx->sys_cache == NULL) { 372 dev_err(psp->adev->dev, "alloc mem_train_ctx.sys_cache failed!\n"); 373 ret = -ENOMEM; 374 goto Err_out; 375 } 376 377 dev_dbg(psp->adev->dev, 378 "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 379 ctx->train_data_size, 380 ctx->p2c_train_data_offset, 381 ctx->c2p_train_data_offset); 382 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 383 return 0; 384 385 Err_out: 386 psp_memory_training_fini(psp); 387 return ret; 388 } 389 390 static uint64_t psp_get_runtime_db_header_pos(struct amdgpu_device *adev) 391 { 392 uint64_t pos; 393 394 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 395 case IP_VERSION(15, 0, 3): 396 pos = adev->discovery.offset + PSP_RUNTIME_DB_OFFSET_FROM_IP_DISCOVERY_TABLE; 397 break; 398 default: 399 pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 400 break; 401 } 402 403 return pos; 404 } 405 406 /* 407 * Helper funciton to query psp runtime database entry 408 * 409 * @adev: amdgpu_device pointer 410 * @entry_type: the type of psp runtime database entry 411 * @db_entry: runtime database entry pointer 412 * 413 * Return false if runtime database doesn't exit or entry is invalid 414 * or true if the specific database entry is found, and copy to @db_entry 415 */ 416 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 417 enum psp_runtime_entry_type entry_type, 418 void *db_entry) 419 { 420 uint64_t db_header_pos, db_dir_pos; 421 struct psp_runtime_data_header db_header = {0}; 422 struct psp_runtime_data_directory db_dir = {0}; 423 bool ret = false; 424 int i; 425 426 /* 427 * Runtime DB is for dGPUs only. 428 */ 429 if (adev->flags & AMD_IS_APU) 430 return false; 431 432 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 433 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 434 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || 435 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) 436 return false; 437 438 db_header_pos = psp_get_runtime_db_header_pos(adev); 439 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 440 441 /* read runtime db header from vram */ 442 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 443 sizeof(struct psp_runtime_data_header), false); 444 445 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 446 /* runtime db doesn't exist, exit */ 447 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n"); 448 return false; 449 } 450 451 /* read runtime database entry from vram */ 452 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 453 sizeof(struct psp_runtime_data_directory), false); 454 455 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 456 /* invalid db entry count, exit */ 457 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 458 return false; 459 } 460 461 /* look up for requested entry type */ 462 for (i = 0; i < db_dir.entry_count && !ret; i++) { 463 if (db_dir.entry_list[i].entry_type == entry_type) { 464 switch (entry_type) { 465 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 466 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 467 /* invalid db entry size */ 468 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 469 return false; 470 } 471 /* read runtime database entry */ 472 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 473 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 474 ret = true; 475 break; 476 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 477 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 478 /* invalid db entry size */ 479 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 480 return false; 481 } 482 /* read runtime database entry */ 483 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 484 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 485 ret = true; 486 break; 487 default: 488 ret = false; 489 break; 490 } 491 } 492 } 493 494 return ret; 495 } 496 497 static int psp_register_irq_handler(struct amdgpu_psp_irq_mgr *mgr) 498 { 499 struct psp_context *psp = mgr->psp; 500 501 if (!psp->funcs->register_irq_handler) 502 return 0; 503 return psp->funcs->register_irq_handler(mgr, &mgr->irq_src); 504 } 505 506 static int psp_irq_enable(struct psp_context *psp) 507 { 508 if (!psp->irq_mgr.irq_src.funcs) 509 return 0; 510 dev_info(psp->adev->dev, "psp interrupt enabled"); 511 return amdgpu_irq_get(psp->adev, &psp->irq_mgr.irq_src, 0); 512 } 513 514 static int psp_irq_disable(struct psp_context *psp) 515 { 516 if (!psp->irq_mgr.irq_src.funcs) 517 return 0; 518 return amdgpu_irq_put(psp->adev, &psp->irq_mgr.irq_src, 0); 519 } 520 521 /** 522 * amdgpu_psp_irq_mgr_dispatch() - run the registered handler for a PSP event 523 * @mgr: IRQ manager 524 * @entry: IH entry from the PSP soft ring 525 * 526 * Invokes the handler for the entry's event id (or the default handler) in 527 * process context. Call from the .process callback for PSP soft ring entries. 528 */ 529 void amdgpu_psp_irq_mgr_dispatch(struct amdgpu_psp_irq_mgr *mgr, 530 struct amdgpu_iv_entry *entry) 531 { 532 struct amdgpu_psp_irq_handler *h; 533 amdgpu_psp_irq_handler_fn cb; 534 u32 event_id = entry->src_data[0]; 535 536 cb = NULL; 537 xa_lock(&mgr->irq_bh_handlers); 538 h = xa_load(&mgr->irq_bh_handlers, (unsigned long)event_id); 539 if (h) { 540 cb = h->callback; 541 } else { 542 h = xa_load(&mgr->irq_bh_handlers, PSP_IRQ_DEFAULT_HANDLER_ID); 543 if (h) { 544 cb = h->callback; 545 } else { 546 dev_dbg(mgr->psp->adev->dev, 547 "PSP event: no handler for event_id:%x\n", 548 event_id); 549 xa_unlock(&mgr->irq_bh_handlers); 550 return; 551 } 552 } 553 xa_unlock(&mgr->irq_bh_handlers); 554 555 if (cb) 556 cb(mgr, event_id, entry); 557 } 558 559 static void psp_irq_mgr_init(struct psp_context *psp) 560 { 561 struct amdgpu_psp_irq_mgr *mgr = &psp->irq_mgr; 562 int ret; 563 564 mgr->psp = psp; 565 xa_init(&mgr->irq_bh_handlers); 566 567 ret = psp_register_irq_handler(mgr); 568 if (ret) 569 dev_dbg(psp->adev->dev, "Failed to register IRQ handler!\n"); 570 } 571 572 static void psp_irq_mgr_fini(struct amdgpu_psp_irq_mgr *mgr) 573 { 574 xa_destroy(&mgr->irq_bh_handlers); 575 } 576 577 /** 578 * amdgpu_psp_irq_mgr_register() - register PSP interrupt handlers by event id 579 * @mgr: PSP interrupt manager 580 * @handlers: per-event handlers, or NULL 581 * @count: number of @handlers 582 * @default_handler: fallback for unregistered event ids, or NULL 583 * 584 * Handlers must be statically allocated and stay valid until psp_irq_mgr_fini(). 585 * 586 * Return: 0 on success, negative error from xa_insert (e.g. duplicate event_id). 587 */ 588 int amdgpu_psp_irq_mgr_register( 589 struct amdgpu_psp_irq_mgr *mgr, 590 const struct amdgpu_psp_irq_handler *handlers, int count, 591 const struct amdgpu_psp_irq_handler *default_handler) 592 { 593 int ret, i; 594 595 if (handlers) { 596 for (i = 0; i < count; i++) { 597 ret = xa_insert(&mgr->irq_bh_handlers, 598 (unsigned long)handlers[i].event_id, 599 (void *)&handlers[i], GFP_KERNEL); 600 if (ret) 601 dev_dbg(mgr->psp->adev->dev, 602 "PSP IRQ: handler already registered for event_id:%x\n", 603 handlers[i].event_id); 604 } 605 } 606 607 if (default_handler) { 608 ret = xa_insert(&mgr->irq_bh_handlers, 609 PSP_IRQ_DEFAULT_HANDLER_ID, 610 (void *)default_handler, GFP_KERNEL); 611 if (ret) 612 dev_dbg(mgr->psp->adev->dev, 613 "PSP IRQ: handler already registered for default handler"); 614 } 615 616 return ret; 617 } 618 619 static int psp_sw_init(struct amdgpu_ip_block *ip_block) 620 { 621 struct amdgpu_device *adev = ip_block->adev; 622 struct psp_context *psp = &adev->psp; 623 int ret; 624 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 625 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 626 struct psp_runtime_scpm_entry scpm_entry; 627 628 psp->cmd = kzalloc_obj(struct psp_gfx_cmd_resp); 629 if (!psp->cmd) { 630 dev_err(adev->dev, "Failed to allocate memory to command buffer!\n"); 631 return -ENOMEM; 632 } 633 634 adev->psp.xgmi_context.supports_extended_data = 635 !adev->gmc.xgmi.connected_to_cpu && 636 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2); 637 638 memset(&scpm_entry, 0, sizeof(scpm_entry)); 639 if ((psp_get_runtime_db_entry(adev, 640 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 641 &scpm_entry)) && 642 (scpm_entry.scpm_status != SCPM_DISABLE)) { 643 adev->scpm_enabled = true; 644 adev->scpm_status = scpm_entry.scpm_status; 645 } else { 646 adev->scpm_enabled = false; 647 adev->scpm_status = SCPM_DISABLE; 648 } 649 650 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 651 652 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 653 if (psp_get_runtime_db_entry(adev, 654 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 655 &boot_cfg_entry)) { 656 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 657 if ((psp->boot_cfg_bitmask) & 658 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 659 /* If psp runtime database exists, then 660 * only enable two stage memory training 661 * when TWO_STAGE_DRAM_TRAINING bit is set 662 * in runtime database 663 */ 664 mem_training_ctx->enable_mem_training = true; 665 } 666 667 } else { 668 /* If psp runtime database doesn't exist or is 669 * invalid, force enable two stage memory training 670 */ 671 mem_training_ctx->enable_mem_training = true; 672 } 673 674 if (mem_training_ctx->enable_mem_training) { 675 ret = psp_memory_training_init(psp); 676 if (ret) { 677 dev_err(adev->dev, "Failed to initialize memory training!\n"); 678 return ret; 679 } 680 681 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 682 if (ret) { 683 dev_err(adev->dev, "Failed to process memory training!\n"); 684 return ret; 685 } 686 } 687 688 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 689 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf || adev->gmc.xgmi.connected_to_cpu) ? 690 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 691 &psp->fw_pri_bo, 692 &psp->fw_pri_mc_addr, 693 &psp->fw_pri_buf); 694 if (ret) 695 return ret; 696 697 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 698 AMDGPU_GEM_DOMAIN_VRAM | 699 AMDGPU_GEM_DOMAIN_GTT, 700 &psp->fence_buf_bo, 701 &psp->fence_buf_mc_addr, 702 &psp->fence_buf); 703 if (ret) 704 goto failed1; 705 706 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 707 AMDGPU_GEM_DOMAIN_VRAM | 708 AMDGPU_GEM_DOMAIN_GTT, 709 &psp->cmd_resp_buf_bo, &psp->cmd_resp_buf_mc_addr, 710 (void **)&psp->cmd_resp_buf_mem); 711 if (ret) 712 goto failed2; 713 714 /* Space for extended data in the tail of the cmd_buf allocation */ 715 psp->cmd_ext_resp_mc_addr = psp->cmd_resp_buf_mc_addr + sizeof(struct psp_gfx_cmd_resp); 716 psp->cmd_ext_resp_mem = psp->cmd_resp_buf_mem + 1; 717 psp_irq_mgr_init(psp); 718 return 0; 719 720 failed2: 721 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 722 &psp->fence_buf_mc_addr, &psp->fence_buf); 723 failed1: 724 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 725 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 726 return ret; 727 } 728 729 static int psp_sw_fini(struct amdgpu_ip_block *ip_block) 730 { 731 struct amdgpu_device *adev = ip_block->adev; 732 struct psp_context *psp = &adev->psp; 733 734 psp_irq_mgr_fini(&psp->irq_mgr); 735 736 psp_memory_training_fini(psp); 737 738 amdgpu_ucode_release(&psp->sos_fw); 739 amdgpu_ucode_release(&psp->asd_fw); 740 amdgpu_ucode_release(&psp->ta_fw); 741 amdgpu_ucode_release(&psp->cap_fw); 742 amdgpu_ucode_release(&psp->toc_fw); 743 744 kfree(psp->cmd); 745 psp->cmd = NULL; 746 747 psp_free_shared_bufs(psp); 748 749 if (psp->km_ring.ring_mem) 750 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 751 &psp->km_ring.ring_mem_mc_addr, 752 (void **)&psp->km_ring.ring_mem); 753 754 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 755 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 756 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 757 &psp->fence_buf_mc_addr, &psp->fence_buf); 758 amdgpu_bo_free_kernel(&psp->cmd_resp_buf_bo, &psp->cmd_resp_buf_mc_addr, 759 (void **)&psp->cmd_resp_buf_mem); 760 761 return 0; 762 } 763 764 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t reg_val, 765 uint32_t mask, uint32_t flags) 766 { 767 bool check_changed = flags & PSP_WAITREG_CHANGED; 768 bool verbose = !(flags & PSP_WAITREG_NOVERBOSE); 769 uint32_t val; 770 int i; 771 struct amdgpu_device *adev = psp->adev; 772 773 if (psp->adev->no_hw_access) 774 return 0; 775 776 for (i = 0; i < adev->usec_timeout; i++) { 777 val = RREG32(reg_index); 778 if (check_changed) { 779 if (val != reg_val) 780 return 0; 781 } else { 782 if ((val & mask) == reg_val) 783 return 0; 784 } 785 udelay(1); 786 } 787 788 if (verbose) 789 dev_err(adev->dev, 790 "psp reg (0x%x) wait timed out, mask: %x, read: %x exp: %x", 791 reg_index, mask, val, reg_val); 792 793 return -ETIME; 794 } 795 796 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 797 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout) 798 { 799 uint32_t val; 800 int i; 801 struct amdgpu_device *adev = psp->adev; 802 803 if (psp->adev->no_hw_access) 804 return 0; 805 806 for (i = 0; i < msec_timeout; i++) { 807 val = RREG32(reg_index); 808 if ((val & mask) == reg_val) 809 return 0; 810 msleep(1); 811 } 812 813 return -ETIME; 814 } 815 816 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 817 { 818 switch (cmd_id) { 819 case GFX_CMD_ID_LOAD_TA: 820 return "LOAD_TA"; 821 case GFX_CMD_ID_UNLOAD_TA: 822 return "UNLOAD_TA"; 823 case GFX_CMD_ID_INVOKE_CMD: 824 return "INVOKE_CMD"; 825 case GFX_CMD_ID_LOAD_ASD: 826 return "LOAD_ASD"; 827 case GFX_CMD_ID_SETUP_TMR: 828 return "SETUP_TMR"; 829 case GFX_CMD_ID_LOAD_IP_FW: 830 return "LOAD_IP_FW"; 831 case GFX_CMD_ID_DESTROY_TMR: 832 return "DESTROY_TMR"; 833 case GFX_CMD_ID_SAVE_RESTORE: 834 return "SAVE_RESTORE_IP_FW"; 835 case GFX_CMD_ID_SETUP_VMR: 836 return "SETUP_VMR"; 837 case GFX_CMD_ID_DESTROY_VMR: 838 return "DESTROY_VMR"; 839 case GFX_CMD_ID_PROG_REG: 840 return "PROG_REG"; 841 case GFX_CMD_ID_GET_FW_ATTESTATION: 842 return "GET_FW_ATTESTATION"; 843 case GFX_CMD_ID_LOAD_TOC: 844 return "ID_LOAD_TOC"; 845 case GFX_CMD_ID_AUTOLOAD_RLC: 846 return "AUTOLOAD_RLC"; 847 case GFX_CMD_ID_BOOT_CFG: 848 return "BOOT_CFG"; 849 case GFX_CMD_ID_CONFIG_SQ_PERFMON: 850 return "CONFIG_SQ_PERFMON"; 851 case GFX_CMD_ID_FB_FW_RESERV_ADDR: 852 return "FB_FW_RESERV_ADDR"; 853 case GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR: 854 return "FB_FW_RESERV_EXT_ADDR"; 855 case GFX_CMD_ID_SRIOV_SPATIAL_PART: 856 return "SPATIAL_PARTITION"; 857 case GFX_CMD_ID_FB_NPS_MODE: 858 return "NPS_MODE_CHANGE"; 859 case GFX_CMD_ID_PERF_HW: 860 return "PERF MONITORING HW"; 861 case GFX_CMD_ID_UAL_GET_INTERFACE_VER: 862 return "UAL_GET_INTERFACE_VER"; 863 case GFX_CMD_ID_UAL_GET_CONFIG: 864 return "UAL_GET_CONFIG"; 865 case GFX_CMD_ID_UAL_SET_PPOD_CONFIG: 866 return "UAL_SET_PPOD_CONFIG"; 867 case GFX_CMD_ID_UAL_SET_VPOD_CONFIG: 868 return "UAL_SET_VPOD_CONFIG"; 869 case GFX_CMD_ID_UAL_SET_STATION_CONFIG: 870 return "UAL_SET_STATION_CONFIG"; 871 case GFX_CMD_ID_UAL_SET_NPA_CONFIG: 872 return "UAL_SET_NPA_CONFIG"; 873 default: 874 return "UNKNOWN CMD"; 875 } 876 } 877 878 static bool psp_err_warn(struct psp_context *psp) 879 { 880 struct psp_gfx_cmd_resp *cmd = psp->cmd_resp_buf_mem; 881 882 /* This response indicates reg list is already loaded */ 883 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 884 cmd->cmd_id == GFX_CMD_ID_LOAD_IP_FW && 885 cmd->cmd.cmd_load_ip_fw.fw_type == GFX_FW_TYPE_REG_LIST && 886 cmd->resp.status == TEE_ERROR_CANCEL) 887 return false; 888 889 return true; 890 } 891 892 static int 893 psp_cmd_submit_buf(struct psp_context *psp, 894 struct amdgpu_firmware_info *ucode, 895 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 896 { 897 int ret; 898 int index; 899 int timeout = psp->adev->psp_timeout; 900 bool ras_intr = false; 901 bool skip_unsupport = false; 902 903 if (psp->adev->no_hw_access) 904 return 0; 905 906 memset(psp->cmd_resp_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 907 908 memcpy(psp->cmd_resp_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 909 910 index = atomic_inc_return(&psp->fence_value); 911 ret = psp_ring_cmd_submit(psp, psp->cmd_resp_buf_mc_addr, fence_mc_addr, index); 912 if (ret) { 913 atomic_dec(&psp->fence_value); 914 goto exit; 915 } 916 917 amdgpu_device_invalidate_hdp(psp->adev, NULL); 918 while (*((unsigned int *)psp->fence_buf) != index) { 919 if (--timeout == 0) 920 break; 921 /* 922 * Shouldn't wait for timeout when err_event_athub occurs, 923 * because gpu reset thread triggered and lock resource should 924 * be released for psp resume sequence. 925 */ 926 ras_intr = amdgpu_ras_intr_triggered(); 927 if (ras_intr) 928 break; 929 usleep_range(150, 300); 930 amdgpu_device_invalidate_hdp(psp->adev, NULL); 931 } 932 933 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 934 skip_unsupport = (psp->cmd_resp_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 935 psp->cmd_resp_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && 936 amdgpu_sriov_vf(psp->adev); 937 938 memcpy(&cmd->resp, &psp->cmd_resp_buf_mem->resp, sizeof(struct psp_gfx_resp)); 939 940 /* In some cases, psp response status is not 0 even there is no 941 * problem while the command is submitted. Some version of PSP FW 942 * doesn't write 0 to that field. 943 * So here we would like to only print a warning instead of an error 944 * during psp initialization to avoid breaking hw_init and it doesn't 945 * return -EINVAL. 946 */ 947 if (!skip_unsupport && (psp->cmd_resp_buf_mem->resp.status || !timeout) && !ras_intr) { 948 if (ucode) 949 dev_warn(psp->adev->dev, 950 "failed to load ucode %s(0x%X) ", 951 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 952 if (psp_err_warn(psp)) 953 dev_warn( 954 psp->adev->dev, 955 "psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 956 psp_gfx_cmd_name(psp->cmd_resp_buf_mem->cmd_id), 957 psp->cmd_resp_buf_mem->cmd_id, 958 psp->cmd_resp_buf_mem->resp.status); 959 /* If any firmware (including CAP) load fails under SRIOV, it should 960 * return failure to stop the VF from initializing. 961 * Also return failure in case of timeout 962 */ 963 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 964 ret = -EINVAL; 965 goto exit; 966 } 967 } 968 969 if (ucode) { 970 ucode->tmr_mc_addr_lo = psp->cmd_resp_buf_mem->resp.fw_addr_lo; 971 ucode->tmr_mc_addr_hi = psp->cmd_resp_buf_mem->resp.fw_addr_hi; 972 } 973 974 exit: 975 return ret; 976 } 977 978 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 979 { 980 struct psp_gfx_cmd_resp *cmd = psp->cmd; 981 982 mutex_lock(&psp->mutex); 983 984 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 985 986 return cmd; 987 } 988 989 static void release_psp_cmd_buf(struct psp_context *psp) 990 { 991 mutex_unlock(&psp->mutex); 992 } 993 994 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 995 struct psp_gfx_cmd_resp *cmd, 996 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 997 { 998 struct amdgpu_device *adev = psp->adev; 999 uint32_t size = 0; 1000 uint64_t tmr_pa = 0; 1001 1002 if (tmr_bo) { 1003 size = amdgpu_bo_size(tmr_bo); 1004 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 1005 } 1006 1007 if (amdgpu_sriov_vf(psp->adev)) 1008 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 1009 else 1010 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 1011 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 1012 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 1013 cmd->cmd.cmd_setup_tmr.buf_size = size; 1014 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 1015 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 1016 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 1017 } 1018 1019 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1020 uint64_t pri_buf_mc, uint32_t size) 1021 { 1022 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 1023 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 1024 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 1025 cmd->cmd.cmd_load_toc.toc_size = size; 1026 } 1027 1028 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 1029 static int psp_load_toc(struct psp_context *psp, 1030 uint32_t *tmr_size) 1031 { 1032 int ret; 1033 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1034 1035 /* Copy toc to psp firmware private buffer */ 1036 ret = psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 1037 if (ret) { 1038 release_psp_cmd_buf(psp); 1039 return ret; 1040 } 1041 1042 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 1043 1044 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1045 psp->fence_buf_mc_addr); 1046 if (!ret) 1047 *tmr_size = psp->cmd_resp_buf_mem->resp.tmr_size; 1048 1049 release_psp_cmd_buf(psp); 1050 1051 return ret; 1052 } 1053 1054 /* Set up Trusted Memory Region */ 1055 static int psp_tmr_init(struct psp_context *psp) 1056 { 1057 int ret = 0; 1058 int tmr_size; 1059 void *tmr_buf; 1060 void **pptr; 1061 1062 /* 1063 * According to HW engineer, they prefer the TMR address be "naturally 1064 * aligned" , e.g. the start address be an integer divide of TMR size. 1065 * 1066 * Note: this memory need be reserved till the driver 1067 * uninitializes. 1068 */ 1069 tmr_size = PSP_TMR_SIZE(psp->adev); 1070 1071 /* For ASICs support RLC autoload, psp will parse the toc 1072 * and calculate the total size of TMR needed 1073 */ 1074 if (!amdgpu_sriov_vf(psp->adev) && 1075 psp->toc.start_addr && 1076 psp->toc.size_bytes && 1077 psp->fw_pri_buf) { 1078 ret = psp_load_toc(psp, &tmr_size); 1079 if (ret) { 1080 dev_err(psp->adev->dev, "Failed to load toc\n"); 1081 return ret; 1082 } 1083 } 1084 1085 if (!psp->tmr_bo && !psp->boot_time_tmr) { 1086 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 1087 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, 1088 PSP_TMR_ALIGNMENT, 1089 AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM, 1090 &psp->tmr_bo, &psp->tmr_mc_addr, 1091 pptr); 1092 } 1093 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && psp->tmr_bo) 1094 psp->tmr_mc_addr = amdgpu_bo_fb_aper_addr(psp->tmr_bo); 1095 1096 return ret; 1097 } 1098 1099 static bool psp_skip_tmr(struct psp_context *psp) 1100 { 1101 u32 ip_version = amdgpu_ip_version(psp->adev, MP0_HWIP, 0); 1102 1103 if (amdgpu_sriov_vf(psp->adev)) 1104 return (ip_version >= IP_VERSION(11, 0, 7)) ? true : false; 1105 else 1106 return (!psp->boot_time_tmr || !psp->autoload_supported) ? false : true; 1107 } 1108 1109 static int psp_tmr_load(struct psp_context *psp) 1110 { 1111 int ret; 1112 struct psp_gfx_cmd_resp *cmd; 1113 1114 if (psp_skip_tmr(psp)) 1115 return 0; 1116 1117 cmd = acquire_psp_cmd_buf(psp); 1118 1119 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 1120 if (psp->tmr_bo) 1121 dev_info(psp->adev->dev, "reserve 0x%lx from 0x%llx for PSP TMR\n", 1122 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 1123 1124 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1125 psp->fence_buf_mc_addr); 1126 1127 release_psp_cmd_buf(psp); 1128 1129 return ret; 1130 } 1131 1132 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 1133 struct psp_gfx_cmd_resp *cmd) 1134 { 1135 if (amdgpu_sriov_vf(psp->adev)) 1136 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 1137 else 1138 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 1139 } 1140 1141 static int psp_tmr_unload(struct psp_context *psp) 1142 { 1143 int ret; 1144 struct psp_gfx_cmd_resp *cmd; 1145 1146 if (psp_skip_tmr(psp)) 1147 return 0; 1148 1149 cmd = acquire_psp_cmd_buf(psp); 1150 1151 psp_prep_tmr_unload_cmd_buf(psp, cmd); 1152 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n"); 1153 1154 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1155 psp->fence_buf_mc_addr); 1156 1157 release_psp_cmd_buf(psp); 1158 1159 return ret; 1160 } 1161 1162 static int psp_tmr_terminate(struct psp_context *psp) 1163 { 1164 return psp_tmr_unload(psp); 1165 } 1166 1167 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 1168 uint64_t *output_ptr) 1169 { 1170 int ret; 1171 struct psp_gfx_cmd_resp *cmd; 1172 1173 if (!output_ptr) 1174 return -EINVAL; 1175 1176 if (amdgpu_sriov_vf(psp->adev)) 1177 return 0; 1178 1179 cmd = acquire_psp_cmd_buf(psp); 1180 1181 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 1182 1183 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1184 psp->fence_buf_mc_addr); 1185 1186 if (!ret) { 1187 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 1188 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 1189 } 1190 1191 release_psp_cmd_buf(psp); 1192 1193 return ret; 1194 } 1195 1196 static int psp_get_fw_reservation_info(struct psp_context *psp, 1197 uint32_t cmd_id, 1198 uint64_t *addr, 1199 uint32_t *size) 1200 { 1201 int ret; 1202 uint32_t status; 1203 struct psp_gfx_cmd_resp *cmd; 1204 1205 cmd = acquire_psp_cmd_buf(psp); 1206 1207 cmd->cmd_id = cmd_id; 1208 1209 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1210 psp->fence_buf_mc_addr); 1211 if (ret) { 1212 release_psp_cmd_buf(psp); 1213 return ret; 1214 } 1215 1216 status = cmd->resp.status; 1217 if (status == PSP_ERR_UNKNOWN_COMMAND) { 1218 release_psp_cmd_buf(psp); 1219 *addr = 0; 1220 *size = 0; 1221 return 0; 1222 } 1223 1224 *addr = (uint64_t)cmd->resp.uresp.fw_reserve_info.reserve_base_address_hi << 32 | 1225 cmd->resp.uresp.fw_reserve_info.reserve_base_address_lo; 1226 *size = cmd->resp.uresp.fw_reserve_info.reserve_size; 1227 1228 release_psp_cmd_buf(psp); 1229 1230 return 0; 1231 } 1232 1233 int psp_ual_get_interface_version(struct psp_context *psp, uint32_t *intf_ver) 1234 { 1235 struct psp_gfx_cmd_resp *cmd; 1236 int ret; 1237 1238 cmd = acquire_psp_cmd_buf(psp); 1239 1240 cmd->cmd_id = GFX_CMD_ID_UAL_GET_INTERFACE_VER; 1241 1242 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1243 1244 if (!ret && !cmd->resp.status) { 1245 *intf_ver = cmd->resp.uresp.get_intf_ver_ual.intf_ver; 1246 } else if (!ret) { 1247 pr_debug("ual_get_if_ver: PSP status %x\n", cmd->resp.status); 1248 ret = -EINVAL; 1249 } 1250 1251 release_psp_cmd_buf(psp); 1252 1253 return ret; 1254 } 1255 1256 int psp_ual_query_info(struct psp_context *psp, uint32_t intf_ver, 1257 struct amdgpu_ualink_info *info, 1258 enum psp_gfx_ual_config_state *cfg_state) 1259 { 1260 struct psp_gfx_get_config_ual_v1 *ual_config; 1261 struct psp_gfx_cmd_resp *cmd; 1262 int ret; 1263 1264 /* TBD check interface version 1.x */ 1265 if (intf_ver > 0x1ffff) { 1266 pr_warn("PSP UAL interface version mismatch: 0x%x\n", intf_ver); 1267 return -EOPNOTSUPP; 1268 } 1269 1270 cmd = acquire_psp_cmd_buf(psp); 1271 1272 ual_config = psp->cmd_ext_resp_mem; 1273 1274 cmd->cmd_id = GFX_CMD_ID_UAL_GET_CONFIG; 1275 cmd->cmd.cmd_get_config_ual.ual_cfg_addr_lo = lower_32_bits(psp->cmd_ext_resp_mc_addr); 1276 cmd->cmd.cmd_get_config_ual.ual_cfg_addr_hi = upper_32_bits(psp->cmd_ext_resp_mc_addr); 1277 cmd->cmd.cmd_get_config_ual.ual_cfg_size = sizeof(*ual_config); 1278 1279 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1280 1281 if (!ret && !cmd->resp.status) { 1282 WARN_ON(cmd->resp.uresp.get_config_ual.resp_size < sizeof(*ual_config)); 1283 1284 info->link_type = (enum amdgpu_ualink_type)ual_config->link_type; 1285 1286 info->ppod.accel_id = ual_config->accelerator_id; 1287 info->ppod.bandwidth = ual_config->bandwidth; 1288 info->ppod.latency = ual_config->latency; 1289 info->ppod.size = ual_config->ppod_size; 1290 memcpy(&info->ppod.id, ual_config->ppod_id, sizeof(info->ppod.id)); 1291 1292 info->vpod.id = ual_config->vpod_id; 1293 info->vpod.size = ual_config->vpod_size; 1294 info->vpod.addr_mode = ual_config->addr_mode; 1295 bitmap_from_arr32(info->vpod.active_accel_bits, 1296 ual_config->vpod_active_accelerators, 1297 min(AMDGPU_UALINK_ACCEL_MAX, PSP_GFX_UAL_MAX_ACC_BIT_MASK*32)); 1298 /* Ensure no uninitialized data in the bitmap, even if these 1299 * constants change in the future. 1300 */ 1301 if (AMDGPU_UALINK_ACCEL_MAX > PSP_GFX_UAL_MAX_ACC_BIT_MASK*32) 1302 bitmap_clear(info->vpod.active_accel_bits, PSP_GFX_UAL_MAX_ACC_BIT_MASK*32, 1303 AMDGPU_UALINK_ACCEL_MAX - PSP_GFX_UAL_MAX_ACC_BIT_MASK*32); 1304 1305 if (cfg_state) 1306 *cfg_state = ual_config->config_state; 1307 } else if (!ret) { 1308 ret = -EINVAL; 1309 } 1310 1311 release_psp_cmd_buf(psp); 1312 1313 return ret; 1314 } 1315 1316 int psp_ual_set_ppod_config(struct psp_context *psp, uint32_t intf_ver, 1317 const struct amdgpu_ualink_ppod_setup *setup) 1318 { 1319 struct psp_gfx_cmd_resp *cmd; 1320 int ret; 1321 1322 /* TBD check interface version 1.x */ 1323 if (intf_ver > 0x1ffff) { 1324 pr_warn("PSP UAL interface version mismatch: 0x%x\n", intf_ver); 1325 return -EOPNOTSUPP; 1326 } 1327 1328 cmd = acquire_psp_cmd_buf(psp); 1329 1330 cmd->cmd_id = GFX_CMD_ID_UAL_SET_PPOD_CONFIG; 1331 cmd->cmd.cmd_set_ppod_config_ual.accelerator_id = setup->ppod.accel_id; 1332 memcpy(cmd->cmd.cmd_set_ppod_config_ual.ppod_id, &setup->ppod.id, 1333 sizeof(cmd->cmd.cmd_set_ppod_config_ual.ppod_id)); 1334 cmd->cmd.cmd_set_ppod_config_ual.ppod_size = setup->ppod.size; 1335 cmd->cmd.cmd_set_ppod_config_ual.bandwidth = setup->ppod.bandwidth; 1336 cmd->cmd.cmd_set_ppod_config_ual.latency = setup->ppod.latency; 1337 1338 memcpy(cmd->cmd.cmd_set_ppod_config_ual.local_accelerators, 1339 setup->local_accels, 1340 min(sizeof(cmd->cmd.cmd_set_ppod_config_ual.local_accelerators), 1341 setup->n_local_accels * sizeof(u32))); 1342 /* Fill the remainder of the array with invalid accelerator IDs */ 1343 if (sizeof(cmd->cmd.cmd_set_ppod_config_ual.local_accelerators) > 1344 setup->n_local_accels * sizeof(u32)) 1345 memset(&cmd->cmd.cmd_set_ppod_config_ual.local_accelerators[setup->n_local_accels], 1346 0xff, sizeof(cmd->cmd.cmd_set_ppod_config_ual.local_accelerators) - 1347 setup->n_local_accels * sizeof(u32)); 1348 1349 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1350 1351 if (!ret && cmd->resp.status) 1352 ret = -EINVAL; 1353 1354 release_psp_cmd_buf(psp); 1355 1356 return ret; 1357 } 1358 1359 int psp_ual_set_vpod_config(struct psp_context *psp, uint32_t intf_ver, 1360 const struct amdgpu_ualink_vpod_config *config) 1361 { 1362 struct psp_gfx_cmd_resp *cmd; 1363 int ret; 1364 1365 /* TBD check interface version 1.x */ 1366 if (intf_ver > 0x1ffff) { 1367 pr_warn("PSP UAL interface version mismatch: 0x%x\n", intf_ver); 1368 return -EOPNOTSUPP; 1369 } 1370 1371 cmd = acquire_psp_cmd_buf(psp); 1372 1373 cmd->cmd_id = GFX_CMD_ID_UAL_SET_VPOD_CONFIG; 1374 cmd->cmd.cmd_set_vpod_config_ual.addr_mode = 1375 (enum psp_gfx_ual_npa_address_mode)config->vpod.addr_mode; 1376 cmd->cmd.cmd_set_vpod_config_ual.vpod_id = config->vpod.id; 1377 cmd->cmd.cmd_set_vpod_config_ual.vpod_size = config->vpod.size; 1378 1379 bitmap_to_arr32(cmd->cmd.cmd_set_vpod_config_ual.vpod_active_accelerators, 1380 config->vpod.active_accel_bits, 1381 min(AMDGPU_UALINK_ACCEL_MAX, PSP_GFX_UAL_MAX_ACC_BIT_MASK*32)); 1382 /* Clear any remaining accelerator bits */ 1383 if (PSP_GFX_UAL_MAX_ACC_BIT_MASK > DIV_ROUND_UP(AMDGPU_UALINK_ACCEL_MAX, 32)) 1384 memset(cmd->cmd.cmd_set_vpod_config_ual.vpod_active_accelerators + 1385 DIV_ROUND_UP(AMDGPU_UALINK_ACCEL_MAX, 32), 0, 1386 (PSP_GFX_UAL_MAX_ACC_BIT_MASK - 1387 DIV_ROUND_UP(AMDGPU_UALINK_ACCEL_MAX, 32)) * sizeof(u32)); 1388 1389 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1390 1391 if (!ret && cmd->resp.status) 1392 ret = -EINVAL; 1393 1394 release_psp_cmd_buf(psp); 1395 1396 return ret; 1397 } 1398 1399 int psp_ual_set_station_config(struct psp_context *psp, uint32_t intf_ver, 1400 const struct amdgpu_ualink_station_config *stations) 1401 { 1402 struct psp_gfx_cmd_resp *cmd; 1403 int ret; 1404 1405 /* TBD check interface version 1.x */ 1406 if (intf_ver > 0x1ffff) { 1407 pr_warn("PSP UAL interface version mismatch: 0x%x\n", intf_ver); 1408 return -EOPNOTSUPP; 1409 } 1410 1411 cmd = acquire_psp_cmd_buf(psp); 1412 1413 cmd->cmd_id = GFX_CMD_ID_UAL_SET_STATION_CONFIG; 1414 cmd->cmd.cmd_set_station_config_ual.num_stations = stations->n_stations; 1415 cmd->cmd.cmd_set_station_config_ual.station_flag = stations->flags; 1416 memcpy(cmd->cmd.cmd_set_station_config_ual.lane_en_bitmap, 1417 stations->lane_en_bitmap, 1418 min(stations->n_stations, 1419 sizeof(cmd->cmd.cmd_set_station_config_ual.lane_en_bitmap))); 1420 /* The remainder is already 0-initialized by acquire_psp_cmd_buf */ 1421 1422 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1423 1424 if (!ret && cmd->resp.status) 1425 ret = -EINVAL; 1426 1427 release_psp_cmd_buf(psp); 1428 1429 return ret; 1430 } 1431 1432 int psp_ual_set_npa_config(struct psp_context *psp, uint32_t intf_ver, 1433 unsigned int vmid, bool enable) 1434 { 1435 struct psp_gfx_cmd_resp *cmd; 1436 int ret; 1437 1438 /* TBD check interface version 1.x */ 1439 if (intf_ver > 0x1ffff) { 1440 pr_warn("PSP UAL interface version mismatch: 0x%x\n", intf_ver); 1441 return -EOPNOTSUPP; 1442 } 1443 1444 cmd = acquire_psp_cmd_buf(psp); 1445 1446 cmd->cmd_id = GFX_CMD_ID_UAL_SET_NPA_CONFIG; 1447 cmd->cmd.cmd_set_npa_config_ual.vmid = vmid; 1448 cmd->cmd.cmd_set_npa_config_ual.enable_npa_translation = enable; 1449 1450 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1451 1452 if (!ret && cmd->resp.status) 1453 ret = -EINVAL; 1454 1455 release_psp_cmd_buf(psp); 1456 1457 return ret; 1458 } 1459 1460 int psp_ual_send_completion(struct psp_context *psp, uint32_t intf_ver, 1461 uint32_t cmd_id, uint32_t status) 1462 { 1463 struct psp_gfx_cmd_resp *cmd; 1464 int ret; 1465 1466 /* TBD check interface version 1.x */ 1467 if (intf_ver > 0x1ffff) { 1468 pr_warn("PSP UAL interface version mismatch: 0x%x\n", intf_ver); 1469 return -EOPNOTSUPP; 1470 } 1471 1472 cmd = acquire_psp_cmd_buf(psp); 1473 1474 cmd->cmd_id = GFX_CMD_ID_UAL_SEND_COMPLETION; 1475 cmd->cmd.cmd_send_completion_ual.cmd_id = cmd_id; 1476 cmd->cmd.cmd_send_completion_ual.status = status; 1477 1478 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1479 1480 if (!ret && cmd->resp.status) 1481 ret = -EINVAL; 1482 1483 release_psp_cmd_buf(psp); 1484 1485 return ret; 1486 } 1487 1488 int psp_update_fw_reservation(struct psp_context *psp) 1489 { 1490 int ret; 1491 uint64_t reserv_addr, reserv_addr_ext; 1492 uint32_t reserv_size, reserv_size_ext, mp0_ip_ver; 1493 struct amdgpu_device *adev = psp->adev; 1494 1495 mp0_ip_ver = amdgpu_ip_version(adev, MP0_HWIP, 0); 1496 1497 if (amdgpu_sriov_vf(psp->adev)) 1498 return 0; 1499 1500 switch (mp0_ip_ver) { 1501 case IP_VERSION(14, 0, 2): 1502 if (adev->psp.sos.fw_version < 0x3b0e0d) 1503 return 0; 1504 break; 1505 1506 case IP_VERSION(14, 0, 3): 1507 if (adev->psp.sos.fw_version < 0x3a0e14) 1508 return 0; 1509 break; 1510 1511 default: 1512 return 0; 1513 } 1514 1515 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_ADDR, &reserv_addr, &reserv_size); 1516 if (ret) 1517 return ret; 1518 ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR, &reserv_addr_ext, &reserv_size_ext); 1519 if (ret) 1520 return ret; 1521 1522 if (reserv_addr != adev->gmc.real_vram_size - reserv_size) { 1523 dev_warn(adev->dev, "reserve fw region is not valid!\n"); 1524 return 0; 1525 } 1526 1527 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_FW); 1528 1529 reserv_size = roundup(reserv_size, SZ_1M); 1530 1531 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW, 1532 reserv_addr, reserv_size, false); 1533 ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW); 1534 if (ret) { 1535 dev_err(adev->dev, "reserve fw region failed(%d)!\n", ret); 1536 return ret; 1537 } 1538 1539 reserv_size_ext = roundup(reserv_size_ext, SZ_1M); 1540 1541 amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_EXTEND, 1542 reserv_addr_ext, reserv_size_ext, false); 1543 ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW_EXTEND); 1544 if (ret) { 1545 dev_err(adev->dev, "reserve extend fw region failed(%d)!\n", ret); 1546 return ret; 1547 } 1548 1549 return 0; 1550 } 1551 1552 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 1553 { 1554 struct psp_context *psp = &adev->psp; 1555 struct psp_gfx_cmd_resp *cmd; 1556 int ret; 1557 1558 if (amdgpu_sriov_vf(adev)) 1559 return 0; 1560 1561 cmd = acquire_psp_cmd_buf(psp); 1562 1563 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1564 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 1565 1566 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1567 if (!ret) { 1568 *boot_cfg = 1569 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 1570 } 1571 1572 release_psp_cmd_buf(psp); 1573 1574 return ret; 1575 } 1576 1577 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 1578 { 1579 int ret; 1580 struct psp_context *psp = &adev->psp; 1581 struct psp_gfx_cmd_resp *cmd; 1582 1583 if (amdgpu_sriov_vf(adev)) 1584 return 0; 1585 1586 cmd = acquire_psp_cmd_buf(psp); 1587 1588 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 1589 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 1590 cmd->cmd.boot_cfg.boot_config = boot_cfg; 1591 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 1592 1593 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1594 1595 release_psp_cmd_buf(psp); 1596 1597 return ret; 1598 } 1599 1600 static int psp_rl_load(struct amdgpu_device *adev) 1601 { 1602 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1603 int ret; 1604 struct psp_context *psp = &adev->psp; 1605 struct psp_gfx_cmd_resp *cmd; 1606 1607 if (!is_psp_fw_valid(psp->rl)) 1608 return 0; 1609 1610 if (con && con->uniras_load_ras_fw) 1611 return 0; 1612 1613 cmd = acquire_psp_cmd_buf(psp); 1614 1615 ret = psp_copy_fw(psp, psp->rl.start_addr, psp->rl.size_bytes); 1616 if (ret) { 1617 release_psp_cmd_buf(psp); 1618 return ret; 1619 } 1620 1621 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 1622 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 1623 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 1624 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 1625 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 1626 1627 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1628 1629 release_psp_cmd_buf(psp); 1630 1631 return ret; 1632 } 1633 1634 int psp_memory_partition(struct psp_context *psp, int mode) 1635 { 1636 struct psp_gfx_cmd_resp *cmd; 1637 int ret; 1638 1639 if (amdgpu_sriov_vf(psp->adev)) 1640 return 0; 1641 1642 cmd = acquire_psp_cmd_buf(psp); 1643 1644 cmd->cmd_id = GFX_CMD_ID_FB_NPS_MODE; 1645 cmd->cmd.cmd_memory_part.mode = mode; 1646 1647 dev_info(psp->adev->dev, 1648 "Requesting %d memory partition change through PSP", mode); 1649 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1650 if (ret) 1651 dev_err(psp->adev->dev, 1652 "PSP request failed to change to NPS%d mode\n", mode); 1653 1654 release_psp_cmd_buf(psp); 1655 1656 return ret; 1657 } 1658 1659 int psp_set_mmhub_eco_sec_level(struct amdgpu_device *adev) 1660 { 1661 int ret; 1662 struct psp_context *psp = &adev->psp; 1663 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1664 1665 cmd->cmd_id = GFX_CMD_ID_SET_MMHUB_ECO_SEC_LEVEL; 1666 1667 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1668 if (ret) { 1669 dev_err(psp->adev->dev, 1670 "PSP request failed to set mmuhub eco sec level with ret=%d\n", ret); 1671 release_psp_cmd_buf(psp); 1672 return ret; 1673 } 1674 1675 if (cmd->resp.status) { 1676 dev_err(psp->adev->dev, 1677 "MMHUB ECO SEC LEVEL command 0x%x failed, PSP response status: 0x%X\n", 1678 cmd->cmd_id, cmd->resp.status); 1679 ret = -EIO; 1680 } 1681 release_psp_cmd_buf(psp); 1682 1683 return ret; 1684 } 1685 1686 static int psp_ptl_fmt_verify(struct psp_context *psp, enum amdgpu_ptl_fmt fmt, 1687 uint32_t *ptl_fmt) 1688 { 1689 struct amdgpu_device *adev = psp->adev; 1690 1691 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) 1692 return -EINVAL; 1693 1694 switch (fmt) { 1695 case AMDGPU_PTL_FMT_I8: 1696 *ptl_fmt = GFX_FTYPE_I8; 1697 break; 1698 case AMDGPU_PTL_FMT_F16: 1699 *ptl_fmt = GFX_FTYPE_F16; 1700 break; 1701 case AMDGPU_PTL_FMT_BF16: 1702 *ptl_fmt = GFX_FTYPE_BF16; 1703 break; 1704 case AMDGPU_PTL_FMT_F32: 1705 *ptl_fmt = GFX_FTYPE_F32; 1706 break; 1707 case AMDGPU_PTL_FMT_F64: 1708 *ptl_fmt = GFX_FTYPE_F64; 1709 break; 1710 case AMDGPU_PTL_FMT_F8: 1711 *ptl_fmt = GFX_FTYPE_F8; 1712 break; 1713 case AMDGPU_PTL_FMT_VECTOR: 1714 *ptl_fmt = GFX_FTYPE_VECTOR; 1715 break; 1716 default: 1717 return -EINVAL; 1718 } 1719 1720 return 0; 1721 } 1722 1723 static int psp_ptl_invoke(struct psp_context *psp, u32 req_code, 1724 uint32_t *ptl_state, uint32_t *fmt1, uint32_t *fmt2) 1725 { 1726 struct psp_gfx_cmd_resp *cmd; 1727 struct amdgpu_ptl *ptl = &psp->ptl; 1728 struct amdgpu_device *adev = psp->adev; 1729 int ret; 1730 1731 if (amdgpu_sriov_vf(adev)) { 1732 ret = amdgpu_virt_ptl_request(adev, req_code, ptl_state, fmt1, fmt2); 1733 if (!ret) { 1734 ptl->enabled = *ptl_state; 1735 ptl->fmt1 = *fmt1; 1736 ptl->fmt2 = *fmt2; 1737 } 1738 return ret; 1739 } 1740 1741 cmd = acquire_psp_cmd_buf(psp); 1742 1743 cmd->cmd_id = GFX_CMD_ID_PERF_HW; 1744 cmd->cmd.cmd_req_perf_hw.req = req_code; 1745 cmd->cmd.cmd_req_perf_hw.ptl_state = *ptl_state; 1746 cmd->cmd.cmd_req_perf_hw.pref_format1 = *fmt1; 1747 cmd->cmd.cmd_req_perf_hw.pref_format2 = *fmt2; 1748 1749 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1750 if (ret) 1751 goto out; 1752 1753 /* 1754 * Check response status explicitly to avoid 1755 * updating cached PTL state with invalid data. 1756 */ 1757 if (cmd->resp.status) { 1758 dev_err(psp->adev->dev, 1759 "PTL command 0x%x failed, PSP response status: 0x%X fw resp=0x%X\n", 1760 req_code, cmd->resp.status, 1761 cmd->resp.uresp.perf_hw_info.resp); 1762 ret = -EIO; 1763 goto out; 1764 } 1765 1766 /* Parse response */ 1767 switch (req_code) { 1768 case PSP_PTL_PERF_MON_QUERY: 1769 *ptl_state = cmd->resp.uresp.perf_hw_info.ptl_state; 1770 *fmt1 = cmd->resp.uresp.perf_hw_info.pref_format1; 1771 *fmt2 = cmd->resp.uresp.perf_hw_info.pref_format2; 1772 dev_dbg(psp->adev->dev, "PTL query: state=%d, fmt1=%d, fmt2=%d\n", 1773 *ptl_state, *fmt1, *fmt2); 1774 break; 1775 case PSP_PTL_PERF_MON_SET: 1776 /* Update cached state only on success */ 1777 ptl->enabled = *ptl_state; 1778 ptl->fmt1 = *fmt1; 1779 ptl->fmt2 = *fmt2; 1780 dev_dbg(psp->adev->dev, "PTL set: state=%d, fmt1=%d, fmt2=%d\n", 1781 *ptl_state, *fmt1, *fmt2); 1782 break; 1783 } 1784 1785 out: 1786 release_psp_cmd_buf(psp); 1787 return ret; 1788 } 1789 1790 int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, 1791 uint32_t *ptl_state, 1792 enum amdgpu_ptl_fmt *fmt1, 1793 enum amdgpu_ptl_fmt *fmt2) 1794 { 1795 uint32_t ptl_fmt1, ptl_fmt2; 1796 struct psp_context *psp; 1797 struct amdgpu_ptl *ptl; 1798 int ret; 1799 1800 if (!adev || !ptl_state || !fmt1 || !fmt2) 1801 return -EINVAL; 1802 1803 psp = &adev->psp; 1804 ptl = &psp->ptl; 1805 1806 if (ptl->permanently_disabled && *ptl_state == 1) 1807 return 0; 1808 1809 if (amdgpu_sriov_vf(adev)) { 1810 ptl_fmt1 = *fmt1; 1811 ptl_fmt2 = *fmt2; 1812 return psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); 1813 } 1814 1815 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) || 1816 psp->sos.fw_version < 0x0036081a) 1817 return -EOPNOTSUPP; 1818 1819 /* Verify formats */ 1820 if (psp_ptl_fmt_verify(psp, *fmt1, &ptl_fmt1) || 1821 psp_ptl_fmt_verify(psp, *fmt2, &ptl_fmt2)) 1822 return -EINVAL; 1823 1824 /* 1825 * Add check to skip if state and formats are identical to current ones 1826 */ 1827 if (req_code == PSP_PTL_PERF_MON_SET && 1828 ptl->enabled == *ptl_state && 1829 ptl->fmt1 == ptl_fmt1 && 1830 ptl->fmt2 == ptl_fmt2) 1831 return 0; 1832 1833 /* If enabling PTL, check disable bitmap */ 1834 if (req_code == PSP_PTL_PERF_MON_SET && *ptl_state == 1) { 1835 if (!bitmap_empty(ptl->disable_bitmap, 1836 AMDGPU_PTL_DISABLE_MAX)) { 1837 dev_dbg(adev->dev, 1838 "PTL enable blocked: SYSFS=%d, PROFILER=%d (ref=%d)\n", 1839 test_bit(AMDGPU_PTL_DISABLE_SYSFS, 1840 ptl->disable_bitmap), 1841 test_bit(AMDGPU_PTL_DISABLE_PROFILER, 1842 ptl->disable_bitmap), 1843 atomic_read(&ptl->disable_ref)); 1844 return 0; 1845 } 1846 } 1847 1848 if (req_code == PSP_PTL_PERF_MON_SET) { 1849 amdgpu_amdkfd_stop_sched_all(adev); 1850 /* Wait for GFX engine idle before PTL state transition */ 1851 ret = amdgpu_device_ip_wait_for_idle(adev, 1852 AMD_IP_BLOCK_TYPE_GFX); 1853 if (ret) { 1854 amdgpu_amdkfd_start_sched_all(adev); 1855 dev_err(adev->dev, "GFX not idle before PTL operation (%d)\n", ret); 1856 return ret; 1857 } 1858 ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); 1859 amdgpu_amdkfd_start_sched_all(adev); 1860 } else { 1861 ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); 1862 } 1863 1864 return ret; 1865 } 1866 1867 static enum amdgpu_ptl_fmt str_to_ptl_fmt(const char *str) 1868 { 1869 int i; 1870 1871 for (i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) { 1872 if (!strcmp(str, amdgpu_ptl_fmt_str[i])) 1873 return (enum amdgpu_ptl_fmt)i; 1874 } 1875 1876 return AMDGPU_PTL_FMT_INVALID; 1877 } 1878 1879 static ssize_t ptl_supported_formats_show(struct device *dev, 1880 struct device_attribute *attr, char *buf) 1881 { 1882 ssize_t len = 0; 1883 1884 for (int i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) { 1885 const char *fmt = amdgpu_ptl_fmt_str[i]; 1886 1887 len += sysfs_emit_at(buf, len, "%s%s", 1888 fmt ? fmt : "UNKNOWN", 1889 (i < AMDGPU_PTL_FMT_INVALID - 1) ? "," : "\n"); 1890 } 1891 1892 return len; 1893 } 1894 1895 static ssize_t ptl_enable_store(struct device *dev, 1896 struct device_attribute *attr, 1897 const char *buf, size_t count) 1898 { 1899 struct drm_device *ddev = dev_get_drvdata(dev); 1900 struct amdgpu_device *adev = drm_to_adev(ddev); 1901 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1902 uint32_t ptl_state, fmt1, fmt2; 1903 int ret; 1904 bool enable; 1905 bool bit_changed = false; 1906 1907 mutex_lock(&ptl->mutex); 1908 if (sysfs_streq(buf, "enabled") || sysfs_streq(buf, "1")) { 1909 enable = true; 1910 } else if (sysfs_streq(buf, "disabled") || sysfs_streq(buf, "0")) { 1911 enable = false; 1912 } else { 1913 mutex_unlock(&ptl->mutex); 1914 return -EINVAL; 1915 } 1916 1917 /* Block enable when permanently disabled */ 1918 if (ptl->permanently_disabled) { 1919 mutex_unlock(&ptl->mutex); 1920 return -EPERM; 1921 } 1922 1923 fmt1 = ptl->fmt1; 1924 fmt2 = ptl->fmt2; 1925 ptl_state = enable ? 1 : 0; 1926 1927 if (enable) 1928 bit_changed = test_and_clear_bit(AMDGPU_PTL_DISABLE_SYSFS, 1929 ptl->disable_bitmap); 1930 1931 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); 1932 if (ret) { 1933 dev_err(adev->dev, "Failed to set PTL err = %d\n", ret); 1934 if (enable && bit_changed) 1935 set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); 1936 mutex_unlock(&ptl->mutex); 1937 return ret; 1938 } 1939 1940 if (!enable) 1941 set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); 1942 1943 mutex_unlock(&ptl->mutex); 1944 1945 return count; 1946 } 1947 1948 static ssize_t ptl_enable_show(struct device *dev, struct device_attribute *attr, char *buf) 1949 { 1950 struct drm_device *ddev = dev_get_drvdata(dev); 1951 struct amdgpu_device *adev = drm_to_adev(ddev); 1952 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1953 uint32_t ptl_state, fmt1, fmt2; 1954 int ret; 1955 1956 if (amdgpu_sriov_vf(adev)) { 1957 ptl_state = ptl->enabled; 1958 fmt1 = ptl->fmt1; 1959 fmt2 = ptl->fmt2; 1960 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_QUERY, 1961 &ptl_state, &fmt1, &fmt2); 1962 if (ret) 1963 return ret; 1964 } 1965 1966 if (ptl->permanently_disabled) 1967 return sysfs_emit(buf, "permanently disabled\n"); 1968 1969 return sysfs_emit(buf, "%s\n", ptl->enabled ? "enabled" : "disabled"); 1970 } 1971 1972 static ssize_t ptl_format_store(struct device *dev, 1973 struct device_attribute *attr, 1974 const char *buf, size_t count) 1975 { 1976 struct drm_device *ddev = dev_get_drvdata(dev); 1977 struct amdgpu_device *adev = drm_to_adev(ddev); 1978 char fmt1_str[8], fmt2_str[8]; 1979 enum amdgpu_ptl_fmt fmt1_enum, fmt2_enum; 1980 struct amdgpu_ptl *ptl = &adev->psp.ptl; 1981 uint32_t ptl_state, fmt1, fmt2; 1982 int ret; 1983 1984 /* Only allow format update when PTL is enabled */ 1985 if (!ptl->enabled) 1986 return -EPERM; 1987 1988 mutex_lock(&ptl->mutex); 1989 /* Parse input, expecting "FMT1,FMT2" */ 1990 if (sscanf(buf, "%7[^,],%7s", fmt1_str, fmt2_str) != 2) { 1991 mutex_unlock(&ptl->mutex); 1992 return -EINVAL; 1993 } 1994 1995 fmt1_enum = str_to_ptl_fmt(fmt1_str); 1996 fmt2_enum = str_to_ptl_fmt(fmt2_str); 1997 1998 if (fmt1_enum >= AMDGPU_PTL_FMT_INVALID || 1999 fmt2_enum >= AMDGPU_PTL_FMT_INVALID || 2000 fmt1_enum == fmt2_enum) { 2001 mutex_unlock(&ptl->mutex); 2002 return -EINVAL; 2003 } 2004 2005 ptl_state = ptl->enabled; 2006 fmt1 = fmt1_enum; 2007 fmt2 = fmt2_enum; 2008 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); 2009 if (ret) { 2010 dev_err(adev->dev, "Failed to update PTL err = %d\n", ret); 2011 mutex_unlock(&ptl->mutex); 2012 return ret; 2013 } 2014 mutex_unlock(&ptl->mutex); 2015 2016 return count; 2017 } 2018 2019 static ssize_t ptl_format_show(struct device *dev, struct device_attribute *attr, char *buf) 2020 { 2021 struct drm_device *ddev = dev_get_drvdata(dev); 2022 struct amdgpu_device *adev = drm_to_adev(ddev); 2023 struct amdgpu_ptl *ptl = &adev->psp.ptl; 2024 uint32_t ptl_state, fmt1, fmt2; 2025 int ret; 2026 2027 if (amdgpu_sriov_vf(adev)) { 2028 ptl_state = ptl->enabled; 2029 fmt1 = ptl->fmt1; 2030 fmt2 = ptl->fmt2; 2031 ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_QUERY, 2032 &ptl_state, &fmt1, &fmt2); 2033 if (ret) 2034 return ret; 2035 } 2036 2037 return sysfs_emit(buf, "%s,%s\n", 2038 amdgpu_ptl_fmt_str[ptl->fmt1], 2039 amdgpu_ptl_fmt_str[ptl->fmt2]); 2040 } 2041 2042 static umode_t amdgpu_ptl_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 2043 { 2044 struct device *dev = kobj_to_dev(kobj); 2045 struct drm_device *ddev = dev_get_drvdata(dev); 2046 struct amdgpu_device *adev = drm_to_adev(ddev); 2047 2048 /* Only show PTL sysfs files if PTL hardware is supported */ 2049 if (adev->psp.ptl.hw_supported_state != AMDGPU_PTL_HW_SUPPORTED) 2050 return 0; 2051 2052 return attr->mode; 2053 } 2054 2055 int amdgpu_ptl_sysfs_init(struct amdgpu_device *adev) 2056 { 2057 struct amdgpu_ptl *ptl = &adev->psp.ptl; 2058 int ret; 2059 2060 if (ptl->hw_supported_state != AMDGPU_PTL_HW_SUPPORTED) 2061 return 0; 2062 2063 if (ptl->ptl_sysfs_created) 2064 return 0; 2065 2066 ret = sysfs_create_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); 2067 if (!ret) 2068 ptl->ptl_sysfs_created = true; 2069 2070 return ret; 2071 } 2072 2073 void amdgpu_ptl_sysfs_fini(struct amdgpu_device *adev) 2074 { 2075 struct amdgpu_ptl *ptl = &adev->psp.ptl; 2076 2077 if (ptl->hw_supported_state != AMDGPU_PTL_HW_SUPPORTED) 2078 return; 2079 2080 if (!ptl->ptl_sysfs_created) 2081 return; 2082 2083 sysfs_remove_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); 2084 ptl->ptl_sysfs_created = false; 2085 } 2086 2087 int psp_spatial_partition(struct psp_context *psp, int mode) 2088 { 2089 struct psp_gfx_cmd_resp *cmd; 2090 int ret; 2091 2092 if (amdgpu_sriov_vf(psp->adev)) 2093 return 0; 2094 2095 cmd = acquire_psp_cmd_buf(psp); 2096 2097 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART; 2098 cmd->cmd.cmd_spatial_part.mode = mode; 2099 2100 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode); 2101 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 2102 2103 release_psp_cmd_buf(psp); 2104 2105 return ret; 2106 } 2107 2108 static int psp_asd_initialize(struct psp_context *psp) 2109 { 2110 int ret; 2111 2112 /* If PSP version doesn't match ASD version, asd loading will be failed. 2113 * add workaround to bypass it for sriov now. 2114 * TODO: add version check to make it common 2115 */ 2116 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 2117 return 0; 2118 2119 /* bypass asd if display hardware is not available */ 2120 if (!amdgpu_device_has_display_hardware(psp->adev) && 2121 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= IP_VERSION(13, 0, 10)) 2122 return 0; 2123 2124 psp->asd_context.mem_context.shared_mc_addr = 0; 2125 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 2126 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 2127 2128 ret = psp_ta_load(psp, &psp->asd_context); 2129 if (!ret) 2130 psp->asd_context.initialized = true; 2131 2132 return ret; 2133 } 2134 2135 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 2136 uint32_t session_id) 2137 { 2138 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 2139 cmd->cmd.cmd_unload_ta.session_id = session_id; 2140 } 2141 2142 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 2143 { 2144 int ret; 2145 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2146 2147 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 2148 2149 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 2150 2151 context->resp_status = cmd->resp.status; 2152 2153 release_psp_cmd_buf(psp); 2154 2155 return ret; 2156 } 2157 2158 static int psp_asd_terminate(struct psp_context *psp) 2159 { 2160 int ret; 2161 2162 if (amdgpu_sriov_vf(psp->adev)) 2163 return 0; 2164 2165 if (!psp->asd_context.initialized) 2166 return 0; 2167 2168 ret = psp_ta_unload(psp, &psp->asd_context); 2169 if (!ret) 2170 psp->asd_context.initialized = false; 2171 2172 return ret; 2173 } 2174 2175 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 2176 uint32_t id, uint32_t value) 2177 { 2178 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 2179 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 2180 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 2181 } 2182 2183 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 2184 uint32_t value) 2185 { 2186 struct psp_gfx_cmd_resp *cmd; 2187 int ret = 0; 2188 2189 if (reg >= PSP_REG_LAST) 2190 return -EINVAL; 2191 2192 cmd = acquire_psp_cmd_buf(psp); 2193 2194 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 2195 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 2196 if (ret) 2197 dev_err(psp->adev->dev, "PSP failed to program reg id %d\n", reg); 2198 2199 release_psp_cmd_buf(psp); 2200 2201 return ret; 2202 } 2203 2204 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 2205 uint64_t ta_bin_mc, 2206 struct ta_context *context) 2207 { 2208 cmd->cmd_id = context->ta_load_type; 2209 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 2210 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 2211 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 2212 2213 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 2214 lower_32_bits(context->mem_context.shared_mc_addr); 2215 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 2216 upper_32_bits(context->mem_context.shared_mc_addr); 2217 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 2218 } 2219 2220 int psp_ta_init_shared_buf(struct psp_context *psp, 2221 struct ta_mem_context *mem_ctx) 2222 { 2223 /* 2224 * Allocate 16k memory aligned to 4k from Frame Buffer (local 2225 * physical) for ta to host memory 2226 */ 2227 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 2228 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | 2229 AMDGPU_GEM_DOMAIN_GTT, 2230 &mem_ctx->shared_bo, 2231 &mem_ctx->shared_mc_addr, 2232 &mem_ctx->shared_buf); 2233 } 2234 2235 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 2236 uint32_t ta_cmd_id, 2237 uint32_t session_id) 2238 { 2239 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 2240 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 2241 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 2242 } 2243 2244 int psp_ta_invoke(struct psp_context *psp, 2245 uint32_t ta_cmd_id, 2246 struct ta_context *context) 2247 { 2248 int ret; 2249 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2250 2251 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 2252 2253 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2254 psp->fence_buf_mc_addr); 2255 2256 context->resp_status = cmd->resp.status; 2257 2258 release_psp_cmd_buf(psp); 2259 2260 return ret; 2261 } 2262 2263 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 2264 { 2265 int ret; 2266 struct psp_gfx_cmd_resp *cmd; 2267 2268 cmd = acquire_psp_cmd_buf(psp); 2269 2270 ret = psp_copy_fw(psp, context->bin_desc.start_addr, 2271 context->bin_desc.size_bytes); 2272 if (ret) { 2273 release_psp_cmd_buf(psp); 2274 return ret; 2275 } 2276 2277 if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && 2278 context->mem_context.shared_bo) 2279 context->mem_context.shared_mc_addr = 2280 amdgpu_bo_fb_aper_addr(context->mem_context.shared_bo); 2281 2282 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 2283 2284 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2285 psp->fence_buf_mc_addr); 2286 2287 context->resp_status = cmd->resp.status; 2288 2289 if (!ret) 2290 context->session_id = cmd->resp.session_id; 2291 2292 release_psp_cmd_buf(psp); 2293 2294 return ret; 2295 } 2296 2297 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2298 { 2299 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 2300 } 2301 2302 int psp_xgmi_terminate(struct psp_context *psp) 2303 { 2304 int ret; 2305 struct amdgpu_device *adev = psp->adev; 2306 2307 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 2308 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 2309 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) && 2310 adev->gmc.xgmi.connected_to_cpu)) 2311 return 0; 2312 2313 if (!psp->xgmi_context.context.initialized) 2314 return 0; 2315 2316 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 2317 2318 psp->xgmi_context.context.initialized = false; 2319 2320 return ret; 2321 } 2322 2323 bool psp_is_xgmi_ta_supported(struct psp_context *psp) 2324 { 2325 return psp->ta_fw && 2326 psp->xgmi_context.context.bin_desc.size_bytes && 2327 psp->xgmi_context.context.bin_desc.start_addr; 2328 } 2329 2330 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 2331 { 2332 struct ta_xgmi_shared_memory *xgmi_cmd; 2333 int ret; 2334 2335 if (!psp_is_xgmi_ta_supported(psp)) 2336 return -ENOENT; 2337 2338 if (!load_ta) 2339 goto invoke; 2340 2341 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 2342 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2343 2344 if (!psp->xgmi_context.context.mem_context.shared_buf) { 2345 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 2346 if (ret) 2347 return ret; 2348 } 2349 2350 /* Load XGMI TA */ 2351 ret = psp_ta_load(psp, &psp->xgmi_context.context); 2352 if (!ret) 2353 psp->xgmi_context.context.initialized = true; 2354 else 2355 return ret; 2356 2357 invoke: 2358 /* Initialize XGMI session */ 2359 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 2360 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 2361 xgmi_cmd->flag_extend_link_record = set_extended_data; 2362 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 2363 2364 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 2365 /* note down the capbility flag for XGMI TA */ 2366 psp->xgmi_context.xgmi_ta_caps = xgmi_cmd->caps_flag; 2367 2368 if (!amdgpu_sriov_vf(psp->adev)) 2369 psp->xgmi_context.supports_ext_link_info = psp->xgmi_context.xgmi_ta_caps & 2370 EXTEND_PEER_LINK_INFO_CMD_FLAG; 2371 else 2372 psp->xgmi_context.supports_ext_link_info = amdgpu_sriov_xgmi_ta_ext_peer_link_en(psp->adev); 2373 2374 return ret; 2375 } 2376 2377 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 2378 { 2379 struct ta_xgmi_shared_memory *xgmi_cmd; 2380 int ret; 2381 2382 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 2383 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 2384 2385 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 2386 2387 /* Invoke xgmi ta to get hive id */ 2388 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 2389 if (ret) 2390 return ret; 2391 2392 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 2393 2394 return 0; 2395 } 2396 2397 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 2398 { 2399 struct ta_xgmi_shared_memory *xgmi_cmd; 2400 int ret; 2401 2402 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 2403 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 2404 2405 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 2406 2407 /* Invoke xgmi ta to get the node id */ 2408 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 2409 if (ret) 2410 return ret; 2411 2412 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 2413 2414 return 0; 2415 } 2416 2417 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 2418 { 2419 return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 2420 IP_VERSION(13, 0, 2) && 2421 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) || 2422 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= 2423 IP_VERSION(13, 0, 6); 2424 } 2425 2426 /* 2427 * Chips that support extended topology information require the driver to 2428 * reflect topology information in the opposite direction. This is 2429 * because the TA has already exceeded its link record limit and if the 2430 * TA holds bi-directional information, the driver would have to do 2431 * multiple fetches instead of just two. 2432 */ 2433 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 2434 struct psp_xgmi_node_info node_info) 2435 { 2436 struct amdgpu_device *mirror_adev; 2437 struct amdgpu_hive_info *hive; 2438 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 2439 uint64_t dst_node_id = node_info.node_id; 2440 uint8_t dst_num_hops = node_info.num_hops; 2441 uint8_t dst_is_sharing_enabled = node_info.is_sharing_enabled; 2442 uint8_t dst_num_links = node_info.num_links; 2443 2444 hive = amdgpu_get_xgmi_hive(psp->adev); 2445 if (WARN_ON(!hive)) 2446 return; 2447 2448 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 2449 struct psp_xgmi_topology_info *mirror_top_info; 2450 int j; 2451 2452 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 2453 continue; 2454 2455 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 2456 for (j = 0; j < mirror_top_info->num_nodes; j++) { 2457 if (mirror_top_info->nodes[j].node_id != src_node_id) 2458 continue; 2459 2460 mirror_top_info->nodes[j].num_hops = dst_num_hops; 2461 mirror_top_info->nodes[j].is_sharing_enabled = dst_is_sharing_enabled; 2462 /* prevent 0 num_links value re-reflection since reflection 2463 * criteria is based on num_hops (direct or indirect). 2464 */ 2465 if (dst_num_links) { 2466 mirror_top_info->nodes[j].num_links = dst_num_links; 2467 /* swap src and dst due to frame of reference */ 2468 for (int k = 0; k < dst_num_links; k++) { 2469 mirror_top_info->nodes[j].port_num[k].src_xgmi_port_num = 2470 node_info.port_num[k].dst_xgmi_port_num; 2471 mirror_top_info->nodes[j].port_num[k].dst_xgmi_port_num = 2472 node_info.port_num[k].src_xgmi_port_num; 2473 } 2474 } 2475 2476 break; 2477 } 2478 2479 break; 2480 } 2481 2482 amdgpu_put_xgmi_hive(hive); 2483 } 2484 2485 int psp_xgmi_get_topology_info(struct psp_context *psp, 2486 int number_devices, 2487 struct psp_xgmi_topology_info *topology, 2488 bool get_extended_data) 2489 { 2490 struct ta_xgmi_shared_memory *xgmi_cmd; 2491 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 2492 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 2493 int i; 2494 int ret; 2495 2496 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 2497 return -EINVAL; 2498 2499 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 2500 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 2501 xgmi_cmd->flag_extend_link_record = get_extended_data; 2502 2503 /* Fill in the shared memory with topology information as input */ 2504 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 2505 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_TOPOLOGY_INFO; 2506 topology_info_input->num_nodes = number_devices; 2507 2508 for (i = 0; i < topology_info_input->num_nodes; i++) { 2509 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 2510 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 2511 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 2512 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 2513 } 2514 2515 /* Invoke xgmi ta to get the topology information */ 2516 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_TOPOLOGY_INFO); 2517 if (ret) 2518 return ret; 2519 2520 /* Read the output topology information from the shared memory */ 2521 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 2522 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 2523 for (i = 0; i < topology->num_nodes; i++) { 2524 /* extended data will either be 0 or equal to non-extended data */ 2525 if (topology_info_output->nodes[i].num_hops) 2526 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 2527 2528 /* non-extended data gets everything here so no need to update */ 2529 if (!get_extended_data) { 2530 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 2531 topology->nodes[i].is_sharing_enabled = 2532 topology_info_output->nodes[i].is_sharing_enabled; 2533 topology->nodes[i].sdma_engine = 2534 topology_info_output->nodes[i].sdma_engine; 2535 } 2536 2537 } 2538 2539 /* Invoke xgmi ta again to get the link information */ 2540 if (psp_xgmi_peer_link_info_supported(psp)) { 2541 struct ta_xgmi_cmd_get_peer_link_info *link_info_output; 2542 struct ta_xgmi_cmd_get_extend_peer_link_info *link_extend_info_output; 2543 bool requires_reflection = 2544 (psp->xgmi_context.supports_extended_data && 2545 get_extended_data) || 2546 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 2547 IP_VERSION(13, 0, 6) || 2548 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == 2549 IP_VERSION(13, 0, 14) || 2550 amdgpu_sriov_vf(psp->adev); 2551 2552 /* popluate the shared output buffer rather than the cmd input buffer 2553 * with node_ids as the input for GET_PEER_LINKS command execution. 2554 * This is required for GET_PEER_LINKS per xgmi ta implementation. 2555 * The same requirement for GET_EXTEND_PEER_LINKS command. 2556 */ 2557 if (psp->xgmi_context.supports_ext_link_info) { 2558 link_extend_info_output = &xgmi_cmd->xgmi_out_message.get_extend_link_info; 2559 2560 for (i = 0; i < topology->num_nodes; i++) 2561 link_extend_info_output->nodes[i].node_id = topology->nodes[i].node_id; 2562 2563 link_extend_info_output->num_nodes = topology->num_nodes; 2564 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_EXTEND_PEER_LINKS; 2565 } else { 2566 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 2567 2568 for (i = 0; i < topology->num_nodes; i++) 2569 link_info_output->nodes[i].node_id = topology->nodes[i].node_id; 2570 2571 link_info_output->num_nodes = topology->num_nodes; 2572 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 2573 } 2574 2575 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 2576 if (ret) 2577 return ret; 2578 2579 for (i = 0; i < topology->num_nodes; i++) { 2580 uint8_t node_num_links = psp->xgmi_context.supports_ext_link_info ? 2581 link_extend_info_output->nodes[i].num_links : link_info_output->nodes[i].num_links; 2582 /* accumulate num_links on extended data */ 2583 if (get_extended_data) { 2584 topology->nodes[i].num_links = topology->nodes[i].num_links + node_num_links; 2585 } else { 2586 topology->nodes[i].num_links = (requires_reflection && topology->nodes[i].num_links) ? 2587 topology->nodes[i].num_links : node_num_links; 2588 } 2589 /* popluate the connected port num info if supported and available */ 2590 if (psp->xgmi_context.supports_ext_link_info && topology->nodes[i].num_links) { 2591 memcpy(topology->nodes[i].port_num, link_extend_info_output->nodes[i].port_num, 2592 sizeof(struct xgmi_connected_port_num) * TA_XGMI__MAX_PORT_NUM); 2593 } 2594 2595 /* reflect the topology information for bi-directionality */ 2596 if (requires_reflection && topology->nodes[i].num_hops) 2597 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 2598 } 2599 } 2600 2601 return 0; 2602 } 2603 2604 int psp_xgmi_set_topology_info(struct psp_context *psp, 2605 int number_devices, 2606 struct psp_xgmi_topology_info *topology) 2607 { 2608 struct ta_xgmi_shared_memory *xgmi_cmd; 2609 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 2610 int i; 2611 2612 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 2613 return -EINVAL; 2614 2615 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 2616 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 2617 2618 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 2619 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 2620 topology_info_input->num_nodes = number_devices; 2621 2622 for (i = 0; i < topology_info_input->num_nodes; i++) { 2623 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 2624 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 2625 topology_info_input->nodes[i].is_sharing_enabled = 1; 2626 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 2627 } 2628 2629 /* Invoke xgmi ta to set topology information */ 2630 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 2631 } 2632 2633 // ras begin 2634 static void psp_ras_ta_check_status(struct psp_context *psp) 2635 { 2636 struct ta_ras_shared_memory *ras_cmd = 2637 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2638 2639 switch (ras_cmd->ras_status) { 2640 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 2641 dev_warn(psp->adev->dev, 2642 "RAS WARNING: cmd failed due to unsupported ip\n"); 2643 break; 2644 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 2645 dev_warn(psp->adev->dev, 2646 "RAS WARNING: cmd failed due to unsupported error injection\n"); 2647 break; 2648 case TA_RAS_STATUS__SUCCESS: 2649 break; 2650 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 2651 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 2652 dev_warn(psp->adev->dev, 2653 "RAS WARNING: Inject error to critical region is not allowed\n"); 2654 break; 2655 default: 2656 dev_warn(psp->adev->dev, 2657 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 2658 break; 2659 } 2660 } 2661 2662 static int psp_ras_send_cmd(struct psp_context *psp, 2663 enum ras_command cmd_id, void *in, void *out) 2664 { 2665 struct ta_ras_shared_memory *ras_cmd; 2666 uint32_t cmd = cmd_id; 2667 int ret = 0; 2668 2669 if (!in) 2670 return -EINVAL; 2671 2672 mutex_lock(&psp->ras_context.mutex); 2673 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2674 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 2675 2676 switch (cmd) { 2677 case TA_RAS_COMMAND__ENABLE_FEATURES: 2678 case TA_RAS_COMMAND__DISABLE_FEATURES: 2679 memcpy(&ras_cmd->ras_in_message, 2680 in, sizeof(ras_cmd->ras_in_message)); 2681 break; 2682 case TA_RAS_COMMAND__TRIGGER_ERROR: 2683 memcpy(&ras_cmd->ras_in_message.trigger_error, 2684 in, sizeof(ras_cmd->ras_in_message.trigger_error)); 2685 break; 2686 case TA_RAS_COMMAND__QUERY_ADDRESS: 2687 memcpy(&ras_cmd->ras_in_message.address, 2688 in, sizeof(ras_cmd->ras_in_message.address)); 2689 break; 2690 default: 2691 dev_err(psp->adev->dev, "Invalid ras cmd id: %u\n", cmd); 2692 ret = -EINVAL; 2693 goto err_out; 2694 } 2695 2696 ras_cmd->cmd_id = cmd; 2697 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 2698 2699 switch (cmd) { 2700 case TA_RAS_COMMAND__TRIGGER_ERROR: 2701 if (!ret && out) 2702 memcpy(out, &ras_cmd->ras_status, sizeof(ras_cmd->ras_status)); 2703 break; 2704 case TA_RAS_COMMAND__QUERY_ADDRESS: 2705 if (ret || ras_cmd->ras_status || psp->cmd_resp_buf_mem->resp.status) 2706 ret = -EINVAL; 2707 else if (out) 2708 memcpy(out, 2709 &ras_cmd->ras_out_message.address, 2710 sizeof(ras_cmd->ras_out_message.address)); 2711 break; 2712 default: 2713 break; 2714 } 2715 2716 err_out: 2717 mutex_unlock(&psp->ras_context.mutex); 2718 2719 return ret; 2720 } 2721 2722 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2723 { 2724 struct ta_ras_shared_memory *ras_cmd; 2725 int ret; 2726 2727 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2728 2729 /* 2730 * TODO: bypass the loading in sriov for now 2731 */ 2732 if (amdgpu_sriov_vf(psp->adev)) 2733 return 0; 2734 2735 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 2736 2737 if (amdgpu_ras_intr_triggered()) 2738 return ret; 2739 2740 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { 2741 dev_warn(psp->adev->dev, "RAS: Unsupported Interface\n"); 2742 return -EINVAL; 2743 } 2744 2745 if (!ret) { 2746 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 2747 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 2748 2749 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 2750 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 2751 dev_warn(psp->adev->dev, 2752 "RAS internal register access blocked\n"); 2753 2754 psp_ras_ta_check_status(psp); 2755 } 2756 2757 return ret; 2758 } 2759 2760 int psp_ras_enable_features(struct psp_context *psp, 2761 union ta_ras_cmd_input *info, bool enable) 2762 { 2763 struct amdgpu_ras *con = amdgpu_ras_get_context(psp->adev); 2764 enum ras_command cmd_id; 2765 int ret; 2766 2767 if (con && con->uniras_load_ras_fw) 2768 return 0; 2769 2770 if (!psp->ras_context.context.initialized || !info) 2771 return -EINVAL; 2772 2773 cmd_id = enable ? 2774 TA_RAS_COMMAND__ENABLE_FEATURES : TA_RAS_COMMAND__DISABLE_FEATURES; 2775 ret = psp_ras_send_cmd(psp, cmd_id, info, NULL); 2776 if (ret) 2777 return -EINVAL; 2778 2779 return 0; 2780 } 2781 2782 int psp_ras_terminate(struct psp_context *psp) 2783 { 2784 int ret; 2785 2786 /* 2787 * TODO: bypass the terminate in sriov for now 2788 */ 2789 if (amdgpu_sriov_vf(psp->adev)) 2790 return 0; 2791 2792 if (!psp->ras_context.context.initialized) 2793 return 0; 2794 2795 ret = psp_ta_unload(psp, &psp->ras_context.context); 2796 2797 psp->ras_context.context.initialized = false; 2798 2799 mutex_destroy(&psp->ras_context.mutex); 2800 2801 return ret; 2802 } 2803 2804 int psp_ras_initialize(struct psp_context *psp) 2805 { 2806 int ret; 2807 uint32_t boot_cfg = 0xFF; 2808 struct amdgpu_device *adev = psp->adev; 2809 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2810 struct ta_ras_shared_memory *ras_cmd; 2811 2812 /* 2813 * TODO: bypass the initialize in sriov for now 2814 */ 2815 if (amdgpu_sriov_vf(adev)) 2816 return 0; 2817 2818 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 2819 !adev->psp.ras_context.context.bin_desc.start_addr) { 2820 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 2821 return 0; 2822 } 2823 2824 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 2825 /* query GECC enablement status from boot config 2826 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 2827 */ 2828 ret = psp_boot_config_get(adev, &boot_cfg); 2829 if (ret) 2830 dev_warn(adev->dev, "PSP get boot config failed\n"); 2831 2832 if (boot_cfg == 1 && !adev->ras_default_ecc_enabled && 2833 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 2834 dev_warn(adev->dev, "GECC is currently enabled, which may affect performance\n"); 2835 dev_warn(adev->dev, 2836 "To disable GECC, please reboot the system and load the amdgpu driver with the parameter amdgpu_ras_enable=0\n"); 2837 } else { 2838 if ((adev->ras_default_ecc_enabled || amdgpu_ras_enable == 1) && 2839 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 2840 if (boot_cfg == 1) { 2841 dev_info(adev->dev, "GECC is enabled\n"); 2842 } else { 2843 /* enable GECC in next boot cycle if it is disabled 2844 * in boot config, or force enable GECC if failed to 2845 * get boot configuration 2846 */ 2847 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 2848 if (ret) 2849 dev_warn(adev->dev, "PSP set boot config failed\n"); 2850 else 2851 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 2852 } 2853 } else { 2854 if (!boot_cfg) { 2855 if (!adev->ras_default_ecc_enabled && 2856 amdgpu_ras_enable != 1 && 2857 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 2858 dev_warn(adev->dev, "GECC is disabled, set amdgpu_ras_enable=1 to enable GECC in next boot cycle if needed\n"); 2859 else 2860 dev_info(adev->dev, "GECC is disabled\n"); 2861 } else { 2862 /* disable GECC in next boot cycle if ras is 2863 * disabled by module parameter amdgpu_ras_enable 2864 * and/or amdgpu_ras_mask, or boot_config_get call 2865 * is failed 2866 */ 2867 ret = psp_boot_config_set(adev, 0); 2868 if (ret) 2869 dev_warn(adev->dev, "PSP set boot config failed\n"); 2870 else 2871 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 2872 } 2873 } 2874 } 2875 } 2876 2877 if (con && con->uniras_load_ras_fw) 2878 return 0; 2879 2880 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 2881 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 2882 2883 if (!psp->ras_context.context.mem_context.shared_buf) { 2884 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 2885 if (ret) 2886 return ret; 2887 } 2888 2889 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 2890 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 2891 2892 if (amdgpu_ras_is_poison_mode_supported(adev)) 2893 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 2894 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 2895 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 2896 ras_cmd->ras_in_message.init_flags.xcc_mask = 2897 adev->gfx.xcc_mask; 2898 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; 2899 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 2900 ras_cmd->ras_in_message.init_flags.nps_mode = 2901 adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 2902 ras_cmd->ras_in_message.init_flags.active_umc_mask = lower_32_bits(adev->umc.active_mask); 2903 ras_cmd->ras_in_message.init_flags.vram_type = (uint8_t)adev->gmc.vram_type; 2904 ras_cmd->ras_in_message.init_flags.ext_umc_mask = upper_32_bits(adev->umc.active_mask); 2905 2906 ret = psp_ta_load(psp, &psp->ras_context.context); 2907 2908 if (!ret && !ras_cmd->ras_status) { 2909 psp->ras_context.context.initialized = true; 2910 mutex_init(&psp->ras_context.mutex); 2911 } else { 2912 if (ras_cmd->ras_status) 2913 dev_warn(adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 2914 2915 /* fail to load RAS TA */ 2916 psp->ras_context.context.initialized = false; 2917 } 2918 2919 return ret; 2920 } 2921 2922 int psp_ras_trigger_error(struct psp_context *psp, 2923 struct ta_ras_trigger_error_input *info, uint32_t instance_mask) 2924 { 2925 struct amdgpu_device *adev = psp->adev; 2926 int ret; 2927 uint32_t dev_mask; 2928 uint32_t ras_status = 0; 2929 2930 if (!psp->ras_context.context.initialized || !info) 2931 return -EINVAL; 2932 2933 switch (info->block_id) { 2934 case TA_RAS_BLOCK__GFX: 2935 dev_mask = GET_MASK(GC, instance_mask); 2936 break; 2937 case TA_RAS_BLOCK__SDMA: 2938 dev_mask = GET_MASK(SDMA0, instance_mask); 2939 break; 2940 case TA_RAS_BLOCK__VCN: 2941 case TA_RAS_BLOCK__JPEG: 2942 dev_mask = GET_MASK(VCN, instance_mask); 2943 break; 2944 default: 2945 dev_mask = instance_mask; 2946 break; 2947 } 2948 2949 /* reuse sub_block_index for backward compatibility */ 2950 dev_mask <<= AMDGPU_RAS_INST_SHIFT; 2951 dev_mask &= AMDGPU_RAS_INST_MASK; 2952 info->sub_block_index |= dev_mask; 2953 2954 ret = psp_ras_send_cmd(psp, 2955 TA_RAS_COMMAND__TRIGGER_ERROR, info, &ras_status); 2956 if (ret) 2957 return -EINVAL; 2958 2959 /* If err_event_athub occurs error inject was successful, however 2960 * return status from TA is no long reliable 2961 */ 2962 if (amdgpu_ras_intr_triggered()) 2963 return 0; 2964 2965 if (ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 2966 return -EACCES; 2967 else if (ras_status) 2968 return -EINVAL; 2969 2970 return 0; 2971 } 2972 2973 int psp_ras_query_address(struct psp_context *psp, 2974 struct ta_ras_query_address_input *addr_in, 2975 struct ta_ras_query_address_output *addr_out) 2976 { 2977 int ret; 2978 2979 if (!psp->ras_context.context.initialized || 2980 !addr_in || !addr_out) 2981 return -EINVAL; 2982 2983 ret = psp_ras_send_cmd(psp, 2984 TA_RAS_COMMAND__QUERY_ADDRESS, addr_in, addr_out); 2985 2986 return ret; 2987 } 2988 // ras end 2989 2990 // HDCP start 2991 static int psp_hdcp_initialize(struct psp_context *psp) 2992 { 2993 int ret; 2994 2995 /* 2996 * TODO: bypass the initialize in sriov for now 2997 */ 2998 if (amdgpu_sriov_vf(psp->adev)) 2999 return 0; 3000 3001 /* bypass hdcp initialization if dmu is harvested */ 3002 if (!amdgpu_device_has_display_hardware(psp->adev)) 3003 return 0; 3004 3005 if (!psp->hdcp_context.context.bin_desc.size_bytes || 3006 !psp->hdcp_context.context.bin_desc.start_addr) { 3007 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 3008 return 0; 3009 } 3010 3011 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 3012 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 3013 3014 if (!psp->hdcp_context.context.mem_context.shared_buf) { 3015 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 3016 if (ret) 3017 return ret; 3018 } 3019 3020 ret = psp_ta_load(psp, &psp->hdcp_context.context); 3021 if (!ret) { 3022 psp->hdcp_context.context.initialized = true; 3023 mutex_init(&psp->hdcp_context.mutex); 3024 } 3025 3026 return ret; 3027 } 3028 3029 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 3030 { 3031 /* 3032 * TODO: bypass the loading in sriov for now 3033 */ 3034 if (amdgpu_sriov_vf(psp->adev)) 3035 return 0; 3036 3037 if (!psp->hdcp_context.context.initialized) 3038 return 0; 3039 3040 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 3041 } 3042 3043 static int psp_hdcp_terminate(struct psp_context *psp) 3044 { 3045 int ret; 3046 3047 /* 3048 * TODO: bypass the terminate in sriov for now 3049 */ 3050 if (amdgpu_sriov_vf(psp->adev)) 3051 return 0; 3052 3053 if (!psp->hdcp_context.context.initialized) 3054 return 0; 3055 3056 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 3057 3058 psp->hdcp_context.context.initialized = false; 3059 3060 return ret; 3061 } 3062 // HDCP end 3063 3064 // DTM start 3065 static int psp_dtm_initialize(struct psp_context *psp) 3066 { 3067 int ret; 3068 3069 /* 3070 * TODO: bypass the initialize in sriov for now 3071 */ 3072 if (amdgpu_sriov_vf(psp->adev)) 3073 return 0; 3074 3075 /* bypass dtm initialization if dmu is harvested */ 3076 if (!amdgpu_device_has_display_hardware(psp->adev)) 3077 return 0; 3078 3079 if (!psp->dtm_context.context.bin_desc.size_bytes || 3080 !psp->dtm_context.context.bin_desc.start_addr) { 3081 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 3082 return 0; 3083 } 3084 3085 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 3086 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 3087 3088 if (!psp->dtm_context.context.mem_context.shared_buf) { 3089 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 3090 if (ret) 3091 return ret; 3092 } 3093 3094 ret = psp_ta_load(psp, &psp->dtm_context.context); 3095 if (!ret) { 3096 psp->dtm_context.context.initialized = true; 3097 mutex_init(&psp->dtm_context.mutex); 3098 } 3099 3100 return ret; 3101 } 3102 3103 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 3104 { 3105 /* 3106 * TODO: bypass the loading in sriov for now 3107 */ 3108 if (amdgpu_sriov_vf(psp->adev)) 3109 return 0; 3110 3111 if (!psp->dtm_context.context.initialized) 3112 return 0; 3113 3114 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 3115 } 3116 3117 static int psp_dtm_terminate(struct psp_context *psp) 3118 { 3119 int ret; 3120 3121 /* 3122 * TODO: bypass the terminate in sriov for now 3123 */ 3124 if (amdgpu_sriov_vf(psp->adev)) 3125 return 0; 3126 3127 if (!psp->dtm_context.context.initialized) 3128 return 0; 3129 3130 ret = psp_ta_unload(psp, &psp->dtm_context.context); 3131 3132 psp->dtm_context.context.initialized = false; 3133 3134 return ret; 3135 } 3136 // DTM end 3137 3138 // RAP start 3139 static int psp_rap_initialize(struct psp_context *psp) 3140 { 3141 int ret; 3142 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 3143 3144 /* 3145 * TODO: bypass the initialize in sriov for now 3146 */ 3147 if (amdgpu_sriov_vf(psp->adev)) 3148 return 0; 3149 3150 if (!psp->rap_context.context.bin_desc.size_bytes || 3151 !psp->rap_context.context.bin_desc.start_addr) { 3152 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 3153 return 0; 3154 } 3155 3156 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 3157 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 3158 3159 if (!psp->rap_context.context.mem_context.shared_buf) { 3160 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 3161 if (ret) 3162 return ret; 3163 } 3164 3165 ret = psp_ta_load(psp, &psp->rap_context.context); 3166 if (!ret) { 3167 psp->rap_context.context.initialized = true; 3168 mutex_init(&psp->rap_context.mutex); 3169 } else 3170 return ret; 3171 3172 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 3173 if (ret || status != TA_RAP_STATUS__SUCCESS) { 3174 psp_rap_terminate(psp); 3175 /* free rap shared memory */ 3176 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 3177 3178 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 3179 ret, status); 3180 3181 return ret; 3182 } 3183 3184 return 0; 3185 } 3186 3187 static int psp_rap_terminate(struct psp_context *psp) 3188 { 3189 int ret; 3190 3191 if (!psp->rap_context.context.initialized) 3192 return 0; 3193 3194 ret = psp_ta_unload(psp, &psp->rap_context.context); 3195 3196 psp->rap_context.context.initialized = false; 3197 3198 return ret; 3199 } 3200 3201 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 3202 { 3203 struct ta_rap_shared_memory *rap_cmd; 3204 int ret = 0; 3205 3206 if (!psp->rap_context.context.initialized) 3207 return 0; 3208 3209 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 3210 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 3211 return -EINVAL; 3212 3213 mutex_lock(&psp->rap_context.mutex); 3214 3215 rap_cmd = (struct ta_rap_shared_memory *) 3216 psp->rap_context.context.mem_context.shared_buf; 3217 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 3218 3219 rap_cmd->cmd_id = ta_cmd_id; 3220 rap_cmd->validation_method_id = METHOD_A; 3221 3222 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 3223 if (ret) 3224 goto out_unlock; 3225 3226 if (status) 3227 *status = rap_cmd->rap_status; 3228 3229 out_unlock: 3230 mutex_unlock(&psp->rap_context.mutex); 3231 3232 return ret; 3233 } 3234 // RAP end 3235 3236 /* securedisplay start */ 3237 static int psp_securedisplay_initialize(struct psp_context *psp) 3238 { 3239 int ret; 3240 struct ta_securedisplay_cmd *securedisplay_cmd; 3241 3242 /* 3243 * TODO: bypass the initialize in sriov for now 3244 */ 3245 if (amdgpu_sriov_vf(psp->adev)) 3246 return 0; 3247 3248 /* bypass securedisplay initialization if dmu is harvested */ 3249 if (!amdgpu_device_has_display_hardware(psp->adev)) 3250 return 0; 3251 3252 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 3253 !psp->securedisplay_context.context.bin_desc.start_addr) { 3254 dev_info(psp->adev->dev, 3255 "SECUREDISPLAY: optional securedisplay ta ucode is not available\n"); 3256 return 0; 3257 } 3258 3259 psp->securedisplay_context.context.mem_context.shared_mem_size = 3260 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 3261 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 3262 3263 if (!psp->securedisplay_context.context.initialized) { 3264 ret = psp_ta_init_shared_buf(psp, 3265 &psp->securedisplay_context.context.mem_context); 3266 if (ret) 3267 return ret; 3268 } 3269 3270 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 3271 if (!ret && !psp->securedisplay_context.context.resp_status) { 3272 psp->securedisplay_context.context.initialized = true; 3273 mutex_init(&psp->securedisplay_context.mutex); 3274 } else { 3275 /* don't try again */ 3276 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 3277 return ret; 3278 } 3279 3280 mutex_lock(&psp->securedisplay_context.mutex); 3281 3282 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 3283 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 3284 3285 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 3286 3287 mutex_unlock(&psp->securedisplay_context.mutex); 3288 3289 if (ret) { 3290 psp_securedisplay_terminate(psp); 3291 /* free securedisplay shared memory */ 3292 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 3293 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 3294 return -EINVAL; 3295 } 3296 3297 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 3298 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 3299 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 3300 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 3301 /* don't try again */ 3302 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 3303 } 3304 3305 return 0; 3306 } 3307 3308 static int psp_securedisplay_terminate(struct psp_context *psp) 3309 { 3310 int ret; 3311 3312 /* 3313 * TODO:bypass the terminate in sriov for now 3314 */ 3315 if (amdgpu_sriov_vf(psp->adev)) 3316 return 0; 3317 3318 if (!psp->securedisplay_context.context.initialized) 3319 return 0; 3320 3321 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 3322 3323 psp->securedisplay_context.context.initialized = false; 3324 3325 return ret; 3326 } 3327 3328 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 3329 { 3330 int ret; 3331 3332 if (!psp->securedisplay_context.context.initialized) 3333 return -EINVAL; 3334 3335 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 3336 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC && 3337 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC_V2) 3338 return -EINVAL; 3339 3340 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 3341 3342 return ret; 3343 } 3344 /* SECUREDISPLAY end */ 3345 3346 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev) 3347 { 3348 struct psp_context *psp = &adev->psp; 3349 int ret = 0; 3350 3351 if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL) 3352 ret = psp->funcs->wait_for_bootloader(psp); 3353 3354 return ret; 3355 } 3356 3357 bool amdgpu_psp_get_ras_capability(struct psp_context *psp) 3358 { 3359 if (psp->funcs && 3360 psp->funcs->get_ras_capability) { 3361 return psp->funcs->get_ras_capability(psp); 3362 } else { 3363 return false; 3364 } 3365 } 3366 3367 bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev) 3368 { 3369 struct psp_context *psp = &adev->psp; 3370 3371 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) 3372 return false; 3373 3374 if (psp->funcs && psp->funcs->is_reload_needed) 3375 return psp->funcs->is_reload_needed(psp); 3376 3377 return false; 3378 } 3379 3380 static void psp_update_gpu_addresses(struct amdgpu_device *adev) 3381 { 3382 struct psp_context *psp = &adev->psp; 3383 3384 if (psp->cmd_resp_buf_bo && psp->cmd_resp_buf_mem) { 3385 psp->fw_pri_mc_addr = amdgpu_bo_fb_aper_addr(psp->fw_pri_bo); 3386 psp->fence_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->fence_buf_bo); 3387 psp->cmd_resp_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->cmd_resp_buf_bo); 3388 psp->cmd_ext_resp_mc_addr = psp->cmd_resp_buf_mc_addr + 3389 sizeof(struct psp_gfx_cmd_resp); 3390 } 3391 if (adev->firmware.rbuf && psp->km_ring.ring_mem) 3392 psp->km_ring.ring_mem_mc_addr = amdgpu_bo_fb_aper_addr(adev->firmware.rbuf); 3393 } 3394 3395 static int psp_hw_start(struct psp_context *psp) 3396 { 3397 struct amdgpu_device *adev = psp->adev; 3398 int ret; 3399 3400 if (amdgpu_virt_xgmi_migrate_enabled(adev)) 3401 psp_update_gpu_addresses(adev); 3402 3403 if (!amdgpu_sriov_vf(adev)) { 3404 if ((is_psp_fw_valid(psp->kdb)) && 3405 (psp->funcs->bootloader_load_kdb != NULL)) { 3406 ret = psp_bootloader_load_kdb(psp); 3407 if (ret) { 3408 dev_err(adev->dev, "PSP load kdb failed!\n"); 3409 return ret; 3410 } 3411 } 3412 3413 if ((is_psp_fw_valid(psp->spl)) && 3414 (psp->funcs->bootloader_load_spl != NULL)) { 3415 ret = psp_bootloader_load_spl(psp); 3416 if (ret) { 3417 dev_err(adev->dev, "PSP load spl failed!\n"); 3418 return ret; 3419 } 3420 } 3421 3422 if ((is_psp_fw_valid(psp->sys)) && 3423 (psp->funcs->bootloader_load_sysdrv != NULL)) { 3424 ret = psp_bootloader_load_sysdrv(psp); 3425 if (ret) { 3426 dev_err(adev->dev, "PSP load sys drv failed!\n"); 3427 return ret; 3428 } 3429 } 3430 3431 if ((is_psp_fw_valid(psp->soc_drv)) && 3432 (psp->funcs->bootloader_load_soc_drv != NULL)) { 3433 ret = psp_bootloader_load_soc_drv(psp); 3434 if (ret) { 3435 dev_err(adev->dev, "PSP load soc drv failed!\n"); 3436 return ret; 3437 } 3438 } 3439 3440 if ((is_psp_fw_valid(psp->intf_drv)) && 3441 (psp->funcs->bootloader_load_intf_drv != NULL)) { 3442 ret = psp_bootloader_load_intf_drv(psp); 3443 if (ret) { 3444 dev_err(adev->dev, "PSP load intf drv failed!\n"); 3445 return ret; 3446 } 3447 } 3448 3449 if ((is_psp_fw_valid(psp->dbg_drv)) && 3450 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 3451 ret = psp_bootloader_load_dbg_drv(psp); 3452 if (ret) { 3453 dev_err(adev->dev, "PSP load dbg drv failed!\n"); 3454 return ret; 3455 } 3456 } 3457 3458 if ((is_psp_fw_valid(psp->ras_drv)) && 3459 (psp->funcs->bootloader_load_ras_drv != NULL)) { 3460 ret = psp_bootloader_load_ras_drv(psp); 3461 if (ret) { 3462 dev_err(adev->dev, "PSP load ras_drv failed!\n"); 3463 return ret; 3464 } 3465 } 3466 3467 if ((is_psp_fw_valid(psp->ipkeymgr_drv)) && 3468 (psp->funcs->bootloader_load_ipkeymgr_drv != NULL)) { 3469 ret = psp_bootloader_load_ipkeymgr_drv(psp); 3470 if (ret) { 3471 dev_err(adev->dev, "PSP load ipkeymgr_drv failed!\n"); 3472 return ret; 3473 } 3474 } 3475 3476 if ((is_psp_fw_valid(psp->spdm_drv)) && 3477 (psp->funcs->bootloader_load_spdm_drv != NULL)) { 3478 ret = psp_bootloader_load_spdm_drv(psp); 3479 if (ret) { 3480 dev_err(adev->dev, "PSP load spdm_drv failed!\n"); 3481 return ret; 3482 } 3483 } 3484 3485 if ((is_psp_fw_valid(psp->sos)) && 3486 (psp->funcs->bootloader_load_sos != NULL)) { 3487 ret = psp_bootloader_load_sos(psp); 3488 if (ret) { 3489 dev_err(adev->dev, "PSP load sos failed!\n"); 3490 return ret; 3491 } 3492 } 3493 } 3494 3495 psp_irq_enable(psp); 3496 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 3497 if (ret) { 3498 dev_err(adev->dev, "PSP create ring failed!\n"); 3499 return ret; 3500 } 3501 3502 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3503 ret = psp_update_fw_reservation(psp); 3504 if (ret) { 3505 dev_err(adev->dev, "update fw reservation failed!\n"); 3506 return ret; 3507 } 3508 } 3509 3510 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 3511 goto skip_pin_bo; 3512 3513 if (!psp->boot_time_tmr || psp->autoload_supported) { 3514 ret = psp_tmr_init(psp); 3515 if (ret) { 3516 dev_err(adev->dev, "PSP tmr init failed!\n"); 3517 return ret; 3518 } 3519 } 3520 3521 skip_pin_bo: 3522 /* 3523 * For ASICs with DF Cstate management centralized 3524 * to PMFW, TMR setup should be performed after PMFW 3525 * loaded and before other non-psp firmware loaded. 3526 */ 3527 if (psp->pmfw_centralized_cstate_management) { 3528 ret = psp_load_smu_fw(psp); 3529 if (ret) 3530 return ret; 3531 } 3532 3533 ret = psp_tmr_load(psp); 3534 if (ret) { 3535 dev_err(adev->dev, "PSP load tmr failed!\n"); 3536 return ret; 3537 } 3538 3539 return 0; 3540 } 3541 3542 int amdgpu_psp_get_fw_type(struct amdgpu_firmware_info *ucode, 3543 enum psp_gfx_fw_type *type) 3544 { 3545 switch (ucode->ucode_id) { 3546 case AMDGPU_UCODE_ID_CAP: 3547 *type = GFX_FW_TYPE_CAP; 3548 break; 3549 case AMDGPU_UCODE_ID_SDMA0: 3550 *type = GFX_FW_TYPE_SDMA0; 3551 break; 3552 case AMDGPU_UCODE_ID_SDMA1: 3553 *type = GFX_FW_TYPE_SDMA1; 3554 break; 3555 case AMDGPU_UCODE_ID_SDMA2: 3556 *type = GFX_FW_TYPE_SDMA2; 3557 break; 3558 case AMDGPU_UCODE_ID_SDMA3: 3559 *type = GFX_FW_TYPE_SDMA3; 3560 break; 3561 case AMDGPU_UCODE_ID_SDMA4: 3562 *type = GFX_FW_TYPE_SDMA4; 3563 break; 3564 case AMDGPU_UCODE_ID_SDMA5: 3565 *type = GFX_FW_TYPE_SDMA5; 3566 break; 3567 case AMDGPU_UCODE_ID_SDMA6: 3568 *type = GFX_FW_TYPE_SDMA6; 3569 break; 3570 case AMDGPU_UCODE_ID_SDMA7: 3571 *type = GFX_FW_TYPE_SDMA7; 3572 break; 3573 case AMDGPU_UCODE_ID_CP_MES: 3574 *type = GFX_FW_TYPE_CP_MES; 3575 break; 3576 case AMDGPU_UCODE_ID_CP_MES_DATA: 3577 *type = GFX_FW_TYPE_MES_STACK; 3578 break; 3579 case AMDGPU_UCODE_ID_CP_MES1: 3580 *type = GFX_FW_TYPE_CP_MES_KIQ; 3581 break; 3582 case AMDGPU_UCODE_ID_CP_MES1_DATA: 3583 *type = GFX_FW_TYPE_MES_KIQ_STACK; 3584 break; 3585 case AMDGPU_UCODE_ID_CP_CE: 3586 *type = GFX_FW_TYPE_CP_CE; 3587 break; 3588 case AMDGPU_UCODE_ID_CP_PFP: 3589 *type = GFX_FW_TYPE_CP_PFP; 3590 break; 3591 case AMDGPU_UCODE_ID_CP_ME: 3592 *type = GFX_FW_TYPE_CP_ME; 3593 break; 3594 case AMDGPU_UCODE_ID_CP_MEC1: 3595 *type = GFX_FW_TYPE_CP_MEC; 3596 break; 3597 case AMDGPU_UCODE_ID_CP_MEC1_JT: 3598 *type = GFX_FW_TYPE_CP_MEC_ME1; 3599 break; 3600 case AMDGPU_UCODE_ID_CP_MEC2: 3601 *type = GFX_FW_TYPE_CP_MEC; 3602 break; 3603 case AMDGPU_UCODE_ID_CP_MEC2_JT: 3604 *type = GFX_FW_TYPE_CP_MEC_ME2; 3605 break; 3606 case AMDGPU_UCODE_ID_RLC_P: 3607 *type = GFX_FW_TYPE_RLC_P; 3608 break; 3609 case AMDGPU_UCODE_ID_RLC_V: 3610 *type = GFX_FW_TYPE_RLC_V; 3611 break; 3612 case AMDGPU_UCODE_ID_RLC_G: 3613 *type = GFX_FW_TYPE_RLC_G; 3614 break; 3615 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 3616 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 3617 break; 3618 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 3619 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 3620 break; 3621 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 3622 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 3623 break; 3624 case AMDGPU_UCODE_ID_RLC_IRAM: 3625 *type = GFX_FW_TYPE_RLC_IRAM; 3626 break; 3627 case AMDGPU_UCODE_ID_RLC_DRAM: 3628 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 3629 break; 3630 case AMDGPU_UCODE_ID_RLC_IRAM_1: 3631 *type = GFX_FW_TYPE_RLX6_UCODE_CORE1; 3632 break; 3633 case AMDGPU_UCODE_ID_RLC_DRAM_1: 3634 *type = GFX_FW_TYPE_RLX6_DRAM_BOOT_CORE1; 3635 break; 3636 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 3637 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 3638 break; 3639 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 3640 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 3641 break; 3642 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 3643 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 3644 break; 3645 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 3646 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 3647 break; 3648 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 3649 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 3650 break; 3651 case AMDGPU_UCODE_ID_SMC: 3652 *type = GFX_FW_TYPE_SMU; 3653 break; 3654 case AMDGPU_UCODE_ID_PPTABLE: 3655 *type = GFX_FW_TYPE_PPTABLE; 3656 break; 3657 case AMDGPU_UCODE_ID_UVD: 3658 *type = GFX_FW_TYPE_UVD; 3659 break; 3660 case AMDGPU_UCODE_ID_UVD1: 3661 *type = GFX_FW_TYPE_UVD1; 3662 break; 3663 case AMDGPU_UCODE_ID_VCE: 3664 *type = GFX_FW_TYPE_VCE; 3665 break; 3666 case AMDGPU_UCODE_ID_VCN: 3667 *type = GFX_FW_TYPE_VCN; 3668 break; 3669 case AMDGPU_UCODE_ID_VCN1: 3670 *type = GFX_FW_TYPE_VCN1; 3671 break; 3672 case AMDGPU_UCODE_ID_DMCU_ERAM: 3673 *type = GFX_FW_TYPE_DMCU_ERAM; 3674 break; 3675 case AMDGPU_UCODE_ID_DMCU_INTV: 3676 *type = GFX_FW_TYPE_DMCU_ISR; 3677 break; 3678 case AMDGPU_UCODE_ID_VCN0_RAM: 3679 *type = GFX_FW_TYPE_VCN0_RAM; 3680 break; 3681 case AMDGPU_UCODE_ID_VCN1_RAM: 3682 *type = GFX_FW_TYPE_VCN1_RAM; 3683 break; 3684 case AMDGPU_UCODE_ID_DMCUB: 3685 *type = GFX_FW_TYPE_DMUB; 3686 break; 3687 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 3688 case AMDGPU_UCODE_ID_SDMA_RS64: 3689 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 3690 break; 3691 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 3692 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 3693 break; 3694 case AMDGPU_UCODE_ID_IMU_I: 3695 *type = GFX_FW_TYPE_IMU_I; 3696 break; 3697 case AMDGPU_UCODE_ID_IMU_D: 3698 *type = GFX_FW_TYPE_IMU_D; 3699 break; 3700 case AMDGPU_UCODE_ID_CP_RS64_PFP: 3701 *type = GFX_FW_TYPE_RS64_PFP; 3702 break; 3703 case AMDGPU_UCODE_ID_CP_RS64_ME: 3704 *type = GFX_FW_TYPE_RS64_ME; 3705 break; 3706 case AMDGPU_UCODE_ID_CP_RS64_MEC: 3707 *type = GFX_FW_TYPE_RS64_MEC; 3708 break; 3709 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 3710 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 3711 break; 3712 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 3713 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 3714 break; 3715 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 3716 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 3717 break; 3718 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 3719 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 3720 break; 3721 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 3722 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 3723 break; 3724 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 3725 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 3726 break; 3727 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 3728 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 3729 break; 3730 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 3731 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 3732 break; 3733 case AMDGPU_UCODE_ID_CP_RS64_MEC_P4_STACK: 3734 *type = GFX_FW_TYPE_RS64_MEC_P4_STACK; 3735 break; 3736 case AMDGPU_UCODE_ID_CP_RS64_MEC_P5_STACK: 3737 *type = GFX_FW_TYPE_RS64_MEC_P5_STACK; 3738 break; 3739 case AMDGPU_UCODE_ID_CP_RS64_MEC_P6_STACK: 3740 *type = GFX_FW_TYPE_RS64_MEC_P6_STACK; 3741 break; 3742 case AMDGPU_UCODE_ID_CP_RS64_MEC_P7_STACK: 3743 *type = GFX_FW_TYPE_RS64_MEC_P7_STACK; 3744 break; 3745 case AMDGPU_UCODE_ID_VPE_CTX: 3746 *type = GFX_FW_TYPE_VPEC_FW1; 3747 break; 3748 case AMDGPU_UCODE_ID_VPE_CTL: 3749 *type = GFX_FW_TYPE_VPEC_FW2; 3750 break; 3751 case AMDGPU_UCODE_ID_VPE: 3752 *type = GFX_FW_TYPE_VPE; 3753 break; 3754 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 3755 *type = GFX_FW_TYPE_UMSCH_UCODE; 3756 break; 3757 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 3758 *type = GFX_FW_TYPE_UMSCH_DATA; 3759 break; 3760 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 3761 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER; 3762 break; 3763 case AMDGPU_UCODE_ID_P2S_TABLE: 3764 *type = GFX_FW_TYPE_P2S_TABLE; 3765 break; 3766 case AMDGPU_UCODE_ID_JPEG_RAM: 3767 *type = GFX_FW_TYPE_JPEG_RAM; 3768 break; 3769 case AMDGPU_UCODE_ID_ISP: 3770 *type = GFX_FW_TYPE_ISP; 3771 break; 3772 case AMDGPU_UCODE_ID_MP5: 3773 *type = GFX_FW_TYPE_MP5; 3774 break; 3775 case AMDGPU_UCODE_ID_MAXIMUM: 3776 default: 3777 return -EINVAL; 3778 } 3779 3780 return 0; 3781 } 3782 3783 static void psp_print_fw_hdr(struct psp_context *psp, 3784 struct amdgpu_firmware_info *ucode) 3785 { 3786 struct amdgpu_device *adev = psp->adev; 3787 struct common_firmware_header *hdr; 3788 3789 switch (ucode->ucode_id) { 3790 case AMDGPU_UCODE_ID_SDMA0: 3791 case AMDGPU_UCODE_ID_SDMA1: 3792 case AMDGPU_UCODE_ID_SDMA2: 3793 case AMDGPU_UCODE_ID_SDMA3: 3794 case AMDGPU_UCODE_ID_SDMA4: 3795 case AMDGPU_UCODE_ID_SDMA5: 3796 case AMDGPU_UCODE_ID_SDMA6: 3797 case AMDGPU_UCODE_ID_SDMA7: 3798 hdr = (struct common_firmware_header *) 3799 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 3800 amdgpu_ucode_print_sdma_hdr(hdr); 3801 break; 3802 case AMDGPU_UCODE_ID_CP_CE: 3803 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 3804 amdgpu_ucode_print_gfx_hdr(hdr); 3805 break; 3806 case AMDGPU_UCODE_ID_CP_PFP: 3807 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 3808 amdgpu_ucode_print_gfx_hdr(hdr); 3809 break; 3810 case AMDGPU_UCODE_ID_CP_ME: 3811 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 3812 amdgpu_ucode_print_gfx_hdr(hdr); 3813 break; 3814 case AMDGPU_UCODE_ID_CP_MEC1: 3815 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 3816 amdgpu_ucode_print_gfx_hdr(hdr); 3817 break; 3818 case AMDGPU_UCODE_ID_RLC_G: 3819 case AMDGPU_UCODE_ID_RLC_DRAM_1: 3820 case AMDGPU_UCODE_ID_RLC_IRAM_1: 3821 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 3822 amdgpu_ucode_print_rlc_hdr(hdr); 3823 break; 3824 case AMDGPU_UCODE_ID_SMC: 3825 hdr = (struct common_firmware_header *)adev->pm.fw->data; 3826 amdgpu_ucode_print_smc_hdr(hdr); 3827 break; 3828 case AMDGPU_UCODE_ID_MP5: 3829 hdr = (struct common_firmware_header *)adev->pm.mp5_fw->data; 3830 amdgpu_ucode_print_smc_hdr(hdr); 3831 break; 3832 default: 3833 break; 3834 } 3835 } 3836 3837 static int psp_prep_load_ip_fw_cmd_buf(struct psp_context *psp, 3838 struct amdgpu_firmware_info *ucode, 3839 struct psp_gfx_cmd_resp *cmd) 3840 { 3841 int ret; 3842 uint64_t fw_mem_mc_addr = ucode->mc_addr; 3843 3844 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 3845 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 3846 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 3847 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 3848 3849 ret = psp_get_fw_type(psp, ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 3850 if (ret) 3851 dev_err(psp->adev->dev, "Unknown firmware type %d\n", ucode->ucode_id); 3852 return ret; 3853 } 3854 3855 int psp_execute_ip_fw_load(struct psp_context *psp, 3856 struct amdgpu_firmware_info *ucode) 3857 { 3858 int ret = 0; 3859 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 3860 3861 ret = psp_prep_load_ip_fw_cmd_buf(psp, ucode, cmd); 3862 if (!ret) { 3863 ret = psp_cmd_submit_buf(psp, ucode, cmd, 3864 psp->fence_buf_mc_addr); 3865 } 3866 3867 release_psp_cmd_buf(psp); 3868 3869 return ret; 3870 } 3871 3872 static int psp_load_p2s_table(struct psp_context *psp) 3873 { 3874 int ret; 3875 struct amdgpu_device *adev = psp->adev; 3876 struct amdgpu_firmware_info *ucode = 3877 &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE]; 3878 3879 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 3880 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 3881 return 0; 3882 3883 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 3884 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 3885 uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D : 3886 0x0036003C; 3887 if (psp->sos.fw_version < supp_vers) 3888 return 0; 3889 } 3890 3891 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 3892 return 0; 3893 3894 ret = psp_execute_ip_fw_load(psp, ucode); 3895 3896 return ret; 3897 } 3898 3899 static int psp_load_smu_fw(struct psp_context *psp) 3900 { 3901 int ret; 3902 struct amdgpu_device *adev = psp->adev; 3903 struct amdgpu_firmware_info *ucode = 3904 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 3905 struct amdgpu_ras *ras = psp->ras_context.ras; 3906 3907 /* 3908 * Skip SMU FW reloading in case of using BACO for runpm only, 3909 * as SMU is always alive. 3910 */ 3911 if (adev->in_runpm && ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 3912 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO))) 3913 return 0; 3914 3915 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 3916 return 0; 3917 3918 if ((amdgpu_in_reset(adev) && ras && adev->ras_enabled && 3919 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) || 3920 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) { 3921 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 3922 if (ret) 3923 dev_err(adev->dev, "Failed to set MP1 state prepare for reload\n"); 3924 } 3925 3926 ret = psp_execute_ip_fw_load(psp, ucode); 3927 3928 if (ret) 3929 dev_err(adev->dev, "PSP load smu failed!\n"); 3930 3931 return ret; 3932 } 3933 3934 static bool fw_load_skip_check(struct psp_context *psp, 3935 struct amdgpu_firmware_info *ucode) 3936 { 3937 if (!ucode->fw || !ucode->ucode_size) 3938 return true; 3939 3940 if (ucode->ucode_id == AMDGPU_UCODE_ID_P2S_TABLE) 3941 return true; 3942 3943 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 3944 (psp_smu_reload_quirk(psp) || 3945 psp->autoload_supported || 3946 psp->pmfw_centralized_cstate_management)) 3947 return true; 3948 3949 if (amdgpu_sriov_vf(psp->adev) && 3950 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 3951 return true; 3952 3953 if (psp->autoload_supported && 3954 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 3955 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 3956 /* skip mec JT when autoload is enabled */ 3957 return true; 3958 3959 return false; 3960 } 3961 3962 int psp_load_fw_list(struct psp_context *psp, 3963 struct amdgpu_firmware_info **ucode_list, int ucode_count) 3964 { 3965 int ret = 0, i; 3966 struct amdgpu_firmware_info *ucode; 3967 3968 for (i = 0; i < ucode_count; ++i) { 3969 ucode = ucode_list[i]; 3970 psp_print_fw_hdr(psp, ucode); 3971 ret = psp_execute_ip_fw_load(psp, ucode); 3972 if (ret) 3973 return ret; 3974 } 3975 return ret; 3976 } 3977 3978 static int psp_load_non_psp_fw(struct psp_context *psp) 3979 { 3980 int i, ret; 3981 struct amdgpu_firmware_info *ucode; 3982 struct amdgpu_device *adev = psp->adev; 3983 3984 if (psp->autoload_supported && 3985 !psp->pmfw_centralized_cstate_management) { 3986 ret = psp_load_smu_fw(psp); 3987 if (ret) 3988 return ret; 3989 } 3990 3991 /* Load P2S table first if it's available */ 3992 psp_load_p2s_table(psp); 3993 3994 for (i = 0; i < adev->firmware.max_ucodes; i++) { 3995 ucode = &adev->firmware.ucode[i]; 3996 3997 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 3998 !fw_load_skip_check(psp, ucode)) { 3999 ret = psp_load_smu_fw(psp); 4000 if (ret) 4001 return ret; 4002 continue; 4003 } 4004 4005 if (fw_load_skip_check(psp, ucode)) 4006 continue; 4007 4008 if (psp->autoload_supported && 4009 (amdgpu_ip_version(adev, MP0_HWIP, 0) == 4010 IP_VERSION(11, 0, 7) || 4011 amdgpu_ip_version(adev, MP0_HWIP, 0) == 4012 IP_VERSION(11, 0, 11) || 4013 amdgpu_ip_version(adev, MP0_HWIP, 0) == 4014 IP_VERSION(11, 0, 12) || 4015 amdgpu_ip_version(adev, MP0_HWIP, 0) == 4016 IP_VERSION(15, 0, 0) || 4017 amdgpu_ip_version(adev, MP0_HWIP, 0) == 4018 IP_VERSION(15, 0, 3) || 4019 amdgpu_ip_version(adev, MP0_HWIP, 0) == 4020 IP_VERSION(15, 0, 5) || 4021 amdgpu_ip_version(adev, MP0_HWIP, 0) == 4022 IP_VERSION(15, 0, 8) || 4023 amdgpu_ip_version(adev, MP0_HWIP, 0) == 4024 IP_VERSION(15, 0, 9)) && 4025 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 4026 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 4027 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 4028 /* PSP only receive one SDMA fw for sienna_cichlid, 4029 * as all four sdma fw are same 4030 */ 4031 continue; 4032 4033 /* IMU ucode is part of IFWI and MP0 15.0.8 would load it */ 4034 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 4035 IP_VERSION(15, 0, 8) && 4036 (ucode->ucode_id == AMDGPU_UCODE_ID_IMU_I || 4037 ucode->ucode_id == AMDGPU_UCODE_ID_IMU_D)) 4038 continue; 4039 4040 psp_print_fw_hdr(psp, ucode); 4041 4042 ret = psp_execute_ip_fw_load(psp, ucode); 4043 if (ret) 4044 return ret; 4045 4046 /* Start rlc autoload after psp received all the gfx firmware */ 4047 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 4048 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 4049 ret = psp_rlc_autoload_start(psp); 4050 if (ret) { 4051 dev_err(adev->dev, "Failed to start rlc autoload\n"); 4052 return ret; 4053 } 4054 } 4055 } 4056 4057 return 0; 4058 } 4059 4060 static int psp_load_fw(struct amdgpu_device *adev) 4061 { 4062 int ret; 4063 struct psp_context *psp = &adev->psp; 4064 4065 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 4066 /* should not destroy ring, only stop */ 4067 psp_ring_stop(psp, PSP_RING_TYPE__KM); 4068 } else { 4069 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 4070 4071 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 4072 if (ret) { 4073 dev_err(adev->dev, "PSP ring init failed!\n"); 4074 goto failed; 4075 } 4076 } 4077 4078 ret = psp_hw_start(psp); 4079 if (ret) 4080 goto failed; 4081 4082 ret = psp_load_non_psp_fw(psp); 4083 if (ret) 4084 goto failed1; 4085 4086 ret = psp_asd_initialize(psp); 4087 if (ret) { 4088 dev_err(adev->dev, "PSP load asd failed!\n"); 4089 goto failed1; 4090 } 4091 4092 ret = psp_rl_load(adev); 4093 if (ret) { 4094 dev_err(adev->dev, "PSP load RL failed!\n"); 4095 goto failed1; 4096 } 4097 4098 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 4099 if (adev->gmc.xgmi.num_physical_nodes > 1) { 4100 ret = psp_xgmi_initialize(psp, false, true); 4101 /* Warning the XGMI seesion initialize failure 4102 * Instead of stop driver initialization 4103 */ 4104 if (ret) 4105 dev_err(psp->adev->dev, 4106 "XGMI: Failed to initialize XGMI session\n"); 4107 } 4108 } 4109 4110 if (psp->ta_fw) { 4111 ret = psp_ras_initialize(psp); 4112 if (ret) 4113 dev_err(psp->adev->dev, 4114 "RAS: Failed to initialize RAS\n"); 4115 4116 ret = psp_hdcp_initialize(psp); 4117 if (ret) 4118 dev_err(psp->adev->dev, 4119 "HDCP: Failed to initialize HDCP\n"); 4120 4121 ret = psp_dtm_initialize(psp); 4122 if (ret) 4123 dev_err(psp->adev->dev, 4124 "DTM: Failed to initialize DTM\n"); 4125 4126 ret = psp_rap_initialize(psp); 4127 if (ret) 4128 dev_err(psp->adev->dev, 4129 "RAP: Failed to initialize RAP\n"); 4130 4131 ret = psp_securedisplay_initialize(psp); 4132 if (ret) 4133 dev_err(psp->adev->dev, 4134 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 4135 } 4136 4137 return 0; 4138 4139 failed1: 4140 psp_free_shared_bufs(psp); 4141 failed: 4142 /* 4143 * all cleanup jobs (xgmi terminate, ras terminate, 4144 * ring destroy, cmd/fence/fw buffers destory, 4145 * psp->cmd destory) are delayed to psp_hw_fini 4146 */ 4147 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 4148 return ret; 4149 } 4150 4151 static int psp_hw_init(struct amdgpu_ip_block *ip_block) 4152 { 4153 int ret; 4154 struct amdgpu_device *adev = ip_block->adev; 4155 4156 mutex_lock(&adev->firmware.mutex); 4157 4158 ret = amdgpu_ucode_init_bo(adev); 4159 if (ret) 4160 goto failed; 4161 4162 ret = psp_load_fw(adev); 4163 if (ret) { 4164 dev_err(adev->dev, "PSP firmware loading failed\n"); 4165 goto failed; 4166 } 4167 4168 mutex_unlock(&adev->firmware.mutex); 4169 return 0; 4170 4171 failed: 4172 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 4173 mutex_unlock(&adev->firmware.mutex); 4174 return -EINVAL; 4175 } 4176 4177 static int psp_hw_fini(struct amdgpu_ip_block *ip_block) 4178 { 4179 struct amdgpu_device *adev = ip_block->adev; 4180 struct psp_context *psp = &adev->psp; 4181 4182 if (psp->ta_fw) { 4183 psp_ras_terminate(psp); 4184 psp_securedisplay_terminate(psp); 4185 psp_rap_terminate(psp); 4186 psp_dtm_terminate(psp); 4187 psp_hdcp_terminate(psp); 4188 4189 if (adev->gmc.xgmi.num_physical_nodes > 1) 4190 psp_xgmi_terminate(psp); 4191 } 4192 4193 psp_asd_terminate(psp); 4194 psp_tmr_terminate(psp); 4195 4196 psp_irq_disable(psp); 4197 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 4198 4199 return 0; 4200 } 4201 4202 static int psp_suspend(struct amdgpu_ip_block *ip_block) 4203 { 4204 int ret = 0; 4205 struct amdgpu_device *adev = ip_block->adev; 4206 struct psp_context *psp = &adev->psp; 4207 4208 if (adev->gmc.xgmi.num_physical_nodes > 1 && 4209 psp->xgmi_context.context.initialized) { 4210 ret = psp_xgmi_terminate(psp); 4211 if (ret) { 4212 dev_err(adev->dev, "Failed to terminate xgmi ta\n"); 4213 goto out; 4214 } 4215 } 4216 4217 if (psp->ta_fw) { 4218 ret = psp_ras_terminate(psp); 4219 if (ret) { 4220 dev_err(adev->dev, "Failed to terminate ras ta\n"); 4221 goto out; 4222 } 4223 ret = psp_hdcp_terminate(psp); 4224 if (ret) { 4225 dev_err(adev->dev, "Failed to terminate hdcp ta\n"); 4226 goto out; 4227 } 4228 ret = psp_dtm_terminate(psp); 4229 if (ret) { 4230 dev_err(adev->dev, "Failed to terminate dtm ta\n"); 4231 goto out; 4232 } 4233 ret = psp_rap_terminate(psp); 4234 if (ret) { 4235 dev_err(adev->dev, "Failed to terminate rap ta\n"); 4236 goto out; 4237 } 4238 ret = psp_securedisplay_terminate(psp); 4239 if (ret) { 4240 dev_err(adev->dev, "Failed to terminate securedisplay ta\n"); 4241 goto out; 4242 } 4243 } 4244 4245 ret = psp_asd_terminate(psp); 4246 if (ret) { 4247 dev_err(adev->dev, "Failed to terminate asd\n"); 4248 goto out; 4249 } 4250 4251 ret = psp_tmr_terminate(psp); 4252 if (ret) { 4253 dev_err(adev->dev, "Failed to terminate tmr\n"); 4254 goto out; 4255 } 4256 psp_irq_disable(psp); 4257 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 4258 if (ret) 4259 dev_err(adev->dev, "PSP ring stop failed\n"); 4260 4261 out: 4262 return ret; 4263 } 4264 4265 static int psp_resume(struct amdgpu_ip_block *ip_block) 4266 { 4267 int ret; 4268 struct amdgpu_device *adev = ip_block->adev; 4269 struct psp_context *psp = &adev->psp; 4270 4271 dev_info(adev->dev, "PSP is resuming...\n"); 4272 4273 if (psp->mem_train_ctx.enable_mem_training) { 4274 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 4275 if (ret) { 4276 dev_err(adev->dev, "Failed to process memory training!\n"); 4277 return ret; 4278 } 4279 } 4280 4281 mutex_lock(&adev->firmware.mutex); 4282 4283 ret = amdgpu_ucode_init_bo(adev); 4284 if (ret) 4285 goto failed; 4286 4287 ret = psp_hw_start(psp); 4288 if (ret) 4289 goto failed; 4290 4291 ret = psp_load_non_psp_fw(psp); 4292 if (ret) 4293 goto failed; 4294 4295 ret = psp_asd_initialize(psp); 4296 if (ret) { 4297 dev_err(adev->dev, "PSP load asd failed!\n"); 4298 goto failed; 4299 } 4300 4301 ret = psp_rl_load(adev); 4302 if (ret) { 4303 dev_err(adev->dev, "PSP load RL failed!\n"); 4304 goto failed; 4305 } 4306 4307 if (adev->gmc.xgmi.num_physical_nodes > 1) { 4308 ret = psp_xgmi_initialize(psp, false, true); 4309 /* Warning the XGMI seesion initialize failure 4310 * Instead of stop driver initialization 4311 */ 4312 if (ret) 4313 dev_err(psp->adev->dev, 4314 "XGMI: Failed to initialize XGMI session\n"); 4315 } 4316 4317 if (psp->ta_fw) { 4318 ret = psp_ras_initialize(psp); 4319 if (ret) 4320 dev_err(psp->adev->dev, 4321 "RAS: Failed to initialize RAS\n"); 4322 4323 ret = psp_hdcp_initialize(psp); 4324 if (ret) 4325 dev_err(psp->adev->dev, 4326 "HDCP: Failed to initialize HDCP\n"); 4327 4328 ret = psp_dtm_initialize(psp); 4329 if (ret) 4330 dev_err(psp->adev->dev, 4331 "DTM: Failed to initialize DTM\n"); 4332 4333 ret = psp_rap_initialize(psp); 4334 if (ret) 4335 dev_err(psp->adev->dev, 4336 "RAP: Failed to initialize RAP\n"); 4337 4338 ret = psp_securedisplay_initialize(psp); 4339 if (ret) 4340 dev_err(psp->adev->dev, 4341 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 4342 } 4343 4344 mutex_unlock(&adev->firmware.mutex); 4345 4346 return 0; 4347 4348 failed: 4349 dev_err(adev->dev, "PSP resume failed\n"); 4350 mutex_unlock(&adev->firmware.mutex); 4351 return ret; 4352 } 4353 4354 int psp_gpu_reset(struct amdgpu_device *adev) 4355 { 4356 int ret; 4357 4358 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 4359 return 0; 4360 4361 mutex_lock(&adev->psp.mutex); 4362 ret = psp_mode1_reset(&adev->psp); 4363 mutex_unlock(&adev->psp.mutex); 4364 4365 return ret; 4366 } 4367 4368 int psp_rlc_autoload_start(struct psp_context *psp) 4369 { 4370 int ret; 4371 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 4372 4373 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 4374 4375 ret = psp_cmd_submit_buf(psp, NULL, cmd, 4376 psp->fence_buf_mc_addr); 4377 4378 release_psp_cmd_buf(psp); 4379 4380 return ret; 4381 } 4382 4383 int psp_ring_cmd_submit(struct psp_context *psp, 4384 uint64_t cmd_buf_mc_addr, 4385 uint64_t fence_mc_addr, 4386 int index) 4387 { 4388 unsigned int psp_write_ptr_reg = 0; 4389 struct psp_gfx_rb_frame *write_frame; 4390 struct psp_ring *ring = &psp->km_ring; 4391 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 4392 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 4393 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 4394 struct amdgpu_device *adev = psp->adev; 4395 uint32_t ring_size_dw = ring->ring_size / 4; 4396 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 4397 4398 /* KM (GPCOM) prepare write pointer */ 4399 psp_write_ptr_reg = psp_ring_get_wptr(psp); 4400 4401 /* Update KM RB frame pointer to new frame */ 4402 /* write_frame ptr increments by size of rb_frame in bytes */ 4403 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 4404 if ((psp_write_ptr_reg % ring_size_dw) == 0) 4405 write_frame = ring_buffer_start; 4406 else 4407 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 4408 /* Check invalid write_frame ptr address */ 4409 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 4410 dev_err(adev->dev, 4411 "ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 4412 ring_buffer_start, ring_buffer_end, write_frame); 4413 dev_err(adev->dev, 4414 "write_frame is pointing to address out of bounds\n"); 4415 return -EINVAL; 4416 } 4417 4418 /* Initialize KM RB frame */ 4419 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 4420 4421 /* Update KM RB frame */ 4422 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 4423 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 4424 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 4425 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 4426 write_frame->fence_value = index; 4427 amdgpu_device_flush_hdp(adev, NULL); 4428 4429 /* Update the write Pointer in DWORDs */ 4430 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 4431 psp_ring_set_wptr(psp, psp_write_ptr_reg); 4432 return 0; 4433 } 4434 4435 /** 4436 * parse_psp_v1_bin_descriptor - Populate struct psp_bin_desc from a 4437 * v1.0 PSP firmware header (standalone images such as ASD or TOC). 4438 */ 4439 static int parse_psp_v1_bin_descriptor(struct psp_bin_desc *desc, 4440 const struct psp_firmware_header_v1_0 *hdr) 4441 { 4442 if (!desc || !hdr) 4443 return -EINVAL; 4444 4445 desc->fw_version = le32_to_cpu(hdr->header.ucode_version); 4446 desc->feature_version = le32_to_cpu(hdr->sos.fw_version); 4447 desc->size_bytes = le32_to_cpu(hdr->header.ucode_size_bytes); 4448 desc->start_addr = (uint8_t *)hdr + 4449 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 4450 4451 return 0; 4452 } 4453 4454 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name) 4455 { 4456 int err; 4457 4458 err = amdgpu_ucode_request(psp->adev, &psp->asd_fw, AMDGPU_UCODE_REQUIRED, 4459 "amdgpu/%s_asd.bin", chip_name); 4460 if (err) 4461 goto out; 4462 4463 err = parse_psp_v1_bin_descriptor(&psp->asd_context.bin_desc, 4464 (const struct psp_firmware_header_v1_0 *)psp->asd_fw->data); 4465 if (err) 4466 goto out; 4467 4468 return 0; 4469 out: 4470 amdgpu_ucode_release(&psp->asd_fw); 4471 return err; 4472 } 4473 4474 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name) 4475 { 4476 int err; 4477 4478 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 8) && 4479 psp->adev->rev_id == 0 && 4480 !amdgpu_emu_mode) 4481 err = amdgpu_ucode_request(psp->adev, &psp->toc_fw, AMDGPU_UCODE_REQUIRED, 4482 "amdgpu/%s_toc_1.bin", chip_name); 4483 else 4484 err = amdgpu_ucode_request(psp->adev, &psp->toc_fw, AMDGPU_UCODE_REQUIRED, 4485 "amdgpu/%s_toc.bin", chip_name); 4486 if (err) 4487 goto out; 4488 4489 err = parse_psp_v1_bin_descriptor(&psp->toc, 4490 (const struct psp_firmware_header_v1_0 *)psp->toc_fw->data); 4491 if (err) 4492 goto out; 4493 4494 return 0; 4495 out: 4496 amdgpu_ucode_release(&psp->toc_fw); 4497 return err; 4498 } 4499 4500 int psp_init_rl_microcode(struct psp_context *psp, const char *chip_name) 4501 { 4502 int err; 4503 4504 err = amdgpu_ucode_request(psp->adev, &psp->rl_fw, AMDGPU_UCODE_REQUIRED, 4505 "amdgpu/%s_rl.bin", chip_name); 4506 if (err) 4507 goto out; 4508 4509 err = parse_psp_v1_bin_descriptor(&psp->rl, 4510 (const struct psp_firmware_header_v1_0 *)psp->rl_fw->data); 4511 if (err) 4512 goto out; 4513 4514 return 0; 4515 out: 4516 amdgpu_ucode_release(&psp->rl_fw); 4517 return err; 4518 } 4519 4520 static int parse_psp_v2_bin_descriptor(struct psp_context *psp, 4521 const struct psp_fw_bin_desc *desc, 4522 const struct psp_firmware_header_v2_0 *sos_hdr) 4523 { 4524 uint8_t *ucode_start_addr = NULL; 4525 4526 if (!psp || !desc || !sos_hdr) 4527 return -EINVAL; 4528 4529 ucode_start_addr = (uint8_t *)sos_hdr + 4530 le32_to_cpu(desc->offset_bytes) + 4531 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 4532 4533 switch (desc->fw_type) { 4534 case PSP_FW_TYPE_PSP_SOS: 4535 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 4536 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 4537 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 4538 psp->sos.start_addr = ucode_start_addr; 4539 break; 4540 case PSP_FW_TYPE_PSP_SYS_DRV: 4541 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 4542 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 4543 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 4544 psp->sys.start_addr = ucode_start_addr; 4545 break; 4546 case PSP_FW_TYPE_PSP_KDB: 4547 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 4548 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 4549 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 4550 psp->kdb.start_addr = ucode_start_addr; 4551 break; 4552 case PSP_FW_TYPE_PSP_TOC: 4553 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 4554 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 4555 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 4556 psp->toc.start_addr = ucode_start_addr; 4557 break; 4558 case PSP_FW_TYPE_PSP_SPL: 4559 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 4560 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 4561 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 4562 psp->spl.start_addr = ucode_start_addr; 4563 break; 4564 case PSP_FW_TYPE_PSP_RL: 4565 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 4566 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 4567 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 4568 psp->rl.start_addr = ucode_start_addr; 4569 break; 4570 case PSP_FW_TYPE_PSP_SOC_DRV: 4571 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 4572 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 4573 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4574 psp->soc_drv.start_addr = ucode_start_addr; 4575 break; 4576 case PSP_FW_TYPE_PSP_INTF_DRV: 4577 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 4578 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 4579 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4580 psp->intf_drv.start_addr = ucode_start_addr; 4581 break; 4582 case PSP_FW_TYPE_PSP_DBG_DRV: 4583 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 4584 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 4585 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4586 psp->dbg_drv.start_addr = ucode_start_addr; 4587 break; 4588 case PSP_FW_TYPE_PSP_RAS_DRV: 4589 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 4590 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 4591 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4592 psp->ras_drv.start_addr = ucode_start_addr; 4593 break; 4594 case PSP_FW_TYPE_PSP_IPKEYMGR_DRV: 4595 psp->ipkeymgr_drv.fw_version = le32_to_cpu(desc->fw_version); 4596 psp->ipkeymgr_drv.feature_version = le32_to_cpu(desc->fw_version); 4597 psp->ipkeymgr_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4598 psp->ipkeymgr_drv.start_addr = ucode_start_addr; 4599 break; 4600 case PSP_FW_TYPE_PSP_SPDM_DRV: 4601 psp->spdm_drv.fw_version = le32_to_cpu(desc->fw_version); 4602 psp->spdm_drv.feature_version = le32_to_cpu(desc->fw_version); 4603 psp->spdm_drv.size_bytes = le32_to_cpu(desc->size_bytes); 4604 psp->spdm_drv.start_addr = ucode_start_addr; 4605 break; 4606 default: 4607 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 4608 break; 4609 } 4610 4611 return 0; 4612 } 4613 4614 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 4615 { 4616 const struct psp_firmware_header_v1_0 *sos_hdr; 4617 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 4618 uint8_t *ucode_array_start_addr; 4619 4620 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 4621 ucode_array_start_addr = (uint8_t *)sos_hdr + 4622 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 4623 4624 if (adev->gmc.xgmi.connected_to_cpu || 4625 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2))) { 4626 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 4627 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 4628 4629 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 4630 adev->psp.sys.start_addr = ucode_array_start_addr; 4631 4632 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 4633 adev->psp.sos.start_addr = ucode_array_start_addr + 4634 le32_to_cpu(sos_hdr->sos.offset_bytes); 4635 } else { 4636 /* Load alternate PSP SOS FW */ 4637 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 4638 4639 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 4640 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 4641 4642 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 4643 adev->psp.sys.start_addr = ucode_array_start_addr + 4644 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 4645 4646 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 4647 adev->psp.sos.start_addr = ucode_array_start_addr + 4648 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 4649 } 4650 4651 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 4652 dev_warn(adev->dev, "PSP SOS FW not available"); 4653 return -EINVAL; 4654 } 4655 4656 return 0; 4657 } 4658 4659 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) 4660 { 4661 struct amdgpu_device *adev = psp->adev; 4662 const struct psp_firmware_header_v1_0 *sos_hdr; 4663 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 4664 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 4665 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 4666 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 4667 const struct psp_firmware_header_v2_1 *sos_hdr_v2_1; 4668 int fw_index, fw_bin_count, start_index = 0; 4669 const struct psp_fw_bin_desc *fw_bin; 4670 uint8_t *ucode_array_start_addr; 4671 int err = 0; 4672 4673 if (amdgpu_is_kicker_fw(adev)) 4674 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 4675 "amdgpu/%s_sos_kicker.bin", chip_name); 4676 else 4677 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED, 4678 "amdgpu/%s_sos.bin", chip_name); 4679 if (err) 4680 goto out; 4681 4682 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 4683 ucode_array_start_addr = (uint8_t *)sos_hdr + 4684 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 4685 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 4686 4687 switch (sos_hdr->header.header_version_major) { 4688 case 1: 4689 err = psp_init_sos_base_fw(adev); 4690 if (err) 4691 goto out; 4692 4693 if (sos_hdr->header.header_version_minor == 1) { 4694 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 4695 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 4696 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4697 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 4698 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 4699 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4700 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 4701 } 4702 if (sos_hdr->header.header_version_minor == 2) { 4703 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 4704 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 4705 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 4706 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 4707 } 4708 if (sos_hdr->header.header_version_minor == 3) { 4709 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 4710 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 4711 adev->psp.toc.start_addr = ucode_array_start_addr + 4712 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 4713 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 4714 adev->psp.kdb.start_addr = ucode_array_start_addr + 4715 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 4716 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 4717 adev->psp.spl.start_addr = ucode_array_start_addr + 4718 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 4719 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 4720 adev->psp.rl.start_addr = ucode_array_start_addr + 4721 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 4722 } 4723 break; 4724 case 2: 4725 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 4726 4727 fw_bin_count = le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); 4728 4729 if (fw_bin_count >= UCODE_MAX_PSP_PACKAGING) { 4730 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 4731 err = -EINVAL; 4732 goto out; 4733 } 4734 4735 if (sos_hdr_v2_0->header.header_version_minor == 1) { 4736 sos_hdr_v2_1 = (const struct psp_firmware_header_v2_1 *)adev->psp.sos_fw->data; 4737 4738 fw_bin = sos_hdr_v2_1->psp_fw_bin; 4739 4740 if (psp_is_aux_sos_load_required(psp)) 4741 start_index = le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 4742 else 4743 fw_bin_count -= le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); 4744 4745 } else { 4746 fw_bin = sos_hdr_v2_0->psp_fw_bin; 4747 } 4748 4749 for (fw_index = start_index; fw_index < fw_bin_count; fw_index++) { 4750 err = parse_psp_v2_bin_descriptor(psp, fw_bin + fw_index, 4751 sos_hdr_v2_0); 4752 if (err) 4753 goto out; 4754 } 4755 break; 4756 default: 4757 dev_err(adev->dev, 4758 "unsupported psp sos firmware\n"); 4759 err = -EINVAL; 4760 goto out; 4761 } 4762 4763 return 0; 4764 out: 4765 amdgpu_ucode_release(&adev->psp.sos_fw); 4766 4767 return err; 4768 } 4769 4770 static bool is_ta_fw_applicable(struct psp_context *psp, 4771 const struct psp_fw_bin_desc *desc) 4772 { 4773 struct amdgpu_device *adev = psp->adev; 4774 uint32_t fw_version; 4775 4776 switch (desc->fw_type) { 4777 case TA_FW_TYPE_PSP_XGMI: 4778 case TA_FW_TYPE_PSP_XGMI_AUX: 4779 /* for now, AUX TA only exists on 13.0.6 ta bin, 4780 * from v20.00.0x.14 4781 */ 4782 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 4783 IP_VERSION(13, 0, 6)) { 4784 fw_version = le32_to_cpu(desc->fw_version); 4785 4786 if (adev->flags & AMD_IS_APU && 4787 (fw_version & 0xff) >= 0x14) 4788 return desc->fw_type == TA_FW_TYPE_PSP_XGMI_AUX; 4789 else 4790 return desc->fw_type == TA_FW_TYPE_PSP_XGMI; 4791 } 4792 break; 4793 default: 4794 break; 4795 } 4796 4797 return true; 4798 } 4799 4800 static int parse_ta_bin_descriptor(struct psp_context *psp, 4801 const struct psp_fw_bin_desc *desc, 4802 const struct ta_firmware_header_v2_0 *ta_hdr) 4803 { 4804 uint8_t *ucode_start_addr = NULL; 4805 4806 if (!psp || !desc || !ta_hdr) 4807 return -EINVAL; 4808 4809 if (!is_ta_fw_applicable(psp, desc)) 4810 return 0; 4811 4812 ucode_start_addr = (uint8_t *)ta_hdr + 4813 le32_to_cpu(desc->offset_bytes) + 4814 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4815 4816 switch (desc->fw_type) { 4817 case TA_FW_TYPE_PSP_ASD: 4818 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4819 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 4820 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4821 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 4822 break; 4823 case TA_FW_TYPE_PSP_XGMI: 4824 case TA_FW_TYPE_PSP_XGMI_AUX: 4825 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4826 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4827 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 4828 break; 4829 case TA_FW_TYPE_PSP_RAS: 4830 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4831 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4832 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 4833 break; 4834 case TA_FW_TYPE_PSP_HDCP: 4835 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4836 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4837 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 4838 break; 4839 case TA_FW_TYPE_PSP_DTM: 4840 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4841 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4842 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 4843 break; 4844 case TA_FW_TYPE_PSP_RAP: 4845 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 4846 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 4847 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 4848 break; 4849 case TA_FW_TYPE_PSP_SECUREDISPLAY: 4850 psp->securedisplay_context.context.bin_desc.fw_version = 4851 le32_to_cpu(desc->fw_version); 4852 psp->securedisplay_context.context.bin_desc.size_bytes = 4853 le32_to_cpu(desc->size_bytes); 4854 psp->securedisplay_context.context.bin_desc.start_addr = 4855 ucode_start_addr; 4856 break; 4857 default: 4858 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 4859 break; 4860 } 4861 4862 return 0; 4863 } 4864 4865 static int parse_ta_v1_microcode(struct psp_context *psp) 4866 { 4867 const struct ta_firmware_header_v1_0 *ta_hdr; 4868 struct amdgpu_device *adev = psp->adev; 4869 4870 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data; 4871 4872 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1) 4873 return -EINVAL; 4874 4875 adev->psp.xgmi_context.context.bin_desc.fw_version = 4876 le32_to_cpu(ta_hdr->xgmi.fw_version); 4877 adev->psp.xgmi_context.context.bin_desc.size_bytes = 4878 le32_to_cpu(ta_hdr->xgmi.size_bytes); 4879 adev->psp.xgmi_context.context.bin_desc.start_addr = 4880 (uint8_t *)ta_hdr + 4881 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4882 4883 adev->psp.ras_context.context.bin_desc.fw_version = 4884 le32_to_cpu(ta_hdr->ras.fw_version); 4885 adev->psp.ras_context.context.bin_desc.size_bytes = 4886 le32_to_cpu(ta_hdr->ras.size_bytes); 4887 adev->psp.ras_context.context.bin_desc.start_addr = 4888 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 4889 le32_to_cpu(ta_hdr->ras.offset_bytes); 4890 4891 adev->psp.hdcp_context.context.bin_desc.fw_version = 4892 le32_to_cpu(ta_hdr->hdcp.fw_version); 4893 adev->psp.hdcp_context.context.bin_desc.size_bytes = 4894 le32_to_cpu(ta_hdr->hdcp.size_bytes); 4895 adev->psp.hdcp_context.context.bin_desc.start_addr = 4896 (uint8_t *)ta_hdr + 4897 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 4898 4899 adev->psp.dtm_context.context.bin_desc.fw_version = 4900 le32_to_cpu(ta_hdr->dtm.fw_version); 4901 adev->psp.dtm_context.context.bin_desc.size_bytes = 4902 le32_to_cpu(ta_hdr->dtm.size_bytes); 4903 adev->psp.dtm_context.context.bin_desc.start_addr = 4904 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 4905 le32_to_cpu(ta_hdr->dtm.offset_bytes); 4906 4907 adev->psp.securedisplay_context.context.bin_desc.fw_version = 4908 le32_to_cpu(ta_hdr->securedisplay.fw_version); 4909 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 4910 le32_to_cpu(ta_hdr->securedisplay.size_bytes); 4911 adev->psp.securedisplay_context.context.bin_desc.start_addr = 4912 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr + 4913 le32_to_cpu(ta_hdr->securedisplay.offset_bytes); 4914 4915 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 4916 4917 return 0; 4918 } 4919 4920 static int parse_ta_v2_microcode(struct psp_context *psp) 4921 { 4922 const struct ta_firmware_header_v2_0 *ta_hdr; 4923 struct amdgpu_device *adev = psp->adev; 4924 int err = 0; 4925 int ta_index = 0; 4926 4927 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 4928 4929 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) 4930 return -EINVAL; 4931 4932 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 4933 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 4934 return -EINVAL; 4935 } 4936 4937 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 4938 err = parse_ta_bin_descriptor(psp, 4939 &ta_hdr->ta_fw_bin[ta_index], 4940 ta_hdr); 4941 if (err) 4942 return err; 4943 } 4944 4945 return 0; 4946 } 4947 4948 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name) 4949 { 4950 const struct common_firmware_header *hdr; 4951 struct amdgpu_device *adev = psp->adev; 4952 int err; 4953 4954 if (amdgpu_is_kicker_fw(adev)) 4955 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 4956 "amdgpu/%s_ta_kicker.bin", chip_name); 4957 else 4958 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED, 4959 "amdgpu/%s_ta.bin", chip_name); 4960 if (err) 4961 return err; 4962 4963 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data; 4964 switch (le16_to_cpu(hdr->header_version_major)) { 4965 case 1: 4966 err = parse_ta_v1_microcode(psp); 4967 break; 4968 case 2: 4969 err = parse_ta_v2_microcode(psp); 4970 break; 4971 default: 4972 dev_err(adev->dev, "unsupported TA header version\n"); 4973 err = -EINVAL; 4974 } 4975 4976 if (err) 4977 amdgpu_ucode_release(&adev->psp.ta_fw); 4978 4979 return err; 4980 } 4981 4982 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) 4983 { 4984 struct amdgpu_device *adev = psp->adev; 4985 struct amdgpu_firmware_info *info; 4986 int err; 4987 4988 if (!amdgpu_sriov_vf(adev)) { 4989 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 4990 return -EINVAL; 4991 } 4992 4993 err = amdgpu_ucode_request(adev, &psp->cap_fw, AMDGPU_UCODE_OPTIONAL, 4994 "amdgpu/%s_cap.bin", chip_name); 4995 if (err) { 4996 if (err == -ENODEV) { 4997 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 4998 err = 0; 4999 } else { 5000 dev_err(adev->dev, "fail to initialize cap microcode\n"); 5001 } 5002 goto out; 5003 } 5004 5005 err = parse_psp_v1_bin_descriptor(&psp->cap, 5006 (const struct psp_firmware_header_v1_0 *)psp->cap_fw->data); 5007 if (err) 5008 goto out; 5009 5010 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 5011 info->ucode_id = AMDGPU_UCODE_ID_CAP; 5012 info->fw = psp->cap_fw; 5013 adev->firmware.fw_size += ALIGN(psp->cap.size_bytes, PAGE_SIZE); 5014 return 0; 5015 5016 out: 5017 amdgpu_ucode_release(&psp->cap_fw); 5018 return err; 5019 } 5020 5021 int psp_config_sq_perfmon(struct psp_context *psp, 5022 uint32_t xcp_id, bool core_override_enable, 5023 bool reg_override_enable, bool perfmon_override_enable) 5024 { 5025 int ret; 5026 5027 if (amdgpu_sriov_vf(psp->adev)) 5028 return 0; 5029 5030 if (xcp_id > MAX_XCP) { 5031 dev_err(psp->adev->dev, "invalid xcp_id %d\n", xcp_id); 5032 return -EINVAL; 5033 } 5034 5035 if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) { 5036 dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n", 5037 amdgpu_ip_version(psp->adev, MP0_HWIP, 0)); 5038 return -EINVAL; 5039 } 5040 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 5041 5042 cmd->cmd_id = GFX_CMD_ID_CONFIG_SQ_PERFMON; 5043 cmd->cmd.config_sq_perfmon.gfx_xcp_mask = BIT_MASK(xcp_id); 5044 cmd->cmd.config_sq_perfmon.core_override = core_override_enable; 5045 cmd->cmd.config_sq_perfmon.reg_override = reg_override_enable; 5046 cmd->cmd.config_sq_perfmon.perfmon_override = perfmon_override_enable; 5047 5048 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 5049 if (ret) 5050 dev_warn(psp->adev->dev, "PSP failed to config sq: xcp%d core%d reg%d perfmon%d\n", 5051 xcp_id, core_override_enable, reg_override_enable, perfmon_override_enable); 5052 5053 release_psp_cmd_buf(psp); 5054 return ret; 5055 } 5056 5057 static int psp_set_clockgating_state(struct amdgpu_ip_block *ip_block, 5058 enum amd_clockgating_state state) 5059 { 5060 return 0; 5061 } 5062 5063 static int psp_set_powergating_state(struct amdgpu_ip_block *ip_block, 5064 enum amd_powergating_state state) 5065 { 5066 return 0; 5067 } 5068 5069 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 5070 struct device_attribute *attr, 5071 char *buf) 5072 { 5073 struct drm_device *ddev = dev_get_drvdata(dev); 5074 struct amdgpu_device *adev = drm_to_adev(ddev); 5075 struct amdgpu_ip_block *ip_block; 5076 uint32_t fw_ver; 5077 int ret; 5078 5079 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 5080 if (!ip_block || !ip_block->status.late_initialized) { 5081 dev_info(adev->dev, "PSP block is not ready yet\n."); 5082 return -EBUSY; 5083 } 5084 5085 mutex_lock(&adev->psp.mutex); 5086 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 5087 mutex_unlock(&adev->psp.mutex); 5088 5089 if (ret) { 5090 dev_err(adev->dev, "Failed to read USBC PD FW, err = %d\n", ret); 5091 return ret; 5092 } 5093 5094 return sysfs_emit(buf, "%x\n", fw_ver); 5095 } 5096 5097 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 5098 struct device_attribute *attr, 5099 const char *buf, 5100 size_t count) 5101 { 5102 struct drm_device *ddev = dev_get_drvdata(dev); 5103 struct amdgpu_device *adev = drm_to_adev(ddev); 5104 int ret, idx; 5105 const struct firmware *usbc_pd_fw; 5106 struct amdgpu_bo *fw_buf_bo = NULL; 5107 uint64_t fw_pri_mc_addr; 5108 void *fw_pri_cpu_addr; 5109 struct amdgpu_ip_block *ip_block; 5110 5111 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP); 5112 if (!ip_block || !ip_block->status.late_initialized) { 5113 dev_err(adev->dev, "PSP block is not ready yet."); 5114 return -EBUSY; 5115 } 5116 5117 if (!drm_dev_enter(ddev, &idx)) 5118 return -ENODEV; 5119 5120 ret = amdgpu_ucode_request(adev, &usbc_pd_fw, AMDGPU_UCODE_REQUIRED, 5121 "amdgpu/%s", buf); 5122 if (ret) 5123 goto fail; 5124 5125 /* LFB address which is aligned to 1MB boundary per PSP request */ 5126 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 5127 AMDGPU_GEM_DOMAIN_VRAM | 5128 AMDGPU_GEM_DOMAIN_GTT, 5129 &fw_buf_bo, &fw_pri_mc_addr, 5130 &fw_pri_cpu_addr); 5131 if (ret) 5132 goto rel_buf; 5133 5134 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 5135 5136 mutex_lock(&adev->psp.mutex); 5137 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 5138 mutex_unlock(&adev->psp.mutex); 5139 5140 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 5141 5142 rel_buf: 5143 amdgpu_ucode_release(&usbc_pd_fw); 5144 fail: 5145 if (ret) { 5146 dev_err(adev->dev, "Failed to load USBC PD FW, err = %d", ret); 5147 count = ret; 5148 } 5149 5150 drm_dev_exit(idx); 5151 return count; 5152 } 5153 5154 int psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 5155 { 5156 int idx; 5157 5158 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 5159 return -ENODEV; 5160 5161 if (!bin_size || bin_size > PSP_1_MEG) { 5162 dev_err(psp->adev->dev, "PSP firmware is invalid\n"); 5163 drm_dev_exit(idx); 5164 return -EINVAL; 5165 } 5166 5167 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 5168 memcpy(psp->fw_pri_buf, start_addr, bin_size); 5169 5170 drm_dev_exit(idx); 5171 return 0; 5172 } 5173 5174 /** 5175 * DOC: usbc_pd_fw 5176 * Reading from this file will retrieve the USB-C PD firmware version. Writing to 5177 * this file will trigger the update process. 5178 */ 5179 static DEVICE_ATTR(usbc_pd_fw, 0644, 5180 psp_usbc_pd_fw_sysfs_read, 5181 psp_usbc_pd_fw_sysfs_write); 5182 /** 5183 * DOC: PTL sysfs attributes 5184 * These sysfs files under /sys/class/drm/cardX/device/ptl allow users to enable or disable 5185 * the Peak Tops Limiter (PTL), configure preferred PTL data formats, and query supported 5186 * formats for each GPU. 5187 */ 5188 static DEVICE_ATTR(ptl_enable, 0644, 5189 ptl_enable_show, ptl_enable_store); 5190 static DEVICE_ATTR(ptl_format, 0644, 5191 ptl_format_show, ptl_format_store); 5192 static DEVICE_ATTR(ptl_supported_formats, 0444, 5193 ptl_supported_formats_show, NULL); 5194 5195 static struct attribute *ptl_attrs[] = { 5196 &dev_attr_ptl_enable.attr, 5197 &dev_attr_ptl_format.attr, 5198 &dev_attr_ptl_supported_formats.attr, 5199 NULL, 5200 }; 5201 5202 const struct attribute_group amdgpu_ptl_attr_group = { 5203 .name = "ptl", 5204 .attrs = ptl_attrs, 5205 .is_visible = amdgpu_ptl_is_visible, 5206 }; 5207 5208 int is_psp_fw_valid(struct psp_bin_desc bin) 5209 { 5210 return bin.size_bytes; 5211 } 5212 5213 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 5214 const struct bin_attribute *bin_attr, 5215 char *buffer, loff_t pos, size_t count) 5216 { 5217 struct device *dev = kobj_to_dev(kobj); 5218 struct drm_device *ddev = dev_get_drvdata(dev); 5219 struct amdgpu_device *adev = drm_to_adev(ddev); 5220 5221 adev->psp.vbflash_done = false; 5222 5223 /* Safeguard against memory drain */ 5224 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 5225 dev_err(adev->dev, "File size cannot exceed %u\n", AMD_VBIOS_FILE_MAX_SIZE_B); 5226 kvfree(adev->psp.vbflash_tmp_buf); 5227 adev->psp.vbflash_tmp_buf = NULL; 5228 adev->psp.vbflash_image_size = 0; 5229 return -ENOMEM; 5230 } 5231 5232 mutex_lock(&adev->psp.mutex); 5233 5234 /* TODO Just allocate max for now and optimize to realloc later if needed */ 5235 if (!adev->psp.vbflash_tmp_buf) { 5236 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 5237 if (!adev->psp.vbflash_tmp_buf) { 5238 mutex_unlock(&adev->psp.mutex); 5239 return -ENOMEM; 5240 } 5241 } 5242 5243 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 5244 adev->psp.vbflash_image_size += count; 5245 mutex_unlock(&adev->psp.mutex); 5246 5247 dev_dbg(adev->dev, "IFWI staged for update\n"); 5248 5249 return count; 5250 } 5251 5252 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 5253 const struct bin_attribute *bin_attr, char *buffer, 5254 loff_t pos, size_t count) 5255 { 5256 struct device *dev = kobj_to_dev(kobj); 5257 struct drm_device *ddev = dev_get_drvdata(dev); 5258 struct amdgpu_device *adev = drm_to_adev(ddev); 5259 struct amdgpu_bo *fw_buf_bo = NULL; 5260 uint64_t fw_pri_mc_addr; 5261 void *fw_pri_cpu_addr; 5262 int ret; 5263 5264 if (adev->psp.vbflash_image_size == 0) 5265 return -EINVAL; 5266 5267 dev_dbg(adev->dev, "PSP IFWI flash process initiated\n"); 5268 5269 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 5270 AMDGPU_GPU_PAGE_SIZE, 5271 AMDGPU_GEM_DOMAIN_VRAM, 5272 &fw_buf_bo, 5273 &fw_pri_mc_addr, 5274 &fw_pri_cpu_addr); 5275 if (ret) 5276 goto rel_buf; 5277 5278 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 5279 5280 mutex_lock(&adev->psp.mutex); 5281 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 5282 mutex_unlock(&adev->psp.mutex); 5283 5284 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 5285 5286 rel_buf: 5287 kvfree(adev->psp.vbflash_tmp_buf); 5288 adev->psp.vbflash_tmp_buf = NULL; 5289 adev->psp.vbflash_image_size = 0; 5290 5291 if (ret) { 5292 dev_err(adev->dev, "Failed to load IFWI, err = %d\n", ret); 5293 return ret; 5294 } 5295 5296 dev_dbg(adev->dev, "PSP IFWI flash process done\n"); 5297 return 0; 5298 } 5299 5300 /** 5301 * DOC: psp_vbflash 5302 * Writing to this file will stage an IFWI for update. Reading from this file 5303 * will trigger the update process. 5304 */ 5305 static const struct bin_attribute psp_vbflash_bin_attr = { 5306 .attr = {.name = "psp_vbflash", .mode = 0660}, 5307 .size = AMD_VBIOS_FILE_MAX_SIZE_B, 5308 .write = amdgpu_psp_vbflash_write, 5309 .read = amdgpu_psp_vbflash_read, 5310 }; 5311 5312 /** 5313 * DOC: psp_vbflash_status 5314 * The status of the flash process. 5315 * 0: IFWI flash not complete. 5316 * 1: IFWI flash complete. 5317 */ 5318 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 5319 struct device_attribute *attr, 5320 char *buf) 5321 { 5322 struct drm_device *ddev = dev_get_drvdata(dev); 5323 struct amdgpu_device *adev = drm_to_adev(ddev); 5324 uint32_t vbflash_status; 5325 5326 vbflash_status = psp_vbflash_status(&adev->psp); 5327 if (!adev->psp.vbflash_done) 5328 vbflash_status = 0; 5329 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 5330 vbflash_status = 1; 5331 5332 return sysfs_emit(buf, "0x%x\n", vbflash_status); 5333 } 5334 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 5335 5336 static const struct bin_attribute *const bin_flash_attrs[] = { 5337 &psp_vbflash_bin_attr, 5338 NULL 5339 }; 5340 5341 static struct attribute *flash_attrs[] = { 5342 &dev_attr_psp_vbflash_status.attr, 5343 &dev_attr_usbc_pd_fw.attr, 5344 NULL 5345 }; 5346 5347 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx) 5348 { 5349 struct device *dev = kobj_to_dev(kobj); 5350 struct drm_device *ddev = dev_get_drvdata(dev); 5351 struct amdgpu_device *adev = drm_to_adev(ddev); 5352 5353 if (attr == &dev_attr_usbc_pd_fw.attr) 5354 return adev->psp.sup_pd_fw_up ? 0660 : 0; 5355 5356 return adev->psp.sup_ifwi_up ? 0440 : 0; 5357 } 5358 5359 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, 5360 const struct bin_attribute *attr, 5361 int idx) 5362 { 5363 struct device *dev = kobj_to_dev(kobj); 5364 struct drm_device *ddev = dev_get_drvdata(dev); 5365 struct amdgpu_device *adev = drm_to_adev(ddev); 5366 5367 return adev->psp.sup_ifwi_up ? 0660 : 0; 5368 } 5369 5370 const struct attribute_group amdgpu_flash_attr_group = { 5371 .attrs = flash_attrs, 5372 .bin_attrs = bin_flash_attrs, 5373 .is_bin_visible = amdgpu_bin_flash_attr_is_visible, 5374 .is_visible = amdgpu_flash_attr_is_visible, 5375 }; 5376 5377 #if defined(CONFIG_DEBUG_FS) 5378 static int psp_read_spirom_debugfs_open(struct inode *inode, struct file *filp) 5379 { 5380 struct amdgpu_device *adev = filp->f_inode->i_private; 5381 struct spirom_bo *bo_triplet; 5382 int ret; 5383 5384 /* serialize the open() file calling */ 5385 if (!mutex_trylock(&adev->psp.mutex)) 5386 return -EBUSY; 5387 5388 /* 5389 * make sure only one userpace process is alive for dumping so that 5390 * only one memory buffer of AMD_VBIOS_FILE_MAX_SIZE * 2 is consumed. 5391 * let's say the case where one process try opening the file while 5392 * another one has proceeded to read or release. In this way, eliminate 5393 * the use of mutex for read() or release() callback as well. 5394 */ 5395 if (adev->psp.spirom_dump_trip) { 5396 mutex_unlock(&adev->psp.mutex); 5397 return -EBUSY; 5398 } 5399 5400 bo_triplet = kzalloc_obj(struct spirom_bo); 5401 if (!bo_triplet) { 5402 mutex_unlock(&adev->psp.mutex); 5403 return -ENOMEM; 5404 } 5405 5406 ret = amdgpu_bo_create_kernel(adev, AMD_VBIOS_FILE_MAX_SIZE_B * 2, 5407 AMDGPU_GPU_PAGE_SIZE, 5408 AMDGPU_GEM_DOMAIN_GTT, 5409 &bo_triplet->bo, 5410 &bo_triplet->mc_addr, 5411 &bo_triplet->cpu_addr); 5412 if (ret) 5413 goto rel_trip; 5414 5415 ret = psp_dump_spirom(&adev->psp, bo_triplet->mc_addr); 5416 if (ret) 5417 goto rel_bo; 5418 5419 adev->psp.spirom_dump_trip = bo_triplet; 5420 mutex_unlock(&adev->psp.mutex); 5421 return 0; 5422 rel_bo: 5423 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr, 5424 &bo_triplet->cpu_addr); 5425 rel_trip: 5426 kfree(bo_triplet); 5427 mutex_unlock(&adev->psp.mutex); 5428 dev_err(adev->dev, "Trying IFWI dump fails, err = %d\n", ret); 5429 return ret; 5430 } 5431 5432 static ssize_t psp_read_spirom_debugfs_read(struct file *filp, char __user *buf, size_t size, 5433 loff_t *pos) 5434 { 5435 struct amdgpu_device *adev = filp->f_inode->i_private; 5436 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip; 5437 5438 if (!bo_triplet) 5439 return -EINVAL; 5440 5441 return simple_read_from_buffer(buf, 5442 size, 5443 pos, bo_triplet->cpu_addr, 5444 AMD_VBIOS_FILE_MAX_SIZE_B * 2); 5445 } 5446 5447 static int psp_read_spirom_debugfs_release(struct inode *inode, struct file *filp) 5448 { 5449 struct amdgpu_device *adev = filp->f_inode->i_private; 5450 struct spirom_bo *bo_triplet = adev->psp.spirom_dump_trip; 5451 5452 if (bo_triplet) { 5453 amdgpu_bo_free_kernel(&bo_triplet->bo, &bo_triplet->mc_addr, 5454 &bo_triplet->cpu_addr); 5455 kfree(bo_triplet); 5456 } 5457 5458 adev->psp.spirom_dump_trip = NULL; 5459 return 0; 5460 } 5461 5462 static const struct file_operations psp_dump_spirom_debugfs_ops = { 5463 .owner = THIS_MODULE, 5464 .open = psp_read_spirom_debugfs_open, 5465 .read = psp_read_spirom_debugfs_read, 5466 .release = psp_read_spirom_debugfs_release, 5467 .llseek = default_llseek, 5468 }; 5469 #endif 5470 5471 void amdgpu_psp_debugfs_init(struct amdgpu_device *adev) 5472 { 5473 #if defined(CONFIG_DEBUG_FS) 5474 struct drm_minor *minor = adev_to_drm(adev)->primary; 5475 5476 debugfs_create_file_size("psp_spirom_dump", 0444, minor->debugfs_root, 5477 adev, &psp_dump_spirom_debugfs_ops, AMD_VBIOS_FILE_MAX_SIZE_B * 2); 5478 #endif 5479 } 5480 5481 const struct amd_ip_funcs psp_ip_funcs = { 5482 .name = "psp", 5483 .early_init = psp_early_init, 5484 .sw_init = psp_sw_init, 5485 .sw_fini = psp_sw_fini, 5486 .hw_init = psp_hw_init, 5487 .hw_fini = psp_hw_fini, 5488 .suspend = psp_suspend, 5489 .resume = psp_resume, 5490 .set_clockgating_state = psp_set_clockgating_state, 5491 .set_powergating_state = psp_set_powergating_state, 5492 }; 5493 5494 const struct amdgpu_ip_block_version psp_v3_1_ip_block = { 5495 .type = AMD_IP_BLOCK_TYPE_PSP, 5496 .major = 3, 5497 .minor = 1, 5498 .rev = 0, 5499 .funcs = &psp_ip_funcs, 5500 }; 5501 5502 const struct amdgpu_ip_block_version psp_v10_0_ip_block = { 5503 .type = AMD_IP_BLOCK_TYPE_PSP, 5504 .major = 10, 5505 .minor = 0, 5506 .rev = 0, 5507 .funcs = &psp_ip_funcs, 5508 }; 5509 5510 const struct amdgpu_ip_block_version psp_v11_0_ip_block = { 5511 .type = AMD_IP_BLOCK_TYPE_PSP, 5512 .major = 11, 5513 .minor = 0, 5514 .rev = 0, 5515 .funcs = &psp_ip_funcs, 5516 }; 5517 5518 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 5519 .type = AMD_IP_BLOCK_TYPE_PSP, 5520 .major = 11, 5521 .minor = 0, 5522 .rev = 8, 5523 .funcs = &psp_ip_funcs, 5524 }; 5525 5526 const struct amdgpu_ip_block_version psp_v12_0_ip_block = { 5527 .type = AMD_IP_BLOCK_TYPE_PSP, 5528 .major = 12, 5529 .minor = 0, 5530 .rev = 0, 5531 .funcs = &psp_ip_funcs, 5532 }; 5533 5534 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 5535 .type = AMD_IP_BLOCK_TYPE_PSP, 5536 .major = 13, 5537 .minor = 0, 5538 .rev = 0, 5539 .funcs = &psp_ip_funcs, 5540 }; 5541 5542 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 5543 .type = AMD_IP_BLOCK_TYPE_PSP, 5544 .major = 13, 5545 .minor = 0, 5546 .rev = 4, 5547 .funcs = &psp_ip_funcs, 5548 }; 5549 5550 const struct amdgpu_ip_block_version psp_v14_0_ip_block = { 5551 .type = AMD_IP_BLOCK_TYPE_PSP, 5552 .major = 14, 5553 .minor = 0, 5554 .rev = 0, 5555 .funcs = &psp_ip_funcs, 5556 }; 5557 5558 const struct amdgpu_ip_block_version psp_v15_0_ip_block = { 5559 .type = AMD_IP_BLOCK_TYPE_PSP, 5560 .major = 15, 5561 .minor = 0, 5562 .rev = 0, 5563 .funcs = &psp_ip_funcs, 5564 }; 5565 5566 const struct amdgpu_ip_block_version psp_v15_0_3_ip_block = { 5567 .type = AMD_IP_BLOCK_TYPE_PSP, 5568 .major = 15, 5569 .minor = 0, 5570 .rev = 3, 5571 .funcs = &psp_ip_funcs, 5572 }; 5573 5574 const struct amdgpu_ip_block_version psp_v15_0_8_ip_block = { 5575 .type = AMD_IP_BLOCK_TYPE_PSP, 5576 .major = 15, 5577 .minor = 0, 5578 .rev = 8, 5579 .funcs = &psp_ip_funcs, 5580 }; 5581