1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/clients/drm_client_setup.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_fbdev_ttm.h> 29 #include <drm/drm_gem.h> 30 #include <drm/drm_managed.h> 31 #include <drm/drm_pciids.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/drm_vblank.h> 34 35 #include <linux/cc_platform.h> 36 #include <linux/dynamic_debug.h> 37 #include <linux/module.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/suspend.h> 41 #include <linux/vga_switcheroo.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_amdkfd.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_drv.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_irq.h" 49 #include "amdgpu_psp.h" 50 #include "amdgpu_ras.h" 51 #include "amdgpu_reset.h" 52 #include "amdgpu_sched.h" 53 #include "amdgpu_xgmi.h" 54 #include "amdgpu_userq.h" 55 #include "amdgpu_userq_fence.h" 56 #include "../amdxcp/amdgpu_xcp_drv.h" 57 58 /* 59 * KMS wrapper. 60 * - 3.0.0 - initial driver 61 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 62 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 63 * at the end of IBs. 64 * - 3.3.0 - Add VM support for UVD on supported hardware. 65 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 66 * - 3.5.0 - Add support for new UVD_NO_OP register. 67 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 68 * - 3.7.0 - Add support for VCE clock list packet 69 * - 3.8.0 - Add support raster config init in the kernel 70 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 71 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 72 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 73 * - 3.12.0 - Add query for double offchip LDS buffers 74 * - 3.13.0 - Add PRT support 75 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 76 * - 3.15.0 - Export more gpu info for gfx9 77 * - 3.16.0 - Add reserved vmid support 78 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 79 * - 3.18.0 - Export gpu always on cu bitmap 80 * - 3.19.0 - Add support for UVD MJPEG decode 81 * - 3.20.0 - Add support for local BOs 82 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 83 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 84 * - 3.23.0 - Add query for VRAM lost counter 85 * - 3.24.0 - Add high priority compute support for gfx9 86 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 87 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 88 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 89 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 90 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 91 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 92 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 93 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 94 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 95 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 96 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 97 * - 3.36.0 - Allow reading more status registers on si/cik 98 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 99 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 100 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 101 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 102 * - 3.41.0 - Add video codec query 103 * - 3.42.0 - Add 16bpc fixed point display support 104 * - 3.43.0 - Add device hot plug/unplug support 105 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 106 * - 3.45.0 - Add context ioctl stable pstate interface 107 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 108 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 109 * - 3.48.0 - Add IP discovery version info to HW INFO 110 * - 3.49.0 - Add gang submit into CS IOCTL 111 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 112 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 113 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 114 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 115 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 116 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 117 * 3.53.0 - Support for GFX11 CP GFX shadowing 118 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 119 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 120 * - 3.56.0 - Update IB start address and size alignment for decode and encode 121 * - 3.57.0 - Compute tunneling on GFX10+ 122 * - 3.58.0 - Add GFX12 DCC support 123 * - 3.59.0 - Cleared VRAM 124 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement) 125 * - 3.61.0 - Contains fix for RV/PCO compute queues 126 * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT 127 * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size 128 * - 3.64.0 - Userq IP support query 129 */ 130 #define KMS_DRIVER_MAJOR 3 131 #define KMS_DRIVER_MINOR 64 132 #define KMS_DRIVER_PATCHLEVEL 0 133 134 /* 135 * amdgpu.debug module options. Are all disabled by default 136 */ 137 enum AMDGPU_DEBUG_MASK { 138 AMDGPU_DEBUG_VM = BIT(0), 139 AMDGPU_DEBUG_LARGEBAR = BIT(1), 140 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 141 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 142 AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5), 143 AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6), 144 AMDGPU_DEBUG_SMU_POOL = BIT(7), 145 AMDGPU_DEBUG_VM_USERPTR = BIT(8), 146 AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9), 147 AMDGPU_DEBUG_ENABLE_CE_CS = BIT(10), 148 AMDGPU_DEBUG_HIBERNATION_THAW_RESUME_GPU = BIT(11), 149 AMDGPU_DEBUG_DISABLE_IP_BLOCK_SOFT_RESET = BIT(12), 150 }; 151 152 unsigned int amdgpu_vram_limit = UINT_MAX; 153 int amdgpu_vis_vram_limit; 154 int amdgpu_gart_size = -1; /* auto */ 155 int amdgpu_gtt_size = -1; /* auto */ 156 int amdgpu_moverate = -1; /* auto */ 157 int amdgpu_audio = -1; 158 int amdgpu_disp_priority; 159 int amdgpu_hw_i2c; 160 int amdgpu_pcie_gen2 = -1; 161 int amdgpu_msi = -1; 162 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 163 int amdgpu_dpm = -1; 164 int amdgpu_fw_load_type = -1; 165 int amdgpu_aspm = -1; 166 int amdgpu_runtime_pm = -1; 167 uint amdgpu_ip_block_mask = 0xffffffff; 168 int amdgpu_bapm = -1; 169 int amdgpu_deep_color; 170 int amdgpu_vm_size = -1; 171 int amdgpu_vm_fragment_size = -1; 172 int amdgpu_vm_block_size = -1; 173 int amdgpu_vm_fault_stop; 174 int amdgpu_vm_update_mode = -1; 175 int amdgpu_exp_hw_support; 176 int amdgpu_dc = -1; 177 int amdgpu_sched_jobs = 32; 178 int amdgpu_sched_hw_submission = 2; 179 uint amdgpu_pcie_gen_cap; 180 uint amdgpu_pcie_lane_cap; 181 u64 amdgpu_cg_mask = 0xffffffffffffffff; 182 uint amdgpu_pg_mask = 0xffffffff; 183 uint amdgpu_sdma_phase_quantum = 32; 184 char *amdgpu_disable_cu; 185 char *amdgpu_virtual_display; 186 int amdgpu_enforce_isolation = -1; 187 int amdgpu_modeset = -1; 188 int amdgpu_iommu_perfopt = -1; 189 190 /* Specifies the default granularity for SVM, used in buffer 191 * migration and restoration of backing memory when handling 192 * recoverable page faults. 193 * 194 * The value is given as log(numPages(buffer)); for a 2 MiB 195 * buffer it computes to be 9 196 */ 197 uint amdgpu_svm_default_granularity = 9; 198 199 /* 200 * OverDrive(bit 14) disabled by default 201 * GFX DCS(bit 19) disabled by default 202 */ 203 uint amdgpu_pp_feature_mask = 0xfff7bfff; 204 uint amdgpu_force_long_training; 205 int amdgpu_lbpw = -1; 206 int amdgpu_compute_multipipe = -1; 207 int amdgpu_gpu_recovery = -1; /* auto */ 208 int amdgpu_emu_mode; 209 uint amdgpu_smu_memory_pool_size; 210 int amdgpu_smu_pptable_id = -1; 211 /* 212 * FBC (bit 0) disabled by default 213 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 214 * - With this, for multiple monitors in sync(e.g. with the same model), 215 * mclk switching will be allowed. And the mclk will be not foced to the 216 * highest. That helps saving some idle power. 217 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 218 * PSR (bit 3) disabled by default 219 * EDP NO POWER SEQUENCING (bit 4) disabled by default 220 */ 221 uint amdgpu_dc_feature_mask = 2; 222 uint amdgpu_dc_debug_mask; 223 uint amdgpu_dc_visual_confirm; 224 int amdgpu_async_gfx_ring = 1; 225 int amdgpu_mcbp = -1; 226 int amdgpu_discovery = -1; 227 int amdgpu_mes_log_enable = 0; 228 int amdgpu_uni_mes = 1; 229 int amdgpu_noretry = -1; 230 int amdgpu_force_asic_type = -1; 231 int amdgpu_tmz = -1; /* auto */ 232 uint amdgpu_freesync_vid_mode; 233 int amdgpu_reset_method = -1; /* auto */ 234 int amdgpu_num_kcq = -1; 235 int amdgpu_smartshift_bias; 236 int amdgpu_use_xgmi_p2p = 1; 237 int amdgpu_vcnfw_log; 238 int amdgpu_sg_display = -1; /* auto */ 239 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 240 int amdgpu_umsch_mm; 241 int amdgpu_seamless = -1; /* auto */ 242 uint amdgpu_debug_mask; 243 int amdgpu_agp = -1; /* auto */ 244 int amdgpu_wbrf = -1; 245 int amdgpu_damage_clips = -1; /* auto */ 246 int amdgpu_umsch_mm_fwlog; 247 int amdgpu_rebar = -1; /* auto */ 248 int amdgpu_user_queue = -1; 249 uint amdgpu_hdmi_hpd_debounce_delay_ms; 250 int amdgpu_ptl = -1; /* auto */ 251 252 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 253 "DRM_UT_CORE", 254 "DRM_UT_DRIVER", 255 "DRM_UT_KMS", 256 "DRM_UT_PRIME", 257 "DRM_UT_ATOMIC", 258 "DRM_UT_VBL", 259 "DRM_UT_STATE", 260 "DRM_UT_LEASE", 261 "DRM_UT_DP", 262 "DRM_UT_DRMRES"); 263 264 struct amdgpu_mgpu_info mgpu_info = { 265 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 266 }; 267 int amdgpu_ras_enable = -1; 268 uint amdgpu_ras_mask = 0xffffffff; 269 int amdgpu_bad_page_threshold = -1; 270 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 271 .timeout_fatal_disable = false, 272 .period = 0x0, /* default to 0x0 (timeout disable) */ 273 }; 274 275 /** 276 * DOC: vramlimit (int) 277 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 278 */ 279 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 280 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 281 282 /** 283 * DOC: vis_vramlimit (int) 284 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 285 */ 286 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 287 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 288 289 /** 290 * DOC: gartsize (uint) 291 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 292 * The default is -1 (The size depends on asic). 293 */ 294 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 295 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 296 297 /** 298 * DOC: gttsize (int) 299 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 300 * The default is -1 (Use value specified by TTM). 301 * This parameter is deprecated and will be removed in the future. 302 */ 303 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 304 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 305 306 /** 307 * DOC: moverate (int) 308 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 309 */ 310 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 311 module_param_named(moverate, amdgpu_moverate, int, 0600); 312 313 /** 314 * DOC: audio (int) 315 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 316 */ 317 MODULE_PARM_DESC(audio, "HDMI/DP Audio enable for non DC displays (-1 = auto, 0 = disable, 1 = enable)"); 318 module_param_named(audio, amdgpu_audio, int, 0444); 319 320 /** 321 * DOC: disp_priority (int) 322 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 323 */ 324 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 325 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 326 327 /** 328 * DOC: hw_i2c (int) 329 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 330 */ 331 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 332 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 333 334 /** 335 * DOC: pcie_gen2 (int) 336 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 337 */ 338 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 339 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 340 341 /** 342 * DOC: msi (int) 343 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 344 */ 345 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 346 module_param_named(msi, amdgpu_msi, int, 0444); 347 348 /** 349 * DOC: svm_default_granularity (uint) 350 * Used in buffer migration and handling of recoverable page faults 351 */ 352 MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB"); 353 module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644); 354 355 /** 356 * DOC: lockup_timeout (string) 357 * Set GPU scheduler timeout value in ms. 358 * 359 * The format can be [single value] for setting all timeouts at once or 360 * [GFX,Compute,SDMA,Video] to set individual timeouts. 361 * Negative values mean infinity. 362 * 363 * By default(with no lockup_timeout settings), the timeout for all queues is 2000. 364 */ 365 MODULE_PARM_DESC(lockup_timeout, 366 "GPU lockup timeout in ms (default: 2000. 0: keep default value. negative: infinity timeout), format: [single value for all] or [GFX,Compute,SDMA,Video]."); 367 module_param_string(lockup_timeout, amdgpu_lockup_timeout, 368 sizeof(amdgpu_lockup_timeout), 0444); 369 370 /** 371 * DOC: dpm (int) 372 * Override for dynamic power management setting 373 * (0 = disable, 1 = enable) 374 * The default is -1 (auto). 375 */ 376 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 377 module_param_named(dpm, amdgpu_dpm, int, 0444); 378 379 /** 380 * DOC: fw_load_type (int) 381 * Set different firmware loading type for debugging, if supported. 382 * Set to 0 to force direct loading if supported by the ASIC. Set 383 * to -1 to select the default loading mode for the ASIC, as defined 384 * by the driver. The default is -1 (auto). 385 */ 386 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 387 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 388 389 /** 390 * DOC: aspm (int) 391 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 392 */ 393 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 394 module_param_named(aspm, amdgpu_aspm, int, 0444); 395 396 /** 397 * DOC: iommu_perfopt (int) 398 * Control the AMD IOMMU PerfOpt DMA-latency optimization 399 * (0 = disable; -1 = enable on supported devices). 400 * This arms the IOMMU PerfOpt control (IOMMU spec, MMIO Offset 016Ch, EFR PerfOptSup / PerfOptEn) 401 * Arming it disables ATS, PRI, PASID and SVA for the GPU and removes IOMMU DMA containment for it, 402 * trading isolation for lower DMA latency. 403 */ 404 MODULE_PARM_DESC(iommu_perfopt, "Control IOMMU PerfOpt DMA-latency optimization (-1 = enable on supported devices, 0 = disable)"); 405 module_param_named(iommu_perfopt, amdgpu_iommu_perfopt, int, 0444); 406 407 /** 408 * DOC: runpm (int) 409 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 410 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 411 * Setting the value to 0 disables this functionality. 412 * Setting the value to -2 is auto enabled with power down when displays are attached. 413 */ 414 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 415 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 416 417 /** 418 * DOC: ip_block_mask (uint) 419 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 420 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 421 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 422 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 423 */ 424 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 425 module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 426 427 /** 428 * DOC: bapm (int) 429 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 430 * The default -1 (auto, enabled) 431 */ 432 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 433 module_param_named(bapm, amdgpu_bapm, int, 0444); 434 435 /** 436 * DOC: deep_color (int) 437 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 438 */ 439 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 440 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 441 442 /** 443 * DOC: vm_size (int) 444 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 445 */ 446 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 447 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 448 449 /** 450 * DOC: vm_fragment_size (int) 451 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 452 */ 453 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 454 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 455 456 /** 457 * DOC: vm_block_size (int) 458 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 459 */ 460 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 461 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 462 463 /** 464 * DOC: vm_fault_stop (int) 465 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 466 */ 467 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 468 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 469 470 /** 471 * DOC: vm_update_mode (int) 472 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 473 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 474 */ 475 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 476 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 477 478 /** 479 * DOC: exp_hw_support (int) 480 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 481 */ 482 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 483 module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 484 485 /** 486 * DOC: dc (int) 487 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 488 */ 489 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 490 module_param_named(dc, amdgpu_dc, int, 0444); 491 492 /** 493 * DOC: sched_jobs (int) 494 * Override the max number of jobs supported in the sw queue. The default is 32. 495 */ 496 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 497 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 498 499 /** 500 * DOC: sched_hw_submission (int) 501 * Override the max number of HW submissions. The default is 2. 502 */ 503 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 504 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 505 506 /** 507 * DOC: ppfeaturemask (hexint) 508 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 509 * The default is the current set of stable power features. 510 */ 511 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 512 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 513 514 /** 515 * DOC: forcelongtraining (uint) 516 * Force long memory training in resume. 517 * The default is zero, indicates short training in resume. 518 */ 519 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 520 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 521 522 /** 523 * DOC: pcie_gen_cap (uint) 524 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 525 * The default is 0 (automatic for each asic). 526 */ 527 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 528 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 529 530 /** 531 * DOC: pcie_lane_cap (uint) 532 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 533 * The default is 0 (automatic for each asic). 534 */ 535 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 536 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 537 538 /** 539 * DOC: cg_mask (ullong) 540 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 541 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 542 */ 543 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 544 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 545 546 /** 547 * DOC: pg_mask (uint) 548 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 549 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 550 */ 551 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 552 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 553 554 /** 555 * DOC: sdma_phase_quantum (uint) 556 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 557 */ 558 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 559 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 560 561 /** 562 * DOC: disable_cu (charp) 563 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 564 */ 565 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 566 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 567 568 /** 569 * DOC: virtual_display (charp) 570 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 571 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 572 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 573 * device at 26:00.0. The default is NULL. 574 */ 575 MODULE_PARM_DESC(virtual_display, 576 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 577 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 578 579 /** 580 * DOC: lbpw (int) 581 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 582 */ 583 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 584 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 585 586 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 587 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 588 589 /** 590 * DOC: gpu_recovery (int) 591 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 592 */ 593 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 594 module_param_named_unsafe(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 595 596 /** 597 * DOC: emu_mode (int) 598 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 599 */ 600 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 601 module_param_named_unsafe(emu_mode, amdgpu_emu_mode, int, 0444); 602 603 /** 604 * DOC: ras_enable (int) 605 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 606 */ 607 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 608 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 609 610 /** 611 * DOC: ras_mask (uint) 612 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 613 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 614 */ 615 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 616 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 617 618 /** 619 * DOC: timeout_fatal_disable (bool) 620 * Disable Watchdog timeout fatal error event 621 */ 622 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 623 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 624 625 /** 626 * DOC: timeout_period (uint) 627 * Modify the watchdog timeout max_cycles as (1 << period) 628 */ 629 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 630 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 631 632 /** 633 * DOC: si_support (int) 634 * 1 = enabled, 0 = disabled, -1 = default 635 * 636 * SI (Southern Islands) are first generation GCN GPUs, supported by both 637 * drivers: radeon (old) and amdgpu (new). This parameter controls whether 638 * amdgpu should support SI. 639 * By default, SI dedicated GPUs are supported by amdgpu. 640 * Only relevant when CONFIG_DRM_AMDGPU_SI is enabled to build SI support in amdgpu. 641 * See also radeon.si_support which should be disabled when amdgpu.si_support is 642 * enabled, and vice versa. 643 */ 644 int amdgpu_si_support = -1; 645 #ifdef CONFIG_DRM_AMDGPU_SI 646 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled, -1 = default)"); 647 module_param_named(si_support, amdgpu_si_support, int, 0444); 648 #endif 649 650 /** 651 * DOC: cik_support (int) 652 * 1 = enabled, 0 = disabled, -1 = default 653 * 654 * CIK (Sea Islands) are second generation GCN GPUs, supported by both 655 * drivers: radeon (old) and amdgpu (new). This parameter controls whether 656 * amdgpu should support CIK. 657 * By default, CIK dedicated GPUs and APUs are supported by amdgpu. 658 * Only relevant when CONFIG_DRM_AMDGPU_CIK is enabled to build CIK support in amdgpu. 659 * See also radeon.cik_support which should be disabled when amdgpu.cik_support is 660 * enabled, and vice versa. 661 */ 662 int amdgpu_cik_support = -1; 663 #ifdef CONFIG_DRM_AMDGPU_CIK 664 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled, -1 = default)"); 665 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 666 #endif 667 668 /** 669 * DOC: smu_memory_pool_size (uint) 670 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 671 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 672 */ 673 MODULE_PARM_DESC(smu_memory_pool_size, 674 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 675 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 676 677 /** 678 * DOC: async_gfx_ring (int) 679 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 680 */ 681 MODULE_PARM_DESC(async_gfx_ring, 682 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 683 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 684 685 /** 686 * DOC: mcbp (int) 687 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 688 */ 689 MODULE_PARM_DESC(mcbp, 690 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 691 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 692 693 /** 694 * DOC: discovery (int) 695 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 696 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 697 */ 698 MODULE_PARM_DESC(discovery, 699 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 700 module_param_named(discovery, amdgpu_discovery, int, 0444); 701 702 /** 703 * DOC: mes_log_enable (int) 704 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. 705 * (0 = disabled (default), 1 = enabled) 706 */ 707 MODULE_PARM_DESC(mes_log_enable, 708 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); 709 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); 710 711 /** 712 * DOC: uni_mes (int) 713 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. 714 * (0 = disabled (default), 1 = enabled) 715 */ 716 MODULE_PARM_DESC(uni_mes, 717 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)"); 718 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444); 719 720 /** 721 * DOC: noretry (int) 722 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 723 * do not support per-process XNACK this also disables retry page faults. 724 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 725 */ 726 MODULE_PARM_DESC(noretry, 727 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 728 module_param_named(noretry, amdgpu_noretry, int, 0644); 729 730 /** 731 * DOC: force_asic_type (int) 732 * A non negative value used to specify the asic type for all supported GPUs. 733 */ 734 MODULE_PARM_DESC(force_asic_type, 735 "A non negative value used to specify the asic type for all supported GPUs"); 736 module_param_named_unsafe(force_asic_type, amdgpu_force_asic_type, int, 0444); 737 738 /** 739 * DOC: use_xgmi_p2p (int) 740 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 741 */ 742 MODULE_PARM_DESC(use_xgmi_p2p, 743 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 744 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 745 746 747 #ifdef CONFIG_HSA_AMD 748 /** 749 * DOC: sched_policy (int) 750 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 751 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 752 * assigns queues to HQDs. 753 */ 754 int sched_policy = KFD_SCHED_POLICY_HWS; 755 module_param_unsafe(sched_policy, int, 0444); 756 MODULE_PARM_DESC(sched_policy, 757 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 758 759 /** 760 * DOC: hws_max_conc_proc (int) 761 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 762 * number of VMIDs assigned to the HWS, which is also the default. 763 */ 764 int hws_max_conc_proc = -1; 765 module_param(hws_max_conc_proc, int, 0444); 766 MODULE_PARM_DESC(hws_max_conc_proc, 767 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 768 769 /** 770 * DOC: cwsr_enable (int) 771 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 772 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 773 * disables it. 774 */ 775 int cwsr_enable = 1; 776 module_param(cwsr_enable, int, 0444); 777 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 778 779 /** 780 * DOC: max_num_of_queues_per_device (int) 781 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 782 * is 4096. 783 */ 784 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 785 module_param(max_num_of_queues_per_device, int, 0444); 786 MODULE_PARM_DESC(max_num_of_queues_per_device, 787 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 788 789 /** 790 * DOC: send_sigterm (int) 791 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 792 * but just print errors on dmesg. Setting 1 enables sending sigterm. 793 */ 794 int send_sigterm; 795 module_param(send_sigterm, int, 0444); 796 MODULE_PARM_DESC(send_sigterm, 797 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 798 799 /** 800 * DOC: halt_if_hws_hang (int) 801 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 802 * Setting 1 enables halt on hang. 803 */ 804 int halt_if_hws_hang; 805 module_param_unsafe(halt_if_hws_hang, int, 0644); 806 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 807 808 /** 809 * DOC: hws_gws_support(bool) 810 * Assume that HWS supports GWS barriers regardless of what firmware version 811 * check says. Default value: false (rely on MEC2 firmware version check). 812 */ 813 bool hws_gws_support; 814 module_param_unsafe(hws_gws_support, bool, 0444); 815 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 816 817 /** 818 * DOC: queue_preemption_timeout_ms (int) 819 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 820 */ 821 int queue_preemption_timeout_ms = 9000; 822 module_param(queue_preemption_timeout_ms, int, 0644); 823 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 824 825 /** 826 * DOC: debug_evictions(bool) 827 * Enable extra debug messages to help determine the cause of evictions 828 */ 829 bool debug_evictions; 830 module_param(debug_evictions, bool, 0644); 831 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 832 833 /** 834 * DOC: no_system_mem_limit(bool) 835 * Disable system memory limit, to support multiple process shared memory 836 */ 837 bool no_system_mem_limit; 838 module_param(no_system_mem_limit, bool, 0644); 839 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 840 841 /** 842 * DOC: no_queue_eviction_on_vm_fault (int) 843 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 844 */ 845 int amdgpu_no_queue_eviction_on_vm_fault; 846 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 847 module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 848 #endif 849 850 /** 851 * DOC: mtype_local (int) 852 */ 853 int amdgpu_mtype_local = -1; 854 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (default: ASIC dependent, 0 = MTYPE_RW, 1 = MTYPE_NC, 2 = MTYPE_CC)"); 855 module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444); 856 857 /** 858 * DOC: pcie_p2p (bool) 859 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 860 */ 861 #ifdef CONFIG_HSA_AMD_P2P 862 bool pcie_p2p = true; 863 module_param(pcie_p2p, bool, 0444); 864 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 865 #endif 866 867 /** 868 * DOC: dcfeaturemask (uint) 869 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 870 * The default is the current set of stable display features. 871 */ 872 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 873 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 874 875 /** 876 * DOC: dcdebugmask (uint) 877 * Display debug options. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 878 */ 879 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 880 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 881 882 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 883 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 884 885 /** 886 * DOC: abmlevel (uint) 887 * Override the default ABM (Adaptive Backlight Management) level used for DC 888 * enabled hardware. Requires DMCU to be supported and loaded. 889 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 890 * default. Values 1-4 control the maximum allowable brightness reduction via 891 * the ABM algorithm, with 1 being the least reduction and 4 being the most 892 * reduction. 893 * 894 * Defaults to -1, or auto. Userspace can only override this level after 895 * boot if it's set to auto. 896 */ 897 int amdgpu_dm_abm_level = -1; 898 MODULE_PARM_DESC(abmlevel, 899 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 900 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 901 902 int amdgpu_backlight = -1; 903 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 904 module_param_named(backlight, amdgpu_backlight, bint, 0444); 905 906 /** 907 * DOC: damageclips (int) 908 * Enable or disable damage clips support. If damage clips support is disabled, 909 * we will force full frame updates, irrespective of what user space sends to 910 * us. 911 * 912 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 913 */ 914 MODULE_PARM_DESC(damageclips, 915 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 916 module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 917 918 /** 919 * DOC: tmz (int) 920 * Trusted Memory Zone (TMZ) is a method to protect data being written 921 * to or read from memory. 922 * 923 * The default value: 0 (off). TODO: change to auto till it is completed. 924 */ 925 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 926 module_param_named(tmz, amdgpu_tmz, int, 0444); 927 928 /** 929 * DOC: freesync_video (uint) 930 * Enable the optimization to adjust front porch timing to achieve seamless 931 * mode change experience when setting a freesync supported mode for which full 932 * modeset is not needed. 933 * 934 * The Display Core will add a set of modes derived from the base FreeSync 935 * video mode into the corresponding connector's mode list based on commonly 936 * used refresh rates and VRR range of the connected display, when users enable 937 * this feature. From the userspace perspective, they can see a seamless mode 938 * change experience when the change between different refresh rates under the 939 * same resolution. Additionally, userspace applications such as Video playback 940 * can read this modeset list and change the refresh rate based on the video 941 * frame rate. Finally, the userspace can also derive an appropriate mode for a 942 * particular refresh rate based on the FreeSync Mode and add it to the 943 * connector's mode list. 944 * 945 * Note: This is an experimental feature. 946 * 947 * The default value: 0 (off). 948 */ 949 MODULE_PARM_DESC( 950 freesync_video, 951 "Adds additional modes via VRR for refresh changes without a full modeset (0 = off (default), 1 = on)"); 952 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 953 954 /** 955 * DOC: reset_method (int) 956 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 957 */ 958 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 959 module_param_named_unsafe(reset_method, amdgpu_reset_method, int, 0644); 960 961 /** 962 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 963 * threshold value of faulty pages detected by RAS ECC, which may 964 * result in the GPU entering bad status when the number of total 965 * faulty pages by ECC exceeds the threshold value. 966 */ 967 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = threshold determined by a formula, 0 < threshold < max records, user-defined threshold)"); 968 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 969 970 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 971 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 972 973 /** 974 * DOC: vcnfw_log (int) 975 * Enable vcnfw log output for debugging, the default is disabled. 976 */ 977 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 978 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 979 980 /** 981 * DOC: sg_display (int) 982 * Disable S/G (scatter/gather) display (i.e., display from system memory). 983 * This option is only relevant on APUs. Set this option to 0 to disable 984 * S/G display if you experience flickering or other issues under memory 985 * pressure and report the issue. 986 */ 987 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 988 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 989 990 /** 991 * DOC: umsch_mm (int) 992 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 993 * (0 = disabled (default), 1 = enabled) 994 */ 995 MODULE_PARM_DESC(umsch_mm, 996 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 997 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 998 999 /** 1000 * DOC: umsch_mm_fwlog (int) 1001 * Enable umschfw log output for debugging, the default is disabled. 1002 */ 1003 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)"); 1004 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444); 1005 1006 /** 1007 * DOC: smu_pptable_id (int) 1008 * Used to override pptable id. id = 0 use VBIOS pptable. 1009 * id > 0 use the soft pptable with specicfied id. 1010 */ 1011 MODULE_PARM_DESC(smu_pptable_id, 1012 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 1013 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 1014 1015 /** 1016 * DOC: partition_mode (int) 1017 * Used to override the default SPX mode. 1018 */ 1019 MODULE_PARM_DESC( 1020 user_partt_mode, 1021 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 1022 0 = AMDGPU_SPX_PARTITION_MODE, \ 1023 1 = AMDGPU_DPX_PARTITION_MODE, \ 1024 2 = AMDGPU_TPX_PARTITION_MODE, \ 1025 3 = AMDGPU_QPX_PARTITION_MODE, \ 1026 4 = AMDGPU_CPX_PARTITION_MODE)"); 1027 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 1028 1029 1030 /** 1031 * DOC: enforce_isolation (int) 1032 * enforce process isolation between graphics and compute. 1033 * (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader) 1034 */ 1035 module_param_named(enforce_isolation, amdgpu_enforce_isolation, int, 0444); 1036 MODULE_PARM_DESC(enforce_isolation, 1037 "enforce process isolation between graphics and compute. (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader)"); 1038 1039 /** 1040 * DOC: modeset (int) 1041 * Override nomodeset (1 = override, -1 = auto). The default is -1 (auto). 1042 */ 1043 MODULE_PARM_DESC(modeset, "Override nomodeset (1 = enable, -1 = auto)"); 1044 module_param_named(modeset, amdgpu_modeset, int, 0444); 1045 1046 /** 1047 * DOC: seamless (int) 1048 * Seamless boot will keep the image on the screen during the boot process. 1049 */ 1050 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 1051 module_param_named(seamless, amdgpu_seamless, int, 0444); 1052 1053 /** 1054 * DOC: debug_mask (uint) 1055 * Debug options for amdgpu, work as a binary mask with the following options: 1056 * 1057 * - 0x1: Debug VM handling 1058 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1059 * limits the VRAM size reported to ROCm applications to the visible 1060 * size, usually 256MB. 1061 * - 0x4: Disable GPU soft recovery, always do a full reset 1062 * - 0x8: Use VRAM for firmware loading 1063 * - 0x10: Enable ACA based RAS logging 1064 * - 0x20: Enable experimental resets 1065 * - 0x40: Disable ring resets 1066 * - 0x80: Use VRAM for SMU pool 1067 */ 1068 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1069 module_param_named_unsafe(debug_mask, amdgpu_debug_mask, uint, 0444); 1070 1071 /** 1072 * DOC: agp (int) 1073 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1074 * address space for direct access to system memory. Note that these accesses 1075 * are non-snooped, so they are only used for access to uncached memory. 1076 */ 1077 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1078 module_param_named(agp, amdgpu_agp, int, 0444); 1079 1080 /** 1081 * DOC: wbrf (int) 1082 * Enable Wifi RFI interference mitigation feature. 1083 * Due to electrical and mechanical constraints there may be likely interference of 1084 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1085 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1086 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1087 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1088 * P-state transition. However, there may be potential performance impact with this 1089 * feature enabled. 1090 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1091 */ 1092 MODULE_PARM_DESC(wbrf, 1093 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1094 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1095 1096 /** 1097 * DOC: rebar (int) 1098 * Allow BAR resizing. Disable this to prevent the driver from attempting 1099 * to resize the BAR if the GPU supports it and there is available MMIO space. 1100 * Note that this just prevents the driver from resizing the BAR. The BIOS 1101 * may have already resized the BAR at boot time. 1102 */ 1103 MODULE_PARM_DESC(rebar, "Resizable BAR (-1 = auto (default), 0 = disable, 1 = enable)"); 1104 module_param_named(rebar, amdgpu_rebar, int, 0444); 1105 1106 /** 1107 * DOC: user_queue (int) 1108 * Enable user queues on systems that support user queues. Possible values: 1109 * 1110 * - -1 = auto (ASIC specific default) 1111 * - 0 = user queues disabled 1112 * - 1 = user queues enabled and kernel queues enabled (if supported) 1113 * - 2 = user queues enabled and kernel queues disabled 1114 */ 1115 MODULE_PARM_DESC(user_queue, "Enable user queues (-1 = auto (default), 0 = disable, 1 = enable, 2 = enable UQs and disable KQs)"); 1116 module_param_named(user_queue, amdgpu_user_queue, int, 0444); 1117 1118 /* 1119 * DOC: hdmi_hpd_debounce_delay_ms (uint) 1120 * HDMI HPD disconnect debounce delay in milliseconds. 1121 * 1122 * Used to filter short disconnect->reconnect HPD toggles some HDMI sinks 1123 * generate while entering/leaving power save. Set to 0 to disable by default. 1124 */ 1125 MODULE_PARM_DESC(hdmi_hpd_debounce_delay_ms, "HDMI HPD disconnect debounce delay in milliseconds (0 to disable (by default), 1500 is common)"); 1126 module_param_named(hdmi_hpd_debounce_delay_ms, amdgpu_hdmi_hpd_debounce_delay_ms, uint, 0644); 1127 1128 /** 1129 * DOC: ptl (int) 1130 * Enable PTL feature at boot time. Possible values: 1131 * 1132 * - -1 = auto (ASIC specific default) 1133 * - 0 = disable PTL (default) 1134 * - 1 = enable PTL 1135 * - 2 = permanently disable PTL (cannot be re-enabled at runtime) 1136 */ 1137 MODULE_PARM_DESC(ptl, "Enable PTL (-1 = auto, 0 = disable (default), 1 = enable, 2 = permanently disable)"); 1138 module_param_named(ptl, amdgpu_ptl, int, 0444); 1139 1140 /* These devices are not supported by amdgpu. 1141 * They are supported by the mach64, r128, radeon drivers 1142 */ 1143 static const u16 amdgpu_unsupported_pciidlist[] = { 1144 /* mach64 */ 1145 0x4354, 1146 0x4358, 1147 0x4554, 1148 0x4742, 1149 0x4744, 1150 0x4749, 1151 0x474C, 1152 0x474D, 1153 0x474E, 1154 0x474F, 1155 0x4750, 1156 0x4751, 1157 0x4752, 1158 0x4753, 1159 0x4754, 1160 0x4755, 1161 0x4756, 1162 0x4757, 1163 0x4758, 1164 0x4759, 1165 0x475A, 1166 0x4C42, 1167 0x4C44, 1168 0x4C47, 1169 0x4C49, 1170 0x4C4D, 1171 0x4C4E, 1172 0x4C50, 1173 0x4C51, 1174 0x4C52, 1175 0x4C53, 1176 0x5654, 1177 0x5655, 1178 0x5656, 1179 /* r128 */ 1180 0x4c45, 1181 0x4c46, 1182 0x4d46, 1183 0x4d4c, 1184 0x5041, 1185 0x5042, 1186 0x5043, 1187 0x5044, 1188 0x5045, 1189 0x5046, 1190 0x5047, 1191 0x5048, 1192 0x5049, 1193 0x504A, 1194 0x504B, 1195 0x504C, 1196 0x504D, 1197 0x504E, 1198 0x504F, 1199 0x5050, 1200 0x5051, 1201 0x5052, 1202 0x5053, 1203 0x5054, 1204 0x5055, 1205 0x5056, 1206 0x5057, 1207 0x5058, 1208 0x5245, 1209 0x5246, 1210 0x5247, 1211 0x524b, 1212 0x524c, 1213 0x534d, 1214 0x5446, 1215 0x544C, 1216 0x5452, 1217 /* radeon */ 1218 0x3150, 1219 0x3151, 1220 0x3152, 1221 0x3154, 1222 0x3155, 1223 0x3E50, 1224 0x3E54, 1225 0x4136, 1226 0x4137, 1227 0x4144, 1228 0x4145, 1229 0x4146, 1230 0x4147, 1231 0x4148, 1232 0x4149, 1233 0x414A, 1234 0x414B, 1235 0x4150, 1236 0x4151, 1237 0x4152, 1238 0x4153, 1239 0x4154, 1240 0x4155, 1241 0x4156, 1242 0x4237, 1243 0x4242, 1244 0x4336, 1245 0x4337, 1246 0x4437, 1247 0x4966, 1248 0x4967, 1249 0x4A48, 1250 0x4A49, 1251 0x4A4A, 1252 0x4A4B, 1253 0x4A4C, 1254 0x4A4D, 1255 0x4A4E, 1256 0x4A4F, 1257 0x4A50, 1258 0x4A54, 1259 0x4B48, 1260 0x4B49, 1261 0x4B4A, 1262 0x4B4B, 1263 0x4B4C, 1264 0x4C57, 1265 0x4C58, 1266 0x4C59, 1267 0x4C5A, 1268 0x4C64, 1269 0x4C66, 1270 0x4C67, 1271 0x4E44, 1272 0x4E45, 1273 0x4E46, 1274 0x4E47, 1275 0x4E48, 1276 0x4E49, 1277 0x4E4A, 1278 0x4E4B, 1279 0x4E50, 1280 0x4E51, 1281 0x4E52, 1282 0x4E53, 1283 0x4E54, 1284 0x4E56, 1285 0x5144, 1286 0x5145, 1287 0x5146, 1288 0x5147, 1289 0x5148, 1290 0x514C, 1291 0x514D, 1292 0x5157, 1293 0x5158, 1294 0x5159, 1295 0x515A, 1296 0x515E, 1297 0x5460, 1298 0x5462, 1299 0x5464, 1300 0x5548, 1301 0x5549, 1302 0x554A, 1303 0x554B, 1304 0x554C, 1305 0x554D, 1306 0x554E, 1307 0x554F, 1308 0x5550, 1309 0x5551, 1310 0x5552, 1311 0x5554, 1312 0x564A, 1313 0x564B, 1314 0x564F, 1315 0x5652, 1316 0x5653, 1317 0x5657, 1318 0x5834, 1319 0x5835, 1320 0x5954, 1321 0x5955, 1322 0x5974, 1323 0x5975, 1324 0x5960, 1325 0x5961, 1326 0x5962, 1327 0x5964, 1328 0x5965, 1329 0x5969, 1330 0x5a41, 1331 0x5a42, 1332 0x5a61, 1333 0x5a62, 1334 0x5b60, 1335 0x5b62, 1336 0x5b63, 1337 0x5b64, 1338 0x5b65, 1339 0x5c61, 1340 0x5c63, 1341 0x5d48, 1342 0x5d49, 1343 0x5d4a, 1344 0x5d4c, 1345 0x5d4d, 1346 0x5d4e, 1347 0x5d4f, 1348 0x5d50, 1349 0x5d52, 1350 0x5d57, 1351 0x5e48, 1352 0x5e4a, 1353 0x5e4b, 1354 0x5e4c, 1355 0x5e4d, 1356 0x5e4f, 1357 0x6700, 1358 0x6701, 1359 0x6702, 1360 0x6703, 1361 0x6704, 1362 0x6705, 1363 0x6706, 1364 0x6707, 1365 0x6708, 1366 0x6709, 1367 0x6718, 1368 0x6719, 1369 0x671c, 1370 0x671d, 1371 0x671f, 1372 0x6720, 1373 0x6721, 1374 0x6722, 1375 0x6723, 1376 0x6724, 1377 0x6725, 1378 0x6726, 1379 0x6727, 1380 0x6728, 1381 0x6729, 1382 0x6738, 1383 0x6739, 1384 0x673e, 1385 0x6740, 1386 0x6741, 1387 0x6742, 1388 0x6743, 1389 0x6744, 1390 0x6745, 1391 0x6746, 1392 0x6747, 1393 0x6748, 1394 0x6749, 1395 0x674A, 1396 0x6750, 1397 0x6751, 1398 0x6758, 1399 0x6759, 1400 0x675B, 1401 0x675D, 1402 0x675F, 1403 0x6760, 1404 0x6761, 1405 0x6762, 1406 0x6763, 1407 0x6764, 1408 0x6765, 1409 0x6766, 1410 0x6767, 1411 0x6768, 1412 0x6770, 1413 0x6771, 1414 0x6772, 1415 0x6778, 1416 0x6779, 1417 0x677B, 1418 0x6840, 1419 0x6841, 1420 0x6842, 1421 0x6843, 1422 0x6849, 1423 0x684C, 1424 0x6850, 1425 0x6858, 1426 0x6859, 1427 0x6880, 1428 0x6888, 1429 0x6889, 1430 0x688A, 1431 0x688C, 1432 0x688D, 1433 0x6898, 1434 0x6899, 1435 0x689b, 1436 0x689c, 1437 0x689d, 1438 0x689e, 1439 0x68a0, 1440 0x68a1, 1441 0x68a8, 1442 0x68a9, 1443 0x68b0, 1444 0x68b8, 1445 0x68b9, 1446 0x68ba, 1447 0x68be, 1448 0x68bf, 1449 0x68c0, 1450 0x68c1, 1451 0x68c7, 1452 0x68c8, 1453 0x68c9, 1454 0x68d8, 1455 0x68d9, 1456 0x68da, 1457 0x68de, 1458 0x68e0, 1459 0x68e1, 1460 0x68e4, 1461 0x68e5, 1462 0x68e8, 1463 0x68e9, 1464 0x68f1, 1465 0x68f2, 1466 0x68f8, 1467 0x68f9, 1468 0x68fa, 1469 0x68fe, 1470 0x7100, 1471 0x7101, 1472 0x7102, 1473 0x7103, 1474 0x7104, 1475 0x7105, 1476 0x7106, 1477 0x7108, 1478 0x7109, 1479 0x710A, 1480 0x710B, 1481 0x710C, 1482 0x710E, 1483 0x710F, 1484 0x7140, 1485 0x7141, 1486 0x7142, 1487 0x7143, 1488 0x7144, 1489 0x7145, 1490 0x7146, 1491 0x7147, 1492 0x7149, 1493 0x714A, 1494 0x714B, 1495 0x714C, 1496 0x714D, 1497 0x714E, 1498 0x714F, 1499 0x7151, 1500 0x7152, 1501 0x7153, 1502 0x715E, 1503 0x715F, 1504 0x7180, 1505 0x7181, 1506 0x7183, 1507 0x7186, 1508 0x7187, 1509 0x7188, 1510 0x718A, 1511 0x718B, 1512 0x718C, 1513 0x718D, 1514 0x718F, 1515 0x7193, 1516 0x7196, 1517 0x719B, 1518 0x719F, 1519 0x71C0, 1520 0x71C1, 1521 0x71C2, 1522 0x71C3, 1523 0x71C4, 1524 0x71C5, 1525 0x71C6, 1526 0x71C7, 1527 0x71CD, 1528 0x71CE, 1529 0x71D2, 1530 0x71D4, 1531 0x71D5, 1532 0x71D6, 1533 0x71DA, 1534 0x71DE, 1535 0x7200, 1536 0x7210, 1537 0x7211, 1538 0x7240, 1539 0x7243, 1540 0x7244, 1541 0x7245, 1542 0x7246, 1543 0x7247, 1544 0x7248, 1545 0x7249, 1546 0x724A, 1547 0x724B, 1548 0x724C, 1549 0x724D, 1550 0x724E, 1551 0x724F, 1552 0x7280, 1553 0x7281, 1554 0x7283, 1555 0x7284, 1556 0x7287, 1557 0x7288, 1558 0x7289, 1559 0x728B, 1560 0x728C, 1561 0x7290, 1562 0x7291, 1563 0x7293, 1564 0x7297, 1565 0x7834, 1566 0x7835, 1567 0x791e, 1568 0x791f, 1569 0x793f, 1570 0x7941, 1571 0x7942, 1572 0x796c, 1573 0x796d, 1574 0x796e, 1575 0x796f, 1576 0x9400, 1577 0x9401, 1578 0x9402, 1579 0x9403, 1580 0x9405, 1581 0x940A, 1582 0x940B, 1583 0x940F, 1584 0x94A0, 1585 0x94A1, 1586 0x94A3, 1587 0x94B1, 1588 0x94B3, 1589 0x94B4, 1590 0x94B5, 1591 0x94B9, 1592 0x9440, 1593 0x9441, 1594 0x9442, 1595 0x9443, 1596 0x9444, 1597 0x9446, 1598 0x944A, 1599 0x944B, 1600 0x944C, 1601 0x944E, 1602 0x9450, 1603 0x9452, 1604 0x9456, 1605 0x945A, 1606 0x945B, 1607 0x945E, 1608 0x9460, 1609 0x9462, 1610 0x946A, 1611 0x946B, 1612 0x947A, 1613 0x947B, 1614 0x9480, 1615 0x9487, 1616 0x9488, 1617 0x9489, 1618 0x948A, 1619 0x948F, 1620 0x9490, 1621 0x9491, 1622 0x9495, 1623 0x9498, 1624 0x949C, 1625 0x949E, 1626 0x949F, 1627 0x94C0, 1628 0x94C1, 1629 0x94C3, 1630 0x94C4, 1631 0x94C5, 1632 0x94C6, 1633 0x94C7, 1634 0x94C8, 1635 0x94C9, 1636 0x94CB, 1637 0x94CC, 1638 0x94CD, 1639 0x9500, 1640 0x9501, 1641 0x9504, 1642 0x9505, 1643 0x9506, 1644 0x9507, 1645 0x9508, 1646 0x9509, 1647 0x950F, 1648 0x9511, 1649 0x9515, 1650 0x9517, 1651 0x9519, 1652 0x9540, 1653 0x9541, 1654 0x9542, 1655 0x954E, 1656 0x954F, 1657 0x9552, 1658 0x9553, 1659 0x9555, 1660 0x9557, 1661 0x955f, 1662 0x9580, 1663 0x9581, 1664 0x9583, 1665 0x9586, 1666 0x9587, 1667 0x9588, 1668 0x9589, 1669 0x958A, 1670 0x958B, 1671 0x958C, 1672 0x958D, 1673 0x958E, 1674 0x958F, 1675 0x9590, 1676 0x9591, 1677 0x9593, 1678 0x9595, 1679 0x9596, 1680 0x9597, 1681 0x9598, 1682 0x9599, 1683 0x959B, 1684 0x95C0, 1685 0x95C2, 1686 0x95C4, 1687 0x95C5, 1688 0x95C6, 1689 0x95C7, 1690 0x95C9, 1691 0x95CC, 1692 0x95CD, 1693 0x95CE, 1694 0x95CF, 1695 0x9610, 1696 0x9611, 1697 0x9612, 1698 0x9613, 1699 0x9614, 1700 0x9615, 1701 0x9616, 1702 0x9640, 1703 0x9641, 1704 0x9642, 1705 0x9643, 1706 0x9644, 1707 0x9645, 1708 0x9647, 1709 0x9648, 1710 0x9649, 1711 0x964a, 1712 0x964b, 1713 0x964c, 1714 0x964e, 1715 0x964f, 1716 0x9710, 1717 0x9711, 1718 0x9712, 1719 0x9713, 1720 0x9714, 1721 0x9715, 1722 0x9802, 1723 0x9803, 1724 0x9804, 1725 0x9805, 1726 0x9806, 1727 0x9807, 1728 0x9808, 1729 0x9809, 1730 0x980A, 1731 0x9900, 1732 0x9901, 1733 0x9903, 1734 0x9904, 1735 0x9905, 1736 0x9906, 1737 0x9907, 1738 0x9908, 1739 0x9909, 1740 0x990A, 1741 0x990B, 1742 0x990C, 1743 0x990D, 1744 0x990E, 1745 0x990F, 1746 0x9910, 1747 0x9913, 1748 0x9917, 1749 0x9918, 1750 0x9919, 1751 0x9990, 1752 0x9991, 1753 0x9992, 1754 0x9993, 1755 0x9994, 1756 0x9995, 1757 0x9996, 1758 0x9997, 1759 0x9998, 1760 0x9999, 1761 0x999A, 1762 0x999B, 1763 0x999C, 1764 0x999D, 1765 0x99A0, 1766 0x99A2, 1767 0x99A4, 1768 /* radeon secondary ids */ 1769 0x3171, 1770 0x3e70, 1771 0x4164, 1772 0x4165, 1773 0x4166, 1774 0x4168, 1775 0x4170, 1776 0x4171, 1777 0x4172, 1778 0x4173, 1779 0x496e, 1780 0x4a69, 1781 0x4a6a, 1782 0x4a6b, 1783 0x4a70, 1784 0x4a74, 1785 0x4b69, 1786 0x4b6b, 1787 0x4b6c, 1788 0x4c6e, 1789 0x4e64, 1790 0x4e65, 1791 0x4e66, 1792 0x4e67, 1793 0x4e68, 1794 0x4e69, 1795 0x4e6a, 1796 0x4e71, 1797 0x4f73, 1798 0x5569, 1799 0x556b, 1800 0x556d, 1801 0x556f, 1802 0x5571, 1803 0x5854, 1804 0x5874, 1805 0x5940, 1806 0x5941, 1807 0x5b70, 1808 0x5b72, 1809 0x5b73, 1810 0x5b74, 1811 0x5b75, 1812 0x5d44, 1813 0x5d45, 1814 0x5d6d, 1815 0x5d6f, 1816 0x5d72, 1817 0x5d77, 1818 0x5e6b, 1819 0x5e6d, 1820 0x7120, 1821 0x7124, 1822 0x7129, 1823 0x712e, 1824 0x712f, 1825 0x7162, 1826 0x7163, 1827 0x7166, 1828 0x7167, 1829 0x7172, 1830 0x7173, 1831 0x71a0, 1832 0x71a1, 1833 0x71a3, 1834 0x71a7, 1835 0x71bb, 1836 0x71e0, 1837 0x71e1, 1838 0x71e2, 1839 0x71e6, 1840 0x71e7, 1841 0x71f2, 1842 0x7269, 1843 0x726b, 1844 0x726e, 1845 0x72a0, 1846 0x72a8, 1847 0x72b1, 1848 0x72b3, 1849 0x793f, 1850 }; 1851 1852 static const struct pci_device_id pciidlist[] = { 1853 { PCI_DEVICE(0x1002, 0x6780), .driver_data = CHIP_TAHITI }, 1854 { PCI_DEVICE(0x1002, 0x6784), .driver_data = CHIP_TAHITI }, 1855 { PCI_DEVICE(0x1002, 0x6788), .driver_data = CHIP_TAHITI }, 1856 { PCI_DEVICE(0x1002, 0x678A), .driver_data = CHIP_TAHITI }, 1857 { PCI_DEVICE(0x1002, 0x6790), .driver_data = CHIP_TAHITI }, 1858 { PCI_DEVICE(0x1002, 0x6791), .driver_data = CHIP_TAHITI }, 1859 { PCI_DEVICE(0x1002, 0x6792), .driver_data = CHIP_TAHITI }, 1860 { PCI_DEVICE(0x1002, 0x6798), .driver_data = CHIP_TAHITI }, 1861 { PCI_DEVICE(0x1002, 0x6799), .driver_data = CHIP_TAHITI }, 1862 { PCI_DEVICE(0x1002, 0x679A), .driver_data = CHIP_TAHITI }, 1863 { PCI_DEVICE(0x1002, 0x679B), .driver_data = CHIP_TAHITI }, 1864 { PCI_DEVICE(0x1002, 0x679E), .driver_data = CHIP_TAHITI }, 1865 { PCI_DEVICE(0x1002, 0x679F), .driver_data = CHIP_TAHITI }, 1866 { PCI_DEVICE(0x1002, 0x6800), .driver_data = CHIP_PITCAIRN|AMD_IS_MOBILITY }, 1867 { PCI_DEVICE(0x1002, 0x6801), .driver_data = CHIP_PITCAIRN|AMD_IS_MOBILITY }, 1868 { PCI_DEVICE(0x1002, 0x6802), .driver_data = CHIP_PITCAIRN|AMD_IS_MOBILITY }, 1869 { PCI_DEVICE(0x1002, 0x6806), .driver_data = CHIP_PITCAIRN }, 1870 { PCI_DEVICE(0x1002, 0x6808), .driver_data = CHIP_PITCAIRN }, 1871 { PCI_DEVICE(0x1002, 0x6809), .driver_data = CHIP_PITCAIRN }, 1872 { PCI_DEVICE(0x1002, 0x6810), .driver_data = CHIP_PITCAIRN }, 1873 { PCI_DEVICE(0x1002, 0x6811), .driver_data = CHIP_PITCAIRN }, 1874 { PCI_DEVICE(0x1002, 0x6816), .driver_data = CHIP_PITCAIRN }, 1875 { PCI_DEVICE(0x1002, 0x6817), .driver_data = CHIP_PITCAIRN }, 1876 { PCI_DEVICE(0x1002, 0x6818), .driver_data = CHIP_PITCAIRN }, 1877 { PCI_DEVICE(0x1002, 0x6819), .driver_data = CHIP_PITCAIRN }, 1878 { PCI_DEVICE(0x1002, 0x6600), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1879 { PCI_DEVICE(0x1002, 0x6601), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1880 { PCI_DEVICE(0x1002, 0x6602), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1881 { PCI_DEVICE(0x1002, 0x6603), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1882 { PCI_DEVICE(0x1002, 0x6604), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1883 { PCI_DEVICE(0x1002, 0x6605), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1884 { PCI_DEVICE(0x1002, 0x6606), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1885 { PCI_DEVICE(0x1002, 0x6607), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1886 { PCI_DEVICE(0x1002, 0x6608), .driver_data = CHIP_OLAND }, 1887 { PCI_DEVICE(0x1002, 0x6610), .driver_data = CHIP_OLAND }, 1888 { PCI_DEVICE(0x1002, 0x6611), .driver_data = CHIP_OLAND }, 1889 { PCI_DEVICE(0x1002, 0x6613), .driver_data = CHIP_OLAND }, 1890 { PCI_DEVICE(0x1002, 0x6617), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1891 { PCI_DEVICE(0x1002, 0x6620), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1892 { PCI_DEVICE(0x1002, 0x6621), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1893 { PCI_DEVICE(0x1002, 0x6623), .driver_data = CHIP_OLAND|AMD_IS_MOBILITY }, 1894 { PCI_DEVICE(0x1002, 0x6631), .driver_data = CHIP_OLAND }, 1895 { PCI_DEVICE(0x1002, 0x6820), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1896 { PCI_DEVICE(0x1002, 0x6821), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1897 { PCI_DEVICE(0x1002, 0x6822), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1898 { PCI_DEVICE(0x1002, 0x6823), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1899 { PCI_DEVICE(0x1002, 0x6824), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1900 { PCI_DEVICE(0x1002, 0x6825), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1901 { PCI_DEVICE(0x1002, 0x6826), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1902 { PCI_DEVICE(0x1002, 0x6827), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1903 { PCI_DEVICE(0x1002, 0x6828), .driver_data = CHIP_VERDE }, 1904 { PCI_DEVICE(0x1002, 0x6829), .driver_data = CHIP_VERDE }, 1905 { PCI_DEVICE(0x1002, 0x682A), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1906 { PCI_DEVICE(0x1002, 0x682B), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1907 { PCI_DEVICE(0x1002, 0x682C), .driver_data = CHIP_VERDE }, 1908 { PCI_DEVICE(0x1002, 0x682D), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1909 { PCI_DEVICE(0x1002, 0x682F), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1910 { PCI_DEVICE(0x1002, 0x6830), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1911 { PCI_DEVICE(0x1002, 0x6831), .driver_data = CHIP_VERDE|AMD_IS_MOBILITY }, 1912 { PCI_DEVICE(0x1002, 0x6835), .driver_data = CHIP_VERDE }, 1913 { PCI_DEVICE(0x1002, 0x6837), .driver_data = CHIP_VERDE }, 1914 { PCI_DEVICE(0x1002, 0x6838), .driver_data = CHIP_VERDE }, 1915 { PCI_DEVICE(0x1002, 0x6839), .driver_data = CHIP_VERDE }, 1916 { PCI_DEVICE(0x1002, 0x683B), .driver_data = CHIP_VERDE }, 1917 { PCI_DEVICE(0x1002, 0x683D), .driver_data = CHIP_VERDE }, 1918 { PCI_DEVICE(0x1002, 0x683F), .driver_data = CHIP_VERDE }, 1919 { PCI_DEVICE(0x1002, 0x6660), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY }, 1920 { PCI_DEVICE(0x1002, 0x6663), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY }, 1921 { PCI_DEVICE(0x1002, 0x6664), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY }, 1922 { PCI_DEVICE(0x1002, 0x6665), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY }, 1923 { PCI_DEVICE(0x1002, 0x6667), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY }, 1924 { PCI_DEVICE(0x1002, 0x666F), .driver_data = CHIP_HAINAN|AMD_IS_MOBILITY }, 1925 /* Kaveri */ 1926 { PCI_DEVICE(0x1002, 0x1304), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1927 { PCI_DEVICE(0x1002, 0x1305), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1928 { PCI_DEVICE(0x1002, 0x1306), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1929 { PCI_DEVICE(0x1002, 0x1307), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1930 { PCI_DEVICE(0x1002, 0x1309), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1931 { PCI_DEVICE(0x1002, 0x130A), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1932 { PCI_DEVICE(0x1002, 0x130B), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1933 { PCI_DEVICE(0x1002, 0x130C), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1934 { PCI_DEVICE(0x1002, 0x130D), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1935 { PCI_DEVICE(0x1002, 0x130E), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1936 { PCI_DEVICE(0x1002, 0x130F), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1937 { PCI_DEVICE(0x1002, 0x1310), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1938 { PCI_DEVICE(0x1002, 0x1311), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1939 { PCI_DEVICE(0x1002, 0x1312), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1940 { PCI_DEVICE(0x1002, 0x1313), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1941 { PCI_DEVICE(0x1002, 0x1315), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1942 { PCI_DEVICE(0x1002, 0x1316), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1943 { PCI_DEVICE(0x1002, 0x1317), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1944 { PCI_DEVICE(0x1002, 0x1318), .driver_data = CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU }, 1945 { PCI_DEVICE(0x1002, 0x131B), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1946 { PCI_DEVICE(0x1002, 0x131C), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1947 { PCI_DEVICE(0x1002, 0x131D), .driver_data = CHIP_KAVERI|AMD_IS_APU }, 1948 /* Bonaire */ 1949 { PCI_DEVICE(0x1002, 0x6640), .driver_data = CHIP_BONAIRE|AMD_IS_MOBILITY }, 1950 { PCI_DEVICE(0x1002, 0x6641), .driver_data = CHIP_BONAIRE|AMD_IS_MOBILITY }, 1951 { PCI_DEVICE(0x1002, 0x6646), .driver_data = CHIP_BONAIRE|AMD_IS_MOBILITY }, 1952 { PCI_DEVICE(0x1002, 0x6647), .driver_data = CHIP_BONAIRE|AMD_IS_MOBILITY }, 1953 { PCI_DEVICE(0x1002, 0x6649), .driver_data = CHIP_BONAIRE }, 1954 { PCI_DEVICE(0x1002, 0x664D), .driver_data = CHIP_BONAIRE }, 1955 { PCI_DEVICE(0x1002, 0x6650), .driver_data = CHIP_BONAIRE }, 1956 { PCI_DEVICE(0x1002, 0x6651), .driver_data = CHIP_BONAIRE }, 1957 { PCI_DEVICE(0x1002, 0x6658), .driver_data = CHIP_BONAIRE }, 1958 { PCI_DEVICE(0x1002, 0x665c), .driver_data = CHIP_BONAIRE }, 1959 { PCI_DEVICE(0x1002, 0x665d), .driver_data = CHIP_BONAIRE }, 1960 { PCI_DEVICE(0x1002, 0x665f), .driver_data = CHIP_BONAIRE }, 1961 /* Hawaii */ 1962 { PCI_DEVICE(0x1002, 0x67A0), .driver_data = CHIP_HAWAII }, 1963 { PCI_DEVICE(0x1002, 0x67A1), .driver_data = CHIP_HAWAII }, 1964 { PCI_DEVICE(0x1002, 0x67A2), .driver_data = CHIP_HAWAII }, 1965 { PCI_DEVICE(0x1002, 0x67A8), .driver_data = CHIP_HAWAII }, 1966 { PCI_DEVICE(0x1002, 0x67A9), .driver_data = CHIP_HAWAII }, 1967 { PCI_DEVICE(0x1002, 0x67AA), .driver_data = CHIP_HAWAII }, 1968 { PCI_DEVICE(0x1002, 0x67B0), .driver_data = CHIP_HAWAII }, 1969 { PCI_DEVICE(0x1002, 0x67B1), .driver_data = CHIP_HAWAII }, 1970 { PCI_DEVICE(0x1002, 0x67B8), .driver_data = CHIP_HAWAII }, 1971 { PCI_DEVICE(0x1002, 0x67B9), .driver_data = CHIP_HAWAII }, 1972 { PCI_DEVICE(0x1002, 0x67BA), .driver_data = CHIP_HAWAII }, 1973 { PCI_DEVICE(0x1002, 0x67BE), .driver_data = CHIP_HAWAII }, 1974 /* Kabini */ 1975 { PCI_DEVICE(0x1002, 0x9830), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU }, 1976 { PCI_DEVICE(0x1002, 0x9831), .driver_data = CHIP_KABINI|AMD_IS_APU }, 1977 { PCI_DEVICE(0x1002, 0x9832), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU }, 1978 { PCI_DEVICE(0x1002, 0x9833), .driver_data = CHIP_KABINI|AMD_IS_APU }, 1979 { PCI_DEVICE(0x1002, 0x9834), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU }, 1980 { PCI_DEVICE(0x1002, 0x9835), .driver_data = CHIP_KABINI|AMD_IS_APU }, 1981 { PCI_DEVICE(0x1002, 0x9836), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU }, 1982 { PCI_DEVICE(0x1002, 0x9837), .driver_data = CHIP_KABINI|AMD_IS_APU }, 1983 { PCI_DEVICE(0x1002, 0x9838), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU }, 1984 { PCI_DEVICE(0x1002, 0x9839), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU }, 1985 { PCI_DEVICE(0x1002, 0x983a), .driver_data = CHIP_KABINI|AMD_IS_APU }, 1986 { PCI_DEVICE(0x1002, 0x983b), .driver_data = CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU }, 1987 { PCI_DEVICE(0x1002, 0x983c), .driver_data = CHIP_KABINI|AMD_IS_APU }, 1988 { PCI_DEVICE(0x1002, 0x983d), .driver_data = CHIP_KABINI|AMD_IS_APU }, 1989 { PCI_DEVICE(0x1002, 0x983e), .driver_data = CHIP_KABINI|AMD_IS_APU }, 1990 { PCI_DEVICE(0x1002, 0x983f), .driver_data = CHIP_KABINI|AMD_IS_APU }, 1991 /* mullins */ 1992 { PCI_DEVICE(0x1002, 0x9850), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1993 { PCI_DEVICE(0x1002, 0x9851), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1994 { PCI_DEVICE(0x1002, 0x9852), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1995 { PCI_DEVICE(0x1002, 0x9853), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1996 { PCI_DEVICE(0x1002, 0x9854), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1997 { PCI_DEVICE(0x1002, 0x9855), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1998 { PCI_DEVICE(0x1002, 0x9856), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 1999 { PCI_DEVICE(0x1002, 0x9857), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2000 { PCI_DEVICE(0x1002, 0x9858), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2001 { PCI_DEVICE(0x1002, 0x9859), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2002 { PCI_DEVICE(0x1002, 0x985A), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2003 { PCI_DEVICE(0x1002, 0x985B), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2004 { PCI_DEVICE(0x1002, 0x985C), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2005 { PCI_DEVICE(0x1002, 0x985D), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2006 { PCI_DEVICE(0x1002, 0x985E), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2007 { PCI_DEVICE(0x1002, 0x985F), .driver_data = CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU }, 2008 /* topaz */ 2009 { PCI_DEVICE(0x1002, 0x6900), .driver_data = CHIP_TOPAZ }, 2010 { PCI_DEVICE(0x1002, 0x6901), .driver_data = CHIP_TOPAZ }, 2011 { PCI_DEVICE(0x1002, 0x6902), .driver_data = CHIP_TOPAZ }, 2012 { PCI_DEVICE(0x1002, 0x6903), .driver_data = CHIP_TOPAZ }, 2013 { PCI_DEVICE(0x1002, 0x6907), .driver_data = CHIP_TOPAZ }, 2014 /* tonga */ 2015 { PCI_DEVICE(0x1002, 0x6920), .driver_data = CHIP_TONGA }, 2016 { PCI_DEVICE(0x1002, 0x6921), .driver_data = CHIP_TONGA }, 2017 { PCI_DEVICE(0x1002, 0x6928), .driver_data = CHIP_TONGA }, 2018 { PCI_DEVICE(0x1002, 0x6929), .driver_data = CHIP_TONGA }, 2019 { PCI_DEVICE(0x1002, 0x692B), .driver_data = CHIP_TONGA }, 2020 { PCI_DEVICE(0x1002, 0x692F), .driver_data = CHIP_TONGA }, 2021 { PCI_DEVICE(0x1002, 0x6930), .driver_data = CHIP_TONGA }, 2022 { PCI_DEVICE(0x1002, 0x6938), .driver_data = CHIP_TONGA }, 2023 { PCI_DEVICE(0x1002, 0x6939), .driver_data = CHIP_TONGA }, 2024 { PCI_DEVICE(0x1002, 0x693B), .driver_data = CHIP_TONGA }, 2025 /* fiji */ 2026 { PCI_DEVICE(0x1002, 0x7300), .driver_data = CHIP_FIJI }, 2027 { PCI_DEVICE(0x1002, 0x730F), .driver_data = CHIP_FIJI }, 2028 /* carrizo */ 2029 { PCI_DEVICE(0x1002, 0x9870), .driver_data = CHIP_CARRIZO|AMD_IS_APU }, 2030 { PCI_DEVICE(0x1002, 0x9874), .driver_data = CHIP_CARRIZO|AMD_IS_APU }, 2031 { PCI_DEVICE(0x1002, 0x9875), .driver_data = CHIP_CARRIZO|AMD_IS_APU }, 2032 { PCI_DEVICE(0x1002, 0x9876), .driver_data = CHIP_CARRIZO|AMD_IS_APU }, 2033 { PCI_DEVICE(0x1002, 0x9877), .driver_data = CHIP_CARRIZO|AMD_IS_APU }, 2034 /* stoney */ 2035 { PCI_DEVICE(0x1002, 0x98E4), .driver_data = CHIP_STONEY|AMD_IS_APU }, 2036 /* Polaris11 */ 2037 { PCI_DEVICE(0x1002, 0x67E0), .driver_data = CHIP_POLARIS11 }, 2038 { PCI_DEVICE(0x1002, 0x67E3), .driver_data = CHIP_POLARIS11 }, 2039 { PCI_DEVICE(0x1002, 0x67E8), .driver_data = CHIP_POLARIS11 }, 2040 { PCI_DEVICE(0x1002, 0x67EB), .driver_data = CHIP_POLARIS11 }, 2041 { PCI_DEVICE(0x1002, 0x67EF), .driver_data = CHIP_POLARIS11 }, 2042 { PCI_DEVICE(0x1002, 0x67FF), .driver_data = CHIP_POLARIS11 }, 2043 { PCI_DEVICE(0x1002, 0x67E1), .driver_data = CHIP_POLARIS11 }, 2044 { PCI_DEVICE(0x1002, 0x67E7), .driver_data = CHIP_POLARIS11 }, 2045 { PCI_DEVICE(0x1002, 0x67E9), .driver_data = CHIP_POLARIS11 }, 2046 /* Polaris10 */ 2047 { PCI_DEVICE(0x1002, 0x67C0), .driver_data = CHIP_POLARIS10 }, 2048 { PCI_DEVICE(0x1002, 0x67C1), .driver_data = CHIP_POLARIS10 }, 2049 { PCI_DEVICE(0x1002, 0x67C2), .driver_data = CHIP_POLARIS10 }, 2050 { PCI_DEVICE(0x1002, 0x67C4), .driver_data = CHIP_POLARIS10 }, 2051 { PCI_DEVICE(0x1002, 0x67C7), .driver_data = CHIP_POLARIS10 }, 2052 { PCI_DEVICE(0x1002, 0x67D0), .driver_data = CHIP_POLARIS10 }, 2053 { PCI_DEVICE(0x1002, 0x67D4), .driver_data = CHIP_POLARIS10 }, 2054 { PCI_DEVICE(0x1002, 0x67DF), .driver_data = CHIP_POLARIS10 }, 2055 { PCI_DEVICE(0x1002, 0x67C8), .driver_data = CHIP_POLARIS10 }, 2056 { PCI_DEVICE(0x1002, 0x67C9), .driver_data = CHIP_POLARIS10 }, 2057 { PCI_DEVICE(0x1002, 0x67CA), .driver_data = CHIP_POLARIS10 }, 2058 { PCI_DEVICE(0x1002, 0x67CC), .driver_data = CHIP_POLARIS10 }, 2059 { PCI_DEVICE(0x1002, 0x67CF), .driver_data = CHIP_POLARIS10 }, 2060 { PCI_DEVICE(0x1002, 0x6FDF), .driver_data = CHIP_POLARIS10 }, 2061 /* Polaris12 */ 2062 { PCI_DEVICE(0x1002, 0x6980), .driver_data = CHIP_POLARIS12 }, 2063 { PCI_DEVICE(0x1002, 0x6981), .driver_data = CHIP_POLARIS12 }, 2064 { PCI_DEVICE(0x1002, 0x6985), .driver_data = CHIP_POLARIS12 }, 2065 { PCI_DEVICE(0x1002, 0x6986), .driver_data = CHIP_POLARIS12 }, 2066 { PCI_DEVICE(0x1002, 0x6987), .driver_data = CHIP_POLARIS12 }, 2067 { PCI_DEVICE(0x1002, 0x698F), .driver_data = CHIP_POLARIS12 }, 2068 { PCI_DEVICE(0x1002, 0x6995), .driver_data = CHIP_POLARIS12 }, 2069 { PCI_DEVICE(0x1002, 0x6997), .driver_data = CHIP_POLARIS12 }, 2070 { PCI_DEVICE(0x1002, 0x699F), .driver_data = CHIP_POLARIS12 }, 2071 /* VEGAM */ 2072 { PCI_DEVICE(0x1002, 0x694C), .driver_data = CHIP_VEGAM }, 2073 { PCI_DEVICE(0x1002, 0x694E), .driver_data = CHIP_VEGAM }, 2074 { PCI_DEVICE(0x1002, 0x694F), .driver_data = CHIP_VEGAM }, 2075 /* Vega 10 */ 2076 { PCI_DEVICE(0x1002, 0x6860), .driver_data = CHIP_VEGA10 }, 2077 { PCI_DEVICE(0x1002, 0x6861), .driver_data = CHIP_VEGA10 }, 2078 { PCI_DEVICE(0x1002, 0x6862), .driver_data = CHIP_VEGA10 }, 2079 { PCI_DEVICE(0x1002, 0x6863), .driver_data = CHIP_VEGA10 }, 2080 { PCI_DEVICE(0x1002, 0x6864), .driver_data = CHIP_VEGA10 }, 2081 { PCI_DEVICE(0x1002, 0x6867), .driver_data = CHIP_VEGA10 }, 2082 { PCI_DEVICE(0x1002, 0x6868), .driver_data = CHIP_VEGA10 }, 2083 { PCI_DEVICE(0x1002, 0x6869), .driver_data = CHIP_VEGA10 }, 2084 { PCI_DEVICE(0x1002, 0x686a), .driver_data = CHIP_VEGA10 }, 2085 { PCI_DEVICE(0x1002, 0x686b), .driver_data = CHIP_VEGA10 }, 2086 { PCI_DEVICE(0x1002, 0x686c), .driver_data = CHIP_VEGA10 }, 2087 { PCI_DEVICE(0x1002, 0x686d), .driver_data = CHIP_VEGA10 }, 2088 { PCI_DEVICE(0x1002, 0x686e), .driver_data = CHIP_VEGA10 }, 2089 { PCI_DEVICE(0x1002, 0x686f), .driver_data = CHIP_VEGA10 }, 2090 { PCI_DEVICE(0x1002, 0x687f), .driver_data = CHIP_VEGA10 }, 2091 /* Vega 12 */ 2092 { PCI_DEVICE(0x1002, 0x69A0), .driver_data = CHIP_VEGA12 }, 2093 { PCI_DEVICE(0x1002, 0x69A1), .driver_data = CHIP_VEGA12 }, 2094 { PCI_DEVICE(0x1002, 0x69A2), .driver_data = CHIP_VEGA12 }, 2095 { PCI_DEVICE(0x1002, 0x69A3), .driver_data = CHIP_VEGA12 }, 2096 { PCI_DEVICE(0x1002, 0x69AF), .driver_data = CHIP_VEGA12 }, 2097 /* Vega 20 */ 2098 { PCI_DEVICE(0x1002, 0x66A0), .driver_data = CHIP_VEGA20 }, 2099 { PCI_DEVICE(0x1002, 0x66A1), .driver_data = CHIP_VEGA20 }, 2100 { PCI_DEVICE(0x1002, 0x66A2), .driver_data = CHIP_VEGA20 }, 2101 { PCI_DEVICE(0x1002, 0x66A3), .driver_data = CHIP_VEGA20 }, 2102 { PCI_DEVICE(0x1002, 0x66A4), .driver_data = CHIP_VEGA20 }, 2103 { PCI_DEVICE(0x1002, 0x66A7), .driver_data = CHIP_VEGA20 }, 2104 { PCI_DEVICE(0x1002, 0x66AF), .driver_data = CHIP_VEGA20 }, 2105 /* Raven */ 2106 { PCI_DEVICE(0x1002, 0x15dd), .driver_data = CHIP_RAVEN|AMD_IS_APU }, 2107 { PCI_DEVICE(0x1002, 0x15d8), .driver_data = CHIP_RAVEN|AMD_IS_APU }, 2108 /* Arcturus */ 2109 { PCI_DEVICE(0x1002, 0x738C), .driver_data = CHIP_ARCTURUS }, 2110 { PCI_DEVICE(0x1002, 0x7388), .driver_data = CHIP_ARCTURUS }, 2111 { PCI_DEVICE(0x1002, 0x738E), .driver_data = CHIP_ARCTURUS }, 2112 { PCI_DEVICE(0x1002, 0x7390), .driver_data = CHIP_ARCTURUS }, 2113 /* Navi10 */ 2114 { PCI_DEVICE(0x1002, 0x7310), .driver_data = CHIP_NAVI10 }, 2115 { PCI_DEVICE(0x1002, 0x7312), .driver_data = CHIP_NAVI10 }, 2116 { PCI_DEVICE(0x1002, 0x7318), .driver_data = CHIP_NAVI10 }, 2117 { PCI_DEVICE(0x1002, 0x7319), .driver_data = CHIP_NAVI10 }, 2118 { PCI_DEVICE(0x1002, 0x731A), .driver_data = CHIP_NAVI10 }, 2119 { PCI_DEVICE(0x1002, 0x731B), .driver_data = CHIP_NAVI10 }, 2120 { PCI_DEVICE(0x1002, 0x731E), .driver_data = CHIP_NAVI10 }, 2121 { PCI_DEVICE(0x1002, 0x731F), .driver_data = CHIP_NAVI10 }, 2122 /* Navi14 */ 2123 { PCI_DEVICE(0x1002, 0x7340), .driver_data = CHIP_NAVI14 }, 2124 { PCI_DEVICE(0x1002, 0x7341), .driver_data = CHIP_NAVI14 }, 2125 { PCI_DEVICE(0x1002, 0x7347), .driver_data = CHIP_NAVI14 }, 2126 { PCI_DEVICE(0x1002, 0x734F), .driver_data = CHIP_NAVI14 }, 2127 2128 /* Renoir */ 2129 { PCI_DEVICE(0x1002, 0x15E7), .driver_data = CHIP_RENOIR|AMD_IS_APU }, 2130 { PCI_DEVICE(0x1002, 0x1636), .driver_data = CHIP_RENOIR|AMD_IS_APU }, 2131 { PCI_DEVICE(0x1002, 0x1638), .driver_data = CHIP_RENOIR|AMD_IS_APU }, 2132 { PCI_DEVICE(0x1002, 0x164C), .driver_data = CHIP_RENOIR|AMD_IS_APU }, 2133 2134 /* Navi12 */ 2135 { PCI_DEVICE(0x1002, 0x7360), .driver_data = CHIP_NAVI12 }, 2136 { PCI_DEVICE(0x1002, 0x7362), .driver_data = CHIP_NAVI12 }, 2137 2138 /* Sienna_Cichlid */ 2139 { PCI_DEVICE(0x1002, 0x73A0), .driver_data = CHIP_SIENNA_CICHLID }, 2140 { PCI_DEVICE(0x1002, 0x73A1), .driver_data = CHIP_SIENNA_CICHLID }, 2141 { PCI_DEVICE(0x1002, 0x73A2), .driver_data = CHIP_SIENNA_CICHLID }, 2142 { PCI_DEVICE(0x1002, 0x73A3), .driver_data = CHIP_SIENNA_CICHLID }, 2143 { PCI_DEVICE(0x1002, 0x73A5), .driver_data = CHIP_SIENNA_CICHLID }, 2144 { PCI_DEVICE(0x1002, 0x73A8), .driver_data = CHIP_SIENNA_CICHLID }, 2145 { PCI_DEVICE(0x1002, 0x73A9), .driver_data = CHIP_SIENNA_CICHLID }, 2146 { PCI_DEVICE(0x1002, 0x73AB), .driver_data = CHIP_SIENNA_CICHLID }, 2147 { PCI_DEVICE(0x1002, 0x73AC), .driver_data = CHIP_SIENNA_CICHLID }, 2148 { PCI_DEVICE(0x1002, 0x73AD), .driver_data = CHIP_SIENNA_CICHLID }, 2149 { PCI_DEVICE(0x1002, 0x73AE), .driver_data = CHIP_SIENNA_CICHLID }, 2150 { PCI_DEVICE(0x1002, 0x73AF), .driver_data = CHIP_SIENNA_CICHLID }, 2151 { PCI_DEVICE(0x1002, 0x73BF), .driver_data = CHIP_SIENNA_CICHLID }, 2152 2153 /* Yellow Carp */ 2154 { PCI_DEVICE(0x1002, 0x164D), .driver_data = CHIP_YELLOW_CARP|AMD_IS_APU }, 2155 { PCI_DEVICE(0x1002, 0x1681), .driver_data = CHIP_YELLOW_CARP|AMD_IS_APU }, 2156 2157 /* Navy_Flounder */ 2158 { PCI_DEVICE(0x1002, 0x73C0), .driver_data = CHIP_NAVY_FLOUNDER }, 2159 { PCI_DEVICE(0x1002, 0x73C1), .driver_data = CHIP_NAVY_FLOUNDER }, 2160 { PCI_DEVICE(0x1002, 0x73C3), .driver_data = CHIP_NAVY_FLOUNDER }, 2161 { PCI_DEVICE(0x1002, 0x73DA), .driver_data = CHIP_NAVY_FLOUNDER }, 2162 { PCI_DEVICE(0x1002, 0x73DB), .driver_data = CHIP_NAVY_FLOUNDER }, 2163 { PCI_DEVICE(0x1002, 0x73DC), .driver_data = CHIP_NAVY_FLOUNDER }, 2164 { PCI_DEVICE(0x1002, 0x73DD), .driver_data = CHIP_NAVY_FLOUNDER }, 2165 { PCI_DEVICE(0x1002, 0x73DE), .driver_data = CHIP_NAVY_FLOUNDER }, 2166 { PCI_DEVICE(0x1002, 0x73DF), .driver_data = CHIP_NAVY_FLOUNDER }, 2167 2168 /* DIMGREY_CAVEFISH */ 2169 { PCI_DEVICE(0x1002, 0x73E0), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2170 { PCI_DEVICE(0x1002, 0x73E1), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2171 { PCI_DEVICE(0x1002, 0x73E2), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2172 { PCI_DEVICE(0x1002, 0x73E3), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2173 { PCI_DEVICE(0x1002, 0x73E8), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2174 { PCI_DEVICE(0x1002, 0x73E9), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2175 { PCI_DEVICE(0x1002, 0x73EA), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2176 { PCI_DEVICE(0x1002, 0x73EB), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2177 { PCI_DEVICE(0x1002, 0x73EC), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2178 { PCI_DEVICE(0x1002, 0x73ED), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2179 { PCI_DEVICE(0x1002, 0x73EF), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2180 { PCI_DEVICE(0x1002, 0x73FF), .driver_data = CHIP_DIMGREY_CAVEFISH }, 2181 2182 /* Aldebaran */ 2183 { PCI_DEVICE(0x1002, 0x7408), .driver_data = CHIP_ALDEBARAN }, 2184 { PCI_DEVICE(0x1002, 0x740C), .driver_data = CHIP_ALDEBARAN }, 2185 { PCI_DEVICE(0x1002, 0x740F), .driver_data = CHIP_ALDEBARAN }, 2186 { PCI_DEVICE(0x1002, 0x7410), .driver_data = CHIP_ALDEBARAN }, 2187 2188 /* CYAN_SKILLFISH */ 2189 { PCI_DEVICE(0x1002, 0x13DB), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU }, 2190 { PCI_DEVICE(0x1002, 0x13F9), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU }, 2191 { PCI_DEVICE(0x1002, 0x13FA), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU }, 2192 { PCI_DEVICE(0x1002, 0x13FB), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU }, 2193 { PCI_DEVICE(0x1002, 0x13FC), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU }, 2194 { PCI_DEVICE(0x1002, 0x13FE), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU }, 2195 { PCI_DEVICE(0x1002, 0x143F), .driver_data = CHIP_CYAN_SKILLFISH|AMD_IS_APU }, 2196 2197 /* BEIGE_GOBY */ 2198 { PCI_DEVICE(0x1002, 0x7420), .driver_data = CHIP_BEIGE_GOBY }, 2199 { PCI_DEVICE(0x1002, 0x7421), .driver_data = CHIP_BEIGE_GOBY }, 2200 { PCI_DEVICE(0x1002, 0x7422), .driver_data = CHIP_BEIGE_GOBY }, 2201 { PCI_DEVICE(0x1002, 0x7423), .driver_data = CHIP_BEIGE_GOBY }, 2202 { PCI_DEVICE(0x1002, 0x7424), .driver_data = CHIP_BEIGE_GOBY }, 2203 { PCI_DEVICE(0x1002, 0x743F), .driver_data = CHIP_BEIGE_GOBY }, 2204 2205 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2206 .class = PCI_CLASS_DISPLAY_VGA << 8, 2207 .class_mask = 0xffffff, 2208 .driver_data = CHIP_IP_DISCOVERY }, 2209 2210 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2211 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2212 .class_mask = 0xffffff, 2213 .driver_data = CHIP_IP_DISCOVERY }, 2214 2215 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2216 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2217 .class_mask = 0xffffff, 2218 .driver_data = CHIP_IP_DISCOVERY }, 2219 2220 { } 2221 }; 2222 2223 MODULE_DEVICE_TABLE(pci, pciidlist); 2224 2225 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2226 /* differentiate between P10 and P11 asics with the same DID */ 2227 {0x67FF, 0xE3, CHIP_POLARIS10}, 2228 {0x67FF, 0xE7, CHIP_POLARIS10}, 2229 {0x67FF, 0xF3, CHIP_POLARIS10}, 2230 {0x67FF, 0xF7, CHIP_POLARIS10}, 2231 }; 2232 2233 static const struct drm_driver amdgpu_kms_driver; 2234 2235 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2236 { 2237 struct pci_dev *p = NULL; 2238 int i; 2239 2240 /* 0 - GPU 2241 * 1 - audio 2242 * 2 - USB 2243 * 3 - UCSI 2244 */ 2245 for (i = 1; i < 4; i++) { 2246 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2247 adev->pdev->bus->number, i); 2248 if (p) { 2249 pm_runtime_get_sync(&p->dev); 2250 pm_runtime_put_autosuspend(&p->dev); 2251 pci_dev_put(p); 2252 } 2253 } 2254 } 2255 2256 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2257 { 2258 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2259 pr_info("debug: VM handling debug enabled\n"); 2260 adev->debug_vm = true; 2261 } 2262 2263 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2264 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2265 adev->debug_largebar = true; 2266 } 2267 2268 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2269 pr_info("debug: soft recovery disabled\n"); 2270 adev->debug_disable_soft_recovery = true; 2271 } 2272 2273 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2274 pr_info("debug: place fw in vram for frontdoor loading\n"); 2275 adev->debug_use_vram_fw_buf = true; 2276 } 2277 2278 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) { 2279 pr_info("debug: enable experimental reset features\n"); 2280 adev->debug_exp_resets = true; 2281 } 2282 2283 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_RING_RESET) { 2284 pr_info("debug: ring reset disabled\n"); 2285 adev->debug_disable_gpu_ring_reset = true; 2286 } 2287 if (amdgpu_debug_mask & AMDGPU_DEBUG_SMU_POOL) { 2288 pr_info("debug: use vram for smu pool\n"); 2289 adev->pm.smu_debug_mask |= SMU_DEBUG_POOL_USE_VRAM; 2290 } 2291 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM_USERPTR) { 2292 pr_info("debug: VM mode debug for userptr is enabled\n"); 2293 adev->debug_vm_userptr = true; 2294 } 2295 2296 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_RAS_CE_LOG) { 2297 pr_info("debug: disable kernel logs of correctable errors\n"); 2298 adev->debug_disable_ce_logs = true; 2299 } 2300 2301 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_CE_CS) { 2302 pr_info("debug: allowing command submission to CE engine\n"); 2303 adev->debug_enable_ce_cs = true; 2304 } 2305 2306 if (amdgpu_debug_mask & AMDGPU_DEBUG_HIBERNATION_THAW_RESUME_GPU) { 2307 pr_info("debug: resume gpu in thaw() of hibernation\n"); 2308 adev->debug_hibernation_thaw_resume_gpu = true; 2309 } 2310 2311 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_IP_BLOCK_SOFT_RESET) { 2312 pr_info("debug: IP block soft reset disabled\n"); 2313 adev->debug_disable_ip_block_soft_reset = true; 2314 } 2315 } 2316 2317 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2318 { 2319 int i; 2320 2321 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2322 if (pdev->device == asic_type_quirks[i].device && 2323 pdev->revision == asic_type_quirks[i].revision) { 2324 flags &= ~AMD_ASIC_MASK; 2325 flags |= asic_type_quirks[i].type; 2326 break; 2327 } 2328 } 2329 2330 return flags; 2331 } 2332 2333 static bool amdgpu_support_enabled(struct device *dev, 2334 const enum amd_asic_type family) 2335 { 2336 const char *gen; 2337 const char *param; 2338 int module_param = -1; 2339 bool radeon_support_built = IS_ENABLED(CONFIG_DRM_RADEON); 2340 bool amdgpu_support_built = false; 2341 bool support_by_default = false; 2342 2343 switch (family) { 2344 case CHIP_TAHITI: 2345 case CHIP_PITCAIRN: 2346 case CHIP_VERDE: 2347 case CHIP_OLAND: 2348 case CHIP_HAINAN: 2349 gen = "SI"; 2350 param = "si_support"; 2351 module_param = amdgpu_si_support; 2352 amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_SI); 2353 support_by_default = true; 2354 break; 2355 2356 case CHIP_BONAIRE: 2357 case CHIP_HAWAII: 2358 case CHIP_KAVERI: 2359 case CHIP_KABINI: 2360 case CHIP_MULLINS: 2361 gen = "CIK"; 2362 param = "cik_support"; 2363 module_param = amdgpu_cik_support; 2364 amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_CIK); 2365 support_by_default = true; 2366 break; 2367 2368 default: 2369 /* All other chips are supported by amdgpu only */ 2370 return true; 2371 } 2372 2373 if (!amdgpu_support_built) { 2374 dev_info(dev, "amdgpu built without %s support\n", gen); 2375 return false; 2376 } 2377 2378 if ((module_param == -1 && (support_by_default || !radeon_support_built)) || 2379 module_param == 1) { 2380 if (radeon_support_built) 2381 dev_info(dev, "%s support provided by amdgpu.\n" 2382 "Use radeon.%s=1 amdgpu.%s=0 to override.\n", 2383 gen, param, param); 2384 2385 return true; 2386 } 2387 2388 if (radeon_support_built) 2389 dev_info(dev, "%s support provided by radeon.\n" 2390 "Use radeon.%s=0 amdgpu.%s=1 to override.\n", 2391 gen, param, param); 2392 else if (module_param == 0) 2393 dev_info(dev, "%s support disabled by module param\n", gen); 2394 2395 return false; 2396 } 2397 2398 static int amdgpu_pci_probe(struct pci_dev *pdev, 2399 const struct pci_device_id *ent) 2400 { 2401 struct drm_device *ddev; 2402 struct amdgpu_device *adev; 2403 unsigned long flags = ent->driver_data; 2404 int ret, retry = 0, i; 2405 bool supports_atomic = false; 2406 2407 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA || 2408 (pdev->class >> 8) == PCI_CLASS_DISPLAY_OTHER) { 2409 if (drm_firmware_drivers_only() && amdgpu_modeset == -1) 2410 return -EINVAL; 2411 } 2412 2413 /* skip devices which are owned by radeon */ 2414 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2415 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2416 return -ENODEV; 2417 } 2418 2419 if (amdgpu_virtual_display || 2420 amdgpu_device_asic_has_dc_support(pdev, flags & AMD_ASIC_MASK)) 2421 supports_atomic = true; 2422 2423 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2424 dev_info(&pdev->dev, "This hardware requires experimental hardware support.\n" 2425 "See modparam exp_hw_support\n"); 2426 return -ENODEV; 2427 } 2428 2429 flags = amdgpu_fix_asic_type(pdev, flags); 2430 2431 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2432 * however, SME requires an indirect IOMMU mapping because the encryption 2433 * bit is beyond the DMA mask of the chip. 2434 */ 2435 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2436 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2437 dev_info(&pdev->dev, 2438 "SME is not compatible with RAVEN\n"); 2439 return -ENOTSUPP; 2440 } 2441 2442 if (!amdgpu_support_enabled(&pdev->dev, flags & AMD_ASIC_MASK)) 2443 return -ENODEV; 2444 2445 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2446 if (IS_ERR(adev)) 2447 return PTR_ERR(adev); 2448 2449 adev->dev = &pdev->dev; 2450 adev->pdev = pdev; 2451 ddev = adev_to_drm(adev); 2452 2453 if (!supports_atomic) 2454 ddev->driver_features &= ~DRIVER_ATOMIC; 2455 2456 ret = pci_enable_device(pdev); 2457 if (ret) 2458 return ret; 2459 2460 pci_set_drvdata(pdev, ddev); 2461 2462 amdgpu_init_debug_options(adev); 2463 2464 ret = amdgpu_driver_load_kms(adev, flags); 2465 if (ret) 2466 goto err_pci; 2467 2468 retry_init: 2469 ret = drm_dev_register(ddev, flags); 2470 if (ret == -EAGAIN && ++retry <= 3) { 2471 drm_info(adev_to_drm(adev), "retry init %d\n", retry); 2472 /* Don't request EX mode too frequently which is attacking */ 2473 msleep(5000); 2474 goto retry_init; 2475 } else if (ret) { 2476 goto err_pci; 2477 } 2478 2479 ret = amdgpu_xcp_dev_register(adev, ent); 2480 if (ret) 2481 goto err_pci; 2482 2483 ret = amdgpu_amdkfd_drm_client_create(adev); 2484 if (ret) 2485 goto err_pci; 2486 2487 /* 2488 * 1. don't init fbdev on hw without DCE 2489 * 2. don't init fbdev if there are no connectors 2490 */ 2491 if (adev->mode_info.mode_config_initialized && 2492 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2493 const struct drm_format_info *format; 2494 2495 /* select 8 bpp console on low vram cards */ 2496 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2497 format = drm_format_info(DRM_FORMAT_C8); 2498 else 2499 format = NULL; 2500 2501 drm_client_setup(adev_to_drm(adev), format); 2502 } 2503 2504 ret = amdgpu_debugfs_init(adev); 2505 if (ret) 2506 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2507 2508 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2509 /* only need to skip on ATPX */ 2510 if (amdgpu_device_supports_px(adev)) 2511 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2512 /* we want direct complete for BOCO */ 2513 if (amdgpu_device_supports_boco(adev)) 2514 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2515 DPM_FLAG_SMART_SUSPEND | 2516 DPM_FLAG_MAY_SKIP_RESUME); 2517 pm_runtime_use_autosuspend(ddev->dev); 2518 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2519 2520 pm_runtime_allow(ddev->dev); 2521 2522 pm_runtime_put_autosuspend(ddev->dev); 2523 2524 pci_wake_from_d3(pdev, TRUE); 2525 2526 /* 2527 * For runpm implemented via BACO, PMFW will handle the 2528 * timing for BACO in and out: 2529 * - put ASIC into BACO state only when both video and 2530 * audio functions are in D3 state. 2531 * - pull ASIC out of BACO state when either video or 2532 * audio function is in D0 state. 2533 * Also, at startup, PMFW assumes both functions are in 2534 * D0 state. 2535 * 2536 * So if snd driver was loaded prior to amdgpu driver 2537 * and audio function was put into D3 state, there will 2538 * be no PMFW-aware D-state transition(D0->D3) on runpm 2539 * suspend. Thus the BACO will be not correctly kicked in. 2540 * 2541 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2542 * into D0 state. Then there will be a PMFW-aware D-state 2543 * transition(D0->D3) on runpm suspend. 2544 */ 2545 if (amdgpu_device_supports_baco(adev) && 2546 !(adev->flags & AMD_IS_APU) && 2547 adev->asic_type >= CHIP_NAVI10) 2548 amdgpu_get_secondary_funcs(adev); 2549 } 2550 2551 return 0; 2552 2553 err_pci: 2554 pci_disable_device(pdev); 2555 return ret; 2556 } 2557 2558 static void 2559 amdgpu_pci_remove(struct pci_dev *pdev) 2560 { 2561 struct drm_device *dev = pci_get_drvdata(pdev); 2562 struct amdgpu_device *adev = drm_to_adev(dev); 2563 2564 amdgpu_ras_eeprom_check_and_recover(adev); 2565 amdgpu_xcp_dev_unplug(adev); 2566 amdgpu_gmc_prepare_nps_mode_change(adev); 2567 drm_dev_unplug(dev); 2568 2569 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2570 pm_runtime_get_sync(dev->dev); 2571 pm_runtime_forbid(dev->dev); 2572 pm_runtime_dont_use_autosuspend(dev->dev); 2573 } 2574 2575 amdgpu_driver_unload_kms(dev); 2576 2577 amdgpu_discovery_sysfs_early_fini(pdev); 2578 2579 /* 2580 * Flush any in flight DMA operations from device. 2581 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2582 * StatusTransactions Pending bit. 2583 */ 2584 pci_disable_device(pdev); 2585 pci_wait_for_pending_transaction(pdev); 2586 } 2587 2588 static void 2589 amdgpu_pci_shutdown(struct pci_dev *pdev) 2590 { 2591 struct drm_device *dev = pci_get_drvdata(pdev); 2592 struct amdgpu_device *adev = drm_to_adev(dev); 2593 2594 if (amdgpu_ras_intr_triggered()) 2595 return; 2596 2597 /* device maybe not resumed here, return immediately in this case */ 2598 if (adev->in_s4 && adev->in_suspend) 2599 return; 2600 2601 /* if we are running in a VM, make sure the device 2602 * torn down properly on reboot/shutdown. 2603 * unfortunately we can't detect certain 2604 * hypervisors so just do this all the time. 2605 */ 2606 if (!amdgpu_passthrough(adev)) 2607 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2608 amdgpu_device_prepare(dev); 2609 amdgpu_device_suspend(dev, true); 2610 adev->mp1_state = PP_MP1_STATE_NONE; 2611 } 2612 2613 static int amdgpu_pmops_prepare(struct device *dev) 2614 { 2615 struct drm_device *drm_dev = dev_get_drvdata(dev); 2616 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2617 2618 /* device maybe not resumed here, return immediately in this case */ 2619 if (adev->in_s4 && adev->in_suspend) 2620 return 0; 2621 2622 /* Return a positive number here so 2623 * DPM_FLAG_SMART_SUSPEND works properly 2624 */ 2625 if (amdgpu_device_supports_boco(adev) && pm_runtime_suspended(dev)) 2626 return 1; 2627 2628 /* if we will not support s3 or s2i for the device 2629 * then skip suspend 2630 */ 2631 if (!amdgpu_acpi_is_s0ix_active(adev) && 2632 !amdgpu_acpi_is_s3_active(adev)) 2633 return 1; 2634 2635 return amdgpu_device_prepare(drm_dev); 2636 } 2637 2638 static void amdgpu_pmops_complete(struct device *dev) 2639 { 2640 amdgpu_device_complete(dev_get_drvdata(dev)); 2641 } 2642 2643 static int amdgpu_pmops_suspend(struct device *dev) 2644 { 2645 struct drm_device *drm_dev = dev_get_drvdata(dev); 2646 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2647 2648 if (amdgpu_acpi_is_s0ix_active(adev)) 2649 adev->in_s0ix = true; 2650 else if (amdgpu_acpi_is_s3_active(adev)) 2651 adev->in_s3 = true; 2652 if (!adev->in_s0ix && !adev->in_s3) { 2653 #if IS_ENABLED(CONFIG_SUSPEND) 2654 /* don't allow going deep first time followed by s2idle the next time */ 2655 if (adev->last_suspend_state != PM_SUSPEND_ON && 2656 adev->last_suspend_state != pm_suspend_target_state) { 2657 drm_err_once(drm_dev, "Unsupported suspend state %d\n", 2658 pm_suspend_target_state); 2659 return -EINVAL; 2660 } 2661 #endif 2662 return 0; 2663 } 2664 2665 #if IS_ENABLED(CONFIG_SUSPEND) 2666 /* cache the state last used for suspend */ 2667 adev->last_suspend_state = pm_suspend_target_state; 2668 #endif 2669 2670 return amdgpu_device_suspend(drm_dev, true); 2671 } 2672 2673 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2674 { 2675 struct drm_device *drm_dev = dev_get_drvdata(dev); 2676 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2677 int r; 2678 2679 /* 2680 * A GPU parked by vga_switcheroo has no power and no PCIe link, so the 2681 * ASIC reset below would fail and abort the whole noirq suspend phase. 2682 * Bail out like amdgpu_device_prepare/suspend/resume() already do. 2683 */ 2684 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 2685 return 0; 2686 2687 if (amdgpu_acpi_should_gpu_reset(adev)) { 2688 amdgpu_device_lock_reset_domain(adev->reset_domain); 2689 r = amdgpu_asic_reset(adev); 2690 amdgpu_device_unlock_reset_domain(adev->reset_domain); 2691 return r; 2692 } 2693 2694 return 0; 2695 } 2696 2697 static int amdgpu_pmops_resume(struct device *dev) 2698 { 2699 struct drm_device *drm_dev = dev_get_drvdata(dev); 2700 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2701 int r; 2702 2703 if (!adev->in_s0ix && !adev->in_s3) 2704 return 0; 2705 2706 /* Avoids registers access if device is physically gone */ 2707 if (!pci_device_is_present(adev->pdev)) 2708 adev->no_hw_access = true; 2709 2710 r = amdgpu_device_resume(drm_dev, true); 2711 if (amdgpu_acpi_is_s0ix_active(adev)) 2712 adev->in_s0ix = false; 2713 else 2714 adev->in_s3 = false; 2715 return r; 2716 } 2717 2718 static int amdgpu_pmops_freeze(struct device *dev) 2719 { 2720 struct drm_device *drm_dev = dev_get_drvdata(dev); 2721 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2722 int r; 2723 2724 r = amdgpu_device_suspend(drm_dev, true); 2725 if (r) 2726 return r; 2727 2728 if (amdgpu_acpi_should_gpu_reset(adev)) { 2729 amdgpu_device_lock_reset_domain(adev->reset_domain); 2730 r = amdgpu_asic_reset(adev); 2731 amdgpu_device_unlock_reset_domain(adev->reset_domain); 2732 return r; 2733 } 2734 return 0; 2735 } 2736 2737 static int amdgpu_pmops_thaw(struct device *dev) 2738 { 2739 struct drm_device *drm_dev = dev_get_drvdata(dev); 2740 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2741 2742 /* do not resume device if it's normal hibernation */ 2743 if (!adev->debug_hibernation_thaw_resume_gpu && 2744 !pm_hibernate_is_recovering() && 2745 !pm_hibernation_mode_is_suspend()) 2746 return 0; 2747 2748 return amdgpu_device_resume(drm_dev, true); 2749 } 2750 2751 static int amdgpu_pmops_poweroff(struct device *dev) 2752 { 2753 struct drm_device *drm_dev = dev_get_drvdata(dev); 2754 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2755 2756 /* device maybe not resumed here, return immediately in this case */ 2757 if (adev->in_s4 && adev->in_suspend) 2758 return 0; 2759 2760 return amdgpu_device_suspend(drm_dev, true); 2761 } 2762 2763 static int amdgpu_pmops_restore(struct device *dev) 2764 { 2765 struct drm_device *drm_dev = dev_get_drvdata(dev); 2766 2767 return amdgpu_device_resume(drm_dev, true); 2768 } 2769 2770 static int amdgpu_runtime_idle_check_display(struct device *dev) 2771 { 2772 struct pci_dev *pdev = to_pci_dev(dev); 2773 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2774 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2775 2776 if (adev->mode_info.num_crtc) { 2777 struct drm_connector *list_connector; 2778 struct drm_connector_list_iter iter; 2779 int ret = 0; 2780 2781 if (amdgpu_runtime_pm != -2) { 2782 /* XXX: Return busy if any displays are connected to avoid 2783 * possible display wakeups after runtime resume due to 2784 * hotplug events in case any displays were connected while 2785 * the GPU was in suspend. Remove this once that is fixed. 2786 */ 2787 mutex_lock(&drm_dev->mode_config.mutex); 2788 drm_connector_list_iter_begin(drm_dev, &iter); 2789 drm_for_each_connector_iter(list_connector, &iter) { 2790 if (list_connector->status == connector_status_connected) { 2791 ret = -EBUSY; 2792 break; 2793 } 2794 } 2795 drm_connector_list_iter_end(&iter); 2796 mutex_unlock(&drm_dev->mode_config.mutex); 2797 2798 if (ret) 2799 return ret; 2800 } 2801 2802 if (adev->dc_enabled) { 2803 struct drm_crtc *crtc; 2804 2805 drm_for_each_crtc(crtc, drm_dev) { 2806 drm_modeset_lock(&crtc->mutex, NULL); 2807 if (crtc->state->active) 2808 ret = -EBUSY; 2809 drm_modeset_unlock(&crtc->mutex); 2810 if (ret < 0) 2811 break; 2812 } 2813 } else { 2814 mutex_lock(&drm_dev->mode_config.mutex); 2815 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2816 2817 drm_connector_list_iter_begin(drm_dev, &iter); 2818 drm_for_each_connector_iter(list_connector, &iter) { 2819 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2820 ret = -EBUSY; 2821 break; 2822 } 2823 } 2824 2825 drm_connector_list_iter_end(&iter); 2826 2827 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2828 mutex_unlock(&drm_dev->mode_config.mutex); 2829 } 2830 if (ret) 2831 return ret; 2832 } 2833 2834 return 0; 2835 } 2836 2837 static int amdgpu_runtime_idle_check_userq(struct device *dev) 2838 { 2839 struct pci_dev *pdev = to_pci_dev(dev); 2840 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2841 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2842 2843 return xa_empty(&adev->userq_doorbell_xa) ? 0 : -EBUSY; 2844 } 2845 2846 static int amdgpu_pmops_runtime_checks(struct device *dev) 2847 { 2848 struct drm_device *drm_dev = dev_get_drvdata(dev); 2849 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2850 int ret; 2851 2852 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2853 pm_runtime_forbid(dev); 2854 return -EBUSY; 2855 } 2856 2857 ret = amdgpu_runtime_idle_check_display(dev); 2858 if (ret) 2859 return ret; 2860 2861 return amdgpu_runtime_idle_check_userq(dev); 2862 } 2863 2864 static int amdgpu_pmops_runtime_idle(struct device *dev) 2865 { 2866 int ret; 2867 2868 ret = amdgpu_pmops_runtime_checks(dev); 2869 pm_runtime_autosuspend(dev); 2870 return ret; 2871 } 2872 2873 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2874 { 2875 struct pci_dev *pdev = to_pci_dev(dev); 2876 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2877 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2878 int ret, i; 2879 2880 ret = amdgpu_pmops_runtime_checks(dev); 2881 if (ret) 2882 return ret; 2883 2884 /* wait for all rings to drain before suspending */ 2885 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2886 struct amdgpu_ring *ring = adev->rings[i]; 2887 2888 if (ring && ring->sched.ready) { 2889 ret = amdgpu_fence_wait_empty(ring); 2890 if (ret) 2891 return -EBUSY; 2892 } 2893 } 2894 2895 adev->in_runpm = true; 2896 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2897 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2898 2899 /* 2900 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2901 * proper cleanups and put itself into a state ready for PNP. That 2902 * can address some random resuming failure observed on BOCO capable 2903 * platforms. 2904 * TODO: this may be also needed for PX capable platform. 2905 */ 2906 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2907 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2908 2909 ret = amdgpu_device_prepare(drm_dev); 2910 if (ret) 2911 return ret; 2912 ret = amdgpu_device_suspend(drm_dev, false); 2913 if (ret) { 2914 adev->in_runpm = false; 2915 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2916 adev->mp1_state = PP_MP1_STATE_NONE; 2917 return ret; 2918 } 2919 2920 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2921 adev->mp1_state = PP_MP1_STATE_NONE; 2922 2923 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2924 /* Only need to handle PCI state in the driver for ATPX 2925 * PCI core handles it for _PR3. 2926 */ 2927 amdgpu_device_cache_pci_state(pdev); 2928 pci_disable_device(pdev); 2929 pci_ignore_hotplug(pdev); 2930 pci_set_power_state(pdev, PCI_D3cold); 2931 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2932 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2933 /* nothing to do */ 2934 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2935 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2936 amdgpu_device_baco_enter(adev); 2937 } 2938 2939 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2940 2941 return 0; 2942 } 2943 2944 static void amdgpu_restore_umd_profile_pstate_after_runpm(struct amdgpu_device *adev) 2945 { 2946 enum amd_dpm_forced_level level; 2947 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2948 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2949 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2950 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2951 2952 level = amdgpu_dpm_get_performance_level(adev); 2953 if (level & profile_mode_mask) 2954 amdgpu_asic_update_umd_stable_pstate(adev, true); 2955 } 2956 2957 static int amdgpu_pmops_runtime_resume(struct device *dev) 2958 { 2959 struct pci_dev *pdev = to_pci_dev(dev); 2960 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2961 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2962 int ret; 2963 2964 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2965 return -EINVAL; 2966 2967 /* Avoids registers access if device is physically gone */ 2968 if (!pci_device_is_present(adev->pdev)) 2969 adev->no_hw_access = true; 2970 2971 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2972 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2973 2974 /* Only need to handle PCI state in the driver for ATPX 2975 * PCI core handles it for _PR3. 2976 */ 2977 pci_set_power_state(pdev, PCI_D0); 2978 amdgpu_device_load_pci_state(pdev); 2979 ret = pci_enable_device(pdev); 2980 if (ret) 2981 return ret; 2982 pci_set_master(pdev); 2983 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2984 /* Only need to handle PCI state in the driver for ATPX 2985 * PCI core handles it for _PR3. 2986 */ 2987 pci_set_master(pdev); 2988 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2989 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2990 amdgpu_device_baco_exit(adev); 2991 } 2992 ret = amdgpu_device_resume(drm_dev, false); 2993 if (ret) { 2994 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2995 pci_disable_device(pdev); 2996 return ret; 2997 } 2998 2999 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 3000 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 3001 3002 amdgpu_restore_umd_profile_pstate_after_runpm(adev); 3003 adev->in_runpm = false; 3004 return 0; 3005 } 3006 3007 static int amdgpu_drm_release(struct inode *inode, struct file *filp) 3008 { 3009 struct drm_file *file_priv = filp->private_data; 3010 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 3011 struct drm_device *dev = file_priv->minor->dev; 3012 int idx; 3013 3014 if (fpriv && drm_dev_enter(dev, &idx)) { 3015 amdgpu_evf_mgr_shutdown(&fpriv->evf_mgr); 3016 amdgpu_userq_mgr_cancel_resume(&fpriv->userq_mgr); 3017 amdgpu_evf_mgr_flush_suspend(&fpriv->evf_mgr); 3018 amdgpu_userq_mgr_fini(&fpriv->userq_mgr); 3019 amdgpu_evf_mgr_fini(&fpriv->evf_mgr); 3020 drm_dev_exit(idx); 3021 } 3022 3023 return drm_release(inode, filp); 3024 } 3025 3026 long amdgpu_drm_ioctl(struct file *filp, 3027 unsigned int cmd, unsigned long arg) 3028 { 3029 struct drm_file *file_priv = filp->private_data; 3030 struct drm_device *dev; 3031 long ret; 3032 3033 dev = file_priv->minor->dev; 3034 ret = pm_runtime_get_sync(dev->dev); 3035 if (ret < 0) 3036 goto out; 3037 3038 ret = drm_ioctl(filp, cmd, arg); 3039 3040 out: 3041 pm_runtime_put_autosuspend(dev->dev); 3042 return ret; 3043 } 3044 3045 static const struct dev_pm_ops amdgpu_pm_ops = { 3046 .prepare = pm_sleep_ptr(amdgpu_pmops_prepare), 3047 .complete = pm_sleep_ptr(amdgpu_pmops_complete), 3048 .suspend = pm_sleep_ptr(amdgpu_pmops_suspend), 3049 .suspend_noirq = pm_sleep_ptr(amdgpu_pmops_suspend_noirq), 3050 .resume = pm_sleep_ptr(amdgpu_pmops_resume), 3051 .freeze = pm_sleep_ptr(amdgpu_pmops_freeze), 3052 .thaw = pm_sleep_ptr(amdgpu_pmops_thaw), 3053 .poweroff = pm_sleep_ptr(amdgpu_pmops_poweroff), 3054 .restore = pm_sleep_ptr(amdgpu_pmops_restore), 3055 .runtime_suspend = amdgpu_pmops_runtime_suspend, 3056 .runtime_resume = amdgpu_pmops_runtime_resume, 3057 .runtime_idle = amdgpu_pmops_runtime_idle, 3058 }; 3059 3060 static int amdgpu_flush(struct file *f, fl_owner_t id) 3061 { 3062 struct drm_file *file_priv = f->private_data; 3063 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 3064 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 3065 3066 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 3067 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 3068 3069 return timeout >= 0 ? 0 : timeout; 3070 } 3071 3072 static const struct file_operations amdgpu_driver_kms_fops = { 3073 .owner = THIS_MODULE, 3074 .open = drm_open, 3075 .flush = amdgpu_flush, 3076 .release = amdgpu_drm_release, 3077 .unlocked_ioctl = amdgpu_drm_ioctl, 3078 .mmap = drm_gem_mmap, 3079 .poll = drm_poll, 3080 .read = drm_read, 3081 #ifdef CONFIG_COMPAT 3082 .compat_ioctl = amdgpu_kms_compat_ioctl, 3083 #endif 3084 #ifdef CONFIG_PROC_FS 3085 .show_fdinfo = drm_show_fdinfo, 3086 #endif 3087 .fop_flags = FOP_UNSIGNED_OFFSET, 3088 }; 3089 3090 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 3091 { 3092 struct drm_file *file; 3093 3094 if (!filp) 3095 return -EINVAL; 3096 3097 if (filp->f_op != &amdgpu_driver_kms_fops) 3098 return -EINVAL; 3099 3100 file = filp->private_data; 3101 *fpriv = file->driver_priv; 3102 return 0; 3103 } 3104 3105 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 3106 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3107 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3108 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3109 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 3110 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3111 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3112 /* KMS */ 3113 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3114 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3115 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3116 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3117 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3118 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3119 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3120 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3121 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3122 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3123 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ, amdgpu_userq_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3124 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3125 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3126 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3127 DRM_IOCTL_DEF_DRV(AMDGPU_PROC_OPTIONS, amdgpu_proc_options_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3128 }; 3129 3130 static const struct drm_driver amdgpu_kms_driver = { 3131 .driver_features = 3132 DRIVER_ATOMIC | 3133 DRIVER_GEM | 3134 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 3135 DRIVER_SYNCOBJ_TIMELINE, 3136 .open = amdgpu_driver_open_kms, 3137 .postclose = amdgpu_driver_postclose_kms, 3138 .ioctls = amdgpu_ioctls_kms, 3139 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 3140 .dumb_create = amdgpu_mode_dumb_create, 3141 .dumb_map_offset = amdgpu_mode_dumb_mmap, 3142 DRM_FBDEV_TTM_DRIVER_OPS, 3143 .fops = &amdgpu_driver_kms_fops, 3144 .release = &amdgpu_driver_release_kms, 3145 #ifdef CONFIG_PROC_FS 3146 .show_fdinfo = amdgpu_show_fdinfo, 3147 #endif 3148 3149 .gem_prime_import = amdgpu_gem_prime_import, 3150 3151 .name = DRIVER_NAME, 3152 .desc = DRIVER_DESC, 3153 .major = KMS_DRIVER_MAJOR, 3154 .minor = KMS_DRIVER_MINOR, 3155 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3156 }; 3157 3158 const struct drm_driver amdgpu_partition_driver = { 3159 .driver_features = 3160 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 3161 DRIVER_SYNCOBJ_TIMELINE, 3162 .open = amdgpu_driver_open_kms, 3163 .postclose = amdgpu_driver_postclose_kms, 3164 .ioctls = amdgpu_ioctls_kms, 3165 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 3166 .dumb_create = amdgpu_mode_dumb_create, 3167 .dumb_map_offset = amdgpu_mode_dumb_mmap, 3168 DRM_FBDEV_TTM_DRIVER_OPS, 3169 .fops = &amdgpu_driver_kms_fops, 3170 .release = &amdgpu_driver_release_kms, 3171 3172 .gem_prime_import = amdgpu_gem_prime_import, 3173 3174 .name = DRIVER_NAME, 3175 .desc = DRIVER_DESC, 3176 .major = KMS_DRIVER_MAJOR, 3177 .minor = KMS_DRIVER_MINOR, 3178 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3179 }; 3180 3181 static struct pci_error_handlers amdgpu_pci_err_handler = { 3182 .error_detected = amdgpu_pci_error_detected, 3183 .mmio_enabled = amdgpu_pci_mmio_enabled, 3184 .slot_reset = amdgpu_pci_slot_reset, 3185 .resume = amdgpu_pci_resume, 3186 }; 3187 3188 static const struct attribute_group *amdgpu_sysfs_groups[] = { 3189 &amdgpu_vram_mgr_attr_group, 3190 &amdgpu_gtt_mgr_attr_group, 3191 &amdgpu_flash_attr_group, 3192 NULL, 3193 }; 3194 3195 static struct pci_driver amdgpu_kms_pci_driver = { 3196 .name = DRIVER_NAME, 3197 .id_table = pciidlist, 3198 .probe = amdgpu_pci_probe, 3199 .remove = amdgpu_pci_remove, 3200 .shutdown = amdgpu_pci_shutdown, 3201 .driver.pm = pm_ptr(&amdgpu_pm_ops), 3202 .err_handler = &amdgpu_pci_err_handler, 3203 .dev_groups = amdgpu_sysfs_groups, 3204 }; 3205 3206 static int __init amdgpu_init(void) 3207 { 3208 int r; 3209 3210 /* Train lockdep on correct lock ordering */ 3211 amdgpu_lockdep_init(); 3212 3213 r = amdgpu_sync_init(); 3214 if (r) 3215 return r; 3216 3217 amdgpu_register_atpx_handler(); 3218 amdgpu_acpi_detect(); 3219 3220 /* Ignore KFD init failures when CONFIG_HSA_AMD is not set. */ 3221 r = amdgpu_amdkfd_init(); 3222 if (r && r != -ENOENT) 3223 goto error_fini_sync; 3224 3225 if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) { 3226 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 3227 pr_crit("Overdrive is enabled, please disable it before " 3228 "reporting any bugs unrelated to overdrive.\n"); 3229 } 3230 3231 /* let modprobe override vga console setting */ 3232 return pci_register_driver(&amdgpu_kms_pci_driver); 3233 3234 error_fini_sync: 3235 amdgpu_sync_fini(); 3236 return r; 3237 } 3238 3239 static void __exit amdgpu_exit(void) 3240 { 3241 amdgpu_amdkfd_fini(); 3242 pci_unregister_driver(&amdgpu_kms_pci_driver); 3243 amdgpu_unregister_atpx_handler(); 3244 amdgpu_acpi_release(); 3245 amdgpu_sync_fini(); 3246 mmu_notifier_synchronize(); 3247 amdgpu_xcp_drv_release(); 3248 3249 /* 3250 * Flush outstanding call_rcu() callbacks before the 3251 * module text is freed. Otherwise a grace period elapsing after 3252 * unload invokes a callback in already-freed module memory and 3253 * faults in rcu_do_batch(). 3254 */ 3255 rcu_barrier(); 3256 } 3257 3258 module_init(amdgpu_init); 3259 module_exit(amdgpu_exit); 3260 3261 MODULE_AUTHOR(DRIVER_AUTHOR); 3262 MODULE_DESCRIPTION(DRIVER_DESC); 3263 MODULE_LICENSE("GPL and additional rights"); 3264