1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 /** 30 * DOC: Interrupt Handling 31 * 32 * Interrupts generated within GPU hardware raise interrupt requests that are 33 * passed to amdgpu IRQ handler which is responsible for detecting source and 34 * type of the interrupt and dispatching matching handlers. If handling an 35 * interrupt requires calling kernel functions that may sleep processing is 36 * dispatched to work handlers. 37 * 38 * If MSI functionality is not disabled by module parameter then MSI 39 * support will be enabled. 40 * 41 * For GPU interrupt sources that may be driven by another driver, IRQ domain 42 * support is used (with mapping between virtual and hardware IRQs). 43 */ 44 45 #include <linux/irq.h> 46 #include <linux/pci.h> 47 48 #include <drm/drm_vblank.h> 49 #include <drm/amdgpu_drm.h> 50 #include <drm/drm_drv.h> 51 #include "amdgpu.h" 52 #include "amdgpu_ih.h" 53 #include "atom.h" 54 #include "amdgpu_connectors.h" 55 #include "amdgpu_trace.h" 56 #include "amdgpu_amdkfd.h" 57 #include "amdgpu_ras.h" 58 59 #include <linux/pm_runtime.h> 60 61 #ifdef CONFIG_DRM_AMD_DC 62 #include "amdgpu_dm_irq.h" 63 #endif 64 65 #define AMDGPU_WAIT_IDLE_TIMEOUT 200 66 67 const char *soc15_ih_clientid_name[] = { 68 "IH", 69 "SDMA2 or ACP", 70 "ATHUB", 71 "BIF", 72 "SDMA3 or DCE", 73 "SDMA4 or ISP", 74 "VMC1 or PCIE0", 75 "RLC", 76 "SDMA0", 77 "SDMA1", 78 "SE0SH", 79 "SE1SH", 80 "SE2SH", 81 "SE3SH", 82 "VCN1 or UVD1", 83 "THM", 84 "VCN or UVD", 85 "SDMA5 or VCE0", 86 "VMC", 87 "SDMA6 or XDMA", 88 "GRBM_CP", 89 "ATS", 90 "ROM_SMUIO", 91 "DF", 92 "SDMA7 or VCE1", 93 "PWR", 94 "reserved", 95 "UTCL2", 96 "EA", 97 "UTCL2LOG", 98 "MP0", 99 "MP1" 100 }; 101 102 const char *soc_v1_0_ih_clientid_name[] = { 103 "IH", 104 "Reserved", 105 "ATHUB", 106 "BIF", 107 "Reserved", 108 "Reserved", 109 "Reserved", 110 "RLC", 111 "Reserved", 112 "Reserved", 113 "GFX", 114 "IMU", 115 "Reserved", 116 "Reserved", 117 "VCN1 or UVD1", 118 "THM", 119 "VCN or UVD", 120 "Reserved", 121 "VMC", 122 "Reserved", 123 "GRBM_CP", 124 "GC_AID", 125 "ROM_SMUIO", 126 "DF", 127 "Reserved", 128 "PWR", 129 "LSDMA", 130 "GC_UTCL2", 131 "nHT", 132 "Reserved", 133 "MP0", 134 "MP1", 135 }; 136 137 const char *soc_v2_0_ih_clientid_name[] = { 138 "IH", 139 "Reserved", 140 "ATHUB", 141 "BIF", 142 "DCN", 143 "Reserved", 144 "Reserved", 145 "RLC", 146 "Reserved", 147 "Reserved", 148 "GFX", 149 "IMU", 150 "NVE", 151 "Reserved", 152 "Reserved", 153 "THM", 154 "UMSCH_VCN", 155 "Reserved", 156 "VMC", 157 "Reserved", 158 "GRBM_CP", 159 "Reserved", 160 "Reserved", 161 "DF", 162 "VPE", 163 "SMUIO", 164 "Reserved", 165 "GC_UTCL2", 166 "Reserved", 167 "Reserved", 168 "MPASP", 169 "MP1", 170 }; 171 172 const int node_id_to_phys_map[NODEID_MAX] = { 173 [AID0_NODEID] = 0, 174 [XCD0_NODEID] = 0, 175 [XCD1_NODEID] = 1, 176 [AID1_NODEID] = 1, 177 [XCD2_NODEID] = 2, 178 [XCD3_NODEID] = 3, 179 [AID2_NODEID] = 2, 180 [XCD4_NODEID] = 4, 181 [XCD5_NODEID] = 5, 182 [AID3_NODEID] = 3, 183 [XCD6_NODEID] = 6, 184 [XCD7_NODEID] = 7, 185 }; 186 187 /** 188 * amdgpu_irq_disable_all - disable *all* interrupts 189 * 190 * @adev: amdgpu device pointer 191 * 192 * Disable all types of interrupts from all sources. 193 */ 194 void amdgpu_irq_disable_all(struct amdgpu_device *adev) 195 { 196 unsigned long irqflags; 197 unsigned int i, j, k; 198 int r; 199 200 spin_lock_irqsave(&adev->irq.lock, irqflags); 201 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 202 if (!adev->irq.client[i].sources) 203 continue; 204 205 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 206 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 207 208 if (!src || !src->funcs->set || !src->num_types) 209 continue; 210 211 for (k = 0; k < src->num_types; ++k) { 212 r = src->funcs->set(adev, src, k, 213 AMDGPU_IRQ_STATE_DISABLE); 214 if (r) 215 dev_err(adev->dev, 216 "error disabling interrupt (%d)\n", 217 r); 218 } 219 } 220 } 221 spin_unlock_irqrestore(&adev->irq.lock, irqflags); 222 } 223 224 /** 225 * amdgpu_irq_handler - IRQ handler 226 * 227 * @irq: IRQ number (unused) 228 * @arg: pointer to DRM device 229 * 230 * IRQ handler for amdgpu driver (all ASICs). 231 * 232 * Returns: 233 * result of handling the IRQ, as defined by &irqreturn_t 234 */ 235 static irqreturn_t amdgpu_irq_handler(int irq, void *arg) 236 { 237 struct drm_device *dev = (struct drm_device *) arg; 238 struct amdgpu_device *adev = drm_to_adev(dev); 239 irqreturn_t ret; 240 241 ret = amdgpu_ih_process(adev, &adev->irq.ih); 242 if (ret == IRQ_HANDLED) 243 pm_runtime_mark_last_busy(dev->dev); 244 245 amdgpu_ras_interrupt_fatal_error_handler(adev); 246 247 return ret; 248 } 249 250 /** 251 * amdgpu_irq_handle_ih1 - kick of processing for IH1 252 * 253 * @work: work structure in struct amdgpu_irq 254 * 255 * Kick of processing IH ring 1. 256 */ 257 static void amdgpu_irq_handle_ih1(struct work_struct *work) 258 { 259 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 260 irq.ih1_work); 261 262 amdgpu_ih_process(adev, &adev->irq.ih1); 263 } 264 265 /** 266 * amdgpu_irq_handle_ih2 - kick of processing for IH2 267 * 268 * @work: work structure in struct amdgpu_irq 269 * 270 * Kick of processing IH ring 2. 271 */ 272 static void amdgpu_irq_handle_ih2(struct work_struct *work) 273 { 274 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 275 irq.ih2_work); 276 277 amdgpu_ih_process(adev, &adev->irq.ih2); 278 } 279 280 /** 281 * amdgpu_irq_handle_ih_soft - kick of processing for ih_soft 282 * 283 * @work: work structure in struct amdgpu_irq 284 * 285 * Kick of processing IH soft ring. 286 */ 287 static void amdgpu_irq_handle_ih_soft(struct work_struct *work) 288 { 289 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 290 irq.ih_soft_work); 291 292 amdgpu_ih_process(adev, &adev->irq.ih_soft); 293 } 294 295 static void amdgpu_irq_handle_ih_psp(struct work_struct *work) 296 { 297 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 298 irq.ih_psp_work); 299 300 amdgpu_ih_process(adev, &adev->irq.ih_psp); 301 } 302 303 static void amdgpu_irq_handle_ih_ualink(struct work_struct *work) 304 { 305 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 306 irq.ih_ualink_work); 307 308 amdgpu_ih_process(adev, &adev->irq.ih_ualink); 309 } 310 311 /** 312 * amdgpu_msi_ok - check whether MSI functionality is enabled 313 * 314 * @adev: amdgpu device pointer (unused) 315 * 316 * Checks whether MSI functionality has been disabled via module parameter 317 * (all ASICs). 318 * 319 * Returns: 320 * *true* if MSIs are allowed to be enabled or *false* otherwise 321 */ 322 static bool amdgpu_msi_ok(struct amdgpu_device *adev) 323 { 324 if (amdgpu_msi == 1) 325 return true; 326 else if (amdgpu_msi == 0) 327 return false; 328 329 return true; 330 } 331 332 void amdgpu_restore_msix(struct amdgpu_device *adev) 333 { 334 u16 ctrl; 335 336 pci_read_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 337 if (!(ctrl & PCI_MSIX_FLAGS_ENABLE)) 338 return; 339 340 /* VF FLR */ 341 ctrl &= ~PCI_MSIX_FLAGS_ENABLE; 342 pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl); 343 ctrl |= PCI_MSIX_FLAGS_ENABLE; 344 pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl); 345 } 346 347 /** 348 * amdgpu_irq_init - initialize interrupt handling 349 * 350 * @adev: amdgpu device pointer 351 * 352 * Sets up work functions for hotplug and reset interrupts, enables MSI 353 * functionality, initializes vblank, hotplug and reset interrupt handling. 354 * 355 * Returns: 356 * 0 on success or error code on failure 357 */ 358 int amdgpu_irq_init(struct amdgpu_device *adev) 359 { 360 unsigned int irq, flags; 361 int r; 362 363 /* Enable MSI if not disabled by module parameter */ 364 adev->irq.msi_enabled = false; 365 366 if (!amdgpu_msi_ok(adev)) 367 flags = PCI_IRQ_INTX; 368 else 369 flags = PCI_IRQ_ALL_TYPES; 370 371 /* we only need one vector */ 372 r = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags); 373 if (r < 0) { 374 dev_err(adev->dev, "Failed to alloc msi vectors\n"); 375 return r; 376 } 377 378 if (amdgpu_msi_ok(adev)) { 379 adev->irq.msi_enabled = true; 380 dev_dbg(adev->dev, "using MSI/MSI-X.\n"); 381 } 382 383 INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1); 384 INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2); 385 INIT_WORK(&adev->irq.ih_soft_work, amdgpu_irq_handle_ih_soft); 386 INIT_WORK(&adev->irq.ih_psp_work, amdgpu_irq_handle_ih_psp); 387 INIT_WORK(&adev->irq.ih_ualink_work, amdgpu_irq_handle_ih_ualink); 388 389 /* Use vector 0 for MSI-X. */ 390 r = pci_irq_vector(adev->pdev, 0); 391 if (r < 0) 392 goto free_vectors; 393 irq = r; 394 395 /* PCI devices require shared interrupts. */ 396 r = request_irq(irq, amdgpu_irq_handler, IRQF_SHARED, adev_to_drm(adev)->driver->name, 397 adev_to_drm(adev)); 398 if (r) 399 goto free_vectors; 400 401 adev->irq.installed = true; 402 adev->irq.irq = irq; 403 adev_to_drm(adev)->max_vblank_count = 0x00ffffff; 404 405 dev_dbg(adev->dev, "irq initialized.\n"); 406 return 0; 407 408 free_vectors: 409 if (adev->irq.msi_enabled) 410 pci_free_irq_vectors(adev->pdev); 411 412 adev->irq.msi_enabled = false; 413 return r; 414 } 415 416 void amdgpu_irq_fini_hw(struct amdgpu_device *adev) 417 { 418 if (adev->irq.installed) { 419 free_irq(adev->irq.irq, adev_to_drm(adev)); 420 adev->irq.installed = false; 421 if (adev->irq.msi_enabled) 422 pci_free_irq_vectors(adev->pdev); 423 } 424 425 amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); 426 amdgpu_ih_ring_fini(adev, &adev->irq.ih_psp); 427 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 428 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 429 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 430 } 431 432 /** 433 * amdgpu_irq_fini_sw - shut down interrupt handling 434 * 435 * @adev: amdgpu device pointer 436 * 437 * Tears down work functions for hotplug and reset interrupts, disables MSI 438 * functionality, shuts down vblank, hotplug and reset interrupt handling, 439 * turns off interrupts from all sources (all ASICs). 440 */ 441 void amdgpu_irq_fini_sw(struct amdgpu_device *adev) 442 { 443 unsigned int i, j; 444 445 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 446 if (!adev->irq.client[i].sources) 447 continue; 448 449 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 450 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 451 452 if (!src) 453 continue; 454 455 kfree(src->enabled_types); 456 src->enabled_types = NULL; 457 } 458 kfree(adev->irq.client[i].sources); 459 adev->irq.client[i].sources = NULL; 460 } 461 } 462 463 /** 464 * amdgpu_irq_add_id - register IRQ source 465 * 466 * @adev: amdgpu device pointer 467 * @client_id: client id 468 * @src_id: source id 469 * @source: IRQ source pointer 470 * 471 * Registers IRQ source on a client. 472 * 473 * Returns: 474 * 0 on success or error code otherwise 475 */ 476 int amdgpu_irq_add_id(struct amdgpu_device *adev, 477 unsigned int client_id, unsigned int src_id, 478 struct amdgpu_irq_src *source) 479 { 480 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) 481 return -EINVAL; 482 483 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) 484 return -EINVAL; 485 486 if (!source->funcs) 487 return -EINVAL; 488 489 if (!adev->irq.client[client_id].sources) { 490 adev->irq.client[client_id].sources = 491 kzalloc_objs(struct amdgpu_irq_src *, 492 AMDGPU_MAX_IRQ_SRC_ID); 493 if (!adev->irq.client[client_id].sources) 494 return -ENOMEM; 495 } 496 497 if (adev->irq.client[client_id].sources[src_id] != NULL) 498 return -EINVAL; 499 500 if (source->num_types && !source->enabled_types) { 501 atomic_t *types; 502 503 types = kzalloc_objs(atomic_t, source->num_types); 504 if (!types) 505 return -ENOMEM; 506 507 source->enabled_types = types; 508 } 509 510 adev->irq.client[client_id].sources[src_id] = source; 511 return 0; 512 } 513 514 /** 515 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks 516 * 517 * @adev: amdgpu device pointer 518 * @ih: interrupt ring instance 519 * 520 * Dispatches IRQ to IP blocks. 521 */ 522 void amdgpu_irq_dispatch(struct amdgpu_device *adev, 523 struct amdgpu_ih_ring *ih) 524 { 525 u32 ring_index = ih->rptr >> 2; 526 struct amdgpu_iv_entry entry; 527 unsigned int client_id, src_id; 528 struct amdgpu_irq_src *src; 529 bool handled = false; 530 int r; 531 532 entry.ih = ih; 533 entry.iv_entry = (const uint32_t *)&ih->ring[ring_index]; 534 535 /* 536 * timestamp is not supported on some legacy SOCs (cik, cz, iceland, 537 * si and tonga), so initialize timestamp and timestamp_src to 0 538 */ 539 entry.timestamp = 0; 540 entry.timestamp_src = 0; 541 542 amdgpu_ih_decode_iv(adev, &entry); 543 544 trace_amdgpu_iv(ih - &adev->irq.ih, &entry); 545 546 client_id = entry.client_id; 547 src_id = entry.src_id; 548 549 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) { 550 dev_dbg(adev->dev, "Invalid client_id in IV: %d\n", client_id); 551 552 } else if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) { 553 dev_dbg(adev->dev, "Invalid src_id in IV: %d\n", src_id); 554 555 } else if (((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) || 556 (client_id == SOC15_IH_CLIENTID_ISP)) && 557 adev->irq.virq[src_id]) { 558 generic_handle_domain_irq(adev->irq.domain, src_id); 559 560 } else if (!adev->irq.client[client_id].sources) { 561 dev_dbg(adev->dev, 562 "Unregistered interrupt client_id: %d src_id: %d\n", 563 client_id, src_id); 564 565 } else if ((src = adev->irq.client[client_id].sources[src_id])) { 566 r = src->funcs->process(adev, src, &entry); 567 if (r < 0) 568 dev_err(adev->dev, "error processing interrupt (%d)\n", 569 r); 570 else if (r) 571 handled = true; 572 573 } else { 574 dev_dbg(adev->dev, 575 "Unregistered interrupt src_id: %d of client_id:%d\n", 576 src_id, client_id); 577 } 578 579 /* Send it to amdkfd as well if it isn't already handled */ 580 if (!handled) 581 amdgpu_amdkfd_interrupt(adev, entry.iv_entry); 582 583 if (amdgpu_ih_ts_after(ih->processed_timestamp, entry.timestamp)) 584 ih->processed_timestamp = entry.timestamp; 585 } 586 587 /** 588 * amdgpu_irq_delegate - delegate IV to soft IH ring 589 * 590 * @adev: amdgpu device pointer 591 * @entry: IV entry 592 * @num_dw: size of IV 593 * 594 * Delegate the IV to the soft IH ring and schedule processing of it. Used 595 * if the hardware delegation to IH1 or IH2 doesn't work for some reason. 596 */ 597 void amdgpu_irq_delegate(struct amdgpu_device *adev, 598 struct amdgpu_iv_entry *entry, 599 unsigned int num_dw) 600 { 601 amdgpu_ih_ring_write(adev, &adev->irq.ih_soft, entry->iv_entry, num_dw); 602 queue_work(system_dfl_wq, &adev->irq.ih_soft_work); 603 } 604 605 void amdgpu_irq_psp_delegate(struct amdgpu_device *adev, 606 struct amdgpu_iv_entry *entry, 607 unsigned int num_dw) 608 { 609 amdgpu_ih_ring_write(adev, &adev->irq.ih_psp, entry->iv_entry, num_dw); 610 schedule_work(&adev->irq.ih_psp_work); 611 } 612 613 void amdgpu_irq_ualink_delegate(struct amdgpu_device *adev, 614 struct amdgpu_iv_entry *entry, 615 unsigned int num_dw) 616 { 617 amdgpu_ih_ring_write(adev, &adev->irq.ih_ualink, entry->iv_entry, num_dw); 618 schedule_work(&adev->irq.ih_ualink_work); 619 } 620 621 /** 622 * amdgpu_irq_update - update hardware interrupt state 623 * 624 * @adev: amdgpu device pointer 625 * @src: interrupt source pointer 626 * @type: type of interrupt 627 * 628 * Updates interrupt state for the specific source (all ASICs). 629 */ 630 int amdgpu_irq_update(struct amdgpu_device *adev, 631 struct amdgpu_irq_src *src, unsigned int type) 632 { 633 unsigned long irqflags; 634 enum amdgpu_interrupt_state state; 635 int r; 636 637 spin_lock_irqsave(&adev->irq.lock, irqflags); 638 639 /* We need to determine after taking the lock, otherwise 640 * we might disable just enabled interrupts again 641 */ 642 if (amdgpu_irq_enabled(adev, src, type)) 643 state = AMDGPU_IRQ_STATE_ENABLE; 644 else 645 state = AMDGPU_IRQ_STATE_DISABLE; 646 647 r = src->funcs->set(adev, src, type, state); 648 spin_unlock_irqrestore(&adev->irq.lock, irqflags); 649 return r; 650 } 651 652 /** 653 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources 654 * 655 * @adev: amdgpu device pointer 656 * 657 * Updates state of all types of interrupts on all sources on resume after 658 * reset. 659 */ 660 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev) 661 { 662 int i, j, k; 663 664 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev)) 665 amdgpu_restore_msix(adev); 666 667 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { 668 if (!adev->irq.client[i].sources) 669 continue; 670 671 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) { 672 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; 673 674 if (!src || !src->funcs || !src->funcs->set) 675 continue; 676 for (k = 0; k < src->num_types; k++) 677 amdgpu_irq_update(adev, src, k); 678 } 679 } 680 } 681 682 /** 683 * amdgpu_irq_get - enable interrupt 684 * 685 * @adev: amdgpu device pointer 686 * @src: interrupt source pointer 687 * @type: type of interrupt 688 * 689 * Enables specified type of interrupt on the specified source (all ASICs). 690 * 691 * Returns: 692 * 0 on success or error code otherwise 693 */ 694 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 695 unsigned int type) 696 { 697 if (!adev->irq.installed) 698 return -ENOENT; 699 700 if (type >= src->num_types) 701 return -EINVAL; 702 703 if (!src->enabled_types || !src->funcs->set) 704 return -EINVAL; 705 706 if (atomic_inc_return(&src->enabled_types[type]) == 1) 707 return amdgpu_irq_update(adev, src, type); 708 709 return 0; 710 } 711 712 /** 713 * amdgpu_irq_put - disable interrupt 714 * 715 * @adev: amdgpu device pointer 716 * @src: interrupt source pointer 717 * @type: type of interrupt 718 * 719 * Enables specified type of interrupt on the specified source (all ASICs). 720 * 721 * Returns: 722 * 0 on success or error code otherwise 723 */ 724 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 725 unsigned int type) 726 { 727 /* When the threshold is reached,the interrupt source may not be enabled.return -EINVAL */ 728 if (amdgpu_ras_is_rma(adev) && !amdgpu_irq_enabled(adev, src, type)) 729 return -EINVAL; 730 731 if (!adev->irq.installed) 732 return -ENOENT; 733 734 if (type >= src->num_types) 735 return -EINVAL; 736 737 if (!src->enabled_types || !src->funcs->set) 738 return -EINVAL; 739 740 if (WARN_ON(!amdgpu_irq_enabled(adev, src, type))) 741 return -EINVAL; 742 743 if (atomic_dec_and_test(&src->enabled_types[type])) 744 return amdgpu_irq_update(adev, src, type); 745 746 return 0; 747 } 748 749 /** 750 * amdgpu_irq_enabled - check whether interrupt is enabled or not 751 * 752 * @adev: amdgpu device pointer 753 * @src: interrupt source pointer 754 * @type: type of interrupt 755 * 756 * Checks whether the given type of interrupt is enabled on the given source. 757 * 758 * Returns: 759 * *true* if interrupt is enabled, *false* if interrupt is disabled or on 760 * invalid parameters 761 */ 762 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 763 unsigned int type) 764 { 765 if (!adev->irq.installed) 766 return false; 767 768 if (type >= src->num_types) 769 return false; 770 771 if (!src->enabled_types || !src->funcs->set) 772 return false; 773 774 return !!atomic_read(&src->enabled_types[type]); 775 } 776 777 /* XXX: Generic IRQ handling */ 778 static void amdgpu_irq_mask(struct irq_data *irqd) 779 { 780 /* XXX */ 781 } 782 783 static void amdgpu_irq_unmask(struct irq_data *irqd) 784 { 785 /* XXX */ 786 } 787 788 /* amdgpu hardware interrupt chip descriptor */ 789 static struct irq_chip amdgpu_irq_chip = { 790 .name = "amdgpu-ih", 791 .irq_mask = amdgpu_irq_mask, 792 .irq_unmask = amdgpu_irq_unmask, 793 }; 794 795 /** 796 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers 797 * 798 * @d: amdgpu IRQ domain pointer (unused) 799 * @irq: virtual IRQ number 800 * @hwirq: hardware irq number 801 * 802 * Current implementation assigns simple interrupt handler to the given virtual 803 * IRQ. 804 * 805 * Returns: 806 * 0 on success or error code otherwise 807 */ 808 static int amdgpu_irqdomain_map(struct irq_domain *d, 809 unsigned int irq, irq_hw_number_t hwirq) 810 { 811 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID) 812 return -EPERM; 813 814 irq_set_chip_and_handler(irq, 815 &amdgpu_irq_chip, handle_simple_irq); 816 return 0; 817 } 818 819 /* Implementation of methods for amdgpu IRQ domain */ 820 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = { 821 .map = amdgpu_irqdomain_map, 822 }; 823 824 /** 825 * amdgpu_irq_add_domain - create a linear IRQ domain 826 * 827 * @adev: amdgpu device pointer 828 * 829 * Creates an IRQ domain for GPU interrupt sources 830 * that may be driven by another driver (e.g., ACP). 831 * 832 * Returns: 833 * 0 on success or error code otherwise 834 */ 835 int amdgpu_irq_add_domain(struct amdgpu_device *adev) 836 { 837 adev->irq.domain = irq_domain_create_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID, 838 &amdgpu_hw_irqdomain_ops, adev); 839 if (!adev->irq.domain) { 840 dev_err(adev->dev, "GPU irq add domain failed\n"); 841 return -ENODEV; 842 } 843 844 return 0; 845 } 846 847 /** 848 * amdgpu_irq_remove_domain - remove the IRQ domain 849 * 850 * @adev: amdgpu device pointer 851 * 852 * Removes the IRQ domain for GPU interrupt sources 853 * that may be driven by another driver (e.g., ACP). 854 */ 855 void amdgpu_irq_remove_domain(struct amdgpu_device *adev) 856 { 857 if (adev->irq.domain) { 858 irq_domain_remove(adev->irq.domain); 859 adev->irq.domain = NULL; 860 } 861 } 862 863 /** 864 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs 865 * 866 * @adev: amdgpu device pointer 867 * @src_id: IH source id 868 * 869 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ 870 * Use this for components that generate a GPU interrupt, but are driven 871 * by a different driver (e.g., ACP). 872 * 873 * Returns: 874 * Linux IRQ 875 */ 876 unsigned int amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned int src_id) 877 { 878 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id); 879 880 return adev->irq.virq[src_id]; 881 } 882