1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * based on nouveau_prime.c
23 *
24 * Authors: Alex Deucher
25 */
26
27 /**
28 * DOC: PRIME Buffer Sharing
29 *
30 * The following callback implementations are used for :ref:`sharing GEM buffer
31 * objects between different devices via PRIME <prime_buffer_sharing>`.
32 */
33
34 #include "amdgpu.h"
35 #include "amdgpu_display.h"
36 #include "amdgpu_gem.h"
37 #include "amdgpu_dma_buf.h"
38 #include "amdgpu_xgmi.h"
39 #include "amdgpu_vm.h"
40 #include <drm/amdgpu_drm.h>
41 #include <drm/ttm/ttm_tt.h>
42 #include <linux/dma-buf.h>
43 #include <linux/dma-fence-array.h>
44 #include <linux/pci-p2pdma.h>
45
46 static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops;
47
48 /**
49 * dma_buf_attach_adev - Helper to get adev of an attachment
50 *
51 * @attach: attachment
52 *
53 * Returns:
54 * A struct amdgpu_device * if the attaching device is an amdgpu device or
55 * partition, NULL otherwise.
56 */
dma_buf_attach_adev(struct dma_buf_attachment * attach)57 static struct amdgpu_device *dma_buf_attach_adev(struct dma_buf_attachment *attach)
58 {
59 if (attach->importer_ops == &amdgpu_dma_buf_attach_ops) {
60 struct drm_gem_object *obj = attach->importer_priv;
61 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
62
63 return amdgpu_ttm_adev(bo->tbo.bdev);
64 }
65
66 return NULL;
67 }
68
69 /**
70 * amdgpu_dma_buf_attach - &dma_buf_ops.attach implementation
71 *
72 * @dmabuf: DMA-buf where we attach to
73 * @attach: attachment to add
74 *
75 * Add the attachment as user to the exported DMA-buf.
76 */
amdgpu_dma_buf_attach(struct dma_buf * dmabuf,struct dma_buf_attachment * attach)77 static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf,
78 struct dma_buf_attachment *attach)
79 {
80 struct amdgpu_device *attach_adev = dma_buf_attach_adev(attach);
81 struct drm_gem_object *obj = dmabuf->priv;
82 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
83 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
84 int r;
85
86 /*
87 * Disable peer-to-peer access for DCC-enabled VRAM surfaces on GFX12+.
88 * Such buffers cannot be safely accessed over P2P due to device-local
89 * compression metadata. Fallback to system-memory path instead.
90 * Device supports GFX12 (GC 12.x or newer)
91 * BO was created with the AMDGPU_GEM_CREATE_GFX12_DCC flag
92 *
93 */
94 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0) &&
95 bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC)
96 attach->peer2peer = false;
97
98 /*
99 * Disable peer-to-peer access for DCC-enabled VRAM surfaces on GFX12+.
100 * Such buffers cannot be safely accessed over P2P due to device-local
101 * compression metadata. Fallback to system-memory path instead.
102 * Device supports GFX12 (GC 12.x or newer)
103 * BO was created with the AMDGPU_GEM_CREATE_GFX12_DCC flag
104 *
105 */
106 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0) &&
107 bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC)
108 attach->peer2peer = false;
109
110 if (!amdgpu_dmabuf_is_xgmi_accessible(attach_adev, bo) &&
111 pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0)
112 attach->peer2peer = false;
113
114 r = dma_resv_lock(bo->tbo.base.resv, NULL);
115 if (r)
116 return r;
117
118 amdgpu_vm_bo_update_shared(bo);
119
120 dma_resv_unlock(bo->tbo.base.resv);
121
122 return 0;
123 }
124
125 /**
126 * amdgpu_dma_buf_pin - &dma_buf_ops.pin implementation
127 *
128 * @attach: attachment to pin down
129 *
130 * Pin the BO which is backing the DMA-buf so that it can't move any more.
131 */
amdgpu_dma_buf_pin(struct dma_buf_attachment * attach)132 static int amdgpu_dma_buf_pin(struct dma_buf_attachment *attach)
133 {
134 struct dma_buf *dmabuf = attach->dmabuf;
135 struct amdgpu_bo *bo = gem_to_amdgpu_bo(dmabuf->priv);
136 u32 domains = bo->allowed_domains;
137
138 dma_resv_assert_held(dmabuf->resv);
139
140 /* Try pinning into VRAM to allow P2P with RDMA NICs without ODP
141 * support if all attachments can do P2P. If any attachment can't do
142 * P2P just pin into GTT instead.
143 *
144 * To avoid with conflicting pinnings between GPUs and RDMA when move
145 * notifiers are disabled, only allow pinning in VRAM when move
146 * notiers are enabled.
147 */
148 if (!IS_ENABLED(CONFIG_DMABUF_MOVE_NOTIFY)) {
149 domains &= ~AMDGPU_GEM_DOMAIN_VRAM;
150 } else {
151 list_for_each_entry(attach, &dmabuf->attachments, node)
152 if (!attach->peer2peer)
153 domains &= ~AMDGPU_GEM_DOMAIN_VRAM;
154 }
155
156 if (domains & AMDGPU_GEM_DOMAIN_VRAM)
157 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
158
159 if (WARN_ON(!domains))
160 return -EINVAL;
161
162 return amdgpu_bo_pin(bo, domains);
163 }
164
165 /**
166 * amdgpu_dma_buf_unpin - &dma_buf_ops.unpin implementation
167 *
168 * @attach: attachment to unpin
169 *
170 * Unpin a previously pinned BO to make it movable again.
171 */
amdgpu_dma_buf_unpin(struct dma_buf_attachment * attach)172 static void amdgpu_dma_buf_unpin(struct dma_buf_attachment *attach)
173 {
174 struct drm_gem_object *obj = attach->dmabuf->priv;
175 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
176
177 amdgpu_bo_unpin(bo);
178 }
179
180 /**
181 * amdgpu_dma_buf_map - &dma_buf_ops.map_dma_buf implementation
182 * @attach: DMA-buf attachment
183 * @dir: DMA direction
184 *
185 * Makes sure that the shared DMA buffer can be accessed by the target device.
186 * For now, simply pins it to the GTT domain, where it should be accessible by
187 * all DMA devices.
188 *
189 * Returns:
190 * sg_table filled with the DMA addresses to use or ERR_PRT with negative error
191 * code.
192 */
amdgpu_dma_buf_map(struct dma_buf_attachment * attach,enum dma_data_direction dir)193 static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach,
194 enum dma_data_direction dir)
195 {
196 struct dma_buf *dma_buf = attach->dmabuf;
197 struct drm_gem_object *obj = dma_buf->priv;
198 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
199 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
200 struct sg_table *sgt;
201 long r;
202
203 if (!bo->tbo.pin_count) {
204 /* move buffer into GTT or VRAM */
205 struct ttm_operation_ctx ctx = { false, false };
206 unsigned int domains = AMDGPU_GEM_DOMAIN_GTT;
207
208 if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM &&
209 attach->peer2peer) {
210 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
211 domains |= AMDGPU_GEM_DOMAIN_VRAM;
212 }
213 amdgpu_bo_placement_from_domain(bo, domains);
214 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
215 if (r)
216 return ERR_PTR(r);
217 }
218
219 switch (bo->tbo.resource->mem_type) {
220 case TTM_PL_TT:
221 sgt = drm_prime_pages_to_sg(obj->dev,
222 bo->tbo.ttm->pages,
223 bo->tbo.ttm->num_pages);
224 if (IS_ERR(sgt))
225 return sgt;
226
227 if (dma_map_sgtable(attach->dev, sgt, dir,
228 DMA_ATTR_SKIP_CPU_SYNC))
229 goto error_free;
230 break;
231
232 case TTM_PL_VRAM:
233 /* XGMI-accessible memory should never be DMA-mapped */
234 if (WARN_ON(amdgpu_dmabuf_is_xgmi_accessible(
235 dma_buf_attach_adev(attach), bo)))
236 return ERR_PTR(-EINVAL);
237
238 r = amdgpu_vram_mgr_alloc_sgt(adev, bo->tbo.resource, 0,
239 bo->tbo.base.size, attach->dev,
240 dir, &sgt);
241 if (r)
242 return ERR_PTR(r);
243 break;
244 default:
245 return ERR_PTR(-EINVAL);
246 }
247
248 return sgt;
249
250 error_free:
251 sg_free_table(sgt);
252 kfree(sgt);
253 return ERR_PTR(-EBUSY);
254 }
255
256 /**
257 * amdgpu_dma_buf_unmap - &dma_buf_ops.unmap_dma_buf implementation
258 * @attach: DMA-buf attachment
259 * @sgt: sg_table to unmap
260 * @dir: DMA direction
261 *
262 * This is called when a shared DMA buffer no longer needs to be accessible by
263 * another device. For now, simply unpins the buffer from GTT.
264 */
amdgpu_dma_buf_unmap(struct dma_buf_attachment * attach,struct sg_table * sgt,enum dma_data_direction dir)265 static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach,
266 struct sg_table *sgt,
267 enum dma_data_direction dir)
268 {
269 if (sg_page(sgt->sgl)) {
270 dma_unmap_sgtable(attach->dev, sgt, dir, 0);
271 sg_free_table(sgt);
272 kfree(sgt);
273 } else {
274 amdgpu_vram_mgr_free_sgt(attach->dev, dir, sgt);
275 }
276 }
277
278 /**
279 * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation
280 * @dma_buf: Shared DMA buffer
281 * @direction: Direction of DMA transfer
282 *
283 * This is called before CPU access to the shared DMA buffer's memory. If it's
284 * a read access, the buffer is moved to the GTT domain if possible, for optimal
285 * CPU read performance.
286 *
287 * Returns:
288 * 0 on success or a negative error code on failure.
289 */
amdgpu_dma_buf_begin_cpu_access(struct dma_buf * dma_buf,enum dma_data_direction direction)290 static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,
291 enum dma_data_direction direction)
292 {
293 struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
294 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
295 struct ttm_operation_ctx ctx = { true, false };
296 u32 domain = amdgpu_display_supported_domains(adev, bo->flags);
297 int ret;
298 bool reads = (direction == DMA_BIDIRECTIONAL ||
299 direction == DMA_FROM_DEVICE);
300
301 if (!reads || !(domain & AMDGPU_GEM_DOMAIN_GTT))
302 return 0;
303
304 /* move to gtt */
305 ret = amdgpu_bo_reserve(bo, false);
306 if (unlikely(ret != 0))
307 return ret;
308
309 if (!bo->tbo.pin_count &&
310 (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
311 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
312 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
313 }
314
315 amdgpu_bo_unreserve(bo);
316 return ret;
317 }
318
amdgpu_dma_buf_vmap(struct dma_buf * dma_buf,struct iosys_map * map)319 static int amdgpu_dma_buf_vmap(struct dma_buf *dma_buf, struct iosys_map *map)
320 {
321 struct drm_gem_object *obj = dma_buf->priv;
322 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
323 int ret;
324
325 /*
326 * Pin to keep buffer in place while it's vmap'ed. The actual
327 * domain is not that important as long as it's mapable. Using
328 * GTT and VRAM should be compatible with most use cases.
329 */
330 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM);
331 if (ret)
332 return ret;
333 ret = drm_gem_dmabuf_vmap(dma_buf, map);
334 if (ret)
335 amdgpu_bo_unpin(bo);
336
337 return ret;
338 }
339
amdgpu_dma_buf_vunmap(struct dma_buf * dma_buf,struct iosys_map * map)340 static void amdgpu_dma_buf_vunmap(struct dma_buf *dma_buf, struct iosys_map *map)
341 {
342 struct drm_gem_object *obj = dma_buf->priv;
343 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
344
345 drm_gem_dmabuf_vunmap(dma_buf, map);
346 amdgpu_bo_unpin(bo);
347 }
348
349 const struct dma_buf_ops amdgpu_dmabuf_ops = {
350 .attach = amdgpu_dma_buf_attach,
351 .pin = amdgpu_dma_buf_pin,
352 .unpin = amdgpu_dma_buf_unpin,
353 .map_dma_buf = amdgpu_dma_buf_map,
354 .unmap_dma_buf = amdgpu_dma_buf_unmap,
355 .release = drm_gem_dmabuf_release,
356 .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access,
357 .mmap = drm_gem_dmabuf_mmap,
358 .vmap = amdgpu_dma_buf_vmap,
359 .vunmap = amdgpu_dma_buf_vunmap,
360 };
361
362 /**
363 * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation
364 * @gobj: GEM BO
365 * @flags: Flags such as DRM_CLOEXEC and DRM_RDWR.
366 *
367 * The main work is done by the &drm_gem_prime_export helper.
368 *
369 * Returns:
370 * Shared DMA buffer representing the GEM BO from the given device.
371 */
amdgpu_gem_prime_export(struct drm_gem_object * gobj,int flags)372 struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj,
373 int flags)
374 {
375 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
376 struct dma_buf *buf;
377 struct ttm_operation_ctx ctx = {
378 .interruptible = true,
379 .no_wait_gpu = true,
380 /* We opt to avoid OOM on system pages allocations */
381 .gfp_retry_mayfail = true,
382 .allow_res_evict = false,
383 };
384 int ret;
385
386 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
387 bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
388 return ERR_PTR(-EPERM);
389
390 ret = ttm_bo_setup_export(&bo->tbo, &ctx);
391 if (ret)
392 return ERR_PTR(ret);
393
394 buf = drm_gem_prime_export(gobj, flags);
395 if (!IS_ERR(buf))
396 buf->ops = &amdgpu_dmabuf_ops;
397
398 return buf;
399 }
400
401 /**
402 * amdgpu_dma_buf_create_obj - create BO for DMA-buf import
403 *
404 * @dev: DRM device
405 * @dma_buf: DMA-buf
406 *
407 * Creates an empty SG BO for DMA-buf import.
408 *
409 * Returns:
410 * A new GEM BO of the given DRM device, representing the memory
411 * described by the given DMA-buf attachment and scatter/gather table.
412 */
413 static struct drm_gem_object *
amdgpu_dma_buf_create_obj(struct drm_device * dev,struct dma_buf * dma_buf)414 amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
415 {
416 struct dma_resv *resv = dma_buf->resv;
417 struct amdgpu_device *adev = drm_to_adev(dev);
418 struct drm_gem_object *gobj;
419 struct amdgpu_bo *bo;
420 uint64_t flags = 0;
421 int ret;
422
423 dma_resv_lock(resv, NULL);
424
425 if (dma_buf->ops == &amdgpu_dmabuf_ops) {
426 struct amdgpu_bo *other = gem_to_amdgpu_bo(dma_buf->priv);
427
428 flags |= other->flags & (AMDGPU_GEM_CREATE_CPU_GTT_USWC |
429 AMDGPU_GEM_CREATE_COHERENT |
430 AMDGPU_GEM_CREATE_EXT_COHERENT |
431 AMDGPU_GEM_CREATE_UNCACHED);
432 }
433
434 ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE,
435 AMDGPU_GEM_DOMAIN_CPU, flags,
436 ttm_bo_type_sg, resv, &gobj, 0);
437 if (ret)
438 goto error;
439
440 bo = gem_to_amdgpu_bo(gobj);
441 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
442 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
443
444 dma_resv_unlock(resv);
445 return gobj;
446
447 error:
448 dma_resv_unlock(resv);
449 return ERR_PTR(ret);
450 }
451
452 /**
453 * amdgpu_dma_buf_move_notify - &attach.move_notify implementation
454 *
455 * @attach: the DMA-buf attachment
456 *
457 * Invalidate the DMA-buf attachment, making sure that the we re-create the
458 * mapping before the next use.
459 */
460 static void
amdgpu_dma_buf_move_notify(struct dma_buf_attachment * attach)461 amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach)
462 {
463 struct drm_gem_object *obj = attach->importer_priv;
464 struct ww_acquire_ctx *ticket = dma_resv_locking_ctx(obj->resv);
465 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
466 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
467 struct ttm_operation_ctx ctx = { false, false };
468 struct ttm_placement placement = {};
469 struct amdgpu_vm_bo_base *bo_base;
470 int r;
471
472 /* FIXME: This should be after the "if", but needs a fix to make sure
473 * DMABuf imports are initialized in the right VM list.
474 */
475 amdgpu_vm_bo_invalidate(bo, false);
476 if (!bo->tbo.resource || bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
477 return;
478
479 r = ttm_bo_validate(&bo->tbo, &placement, &ctx);
480 if (r) {
481 DRM_ERROR("Failed to invalidate DMA-buf import (%d))\n", r);
482 return;
483 }
484
485 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
486 struct amdgpu_vm *vm = bo_base->vm;
487 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
488
489 if (ticket) {
490 /* When we get an error here it means that somebody
491 * else is holding the VM lock and updating page tables
492 * So we can just continue here.
493 */
494 r = dma_resv_lock(resv, ticket);
495 if (r)
496 continue;
497
498 } else {
499 /* TODO: This is more problematic and we actually need
500 * to allow page tables updates without holding the
501 * lock.
502 */
503 if (!dma_resv_trylock(resv))
504 continue;
505 }
506
507 /* Reserve fences for two SDMA page table updates */
508 r = dma_resv_reserve_fences(resv, 2);
509 if (!r)
510 r = amdgpu_vm_clear_freed(adev, vm, NULL);
511 if (!r)
512 r = amdgpu_vm_handle_moved(adev, vm, ticket);
513
514 if (r && r != -EBUSY)
515 DRM_ERROR("Failed to invalidate VM page tables (%d))\n",
516 r);
517
518 dma_resv_unlock(resv);
519 }
520 }
521
522 static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = {
523 .allow_peer2peer = true,
524 .move_notify = amdgpu_dma_buf_move_notify
525 };
526
527 /**
528 * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation
529 * @dev: DRM device
530 * @dma_buf: Shared DMA buffer
531 *
532 * Import a dma_buf into a the driver and potentially create a new GEM object.
533 *
534 * Returns:
535 * GEM BO representing the shared DMA buffer for the given device.
536 */
amdgpu_gem_prime_import(struct drm_device * dev,struct dma_buf * dma_buf)537 struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
538 struct dma_buf *dma_buf)
539 {
540 struct dma_buf_attachment *attach;
541 struct drm_gem_object *obj;
542
543 if (dma_buf->ops == &amdgpu_dmabuf_ops) {
544 obj = dma_buf->priv;
545 if (obj->dev == dev) {
546 /*
547 * Importing dmabuf exported from out own gem increases
548 * refcount on gem itself instead of f_count of dmabuf.
549 */
550 drm_gem_object_get(obj);
551 return obj;
552 }
553 }
554
555 obj = amdgpu_dma_buf_create_obj(dev, dma_buf);
556 if (IS_ERR(obj))
557 return obj;
558
559 attach = dma_buf_dynamic_attach(dma_buf, dev->dev,
560 &amdgpu_dma_buf_attach_ops, obj);
561 if (IS_ERR(attach)) {
562 drm_gem_object_put(obj);
563 return ERR_CAST(attach);
564 }
565
566 get_dma_buf(dma_buf);
567 obj->import_attach = attach;
568 return obj;
569 }
570
571 /**
572 * amdgpu_dmabuf_is_xgmi_accessible - Check if xgmi available for P2P transfer
573 *
574 * @adev: amdgpu_device pointer of the importer
575 * @bo: amdgpu buffer object
576 *
577 * Returns:
578 * True if dmabuf accessible over xgmi, false otherwise.
579 */
amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device * adev,struct amdgpu_bo * bo)580 bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev,
581 struct amdgpu_bo *bo)
582 {
583 struct drm_gem_object *obj = &bo->tbo.base;
584 struct drm_gem_object *gobj;
585
586 if (!adev)
587 return false;
588
589 if (drm_gem_is_imported(obj)) {
590 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
591
592 if (dma_buf->ops != &amdgpu_dmabuf_ops)
593 /* No XGMI with non AMD GPUs */
594 return false;
595
596 gobj = dma_buf->priv;
597 bo = gem_to_amdgpu_bo(gobj);
598 }
599
600 if (amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev)) &&
601 (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM))
602 return true;
603
604 return false;
605 }
606