1 /*
2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include <drm/amdgpu_drm.h>
26 #include <drm/clients/drm_client_setup.h>
27 #include <drm/drm_drv.h>
28 #include <drm/drm_fbdev_ttm.h>
29 #include <drm/drm_gem.h>
30 #include <drm/drm_managed.h>
31 #include <drm/drm_pciids.h>
32 #include <drm/drm_probe_helper.h>
33 #include <drm/drm_vblank.h>
34
35 #include <linux/cc_platform.h>
36 #include <linux/console.h>
37 #include <linux/dynamic_debug.h>
38 #include <linux/module.h>
39 #include <linux/mmu_notifier.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/suspend.h>
42 #include <linux/vga_switcheroo.h>
43
44 #include "amdgpu.h"
45 #include "amdgpu_amdkfd.h"
46 #include "amdgpu_dma_buf.h"
47 #include "amdgpu_drv.h"
48 #include "amdgpu_fdinfo.h"
49 #include "amdgpu_irq.h"
50 #include "amdgpu_psp.h"
51 #include "amdgpu_ras.h"
52 #include "amdgpu_reset.h"
53 #include "amdgpu_sched.h"
54 #include "amdgpu_xgmi.h"
55 #include "amdgpu_userq.h"
56 #include "amdgpu_userq_fence.h"
57 #include "../amdxcp/amdgpu_xcp_drv.h"
58
59 /*
60 * KMS wrapper.
61 * - 3.0.0 - initial driver
62 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
63 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
64 * at the end of IBs.
65 * - 3.3.0 - Add VM support for UVD on supported hardware.
66 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
67 * - 3.5.0 - Add support for new UVD_NO_OP register.
68 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
69 * - 3.7.0 - Add support for VCE clock list packet
70 * - 3.8.0 - Add support raster config init in the kernel
71 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
72 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
73 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
74 * - 3.12.0 - Add query for double offchip LDS buffers
75 * - 3.13.0 - Add PRT support
76 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
77 * - 3.15.0 - Export more gpu info for gfx9
78 * - 3.16.0 - Add reserved vmid support
79 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
80 * - 3.18.0 - Export gpu always on cu bitmap
81 * - 3.19.0 - Add support for UVD MJPEG decode
82 * - 3.20.0 - Add support for local BOs
83 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
84 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
85 * - 3.23.0 - Add query for VRAM lost counter
86 * - 3.24.0 - Add high priority compute support for gfx9
87 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
88 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
89 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
90 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
91 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
92 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
93 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
94 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
95 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
96 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
97 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
98 * - 3.36.0 - Allow reading more status registers on si/cik
99 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
100 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
101 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
102 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
103 * - 3.41.0 - Add video codec query
104 * - 3.42.0 - Add 16bpc fixed point display support
105 * - 3.43.0 - Add device hot plug/unplug support
106 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
107 * - 3.45.0 - Add context ioctl stable pstate interface
108 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm
109 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
110 * - 3.48.0 - Add IP discovery version info to HW INFO
111 * - 3.49.0 - Add gang submit into CS IOCTL
112 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock
113 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock
114 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl
115 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields:
116 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size,
117 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi
118 * 3.53.0 - Support for GFX11 CP GFX shadowing
119 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support
120 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query
121 * - 3.56.0 - Update IB start address and size alignment for decode and encode
122 * - 3.57.0 - Compute tunneling on GFX10+
123 * - 3.58.0 - Add GFX12 DCC support
124 * - 3.59.0 - Cleared VRAM
125 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement)
126 * - 3.61.0 - Contains fix for RV/PCO compute queues
127 * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT
128 * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size
129 * - 3.64.0 - Userq IP support query
130 */
131 #define KMS_DRIVER_MAJOR 3
132 #define KMS_DRIVER_MINOR 64
133 #define KMS_DRIVER_PATCHLEVEL 0
134
135 /*
136 * amdgpu.debug module options. Are all disabled by default
137 */
138 enum AMDGPU_DEBUG_MASK {
139 AMDGPU_DEBUG_VM = BIT(0),
140 AMDGPU_DEBUG_LARGEBAR = BIT(1),
141 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2),
142 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3),
143 AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4),
144 AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5),
145 AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6),
146 AMDGPU_DEBUG_SMU_POOL = BIT(7),
147 AMDGPU_DEBUG_VM_USERPTR = BIT(8),
148 AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9),
149 AMDGPU_DEBUG_ENABLE_CE_CS = BIT(10)
150 };
151
152 unsigned int amdgpu_vram_limit = UINT_MAX;
153 int amdgpu_vis_vram_limit;
154 int amdgpu_gart_size = -1; /* auto */
155 int amdgpu_gtt_size = -1; /* auto */
156 int amdgpu_moverate = -1; /* auto */
157 int amdgpu_audio = -1;
158 int amdgpu_disp_priority;
159 int amdgpu_hw_i2c;
160 int amdgpu_pcie_gen2 = -1;
161 int amdgpu_msi = -1;
162 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
163 int amdgpu_dpm = -1;
164 int amdgpu_fw_load_type = -1;
165 int amdgpu_aspm = -1;
166 int amdgpu_runtime_pm = -1;
167 uint amdgpu_ip_block_mask = 0xffffffff;
168 int amdgpu_bapm = -1;
169 int amdgpu_deep_color;
170 int amdgpu_vm_size = -1;
171 int amdgpu_vm_fragment_size = -1;
172 int amdgpu_vm_block_size = -1;
173 int amdgpu_vm_fault_stop;
174 int amdgpu_vm_update_mode = -1;
175 int amdgpu_exp_hw_support;
176 int amdgpu_dc = -1;
177 int amdgpu_sched_jobs = 32;
178 int amdgpu_sched_hw_submission = 2;
179 uint amdgpu_pcie_gen_cap;
180 uint amdgpu_pcie_lane_cap;
181 u64 amdgpu_cg_mask = 0xffffffffffffffff;
182 uint amdgpu_pg_mask = 0xffffffff;
183 uint amdgpu_sdma_phase_quantum = 32;
184 char *amdgpu_disable_cu;
185 char *amdgpu_virtual_display;
186 int amdgpu_enforce_isolation = -1;
187 int amdgpu_modeset = -1;
188
189 /* Specifies the default granularity for SVM, used in buffer
190 * migration and restoration of backing memory when handling
191 * recoverable page faults.
192 *
193 * The value is given as log(numPages(buffer)); for a 2 MiB
194 * buffer it computes to be 9
195 */
196 uint amdgpu_svm_default_granularity = 9;
197
198 /*
199 * OverDrive(bit 14) disabled by default
200 * GFX DCS(bit 19) disabled by default
201 */
202 uint amdgpu_pp_feature_mask = 0xfff7bfff;
203 uint amdgpu_force_long_training;
204 int amdgpu_lbpw = -1;
205 int amdgpu_compute_multipipe = -1;
206 int amdgpu_gpu_recovery = -1; /* auto */
207 int amdgpu_emu_mode;
208 uint amdgpu_smu_memory_pool_size;
209 int amdgpu_smu_pptable_id = -1;
210 /*
211 * FBC (bit 0) disabled by default
212 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
213 * - With this, for multiple monitors in sync(e.g. with the same model),
214 * mclk switching will be allowed. And the mclk will be not foced to the
215 * highest. That helps saving some idle power.
216 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
217 * PSR (bit 3) disabled by default
218 * EDP NO POWER SEQUENCING (bit 4) disabled by default
219 */
220 uint amdgpu_dc_feature_mask = 2;
221 uint amdgpu_dc_debug_mask;
222 uint amdgpu_dc_visual_confirm;
223 int amdgpu_async_gfx_ring = 1;
224 int amdgpu_mcbp = -1;
225 int amdgpu_discovery = -1;
226 int amdgpu_mes_log_enable = 0;
227 int amdgpu_uni_mes = 1;
228 int amdgpu_noretry = -1;
229 int amdgpu_force_asic_type = -1;
230 int amdgpu_tmz = -1; /* auto */
231 uint amdgpu_freesync_vid_mode;
232 int amdgpu_reset_method = -1; /* auto */
233 int amdgpu_num_kcq = -1;
234 int amdgpu_smartshift_bias;
235 int amdgpu_use_xgmi_p2p = 1;
236 int amdgpu_vcnfw_log;
237 int amdgpu_sg_display = -1; /* auto */
238 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE;
239 int amdgpu_umsch_mm;
240 int amdgpu_seamless = -1; /* auto */
241 uint amdgpu_debug_mask;
242 int amdgpu_agp = -1; /* auto */
243 int amdgpu_wbrf = -1;
244 int amdgpu_damage_clips = -1; /* auto */
245 int amdgpu_umsch_mm_fwlog;
246 int amdgpu_rebar = -1; /* auto */
247 int amdgpu_user_queue = -1;
248 uint amdgpu_hdmi_hpd_debounce_delay_ms;
249
250 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
251 "DRM_UT_CORE",
252 "DRM_UT_DRIVER",
253 "DRM_UT_KMS",
254 "DRM_UT_PRIME",
255 "DRM_UT_ATOMIC",
256 "DRM_UT_VBL",
257 "DRM_UT_STATE",
258 "DRM_UT_LEASE",
259 "DRM_UT_DP",
260 "DRM_UT_DRMRES");
261
262 struct amdgpu_mgpu_info mgpu_info = {
263 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
264 };
265 int amdgpu_ras_enable = -1;
266 uint amdgpu_ras_mask = 0xffffffff;
267 int amdgpu_bad_page_threshold = -1;
268 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
269 .timeout_fatal_disable = false,
270 .period = 0x0, /* default to 0x0 (timeout disable) */
271 };
272
273 /**
274 * DOC: vramlimit (int)
275 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
276 */
277 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
278 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
279
280 /**
281 * DOC: vis_vramlimit (int)
282 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
283 */
284 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
285 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
286
287 /**
288 * DOC: gartsize (uint)
289 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing.
290 * The default is -1 (The size depends on asic).
291 */
292 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)");
293 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
294
295 /**
296 * DOC: gttsize (int)
297 * Restrict the size of GTT domain (for userspace use) in MiB for testing.
298 * The default is -1 (Use value specified by TTM).
299 * This parameter is deprecated and will be removed in the future.
300 */
301 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)");
302 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
303
304 /**
305 * DOC: moverate (int)
306 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
307 */
308 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
309 module_param_named(moverate, amdgpu_moverate, int, 0600);
310
311 /**
312 * DOC: audio (int)
313 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
314 */
315 MODULE_PARM_DESC(audio, "HDMI/DP Audio enable for non DC displays (-1 = auto, 0 = disable, 1 = enable)");
316 module_param_named(audio, amdgpu_audio, int, 0444);
317
318 /**
319 * DOC: disp_priority (int)
320 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
321 */
322 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
323 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
324
325 /**
326 * DOC: hw_i2c (int)
327 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
328 */
329 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
330 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
331
332 /**
333 * DOC: pcie_gen2 (int)
334 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
335 */
336 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
337 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
338
339 /**
340 * DOC: msi (int)
341 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
342 */
343 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
344 module_param_named(msi, amdgpu_msi, int, 0444);
345
346 /**
347 * DOC: svm_default_granularity (uint)
348 * Used in buffer migration and handling of recoverable page faults
349 */
350 MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB");
351 module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644);
352
353 /**
354 * DOC: lockup_timeout (string)
355 * Set GPU scheduler timeout value in ms.
356 *
357 * The format can be [single value] for setting all timeouts at once or
358 * [GFX,Compute,SDMA,Video] to set individual timeouts.
359 * Negative values mean infinity.
360 *
361 * By default(with no lockup_timeout settings), the timeout for all queues is 2000.
362 */
363 MODULE_PARM_DESC(lockup_timeout,
364 "GPU lockup timeout in ms (default: 2000. 0: keep default value. negative: infinity timeout), format: [single value for all] or [GFX,Compute,SDMA,Video].");
365 module_param_string(lockup_timeout, amdgpu_lockup_timeout,
366 sizeof(amdgpu_lockup_timeout), 0444);
367
368 /**
369 * DOC: dpm (int)
370 * Override for dynamic power management setting
371 * (0 = disable, 1 = enable)
372 * The default is -1 (auto).
373 */
374 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
375 module_param_named(dpm, amdgpu_dpm, int, 0444);
376
377 /**
378 * DOC: fw_load_type (int)
379 * Set different firmware loading type for debugging, if supported.
380 * Set to 0 to force direct loading if supported by the ASIC. Set
381 * to -1 to select the default loading mode for the ASIC, as defined
382 * by the driver. The default is -1 (auto).
383 */
384 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)");
385 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
386
387 /**
388 * DOC: aspm (int)
389 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
390 */
391 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
392 module_param_named(aspm, amdgpu_aspm, int, 0444);
393
394 /**
395 * DOC: runpm (int)
396 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
397 * the dGPUs when they are idle if supported. The default is -1 (auto enable).
398 * Setting the value to 0 disables this functionality.
399 * Setting the value to -2 is auto enabled with power down when displays are attached.
400 */
401 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)");
402 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
403
404 /**
405 * DOC: ip_block_mask (uint)
406 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
407 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
408 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
409 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
410 */
411 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
412 module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
413
414 /**
415 * DOC: bapm (int)
416 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
417 * The default -1 (auto, enabled)
418 */
419 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
420 module_param_named(bapm, amdgpu_bapm, int, 0444);
421
422 /**
423 * DOC: deep_color (int)
424 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
425 */
426 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
427 module_param_named(deep_color, amdgpu_deep_color, int, 0444);
428
429 /**
430 * DOC: vm_size (int)
431 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
432 */
433 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
434 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
435
436 /**
437 * DOC: vm_fragment_size (int)
438 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
439 */
440 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
441 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
442
443 /**
444 * DOC: vm_block_size (int)
445 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
446 */
447 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
448 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
449
450 /**
451 * DOC: vm_fault_stop (int)
452 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
453 */
454 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
455 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
456
457 /**
458 * DOC: vm_update_mode (int)
459 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
460 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
461 */
462 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
463 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
464
465 /**
466 * DOC: exp_hw_support (int)
467 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
468 */
469 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
470 module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
471
472 /**
473 * DOC: dc (int)
474 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
475 */
476 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
477 module_param_named(dc, amdgpu_dc, int, 0444);
478
479 /**
480 * DOC: sched_jobs (int)
481 * Override the max number of jobs supported in the sw queue. The default is 32.
482 */
483 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
484 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
485
486 /**
487 * DOC: sched_hw_submission (int)
488 * Override the max number of HW submissions. The default is 2.
489 */
490 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
491 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
492
493 /**
494 * DOC: ppfeaturemask (hexint)
495 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
496 * The default is the current set of stable power features.
497 */
498 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
499 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
500
501 /**
502 * DOC: forcelongtraining (uint)
503 * Force long memory training in resume.
504 * The default is zero, indicates short training in resume.
505 */
506 MODULE_PARM_DESC(forcelongtraining, "force memory long training");
507 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
508
509 /**
510 * DOC: pcie_gen_cap (uint)
511 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
512 * The default is 0 (automatic for each asic).
513 */
514 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
515 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
516
517 /**
518 * DOC: pcie_lane_cap (uint)
519 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
520 * The default is 0 (automatic for each asic).
521 */
522 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
523 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
524
525 /**
526 * DOC: cg_mask (ullong)
527 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
528 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled).
529 */
530 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
531 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444);
532
533 /**
534 * DOC: pg_mask (uint)
535 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
536 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
537 */
538 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
539 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
540
541 /**
542 * DOC: sdma_phase_quantum (uint)
543 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
544 */
545 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
546 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
547
548 /**
549 * DOC: disable_cu (charp)
550 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
551 */
552 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
553 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
554
555 /**
556 * DOC: virtual_display (charp)
557 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
558 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
559 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
560 * device at 26:00.0. The default is NULL.
561 */
562 MODULE_PARM_DESC(virtual_display,
563 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
564 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
565
566 /**
567 * DOC: lbpw (int)
568 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
569 */
570 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
571 module_param_named(lbpw, amdgpu_lbpw, int, 0444);
572
573 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
574 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
575
576 /**
577 * DOC: gpu_recovery (int)
578 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
579 */
580 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
581 module_param_named_unsafe(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
582
583 /**
584 * DOC: emu_mode (int)
585 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
586 */
587 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
588 module_param_named_unsafe(emu_mode, amdgpu_emu_mode, int, 0444);
589
590 /**
591 * DOC: ras_enable (int)
592 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
593 */
594 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
595 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
596
597 /**
598 * DOC: ras_mask (uint)
599 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
600 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
601 */
602 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
603 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
604
605 /**
606 * DOC: timeout_fatal_disable (bool)
607 * Disable Watchdog timeout fatal error event
608 */
609 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
610 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
611
612 /**
613 * DOC: timeout_period (uint)
614 * Modify the watchdog timeout max_cycles as (1 << period)
615 */
616 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
617 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
618
619 /**
620 * DOC: si_support (int)
621 * 1 = enabled, 0 = disabled, -1 = default
622 *
623 * SI (Southern Islands) are first generation GCN GPUs, supported by both
624 * drivers: radeon (old) and amdgpu (new). This parameter controls whether
625 * amdgpu should support SI.
626 * By default, SI dedicated GPUs are supported by amdgpu.
627 * Only relevant when CONFIG_DRM_AMDGPU_SI is enabled to build SI support in amdgpu.
628 * See also radeon.si_support which should be disabled when amdgpu.si_support is
629 * enabled, and vice versa.
630 */
631 int amdgpu_si_support = -1;
632 #ifdef CONFIG_DRM_AMDGPU_SI
633 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled, -1 = default)");
634 module_param_named(si_support, amdgpu_si_support, int, 0444);
635 #endif
636
637 /**
638 * DOC: cik_support (int)
639 * 1 = enabled, 0 = disabled, -1 = default
640 *
641 * CIK (Sea Islands) are second generation GCN GPUs, supported by both
642 * drivers: radeon (old) and amdgpu (new). This parameter controls whether
643 * amdgpu should support CIK.
644 * By default, CIK dedicated GPUs and APUs are supported by amdgpu.
645 * Only relevant when CONFIG_DRM_AMDGPU_CIK is enabled to build CIK support in amdgpu.
646 * See also radeon.cik_support which should be disabled when amdgpu.cik_support is
647 * enabled, and vice versa.
648 */
649 int amdgpu_cik_support = -1;
650 #ifdef CONFIG_DRM_AMDGPU_CIK
651 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled, -1 = default)");
652 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
653 #endif
654
655 /**
656 * DOC: smu_memory_pool_size (uint)
657 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
658 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
659 */
660 MODULE_PARM_DESC(smu_memory_pool_size,
661 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
662 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
663
664 /**
665 * DOC: async_gfx_ring (int)
666 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
667 */
668 MODULE_PARM_DESC(async_gfx_ring,
669 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
670 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
671
672 /**
673 * DOC: mcbp (int)
674 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default))
675 */
676 MODULE_PARM_DESC(mcbp,
677 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)");
678 module_param_named(mcbp, amdgpu_mcbp, int, 0444);
679
680 /**
681 * DOC: discovery (int)
682 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
683 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
684 */
685 MODULE_PARM_DESC(discovery,
686 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
687 module_param_named(discovery, amdgpu_discovery, int, 0444);
688
689 /**
690 * DOC: mes_log_enable (int)
691 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log.
692 * (0 = disabled (default), 1 = enabled)
693 */
694 MODULE_PARM_DESC(mes_log_enable,
695 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)");
696 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444);
697
698 /**
699 * DOC: uni_mes (int)
700 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler.
701 * (0 = disabled (default), 1 = enabled)
702 */
703 MODULE_PARM_DESC(uni_mes,
704 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)");
705 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444);
706
707 /**
708 * DOC: noretry (int)
709 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
710 * do not support per-process XNACK this also disables retry page faults.
711 * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
712 */
713 MODULE_PARM_DESC(noretry,
714 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
715 module_param_named(noretry, amdgpu_noretry, int, 0644);
716
717 /**
718 * DOC: force_asic_type (int)
719 * A non negative value used to specify the asic type for all supported GPUs.
720 */
721 MODULE_PARM_DESC(force_asic_type,
722 "A non negative value used to specify the asic type for all supported GPUs");
723 module_param_named_unsafe(force_asic_type, amdgpu_force_asic_type, int, 0444);
724
725 /**
726 * DOC: use_xgmi_p2p (int)
727 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable).
728 */
729 MODULE_PARM_DESC(use_xgmi_p2p,
730 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))");
731 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444);
732
733
734 #ifdef CONFIG_HSA_AMD
735 /**
736 * DOC: sched_policy (int)
737 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
738 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
739 * assigns queues to HQDs.
740 */
741 int sched_policy = KFD_SCHED_POLICY_HWS;
742 module_param_unsafe(sched_policy, int, 0444);
743 MODULE_PARM_DESC(sched_policy,
744 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
745
746 /**
747 * DOC: hws_max_conc_proc (int)
748 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
749 * number of VMIDs assigned to the HWS, which is also the default.
750 */
751 int hws_max_conc_proc = -1;
752 module_param(hws_max_conc_proc, int, 0444);
753 MODULE_PARM_DESC(hws_max_conc_proc,
754 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
755
756 /**
757 * DOC: cwsr_enable (int)
758 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
759 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
760 * disables it.
761 */
762 int cwsr_enable = 1;
763 module_param(cwsr_enable, int, 0444);
764 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
765
766 /**
767 * DOC: max_num_of_queues_per_device (int)
768 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
769 * is 4096.
770 */
771 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
772 module_param(max_num_of_queues_per_device, int, 0444);
773 MODULE_PARM_DESC(max_num_of_queues_per_device,
774 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
775
776 /**
777 * DOC: send_sigterm (int)
778 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
779 * but just print errors on dmesg. Setting 1 enables sending sigterm.
780 */
781 int send_sigterm;
782 module_param(send_sigterm, int, 0444);
783 MODULE_PARM_DESC(send_sigterm,
784 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
785
786 /**
787 * DOC: halt_if_hws_hang (int)
788 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
789 * Setting 1 enables halt on hang.
790 */
791 int halt_if_hws_hang;
792 module_param_unsafe(halt_if_hws_hang, int, 0644);
793 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
794
795 /**
796 * DOC: hws_gws_support(bool)
797 * Assume that HWS supports GWS barriers regardless of what firmware version
798 * check says. Default value: false (rely on MEC2 firmware version check).
799 */
800 bool hws_gws_support;
801 module_param_unsafe(hws_gws_support, bool, 0444);
802 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
803
804 /**
805 * DOC: queue_preemption_timeout_ms (int)
806 * queue preemption timeout in ms (1 = Minimum, 9000 = default)
807 */
808 int queue_preemption_timeout_ms = 9000;
809 module_param(queue_preemption_timeout_ms, int, 0644);
810 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
811
812 /**
813 * DOC: debug_evictions(bool)
814 * Enable extra debug messages to help determine the cause of evictions
815 */
816 bool debug_evictions;
817 module_param(debug_evictions, bool, 0644);
818 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
819
820 /**
821 * DOC: no_system_mem_limit(bool)
822 * Disable system memory limit, to support multiple process shared memory
823 */
824 bool no_system_mem_limit;
825 module_param(no_system_mem_limit, bool, 0644);
826 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
827
828 /**
829 * DOC: no_queue_eviction_on_vm_fault (int)
830 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
831 */
832 int amdgpu_no_queue_eviction_on_vm_fault;
833 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
834 module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
835 #endif
836
837 /**
838 * DOC: mtype_local (int)
839 */
840 int amdgpu_mtype_local = -1;
841 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (default: ASIC dependent, 0 = MTYPE_RW, 1 = MTYPE_NC, 2 = MTYPE_CC)");
842 module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444);
843
844 /**
845 * DOC: pcie_p2p (bool)
846 * Enable PCIe P2P (requires large-BAR). Default value: true (on)
847 */
848 #ifdef CONFIG_HSA_AMD_P2P
849 bool pcie_p2p = true;
850 module_param(pcie_p2p, bool, 0444);
851 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))");
852 #endif
853
854 /**
855 * DOC: dcfeaturemask (uint)
856 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
857 * The default is the current set of stable display features.
858 */
859 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
860 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
861
862 /**
863 * DOC: dcdebugmask (uint)
864 * Display debug options. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
865 */
866 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
867 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
868
869 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)");
870 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444);
871
872 /**
873 * DOC: abmlevel (uint)
874 * Override the default ABM (Adaptive Backlight Management) level used for DC
875 * enabled hardware. Requires DMCU to be supported and loaded.
876 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
877 * default. Values 1-4 control the maximum allowable brightness reduction via
878 * the ABM algorithm, with 1 being the least reduction and 4 being the most
879 * reduction.
880 *
881 * Defaults to -1, or auto. Userspace can only override this level after
882 * boot if it's set to auto.
883 */
884 int amdgpu_dm_abm_level = -1;
885 MODULE_PARM_DESC(abmlevel,
886 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))");
887 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444);
888
889 int amdgpu_backlight = -1;
890 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
891 module_param_named(backlight, amdgpu_backlight, bint, 0444);
892
893 /**
894 * DOC: damageclips (int)
895 * Enable or disable damage clips support. If damage clips support is disabled,
896 * we will force full frame updates, irrespective of what user space sends to
897 * us.
898 *
899 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected).
900 */
901 MODULE_PARM_DESC(damageclips,
902 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))");
903 module_param_named(damageclips, amdgpu_damage_clips, int, 0444);
904
905 /**
906 * DOC: tmz (int)
907 * Trusted Memory Zone (TMZ) is a method to protect data being written
908 * to or read from memory.
909 *
910 * The default value: 0 (off). TODO: change to auto till it is completed.
911 */
912 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
913 module_param_named(tmz, amdgpu_tmz, int, 0444);
914
915 /**
916 * DOC: freesync_video (uint)
917 * Enable the optimization to adjust front porch timing to achieve seamless
918 * mode change experience when setting a freesync supported mode for which full
919 * modeset is not needed.
920 *
921 * The Display Core will add a set of modes derived from the base FreeSync
922 * video mode into the corresponding connector's mode list based on commonly
923 * used refresh rates and VRR range of the connected display, when users enable
924 * this feature. From the userspace perspective, they can see a seamless mode
925 * change experience when the change between different refresh rates under the
926 * same resolution. Additionally, userspace applications such as Video playback
927 * can read this modeset list and change the refresh rate based on the video
928 * frame rate. Finally, the userspace can also derive an appropriate mode for a
929 * particular refresh rate based on the FreeSync Mode and add it to the
930 * connector's mode list.
931 *
932 * Note: This is an experimental feature.
933 *
934 * The default value: 0 (off).
935 */
936 MODULE_PARM_DESC(
937 freesync_video,
938 "Adds additional modes via VRR for refresh changes without a full modeset (0 = off (default), 1 = on)");
939 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);
940
941 /**
942 * DOC: reset_method (int)
943 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
944 */
945 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
946 module_param_named_unsafe(reset_method, amdgpu_reset_method, int, 0644);
947
948 /**
949 * DOC: bad_page_threshold (int) Bad page threshold is specifies the
950 * threshold value of faulty pages detected by RAS ECC, which may
951 * result in the GPU entering bad status when the number of total
952 * faulty pages by ECC exceeds the threshold value.
953 */
954 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = threshold determined by a formula, 0 < threshold < max records, user-defined threshold)");
955 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
956
957 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
958 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
959
960 /**
961 * DOC: vcnfw_log (int)
962 * Enable vcnfw log output for debugging, the default is disabled.
963 */
964 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)");
965 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
966
967 /**
968 * DOC: sg_display (int)
969 * Disable S/G (scatter/gather) display (i.e., display from system memory).
970 * This option is only relevant on APUs. Set this option to 0 to disable
971 * S/G display if you experience flickering or other issues under memory
972 * pressure and report the issue.
973 */
974 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)");
975 module_param_named(sg_display, amdgpu_sg_display, int, 0444);
976
977 /**
978 * DOC: umsch_mm (int)
979 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE.
980 * (0 = disabled (default), 1 = enabled)
981 */
982 MODULE_PARM_DESC(umsch_mm,
983 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)");
984 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444);
985
986 /**
987 * DOC: umsch_mm_fwlog (int)
988 * Enable umschfw log output for debugging, the default is disabled.
989 */
990 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)");
991 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444);
992
993 /**
994 * DOC: smu_pptable_id (int)
995 * Used to override pptable id. id = 0 use VBIOS pptable.
996 * id > 0 use the soft pptable with specicfied id.
997 */
998 MODULE_PARM_DESC(smu_pptable_id,
999 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
1000 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
1001
1002 /**
1003 * DOC: partition_mode (int)
1004 * Used to override the default SPX mode.
1005 */
1006 MODULE_PARM_DESC(
1007 user_partt_mode,
1008 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \
1009 0 = AMDGPU_SPX_PARTITION_MODE, \
1010 1 = AMDGPU_DPX_PARTITION_MODE, \
1011 2 = AMDGPU_TPX_PARTITION_MODE, \
1012 3 = AMDGPU_QPX_PARTITION_MODE, \
1013 4 = AMDGPU_CPX_PARTITION_MODE)");
1014 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444);
1015
1016
1017 /**
1018 * DOC: enforce_isolation (int)
1019 * enforce process isolation between graphics and compute.
1020 * (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader)
1021 */
1022 module_param_named(enforce_isolation, amdgpu_enforce_isolation, int, 0444);
1023 MODULE_PARM_DESC(enforce_isolation,
1024 "enforce process isolation between graphics and compute. (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader)");
1025
1026 /**
1027 * DOC: modeset (int)
1028 * Override nomodeset (1 = override, -1 = auto). The default is -1 (auto).
1029 */
1030 MODULE_PARM_DESC(modeset, "Override nomodeset (1 = enable, -1 = auto)");
1031 module_param_named(modeset, amdgpu_modeset, int, 0444);
1032
1033 /**
1034 * DOC: seamless (int)
1035 * Seamless boot will keep the image on the screen during the boot process.
1036 */
1037 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)");
1038 module_param_named(seamless, amdgpu_seamless, int, 0444);
1039
1040 /**
1041 * DOC: debug_mask (uint)
1042 * Debug options for amdgpu, work as a binary mask with the following options:
1043 *
1044 * - 0x1: Debug VM handling
1045 * - 0x2: Enable simulating large-bar capability on non-large bar system. This
1046 * limits the VRAM size reported to ROCm applications to the visible
1047 * size, usually 256MB.
1048 * - 0x4: Disable GPU soft recovery, always do a full reset
1049 * - 0x8: Use VRAM for firmware loading
1050 * - 0x10: Enable ACA based RAS logging
1051 * - 0x20: Enable experimental resets
1052 * - 0x40: Disable ring resets
1053 * - 0x80: Use VRAM for SMU pool
1054 */
1055 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default");
1056 module_param_named_unsafe(debug_mask, amdgpu_debug_mask, uint, 0444);
1057
1058 /**
1059 * DOC: agp (int)
1060 * Enable the AGP aperture. This provides an aperture in the GPU's internal
1061 * address space for direct access to system memory. Note that these accesses
1062 * are non-snooped, so they are only used for access to uncached memory.
1063 */
1064 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)");
1065 module_param_named(agp, amdgpu_agp, int, 0444);
1066
1067 /**
1068 * DOC: wbrf (int)
1069 * Enable Wifi RFI interference mitigation feature.
1070 * Due to electrical and mechanical constraints there may be likely interference of
1071 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio
1072 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference,
1073 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based
1074 * on active list of frequencies in-use (to be avoided) as part of initial setting or
1075 * P-state transition. However, there may be potential performance impact with this
1076 * feature enabled.
1077 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported))
1078 */
1079 MODULE_PARM_DESC(wbrf,
1080 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)");
1081 module_param_named(wbrf, amdgpu_wbrf, int, 0444);
1082
1083 /**
1084 * DOC: rebar (int)
1085 * Allow BAR resizing. Disable this to prevent the driver from attempting
1086 * to resize the BAR if the GPU supports it and there is available MMIO space.
1087 * Note that this just prevents the driver from resizing the BAR. The BIOS
1088 * may have already resized the BAR at boot time.
1089 */
1090 MODULE_PARM_DESC(rebar, "Resizable BAR (-1 = auto (default), 0 = disable, 1 = enable)");
1091 module_param_named(rebar, amdgpu_rebar, int, 0444);
1092
1093 /**
1094 * DOC: user_queue (int)
1095 * Enable user queues on systems that support user queues. Possible values:
1096 *
1097 * - -1 = auto (ASIC specific default)
1098 * - 0 = user queues disabled
1099 * - 1 = user queues enabled and kernel queues enabled (if supported)
1100 * - 2 = user queues enabled and kernel queues disabled
1101 */
1102 MODULE_PARM_DESC(user_queue, "Enable user queues (-1 = auto (default), 0 = disable, 1 = enable, 2 = enable UQs and disable KQs)");
1103 module_param_named(user_queue, amdgpu_user_queue, int, 0444);
1104
1105 /*
1106 * DOC: hdmi_hpd_debounce_delay_ms (uint)
1107 * HDMI HPD disconnect debounce delay in milliseconds.
1108 *
1109 * Used to filter short disconnect->reconnect HPD toggles some HDMI sinks
1110 * generate while entering/leaving power save. Set to 0 to disable by default.
1111 */
1112 MODULE_PARM_DESC(hdmi_hpd_debounce_delay_ms, "HDMI HPD disconnect debounce delay in milliseconds (0 to disable (by default), 1500 is common)");
1113 module_param_named(hdmi_hpd_debounce_delay_ms, amdgpu_hdmi_hpd_debounce_delay_ms, uint, 0644);
1114
1115 /* These devices are not supported by amdgpu.
1116 * They are supported by the mach64, r128, radeon drivers
1117 */
1118 static const u16 amdgpu_unsupported_pciidlist[] = {
1119 /* mach64 */
1120 0x4354,
1121 0x4358,
1122 0x4554,
1123 0x4742,
1124 0x4744,
1125 0x4749,
1126 0x474C,
1127 0x474D,
1128 0x474E,
1129 0x474F,
1130 0x4750,
1131 0x4751,
1132 0x4752,
1133 0x4753,
1134 0x4754,
1135 0x4755,
1136 0x4756,
1137 0x4757,
1138 0x4758,
1139 0x4759,
1140 0x475A,
1141 0x4C42,
1142 0x4C44,
1143 0x4C47,
1144 0x4C49,
1145 0x4C4D,
1146 0x4C4E,
1147 0x4C50,
1148 0x4C51,
1149 0x4C52,
1150 0x4C53,
1151 0x5654,
1152 0x5655,
1153 0x5656,
1154 /* r128 */
1155 0x4c45,
1156 0x4c46,
1157 0x4d46,
1158 0x4d4c,
1159 0x5041,
1160 0x5042,
1161 0x5043,
1162 0x5044,
1163 0x5045,
1164 0x5046,
1165 0x5047,
1166 0x5048,
1167 0x5049,
1168 0x504A,
1169 0x504B,
1170 0x504C,
1171 0x504D,
1172 0x504E,
1173 0x504F,
1174 0x5050,
1175 0x5051,
1176 0x5052,
1177 0x5053,
1178 0x5054,
1179 0x5055,
1180 0x5056,
1181 0x5057,
1182 0x5058,
1183 0x5245,
1184 0x5246,
1185 0x5247,
1186 0x524b,
1187 0x524c,
1188 0x534d,
1189 0x5446,
1190 0x544C,
1191 0x5452,
1192 /* radeon */
1193 0x3150,
1194 0x3151,
1195 0x3152,
1196 0x3154,
1197 0x3155,
1198 0x3E50,
1199 0x3E54,
1200 0x4136,
1201 0x4137,
1202 0x4144,
1203 0x4145,
1204 0x4146,
1205 0x4147,
1206 0x4148,
1207 0x4149,
1208 0x414A,
1209 0x414B,
1210 0x4150,
1211 0x4151,
1212 0x4152,
1213 0x4153,
1214 0x4154,
1215 0x4155,
1216 0x4156,
1217 0x4237,
1218 0x4242,
1219 0x4336,
1220 0x4337,
1221 0x4437,
1222 0x4966,
1223 0x4967,
1224 0x4A48,
1225 0x4A49,
1226 0x4A4A,
1227 0x4A4B,
1228 0x4A4C,
1229 0x4A4D,
1230 0x4A4E,
1231 0x4A4F,
1232 0x4A50,
1233 0x4A54,
1234 0x4B48,
1235 0x4B49,
1236 0x4B4A,
1237 0x4B4B,
1238 0x4B4C,
1239 0x4C57,
1240 0x4C58,
1241 0x4C59,
1242 0x4C5A,
1243 0x4C64,
1244 0x4C66,
1245 0x4C67,
1246 0x4E44,
1247 0x4E45,
1248 0x4E46,
1249 0x4E47,
1250 0x4E48,
1251 0x4E49,
1252 0x4E4A,
1253 0x4E4B,
1254 0x4E50,
1255 0x4E51,
1256 0x4E52,
1257 0x4E53,
1258 0x4E54,
1259 0x4E56,
1260 0x5144,
1261 0x5145,
1262 0x5146,
1263 0x5147,
1264 0x5148,
1265 0x514C,
1266 0x514D,
1267 0x5157,
1268 0x5158,
1269 0x5159,
1270 0x515A,
1271 0x515E,
1272 0x5460,
1273 0x5462,
1274 0x5464,
1275 0x5548,
1276 0x5549,
1277 0x554A,
1278 0x554B,
1279 0x554C,
1280 0x554D,
1281 0x554E,
1282 0x554F,
1283 0x5550,
1284 0x5551,
1285 0x5552,
1286 0x5554,
1287 0x564A,
1288 0x564B,
1289 0x564F,
1290 0x5652,
1291 0x5653,
1292 0x5657,
1293 0x5834,
1294 0x5835,
1295 0x5954,
1296 0x5955,
1297 0x5974,
1298 0x5975,
1299 0x5960,
1300 0x5961,
1301 0x5962,
1302 0x5964,
1303 0x5965,
1304 0x5969,
1305 0x5a41,
1306 0x5a42,
1307 0x5a61,
1308 0x5a62,
1309 0x5b60,
1310 0x5b62,
1311 0x5b63,
1312 0x5b64,
1313 0x5b65,
1314 0x5c61,
1315 0x5c63,
1316 0x5d48,
1317 0x5d49,
1318 0x5d4a,
1319 0x5d4c,
1320 0x5d4d,
1321 0x5d4e,
1322 0x5d4f,
1323 0x5d50,
1324 0x5d52,
1325 0x5d57,
1326 0x5e48,
1327 0x5e4a,
1328 0x5e4b,
1329 0x5e4c,
1330 0x5e4d,
1331 0x5e4f,
1332 0x6700,
1333 0x6701,
1334 0x6702,
1335 0x6703,
1336 0x6704,
1337 0x6705,
1338 0x6706,
1339 0x6707,
1340 0x6708,
1341 0x6709,
1342 0x6718,
1343 0x6719,
1344 0x671c,
1345 0x671d,
1346 0x671f,
1347 0x6720,
1348 0x6721,
1349 0x6722,
1350 0x6723,
1351 0x6724,
1352 0x6725,
1353 0x6726,
1354 0x6727,
1355 0x6728,
1356 0x6729,
1357 0x6738,
1358 0x6739,
1359 0x673e,
1360 0x6740,
1361 0x6741,
1362 0x6742,
1363 0x6743,
1364 0x6744,
1365 0x6745,
1366 0x6746,
1367 0x6747,
1368 0x6748,
1369 0x6749,
1370 0x674A,
1371 0x6750,
1372 0x6751,
1373 0x6758,
1374 0x6759,
1375 0x675B,
1376 0x675D,
1377 0x675F,
1378 0x6760,
1379 0x6761,
1380 0x6762,
1381 0x6763,
1382 0x6764,
1383 0x6765,
1384 0x6766,
1385 0x6767,
1386 0x6768,
1387 0x6770,
1388 0x6771,
1389 0x6772,
1390 0x6778,
1391 0x6779,
1392 0x677B,
1393 0x6840,
1394 0x6841,
1395 0x6842,
1396 0x6843,
1397 0x6849,
1398 0x684C,
1399 0x6850,
1400 0x6858,
1401 0x6859,
1402 0x6880,
1403 0x6888,
1404 0x6889,
1405 0x688A,
1406 0x688C,
1407 0x688D,
1408 0x6898,
1409 0x6899,
1410 0x689b,
1411 0x689c,
1412 0x689d,
1413 0x689e,
1414 0x68a0,
1415 0x68a1,
1416 0x68a8,
1417 0x68a9,
1418 0x68b0,
1419 0x68b8,
1420 0x68b9,
1421 0x68ba,
1422 0x68be,
1423 0x68bf,
1424 0x68c0,
1425 0x68c1,
1426 0x68c7,
1427 0x68c8,
1428 0x68c9,
1429 0x68d8,
1430 0x68d9,
1431 0x68da,
1432 0x68de,
1433 0x68e0,
1434 0x68e1,
1435 0x68e4,
1436 0x68e5,
1437 0x68e8,
1438 0x68e9,
1439 0x68f1,
1440 0x68f2,
1441 0x68f8,
1442 0x68f9,
1443 0x68fa,
1444 0x68fe,
1445 0x7100,
1446 0x7101,
1447 0x7102,
1448 0x7103,
1449 0x7104,
1450 0x7105,
1451 0x7106,
1452 0x7108,
1453 0x7109,
1454 0x710A,
1455 0x710B,
1456 0x710C,
1457 0x710E,
1458 0x710F,
1459 0x7140,
1460 0x7141,
1461 0x7142,
1462 0x7143,
1463 0x7144,
1464 0x7145,
1465 0x7146,
1466 0x7147,
1467 0x7149,
1468 0x714A,
1469 0x714B,
1470 0x714C,
1471 0x714D,
1472 0x714E,
1473 0x714F,
1474 0x7151,
1475 0x7152,
1476 0x7153,
1477 0x715E,
1478 0x715F,
1479 0x7180,
1480 0x7181,
1481 0x7183,
1482 0x7186,
1483 0x7187,
1484 0x7188,
1485 0x718A,
1486 0x718B,
1487 0x718C,
1488 0x718D,
1489 0x718F,
1490 0x7193,
1491 0x7196,
1492 0x719B,
1493 0x719F,
1494 0x71C0,
1495 0x71C1,
1496 0x71C2,
1497 0x71C3,
1498 0x71C4,
1499 0x71C5,
1500 0x71C6,
1501 0x71C7,
1502 0x71CD,
1503 0x71CE,
1504 0x71D2,
1505 0x71D4,
1506 0x71D5,
1507 0x71D6,
1508 0x71DA,
1509 0x71DE,
1510 0x7200,
1511 0x7210,
1512 0x7211,
1513 0x7240,
1514 0x7243,
1515 0x7244,
1516 0x7245,
1517 0x7246,
1518 0x7247,
1519 0x7248,
1520 0x7249,
1521 0x724A,
1522 0x724B,
1523 0x724C,
1524 0x724D,
1525 0x724E,
1526 0x724F,
1527 0x7280,
1528 0x7281,
1529 0x7283,
1530 0x7284,
1531 0x7287,
1532 0x7288,
1533 0x7289,
1534 0x728B,
1535 0x728C,
1536 0x7290,
1537 0x7291,
1538 0x7293,
1539 0x7297,
1540 0x7834,
1541 0x7835,
1542 0x791e,
1543 0x791f,
1544 0x793f,
1545 0x7941,
1546 0x7942,
1547 0x796c,
1548 0x796d,
1549 0x796e,
1550 0x796f,
1551 0x9400,
1552 0x9401,
1553 0x9402,
1554 0x9403,
1555 0x9405,
1556 0x940A,
1557 0x940B,
1558 0x940F,
1559 0x94A0,
1560 0x94A1,
1561 0x94A3,
1562 0x94B1,
1563 0x94B3,
1564 0x94B4,
1565 0x94B5,
1566 0x94B9,
1567 0x9440,
1568 0x9441,
1569 0x9442,
1570 0x9443,
1571 0x9444,
1572 0x9446,
1573 0x944A,
1574 0x944B,
1575 0x944C,
1576 0x944E,
1577 0x9450,
1578 0x9452,
1579 0x9456,
1580 0x945A,
1581 0x945B,
1582 0x945E,
1583 0x9460,
1584 0x9462,
1585 0x946A,
1586 0x946B,
1587 0x947A,
1588 0x947B,
1589 0x9480,
1590 0x9487,
1591 0x9488,
1592 0x9489,
1593 0x948A,
1594 0x948F,
1595 0x9490,
1596 0x9491,
1597 0x9495,
1598 0x9498,
1599 0x949C,
1600 0x949E,
1601 0x949F,
1602 0x94C0,
1603 0x94C1,
1604 0x94C3,
1605 0x94C4,
1606 0x94C5,
1607 0x94C6,
1608 0x94C7,
1609 0x94C8,
1610 0x94C9,
1611 0x94CB,
1612 0x94CC,
1613 0x94CD,
1614 0x9500,
1615 0x9501,
1616 0x9504,
1617 0x9505,
1618 0x9506,
1619 0x9507,
1620 0x9508,
1621 0x9509,
1622 0x950F,
1623 0x9511,
1624 0x9515,
1625 0x9517,
1626 0x9519,
1627 0x9540,
1628 0x9541,
1629 0x9542,
1630 0x954E,
1631 0x954F,
1632 0x9552,
1633 0x9553,
1634 0x9555,
1635 0x9557,
1636 0x955f,
1637 0x9580,
1638 0x9581,
1639 0x9583,
1640 0x9586,
1641 0x9587,
1642 0x9588,
1643 0x9589,
1644 0x958A,
1645 0x958B,
1646 0x958C,
1647 0x958D,
1648 0x958E,
1649 0x958F,
1650 0x9590,
1651 0x9591,
1652 0x9593,
1653 0x9595,
1654 0x9596,
1655 0x9597,
1656 0x9598,
1657 0x9599,
1658 0x959B,
1659 0x95C0,
1660 0x95C2,
1661 0x95C4,
1662 0x95C5,
1663 0x95C6,
1664 0x95C7,
1665 0x95C9,
1666 0x95CC,
1667 0x95CD,
1668 0x95CE,
1669 0x95CF,
1670 0x9610,
1671 0x9611,
1672 0x9612,
1673 0x9613,
1674 0x9614,
1675 0x9615,
1676 0x9616,
1677 0x9640,
1678 0x9641,
1679 0x9642,
1680 0x9643,
1681 0x9644,
1682 0x9645,
1683 0x9647,
1684 0x9648,
1685 0x9649,
1686 0x964a,
1687 0x964b,
1688 0x964c,
1689 0x964e,
1690 0x964f,
1691 0x9710,
1692 0x9711,
1693 0x9712,
1694 0x9713,
1695 0x9714,
1696 0x9715,
1697 0x9802,
1698 0x9803,
1699 0x9804,
1700 0x9805,
1701 0x9806,
1702 0x9807,
1703 0x9808,
1704 0x9809,
1705 0x980A,
1706 0x9900,
1707 0x9901,
1708 0x9903,
1709 0x9904,
1710 0x9905,
1711 0x9906,
1712 0x9907,
1713 0x9908,
1714 0x9909,
1715 0x990A,
1716 0x990B,
1717 0x990C,
1718 0x990D,
1719 0x990E,
1720 0x990F,
1721 0x9910,
1722 0x9913,
1723 0x9917,
1724 0x9918,
1725 0x9919,
1726 0x9990,
1727 0x9991,
1728 0x9992,
1729 0x9993,
1730 0x9994,
1731 0x9995,
1732 0x9996,
1733 0x9997,
1734 0x9998,
1735 0x9999,
1736 0x999A,
1737 0x999B,
1738 0x999C,
1739 0x999D,
1740 0x99A0,
1741 0x99A2,
1742 0x99A4,
1743 /* radeon secondary ids */
1744 0x3171,
1745 0x3e70,
1746 0x4164,
1747 0x4165,
1748 0x4166,
1749 0x4168,
1750 0x4170,
1751 0x4171,
1752 0x4172,
1753 0x4173,
1754 0x496e,
1755 0x4a69,
1756 0x4a6a,
1757 0x4a6b,
1758 0x4a70,
1759 0x4a74,
1760 0x4b69,
1761 0x4b6b,
1762 0x4b6c,
1763 0x4c6e,
1764 0x4e64,
1765 0x4e65,
1766 0x4e66,
1767 0x4e67,
1768 0x4e68,
1769 0x4e69,
1770 0x4e6a,
1771 0x4e71,
1772 0x4f73,
1773 0x5569,
1774 0x556b,
1775 0x556d,
1776 0x556f,
1777 0x5571,
1778 0x5854,
1779 0x5874,
1780 0x5940,
1781 0x5941,
1782 0x5b70,
1783 0x5b72,
1784 0x5b73,
1785 0x5b74,
1786 0x5b75,
1787 0x5d44,
1788 0x5d45,
1789 0x5d6d,
1790 0x5d6f,
1791 0x5d72,
1792 0x5d77,
1793 0x5e6b,
1794 0x5e6d,
1795 0x7120,
1796 0x7124,
1797 0x7129,
1798 0x712e,
1799 0x712f,
1800 0x7162,
1801 0x7163,
1802 0x7166,
1803 0x7167,
1804 0x7172,
1805 0x7173,
1806 0x71a0,
1807 0x71a1,
1808 0x71a3,
1809 0x71a7,
1810 0x71bb,
1811 0x71e0,
1812 0x71e1,
1813 0x71e2,
1814 0x71e6,
1815 0x71e7,
1816 0x71f2,
1817 0x7269,
1818 0x726b,
1819 0x726e,
1820 0x72a0,
1821 0x72a8,
1822 0x72b1,
1823 0x72b3,
1824 0x793f,
1825 };
1826
1827 static const struct pci_device_id pciidlist[] = {
1828 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1829 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1830 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1831 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1832 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1833 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1834 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1835 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1836 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1837 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1838 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1839 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1840 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1841 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1842 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1843 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1844 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1845 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1846 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1847 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1848 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1849 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1850 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1851 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1852 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1853 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1854 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1855 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1856 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1857 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1858 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1859 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1860 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1861 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1862 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1863 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1864 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1865 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1866 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1867 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1868 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1869 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1870 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1871 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1872 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1873 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1874 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1875 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1876 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1877 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1878 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1879 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1880 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1881 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1882 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1883 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1884 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1885 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1886 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1887 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1888 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1889 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1890 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1891 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1892 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1893 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1894 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1895 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1896 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1897 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1898 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1899 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1900 /* Kaveri */
1901 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1902 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1903 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1904 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1905 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1906 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1907 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1908 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1909 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1910 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1911 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1912 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1913 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1914 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1915 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1916 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1917 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1918 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1919 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1920 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1921 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1922 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1923 /* Bonaire */
1924 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1925 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1926 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1927 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1928 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1929 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1930 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1931 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1932 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1933 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1934 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1935 /* Hawaii */
1936 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1937 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1938 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1939 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1940 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1941 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1942 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1943 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1944 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1945 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1946 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1947 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1948 /* Kabini */
1949 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1950 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1951 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1952 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1953 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1954 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1955 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1956 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1957 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1958 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1959 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1960 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1961 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1962 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1963 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1964 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1965 /* mullins */
1966 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1967 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1968 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1969 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1970 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1971 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1972 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1973 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1974 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1975 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1976 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1977 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1978 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1979 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1980 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1981 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1982 /* topaz */
1983 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1984 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1985 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1986 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1987 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1988 /* tonga */
1989 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1990 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1991 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1992 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1993 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1994 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1995 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1996 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1997 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1998 /* fiji */
1999 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
2000 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
2001 /* carrizo */
2002 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
2003 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
2004 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
2005 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
2006 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
2007 /* stoney */
2008 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
2009 /* Polaris11 */
2010 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2011 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2012 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2013 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2014 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2015 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2016 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2017 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2018 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2019 /* Polaris10 */
2020 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2021 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2022 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2023 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2024 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2025 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2026 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2027 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2028 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2029 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2030 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2031 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2032 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2033 /* Polaris12 */
2034 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2035 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2036 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2037 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2038 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2039 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2040 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2041 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2042 /* VEGAM */
2043 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
2044 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
2045 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
2046 /* Vega 10 */
2047 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2048 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2049 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2050 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2051 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2052 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2053 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2054 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2055 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2056 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2057 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2058 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2059 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2060 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2061 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2062 /* Vega 12 */
2063 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
2064 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
2065 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
2066 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
2067 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
2068 /* Vega 20 */
2069 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
2070 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
2071 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
2072 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
2073 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
2074 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
2075 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
2076 /* Raven */
2077 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
2078 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
2079 /* Arcturus */
2080 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
2081 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
2082 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
2083 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
2084 /* Navi10 */
2085 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2086 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2087 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2088 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2089 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2090 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2091 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2092 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2093 /* Navi14 */
2094 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
2095 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
2096 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
2097 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
2098
2099 /* Renoir */
2100 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
2101 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
2102 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
2103 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
2104
2105 /* Navi12 */
2106 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
2107 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
2108
2109 /* Sienna_Cichlid */
2110 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2111 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2112 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2113 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2114 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2115 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2116 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2117 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2118 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2119 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2120 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2121 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2122 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2123
2124 /* Yellow Carp */
2125 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
2126 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
2127
2128 /* Navy_Flounder */
2129 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2130 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2131 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2132 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2133 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2134 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2135 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2136 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2137 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2138
2139 /* DIMGREY_CAVEFISH */
2140 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2141 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2142 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2143 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2144 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2145 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2146 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2147 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2148 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2149 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2150 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2151 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2152
2153 /* Aldebaran */
2154 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2155 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2156 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2157 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2158
2159 /* CYAN_SKILLFISH */
2160 {0x1002, 0x13DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2161 {0x1002, 0x13F9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2162 {0x1002, 0x13FA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2163 {0x1002, 0x13FB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2164 {0x1002, 0x13FC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2165 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2166 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2167
2168 /* BEIGE_GOBY */
2169 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2170 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2171 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2172 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2173 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2174 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2175
2176 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2177 .class = PCI_CLASS_DISPLAY_VGA << 8,
2178 .class_mask = 0xffffff,
2179 .driver_data = CHIP_IP_DISCOVERY },
2180
2181 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2182 .class = PCI_CLASS_DISPLAY_OTHER << 8,
2183 .class_mask = 0xffffff,
2184 .driver_data = CHIP_IP_DISCOVERY },
2185
2186 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2187 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8,
2188 .class_mask = 0xffffff,
2189 .driver_data = CHIP_IP_DISCOVERY },
2190
2191 {0, 0, 0}
2192 };
2193
2194 MODULE_DEVICE_TABLE(pci, pciidlist);
2195
2196 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = {
2197 /* differentiate between P10 and P11 asics with the same DID */
2198 {0x67FF, 0xE3, CHIP_POLARIS10},
2199 {0x67FF, 0xE7, CHIP_POLARIS10},
2200 {0x67FF, 0xF3, CHIP_POLARIS10},
2201 {0x67FF, 0xF7, CHIP_POLARIS10},
2202 };
2203
2204 static const struct drm_driver amdgpu_kms_driver;
2205
amdgpu_get_secondary_funcs(struct amdgpu_device * adev)2206 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
2207 {
2208 struct pci_dev *p = NULL;
2209 int i;
2210
2211 /* 0 - GPU
2212 * 1 - audio
2213 * 2 - USB
2214 * 3 - UCSI
2215 */
2216 for (i = 1; i < 4; i++) {
2217 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
2218 adev->pdev->bus->number, i);
2219 if (p) {
2220 pm_runtime_get_sync(&p->dev);
2221 pm_runtime_put_autosuspend(&p->dev);
2222 pci_dev_put(p);
2223 }
2224 }
2225 }
2226
amdgpu_init_debug_options(struct amdgpu_device * adev)2227 static void amdgpu_init_debug_options(struct amdgpu_device *adev)
2228 {
2229 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) {
2230 pr_info("debug: VM handling debug enabled\n");
2231 adev->debug_vm = true;
2232 }
2233
2234 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) {
2235 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n");
2236 adev->debug_largebar = true;
2237 }
2238
2239 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) {
2240 pr_info("debug: soft reset for GPU recovery disabled\n");
2241 adev->debug_disable_soft_recovery = true;
2242 }
2243
2244 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) {
2245 pr_info("debug: place fw in vram for frontdoor loading\n");
2246 adev->debug_use_vram_fw_buf = true;
2247 }
2248
2249 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) {
2250 pr_info("debug: enable RAS ACA\n");
2251 adev->debug_enable_ras_aca = true;
2252 }
2253
2254 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) {
2255 pr_info("debug: enable experimental reset features\n");
2256 adev->debug_exp_resets = true;
2257 }
2258
2259 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_RING_RESET) {
2260 pr_info("debug: ring reset disabled\n");
2261 adev->debug_disable_gpu_ring_reset = true;
2262 }
2263 if (amdgpu_debug_mask & AMDGPU_DEBUG_SMU_POOL) {
2264 pr_info("debug: use vram for smu pool\n");
2265 adev->pm.smu_debug_mask |= SMU_DEBUG_POOL_USE_VRAM;
2266 }
2267 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM_USERPTR) {
2268 pr_info("debug: VM mode debug for userptr is enabled\n");
2269 adev->debug_vm_userptr = true;
2270 }
2271
2272 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_RAS_CE_LOG) {
2273 pr_info("debug: disable kernel logs of correctable errors\n");
2274 adev->debug_disable_ce_logs = true;
2275 }
2276
2277 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_CE_CS) {
2278 pr_info("debug: allowing command submission to CE engine\n");
2279 adev->debug_enable_ce_cs = true;
2280 }
2281 }
2282
amdgpu_fix_asic_type(struct pci_dev * pdev,unsigned long flags)2283 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags)
2284 {
2285 int i;
2286
2287 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) {
2288 if (pdev->device == asic_type_quirks[i].device &&
2289 pdev->revision == asic_type_quirks[i].revision) {
2290 flags &= ~AMD_ASIC_MASK;
2291 flags |= asic_type_quirks[i].type;
2292 break;
2293 }
2294 }
2295
2296 return flags;
2297 }
2298
amdgpu_support_enabled(struct device * dev,const enum amd_asic_type family)2299 static bool amdgpu_support_enabled(struct device *dev,
2300 const enum amd_asic_type family)
2301 {
2302 const char *gen;
2303 const char *param;
2304 int module_param = -1;
2305 bool radeon_support_built = IS_ENABLED(CONFIG_DRM_RADEON);
2306 bool amdgpu_support_built = false;
2307 bool support_by_default = false;
2308
2309 switch (family) {
2310 case CHIP_TAHITI:
2311 case CHIP_PITCAIRN:
2312 case CHIP_VERDE:
2313 case CHIP_OLAND:
2314 case CHIP_HAINAN:
2315 gen = "SI";
2316 param = "si_support";
2317 module_param = amdgpu_si_support;
2318 amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_SI);
2319 support_by_default = true;
2320 break;
2321
2322 case CHIP_BONAIRE:
2323 case CHIP_HAWAII:
2324 case CHIP_KAVERI:
2325 case CHIP_KABINI:
2326 case CHIP_MULLINS:
2327 gen = "CIK";
2328 param = "cik_support";
2329 module_param = amdgpu_cik_support;
2330 amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_CIK);
2331 support_by_default = true;
2332 break;
2333
2334 default:
2335 /* All other chips are supported by amdgpu only */
2336 return true;
2337 }
2338
2339 if (!amdgpu_support_built) {
2340 dev_info(dev, "amdgpu built without %s support\n", gen);
2341 return false;
2342 }
2343
2344 if ((module_param == -1 && (support_by_default || !radeon_support_built)) ||
2345 module_param == 1) {
2346 if (radeon_support_built)
2347 dev_info(dev, "%s support provided by amdgpu.\n"
2348 "Use radeon.%s=1 amdgpu.%s=0 to override.\n",
2349 gen, param, param);
2350
2351 return true;
2352 }
2353
2354 if (radeon_support_built)
2355 dev_info(dev, "%s support provided by radeon.\n"
2356 "Use radeon.%s=0 amdgpu.%s=1 to override.\n",
2357 gen, param, param);
2358 else if (module_param == 0)
2359 dev_info(dev, "%s support disabled by module param\n", gen);
2360
2361 return false;
2362 }
2363
amdgpu_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)2364 static int amdgpu_pci_probe(struct pci_dev *pdev,
2365 const struct pci_device_id *ent)
2366 {
2367 struct drm_device *ddev;
2368 struct amdgpu_device *adev;
2369 unsigned long flags = ent->driver_data;
2370 int ret, retry = 0, i;
2371 bool supports_atomic = false;
2372
2373 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA ||
2374 (pdev->class >> 8) == PCI_CLASS_DISPLAY_OTHER) {
2375 if (drm_firmware_drivers_only() && amdgpu_modeset == -1)
2376 return -EINVAL;
2377 }
2378
2379 /* skip devices which are owned by radeon */
2380 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
2381 if (amdgpu_unsupported_pciidlist[i] == pdev->device)
2382 return -ENODEV;
2383 }
2384
2385 if (amdgpu_virtual_display ||
2386 amdgpu_device_asic_has_dc_support(pdev, flags & AMD_ASIC_MASK))
2387 supports_atomic = true;
2388
2389 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
2390 dev_info(&pdev->dev, "This hardware requires experimental hardware support.\n"
2391 "See modparam exp_hw_support\n");
2392 return -ENODEV;
2393 }
2394
2395 flags = amdgpu_fix_asic_type(pdev, flags);
2396
2397 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
2398 * however, SME requires an indirect IOMMU mapping because the encryption
2399 * bit is beyond the DMA mask of the chip.
2400 */
2401 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
2402 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
2403 dev_info(&pdev->dev,
2404 "SME is not compatible with RAVEN\n");
2405 return -ENOTSUPP;
2406 }
2407
2408 if (!amdgpu_support_enabled(&pdev->dev, flags & AMD_ASIC_MASK))
2409 return -ENODEV;
2410
2411 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
2412 if (IS_ERR(adev))
2413 return PTR_ERR(adev);
2414
2415 adev->dev = &pdev->dev;
2416 adev->pdev = pdev;
2417 ddev = adev_to_drm(adev);
2418
2419 if (!supports_atomic)
2420 ddev->driver_features &= ~DRIVER_ATOMIC;
2421
2422 ret = pci_enable_device(pdev);
2423 if (ret)
2424 return ret;
2425
2426 pci_set_drvdata(pdev, ddev);
2427
2428 amdgpu_init_debug_options(adev);
2429
2430 ret = amdgpu_driver_load_kms(adev, flags);
2431 if (ret)
2432 goto err_pci;
2433
2434 retry_init:
2435 ret = drm_dev_register(ddev, flags);
2436 if (ret == -EAGAIN && ++retry <= 3) {
2437 drm_info(adev_to_drm(adev), "retry init %d\n", retry);
2438 /* Don't request EX mode too frequently which is attacking */
2439 msleep(5000);
2440 goto retry_init;
2441 } else if (ret) {
2442 goto err_pci;
2443 }
2444
2445 ret = amdgpu_xcp_dev_register(adev, ent);
2446 if (ret)
2447 goto err_pci;
2448
2449 ret = amdgpu_amdkfd_drm_client_create(adev);
2450 if (ret)
2451 goto err_pci;
2452
2453 /*
2454 * 1. don't init fbdev on hw without DCE
2455 * 2. don't init fbdev if there are no connectors
2456 */
2457 if (adev->mode_info.mode_config_initialized &&
2458 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
2459 const struct drm_format_info *format;
2460
2461 /* select 8 bpp console on low vram cards */
2462 if (adev->gmc.real_vram_size <= (32*1024*1024))
2463 format = drm_format_info(DRM_FORMAT_C8);
2464 else
2465 format = NULL;
2466
2467 drm_client_setup(adev_to_drm(adev), format);
2468 }
2469
2470 ret = amdgpu_debugfs_init(adev);
2471 if (ret)
2472 DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
2473
2474 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2475 /* only need to skip on ATPX */
2476 if (amdgpu_device_supports_px(adev))
2477 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
2478 /* we want direct complete for BOCO */
2479 if (amdgpu_device_supports_boco(adev))
2480 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE |
2481 DPM_FLAG_SMART_SUSPEND |
2482 DPM_FLAG_MAY_SKIP_RESUME);
2483 pm_runtime_use_autosuspend(ddev->dev);
2484 pm_runtime_set_autosuspend_delay(ddev->dev, 5000);
2485
2486 pm_runtime_allow(ddev->dev);
2487
2488 pm_runtime_put_autosuspend(ddev->dev);
2489
2490 pci_wake_from_d3(pdev, TRUE);
2491
2492 /*
2493 * For runpm implemented via BACO, PMFW will handle the
2494 * timing for BACO in and out:
2495 * - put ASIC into BACO state only when both video and
2496 * audio functions are in D3 state.
2497 * - pull ASIC out of BACO state when either video or
2498 * audio function is in D0 state.
2499 * Also, at startup, PMFW assumes both functions are in
2500 * D0 state.
2501 *
2502 * So if snd driver was loaded prior to amdgpu driver
2503 * and audio function was put into D3 state, there will
2504 * be no PMFW-aware D-state transition(D0->D3) on runpm
2505 * suspend. Thus the BACO will be not correctly kicked in.
2506 *
2507 * Via amdgpu_get_secondary_funcs(), the audio dev is put
2508 * into D0 state. Then there will be a PMFW-aware D-state
2509 * transition(D0->D3) on runpm suspend.
2510 */
2511 if (amdgpu_device_supports_baco(adev) &&
2512 !(adev->flags & AMD_IS_APU) &&
2513 adev->asic_type >= CHIP_NAVI10)
2514 amdgpu_get_secondary_funcs(adev);
2515 }
2516
2517 return 0;
2518
2519 err_pci:
2520 pci_disable_device(pdev);
2521 return ret;
2522 }
2523
2524 static void
amdgpu_pci_remove(struct pci_dev * pdev)2525 amdgpu_pci_remove(struct pci_dev *pdev)
2526 {
2527 struct drm_device *dev = pci_get_drvdata(pdev);
2528 struct amdgpu_device *adev = drm_to_adev(dev);
2529
2530 amdgpu_ras_eeprom_check_and_recover(adev);
2531 amdgpu_xcp_dev_unplug(adev);
2532 amdgpu_gmc_prepare_nps_mode_change(adev);
2533 drm_dev_unplug(dev);
2534
2535 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2536 pm_runtime_get_sync(dev->dev);
2537 pm_runtime_forbid(dev->dev);
2538 }
2539
2540 amdgpu_driver_unload_kms(dev);
2541
2542 /*
2543 * Flush any in flight DMA operations from device.
2544 * Clear the Bus Master Enable bit and then wait on the PCIe Device
2545 * StatusTransactions Pending bit.
2546 */
2547 pci_disable_device(pdev);
2548 pci_wait_for_pending_transaction(pdev);
2549 }
2550
2551 static void
amdgpu_pci_shutdown(struct pci_dev * pdev)2552 amdgpu_pci_shutdown(struct pci_dev *pdev)
2553 {
2554 struct drm_device *dev = pci_get_drvdata(pdev);
2555 struct amdgpu_device *adev = drm_to_adev(dev);
2556
2557 if (amdgpu_ras_intr_triggered())
2558 return;
2559
2560 /* device maybe not resumed here, return immediately in this case */
2561 if (adev->in_s4 && adev->in_suspend)
2562 return;
2563
2564 /* if we are running in a VM, make sure the device
2565 * torn down properly on reboot/shutdown.
2566 * unfortunately we can't detect certain
2567 * hypervisors so just do this all the time.
2568 */
2569 if (!amdgpu_passthrough(adev))
2570 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2571 amdgpu_device_prepare(dev);
2572 amdgpu_device_suspend(dev, true);
2573 adev->mp1_state = PP_MP1_STATE_NONE;
2574 }
2575
amdgpu_pmops_prepare(struct device * dev)2576 static int amdgpu_pmops_prepare(struct device *dev)
2577 {
2578 struct drm_device *drm_dev = dev_get_drvdata(dev);
2579 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2580
2581 /* device maybe not resumed here, return immediately in this case */
2582 if (adev->in_s4 && adev->in_suspend)
2583 return 0;
2584
2585 /* Return a positive number here so
2586 * DPM_FLAG_SMART_SUSPEND works properly
2587 */
2588 if (amdgpu_device_supports_boco(adev) && pm_runtime_suspended(dev))
2589 return 1;
2590
2591 /* if we will not support s3 or s2i for the device
2592 * then skip suspend
2593 */
2594 if (!amdgpu_acpi_is_s0ix_active(adev) &&
2595 !amdgpu_acpi_is_s3_active(adev))
2596 return 1;
2597
2598 return amdgpu_device_prepare(drm_dev);
2599 }
2600
amdgpu_pmops_complete(struct device * dev)2601 static void amdgpu_pmops_complete(struct device *dev)
2602 {
2603 amdgpu_device_complete(dev_get_drvdata(dev));
2604 }
2605
amdgpu_pmops_suspend(struct device * dev)2606 static int amdgpu_pmops_suspend(struct device *dev)
2607 {
2608 struct drm_device *drm_dev = dev_get_drvdata(dev);
2609 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2610
2611 if (amdgpu_acpi_is_s0ix_active(adev))
2612 adev->in_s0ix = true;
2613 else if (amdgpu_acpi_is_s3_active(adev))
2614 adev->in_s3 = true;
2615 if (!adev->in_s0ix && !adev->in_s3) {
2616 #if IS_ENABLED(CONFIG_SUSPEND)
2617 /* don't allow going deep first time followed by s2idle the next time */
2618 if (adev->last_suspend_state != PM_SUSPEND_ON &&
2619 adev->last_suspend_state != pm_suspend_target_state) {
2620 drm_err_once(drm_dev, "Unsupported suspend state %d\n",
2621 pm_suspend_target_state);
2622 return -EINVAL;
2623 }
2624 #endif
2625 return 0;
2626 }
2627
2628 #if IS_ENABLED(CONFIG_SUSPEND)
2629 /* cache the state last used for suspend */
2630 adev->last_suspend_state = pm_suspend_target_state;
2631 #endif
2632
2633 return amdgpu_device_suspend(drm_dev, true);
2634 }
2635
amdgpu_pmops_suspend_noirq(struct device * dev)2636 static int amdgpu_pmops_suspend_noirq(struct device *dev)
2637 {
2638 struct drm_device *drm_dev = dev_get_drvdata(dev);
2639 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2640 int r;
2641
2642 if (amdgpu_acpi_should_gpu_reset(adev)) {
2643 amdgpu_device_lock_reset_domain(adev->reset_domain);
2644 r = amdgpu_asic_reset(adev);
2645 amdgpu_device_unlock_reset_domain(adev->reset_domain);
2646 return r;
2647 }
2648
2649 return 0;
2650 }
2651
amdgpu_pmops_resume(struct device * dev)2652 static int amdgpu_pmops_resume(struct device *dev)
2653 {
2654 struct drm_device *drm_dev = dev_get_drvdata(dev);
2655 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2656 int r;
2657
2658 if (!adev->in_s0ix && !adev->in_s3)
2659 return 0;
2660
2661 /* Avoids registers access if device is physically gone */
2662 if (!pci_device_is_present(adev->pdev))
2663 adev->no_hw_access = true;
2664
2665 r = amdgpu_device_resume(drm_dev, true);
2666 if (amdgpu_acpi_is_s0ix_active(adev))
2667 adev->in_s0ix = false;
2668 else
2669 adev->in_s3 = false;
2670 return r;
2671 }
2672
amdgpu_pmops_freeze(struct device * dev)2673 static int amdgpu_pmops_freeze(struct device *dev)
2674 {
2675 struct drm_device *drm_dev = dev_get_drvdata(dev);
2676 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2677 int r;
2678
2679 r = amdgpu_device_suspend(drm_dev, true);
2680 if (r)
2681 return r;
2682
2683 if (amdgpu_acpi_should_gpu_reset(adev)) {
2684 amdgpu_device_lock_reset_domain(adev->reset_domain);
2685 r = amdgpu_asic_reset(adev);
2686 amdgpu_device_unlock_reset_domain(adev->reset_domain);
2687 return r;
2688 }
2689 return 0;
2690 }
2691
amdgpu_pmops_thaw(struct device * dev)2692 static int amdgpu_pmops_thaw(struct device *dev)
2693 {
2694 struct drm_device *drm_dev = dev_get_drvdata(dev);
2695
2696 /* do not resume device if it's normal hibernation */
2697 if (console_suspend_enabled &&
2698 !pm_hibernate_is_recovering() &&
2699 !pm_hibernation_mode_is_suspend())
2700 return 0;
2701
2702 return amdgpu_device_resume(drm_dev, true);
2703 }
2704
amdgpu_pmops_poweroff(struct device * dev)2705 static int amdgpu_pmops_poweroff(struct device *dev)
2706 {
2707 struct drm_device *drm_dev = dev_get_drvdata(dev);
2708 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2709
2710 /* device maybe not resumed here, return immediately in this case */
2711 if (adev->in_s4 && adev->in_suspend)
2712 return 0;
2713
2714 return amdgpu_device_suspend(drm_dev, true);
2715 }
2716
amdgpu_pmops_restore(struct device * dev)2717 static int amdgpu_pmops_restore(struct device *dev)
2718 {
2719 struct drm_device *drm_dev = dev_get_drvdata(dev);
2720
2721 return amdgpu_device_resume(drm_dev, true);
2722 }
2723
amdgpu_runtime_idle_check_display(struct device * dev)2724 static int amdgpu_runtime_idle_check_display(struct device *dev)
2725 {
2726 struct pci_dev *pdev = to_pci_dev(dev);
2727 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2728 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2729
2730 if (adev->mode_info.num_crtc) {
2731 struct drm_connector *list_connector;
2732 struct drm_connector_list_iter iter;
2733 int ret = 0;
2734
2735 if (amdgpu_runtime_pm != -2) {
2736 /* XXX: Return busy if any displays are connected to avoid
2737 * possible display wakeups after runtime resume due to
2738 * hotplug events in case any displays were connected while
2739 * the GPU was in suspend. Remove this once that is fixed.
2740 */
2741 mutex_lock(&drm_dev->mode_config.mutex);
2742 drm_connector_list_iter_begin(drm_dev, &iter);
2743 drm_for_each_connector_iter(list_connector, &iter) {
2744 if (list_connector->status == connector_status_connected) {
2745 ret = -EBUSY;
2746 break;
2747 }
2748 }
2749 drm_connector_list_iter_end(&iter);
2750 mutex_unlock(&drm_dev->mode_config.mutex);
2751
2752 if (ret)
2753 return ret;
2754 }
2755
2756 if (adev->dc_enabled) {
2757 struct drm_crtc *crtc;
2758
2759 drm_for_each_crtc(crtc, drm_dev) {
2760 drm_modeset_lock(&crtc->mutex, NULL);
2761 if (crtc->state->active)
2762 ret = -EBUSY;
2763 drm_modeset_unlock(&crtc->mutex);
2764 if (ret < 0)
2765 break;
2766 }
2767 } else {
2768 mutex_lock(&drm_dev->mode_config.mutex);
2769 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2770
2771 drm_connector_list_iter_begin(drm_dev, &iter);
2772 drm_for_each_connector_iter(list_connector, &iter) {
2773 if (list_connector->dpms == DRM_MODE_DPMS_ON) {
2774 ret = -EBUSY;
2775 break;
2776 }
2777 }
2778
2779 drm_connector_list_iter_end(&iter);
2780
2781 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2782 mutex_unlock(&drm_dev->mode_config.mutex);
2783 }
2784 if (ret)
2785 return ret;
2786 }
2787
2788 return 0;
2789 }
2790
amdgpu_runtime_idle_check_userq(struct device * dev)2791 static int amdgpu_runtime_idle_check_userq(struct device *dev)
2792 {
2793 struct pci_dev *pdev = to_pci_dev(dev);
2794 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2795 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2796
2797 return xa_empty(&adev->userq_doorbell_xa) ? 0 : -EBUSY;
2798 }
2799
amdgpu_pmops_runtime_suspend(struct device * dev)2800 static int amdgpu_pmops_runtime_suspend(struct device *dev)
2801 {
2802 struct pci_dev *pdev = to_pci_dev(dev);
2803 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2804 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2805 int ret, i;
2806
2807 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2808 pm_runtime_forbid(dev);
2809 return -EBUSY;
2810 }
2811
2812 ret = amdgpu_runtime_idle_check_display(dev);
2813 if (ret)
2814 return ret;
2815 ret = amdgpu_runtime_idle_check_userq(dev);
2816 if (ret)
2817 return ret;
2818
2819 /* wait for all rings to drain before suspending */
2820 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2821 struct amdgpu_ring *ring = adev->rings[i];
2822
2823 if (ring && ring->sched.ready) {
2824 ret = amdgpu_fence_wait_empty(ring);
2825 if (ret)
2826 return -EBUSY;
2827 }
2828 }
2829
2830 adev->in_runpm = true;
2831 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)
2832 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2833
2834 /*
2835 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
2836 * proper cleanups and put itself into a state ready for PNP. That
2837 * can address some random resuming failure observed on BOCO capable
2838 * platforms.
2839 * TODO: this may be also needed for PX capable platform.
2840 */
2841 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)
2842 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2843
2844 ret = amdgpu_device_prepare(drm_dev);
2845 if (ret)
2846 return ret;
2847 ret = amdgpu_device_suspend(drm_dev, false);
2848 if (ret) {
2849 adev->in_runpm = false;
2850 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)
2851 adev->mp1_state = PP_MP1_STATE_NONE;
2852 return ret;
2853 }
2854
2855 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)
2856 adev->mp1_state = PP_MP1_STATE_NONE;
2857
2858 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) {
2859 /* Only need to handle PCI state in the driver for ATPX
2860 * PCI core handles it for _PR3.
2861 */
2862 amdgpu_device_cache_pci_state(pdev);
2863 pci_disable_device(pdev);
2864 pci_ignore_hotplug(pdev);
2865 pci_set_power_state(pdev, PCI_D3cold);
2866 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
2867 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) {
2868 /* nothing to do */
2869 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) ||
2870 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) {
2871 amdgpu_device_baco_enter(adev);
2872 }
2873
2874 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n");
2875
2876 return 0;
2877 }
2878
amdgpu_pmops_runtime_resume(struct device * dev)2879 static int amdgpu_pmops_runtime_resume(struct device *dev)
2880 {
2881 struct pci_dev *pdev = to_pci_dev(dev);
2882 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2883 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2884 int ret;
2885
2886 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE)
2887 return -EINVAL;
2888
2889 /* Avoids registers access if device is physically gone */
2890 if (!pci_device_is_present(adev->pdev))
2891 adev->no_hw_access = true;
2892
2893 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) {
2894 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2895
2896 /* Only need to handle PCI state in the driver for ATPX
2897 * PCI core handles it for _PR3.
2898 */
2899 pci_set_power_state(pdev, PCI_D0);
2900 amdgpu_device_load_pci_state(pdev);
2901 ret = pci_enable_device(pdev);
2902 if (ret)
2903 return ret;
2904 pci_set_master(pdev);
2905 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) {
2906 /* Only need to handle PCI state in the driver for ATPX
2907 * PCI core handles it for _PR3.
2908 */
2909 pci_set_master(pdev);
2910 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) ||
2911 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) {
2912 amdgpu_device_baco_exit(adev);
2913 }
2914 ret = amdgpu_device_resume(drm_dev, false);
2915 if (ret) {
2916 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)
2917 pci_disable_device(pdev);
2918 return ret;
2919 }
2920
2921 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)
2922 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
2923 adev->in_runpm = false;
2924 return 0;
2925 }
2926
amdgpu_pmops_runtime_idle(struct device * dev)2927 static int amdgpu_pmops_runtime_idle(struct device *dev)
2928 {
2929 struct drm_device *drm_dev = dev_get_drvdata(dev);
2930 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2931 int ret;
2932
2933 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2934 pm_runtime_forbid(dev);
2935 return -EBUSY;
2936 }
2937
2938 ret = amdgpu_runtime_idle_check_display(dev);
2939 if (ret)
2940 goto done;
2941
2942 ret = amdgpu_runtime_idle_check_userq(dev);
2943 done:
2944 pm_runtime_autosuspend(dev);
2945 return ret;
2946 }
2947
amdgpu_drm_release(struct inode * inode,struct file * filp)2948 static int amdgpu_drm_release(struct inode *inode, struct file *filp)
2949 {
2950 struct drm_file *file_priv = filp->private_data;
2951 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
2952 struct drm_device *dev = file_priv->minor->dev;
2953 int idx;
2954
2955 if (fpriv && drm_dev_enter(dev, &idx)) {
2956 amdgpu_evf_mgr_shutdown(&fpriv->evf_mgr);
2957 amdgpu_userq_mgr_cancel_resume(&fpriv->userq_mgr);
2958 amdgpu_evf_mgr_flush_suspend(&fpriv->evf_mgr);
2959 amdgpu_userq_mgr_fini(&fpriv->userq_mgr);
2960 amdgpu_evf_mgr_fini(&fpriv->evf_mgr);
2961 drm_dev_exit(idx);
2962 }
2963
2964 return drm_release(inode, filp);
2965 }
2966
amdgpu_drm_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)2967 long amdgpu_drm_ioctl(struct file *filp,
2968 unsigned int cmd, unsigned long arg)
2969 {
2970 struct drm_file *file_priv = filp->private_data;
2971 struct drm_device *dev;
2972 long ret;
2973
2974 dev = file_priv->minor->dev;
2975 ret = pm_runtime_get_sync(dev->dev);
2976 if (ret < 0)
2977 goto out;
2978
2979 ret = drm_ioctl(filp, cmd, arg);
2980
2981 out:
2982 pm_runtime_put_autosuspend(dev->dev);
2983 return ret;
2984 }
2985
2986 static const struct dev_pm_ops amdgpu_pm_ops = {
2987 .prepare = pm_sleep_ptr(amdgpu_pmops_prepare),
2988 .complete = pm_sleep_ptr(amdgpu_pmops_complete),
2989 .suspend = pm_sleep_ptr(amdgpu_pmops_suspend),
2990 .suspend_noirq = pm_sleep_ptr(amdgpu_pmops_suspend_noirq),
2991 .resume = pm_sleep_ptr(amdgpu_pmops_resume),
2992 .freeze = pm_sleep_ptr(amdgpu_pmops_freeze),
2993 .thaw = pm_sleep_ptr(amdgpu_pmops_thaw),
2994 .poweroff = pm_sleep_ptr(amdgpu_pmops_poweroff),
2995 .restore = pm_sleep_ptr(amdgpu_pmops_restore),
2996 .runtime_suspend = amdgpu_pmops_runtime_suspend,
2997 .runtime_resume = amdgpu_pmops_runtime_resume,
2998 .runtime_idle = amdgpu_pmops_runtime_idle,
2999 };
3000
amdgpu_flush(struct file * f,fl_owner_t id)3001 static int amdgpu_flush(struct file *f, fl_owner_t id)
3002 {
3003 struct drm_file *file_priv = f->private_data;
3004 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
3005 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
3006
3007 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
3008 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
3009
3010 return timeout >= 0 ? 0 : timeout;
3011 }
3012
3013 static const struct file_operations amdgpu_driver_kms_fops = {
3014 .owner = THIS_MODULE,
3015 .open = drm_open,
3016 .flush = amdgpu_flush,
3017 .release = amdgpu_drm_release,
3018 .unlocked_ioctl = amdgpu_drm_ioctl,
3019 .mmap = drm_gem_mmap,
3020 .poll = drm_poll,
3021 .read = drm_read,
3022 #ifdef CONFIG_COMPAT
3023 .compat_ioctl = amdgpu_kms_compat_ioctl,
3024 #endif
3025 #ifdef CONFIG_PROC_FS
3026 .show_fdinfo = drm_show_fdinfo,
3027 #endif
3028 .fop_flags = FOP_UNSIGNED_OFFSET,
3029 };
3030
amdgpu_file_to_fpriv(struct file * filp,struct amdgpu_fpriv ** fpriv)3031 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
3032 {
3033 struct drm_file *file;
3034
3035 if (!filp)
3036 return -EINVAL;
3037
3038 if (filp->f_op != &amdgpu_driver_kms_fops)
3039 return -EINVAL;
3040
3041 file = filp->private_data;
3042 *fpriv = file->driver_priv;
3043 return 0;
3044 }
3045
3046 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
3047 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3048 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3049 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3050 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
3051 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3052 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3053 /* KMS */
3054 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3055 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3056 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3057 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3058 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3059 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3060 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3061 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3062 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3063 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3064 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ, amdgpu_userq_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3065 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3066 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3067 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3068 };
3069
3070 static const struct drm_driver amdgpu_kms_driver = {
3071 .driver_features =
3072 DRIVER_ATOMIC |
3073 DRIVER_GEM |
3074 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
3075 DRIVER_SYNCOBJ_TIMELINE,
3076 .open = amdgpu_driver_open_kms,
3077 .postclose = amdgpu_driver_postclose_kms,
3078 .ioctls = amdgpu_ioctls_kms,
3079 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
3080 .dumb_create = amdgpu_mode_dumb_create,
3081 .dumb_map_offset = amdgpu_mode_dumb_mmap,
3082 DRM_FBDEV_TTM_DRIVER_OPS,
3083 .fops = &amdgpu_driver_kms_fops,
3084 .release = &amdgpu_driver_release_kms,
3085 #ifdef CONFIG_PROC_FS
3086 .show_fdinfo = amdgpu_show_fdinfo,
3087 #endif
3088
3089 .gem_prime_import = amdgpu_gem_prime_import,
3090
3091 .name = DRIVER_NAME,
3092 .desc = DRIVER_DESC,
3093 .major = KMS_DRIVER_MAJOR,
3094 .minor = KMS_DRIVER_MINOR,
3095 .patchlevel = KMS_DRIVER_PATCHLEVEL,
3096 };
3097
3098 const struct drm_driver amdgpu_partition_driver = {
3099 .driver_features =
3100 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ |
3101 DRIVER_SYNCOBJ_TIMELINE,
3102 .open = amdgpu_driver_open_kms,
3103 .postclose = amdgpu_driver_postclose_kms,
3104 .ioctls = amdgpu_ioctls_kms,
3105 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
3106 .dumb_create = amdgpu_mode_dumb_create,
3107 .dumb_map_offset = amdgpu_mode_dumb_mmap,
3108 DRM_FBDEV_TTM_DRIVER_OPS,
3109 .fops = &amdgpu_driver_kms_fops,
3110 .release = &amdgpu_driver_release_kms,
3111
3112 .gem_prime_import = amdgpu_gem_prime_import,
3113
3114 .name = DRIVER_NAME,
3115 .desc = DRIVER_DESC,
3116 .major = KMS_DRIVER_MAJOR,
3117 .minor = KMS_DRIVER_MINOR,
3118 .patchlevel = KMS_DRIVER_PATCHLEVEL,
3119 };
3120
3121 static struct pci_error_handlers amdgpu_pci_err_handler = {
3122 .error_detected = amdgpu_pci_error_detected,
3123 .mmio_enabled = amdgpu_pci_mmio_enabled,
3124 .slot_reset = amdgpu_pci_slot_reset,
3125 .resume = amdgpu_pci_resume,
3126 };
3127
3128 static const struct attribute_group *amdgpu_sysfs_groups[] = {
3129 &amdgpu_vram_mgr_attr_group,
3130 &amdgpu_gtt_mgr_attr_group,
3131 &amdgpu_flash_attr_group,
3132 NULL,
3133 };
3134
3135 static struct pci_driver amdgpu_kms_pci_driver = {
3136 .name = DRIVER_NAME,
3137 .id_table = pciidlist,
3138 .probe = amdgpu_pci_probe,
3139 .remove = amdgpu_pci_remove,
3140 .shutdown = amdgpu_pci_shutdown,
3141 .driver.pm = pm_ptr(&amdgpu_pm_ops),
3142 .err_handler = &amdgpu_pci_err_handler,
3143 .dev_groups = amdgpu_sysfs_groups,
3144 };
3145
amdgpu_init(void)3146 static int __init amdgpu_init(void)
3147 {
3148 int r;
3149
3150 r = amdgpu_sync_init();
3151 if (r)
3152 goto error_sync;
3153
3154 r = amdgpu_userq_fence_slab_init();
3155 if (r)
3156 goto error_fence;
3157
3158 amdgpu_register_atpx_handler();
3159 amdgpu_acpi_detect();
3160
3161 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
3162 amdgpu_amdkfd_init();
3163
3164 if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) {
3165 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
3166 pr_crit("Overdrive is enabled, please disable it before "
3167 "reporting any bugs unrelated to overdrive.\n");
3168 }
3169
3170 /* let modprobe override vga console setting */
3171 return pci_register_driver(&amdgpu_kms_pci_driver);
3172
3173 error_fence:
3174 amdgpu_sync_fini();
3175
3176 error_sync:
3177 return r;
3178 }
3179
amdgpu_exit(void)3180 static void __exit amdgpu_exit(void)
3181 {
3182 amdgpu_amdkfd_fini();
3183 pci_unregister_driver(&amdgpu_kms_pci_driver);
3184 amdgpu_unregister_atpx_handler();
3185 amdgpu_acpi_release();
3186 amdgpu_sync_fini();
3187 amdgpu_userq_fence_slab_fini();
3188 mmu_notifier_synchronize();
3189 amdgpu_xcp_drv_release();
3190 }
3191
3192 module_init(amdgpu_init);
3193 module_exit(amdgpu_exit);
3194
3195 MODULE_AUTHOR(DRIVER_AUTHOR);
3196 MODULE_DESCRIPTION(DRIVER_DESC);
3197 MODULE_LICENSE("GPL and additional rights");
3198