1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/clients/drm_client_setup.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_fbdev_ttm.h> 29 #include <drm/drm_gem.h> 30 #include <drm/drm_managed.h> 31 #include <drm/drm_pciids.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/drm_vblank.h> 34 35 #include <linux/cc_platform.h> 36 #include <linux/dynamic_debug.h> 37 #include <linux/module.h> 38 #include <linux/mmu_notifier.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/suspend.h> 41 #include <linux/vga_switcheroo.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_amdkfd.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_drv.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_irq.h" 49 #include "amdgpu_psp.h" 50 #include "amdgpu_ras.h" 51 #include "amdgpu_reset.h" 52 #include "amdgpu_sched.h" 53 #include "amdgpu_xgmi.h" 54 #include "../amdxcp/amdgpu_xcp_drv.h" 55 56 /* 57 * KMS wrapper. 58 * - 3.0.0 - initial driver 59 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 60 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 61 * at the end of IBs. 62 * - 3.3.0 - Add VM support for UVD on supported hardware. 63 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 64 * - 3.5.0 - Add support for new UVD_NO_OP register. 65 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 66 * - 3.7.0 - Add support for VCE clock list packet 67 * - 3.8.0 - Add support raster config init in the kernel 68 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 69 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 70 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 71 * - 3.12.0 - Add query for double offchip LDS buffers 72 * - 3.13.0 - Add PRT support 73 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 74 * - 3.15.0 - Export more gpu info for gfx9 75 * - 3.16.0 - Add reserved vmid support 76 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 77 * - 3.18.0 - Export gpu always on cu bitmap 78 * - 3.19.0 - Add support for UVD MJPEG decode 79 * - 3.20.0 - Add support for local BOs 80 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 81 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 82 * - 3.23.0 - Add query for VRAM lost counter 83 * - 3.24.0 - Add high priority compute support for gfx9 84 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 85 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 86 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 87 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 88 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 89 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 90 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 91 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 92 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 93 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 94 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 95 * - 3.36.0 - Allow reading more status registers on si/cik 96 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 97 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 98 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 99 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 100 * - 3.41.0 - Add video codec query 101 * - 3.42.0 - Add 16bpc fixed point display support 102 * - 3.43.0 - Add device hot plug/unplug support 103 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 104 * - 3.45.0 - Add context ioctl stable pstate interface 105 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 106 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 107 * - 3.48.0 - Add IP discovery version info to HW INFO 108 * - 3.49.0 - Add gang submit into CS IOCTL 109 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 110 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 111 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 112 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 113 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 114 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 115 * 3.53.0 - Support for GFX11 CP GFX shadowing 116 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 117 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 118 * - 3.56.0 - Update IB start address and size alignment for decode and encode 119 * - 3.57.0 - Compute tunneling on GFX10+ 120 * - 3.58.0 - Add GFX12 DCC support 121 * - 3.59.0 - Cleared VRAM 122 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement) 123 * - 3.61.0 - Contains fix for RV/PCO compute queues 124 * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT 125 * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size 126 */ 127 #define KMS_DRIVER_MAJOR 3 128 #define KMS_DRIVER_MINOR 63 129 #define KMS_DRIVER_PATCHLEVEL 0 130 131 /* 132 * amdgpu.debug module options. Are all disabled by default 133 */ 134 enum AMDGPU_DEBUG_MASK { 135 AMDGPU_DEBUG_VM = BIT(0), 136 AMDGPU_DEBUG_LARGEBAR = BIT(1), 137 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 138 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 139 AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4), 140 AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5), 141 AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6), 142 AMDGPU_DEBUG_SMU_POOL = BIT(7), 143 }; 144 145 unsigned int amdgpu_vram_limit = UINT_MAX; 146 int amdgpu_vis_vram_limit; 147 int amdgpu_gart_size = -1; /* auto */ 148 int amdgpu_gtt_size = -1; /* auto */ 149 int amdgpu_moverate = -1; /* auto */ 150 int amdgpu_audio = -1; 151 int amdgpu_disp_priority; 152 int amdgpu_hw_i2c; 153 int amdgpu_pcie_gen2 = -1; 154 int amdgpu_msi = -1; 155 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 156 int amdgpu_dpm = -1; 157 int amdgpu_fw_load_type = -1; 158 int amdgpu_aspm = -1; 159 int amdgpu_runtime_pm = -1; 160 uint amdgpu_ip_block_mask = 0xffffffff; 161 int amdgpu_bapm = -1; 162 int amdgpu_deep_color; 163 int amdgpu_vm_size = -1; 164 int amdgpu_vm_fragment_size = -1; 165 int amdgpu_vm_block_size = -1; 166 int amdgpu_vm_fault_stop; 167 int amdgpu_vm_update_mode = -1; 168 int amdgpu_exp_hw_support; 169 int amdgpu_dc = -1; 170 int amdgpu_sched_jobs = 32; 171 int amdgpu_sched_hw_submission = 2; 172 uint amdgpu_pcie_gen_cap; 173 uint amdgpu_pcie_lane_cap; 174 u64 amdgpu_cg_mask = 0xffffffffffffffff; 175 uint amdgpu_pg_mask = 0xffffffff; 176 uint amdgpu_sdma_phase_quantum = 32; 177 char *amdgpu_disable_cu; 178 char *amdgpu_virtual_display; 179 bool enforce_isolation; 180 int amdgpu_modeset = -1; 181 182 /* Specifies the default granularity for SVM, used in buffer 183 * migration and restoration of backing memory when handling 184 * recoverable page faults. 185 * 186 * The value is given as log(numPages(buffer)); for a 2 MiB 187 * buffer it computes to be 9 188 */ 189 uint amdgpu_svm_default_granularity = 9; 190 191 /* 192 * OverDrive(bit 14) disabled by default 193 * GFX DCS(bit 19) disabled by default 194 */ 195 uint amdgpu_pp_feature_mask = 0xfff7bfff; 196 uint amdgpu_force_long_training; 197 int amdgpu_lbpw = -1; 198 int amdgpu_compute_multipipe = -1; 199 int amdgpu_gpu_recovery = -1; /* auto */ 200 int amdgpu_emu_mode; 201 uint amdgpu_smu_memory_pool_size; 202 int amdgpu_smu_pptable_id = -1; 203 /* 204 * FBC (bit 0) disabled by default 205 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 206 * - With this, for multiple monitors in sync(e.g. with the same model), 207 * mclk switching will be allowed. And the mclk will be not foced to the 208 * highest. That helps saving some idle power. 209 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 210 * PSR (bit 3) disabled by default 211 * EDP NO POWER SEQUENCING (bit 4) disabled by default 212 */ 213 uint amdgpu_dc_feature_mask = 2; 214 uint amdgpu_dc_debug_mask; 215 uint amdgpu_dc_visual_confirm; 216 int amdgpu_async_gfx_ring = 1; 217 int amdgpu_mcbp = -1; 218 int amdgpu_discovery = -1; 219 int amdgpu_mes; 220 int amdgpu_mes_log_enable = 0; 221 int amdgpu_mes_kiq; 222 int amdgpu_uni_mes = 1; 223 int amdgpu_noretry = -1; 224 int amdgpu_force_asic_type = -1; 225 int amdgpu_tmz = -1; /* auto */ 226 uint amdgpu_freesync_vid_mode; 227 int amdgpu_reset_method = -1; /* auto */ 228 int amdgpu_num_kcq = -1; 229 int amdgpu_smartshift_bias; 230 int amdgpu_use_xgmi_p2p = 1; 231 int amdgpu_vcnfw_log; 232 int amdgpu_sg_display = -1; /* auto */ 233 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 234 int amdgpu_umsch_mm; 235 int amdgpu_seamless = -1; /* auto */ 236 uint amdgpu_debug_mask; 237 int amdgpu_agp = -1; /* auto */ 238 int amdgpu_wbrf = -1; 239 int amdgpu_damage_clips = -1; /* auto */ 240 int amdgpu_umsch_mm_fwlog; 241 242 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 243 "DRM_UT_CORE", 244 "DRM_UT_DRIVER", 245 "DRM_UT_KMS", 246 "DRM_UT_PRIME", 247 "DRM_UT_ATOMIC", 248 "DRM_UT_VBL", 249 "DRM_UT_STATE", 250 "DRM_UT_LEASE", 251 "DRM_UT_DP", 252 "DRM_UT_DRMRES"); 253 254 struct amdgpu_mgpu_info mgpu_info = { 255 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 256 }; 257 int amdgpu_ras_enable = -1; 258 uint amdgpu_ras_mask = 0xffffffff; 259 int amdgpu_bad_page_threshold = -1; 260 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 261 .timeout_fatal_disable = false, 262 .period = 0x0, /* default to 0x0 (timeout disable) */ 263 }; 264 265 /** 266 * DOC: vramlimit (int) 267 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 268 */ 269 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 270 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 271 272 /** 273 * DOC: vis_vramlimit (int) 274 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 275 */ 276 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 277 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 278 279 /** 280 * DOC: gartsize (uint) 281 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 282 * The default is -1 (The size depends on asic). 283 */ 284 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 285 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 286 287 /** 288 * DOC: gttsize (int) 289 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 290 * The default is -1 (Use value specified by TTM). 291 * This parameter is deprecated and will be removed in the future. 292 */ 293 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 294 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 295 296 /** 297 * DOC: moverate (int) 298 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 299 */ 300 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 301 module_param_named(moverate, amdgpu_moverate, int, 0600); 302 303 /** 304 * DOC: audio (int) 305 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 306 */ 307 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 308 module_param_named(audio, amdgpu_audio, int, 0444); 309 310 /** 311 * DOC: disp_priority (int) 312 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 313 */ 314 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 315 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 316 317 /** 318 * DOC: hw_i2c (int) 319 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 320 */ 321 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 322 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 323 324 /** 325 * DOC: pcie_gen2 (int) 326 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 327 */ 328 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 329 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 330 331 /** 332 * DOC: msi (int) 333 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 334 */ 335 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 336 module_param_named(msi, amdgpu_msi, int, 0444); 337 338 /** 339 * DOC: svm_default_granularity (uint) 340 * Used in buffer migration and handling of recoverable page faults 341 */ 342 MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB"); 343 module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644); 344 345 /** 346 * DOC: lockup_timeout (string) 347 * Set GPU scheduler timeout value in ms. 348 * 349 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 350 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 351 * to the default timeout. 352 * 353 * - With one value specified, the setting will apply to all non-compute jobs. 354 * - With multiple values specified, the first one will be for GFX. 355 * The second one is for Compute. The third and fourth ones are 356 * for SDMA and Video. 357 * 358 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 359 * jobs is 10000. The timeout for compute is 60000. 360 */ 361 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 362 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 363 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 364 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 365 366 /** 367 * DOC: dpm (int) 368 * Override for dynamic power management setting 369 * (0 = disable, 1 = enable) 370 * The default is -1 (auto). 371 */ 372 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 373 module_param_named(dpm, amdgpu_dpm, int, 0444); 374 375 /** 376 * DOC: fw_load_type (int) 377 * Set different firmware loading type for debugging, if supported. 378 * Set to 0 to force direct loading if supported by the ASIC. Set 379 * to -1 to select the default loading mode for the ASIC, as defined 380 * by the driver. The default is -1 (auto). 381 */ 382 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 383 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 384 385 /** 386 * DOC: aspm (int) 387 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 388 */ 389 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 390 module_param_named(aspm, amdgpu_aspm, int, 0444); 391 392 /** 393 * DOC: runpm (int) 394 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 395 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 396 * Setting the value to 0 disables this functionality. 397 * Setting the value to -2 is auto enabled with power down when displays are attached. 398 */ 399 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 400 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 401 402 /** 403 * DOC: ip_block_mask (uint) 404 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 405 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 406 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 407 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 408 */ 409 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 410 module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 411 412 /** 413 * DOC: bapm (int) 414 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 415 * The default -1 (auto, enabled) 416 */ 417 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 418 module_param_named(bapm, amdgpu_bapm, int, 0444); 419 420 /** 421 * DOC: deep_color (int) 422 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 423 */ 424 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 425 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 426 427 /** 428 * DOC: vm_size (int) 429 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 430 */ 431 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 432 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 433 434 /** 435 * DOC: vm_fragment_size (int) 436 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 437 */ 438 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 439 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 440 441 /** 442 * DOC: vm_block_size (int) 443 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 444 */ 445 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 446 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 447 448 /** 449 * DOC: vm_fault_stop (int) 450 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 451 */ 452 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 453 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 454 455 /** 456 * DOC: vm_update_mode (int) 457 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 458 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 459 */ 460 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 461 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 462 463 /** 464 * DOC: exp_hw_support (int) 465 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 466 */ 467 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 468 module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 469 470 /** 471 * DOC: dc (int) 472 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 473 */ 474 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 475 module_param_named(dc, amdgpu_dc, int, 0444); 476 477 /** 478 * DOC: sched_jobs (int) 479 * Override the max number of jobs supported in the sw queue. The default is 32. 480 */ 481 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 482 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 483 484 /** 485 * DOC: sched_hw_submission (int) 486 * Override the max number of HW submissions. The default is 2. 487 */ 488 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 489 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 490 491 /** 492 * DOC: ppfeaturemask (hexint) 493 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 494 * The default is the current set of stable power features. 495 */ 496 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 497 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 498 499 /** 500 * DOC: forcelongtraining (uint) 501 * Force long memory training in resume. 502 * The default is zero, indicates short training in resume. 503 */ 504 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 505 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 506 507 /** 508 * DOC: pcie_gen_cap (uint) 509 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 510 * The default is 0 (automatic for each asic). 511 */ 512 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 513 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 514 515 /** 516 * DOC: pcie_lane_cap (uint) 517 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 518 * The default is 0 (automatic for each asic). 519 */ 520 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 521 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 522 523 /** 524 * DOC: cg_mask (ullong) 525 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 526 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 527 */ 528 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 529 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 530 531 /** 532 * DOC: pg_mask (uint) 533 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 534 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 535 */ 536 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 537 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 538 539 /** 540 * DOC: sdma_phase_quantum (uint) 541 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 542 */ 543 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 544 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 545 546 /** 547 * DOC: disable_cu (charp) 548 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 549 */ 550 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 551 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 552 553 /** 554 * DOC: virtual_display (charp) 555 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 556 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 557 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 558 * device at 26:00.0. The default is NULL. 559 */ 560 MODULE_PARM_DESC(virtual_display, 561 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 562 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 563 564 /** 565 * DOC: lbpw (int) 566 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 567 */ 568 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 569 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 570 571 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 572 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 573 574 /** 575 * DOC: gpu_recovery (int) 576 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 577 */ 578 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 579 module_param_named_unsafe(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 580 581 /** 582 * DOC: emu_mode (int) 583 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 584 */ 585 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 586 module_param_named_unsafe(emu_mode, amdgpu_emu_mode, int, 0444); 587 588 /** 589 * DOC: ras_enable (int) 590 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 591 */ 592 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 593 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 594 595 /** 596 * DOC: ras_mask (uint) 597 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 598 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 599 */ 600 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 601 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 602 603 /** 604 * DOC: timeout_fatal_disable (bool) 605 * Disable Watchdog timeout fatal error event 606 */ 607 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 608 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 609 610 /** 611 * DOC: timeout_period (uint) 612 * Modify the watchdog timeout max_cycles as (1 << period) 613 */ 614 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 615 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 616 617 /** 618 * DOC: si_support (int) 619 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 620 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 621 * otherwise using amdgpu driver. 622 */ 623 #ifdef CONFIG_DRM_AMDGPU_SI 624 625 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 626 int amdgpu_si_support; 627 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 628 #else 629 int amdgpu_si_support = 1; 630 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 631 #endif 632 633 module_param_named(si_support, amdgpu_si_support, int, 0444); 634 #endif 635 636 /** 637 * DOC: cik_support (int) 638 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 639 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 640 * otherwise using amdgpu driver. 641 */ 642 #ifdef CONFIG_DRM_AMDGPU_CIK 643 644 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 645 int amdgpu_cik_support; 646 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 647 #else 648 int amdgpu_cik_support = 1; 649 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 650 #endif 651 652 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 653 #endif 654 655 /** 656 * DOC: smu_memory_pool_size (uint) 657 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 658 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 659 */ 660 MODULE_PARM_DESC(smu_memory_pool_size, 661 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 662 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 663 664 /** 665 * DOC: async_gfx_ring (int) 666 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 667 */ 668 MODULE_PARM_DESC(async_gfx_ring, 669 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 670 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 671 672 /** 673 * DOC: mcbp (int) 674 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 675 */ 676 MODULE_PARM_DESC(mcbp, 677 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 678 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 679 680 /** 681 * DOC: discovery (int) 682 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 683 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 684 */ 685 MODULE_PARM_DESC(discovery, 686 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 687 module_param_named(discovery, amdgpu_discovery, int, 0444); 688 689 /** 690 * DOC: mes (int) 691 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 692 * (0 = disabled (default), 1 = enabled) 693 */ 694 MODULE_PARM_DESC(mes, 695 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 696 module_param_named(mes, amdgpu_mes, int, 0444); 697 698 /** 699 * DOC: mes_log_enable (int) 700 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. 701 * (0 = disabled (default), 1 = enabled) 702 */ 703 MODULE_PARM_DESC(mes_log_enable, 704 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); 705 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); 706 707 /** 708 * DOC: mes_kiq (int) 709 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 710 * (0 = disabled (default), 1 = enabled) 711 */ 712 MODULE_PARM_DESC(mes_kiq, 713 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 714 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 715 716 /** 717 * DOC: uni_mes (int) 718 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. 719 * (0 = disabled (default), 1 = enabled) 720 */ 721 MODULE_PARM_DESC(uni_mes, 722 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)"); 723 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444); 724 725 /** 726 * DOC: noretry (int) 727 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 728 * do not support per-process XNACK this also disables retry page faults. 729 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 730 */ 731 MODULE_PARM_DESC(noretry, 732 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 733 module_param_named(noretry, amdgpu_noretry, int, 0644); 734 735 /** 736 * DOC: force_asic_type (int) 737 * A non negative value used to specify the asic type for all supported GPUs. 738 */ 739 MODULE_PARM_DESC(force_asic_type, 740 "A non negative value used to specify the asic type for all supported GPUs"); 741 module_param_named_unsafe(force_asic_type, amdgpu_force_asic_type, int, 0444); 742 743 /** 744 * DOC: use_xgmi_p2p (int) 745 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 746 */ 747 MODULE_PARM_DESC(use_xgmi_p2p, 748 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 749 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 750 751 752 #ifdef CONFIG_HSA_AMD 753 /** 754 * DOC: sched_policy (int) 755 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 756 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 757 * assigns queues to HQDs. 758 */ 759 int sched_policy = KFD_SCHED_POLICY_HWS; 760 module_param_unsafe(sched_policy, int, 0444); 761 MODULE_PARM_DESC(sched_policy, 762 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 763 764 /** 765 * DOC: hws_max_conc_proc (int) 766 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 767 * number of VMIDs assigned to the HWS, which is also the default. 768 */ 769 int hws_max_conc_proc = -1; 770 module_param(hws_max_conc_proc, int, 0444); 771 MODULE_PARM_DESC(hws_max_conc_proc, 772 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 773 774 /** 775 * DOC: cwsr_enable (int) 776 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 777 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 778 * disables it. 779 */ 780 int cwsr_enable = 1; 781 module_param(cwsr_enable, int, 0444); 782 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 783 784 /** 785 * DOC: max_num_of_queues_per_device (int) 786 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 787 * is 4096. 788 */ 789 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 790 module_param(max_num_of_queues_per_device, int, 0444); 791 MODULE_PARM_DESC(max_num_of_queues_per_device, 792 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 793 794 /** 795 * DOC: send_sigterm (int) 796 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 797 * but just print errors on dmesg. Setting 1 enables sending sigterm. 798 */ 799 int send_sigterm; 800 module_param(send_sigterm, int, 0444); 801 MODULE_PARM_DESC(send_sigterm, 802 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 803 804 /** 805 * DOC: halt_if_hws_hang (int) 806 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 807 * Setting 1 enables halt on hang. 808 */ 809 int halt_if_hws_hang; 810 module_param_unsafe(halt_if_hws_hang, int, 0644); 811 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 812 813 /** 814 * DOC: hws_gws_support(bool) 815 * Assume that HWS supports GWS barriers regardless of what firmware version 816 * check says. Default value: false (rely on MEC2 firmware version check). 817 */ 818 bool hws_gws_support; 819 module_param_unsafe(hws_gws_support, bool, 0444); 820 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 821 822 /** 823 * DOC: queue_preemption_timeout_ms (int) 824 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 825 */ 826 int queue_preemption_timeout_ms = 9000; 827 module_param(queue_preemption_timeout_ms, int, 0644); 828 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 829 830 /** 831 * DOC: debug_evictions(bool) 832 * Enable extra debug messages to help determine the cause of evictions 833 */ 834 bool debug_evictions; 835 module_param(debug_evictions, bool, 0644); 836 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 837 838 /** 839 * DOC: no_system_mem_limit(bool) 840 * Disable system memory limit, to support multiple process shared memory 841 */ 842 bool no_system_mem_limit; 843 module_param(no_system_mem_limit, bool, 0644); 844 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 845 846 /** 847 * DOC: no_queue_eviction_on_vm_fault (int) 848 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 849 */ 850 int amdgpu_no_queue_eviction_on_vm_fault; 851 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 852 module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 853 #endif 854 855 /** 856 * DOC: mtype_local (int) 857 */ 858 int amdgpu_mtype_local; 859 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 860 module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444); 861 862 /** 863 * DOC: pcie_p2p (bool) 864 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 865 */ 866 #ifdef CONFIG_HSA_AMD_P2P 867 bool pcie_p2p = true; 868 module_param(pcie_p2p, bool, 0444); 869 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 870 #endif 871 872 /** 873 * DOC: dcfeaturemask (uint) 874 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 875 * The default is the current set of stable display features. 876 */ 877 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 878 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 879 880 /** 881 * DOC: dcdebugmask (uint) 882 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 883 */ 884 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 885 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 886 887 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 888 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 889 890 /** 891 * DOC: abmlevel (uint) 892 * Override the default ABM (Adaptive Backlight Management) level used for DC 893 * enabled hardware. Requires DMCU to be supported and loaded. 894 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 895 * default. Values 1-4 control the maximum allowable brightness reduction via 896 * the ABM algorithm, with 1 being the least reduction and 4 being the most 897 * reduction. 898 * 899 * Defaults to -1, or auto. Userspace can only override this level after 900 * boot if it's set to auto. 901 */ 902 int amdgpu_dm_abm_level = -1; 903 MODULE_PARM_DESC(abmlevel, 904 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 905 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 906 907 int amdgpu_backlight = -1; 908 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 909 module_param_named(backlight, amdgpu_backlight, bint, 0444); 910 911 /** 912 * DOC: damageclips (int) 913 * Enable or disable damage clips support. If damage clips support is disabled, 914 * we will force full frame updates, irrespective of what user space sends to 915 * us. 916 * 917 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 918 */ 919 MODULE_PARM_DESC(damageclips, 920 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 921 module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 922 923 /** 924 * DOC: tmz (int) 925 * Trusted Memory Zone (TMZ) is a method to protect data being written 926 * to or read from memory. 927 * 928 * The default value: 0 (off). TODO: change to auto till it is completed. 929 */ 930 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 931 module_param_named(tmz, amdgpu_tmz, int, 0444); 932 933 /** 934 * DOC: freesync_video (uint) 935 * Enable the optimization to adjust front porch timing to achieve seamless 936 * mode change experience when setting a freesync supported mode for which full 937 * modeset is not needed. 938 * 939 * The Display Core will add a set of modes derived from the base FreeSync 940 * video mode into the corresponding connector's mode list based on commonly 941 * used refresh rates and VRR range of the connected display, when users enable 942 * this feature. From the userspace perspective, they can see a seamless mode 943 * change experience when the change between different refresh rates under the 944 * same resolution. Additionally, userspace applications such as Video playback 945 * can read this modeset list and change the refresh rate based on the video 946 * frame rate. Finally, the userspace can also derive an appropriate mode for a 947 * particular refresh rate based on the FreeSync Mode and add it to the 948 * connector's mode list. 949 * 950 * Note: This is an experimental feature. 951 * 952 * The default value: 0 (off). 953 */ 954 MODULE_PARM_DESC( 955 freesync_video, 956 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 957 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 958 959 /** 960 * DOC: reset_method (int) 961 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 962 */ 963 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 964 module_param_named_unsafe(reset_method, amdgpu_reset_method, int, 0644); 965 966 /** 967 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 968 * threshold value of faulty pages detected by RAS ECC, which may 969 * result in the GPU entering bad status when the number of total 970 * faulty pages by ECC exceeds the threshold value. 971 */ 972 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = threshold determined by a formula, 0 < threshold < max records, user-defined threshold)"); 973 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 974 975 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 976 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 977 978 /** 979 * DOC: vcnfw_log (int) 980 * Enable vcnfw log output for debugging, the default is disabled. 981 */ 982 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 983 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 984 985 /** 986 * DOC: sg_display (int) 987 * Disable S/G (scatter/gather) display (i.e., display from system memory). 988 * This option is only relevant on APUs. Set this option to 0 to disable 989 * S/G display if you experience flickering or other issues under memory 990 * pressure and report the issue. 991 */ 992 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 993 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 994 995 /** 996 * DOC: umsch_mm (int) 997 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 998 * (0 = disabled (default), 1 = enabled) 999 */ 1000 MODULE_PARM_DESC(umsch_mm, 1001 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 1002 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 1003 1004 /** 1005 * DOC: umsch_mm_fwlog (int) 1006 * Enable umschfw log output for debugging, the default is disabled. 1007 */ 1008 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)"); 1009 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444); 1010 1011 /** 1012 * DOC: smu_pptable_id (int) 1013 * Used to override pptable id. id = 0 use VBIOS pptable. 1014 * id > 0 use the soft pptable with specicfied id. 1015 */ 1016 MODULE_PARM_DESC(smu_pptable_id, 1017 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 1018 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 1019 1020 /** 1021 * DOC: partition_mode (int) 1022 * Used to override the default SPX mode. 1023 */ 1024 MODULE_PARM_DESC( 1025 user_partt_mode, 1026 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 1027 0 = AMDGPU_SPX_PARTITION_MODE, \ 1028 1 = AMDGPU_DPX_PARTITION_MODE, \ 1029 2 = AMDGPU_TPX_PARTITION_MODE, \ 1030 3 = AMDGPU_QPX_PARTITION_MODE, \ 1031 4 = AMDGPU_CPX_PARTITION_MODE)"); 1032 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 1033 1034 1035 /** 1036 * DOC: enforce_isolation (bool) 1037 * enforce process isolation between graphics and compute via using the same reserved vmid. 1038 */ 1039 module_param(enforce_isolation, bool, 0444); 1040 MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on"); 1041 1042 /** 1043 * DOC: modeset (int) 1044 * Override nomodeset (1 = override, -1 = auto). The default is -1 (auto). 1045 */ 1046 MODULE_PARM_DESC(modeset, "Override nomodeset (1 = enable, -1 = auto)"); 1047 module_param_named(modeset, amdgpu_modeset, int, 0444); 1048 1049 /** 1050 * DOC: seamless (int) 1051 * Seamless boot will keep the image on the screen during the boot process. 1052 */ 1053 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 1054 module_param_named(seamless, amdgpu_seamless, int, 0444); 1055 1056 /** 1057 * DOC: debug_mask (uint) 1058 * Debug options for amdgpu, work as a binary mask with the following options: 1059 * 1060 * - 0x1: Debug VM handling 1061 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1062 * limits the VRAM size reported to ROCm applications to the visible 1063 * size, usually 256MB. 1064 * - 0x4: Disable GPU soft recovery, always do a full reset 1065 * - 0x8: Use VRAM for firmware loading 1066 * - 0x10: Enable ACA based RAS logging 1067 * - 0x20: Enable experimental resets 1068 * - 0x40: Disable ring resets 1069 * - 0x80: Use VRAM for SMU pool 1070 */ 1071 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1072 module_param_named_unsafe(debug_mask, amdgpu_debug_mask, uint, 0444); 1073 1074 /** 1075 * DOC: agp (int) 1076 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1077 * address space for direct access to system memory. Note that these accesses 1078 * are non-snooped, so they are only used for access to uncached memory. 1079 */ 1080 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1081 module_param_named(agp, amdgpu_agp, int, 0444); 1082 1083 /** 1084 * DOC: wbrf (int) 1085 * Enable Wifi RFI interference mitigation feature. 1086 * Due to electrical and mechanical constraints there may be likely interference of 1087 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1088 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1089 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1090 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1091 * P-state transition. However, there may be potential performance impact with this 1092 * feature enabled. 1093 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1094 */ 1095 MODULE_PARM_DESC(wbrf, 1096 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1097 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1098 1099 /* These devices are not supported by amdgpu. 1100 * They are supported by the mach64, r128, radeon drivers 1101 */ 1102 static const u16 amdgpu_unsupported_pciidlist[] = { 1103 /* mach64 */ 1104 0x4354, 1105 0x4358, 1106 0x4554, 1107 0x4742, 1108 0x4744, 1109 0x4749, 1110 0x474C, 1111 0x474D, 1112 0x474E, 1113 0x474F, 1114 0x4750, 1115 0x4751, 1116 0x4752, 1117 0x4753, 1118 0x4754, 1119 0x4755, 1120 0x4756, 1121 0x4757, 1122 0x4758, 1123 0x4759, 1124 0x475A, 1125 0x4C42, 1126 0x4C44, 1127 0x4C47, 1128 0x4C49, 1129 0x4C4D, 1130 0x4C4E, 1131 0x4C50, 1132 0x4C51, 1133 0x4C52, 1134 0x4C53, 1135 0x5654, 1136 0x5655, 1137 0x5656, 1138 /* r128 */ 1139 0x4c45, 1140 0x4c46, 1141 0x4d46, 1142 0x4d4c, 1143 0x5041, 1144 0x5042, 1145 0x5043, 1146 0x5044, 1147 0x5045, 1148 0x5046, 1149 0x5047, 1150 0x5048, 1151 0x5049, 1152 0x504A, 1153 0x504B, 1154 0x504C, 1155 0x504D, 1156 0x504E, 1157 0x504F, 1158 0x5050, 1159 0x5051, 1160 0x5052, 1161 0x5053, 1162 0x5054, 1163 0x5055, 1164 0x5056, 1165 0x5057, 1166 0x5058, 1167 0x5245, 1168 0x5246, 1169 0x5247, 1170 0x524b, 1171 0x524c, 1172 0x534d, 1173 0x5446, 1174 0x544C, 1175 0x5452, 1176 /* radeon */ 1177 0x3150, 1178 0x3151, 1179 0x3152, 1180 0x3154, 1181 0x3155, 1182 0x3E50, 1183 0x3E54, 1184 0x4136, 1185 0x4137, 1186 0x4144, 1187 0x4145, 1188 0x4146, 1189 0x4147, 1190 0x4148, 1191 0x4149, 1192 0x414A, 1193 0x414B, 1194 0x4150, 1195 0x4151, 1196 0x4152, 1197 0x4153, 1198 0x4154, 1199 0x4155, 1200 0x4156, 1201 0x4237, 1202 0x4242, 1203 0x4336, 1204 0x4337, 1205 0x4437, 1206 0x4966, 1207 0x4967, 1208 0x4A48, 1209 0x4A49, 1210 0x4A4A, 1211 0x4A4B, 1212 0x4A4C, 1213 0x4A4D, 1214 0x4A4E, 1215 0x4A4F, 1216 0x4A50, 1217 0x4A54, 1218 0x4B48, 1219 0x4B49, 1220 0x4B4A, 1221 0x4B4B, 1222 0x4B4C, 1223 0x4C57, 1224 0x4C58, 1225 0x4C59, 1226 0x4C5A, 1227 0x4C64, 1228 0x4C66, 1229 0x4C67, 1230 0x4E44, 1231 0x4E45, 1232 0x4E46, 1233 0x4E47, 1234 0x4E48, 1235 0x4E49, 1236 0x4E4A, 1237 0x4E4B, 1238 0x4E50, 1239 0x4E51, 1240 0x4E52, 1241 0x4E53, 1242 0x4E54, 1243 0x4E56, 1244 0x5144, 1245 0x5145, 1246 0x5146, 1247 0x5147, 1248 0x5148, 1249 0x514C, 1250 0x514D, 1251 0x5157, 1252 0x5158, 1253 0x5159, 1254 0x515A, 1255 0x515E, 1256 0x5460, 1257 0x5462, 1258 0x5464, 1259 0x5548, 1260 0x5549, 1261 0x554A, 1262 0x554B, 1263 0x554C, 1264 0x554D, 1265 0x554E, 1266 0x554F, 1267 0x5550, 1268 0x5551, 1269 0x5552, 1270 0x5554, 1271 0x564A, 1272 0x564B, 1273 0x564F, 1274 0x5652, 1275 0x5653, 1276 0x5657, 1277 0x5834, 1278 0x5835, 1279 0x5954, 1280 0x5955, 1281 0x5974, 1282 0x5975, 1283 0x5960, 1284 0x5961, 1285 0x5962, 1286 0x5964, 1287 0x5965, 1288 0x5969, 1289 0x5a41, 1290 0x5a42, 1291 0x5a61, 1292 0x5a62, 1293 0x5b60, 1294 0x5b62, 1295 0x5b63, 1296 0x5b64, 1297 0x5b65, 1298 0x5c61, 1299 0x5c63, 1300 0x5d48, 1301 0x5d49, 1302 0x5d4a, 1303 0x5d4c, 1304 0x5d4d, 1305 0x5d4e, 1306 0x5d4f, 1307 0x5d50, 1308 0x5d52, 1309 0x5d57, 1310 0x5e48, 1311 0x5e4a, 1312 0x5e4b, 1313 0x5e4c, 1314 0x5e4d, 1315 0x5e4f, 1316 0x6700, 1317 0x6701, 1318 0x6702, 1319 0x6703, 1320 0x6704, 1321 0x6705, 1322 0x6706, 1323 0x6707, 1324 0x6708, 1325 0x6709, 1326 0x6718, 1327 0x6719, 1328 0x671c, 1329 0x671d, 1330 0x671f, 1331 0x6720, 1332 0x6721, 1333 0x6722, 1334 0x6723, 1335 0x6724, 1336 0x6725, 1337 0x6726, 1338 0x6727, 1339 0x6728, 1340 0x6729, 1341 0x6738, 1342 0x6739, 1343 0x673e, 1344 0x6740, 1345 0x6741, 1346 0x6742, 1347 0x6743, 1348 0x6744, 1349 0x6745, 1350 0x6746, 1351 0x6747, 1352 0x6748, 1353 0x6749, 1354 0x674A, 1355 0x6750, 1356 0x6751, 1357 0x6758, 1358 0x6759, 1359 0x675B, 1360 0x675D, 1361 0x675F, 1362 0x6760, 1363 0x6761, 1364 0x6762, 1365 0x6763, 1366 0x6764, 1367 0x6765, 1368 0x6766, 1369 0x6767, 1370 0x6768, 1371 0x6770, 1372 0x6771, 1373 0x6772, 1374 0x6778, 1375 0x6779, 1376 0x677B, 1377 0x6840, 1378 0x6841, 1379 0x6842, 1380 0x6843, 1381 0x6849, 1382 0x684C, 1383 0x6850, 1384 0x6858, 1385 0x6859, 1386 0x6880, 1387 0x6888, 1388 0x6889, 1389 0x688A, 1390 0x688C, 1391 0x688D, 1392 0x6898, 1393 0x6899, 1394 0x689b, 1395 0x689c, 1396 0x689d, 1397 0x689e, 1398 0x68a0, 1399 0x68a1, 1400 0x68a8, 1401 0x68a9, 1402 0x68b0, 1403 0x68b8, 1404 0x68b9, 1405 0x68ba, 1406 0x68be, 1407 0x68bf, 1408 0x68c0, 1409 0x68c1, 1410 0x68c7, 1411 0x68c8, 1412 0x68c9, 1413 0x68d8, 1414 0x68d9, 1415 0x68da, 1416 0x68de, 1417 0x68e0, 1418 0x68e1, 1419 0x68e4, 1420 0x68e5, 1421 0x68e8, 1422 0x68e9, 1423 0x68f1, 1424 0x68f2, 1425 0x68f8, 1426 0x68f9, 1427 0x68fa, 1428 0x68fe, 1429 0x7100, 1430 0x7101, 1431 0x7102, 1432 0x7103, 1433 0x7104, 1434 0x7105, 1435 0x7106, 1436 0x7108, 1437 0x7109, 1438 0x710A, 1439 0x710B, 1440 0x710C, 1441 0x710E, 1442 0x710F, 1443 0x7140, 1444 0x7141, 1445 0x7142, 1446 0x7143, 1447 0x7144, 1448 0x7145, 1449 0x7146, 1450 0x7147, 1451 0x7149, 1452 0x714A, 1453 0x714B, 1454 0x714C, 1455 0x714D, 1456 0x714E, 1457 0x714F, 1458 0x7151, 1459 0x7152, 1460 0x7153, 1461 0x715E, 1462 0x715F, 1463 0x7180, 1464 0x7181, 1465 0x7183, 1466 0x7186, 1467 0x7187, 1468 0x7188, 1469 0x718A, 1470 0x718B, 1471 0x718C, 1472 0x718D, 1473 0x718F, 1474 0x7193, 1475 0x7196, 1476 0x719B, 1477 0x719F, 1478 0x71C0, 1479 0x71C1, 1480 0x71C2, 1481 0x71C3, 1482 0x71C4, 1483 0x71C5, 1484 0x71C6, 1485 0x71C7, 1486 0x71CD, 1487 0x71CE, 1488 0x71D2, 1489 0x71D4, 1490 0x71D5, 1491 0x71D6, 1492 0x71DA, 1493 0x71DE, 1494 0x7200, 1495 0x7210, 1496 0x7211, 1497 0x7240, 1498 0x7243, 1499 0x7244, 1500 0x7245, 1501 0x7246, 1502 0x7247, 1503 0x7248, 1504 0x7249, 1505 0x724A, 1506 0x724B, 1507 0x724C, 1508 0x724D, 1509 0x724E, 1510 0x724F, 1511 0x7280, 1512 0x7281, 1513 0x7283, 1514 0x7284, 1515 0x7287, 1516 0x7288, 1517 0x7289, 1518 0x728B, 1519 0x728C, 1520 0x7290, 1521 0x7291, 1522 0x7293, 1523 0x7297, 1524 0x7834, 1525 0x7835, 1526 0x791e, 1527 0x791f, 1528 0x793f, 1529 0x7941, 1530 0x7942, 1531 0x796c, 1532 0x796d, 1533 0x796e, 1534 0x796f, 1535 0x9400, 1536 0x9401, 1537 0x9402, 1538 0x9403, 1539 0x9405, 1540 0x940A, 1541 0x940B, 1542 0x940F, 1543 0x94A0, 1544 0x94A1, 1545 0x94A3, 1546 0x94B1, 1547 0x94B3, 1548 0x94B4, 1549 0x94B5, 1550 0x94B9, 1551 0x9440, 1552 0x9441, 1553 0x9442, 1554 0x9443, 1555 0x9444, 1556 0x9446, 1557 0x944A, 1558 0x944B, 1559 0x944C, 1560 0x944E, 1561 0x9450, 1562 0x9452, 1563 0x9456, 1564 0x945A, 1565 0x945B, 1566 0x945E, 1567 0x9460, 1568 0x9462, 1569 0x946A, 1570 0x946B, 1571 0x947A, 1572 0x947B, 1573 0x9480, 1574 0x9487, 1575 0x9488, 1576 0x9489, 1577 0x948A, 1578 0x948F, 1579 0x9490, 1580 0x9491, 1581 0x9495, 1582 0x9498, 1583 0x949C, 1584 0x949E, 1585 0x949F, 1586 0x94C0, 1587 0x94C1, 1588 0x94C3, 1589 0x94C4, 1590 0x94C5, 1591 0x94C6, 1592 0x94C7, 1593 0x94C8, 1594 0x94C9, 1595 0x94CB, 1596 0x94CC, 1597 0x94CD, 1598 0x9500, 1599 0x9501, 1600 0x9504, 1601 0x9505, 1602 0x9506, 1603 0x9507, 1604 0x9508, 1605 0x9509, 1606 0x950F, 1607 0x9511, 1608 0x9515, 1609 0x9517, 1610 0x9519, 1611 0x9540, 1612 0x9541, 1613 0x9542, 1614 0x954E, 1615 0x954F, 1616 0x9552, 1617 0x9553, 1618 0x9555, 1619 0x9557, 1620 0x955f, 1621 0x9580, 1622 0x9581, 1623 0x9583, 1624 0x9586, 1625 0x9587, 1626 0x9588, 1627 0x9589, 1628 0x958A, 1629 0x958B, 1630 0x958C, 1631 0x958D, 1632 0x958E, 1633 0x958F, 1634 0x9590, 1635 0x9591, 1636 0x9593, 1637 0x9595, 1638 0x9596, 1639 0x9597, 1640 0x9598, 1641 0x9599, 1642 0x959B, 1643 0x95C0, 1644 0x95C2, 1645 0x95C4, 1646 0x95C5, 1647 0x95C6, 1648 0x95C7, 1649 0x95C9, 1650 0x95CC, 1651 0x95CD, 1652 0x95CE, 1653 0x95CF, 1654 0x9610, 1655 0x9611, 1656 0x9612, 1657 0x9613, 1658 0x9614, 1659 0x9615, 1660 0x9616, 1661 0x9640, 1662 0x9641, 1663 0x9642, 1664 0x9643, 1665 0x9644, 1666 0x9645, 1667 0x9647, 1668 0x9648, 1669 0x9649, 1670 0x964a, 1671 0x964b, 1672 0x964c, 1673 0x964e, 1674 0x964f, 1675 0x9710, 1676 0x9711, 1677 0x9712, 1678 0x9713, 1679 0x9714, 1680 0x9715, 1681 0x9802, 1682 0x9803, 1683 0x9804, 1684 0x9805, 1685 0x9806, 1686 0x9807, 1687 0x9808, 1688 0x9809, 1689 0x980A, 1690 0x9900, 1691 0x9901, 1692 0x9903, 1693 0x9904, 1694 0x9905, 1695 0x9906, 1696 0x9907, 1697 0x9908, 1698 0x9909, 1699 0x990A, 1700 0x990B, 1701 0x990C, 1702 0x990D, 1703 0x990E, 1704 0x990F, 1705 0x9910, 1706 0x9913, 1707 0x9917, 1708 0x9918, 1709 0x9919, 1710 0x9990, 1711 0x9991, 1712 0x9992, 1713 0x9993, 1714 0x9994, 1715 0x9995, 1716 0x9996, 1717 0x9997, 1718 0x9998, 1719 0x9999, 1720 0x999A, 1721 0x999B, 1722 0x999C, 1723 0x999D, 1724 0x99A0, 1725 0x99A2, 1726 0x99A4, 1727 /* radeon secondary ids */ 1728 0x3171, 1729 0x3e70, 1730 0x4164, 1731 0x4165, 1732 0x4166, 1733 0x4168, 1734 0x4170, 1735 0x4171, 1736 0x4172, 1737 0x4173, 1738 0x496e, 1739 0x4a69, 1740 0x4a6a, 1741 0x4a6b, 1742 0x4a70, 1743 0x4a74, 1744 0x4b69, 1745 0x4b6b, 1746 0x4b6c, 1747 0x4c6e, 1748 0x4e64, 1749 0x4e65, 1750 0x4e66, 1751 0x4e67, 1752 0x4e68, 1753 0x4e69, 1754 0x4e6a, 1755 0x4e71, 1756 0x4f73, 1757 0x5569, 1758 0x556b, 1759 0x556d, 1760 0x556f, 1761 0x5571, 1762 0x5854, 1763 0x5874, 1764 0x5940, 1765 0x5941, 1766 0x5b70, 1767 0x5b72, 1768 0x5b73, 1769 0x5b74, 1770 0x5b75, 1771 0x5d44, 1772 0x5d45, 1773 0x5d6d, 1774 0x5d6f, 1775 0x5d72, 1776 0x5d77, 1777 0x5e6b, 1778 0x5e6d, 1779 0x7120, 1780 0x7124, 1781 0x7129, 1782 0x712e, 1783 0x712f, 1784 0x7162, 1785 0x7163, 1786 0x7166, 1787 0x7167, 1788 0x7172, 1789 0x7173, 1790 0x71a0, 1791 0x71a1, 1792 0x71a3, 1793 0x71a7, 1794 0x71bb, 1795 0x71e0, 1796 0x71e1, 1797 0x71e2, 1798 0x71e6, 1799 0x71e7, 1800 0x71f2, 1801 0x7269, 1802 0x726b, 1803 0x726e, 1804 0x72a0, 1805 0x72a8, 1806 0x72b1, 1807 0x72b3, 1808 0x793f, 1809 }; 1810 1811 static const struct pci_device_id pciidlist[] = { 1812 #ifdef CONFIG_DRM_AMDGPU_SI 1813 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1814 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1815 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1816 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1817 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1818 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1819 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1820 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1821 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1822 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1823 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1824 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1825 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1826 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1827 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1828 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1829 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1830 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1831 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1832 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1833 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1834 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1835 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1836 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1837 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1838 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1839 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1840 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1841 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1842 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1843 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1844 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1845 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1846 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1847 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1848 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1849 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1850 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1851 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1852 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1853 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1854 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1855 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1856 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1857 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1858 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1859 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1860 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1861 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1862 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1863 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1864 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1865 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1866 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1867 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1868 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1869 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1870 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1871 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1872 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1873 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1874 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1875 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1876 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1877 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1878 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1879 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1880 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1881 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1882 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1883 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1884 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1885 #endif 1886 #ifdef CONFIG_DRM_AMDGPU_CIK 1887 /* Kaveri */ 1888 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1889 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1890 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1891 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1892 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1893 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1894 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1895 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1896 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1897 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1898 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1899 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1900 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1901 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1902 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1903 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1904 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1905 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1906 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1907 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1908 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1909 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1910 /* Bonaire */ 1911 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1912 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1913 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1914 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1915 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1916 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1917 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1918 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1919 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1920 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1921 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1922 /* Hawaii */ 1923 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1924 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1925 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1926 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1927 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1928 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1929 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1930 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1931 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1932 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1933 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1934 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1935 /* Kabini */ 1936 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1937 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1938 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1939 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1940 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1941 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1942 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1943 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1944 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1945 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1946 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1947 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1948 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1949 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1950 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1951 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1952 /* mullins */ 1953 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1954 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1955 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1956 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1957 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1958 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1959 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1960 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1961 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1962 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1963 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1964 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1965 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1966 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1967 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1968 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1969 #endif 1970 /* topaz */ 1971 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1972 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1973 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1974 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1975 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1976 /* tonga */ 1977 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1978 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1979 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1980 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1981 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1982 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1983 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1984 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1985 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1986 /* fiji */ 1987 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1988 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1989 /* carrizo */ 1990 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1991 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1992 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1993 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1994 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1995 /* stoney */ 1996 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1997 /* Polaris11 */ 1998 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1999 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2000 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2001 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2002 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2003 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2004 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2005 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2006 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 2007 /* Polaris10 */ 2008 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2009 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2010 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2011 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2012 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2013 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2014 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2015 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2016 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2017 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2018 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2019 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2020 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2021 /* Polaris12 */ 2022 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2023 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2024 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2025 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2026 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2027 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2028 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2029 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2030 /* VEGAM */ 2031 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2032 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2033 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2034 /* Vega 10 */ 2035 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2036 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2037 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2038 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2039 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2040 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2041 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2042 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2043 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2044 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2045 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2046 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2047 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2048 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2049 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2050 /* Vega 12 */ 2051 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2052 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2053 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2054 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2055 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2056 /* Vega 20 */ 2057 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2058 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2059 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2060 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2061 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2062 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2063 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2064 /* Raven */ 2065 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2066 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2067 /* Arcturus */ 2068 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2069 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2070 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2071 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2072 /* Navi10 */ 2073 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2074 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2075 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2076 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2077 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2078 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2079 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2080 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2081 /* Navi14 */ 2082 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2083 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2084 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2085 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2086 2087 /* Renoir */ 2088 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2089 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2090 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2091 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2092 2093 /* Navi12 */ 2094 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2095 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2096 2097 /* Sienna_Cichlid */ 2098 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2099 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2100 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2101 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2102 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2103 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2104 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2105 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2106 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2107 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2108 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2109 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2110 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2111 2112 /* Yellow Carp */ 2113 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2114 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2115 2116 /* Navy_Flounder */ 2117 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2118 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2119 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2120 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2121 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2122 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2123 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2124 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2125 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2126 2127 /* DIMGREY_CAVEFISH */ 2128 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2129 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2130 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2131 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2132 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2133 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2134 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2135 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2136 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2137 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2138 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2139 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2140 2141 /* Aldebaran */ 2142 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2143 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2144 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2145 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2146 2147 /* CYAN_SKILLFISH */ 2148 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2149 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2150 2151 /* BEIGE_GOBY */ 2152 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2153 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2154 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2155 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2156 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2157 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2158 2159 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2160 .class = PCI_CLASS_DISPLAY_VGA << 8, 2161 .class_mask = 0xffffff, 2162 .driver_data = CHIP_IP_DISCOVERY }, 2163 2164 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2165 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2166 .class_mask = 0xffffff, 2167 .driver_data = CHIP_IP_DISCOVERY }, 2168 2169 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2170 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2171 .class_mask = 0xffffff, 2172 .driver_data = CHIP_IP_DISCOVERY }, 2173 2174 {0, 0, 0} 2175 }; 2176 2177 MODULE_DEVICE_TABLE(pci, pciidlist); 2178 2179 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2180 /* differentiate between P10 and P11 asics with the same DID */ 2181 {0x67FF, 0xE3, CHIP_POLARIS10}, 2182 {0x67FF, 0xE7, CHIP_POLARIS10}, 2183 {0x67FF, 0xF3, CHIP_POLARIS10}, 2184 {0x67FF, 0xF7, CHIP_POLARIS10}, 2185 }; 2186 2187 static const struct drm_driver amdgpu_kms_driver; 2188 2189 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2190 { 2191 struct pci_dev *p = NULL; 2192 int i; 2193 2194 /* 0 - GPU 2195 * 1 - audio 2196 * 2 - USB 2197 * 3 - UCSI 2198 */ 2199 for (i = 1; i < 4; i++) { 2200 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2201 adev->pdev->bus->number, i); 2202 if (p) { 2203 pm_runtime_get_sync(&p->dev); 2204 pm_runtime_mark_last_busy(&p->dev); 2205 pm_runtime_put_autosuspend(&p->dev); 2206 pci_dev_put(p); 2207 } 2208 } 2209 } 2210 2211 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2212 { 2213 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2214 pr_info("debug: VM handling debug enabled\n"); 2215 adev->debug_vm = true; 2216 } 2217 2218 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2219 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2220 adev->debug_largebar = true; 2221 } 2222 2223 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2224 pr_info("debug: soft reset for GPU recovery disabled\n"); 2225 adev->debug_disable_soft_recovery = true; 2226 } 2227 2228 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2229 pr_info("debug: place fw in vram for frontdoor loading\n"); 2230 adev->debug_use_vram_fw_buf = true; 2231 } 2232 2233 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) { 2234 pr_info("debug: enable RAS ACA\n"); 2235 adev->debug_enable_ras_aca = true; 2236 } 2237 2238 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) { 2239 pr_info("debug: enable experimental reset features\n"); 2240 adev->debug_exp_resets = true; 2241 } 2242 2243 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_RING_RESET) { 2244 pr_info("debug: ring reset disabled\n"); 2245 adev->debug_disable_gpu_ring_reset = true; 2246 } 2247 if (amdgpu_debug_mask & AMDGPU_DEBUG_SMU_POOL) { 2248 pr_info("debug: use vram for smu pool\n"); 2249 adev->pm.smu_debug_mask |= SMU_DEBUG_POOL_USE_VRAM; 2250 } 2251 } 2252 2253 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2254 { 2255 int i; 2256 2257 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2258 if (pdev->device == asic_type_quirks[i].device && 2259 pdev->revision == asic_type_quirks[i].revision) { 2260 flags &= ~AMD_ASIC_MASK; 2261 flags |= asic_type_quirks[i].type; 2262 break; 2263 } 2264 } 2265 2266 return flags; 2267 } 2268 2269 static int amdgpu_pci_probe(struct pci_dev *pdev, 2270 const struct pci_device_id *ent) 2271 { 2272 struct drm_device *ddev; 2273 struct amdgpu_device *adev; 2274 unsigned long flags = ent->driver_data; 2275 int ret, retry = 0, i; 2276 bool supports_atomic = false; 2277 2278 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA || 2279 (pdev->class >> 8) == PCI_CLASS_DISPLAY_OTHER) { 2280 if (drm_firmware_drivers_only() && amdgpu_modeset == -1) 2281 return -EINVAL; 2282 } 2283 2284 /* skip devices which are owned by radeon */ 2285 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2286 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2287 return -ENODEV; 2288 } 2289 2290 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2291 amdgpu_aspm = 0; 2292 2293 if (amdgpu_virtual_display || 2294 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2295 supports_atomic = true; 2296 2297 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2298 DRM_INFO("This hardware requires experimental hardware support.\n" 2299 "See modparam exp_hw_support\n"); 2300 return -ENODEV; 2301 } 2302 2303 flags = amdgpu_fix_asic_type(pdev, flags); 2304 2305 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2306 * however, SME requires an indirect IOMMU mapping because the encryption 2307 * bit is beyond the DMA mask of the chip. 2308 */ 2309 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2310 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2311 dev_info(&pdev->dev, 2312 "SME is not compatible with RAVEN\n"); 2313 return -ENOTSUPP; 2314 } 2315 2316 #ifdef CONFIG_DRM_AMDGPU_SI 2317 if (!amdgpu_si_support) { 2318 switch (flags & AMD_ASIC_MASK) { 2319 case CHIP_TAHITI: 2320 case CHIP_PITCAIRN: 2321 case CHIP_VERDE: 2322 case CHIP_OLAND: 2323 case CHIP_HAINAN: 2324 dev_info(&pdev->dev, 2325 "SI support provided by radeon.\n"); 2326 dev_info(&pdev->dev, 2327 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2328 ); 2329 return -ENODEV; 2330 } 2331 } 2332 #endif 2333 #ifdef CONFIG_DRM_AMDGPU_CIK 2334 if (!amdgpu_cik_support) { 2335 switch (flags & AMD_ASIC_MASK) { 2336 case CHIP_KAVERI: 2337 case CHIP_BONAIRE: 2338 case CHIP_HAWAII: 2339 case CHIP_KABINI: 2340 case CHIP_MULLINS: 2341 dev_info(&pdev->dev, 2342 "CIK support provided by radeon.\n"); 2343 dev_info(&pdev->dev, 2344 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2345 ); 2346 return -ENODEV; 2347 } 2348 } 2349 #endif 2350 2351 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2352 if (IS_ERR(adev)) 2353 return PTR_ERR(adev); 2354 2355 adev->dev = &pdev->dev; 2356 adev->pdev = pdev; 2357 ddev = adev_to_drm(adev); 2358 2359 if (!supports_atomic) 2360 ddev->driver_features &= ~DRIVER_ATOMIC; 2361 2362 ret = pci_enable_device(pdev); 2363 if (ret) 2364 return ret; 2365 2366 pci_set_drvdata(pdev, ddev); 2367 2368 amdgpu_init_debug_options(adev); 2369 2370 ret = amdgpu_driver_load_kms(adev, flags); 2371 if (ret) 2372 goto err_pci; 2373 2374 retry_init: 2375 ret = drm_dev_register(ddev, flags); 2376 if (ret == -EAGAIN && ++retry <= 3) { 2377 DRM_INFO("retry init %d\n", retry); 2378 /* Don't request EX mode too frequently which is attacking */ 2379 msleep(5000); 2380 goto retry_init; 2381 } else if (ret) { 2382 goto err_pci; 2383 } 2384 2385 ret = amdgpu_xcp_dev_register(adev, ent); 2386 if (ret) 2387 goto err_pci; 2388 2389 ret = amdgpu_amdkfd_drm_client_create(adev); 2390 if (ret) 2391 goto err_pci; 2392 2393 /* 2394 * 1. don't init fbdev on hw without DCE 2395 * 2. don't init fbdev if there are no connectors 2396 */ 2397 if (adev->mode_info.mode_config_initialized && 2398 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2399 const struct drm_format_info *format; 2400 2401 /* select 8 bpp console on low vram cards */ 2402 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2403 format = drm_format_info(DRM_FORMAT_C8); 2404 else 2405 format = NULL; 2406 2407 drm_client_setup(adev_to_drm(adev), format); 2408 } 2409 2410 ret = amdgpu_debugfs_init(adev); 2411 if (ret) 2412 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2413 2414 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2415 /* only need to skip on ATPX */ 2416 if (amdgpu_device_supports_px(ddev)) 2417 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2418 /* we want direct complete for BOCO */ 2419 if (amdgpu_device_supports_boco(ddev)) 2420 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2421 DPM_FLAG_SMART_SUSPEND | 2422 DPM_FLAG_MAY_SKIP_RESUME); 2423 pm_runtime_use_autosuspend(ddev->dev); 2424 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2425 2426 pm_runtime_allow(ddev->dev); 2427 2428 pm_runtime_mark_last_busy(ddev->dev); 2429 pm_runtime_put_autosuspend(ddev->dev); 2430 2431 pci_wake_from_d3(pdev, TRUE); 2432 2433 /* 2434 * For runpm implemented via BACO, PMFW will handle the 2435 * timing for BACO in and out: 2436 * - put ASIC into BACO state only when both video and 2437 * audio functions are in D3 state. 2438 * - pull ASIC out of BACO state when either video or 2439 * audio function is in D0 state. 2440 * Also, at startup, PMFW assumes both functions are in 2441 * D0 state. 2442 * 2443 * So if snd driver was loaded prior to amdgpu driver 2444 * and audio function was put into D3 state, there will 2445 * be no PMFW-aware D-state transition(D0->D3) on runpm 2446 * suspend. Thus the BACO will be not correctly kicked in. 2447 * 2448 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2449 * into D0 state. Then there will be a PMFW-aware D-state 2450 * transition(D0->D3) on runpm suspend. 2451 */ 2452 if (amdgpu_device_supports_baco(ddev) && 2453 !(adev->flags & AMD_IS_APU) && 2454 (adev->asic_type >= CHIP_NAVI10)) 2455 amdgpu_get_secondary_funcs(adev); 2456 } 2457 2458 return 0; 2459 2460 err_pci: 2461 pci_disable_device(pdev); 2462 return ret; 2463 } 2464 2465 static void 2466 amdgpu_pci_remove(struct pci_dev *pdev) 2467 { 2468 struct drm_device *dev = pci_get_drvdata(pdev); 2469 struct amdgpu_device *adev = drm_to_adev(dev); 2470 2471 amdgpu_xcp_dev_unplug(adev); 2472 amdgpu_gmc_prepare_nps_mode_change(adev); 2473 drm_dev_unplug(dev); 2474 2475 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2476 pm_runtime_get_sync(dev->dev); 2477 pm_runtime_forbid(dev->dev); 2478 } 2479 2480 amdgpu_driver_unload_kms(dev); 2481 2482 /* 2483 * Flush any in flight DMA operations from device. 2484 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2485 * StatusTransactions Pending bit. 2486 */ 2487 pci_disable_device(pdev); 2488 pci_wait_for_pending_transaction(pdev); 2489 } 2490 2491 static void 2492 amdgpu_pci_shutdown(struct pci_dev *pdev) 2493 { 2494 struct drm_device *dev = pci_get_drvdata(pdev); 2495 struct amdgpu_device *adev = drm_to_adev(dev); 2496 2497 if (amdgpu_ras_intr_triggered()) 2498 return; 2499 2500 /* if we are running in a VM, make sure the device 2501 * torn down properly on reboot/shutdown. 2502 * unfortunately we can't detect certain 2503 * hypervisors so just do this all the time. 2504 */ 2505 if (!amdgpu_passthrough(adev)) 2506 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2507 amdgpu_device_ip_suspend(adev); 2508 adev->mp1_state = PP_MP1_STATE_NONE; 2509 } 2510 2511 static int amdgpu_pmops_prepare(struct device *dev) 2512 { 2513 struct drm_device *drm_dev = dev_get_drvdata(dev); 2514 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2515 2516 /* Return a positive number here so 2517 * DPM_FLAG_SMART_SUSPEND works properly 2518 */ 2519 if (amdgpu_device_supports_boco(drm_dev) && 2520 pm_runtime_suspended(dev)) 2521 return 1; 2522 2523 /* if we will not support s3 or s2i for the device 2524 * then skip suspend 2525 */ 2526 if (!amdgpu_acpi_is_s0ix_active(adev) && 2527 !amdgpu_acpi_is_s3_active(adev)) 2528 return 1; 2529 2530 return amdgpu_device_prepare(drm_dev); 2531 } 2532 2533 static void amdgpu_pmops_complete(struct device *dev) 2534 { 2535 /* nothing to do */ 2536 } 2537 2538 static int amdgpu_pmops_suspend(struct device *dev) 2539 { 2540 struct drm_device *drm_dev = dev_get_drvdata(dev); 2541 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2542 2543 if (amdgpu_acpi_is_s0ix_active(adev)) 2544 adev->in_s0ix = true; 2545 else if (amdgpu_acpi_is_s3_active(adev)) 2546 adev->in_s3 = true; 2547 if (!adev->in_s0ix && !adev->in_s3) 2548 return 0; 2549 return amdgpu_device_suspend(drm_dev, true); 2550 } 2551 2552 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2553 { 2554 struct drm_device *drm_dev = dev_get_drvdata(dev); 2555 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2556 2557 if (amdgpu_acpi_should_gpu_reset(adev)) 2558 return amdgpu_asic_reset(adev); 2559 2560 return 0; 2561 } 2562 2563 static int amdgpu_pmops_resume(struct device *dev) 2564 { 2565 struct drm_device *drm_dev = dev_get_drvdata(dev); 2566 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2567 int r; 2568 2569 if (!adev->in_s0ix && !adev->in_s3) 2570 return 0; 2571 2572 /* Avoids registers access if device is physically gone */ 2573 if (!pci_device_is_present(adev->pdev)) 2574 adev->no_hw_access = true; 2575 2576 r = amdgpu_device_resume(drm_dev, true); 2577 if (amdgpu_acpi_is_s0ix_active(adev)) 2578 adev->in_s0ix = false; 2579 else 2580 adev->in_s3 = false; 2581 return r; 2582 } 2583 2584 static int amdgpu_pmops_freeze(struct device *dev) 2585 { 2586 struct drm_device *drm_dev = dev_get_drvdata(dev); 2587 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2588 int r; 2589 2590 r = amdgpu_device_suspend(drm_dev, true); 2591 if (r) 2592 return r; 2593 2594 if (amdgpu_acpi_should_gpu_reset(adev)) 2595 return amdgpu_asic_reset(adev); 2596 return 0; 2597 } 2598 2599 static int amdgpu_pmops_thaw(struct device *dev) 2600 { 2601 struct drm_device *drm_dev = dev_get_drvdata(dev); 2602 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2603 int r; 2604 2605 r = amdgpu_device_resume(drm_dev, true); 2606 adev->in_s4 = false; 2607 2608 return r; 2609 } 2610 2611 static int amdgpu_pmops_poweroff(struct device *dev) 2612 { 2613 struct drm_device *drm_dev = dev_get_drvdata(dev); 2614 2615 return amdgpu_device_suspend(drm_dev, true); 2616 } 2617 2618 static int amdgpu_pmops_restore(struct device *dev) 2619 { 2620 struct drm_device *drm_dev = dev_get_drvdata(dev); 2621 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2622 2623 adev->in_s4 = false; 2624 2625 return amdgpu_device_resume(drm_dev, true); 2626 } 2627 2628 static int amdgpu_runtime_idle_check_display(struct device *dev) 2629 { 2630 struct pci_dev *pdev = to_pci_dev(dev); 2631 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2632 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2633 2634 if (adev->mode_info.num_crtc) { 2635 struct drm_connector *list_connector; 2636 struct drm_connector_list_iter iter; 2637 int ret = 0; 2638 2639 if (amdgpu_runtime_pm != -2) { 2640 /* XXX: Return busy if any displays are connected to avoid 2641 * possible display wakeups after runtime resume due to 2642 * hotplug events in case any displays were connected while 2643 * the GPU was in suspend. Remove this once that is fixed. 2644 */ 2645 mutex_lock(&drm_dev->mode_config.mutex); 2646 drm_connector_list_iter_begin(drm_dev, &iter); 2647 drm_for_each_connector_iter(list_connector, &iter) { 2648 if (list_connector->status == connector_status_connected) { 2649 ret = -EBUSY; 2650 break; 2651 } 2652 } 2653 drm_connector_list_iter_end(&iter); 2654 mutex_unlock(&drm_dev->mode_config.mutex); 2655 2656 if (ret) 2657 return ret; 2658 } 2659 2660 if (adev->dc_enabled) { 2661 struct drm_crtc *crtc; 2662 2663 drm_for_each_crtc(crtc, drm_dev) { 2664 drm_modeset_lock(&crtc->mutex, NULL); 2665 if (crtc->state->active) 2666 ret = -EBUSY; 2667 drm_modeset_unlock(&crtc->mutex); 2668 if (ret < 0) 2669 break; 2670 } 2671 } else { 2672 mutex_lock(&drm_dev->mode_config.mutex); 2673 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2674 2675 drm_connector_list_iter_begin(drm_dev, &iter); 2676 drm_for_each_connector_iter(list_connector, &iter) { 2677 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2678 ret = -EBUSY; 2679 break; 2680 } 2681 } 2682 2683 drm_connector_list_iter_end(&iter); 2684 2685 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2686 mutex_unlock(&drm_dev->mode_config.mutex); 2687 } 2688 if (ret) 2689 return ret; 2690 } 2691 2692 return 0; 2693 } 2694 2695 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2696 { 2697 struct pci_dev *pdev = to_pci_dev(dev); 2698 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2699 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2700 int ret, i; 2701 2702 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2703 pm_runtime_forbid(dev); 2704 return -EBUSY; 2705 } 2706 2707 ret = amdgpu_runtime_idle_check_display(dev); 2708 if (ret) 2709 return ret; 2710 2711 /* wait for all rings to drain before suspending */ 2712 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2713 struct amdgpu_ring *ring = adev->rings[i]; 2714 2715 if (ring && ring->sched.ready) { 2716 ret = amdgpu_fence_wait_empty(ring); 2717 if (ret) 2718 return -EBUSY; 2719 } 2720 } 2721 2722 adev->in_runpm = true; 2723 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2724 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2725 2726 /* 2727 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2728 * proper cleanups and put itself into a state ready for PNP. That 2729 * can address some random resuming failure observed on BOCO capable 2730 * platforms. 2731 * TODO: this may be also needed for PX capable platform. 2732 */ 2733 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2734 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2735 2736 ret = amdgpu_device_prepare(drm_dev); 2737 if (ret) 2738 return ret; 2739 ret = amdgpu_device_suspend(drm_dev, false); 2740 if (ret) { 2741 adev->in_runpm = false; 2742 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2743 adev->mp1_state = PP_MP1_STATE_NONE; 2744 return ret; 2745 } 2746 2747 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2748 adev->mp1_state = PP_MP1_STATE_NONE; 2749 2750 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2751 /* Only need to handle PCI state in the driver for ATPX 2752 * PCI core handles it for _PR3. 2753 */ 2754 amdgpu_device_cache_pci_state(pdev); 2755 pci_disable_device(pdev); 2756 pci_ignore_hotplug(pdev); 2757 pci_set_power_state(pdev, PCI_D3cold); 2758 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2759 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2760 /* nothing to do */ 2761 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2762 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2763 amdgpu_device_baco_enter(drm_dev); 2764 } 2765 2766 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2767 2768 return 0; 2769 } 2770 2771 static int amdgpu_pmops_runtime_resume(struct device *dev) 2772 { 2773 struct pci_dev *pdev = to_pci_dev(dev); 2774 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2775 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2776 int ret; 2777 2778 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2779 return -EINVAL; 2780 2781 /* Avoids registers access if device is physically gone */ 2782 if (!pci_device_is_present(adev->pdev)) 2783 adev->no_hw_access = true; 2784 2785 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2786 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2787 2788 /* Only need to handle PCI state in the driver for ATPX 2789 * PCI core handles it for _PR3. 2790 */ 2791 pci_set_power_state(pdev, PCI_D0); 2792 amdgpu_device_load_pci_state(pdev); 2793 ret = pci_enable_device(pdev); 2794 if (ret) 2795 return ret; 2796 pci_set_master(pdev); 2797 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2798 /* Only need to handle PCI state in the driver for ATPX 2799 * PCI core handles it for _PR3. 2800 */ 2801 pci_set_master(pdev); 2802 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2803 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2804 amdgpu_device_baco_exit(drm_dev); 2805 } 2806 ret = amdgpu_device_resume(drm_dev, false); 2807 if (ret) { 2808 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2809 pci_disable_device(pdev); 2810 return ret; 2811 } 2812 2813 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2814 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2815 adev->in_runpm = false; 2816 return 0; 2817 } 2818 2819 static int amdgpu_pmops_runtime_idle(struct device *dev) 2820 { 2821 struct drm_device *drm_dev = dev_get_drvdata(dev); 2822 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2823 int ret; 2824 2825 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2826 pm_runtime_forbid(dev); 2827 return -EBUSY; 2828 } 2829 2830 ret = amdgpu_runtime_idle_check_display(dev); 2831 2832 pm_runtime_mark_last_busy(dev); 2833 pm_runtime_autosuspend(dev); 2834 return ret; 2835 } 2836 2837 long amdgpu_drm_ioctl(struct file *filp, 2838 unsigned int cmd, unsigned long arg) 2839 { 2840 struct drm_file *file_priv = filp->private_data; 2841 struct drm_device *dev; 2842 long ret; 2843 2844 dev = file_priv->minor->dev; 2845 ret = pm_runtime_get_sync(dev->dev); 2846 if (ret < 0) 2847 goto out; 2848 2849 ret = drm_ioctl(filp, cmd, arg); 2850 2851 pm_runtime_mark_last_busy(dev->dev); 2852 out: 2853 pm_runtime_put_autosuspend(dev->dev); 2854 return ret; 2855 } 2856 2857 static const struct dev_pm_ops amdgpu_pm_ops = { 2858 .prepare = amdgpu_pmops_prepare, 2859 .complete = amdgpu_pmops_complete, 2860 .suspend = amdgpu_pmops_suspend, 2861 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2862 .resume = amdgpu_pmops_resume, 2863 .freeze = amdgpu_pmops_freeze, 2864 .thaw = amdgpu_pmops_thaw, 2865 .poweroff = amdgpu_pmops_poweroff, 2866 .restore = amdgpu_pmops_restore, 2867 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2868 .runtime_resume = amdgpu_pmops_runtime_resume, 2869 .runtime_idle = amdgpu_pmops_runtime_idle, 2870 }; 2871 2872 static int amdgpu_flush(struct file *f, fl_owner_t id) 2873 { 2874 struct drm_file *file_priv = f->private_data; 2875 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2876 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2877 2878 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2879 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2880 2881 return timeout >= 0 ? 0 : timeout; 2882 } 2883 2884 static const struct file_operations amdgpu_driver_kms_fops = { 2885 .owner = THIS_MODULE, 2886 .open = drm_open, 2887 .flush = amdgpu_flush, 2888 .release = drm_release, 2889 .unlocked_ioctl = amdgpu_drm_ioctl, 2890 .mmap = drm_gem_mmap, 2891 .poll = drm_poll, 2892 .read = drm_read, 2893 #ifdef CONFIG_COMPAT 2894 .compat_ioctl = amdgpu_kms_compat_ioctl, 2895 #endif 2896 #ifdef CONFIG_PROC_FS 2897 .show_fdinfo = drm_show_fdinfo, 2898 #endif 2899 .fop_flags = FOP_UNSIGNED_OFFSET, 2900 }; 2901 2902 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2903 { 2904 struct drm_file *file; 2905 2906 if (!filp) 2907 return -EINVAL; 2908 2909 if (filp->f_op != &amdgpu_driver_kms_fops) 2910 return -EINVAL; 2911 2912 file = filp->private_data; 2913 *fpriv = file->driver_priv; 2914 return 0; 2915 } 2916 2917 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2918 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2919 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2920 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2921 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2922 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2923 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2924 /* KMS */ 2925 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2926 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2927 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2928 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2929 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2930 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2931 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2932 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2933 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2934 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2935 }; 2936 2937 static const struct drm_driver amdgpu_kms_driver = { 2938 .driver_features = 2939 DRIVER_ATOMIC | 2940 DRIVER_GEM | 2941 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2942 DRIVER_SYNCOBJ_TIMELINE, 2943 .open = amdgpu_driver_open_kms, 2944 .postclose = amdgpu_driver_postclose_kms, 2945 .ioctls = amdgpu_ioctls_kms, 2946 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2947 .dumb_create = amdgpu_mode_dumb_create, 2948 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2949 DRM_FBDEV_TTM_DRIVER_OPS, 2950 .fops = &amdgpu_driver_kms_fops, 2951 .release = &amdgpu_driver_release_kms, 2952 #ifdef CONFIG_PROC_FS 2953 .show_fdinfo = amdgpu_show_fdinfo, 2954 #endif 2955 2956 .gem_prime_import = amdgpu_gem_prime_import, 2957 2958 .name = DRIVER_NAME, 2959 .desc = DRIVER_DESC, 2960 .major = KMS_DRIVER_MAJOR, 2961 .minor = KMS_DRIVER_MINOR, 2962 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2963 }; 2964 2965 const struct drm_driver amdgpu_partition_driver = { 2966 .driver_features = 2967 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 2968 DRIVER_SYNCOBJ_TIMELINE, 2969 .open = amdgpu_driver_open_kms, 2970 .postclose = amdgpu_driver_postclose_kms, 2971 .ioctls = amdgpu_ioctls_kms, 2972 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2973 .dumb_create = amdgpu_mode_dumb_create, 2974 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2975 DRM_FBDEV_TTM_DRIVER_OPS, 2976 .fops = &amdgpu_driver_kms_fops, 2977 .release = &amdgpu_driver_release_kms, 2978 2979 .gem_prime_import = amdgpu_gem_prime_import, 2980 2981 .name = DRIVER_NAME, 2982 .desc = DRIVER_DESC, 2983 .major = KMS_DRIVER_MAJOR, 2984 .minor = KMS_DRIVER_MINOR, 2985 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2986 }; 2987 2988 static struct pci_error_handlers amdgpu_pci_err_handler = { 2989 .error_detected = amdgpu_pci_error_detected, 2990 .mmio_enabled = amdgpu_pci_mmio_enabled, 2991 .slot_reset = amdgpu_pci_slot_reset, 2992 .resume = amdgpu_pci_resume, 2993 }; 2994 2995 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2996 &amdgpu_vram_mgr_attr_group, 2997 &amdgpu_gtt_mgr_attr_group, 2998 &amdgpu_flash_attr_group, 2999 NULL, 3000 }; 3001 3002 static struct pci_driver amdgpu_kms_pci_driver = { 3003 .name = DRIVER_NAME, 3004 .id_table = pciidlist, 3005 .probe = amdgpu_pci_probe, 3006 .remove = amdgpu_pci_remove, 3007 .shutdown = amdgpu_pci_shutdown, 3008 .driver.pm = &amdgpu_pm_ops, 3009 .err_handler = &amdgpu_pci_err_handler, 3010 .dev_groups = amdgpu_sysfs_groups, 3011 }; 3012 3013 static int __init amdgpu_init(void) 3014 { 3015 int r; 3016 3017 r = amdgpu_sync_init(); 3018 if (r) 3019 goto error_sync; 3020 3021 r = amdgpu_fence_slab_init(); 3022 if (r) 3023 goto error_fence; 3024 3025 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 3026 amdgpu_register_atpx_handler(); 3027 amdgpu_acpi_detect(); 3028 3029 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 3030 amdgpu_amdkfd_init(); 3031 3032 if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) { 3033 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 3034 pr_crit("Overdrive is enabled, please disable it before " 3035 "reporting any bugs unrelated to overdrive.\n"); 3036 } 3037 3038 /* let modprobe override vga console setting */ 3039 return pci_register_driver(&amdgpu_kms_pci_driver); 3040 3041 error_fence: 3042 amdgpu_sync_fini(); 3043 3044 error_sync: 3045 return r; 3046 } 3047 3048 static void __exit amdgpu_exit(void) 3049 { 3050 amdgpu_amdkfd_fini(); 3051 pci_unregister_driver(&amdgpu_kms_pci_driver); 3052 amdgpu_unregister_atpx_handler(); 3053 amdgpu_acpi_release(); 3054 amdgpu_sync_fini(); 3055 amdgpu_fence_slab_fini(); 3056 mmu_notifier_synchronize(); 3057 amdgpu_xcp_drv_release(); 3058 } 3059 3060 module_init(amdgpu_init); 3061 module_exit(amdgpu_exit); 3062 3063 MODULE_AUTHOR(DRIVER_AUTHOR); 3064 MODULE_DESCRIPTION(DRIVER_DESC); 3065 MODULE_LICENSE("GPL and additional rights"); 3066