1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * based on nouveau_prime.c
23 *
24 * Authors: Alex Deucher
25 */
26
27 /**
28 * DOC: PRIME Buffer Sharing
29 *
30 * The following callback implementations are used for :ref:`sharing GEM buffer
31 * objects between different devices via PRIME <prime_buffer_sharing>`.
32 */
33
34 #include "amdgpu.h"
35 #include "amdgpu_display.h"
36 #include "amdgpu_gem.h"
37 #include "amdgpu_dma_buf.h"
38 #include "amdgpu_xgmi.h"
39 #include "amdgpu_vm.h"
40 #include <drm/amdgpu_drm.h>
41 #include <drm/ttm/ttm_tt.h>
42 #include <linux/dma-buf.h>
43 #include <linux/dma-fence-array.h>
44 #include <linux/pci-p2pdma.h>
45
46 /**
47 * amdgpu_dma_buf_attach - &dma_buf_ops.attach implementation
48 *
49 * @dmabuf: DMA-buf where we attach to
50 * @attach: attachment to add
51 *
52 * Add the attachment as user to the exported DMA-buf.
53 */
amdgpu_dma_buf_attach(struct dma_buf * dmabuf,struct dma_buf_attachment * attach)54 static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf,
55 struct dma_buf_attachment *attach)
56 {
57 struct drm_gem_object *obj = dmabuf->priv;
58 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
59 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
60
61 if (pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0)
62 attach->peer2peer = false;
63
64 amdgpu_vm_bo_update_shared(bo);
65
66 return 0;
67 }
68
69 /**
70 * amdgpu_dma_buf_pin - &dma_buf_ops.pin implementation
71 *
72 * @attach: attachment to pin down
73 *
74 * Pin the BO which is backing the DMA-buf so that it can't move any more.
75 */
amdgpu_dma_buf_pin(struct dma_buf_attachment * attach)76 static int amdgpu_dma_buf_pin(struct dma_buf_attachment *attach)
77 {
78 struct drm_gem_object *obj = attach->dmabuf->priv;
79 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
80
81 /* pin buffer into GTT */
82 return amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
83 }
84
85 /**
86 * amdgpu_dma_buf_unpin - &dma_buf_ops.unpin implementation
87 *
88 * @attach: attachment to unpin
89 *
90 * Unpin a previously pinned BO to make it movable again.
91 */
amdgpu_dma_buf_unpin(struct dma_buf_attachment * attach)92 static void amdgpu_dma_buf_unpin(struct dma_buf_attachment *attach)
93 {
94 struct drm_gem_object *obj = attach->dmabuf->priv;
95 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
96
97 amdgpu_bo_unpin(bo);
98 }
99
100 /**
101 * amdgpu_dma_buf_map - &dma_buf_ops.map_dma_buf implementation
102 * @attach: DMA-buf attachment
103 * @dir: DMA direction
104 *
105 * Makes sure that the shared DMA buffer can be accessed by the target device.
106 * For now, simply pins it to the GTT domain, where it should be accessible by
107 * all DMA devices.
108 *
109 * Returns:
110 * sg_table filled with the DMA addresses to use or ERR_PRT with negative error
111 * code.
112 */
amdgpu_dma_buf_map(struct dma_buf_attachment * attach,enum dma_data_direction dir)113 static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach,
114 enum dma_data_direction dir)
115 {
116 struct dma_buf *dma_buf = attach->dmabuf;
117 struct drm_gem_object *obj = dma_buf->priv;
118 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
119 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
120 struct sg_table *sgt;
121 long r;
122
123 if (!bo->tbo.pin_count) {
124 /* move buffer into GTT or VRAM */
125 struct ttm_operation_ctx ctx = { false, false };
126 unsigned int domains = AMDGPU_GEM_DOMAIN_GTT;
127
128 if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM &&
129 attach->peer2peer) {
130 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
131 domains |= AMDGPU_GEM_DOMAIN_VRAM;
132 }
133 amdgpu_bo_placement_from_domain(bo, domains);
134 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
135 if (r)
136 return ERR_PTR(r);
137
138 } else if (bo->tbo.resource->mem_type != TTM_PL_TT) {
139 return ERR_PTR(-EBUSY);
140 }
141
142 switch (bo->tbo.resource->mem_type) {
143 case TTM_PL_TT:
144 sgt = drm_prime_pages_to_sg(obj->dev,
145 bo->tbo.ttm->pages,
146 bo->tbo.ttm->num_pages);
147 if (IS_ERR(sgt))
148 return sgt;
149
150 if (dma_map_sgtable(attach->dev, sgt, dir,
151 DMA_ATTR_SKIP_CPU_SYNC))
152 goto error_free;
153 break;
154
155 case TTM_PL_VRAM:
156 r = amdgpu_vram_mgr_alloc_sgt(adev, bo->tbo.resource, 0,
157 bo->tbo.base.size, attach->dev,
158 dir, &sgt);
159 if (r)
160 return ERR_PTR(r);
161 break;
162 default:
163 return ERR_PTR(-EINVAL);
164 }
165
166 return sgt;
167
168 error_free:
169 sg_free_table(sgt);
170 kfree(sgt);
171 return ERR_PTR(-EBUSY);
172 }
173
174 /**
175 * amdgpu_dma_buf_unmap - &dma_buf_ops.unmap_dma_buf implementation
176 * @attach: DMA-buf attachment
177 * @sgt: sg_table to unmap
178 * @dir: DMA direction
179 *
180 * This is called when a shared DMA buffer no longer needs to be accessible by
181 * another device. For now, simply unpins the buffer from GTT.
182 */
amdgpu_dma_buf_unmap(struct dma_buf_attachment * attach,struct sg_table * sgt,enum dma_data_direction dir)183 static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach,
184 struct sg_table *sgt,
185 enum dma_data_direction dir)
186 {
187 if (sgt->sgl->page_link) {
188 dma_unmap_sgtable(attach->dev, sgt, dir, 0);
189 sg_free_table(sgt);
190 kfree(sgt);
191 } else {
192 amdgpu_vram_mgr_free_sgt(attach->dev, dir, sgt);
193 }
194 }
195
196 /**
197 * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation
198 * @dma_buf: Shared DMA buffer
199 * @direction: Direction of DMA transfer
200 *
201 * This is called before CPU access to the shared DMA buffer's memory. If it's
202 * a read access, the buffer is moved to the GTT domain if possible, for optimal
203 * CPU read performance.
204 *
205 * Returns:
206 * 0 on success or a negative error code on failure.
207 */
amdgpu_dma_buf_begin_cpu_access(struct dma_buf * dma_buf,enum dma_data_direction direction)208 static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,
209 enum dma_data_direction direction)
210 {
211 struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
212 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
213 struct ttm_operation_ctx ctx = { true, false };
214 u32 domain = amdgpu_display_supported_domains(adev, bo->flags);
215 int ret;
216 bool reads = (direction == DMA_BIDIRECTIONAL ||
217 direction == DMA_FROM_DEVICE);
218
219 if (!reads || !(domain & AMDGPU_GEM_DOMAIN_GTT))
220 return 0;
221
222 /* move to gtt */
223 ret = amdgpu_bo_reserve(bo, false);
224 if (unlikely(ret != 0))
225 return ret;
226
227 if (!bo->tbo.pin_count &&
228 (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
229 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
230 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
231 }
232
233 amdgpu_bo_unreserve(bo);
234 return ret;
235 }
236
237 const struct dma_buf_ops amdgpu_dmabuf_ops = {
238 .attach = amdgpu_dma_buf_attach,
239 .pin = amdgpu_dma_buf_pin,
240 .unpin = amdgpu_dma_buf_unpin,
241 .map_dma_buf = amdgpu_dma_buf_map,
242 .unmap_dma_buf = amdgpu_dma_buf_unmap,
243 .release = drm_gem_dmabuf_release,
244 .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access,
245 .mmap = drm_gem_dmabuf_mmap,
246 .vmap = drm_gem_dmabuf_vmap,
247 .vunmap = drm_gem_dmabuf_vunmap,
248 };
249
250 /**
251 * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation
252 * @gobj: GEM BO
253 * @flags: Flags such as DRM_CLOEXEC and DRM_RDWR.
254 *
255 * The main work is done by the &drm_gem_prime_export helper.
256 *
257 * Returns:
258 * Shared DMA buffer representing the GEM BO from the given device.
259 */
amdgpu_gem_prime_export(struct drm_gem_object * gobj,int flags)260 struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj,
261 int flags)
262 {
263 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
264 struct dma_buf *buf;
265
266 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
267 bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
268 return ERR_PTR(-EPERM);
269
270 buf = drm_gem_prime_export(gobj, flags);
271 if (!IS_ERR(buf))
272 buf->ops = &amdgpu_dmabuf_ops;
273
274 return buf;
275 }
276
277 /**
278 * amdgpu_dma_buf_create_obj - create BO for DMA-buf import
279 *
280 * @dev: DRM device
281 * @dma_buf: DMA-buf
282 *
283 * Creates an empty SG BO for DMA-buf import.
284 *
285 * Returns:
286 * A new GEM BO of the given DRM device, representing the memory
287 * described by the given DMA-buf attachment and scatter/gather table.
288 */
289 static struct drm_gem_object *
amdgpu_dma_buf_create_obj(struct drm_device * dev,struct dma_buf * dma_buf)290 amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
291 {
292 struct dma_resv *resv = dma_buf->resv;
293 struct amdgpu_device *adev = drm_to_adev(dev);
294 struct drm_gem_object *gobj;
295 struct amdgpu_bo *bo;
296 uint64_t flags = 0;
297 int ret;
298
299 dma_resv_lock(resv, NULL);
300
301 if (dma_buf->ops == &amdgpu_dmabuf_ops) {
302 struct amdgpu_bo *other = gem_to_amdgpu_bo(dma_buf->priv);
303
304 flags |= other->flags & (AMDGPU_GEM_CREATE_CPU_GTT_USWC |
305 AMDGPU_GEM_CREATE_COHERENT |
306 AMDGPU_GEM_CREATE_EXT_COHERENT |
307 AMDGPU_GEM_CREATE_UNCACHED);
308 }
309
310 ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE,
311 AMDGPU_GEM_DOMAIN_CPU, flags,
312 ttm_bo_type_sg, resv, &gobj, 0);
313 if (ret)
314 goto error;
315
316 bo = gem_to_amdgpu_bo(gobj);
317 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
318 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
319
320 dma_resv_unlock(resv);
321 return gobj;
322
323 error:
324 dma_resv_unlock(resv);
325 return ERR_PTR(ret);
326 }
327
328 /**
329 * amdgpu_dma_buf_move_notify - &attach.move_notify implementation
330 *
331 * @attach: the DMA-buf attachment
332 *
333 * Invalidate the DMA-buf attachment, making sure that the we re-create the
334 * mapping before the next use.
335 */
336 static void
amdgpu_dma_buf_move_notify(struct dma_buf_attachment * attach)337 amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach)
338 {
339 struct drm_gem_object *obj = attach->importer_priv;
340 struct ww_acquire_ctx *ticket = dma_resv_locking_ctx(obj->resv);
341 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
342 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
343 struct ttm_operation_ctx ctx = { false, false };
344 struct ttm_placement placement = {};
345 struct amdgpu_vm_bo_base *bo_base;
346 int r;
347
348 /* FIXME: This should be after the "if", but needs a fix to make sure
349 * DMABuf imports are initialized in the right VM list.
350 */
351 amdgpu_vm_bo_invalidate(bo, false);
352 if (!bo->tbo.resource || bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
353 return;
354
355 r = ttm_bo_validate(&bo->tbo, &placement, &ctx);
356 if (r) {
357 DRM_ERROR("Failed to invalidate DMA-buf import (%d))\n", r);
358 return;
359 }
360
361 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
362 struct amdgpu_vm *vm = bo_base->vm;
363 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
364
365 if (ticket) {
366 /* When we get an error here it means that somebody
367 * else is holding the VM lock and updating page tables
368 * So we can just continue here.
369 */
370 r = dma_resv_lock(resv, ticket);
371 if (r)
372 continue;
373
374 } else {
375 /* TODO: This is more problematic and we actually need
376 * to allow page tables updates without holding the
377 * lock.
378 */
379 if (!dma_resv_trylock(resv))
380 continue;
381 }
382
383 /* Reserve fences for two SDMA page table updates */
384 r = dma_resv_reserve_fences(resv, 2);
385 if (!r)
386 r = amdgpu_vm_clear_freed(adev, vm, NULL);
387 if (!r)
388 r = amdgpu_vm_handle_moved(adev, vm, ticket);
389
390 if (r && r != -EBUSY)
391 DRM_ERROR("Failed to invalidate VM page tables (%d))\n",
392 r);
393
394 dma_resv_unlock(resv);
395 }
396 }
397
398 static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = {
399 .allow_peer2peer = true,
400 .move_notify = amdgpu_dma_buf_move_notify
401 };
402
403 /**
404 * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation
405 * @dev: DRM device
406 * @dma_buf: Shared DMA buffer
407 *
408 * Import a dma_buf into a the driver and potentially create a new GEM object.
409 *
410 * Returns:
411 * GEM BO representing the shared DMA buffer for the given device.
412 */
amdgpu_gem_prime_import(struct drm_device * dev,struct dma_buf * dma_buf)413 struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
414 struct dma_buf *dma_buf)
415 {
416 struct dma_buf_attachment *attach;
417 struct drm_gem_object *obj;
418
419 if (dma_buf->ops == &amdgpu_dmabuf_ops) {
420 obj = dma_buf->priv;
421 if (obj->dev == dev) {
422 /*
423 * Importing dmabuf exported from out own gem increases
424 * refcount on gem itself instead of f_count of dmabuf.
425 */
426 drm_gem_object_get(obj);
427 return obj;
428 }
429 }
430
431 obj = amdgpu_dma_buf_create_obj(dev, dma_buf);
432 if (IS_ERR(obj))
433 return obj;
434
435 attach = dma_buf_dynamic_attach(dma_buf, dev->dev,
436 &amdgpu_dma_buf_attach_ops, obj);
437 if (IS_ERR(attach)) {
438 drm_gem_object_put(obj);
439 return ERR_CAST(attach);
440 }
441
442 get_dma_buf(dma_buf);
443 obj->import_attach = attach;
444 return obj;
445 }
446
447 /**
448 * amdgpu_dmabuf_is_xgmi_accessible - Check if xgmi available for P2P transfer
449 *
450 * @adev: amdgpu_device pointer of the importer
451 * @bo: amdgpu buffer object
452 *
453 * Returns:
454 * True if dmabuf accessible over xgmi, false otherwise.
455 */
amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device * adev,struct amdgpu_bo * bo)456 bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev,
457 struct amdgpu_bo *bo)
458 {
459 struct drm_gem_object *obj = &bo->tbo.base;
460 struct drm_gem_object *gobj;
461
462 if (obj->import_attach) {
463 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
464
465 if (dma_buf->ops != &amdgpu_dmabuf_ops)
466 /* No XGMI with non AMD GPUs */
467 return false;
468
469 gobj = dma_buf->priv;
470 bo = gem_to_amdgpu_bo(gobj);
471 }
472
473 if (amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev)) &&
474 (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM))
475 return true;
476
477 return false;
478 }
479