1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2023 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include <drm/drm_print.h>
28 #include <drm/drm_plane.h>
29 #include <drm/drm_property.h>
30 #include <drm/drm_colorop.h>
31
32 #include "amdgpu.h"
33 #include "amdgpu_dm_colorop.h"
34 #include "dc.h"
35
36 const u64 amdgpu_dm_supported_degam_tfs =
37 BIT(DRM_COLOROP_1D_CURVE_SRGB_EOTF) |
38 BIT(DRM_COLOROP_1D_CURVE_PQ_125_EOTF) |
39 BIT(DRM_COLOROP_1D_CURVE_BT2020_INV_OETF) |
40 BIT(DRM_COLOROP_1D_CURVE_GAMMA22);
41
42 const u64 amdgpu_dm_supported_shaper_tfs =
43 BIT(DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF) |
44 BIT(DRM_COLOROP_1D_CURVE_PQ_125_INV_EOTF) |
45 BIT(DRM_COLOROP_1D_CURVE_BT2020_OETF) |
46 BIT(DRM_COLOROP_1D_CURVE_GAMMA22_INV);
47
48 const u64 amdgpu_dm_supported_blnd_tfs =
49 BIT(DRM_COLOROP_1D_CURVE_SRGB_EOTF) |
50 BIT(DRM_COLOROP_1D_CURVE_PQ_125_EOTF) |
51 BIT(DRM_COLOROP_1D_CURVE_BT2020_INV_OETF) |
52 BIT(DRM_COLOROP_1D_CURVE_GAMMA22);
53
54 #define MAX_COLOR_PIPELINE_OPS 10
55
56 #define LUT3D_SIZE 17
57
58 static const struct drm_colorop_funcs dm_colorop_funcs = {
59 .destroy = drm_colorop_destroy,
60 };
61
amdgpu_dm_initialize_default_pipeline(struct drm_plane * plane,struct drm_prop_enum_list * list)62 int amdgpu_dm_initialize_default_pipeline(struct drm_plane *plane, struct drm_prop_enum_list *list)
63 {
64 struct drm_colorop *ops[MAX_COLOR_PIPELINE_OPS];
65 struct drm_device *dev = plane->dev;
66 struct amdgpu_device *adev = drm_to_adev(dev);
67 bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;
68 int ret;
69 int i = 0;
70
71 memset(ops, 0, sizeof(ops));
72
73 /* 1D curve - DEGAM TF */
74 ops[i] = kzalloc_obj(*ops[0]);
75 if (!ops[i]) {
76 ret = -ENOMEM;
77 goto cleanup;
78 }
79
80 ret = drm_plane_colorop_curve_1d_init(dev, ops[i], plane, &dm_colorop_funcs,
81 amdgpu_dm_supported_degam_tfs,
82 DRM_COLOROP_FLAG_ALLOW_BYPASS);
83 if (ret)
84 goto cleanup;
85
86 list->type = ops[i]->base.id;
87
88 i++;
89
90 /* Multiplier */
91 ops[i] = kzalloc_obj(struct drm_colorop);
92 if (!ops[i]) {
93 ret = -ENOMEM;
94 goto cleanup;
95 }
96
97 ret = drm_plane_colorop_mult_init(dev, ops[i], plane, &dm_colorop_funcs,
98 DRM_COLOROP_FLAG_ALLOW_BYPASS);
99 if (ret)
100 goto cleanup;
101
102 drm_colorop_set_next_property(ops[i-1], ops[i]);
103
104 i++;
105
106 /* 3x4 matrix */
107 ops[i] = kzalloc_obj(struct drm_colorop);
108 if (!ops[i]) {
109 ret = -ENOMEM;
110 goto cleanup;
111 }
112
113 ret = drm_plane_colorop_ctm_3x4_init(dev, ops[i], plane,
114 &dm_colorop_funcs,
115 DRM_COLOROP_FLAG_ALLOW_BYPASS);
116 if (ret)
117 goto cleanup;
118
119 drm_colorop_set_next_property(ops[i-1], ops[i]);
120
121 i++;
122
123 if (has_3dlut) {
124 /* 1D curve - SHAPER TF */
125 ops[i] = kzalloc_obj(*ops[0]);
126 if (!ops[i]) {
127 ret = -ENOMEM;
128 goto cleanup;
129 }
130
131 ret = drm_plane_colorop_curve_1d_init(dev, ops[i], plane, &dm_colorop_funcs,
132 amdgpu_dm_supported_shaper_tfs,
133 DRM_COLOROP_FLAG_ALLOW_BYPASS);
134 if (ret)
135 goto cleanup;
136
137 drm_colorop_set_next_property(ops[i-1], ops[i]);
138
139 i++;
140
141 /* 1D LUT - SHAPER LUT */
142 ops[i] = kzalloc_obj(*ops[0]);
143 if (!ops[i]) {
144 ret = -ENOMEM;
145 goto cleanup;
146 }
147
148 ret = drm_plane_colorop_curve_1d_lut_init(dev, ops[i], plane,
149 &dm_colorop_funcs,
150 MAX_COLOR_LUT_ENTRIES,
151 DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
152 DRM_COLOROP_FLAG_ALLOW_BYPASS);
153 if (ret)
154 goto cleanup;
155
156 drm_colorop_set_next_property(ops[i-1], ops[i]);
157
158 i++;
159
160 /* 3D LUT */
161 ops[i] = kzalloc_obj(*ops[0]);
162 if (!ops[i]) {
163 ret = -ENOMEM;
164 goto cleanup;
165 }
166
167 ret = drm_plane_colorop_3dlut_init(dev, ops[i], plane,
168 &dm_colorop_funcs, LUT3D_SIZE,
169 DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL,
170 DRM_COLOROP_FLAG_ALLOW_BYPASS);
171 if (ret)
172 goto cleanup;
173
174 drm_colorop_set_next_property(ops[i-1], ops[i]);
175
176 i++;
177 }
178
179 /* 1D curve - BLND TF */
180 ops[i] = kzalloc_obj(*ops[0]);
181 if (!ops[i]) {
182 ret = -ENOMEM;
183 goto cleanup;
184 }
185
186 ret = drm_plane_colorop_curve_1d_init(dev, ops[i], plane, &dm_colorop_funcs,
187 amdgpu_dm_supported_blnd_tfs,
188 DRM_COLOROP_FLAG_ALLOW_BYPASS);
189 if (ret)
190 goto cleanup;
191
192 drm_colorop_set_next_property(ops[i - 1], ops[i]);
193
194 i++;
195
196 /* 1D LUT - BLND LUT */
197 ops[i] = kzalloc_obj(struct drm_colorop);
198 if (!ops[i]) {
199 ret = -ENOMEM;
200 goto cleanup;
201 }
202
203 ret = drm_plane_colorop_curve_1d_lut_init(dev, ops[i], plane, &dm_colorop_funcs,
204 MAX_COLOR_LUT_ENTRIES,
205 DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
206 DRM_COLOROP_FLAG_ALLOW_BYPASS);
207 if (ret)
208 goto cleanup;
209
210 drm_colorop_set_next_property(ops[i-1], ops[i]);
211
212 list->name = kasprintf(GFP_KERNEL, "Color Pipeline %d", ops[0]->base.id);
213
214 return 0;
215
216 cleanup:
217 if (ret == -ENOMEM)
218 drm_err(plane->dev, "KMS: Failed to allocate colorop\n");
219
220 drm_colorop_pipeline_destroy(dev);
221
222 return ret;
223 }
224