1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2021 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "amdgpu_dm_psr.h"
28 #include "dc_dmub_srv.h"
29 #include "dc.h"
30 #include "amdgpu_dm.h"
31 #include "modules/power/power_helpers.h"
32
link_supports_psrsu(struct dc_link * link)33 static bool link_supports_psrsu(struct dc_link *link)
34 {
35 struct dc *dc = link->ctx->dc;
36
37 if (!dc->caps.dmcub_support)
38 return false;
39
40 if (dc->ctx->dce_version < DCN_VERSION_3_1)
41 return false;
42
43 if (!is_psr_su_specific_panel(link))
44 return false;
45
46 if (!link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP ||
47 !link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED)
48 return false;
49
50 if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED &&
51 !link->dpcd_caps.psr_info.psr2_su_y_granularity_cap)
52 return false;
53
54 if (amdgpu_dc_debug_mask & DC_DISABLE_PSR_SU)
55 return false;
56
57 /* Temporarily disable PSR-SU to avoid glitches */
58 return false;
59 }
60
61 /*
62 * amdgpu_dm_set_psr_caps() - set link psr capabilities
63 * @link: link
64 *
65 */
amdgpu_dm_set_psr_caps(struct dc_link * link)66 void amdgpu_dm_set_psr_caps(struct dc_link *link)
67 {
68 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) {
69 link->psr_settings.psr_feature_enabled = false;
70 return;
71 }
72
73 if (link->type == dc_connection_none) {
74 link->psr_settings.psr_feature_enabled = false;
75 return;
76 }
77
78 if (link->dpcd_caps.psr_info.psr_version == 0) {
79 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
80 link->psr_settings.psr_feature_enabled = false;
81
82 } else {
83 unsigned int panel_inst = 0;
84
85 if (link_supports_psrsu(link))
86 link->psr_settings.psr_version = DC_PSR_VERSION_SU_1;
87 else
88 link->psr_settings.psr_version = DC_PSR_VERSION_1;
89
90 link->psr_settings.psr_feature_enabled = true;
91
92 /*disable allow psr/psrsu/replay on eDP1*/
93 if (dc_get_edp_link_panel_inst(link->ctx->dc, link, &panel_inst) && panel_inst == 1) {
94 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
95 link->psr_settings.psr_feature_enabled = false;
96 }
97 }
98 }
99
100 /*
101 * amdgpu_dm_link_setup_psr() - configure psr link
102 * @stream: stream state
103 *
104 * Return: true if success
105 */
amdgpu_dm_link_setup_psr(struct dc_stream_state * stream)106 bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
107 {
108 struct dc_link *link = NULL;
109 struct psr_config psr_config = {0};
110 struct psr_context psr_context = {0};
111 struct dc *dc = NULL;
112 bool ret = false;
113
114 if (stream == NULL)
115 return false;
116
117 link = stream->link;
118 dc = link->ctx->dc;
119
120 if (link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) {
121 mod_power_calc_psr_configs(&psr_config, link, stream);
122
123 /* linux DM specific updating for psr config fields */
124 psr_config.allow_smu_optimizations =
125 (amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT) &&
126 mod_power_only_edp(dc->current_state, stream);
127 psr_config.allow_multi_disp_optimizations =
128 (amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT);
129
130 if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
131 if (!psr_su_set_dsc_slice_height(dc, link, stream, &psr_config))
132 return false;
133 }
134
135 ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
136
137 }
138 DRM_DEBUG_DRIVER("PSR link: %d\n", link->psr_settings.psr_feature_enabled);
139
140 return ret;
141 }
142
143 /*
144 * amdgpu_dm_psr_enable() - enable psr f/w
145 * @stream: stream state
146 *
147 */
amdgpu_dm_psr_enable(struct dc_stream_state * stream)148 void amdgpu_dm_psr_enable(struct dc_stream_state *stream)
149 {
150 struct dc_link *link = stream->link;
151 unsigned int vsync_rate_hz = 0;
152 struct dc_static_screen_params params = {0};
153 /* Calculate number of static frames before generating interrupt to
154 * enter PSR.
155 */
156 // Init fail safe of 2 frames static
157 unsigned int num_frames_static = 2;
158 unsigned int power_opt = 0;
159 bool psr_enable = true;
160
161 DRM_DEBUG_DRIVER("Enabling psr...\n");
162
163 vsync_rate_hz = div64_u64(div64_u64((
164 stream->timing.pix_clk_100hz * (uint64_t)100),
165 stream->timing.v_total),
166 stream->timing.h_total);
167
168 /* Round up
169 * Calculate number of frames such that at least 30 ms of time has
170 * passed.
171 */
172 if (vsync_rate_hz != 0) {
173 unsigned int frame_time_microsec = 1000000 / vsync_rate_hz;
174
175 num_frames_static = (30000 / frame_time_microsec) + 1;
176 }
177
178 params.triggers.cursor_update = true;
179 params.triggers.overlay_update = true;
180 params.triggers.surface_update = true;
181 params.num_frames = num_frames_static;
182
183 dc_stream_set_static_screen_params(link->ctx->dc,
184 &stream, 1,
185 ¶ms);
186
187 /*
188 * Only enable static-screen optimizations for PSR1. For PSR SU, this
189 * causes vstartup interrupt issues, used by amdgpu_dm to send vblank
190 * events.
191 */
192 if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1)
193 power_opt |= psr_power_opt_z10_static_screen;
194
195 dc_link_set_psr_allow_active(link, &psr_enable, false, false, &power_opt);
196
197 if (link->ctx->dc->caps.ips_support)
198 dc_allow_idle_optimizations(link->ctx->dc, true);
199 }
200
201 /*
202 * amdgpu_dm_psr_disable() - disable psr f/w
203 * @stream: stream state
204 *
205 * Return: true if success
206 */
amdgpu_dm_psr_disable(struct dc_stream_state * stream,bool wait)207 bool amdgpu_dm_psr_disable(struct dc_stream_state *stream, bool wait)
208 {
209 bool psr_enable = false;
210
211 DRM_DEBUG_DRIVER("Disabling psr...\n");
212
213 return dc_link_set_psr_allow_active(stream->link, &psr_enable, wait, false, NULL);
214 }
215
216 /*
217 * amdgpu_dm_psr_disable_all() - disable psr f/w for all streams
218 * if psr is enabled on any stream
219 *
220 * Return: true if success
221 */
amdgpu_dm_psr_disable_all(struct amdgpu_display_manager * dm)222 bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm)
223 {
224 DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n");
225 return dc_set_psr_allow_active(dm->dc, false);
226 }
227
228 /*
229 * amdgpu_dm_psr_is_active_allowed() - check if psr is allowed on any stream
230 * @dm: pointer to amdgpu_display_manager
231 *
232 * Return: true if allowed
233 */
234
amdgpu_dm_psr_is_active_allowed(struct amdgpu_display_manager * dm)235 bool amdgpu_dm_psr_is_active_allowed(struct amdgpu_display_manager *dm)
236 {
237 unsigned int i;
238 bool allow_active = false;
239
240 for (i = 0; i < dm->dc->current_state->stream_count ; i++) {
241 struct dc_link *link;
242 struct dc_stream_state *stream = dm->dc->current_state->streams[i];
243
244 link = stream->link;
245 if (!link)
246 continue;
247 if (link->psr_settings.psr_feature_enabled &&
248 link->psr_settings.psr_allow_active) {
249 allow_active = true;
250 break;
251 }
252 }
253
254 return allow_active;
255 }
256
257 /**
258 * amdgpu_dm_psr_wait_disable() - Wait for eDP panel to exit PSR
259 * @stream: stream state attached to the eDP link
260 *
261 * Waits for a max of 500ms for the eDP panel to exit PSR.
262 *
263 * Return: true if panel exited PSR, false otherwise.
264 */
amdgpu_dm_psr_wait_disable(struct dc_stream_state * stream)265 bool amdgpu_dm_psr_wait_disable(struct dc_stream_state *stream)
266 {
267 enum dc_psr_state psr_state = PSR_STATE0;
268 struct dc_link *link = stream->link;
269 int retry_count;
270
271 if (link == NULL)
272 return false;
273
274 for (retry_count = 0; retry_count <= 1000; retry_count++) {
275 dc_link_get_psr_state(link, &psr_state);
276 if (psr_state == PSR_STATE0)
277 break;
278 udelay(500);
279 }
280
281 if (retry_count == 1000)
282 return false;
283
284 return true;
285 }
286