1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26 #include <drm/drm_vblank.h>
27 #include <drm/drm_atomic_helper.h>
28
29 #include "dc.h"
30 #include "amdgpu.h"
31 #include "amdgpu_dm_psr.h"
32 #include "amdgpu_dm_replay.h"
33 #include "amdgpu_dm_crtc.h"
34 #include "amdgpu_dm_plane.h"
35 #include "amdgpu_dm_trace.h"
36 #include "amdgpu_dm_debugfs.h"
37
38 #define HPD_DETECTION_PERIOD_uS 2000000
39 #define HPD_DETECTION_TIME_uS 100000
40
amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc * acrtc)41 void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc)
42 {
43 struct drm_crtc *crtc = &acrtc->base;
44 struct drm_device *dev = crtc->dev;
45 unsigned long flags;
46
47 drm_crtc_handle_vblank(crtc);
48
49 spin_lock_irqsave(&dev->event_lock, flags);
50
51 /* Send completion event for cursor-only commits */
52 if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
53 drm_crtc_send_vblank_event(crtc, acrtc->event);
54 drm_crtc_vblank_put(crtc);
55 acrtc->event = NULL;
56 }
57
58 spin_unlock_irqrestore(&dev->event_lock, flags);
59 }
60
amdgpu_dm_crtc_modeset_required(struct drm_crtc_state * crtc_state,struct dc_stream_state * new_stream,struct dc_stream_state * old_stream)61 bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state,
62 struct dc_stream_state *new_stream,
63 struct dc_stream_state *old_stream)
64 {
65 return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
66 }
67
amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc * acrtc)68 bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc)
69
70 {
71 return acrtc->dm_irq_params.freesync_config.state ==
72 VRR_STATE_ACTIVE_VARIABLE ||
73 acrtc->dm_irq_params.freesync_config.state ==
74 VRR_STATE_ACTIVE_FIXED;
75 }
76
amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc * crtc,bool enable)77 int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
78 {
79 enum dc_irq_source irq_source;
80 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
81 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
82 int rc;
83
84 if (acrtc->otg_inst == -1)
85 return 0;
86
87 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
88
89 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
90
91 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
92 acrtc->crtc_id, enable ? "en" : "dis", rc);
93 return rc;
94 }
95
amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state * dm_state)96 bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state)
97 {
98 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
99 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
100 }
101
102 /**
103 * amdgpu_dm_crtc_set_panel_sr_feature() - Manage panel self-refresh features.
104 *
105 * @vblank_work: is a pointer to a struct vblank_control_work object.
106 * @vblank_enabled: indicates whether the DRM vblank counter is currently
107 * enabled (true) or disabled (false).
108 * @allow_sr_entry: represents whether entry into the self-refresh mode is
109 * allowed (true) or not allowed (false).
110 *
111 * The DRM vblank counter enable/disable action is used as the trigger to enable
112 * or disable various panel self-refresh features:
113 *
114 * Panel Replay and PSR SU
115 * - Enable when:
116 * - VRR is disabled
117 * - vblank counter is disabled
118 * - entry is allowed: usermode demonstrates an adequate number of fast
119 * commits)
120 * - CRC capture window isn't active
121 * - Keep enabled even when vblank counter gets enabled
122 *
123 * PSR1
124 * - Enable condition same as above
125 * - Disable when vblank counter is enabled
126 */
amdgpu_dm_crtc_set_panel_sr_feature(struct vblank_control_work * vblank_work,bool vblank_enabled,bool allow_sr_entry)127 static void amdgpu_dm_crtc_set_panel_sr_feature(
128 struct vblank_control_work *vblank_work,
129 bool vblank_enabled, bool allow_sr_entry)
130 {
131 struct dc_link *link = vblank_work->stream->link;
132 bool is_sr_active = (link->replay_settings.replay_allow_active ||
133 link->psr_settings.psr_allow_active);
134 bool is_crc_window_active = false;
135 bool vrr_active = amdgpu_dm_crtc_vrr_active_irq(vblank_work->acrtc);
136
137 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
138 is_crc_window_active =
139 amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base);
140 #endif
141
142 if (link->replay_settings.replay_feature_enabled && !vrr_active &&
143 allow_sr_entry && !is_sr_active && !is_crc_window_active) {
144 amdgpu_dm_replay_enable(vblank_work->stream, true);
145 } else if (vblank_enabled) {
146 if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active)
147 amdgpu_dm_psr_disable(vblank_work->stream, false);
148 } else if (link->psr_settings.psr_feature_enabled && !vrr_active &&
149 allow_sr_entry && !is_sr_active && !is_crc_window_active) {
150
151 struct amdgpu_dm_connector *aconn =
152 (struct amdgpu_dm_connector *) vblank_work->stream->dm_stream_context;
153
154 if (!aconn->disallow_edp_enter_psr) {
155 struct amdgpu_display_manager *dm = vblank_work->dm;
156
157 amdgpu_dm_psr_enable(vblank_work->stream);
158 if (dm->idle_workqueue &&
159 (dm->dc->config.disable_ips == DMUB_IPS_ENABLE) &&
160 dm->dc->idle_optimizations_allowed &&
161 dm->idle_workqueue->enable &&
162 !dm->idle_workqueue->running)
163 schedule_work(&dm->idle_workqueue->work);
164 }
165 }
166 }
167
amdgpu_dm_is_headless(struct amdgpu_device * adev)168 bool amdgpu_dm_is_headless(struct amdgpu_device *adev)
169 {
170 struct drm_connector *connector;
171 struct drm_connector_list_iter iter;
172 struct drm_device *dev;
173 bool is_headless = true;
174
175 if (adev == NULL)
176 return true;
177
178 dev = adev->dm.ddev;
179
180 drm_connector_list_iter_begin(dev, &iter);
181 drm_for_each_connector_iter(connector, &iter) {
182
183 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
184 continue;
185
186 if (connector->status == connector_status_connected) {
187 is_headless = false;
188 break;
189 }
190 }
191 drm_connector_list_iter_end(&iter);
192 return is_headless;
193 }
194
amdgpu_dm_idle_worker(struct work_struct * work)195 static void amdgpu_dm_idle_worker(struct work_struct *work)
196 {
197 struct idle_workqueue *idle_work;
198
199 idle_work = container_of(work, struct idle_workqueue, work);
200 idle_work->dm->idle_workqueue->running = true;
201
202 while (idle_work->enable) {
203 fsleep(HPD_DETECTION_PERIOD_uS);
204 mutex_lock(&idle_work->dm->dc_lock);
205 if (!idle_work->dm->dc->idle_optimizations_allowed) {
206 mutex_unlock(&idle_work->dm->dc_lock);
207 break;
208 }
209 dc_allow_idle_optimizations(idle_work->dm->dc, false);
210
211 mutex_unlock(&idle_work->dm->dc_lock);
212 fsleep(HPD_DETECTION_TIME_uS);
213 mutex_lock(&idle_work->dm->dc_lock);
214
215 if (!amdgpu_dm_is_headless(idle_work->dm->adev) &&
216 !amdgpu_dm_psr_is_active_allowed(idle_work->dm)) {
217 mutex_unlock(&idle_work->dm->dc_lock);
218 break;
219 }
220
221 if (idle_work->enable) {
222 dc_post_update_surfaces_to_stream(idle_work->dm->dc);
223 dc_allow_idle_optimizations(idle_work->dm->dc, true);
224 }
225 mutex_unlock(&idle_work->dm->dc_lock);
226 }
227 idle_work->dm->idle_workqueue->running = false;
228 }
229
idle_create_workqueue(struct amdgpu_device * adev)230 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev)
231 {
232 struct idle_workqueue *idle_work;
233
234 idle_work = kzalloc(sizeof(*idle_work), GFP_KERNEL);
235 if (ZERO_OR_NULL_PTR(idle_work))
236 return NULL;
237
238 idle_work->dm = &adev->dm;
239 idle_work->enable = false;
240 idle_work->running = false;
241 INIT_WORK(&idle_work->work, amdgpu_dm_idle_worker);
242
243 return idle_work;
244 }
245
amdgpu_dm_crtc_vblank_control_worker(struct work_struct * work)246 static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)
247 {
248 struct vblank_control_work *vblank_work =
249 container_of(work, struct vblank_control_work, work);
250 struct amdgpu_display_manager *dm = vblank_work->dm;
251 struct amdgpu_device *adev = drm_to_adev(dm->ddev);
252 int r;
253
254 mutex_lock(&dm->dc_lock);
255
256 if (vblank_work->enable)
257 dm->active_vblank_irq_count++;
258 else if (dm->active_vblank_irq_count)
259 dm->active_vblank_irq_count--;
260
261 if (dm->active_vblank_irq_count > 0)
262 dc_allow_idle_optimizations(dm->dc, false);
263
264 /*
265 * Control PSR based on vblank requirements from OS
266 *
267 * If panel supports PSR SU, there's no need to disable PSR when OS is
268 * submitting fast atomic commits (we infer this by whether the OS
269 * requests vblank events). Fast atomic commits will simply trigger a
270 * full-frame-update (FFU); a specific case of selective-update (SU)
271 * where the SU region is the full hactive*vactive region. See
272 * fill_dc_dirty_rects().
273 */
274 if (vblank_work->stream && vblank_work->stream->link && vblank_work->acrtc) {
275 amdgpu_dm_crtc_set_panel_sr_feature(
276 vblank_work, vblank_work->enable,
277 vblank_work->acrtc->dm_irq_params.allow_sr_entry);
278 }
279
280 if (dm->active_vblank_irq_count == 0) {
281 dc_post_update_surfaces_to_stream(dm->dc);
282
283 r = amdgpu_dpm_pause_power_profile(adev, true);
284 if (r)
285 dev_warn(adev->dev, "failed to set default power profile mode\n");
286
287 dc_allow_idle_optimizations(dm->dc, true);
288
289 r = amdgpu_dpm_pause_power_profile(adev, false);
290 if (r)
291 dev_warn(adev->dev, "failed to restore the power profile mode\n");
292 }
293
294 mutex_unlock(&dm->dc_lock);
295
296 dc_stream_release(vblank_work->stream);
297
298 kfree(vblank_work);
299 }
300
amdgpu_dm_crtc_set_vblank(struct drm_crtc * crtc,bool enable)301 static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
302 {
303 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
304 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
305 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
306 struct amdgpu_display_manager *dm = &adev->dm;
307 struct vblank_control_work *work;
308 int irq_type;
309 int rc = 0;
310
311 if (enable && !acrtc->base.enabled) {
312 drm_dbg_vbl(crtc->dev,
313 "Reject vblank enable on unconfigured CRTC %d (enabled=%d)\n",
314 acrtc->crtc_id, acrtc->base.enabled);
315 return -EINVAL;
316 }
317
318 irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
319
320 if (enable) {
321 struct dc *dc = adev->dm.dc;
322 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
323 struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;
324 struct replay_settings *pr = &acrtc_state->stream->link->replay_settings;
325 bool sr_supported = (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED) ||
326 pr->config.replay_supported;
327
328 /*
329 * IPS & self-refresh feature can cause vblank counter resets between
330 * vblank disable and enable.
331 * It may cause system stuck due to waiting for the vblank counter.
332 * Call this function to estimate missed vblanks by using timestamps and
333 * update the vblank counter in DRM.
334 */
335 if (dc->caps.ips_support &&
336 dc->config.disable_ips != DMUB_IPS_DISABLE_ALL &&
337 sr_supported && vblank->config.disable_immediate)
338 drm_crtc_vblank_restore(crtc);
339 }
340
341 if (dc_supports_vrr(dm->dc->ctx->dce_version)) {
342 if (enable) {
343 /* vblank irq on -> Only need vupdate irq in vrr mode */
344 if (amdgpu_dm_crtc_vrr_active(acrtc_state))
345 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true);
346 } else {
347 /* vblank irq off -> vupdate irq off */
348 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false);
349 }
350 }
351
352 if (rc)
353 return rc;
354
355 /* crtc vblank or vstartup interrupt */
356 if (enable) {
357 rc = amdgpu_irq_get(adev, &adev->crtc_irq, irq_type);
358 drm_dbg_vbl(crtc->dev, "Get crtc_irq ret=%d\n", rc);
359 } else {
360 rc = amdgpu_irq_put(adev, &adev->crtc_irq, irq_type);
361 drm_dbg_vbl(crtc->dev, "Put crtc_irq ret=%d\n", rc);
362 }
363
364 if (rc)
365 return rc;
366
367 /*
368 * hubp surface flip interrupt
369 *
370 * We have no guarantee that the frontend index maps to the same
371 * backend index - some even map to more than one.
372 *
373 * TODO: Use a different interrupt or check DC itself for the mapping.
374 */
375 if (enable) {
376 rc = amdgpu_irq_get(adev, &adev->pageflip_irq, irq_type);
377 drm_dbg_vbl(crtc->dev, "Get pageflip_irq ret=%d\n", rc);
378 } else {
379 rc = amdgpu_irq_put(adev, &adev->pageflip_irq, irq_type);
380 drm_dbg_vbl(crtc->dev, "Put pageflip_irq ret=%d\n", rc);
381 }
382
383 if (rc)
384 return rc;
385
386 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
387 /* crtc vline0 interrupt, only available on DCN+ */
388 if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) {
389 if (enable) {
390 rc = amdgpu_irq_get(adev, &adev->vline0_irq, irq_type);
391 drm_dbg_vbl(crtc->dev, "Get vline0_irq ret=%d\n", rc);
392 } else {
393 rc = amdgpu_irq_put(adev, &adev->vline0_irq, irq_type);
394 drm_dbg_vbl(crtc->dev, "Put vline0_irq ret=%d\n", rc);
395 }
396
397 if (rc)
398 return rc;
399 }
400 #endif
401
402 if (amdgpu_in_reset(adev))
403 return 0;
404
405 if (dm->vblank_control_workqueue) {
406 work = kzalloc(sizeof(*work), GFP_ATOMIC);
407 if (!work)
408 return -ENOMEM;
409
410 INIT_WORK(&work->work, amdgpu_dm_crtc_vblank_control_worker);
411 work->dm = dm;
412 work->acrtc = acrtc;
413 work->enable = enable;
414
415 if (acrtc_state->stream) {
416 dc_stream_retain(acrtc_state->stream);
417 work->stream = acrtc_state->stream;
418 }
419
420 queue_work(dm->vblank_control_workqueue, &work->work);
421 }
422
423 return 0;
424 }
425
amdgpu_dm_crtc_enable_vblank(struct drm_crtc * crtc)426 int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc)
427 {
428 return amdgpu_dm_crtc_set_vblank(crtc, true);
429 }
430
amdgpu_dm_crtc_disable_vblank(struct drm_crtc * crtc)431 void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc)
432 {
433 amdgpu_dm_crtc_set_vblank(crtc, false);
434 }
435
amdgpu_dm_crtc_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * state)436 static void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc,
437 struct drm_crtc_state *state)
438 {
439 struct dm_crtc_state *cur = to_dm_crtc_state(state);
440
441 /* TODO Destroy dc_stream objects are stream object is flattened */
442 if (cur->stream)
443 dc_stream_release(cur->stream);
444
445
446 __drm_atomic_helper_crtc_destroy_state(state);
447
448
449 kfree(state);
450 }
451
amdgpu_dm_crtc_duplicate_state(struct drm_crtc * crtc)452 static struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *crtc)
453 {
454 struct dm_crtc_state *state, *cur;
455
456 cur = to_dm_crtc_state(crtc->state);
457
458 if (WARN_ON(!crtc->state))
459 return NULL;
460
461 state = kzalloc(sizeof(*state), GFP_KERNEL);
462 if (!state)
463 return NULL;
464
465 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
466
467 if (cur->stream) {
468 state->stream = cur->stream;
469 dc_stream_retain(state->stream);
470 }
471
472 state->active_planes = cur->active_planes;
473 state->vrr_infopacket = cur->vrr_infopacket;
474 state->abm_level = cur->abm_level;
475 state->vrr_supported = cur->vrr_supported;
476 state->freesync_config = cur->freesync_config;
477 state->cm_has_degamma = cur->cm_has_degamma;
478 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
479 state->regamma_tf = cur->regamma_tf;
480 state->crc_skip_count = cur->crc_skip_count;
481 state->mpo_requested = cur->mpo_requested;
482 state->cursor_mode = cur->cursor_mode;
483 /* TODO Duplicate dc_stream after objects are stream object is flattened */
484
485 return &state->base;
486 }
487
amdgpu_dm_crtc_destroy(struct drm_crtc * crtc)488 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
489 {
490 drm_crtc_cleanup(crtc);
491 kfree(crtc);
492 }
493
amdgpu_dm_crtc_reset_state(struct drm_crtc * crtc)494 static void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc)
495 {
496 struct dm_crtc_state *state;
497
498 if (crtc->state)
499 amdgpu_dm_crtc_destroy_state(crtc, crtc->state);
500
501 state = kzalloc(sizeof(*state), GFP_KERNEL);
502 if (WARN_ON(!state))
503 return;
504
505 __drm_atomic_helper_crtc_reset(crtc, &state->base);
506 }
507
508 #ifdef CONFIG_DEBUG_FS
amdgpu_dm_crtc_late_register(struct drm_crtc * crtc)509 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
510 {
511 crtc_debugfs_init(crtc);
512
513 return 0;
514 }
515 #endif
516
517 #ifdef AMD_PRIVATE_COLOR
518 /**
519 * dm_crtc_additional_color_mgmt - enable additional color properties
520 * @crtc: DRM CRTC
521 *
522 * This function lets the driver enable post-blending CRTC regamma transfer
523 * function property in addition to DRM CRTC gamma LUT. Default value means
524 * linear transfer function, which is the default CRTC gamma LUT behaviour
525 * without this property.
526 */
527 static void
dm_crtc_additional_color_mgmt(struct drm_crtc * crtc)528 dm_crtc_additional_color_mgmt(struct drm_crtc *crtc)
529 {
530 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
531
532 if (adev->dm.dc->caps.color.mpc.ogam_ram)
533 drm_object_attach_property(&crtc->base,
534 adev->mode_info.regamma_tf_property,
535 AMDGPU_TRANSFER_FUNCTION_DEFAULT);
536 }
537
538 static int
amdgpu_dm_atomic_crtc_set_property(struct drm_crtc * crtc,struct drm_crtc_state * state,struct drm_property * property,uint64_t val)539 amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc,
540 struct drm_crtc_state *state,
541 struct drm_property *property,
542 uint64_t val)
543 {
544 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
545 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);
546
547 if (property == adev->mode_info.regamma_tf_property) {
548 if (acrtc_state->regamma_tf != val) {
549 acrtc_state->regamma_tf = val;
550 acrtc_state->base.color_mgmt_changed |= 1;
551 }
552 } else {
553 drm_dbg_atomic(crtc->dev,
554 "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n",
555 crtc->base.id, crtc->name,
556 property->base.id, property->name);
557 return -EINVAL;
558 }
559
560 return 0;
561 }
562
563 static int
amdgpu_dm_atomic_crtc_get_property(struct drm_crtc * crtc,const struct drm_crtc_state * state,struct drm_property * property,uint64_t * val)564 amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc,
565 const struct drm_crtc_state *state,
566 struct drm_property *property,
567 uint64_t *val)
568 {
569 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
570 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);
571
572 if (property == adev->mode_info.regamma_tf_property)
573 *val = acrtc_state->regamma_tf;
574 else
575 return -EINVAL;
576
577 return 0;
578 }
579 #endif
580
581 /* Implemented only the options currently available for the driver */
582 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
583 .reset = amdgpu_dm_crtc_reset_state,
584 .destroy = amdgpu_dm_crtc_destroy,
585 .set_config = drm_atomic_helper_set_config,
586 .page_flip = drm_atomic_helper_page_flip,
587 .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state,
588 .atomic_destroy_state = amdgpu_dm_crtc_destroy_state,
589 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
590 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
591 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
592 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
593 .enable_vblank = amdgpu_dm_crtc_enable_vblank,
594 .disable_vblank = amdgpu_dm_crtc_disable_vblank,
595 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
596 #if defined(CONFIG_DEBUG_FS)
597 .late_register = amdgpu_dm_crtc_late_register,
598 #endif
599 #ifdef AMD_PRIVATE_COLOR
600 .atomic_set_property = amdgpu_dm_atomic_crtc_set_property,
601 .atomic_get_property = amdgpu_dm_atomic_crtc_get_property,
602 #endif
603 };
604
amdgpu_dm_crtc_helper_disable(struct drm_crtc * crtc)605 static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc)
606 {
607 }
608
amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state * new_crtc_state)609 static int amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
610 {
611 struct drm_atomic_state *state = new_crtc_state->state;
612 struct drm_plane *plane;
613 int num_active = 0;
614
615 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
616 struct drm_plane_state *new_plane_state;
617
618 /* Cursor planes are "fake". */
619 if (plane->type == DRM_PLANE_TYPE_CURSOR)
620 continue;
621
622 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
623
624 if (!new_plane_state) {
625 /*
626 * The plane is enable on the CRTC and hasn't changed
627 * state. This means that it previously passed
628 * validation and is therefore enabled.
629 */
630 num_active += 1;
631 continue;
632 }
633
634 /* We need a framebuffer to be considered enabled. */
635 num_active += (new_plane_state->fb != NULL);
636 }
637
638 return num_active;
639 }
640
amdgpu_dm_crtc_update_crtc_active_planes(struct drm_crtc * crtc,struct drm_crtc_state * new_crtc_state)641 static void amdgpu_dm_crtc_update_crtc_active_planes(struct drm_crtc *crtc,
642 struct drm_crtc_state *new_crtc_state)
643 {
644 struct dm_crtc_state *dm_new_crtc_state =
645 to_dm_crtc_state(new_crtc_state);
646
647 dm_new_crtc_state->active_planes = 0;
648
649 if (!dm_new_crtc_state->stream)
650 return;
651
652 dm_new_crtc_state->active_planes =
653 amdgpu_dm_crtc_count_crtc_active_planes(new_crtc_state);
654 }
655
amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)656 static bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
657 const struct drm_display_mode *mode,
658 struct drm_display_mode *adjusted_mode)
659 {
660 return true;
661 }
662
amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc * crtc,struct drm_atomic_state * state)663 static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
664 struct drm_atomic_state *state)
665 {
666 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
667 crtc);
668 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
669 struct dc *dc = adev->dm.dc;
670 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
671 int ret = -EINVAL;
672
673 trace_amdgpu_dm_crtc_atomic_check(crtc_state);
674
675 amdgpu_dm_crtc_update_crtc_active_planes(crtc, crtc_state);
676
677 if (WARN_ON(unlikely(!dm_crtc_state->stream &&
678 amdgpu_dm_crtc_modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) {
679 return ret;
680 }
681
682 /*
683 * We require the primary plane to be enabled whenever the CRTC is, otherwise
684 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other
685 * planes are disabled, which is not supported by the hardware. And there is legacy
686 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL.
687 */
688 if (crtc_state->enable &&
689 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) {
690 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n");
691 return -EINVAL;
692 }
693
694 /*
695 * Only allow async flips for fast updates that don't change the FB
696 * pitch, the DCC state, rotation, etc.
697 */
698 if (crtc_state->async_flip &&
699 dm_crtc_state->update_type != UPDATE_TYPE_FAST) {
700 drm_dbg_atomic(crtc->dev,
701 "[CRTC:%d:%s] async flips are only supported for fast updates\n",
702 crtc->base.id, crtc->name);
703 return -EINVAL;
704 }
705
706 if (!state->legacy_cursor_update && amdgpu_dm_crtc_vrr_active(dm_crtc_state)) {
707 struct drm_plane_state *primary_state;
708
709 /* Pull in primary plane for correct VRR handling */
710 primary_state = drm_atomic_get_plane_state(state, crtc->primary);
711 if (IS_ERR(primary_state))
712 return PTR_ERR(primary_state);
713 }
714
715 /* In some use cases, like reset, no stream is attached */
716 if (!dm_crtc_state->stream)
717 return 0;
718
719 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
720 return 0;
721
722 DRM_DEBUG_ATOMIC("Failed DC stream validation\n");
723 return ret;
724 }
725
726 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
727 .disable = amdgpu_dm_crtc_helper_disable,
728 .atomic_check = amdgpu_dm_crtc_helper_atomic_check,
729 .mode_fixup = amdgpu_dm_crtc_helper_mode_fixup,
730 .get_scanout_position = amdgpu_crtc_get_scanout_position,
731 };
732
amdgpu_dm_crtc_init(struct amdgpu_display_manager * dm,struct drm_plane * plane,uint32_t crtc_index)733 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
734 struct drm_plane *plane,
735 uint32_t crtc_index)
736 {
737 struct amdgpu_crtc *acrtc = NULL;
738 struct drm_plane *cursor_plane;
739 bool is_dcn;
740 int res = -ENOMEM;
741
742 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
743 if (!cursor_plane)
744 goto fail;
745
746 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
747 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
748
749 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
750 if (!acrtc)
751 goto fail;
752
753 res = drm_crtc_init_with_planes(
754 dm->ddev,
755 &acrtc->base,
756 plane,
757 cursor_plane,
758 &amdgpu_dm_crtc_funcs, NULL);
759
760 if (res)
761 goto fail;
762
763 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
764
765 /* Create (reset) the plane state */
766 if (acrtc->base.funcs->reset)
767 acrtc->base.funcs->reset(&acrtc->base);
768
769 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
770 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
771
772 acrtc->crtc_id = crtc_index;
773 acrtc->base.enabled = false;
774 acrtc->otg_inst = -1;
775
776 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
777
778 /* Don't enable DRM CRTC degamma property for DCE since it doesn't
779 * support programmable degamma anywhere.
780 */
781 is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch;
782 /* Dont't enable DRM CRTC degamma property for DCN401 since the
783 * pre-blending degamma LUT doesn't apply to cursor, and therefore
784 * can't work similar to a post-blending degamma LUT as in other hw
785 * versions.
786 * TODO: revisit it once KMS plane color API is merged.
787 */
788 drm_crtc_enable_color_mgmt(&acrtc->base,
789 (is_dcn &&
790 dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01) ?
791 MAX_COLOR_LUT_ENTRIES : 0,
792 true, MAX_COLOR_LUT_ENTRIES);
793
794 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
795
796 #ifdef AMD_PRIVATE_COLOR
797 dm_crtc_additional_color_mgmt(&acrtc->base);
798 #endif
799 return 0;
800
801 fail:
802 kfree(acrtc);
803 kfree(cursor_plane);
804 return res;
805 }
806
807