1 /* 2 * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_discovery.h" 28 #include "soc15_hw_ip.h" 29 #include "discovery.h" 30 #include "amdgpu_ras.h" 31 32 #include "soc15.h" 33 #include "gfx_v9_0.h" 34 #include "gfx_v9_4_3.h" 35 #include "gmc_v9_0.h" 36 #include "df_v1_7.h" 37 #include "df_v3_6.h" 38 #include "df_v4_3.h" 39 #include "df_v4_6_2.h" 40 #include "df_v4_15.h" 41 #include "nbio_v6_1.h" 42 #include "nbio_v7_0.h" 43 #include "nbio_v7_4.h" 44 #include "nbio_v7_9.h" 45 #include "nbio_v7_11.h" 46 #include "hdp_v4_0.h" 47 #include "vega10_ih.h" 48 #include "vega20_ih.h" 49 #include "sdma_v4_0.h" 50 #include "sdma_v4_4_2.h" 51 #include "uvd_v7_0.h" 52 #include "vce_v4_0.h" 53 #include "vcn_v1_0.h" 54 #include "vcn_v2_5.h" 55 #include "jpeg_v2_5.h" 56 #include "smuio_v9_0.h" 57 #include "gmc_v10_0.h" 58 #include "gmc_v11_0.h" 59 #include "gmc_v12_0.h" 60 #include "gfxhub_v2_0.h" 61 #include "mmhub_v2_0.h" 62 #include "nbio_v2_3.h" 63 #include "nbio_v4_3.h" 64 #include "nbio_v7_2.h" 65 #include "nbio_v7_7.h" 66 #include "nbif_v6_3_1.h" 67 #include "hdp_v5_0.h" 68 #include "hdp_v5_2.h" 69 #include "hdp_v6_0.h" 70 #include "hdp_v7_0.h" 71 #include "nv.h" 72 #include "soc21.h" 73 #include "soc24.h" 74 #include "soc_v1_0.h" 75 #include "navi10_ih.h" 76 #include "ih_v6_0.h" 77 #include "ih_v6_1.h" 78 #include "ih_v7_0.h" 79 #include "gfx_v10_0.h" 80 #include "gfx_v11_0.h" 81 #include "gfx_v12_0.h" 82 #include "gfx_v12_1.h" 83 #include "sdma_v5_0.h" 84 #include "sdma_v5_2.h" 85 #include "sdma_v6_0.h" 86 #include "sdma_v7_0.h" 87 #include "sdma_v7_1.h" 88 #include "lsdma_v6_0.h" 89 #include "lsdma_v7_0.h" 90 #include "lsdma_v7_1.h" 91 #include "vcn_v2_0.h" 92 #include "jpeg_v2_0.h" 93 #include "vcn_v3_0.h" 94 #include "jpeg_v3_0.h" 95 #include "vcn_v4_0.h" 96 #include "jpeg_v4_0.h" 97 #include "vcn_v4_0_3.h" 98 #include "jpeg_v4_0_3.h" 99 #include "vcn_v4_0_5.h" 100 #include "jpeg_v4_0_5.h" 101 #include "amdgpu_vkms.h" 102 #include "mes_v11_0.h" 103 #include "mes_v12_0.h" 104 #include "mes_v12_1.h" 105 #include "smuio_v11_0.h" 106 #include "smuio_v11_0_6.h" 107 #include "smuio_v13_0.h" 108 #include "smuio_v13_0_3.h" 109 #include "smuio_v13_0_6.h" 110 #include "smuio_v14_0_2.h" 111 #include "smuio_v15_0_0.h" 112 #include "smuio_v15_0_8.h" 113 #include "vcn_v5_0_0.h" 114 #include "vcn_v5_0_1.h" 115 #include "vcn_v5_0_2.h" 116 #include "jpeg_v5_0_0.h" 117 #include "jpeg_v5_0_1.h" 118 #include "jpeg_v5_0_2.h" 119 #include "jpeg_v5_3_0.h" 120 121 #include "amdgpu_ras_mgr.h" 122 123 #include "amdgpu_vpe.h" 124 #if defined(CONFIG_DRM_AMD_ISP) 125 #include "amdgpu_isp.h" 126 #endif 127 128 MODULE_FIRMWARE("amdgpu/ip_discovery.bin"); 129 MODULE_FIRMWARE("amdgpu/vega10_ip_discovery.bin"); 130 MODULE_FIRMWARE("amdgpu/vega12_ip_discovery.bin"); 131 MODULE_FIRMWARE("amdgpu/vega20_ip_discovery.bin"); 132 MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin"); 133 MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin"); 134 MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin"); 135 MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin"); 136 MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin"); 137 138 /* Note: These registers are consistent across all the SOCs */ 139 #define mmIP_DISCOVERY_VERSION 0x16A00 140 #define mmRCC_CONFIG_MEMSIZE 0xde3 141 #define mmMP0_SMN_C2PMSG_33 0x16061 142 #define mmMM_INDEX 0x0 143 #define mmMM_INDEX_HI 0x6 144 #define mmMM_DATA 0x1 145 146 #define mmDRIVER_SCRATCH_0 0x94 147 #define mmDRIVER_SCRATCH_1 0x95 148 #define mmDRIVER_SCRATCH_2 0x96 149 150 static const char *hw_id_names[HW_ID_MAX] = { 151 [MP1_HWID] = "MP1", 152 [MP2_HWID] = "MP2", 153 [THM_HWID] = "THM", 154 [SMUIO_HWID] = "SMUIO", 155 [FUSE_HWID] = "FUSE", 156 [CLKA_HWID] = "CLKA", 157 [PWR_HWID] = "PWR", 158 [GC_HWID] = "GC", 159 [UVD_HWID] = "UVD", 160 [AUDIO_AZ_HWID] = "AUDIO_AZ", 161 [ACP_HWID] = "ACP", 162 [DCI_HWID] = "DCI", 163 [DMU_HWID] = "DMU", 164 [DCO_HWID] = "DCO", 165 [DIO_HWID] = "DIO", 166 [XDMA_HWID] = "XDMA", 167 [DCEAZ_HWID] = "DCEAZ", 168 [DAZ_HWID] = "DAZ", 169 [SDPMUX_HWID] = "SDPMUX", 170 [NTB_HWID] = "NTB", 171 [IOHC_HWID] = "IOHC", 172 [L2IMU_HWID] = "L2IMU", 173 [VCE_HWID] = "VCE", 174 [MMHUB_HWID] = "MMHUB", 175 [ATHUB_HWID] = "ATHUB", 176 [DBGU_NBIO_HWID] = "DBGU_NBIO", 177 [DFX_HWID] = "DFX", 178 [DBGU0_HWID] = "DBGU0", 179 [DBGU1_HWID] = "DBGU1", 180 [OSSSYS_HWID] = "OSSSYS", 181 [HDP_HWID] = "HDP", 182 [SDMA0_HWID] = "SDMA0", 183 [SDMA1_HWID] = "SDMA1", 184 [SDMA2_HWID] = "SDMA2", 185 [SDMA3_HWID] = "SDMA3", 186 [LSDMA_HWID] = "LSDMA", 187 [ISP_HWID] = "ISP", 188 [DBGU_IO_HWID] = "DBGU_IO", 189 [DF_HWID] = "DF", 190 [CLKB_HWID] = "CLKB", 191 [FCH_HWID] = "FCH", 192 [DFX_DAP_HWID] = "DFX_DAP", 193 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 194 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 195 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 196 [L1IMU3_HWID] = "L1IMU3", 197 [L1IMU4_HWID] = "L1IMU4", 198 [L1IMU5_HWID] = "L1IMU5", 199 [L1IMU6_HWID] = "L1IMU6", 200 [L1IMU7_HWID] = "L1IMU7", 201 [L1IMU8_HWID] = "L1IMU8", 202 [L1IMU9_HWID] = "L1IMU9", 203 [L1IMU10_HWID] = "L1IMU10", 204 [L1IMU11_HWID] = "L1IMU11", 205 [L1IMU12_HWID] = "L1IMU12", 206 [L1IMU13_HWID] = "L1IMU13", 207 [L1IMU14_HWID] = "L1IMU14", 208 [L1IMU15_HWID] = "L1IMU15", 209 [WAFLC_HWID] = "WAFLC", 210 [FCH_USB_PD_HWID] = "FCH_USB_PD", 211 [PCIE_HWID] = "PCIE", 212 [PCS_HWID] = "PCS", 213 [DDCL_HWID] = "DDCL", 214 [SST_HWID] = "SST", 215 [IOAGR_HWID] = "IOAGR", 216 [NBIF_HWID] = "NBIF", 217 [IOAPIC_HWID] = "IOAPIC", 218 [SYSTEMHUB_HWID] = "SYSTEMHUB", 219 [NTBCCP_HWID] = "NTBCCP", 220 [UMC_HWID] = "UMC", 221 [SATA_HWID] = "SATA", 222 [USB_HWID] = "USB", 223 [CCXSEC_HWID] = "CCXSEC", 224 [XGMI_HWID] = "XGMI", 225 [XGBE_HWID] = "XGBE", 226 [MP0_HWID] = "MP0", 227 [VPE_HWID] = "VPE", 228 [ATU_HWID] = "ATU", 229 [AIGC_HWID] = "AIGC", 230 }; 231 232 static int hw_id_map[MAX_HWIP] = { 233 [GC_HWIP] = GC_HWID, 234 [HDP_HWIP] = HDP_HWID, 235 [SDMA0_HWIP] = SDMA0_HWID, 236 [SDMA1_HWIP] = SDMA1_HWID, 237 [SDMA2_HWIP] = SDMA2_HWID, 238 [SDMA3_HWIP] = SDMA3_HWID, 239 [LSDMA_HWIP] = LSDMA_HWID, 240 [MMHUB_HWIP] = MMHUB_HWID, 241 [ATHUB_HWIP] = ATHUB_HWID, 242 [NBIO_HWIP] = NBIF_HWID, 243 [MP0_HWIP] = MP0_HWID, 244 [MP1_HWIP] = MP1_HWID, 245 [UVD_HWIP] = UVD_HWID, 246 [VCE_HWIP] = VCE_HWID, 247 [DF_HWIP] = DF_HWID, 248 [DCE_HWIP] = DMU_HWID, 249 [OSSSYS_HWIP] = OSSSYS_HWID, 250 [SMUIO_HWIP] = SMUIO_HWID, 251 [PWR_HWIP] = PWR_HWID, 252 [NBIF_HWIP] = NBIF_HWID, 253 [THM_HWIP] = THM_HWID, 254 [CLK_HWIP] = CLKA_HWID, 255 [UMC_HWIP] = UMC_HWID, 256 [XGMI_HWIP] = XGMI_HWID, 257 [DCI_HWIP] = DCI_HWID, 258 [PCIE_HWIP] = PCIE_HWID, 259 [VPE_HWIP] = VPE_HWID, 260 [ISP_HWIP] = ISP_HWID, 261 [ATU_HWIP] = ATU_HWID, 262 }; 263 264 static int amdgpu_discovery_get_tmr_info(struct amdgpu_device *adev, 265 bool *is_tmr_in_sysmem) 266 { 267 u64 vram_size, tmr_offset, tmr_size; 268 u32 msg, tmr_offset_lo, tmr_offset_hi; 269 int i, ret; 270 271 if (!amdgpu_sriov_vf(adev)) { 272 /* It can take up to two second for IFWI init to complete on some dGPUs, 273 * but generally it should be in the 60-100ms range. Normally this starts 274 * as soon as the device gets power so by the time the OS loads this has long 275 * completed. However, when a card is hotplugged via e.g., USB4, we need to 276 * wait for this to complete. Once the C2PMSG is updated, we can 277 * continue. 278 */ 279 280 for (i = 0; i < 2000; i++) { 281 msg = RREG32(mmMP0_SMN_C2PMSG_33); 282 if (msg & 0x80000000) 283 break; 284 msleep(1); 285 } 286 } 287 288 vram_size = RREG32(mmRCC_CONFIG_MEMSIZE); 289 if (vram_size == U32_MAX) 290 return -ENXIO; 291 else if (!vram_size) 292 *is_tmr_in_sysmem = true; 293 else 294 *is_tmr_in_sysmem = false; 295 296 /* init the default tmr size and offset */ 297 adev->discovery.size = DISCOVERY_TMR_SIZE; 298 if (vram_size) 299 adev->discovery.offset = (vram_size << 20) - DISCOVERY_TMR_OFFSET; 300 301 if (amdgpu_sriov_vf(adev)) { 302 if (adev->virt.is_dynamic_crit_regn_enabled) { 303 adev->discovery.offset = 304 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].offset; 305 adev->discovery.size = 306 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb << 10; 307 if (!adev->discovery.offset || !adev->discovery.size) 308 return -EINVAL; 309 } else { 310 goto out; 311 } 312 } else { 313 tmr_size = RREG32(mmDRIVER_SCRATCH_2); 314 if (tmr_size) { 315 /* It's preferred to transition to PSP mailbox reg interface 316 * for both bare-metal and passthrough if available */ 317 adev->discovery.size = (u32)tmr_size; 318 tmr_offset_lo = RREG32(mmDRIVER_SCRATCH_0); 319 tmr_offset_hi = RREG32(mmDRIVER_SCRATCH_1); 320 adev->discovery.offset = ((u64)le32_to_cpu(tmr_offset_hi) << 32 | 321 le32_to_cpu(tmr_offset_lo)); 322 } else if (!vram_size) { 323 /* fall back to apci approach to query tmr offset if vram_size is 0 */ 324 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); 325 if (ret) 326 return ret; 327 adev->discovery.size = DISCOVERY_TMR_SIZE; 328 adev->discovery.offset = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; 329 } 330 } 331 out: 332 adev->discovery.bin = kzalloc(adev->discovery.size, GFP_KERNEL); 333 if (!adev->discovery.bin) 334 return -ENOMEM; 335 adev->discovery.debugfs_blob.data = adev->discovery.bin; 336 adev->discovery.debugfs_blob.size = adev->discovery.size; 337 338 return 0; 339 } 340 341 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) 342 { 343 void *discv_regn; 344 345 /* This region is read-only and reserved from system use */ 346 discv_regn = memremap(adev->discovery.offset, adev->discovery.size, MEMREMAP_WC); 347 if (discv_regn) { 348 memcpy(binary, discv_regn, adev->discovery.size); 349 memunmap(discv_regn); 350 return 0; 351 } 352 353 return -ENOENT; 354 } 355 356 #define IP_DISCOVERY_V2 2 357 #define IP_DISCOVERY_V4 4 358 359 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, 360 uint8_t *binary, 361 bool is_tmr_in_sysmem) 362 { 363 int ret = 0; 364 365 if (!is_tmr_in_sysmem) { 366 if (amdgpu_sriov_vf(adev) && 367 amdgpu_sriov_xgmi_connected_to_cpu(adev)) { 368 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 369 } else { 370 amdgpu_device_vram_access(adev, adev->discovery.offset, 371 (uint32_t *)binary, 372 adev->discovery.size, false); 373 adev->discovery.reserve_tmr = true; 374 } 375 } else { 376 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 377 } 378 379 return ret; 380 } 381 382 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, 383 uint8_t *binary, 384 const char *fw_name) 385 { 386 const struct firmware *fw; 387 int r; 388 389 r = firmware_request_nowarn(&fw, fw_name, adev->dev); 390 if (r) { 391 if (amdgpu_discovery == 2) 392 dev_err(adev->dev, "can't load firmware \"%s\"\n", fw_name); 393 else 394 drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fw_name); 395 return r; 396 } 397 398 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 399 release_firmware(fw); 400 401 return 0; 402 } 403 404 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 405 { 406 uint16_t checksum = 0; 407 int i; 408 409 for (i = 0; i < size; i++) 410 checksum += data[i]; 411 412 return checksum; 413 } 414 415 static inline bool amdgpu_discovery_verify_checksum(struct amdgpu_device *adev, 416 uint8_t *data, uint32_t size, 417 uint16_t expected) 418 { 419 uint16_t calculated; 420 421 calculated = amdgpu_discovery_calculate_checksum(data, size); 422 423 if (calculated != expected) { 424 dev_err(adev->dev, "Discovery checksum failed: calc 0x%04x != exp 0x%04x, size %u.\n", 425 calculated, expected, size); 426 return false; 427 } 428 429 return true; 430 } 431 432 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 433 { 434 struct binary_header *bhdr; 435 bhdr = (struct binary_header *)binary; 436 437 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 438 } 439 440 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 441 { 442 /* 443 * So far, apply this quirk only on those Navy Flounder boards which 444 * have a bad harvest table of VCN config. 445 */ 446 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) && 447 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) { 448 switch (adev->pdev->revision) { 449 case 0xC1: 450 case 0xC2: 451 case 0xC3: 452 case 0xC5: 453 case 0xC7: 454 case 0xCF: 455 case 0xDF: 456 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 457 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; 458 break; 459 default: 460 break; 461 } 462 } 463 } 464 465 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, 466 struct table_info *info) 467 { 468 uint8_t *discovery_bin = adev->discovery.bin; 469 uint16_t checksum; 470 uint16_t offset; 471 472 offset = le16_to_cpu(info->offset); 473 checksum = le16_to_cpu(info->checksum); 474 475 struct nps_info_header *nhdr = 476 (struct nps_info_header *)(discovery_bin + offset); 477 478 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) { 479 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n"); 480 return -EINVAL; 481 } 482 483 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, 484 le32_to_cpu(nhdr->size_bytes), 485 checksum)) { 486 dev_dbg(adev->dev, "invalid nps info data table checksum\n"); 487 return -EINVAL; 488 } 489 490 return 0; 491 } 492 493 static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev) 494 { 495 if (amdgpu_discovery == 2) { 496 /* Assume there is valid discovery TMR in VRAM even if binary is sideloaded */ 497 adev->discovery.reserve_tmr = true; 498 return "amdgpu/ip_discovery.bin"; 499 } 500 501 switch (adev->asic_type) { 502 case CHIP_VEGA10: 503 return "amdgpu/vega10_ip_discovery.bin"; 504 case CHIP_VEGA12: 505 return "amdgpu/vega12_ip_discovery.bin"; 506 case CHIP_RAVEN: 507 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 508 return "amdgpu/raven2_ip_discovery.bin"; 509 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 510 return "amdgpu/picasso_ip_discovery.bin"; 511 else 512 return "amdgpu/raven_ip_discovery.bin"; 513 case CHIP_VEGA20: 514 return "amdgpu/vega20_ip_discovery.bin"; 515 case CHIP_ARCTURUS: 516 return "amdgpu/arcturus_ip_discovery.bin"; 517 case CHIP_ALDEBARAN: 518 return "amdgpu/aldebaran_ip_discovery.bin"; 519 default: 520 return NULL; 521 } 522 } 523 524 static int amdgpu_discovery_get_table_info(struct amdgpu_device *adev, 525 struct table_info **info, 526 uint16_t table_id) 527 { 528 struct binary_header *bhdr = 529 (struct binary_header *)adev->discovery.bin; 530 struct binary_header_v2 *bhdrv2; 531 532 switch (bhdr->version_major) { 533 case 2: 534 bhdrv2 = (struct binary_header_v2 *)adev->discovery.bin; 535 *info = &bhdrv2->table_list[table_id]; 536 break; 537 case 1: 538 *info = &bhdr->table_list[table_id]; 539 break; 540 default: 541 dev_err(adev->dev, "Invalid ip discovery table version\n"); 542 return -EINVAL; 543 } 544 545 return 0; 546 } 547 548 static int amdgpu_discovery_table_check(struct amdgpu_device *adev, 549 uint8_t *discovery_bin, 550 uint16_t table_id) 551 { 552 int r, act_val, exp_val, table_size; 553 uint16_t offset, checksum; 554 struct table_info *info; 555 bool check_table = true; 556 char *table_name; 557 558 r = amdgpu_discovery_get_table_info(adev, &info, table_id); 559 if (r) 560 return r; 561 offset = le16_to_cpu(info->offset); 562 checksum = le16_to_cpu(info->checksum); 563 564 switch (table_id) { 565 case IP_DISCOVERY: { 566 struct ip_discovery_header *ihdr = 567 (struct ip_discovery_header *)(discovery_bin + offset); 568 act_val = le32_to_cpu(ihdr->signature); 569 exp_val = DISCOVERY_TABLE_SIGNATURE; 570 table_size = le16_to_cpu(ihdr->size); 571 table_name = "data table"; 572 break; 573 } 574 case GC: { 575 struct gpu_info_header *ghdr = 576 (struct gpu_info_header *)(discovery_bin + offset); 577 act_val = le32_to_cpu(ghdr->table_id); 578 exp_val = GC_TABLE_ID; 579 table_size = le16_to_cpu(ghdr->size); 580 table_name = "gc table"; 581 break; 582 } 583 case HARVEST_INFO: { 584 struct harvest_info_header *hhdr = 585 (struct harvest_info_header *)(discovery_bin + offset); 586 act_val = le32_to_cpu(hhdr->signature); 587 exp_val = HARVEST_TABLE_SIGNATURE; 588 table_size = sizeof(struct harvest_table); 589 table_name = "harvest table"; 590 break; 591 } 592 case VCN_INFO: { 593 struct vcn_info_header *vhdr = 594 (struct vcn_info_header *)(discovery_bin + offset); 595 act_val = le32_to_cpu(vhdr->table_id); 596 exp_val = VCN_INFO_TABLE_ID; 597 table_size = le32_to_cpu(vhdr->size_bytes); 598 table_name = "vcn table"; 599 break; 600 } 601 case MALL_INFO: { 602 struct mall_info_header *mhdr = 603 (struct mall_info_header *)(discovery_bin + offset); 604 act_val = le32_to_cpu(mhdr->table_id); 605 exp_val = MALL_INFO_TABLE_ID; 606 table_size = le32_to_cpu(mhdr->size_bytes); 607 table_name = "mall table"; 608 check_table = false; 609 break; 610 } 611 default: 612 dev_err(adev->dev, "invalid ip discovery table id %d specified\n", table_id); 613 check_table = false; 614 break; 615 } 616 617 if (check_table && offset) { 618 if (act_val != exp_val) { 619 dev_err(adev->dev, "invalid ip discovery %s signature\n", table_name); 620 return -EINVAL; 621 } 622 623 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, 624 table_size, checksum)) { 625 dev_err(adev->dev, "invalid ip discovery %s checksum\n", table_name); 626 return -EINVAL; 627 } 628 } 629 630 return 0; 631 } 632 633 static int amdgpu_discovery_init(struct amdgpu_device *adev) 634 { 635 struct binary_header *bhdr; 636 uint8_t *discovery_bin; 637 const char *fw_name; 638 uint16_t offset; 639 uint16_t size; 640 uint16_t checksum; 641 uint16_t table_id; 642 bool is_tmr_in_sysmem; 643 int r; 644 645 r = amdgpu_discovery_get_tmr_info(adev, &is_tmr_in_sysmem); 646 if (r) 647 return r; 648 649 discovery_bin = adev->discovery.bin; 650 /* Read from file if it is the preferred option */ 651 fw_name = amdgpu_discovery_get_fw_name(adev); 652 if (fw_name != NULL) { 653 drm_dbg(&adev->ddev, "use ip discovery information from file"); 654 r = amdgpu_discovery_read_binary_from_file(adev, discovery_bin, 655 fw_name); 656 if (r) 657 goto out; 658 } else { 659 drm_dbg(&adev->ddev, "use ip discovery information from memory"); 660 r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin, 661 is_tmr_in_sysmem); 662 if (r) 663 goto out; 664 } 665 666 /* check the ip discovery binary signature */ 667 if (!amdgpu_discovery_verify_binary_signature(discovery_bin)) { 668 dev_err(adev->dev, 669 "get invalid ip discovery binary signature\n"); 670 r = -EINVAL; 671 goto out; 672 } 673 674 bhdr = (struct binary_header *)discovery_bin; 675 676 offset = offsetof(struct binary_header, binary_checksum) + 677 sizeof(bhdr->binary_checksum); 678 size = le16_to_cpu(bhdr->binary_size) - offset; 679 checksum = le16_to_cpu(bhdr->binary_checksum); 680 681 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, size, 682 checksum)) { 683 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 684 r = -EINVAL; 685 goto out; 686 } 687 688 for (table_id = 0; table_id <= MALL_INFO; table_id++) { 689 r = amdgpu_discovery_table_check(adev, discovery_bin, table_id); 690 if (r) 691 goto out; 692 } 693 694 return 0; 695 696 out: 697 kfree(adev->discovery.bin); 698 adev->discovery.bin = NULL; 699 if ((amdgpu_discovery != 2) && 700 (RREG32(mmIP_DISCOVERY_VERSION) == 4)) 701 amdgpu_ras_query_boot_status(adev, 4); 702 return r; 703 } 704 705 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); 706 707 void amdgpu_discovery_fini(struct amdgpu_device *adev) 708 { 709 amdgpu_discovery_sysfs_fini(adev); 710 kfree(adev->discovery.bin); 711 adev->discovery.bin = NULL; 712 } 713 714 static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev, 715 uint8_t instance, uint16_t hw_id) 716 { 717 if (instance >= HWIP_MAX_INSTANCE) { 718 dev_err(adev->dev, 719 "Unexpected instance_number (%d) from ip discovery blob\n", 720 instance); 721 return -EINVAL; 722 } 723 if (hw_id >= HW_ID_MAX) { 724 dev_err(adev->dev, 725 "Unexpected hw_id (%d) from ip discovery blob\n", 726 hw_id); 727 return -EINVAL; 728 } 729 730 return 0; 731 } 732 733 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 734 uint32_t *vcn_harvest_count) 735 { 736 uint8_t *discovery_bin = adev->discovery.bin; 737 struct binary_header *bhdr; 738 struct ip_discovery_header *ihdr; 739 struct die_header *dhdr; 740 struct ip *ip; 741 uint16_t die_offset, ip_offset, num_dies, num_ips; 742 uint16_t hw_id; 743 uint8_t inst; 744 int i, j; 745 746 bhdr = (struct binary_header *)discovery_bin; 747 ihdr = (struct ip_discovery_header 748 *)(discovery_bin + 749 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 750 num_dies = le16_to_cpu(ihdr->num_dies); 751 752 /* scan harvest bit of all IP data structures */ 753 for (i = 0; i < num_dies; i++) { 754 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 755 dhdr = (struct die_header *)(discovery_bin + die_offset); 756 num_ips = le16_to_cpu(dhdr->num_ips); 757 ip_offset = die_offset + sizeof(*dhdr); 758 759 for (j = 0; j < num_ips; j++) { 760 ip = (struct ip *)(discovery_bin + ip_offset); 761 inst = ip->number_instance; 762 hw_id = le16_to_cpu(ip->hw_id); 763 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 764 goto next_ip; 765 766 if (ip->harvest == 1) { 767 switch (hw_id) { 768 case VCN_HWID: 769 (*vcn_harvest_count)++; 770 if (inst == 0) { 771 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 772 adev->vcn.inst_mask &= 773 ~AMDGPU_VCN_HARVEST_VCN0; 774 adev->jpeg.inst_mask &= 775 ~AMDGPU_VCN_HARVEST_VCN0; 776 } else { 777 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 778 adev->vcn.inst_mask &= 779 ~AMDGPU_VCN_HARVEST_VCN1; 780 adev->jpeg.inst_mask &= 781 ~AMDGPU_VCN_HARVEST_VCN1; 782 } 783 break; 784 case DMU_HWID: 785 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 786 break; 787 default: 788 break; 789 } 790 } 791 next_ip: 792 ip_offset += struct_size(ip, base_address, 793 ip->num_base_address); 794 } 795 } 796 } 797 798 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 799 uint32_t *vcn_harvest_count, 800 uint32_t *umc_harvest_count) 801 { 802 uint8_t *discovery_bin = adev->discovery.bin; 803 struct table_info *info; 804 struct harvest_table *harvest_info; 805 u16 offset; 806 int i; 807 u64 umc_harvest_config = 0; 808 809 if (amdgpu_discovery_get_table_info(adev, &info, HARVEST_INFO)) 810 return; 811 offset = le16_to_cpu(info->offset); 812 813 if (!offset) { 814 dev_err(adev->dev, "invalid harvest table offset\n"); 815 return; 816 } 817 818 harvest_info = (struct harvest_table *)(discovery_bin + offset); 819 820 for (i = 0; i < 32; i++) { 821 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) 822 break; 823 824 switch (le16_to_cpu(harvest_info->list[i].hw_id)) { 825 case VCN_HWID: 826 (*vcn_harvest_count)++; 827 adev->vcn.harvest_config |= 828 (1 << harvest_info->list[i].number_instance); 829 adev->jpeg.harvest_config |= 830 (1 << harvest_info->list[i].number_instance); 831 832 adev->vcn.inst_mask &= 833 ~(1U << harvest_info->list[i].number_instance); 834 adev->jpeg.inst_mask &= 835 ~(1U << harvest_info->list[i].number_instance); 836 break; 837 case DMU_HWID: 838 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 839 break; 840 case UMC_HWID: 841 umc_harvest_config |= 842 1 << (le16_to_cpu(harvest_info->list[i].number_instance)); 843 (*umc_harvest_count)++; 844 break; 845 case GC_HWID: 846 adev->gfx.xcc_mask &= 847 ~(1U << harvest_info->list[i].number_instance); 848 break; 849 case SDMA0_HWID: 850 adev->sdma.sdma_mask &= 851 ~(1U << harvest_info->list[i].number_instance); 852 break; 853 #if defined(CONFIG_DRM_AMD_ISP) 854 case ISP_HWID: 855 adev->isp.harvest_config |= 856 ~(1U << harvest_info->list[i].number_instance); 857 break; 858 #endif 859 default: 860 break; 861 } 862 } 863 864 adev->umc.active_mask = ((1ULL << adev->umc.node_inst_num) - 1ULL) & 865 ~umc_harvest_config; 866 } 867 868 /* ================================================== */ 869 870 struct ip_hw_instance { 871 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 872 873 int hw_id; 874 u8 num_instance; 875 u8 major, minor, revision; 876 u8 harvest; 877 878 int num_base_addresses; 879 u32 base_addr[] __counted_by(num_base_addresses); 880 }; 881 882 struct ip_hw_id { 883 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 884 int hw_id; 885 }; 886 887 struct ip_die_entry { 888 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 889 u16 num_ips; 890 }; 891 892 /* -------------------------------------------------- */ 893 894 struct ip_hw_instance_attr { 895 struct attribute attr; 896 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 897 }; 898 899 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 900 { 901 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 902 } 903 904 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 905 { 906 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 907 } 908 909 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 910 { 911 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 912 } 913 914 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 915 { 916 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 917 } 918 919 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 920 { 921 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 922 } 923 924 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 925 { 926 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 927 } 928 929 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 930 { 931 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 932 } 933 934 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 935 { 936 ssize_t at; 937 int ii; 938 939 for (at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 940 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 941 */ 942 if (at + 12 > PAGE_SIZE) 943 break; 944 at += sysfs_emit_at(buf, at, "0x%08X\n", 945 ip_hw_instance->base_addr[ii]); 946 } 947 948 return at; 949 } 950 951 static struct ip_hw_instance_attr ip_hw_attr[] = { 952 __ATTR_RO(hw_id), 953 __ATTR_RO(num_instance), 954 __ATTR_RO(major), 955 __ATTR_RO(minor), 956 __ATTR_RO(revision), 957 __ATTR_RO(harvest), 958 __ATTR_RO(num_base_addresses), 959 __ATTR_RO(base_addr), 960 }; 961 962 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 963 ATTRIBUTE_GROUPS(ip_hw_instance); 964 965 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 966 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 967 968 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 969 struct attribute *attr, 970 char *buf) 971 { 972 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 973 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 974 975 if (!ip_hw_attr->show) 976 return -EIO; 977 978 return ip_hw_attr->show(ip_hw_instance, buf); 979 } 980 981 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 982 .show = ip_hw_instance_attr_show, 983 }; 984 985 static void ip_hw_instance_release(struct kobject *kobj) 986 { 987 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 988 989 kfree(ip_hw_instance); 990 } 991 992 static const struct kobj_type ip_hw_instance_ktype = { 993 .release = ip_hw_instance_release, 994 .sysfs_ops = &ip_hw_instance_sysfs_ops, 995 .default_groups = ip_hw_instance_groups, 996 }; 997 998 /* -------------------------------------------------- */ 999 1000 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 1001 1002 static void ip_hw_id_release(struct kobject *kobj) 1003 { 1004 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 1005 1006 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 1007 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 1008 kfree(ip_hw_id); 1009 } 1010 1011 static const struct kobj_type ip_hw_id_ktype = { 1012 .release = ip_hw_id_release, 1013 .sysfs_ops = &kobj_sysfs_ops, 1014 }; 1015 1016 /* -------------------------------------------------- */ 1017 1018 static void die_kobj_release(struct kobject *kobj); 1019 static void ip_disc_release(struct kobject *kobj); 1020 1021 struct ip_die_entry_attribute { 1022 struct attribute attr; 1023 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 1024 }; 1025 1026 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 1027 1028 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 1029 { 1030 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 1031 } 1032 1033 /* If there are more ip_die_entry attrs, other than the number of IPs, 1034 * we can make this intro an array of attrs, and then initialize 1035 * ip_die_entry_attrs in a loop. 1036 */ 1037 static struct ip_die_entry_attribute num_ips_attr = 1038 __ATTR_RO(num_ips); 1039 1040 static struct attribute *ip_die_entry_attrs[] = { 1041 &num_ips_attr.attr, 1042 NULL, 1043 }; 1044 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 1045 1046 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 1047 1048 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 1049 struct attribute *attr, 1050 char *buf) 1051 { 1052 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 1053 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1054 1055 if (!ip_die_entry_attr->show) 1056 return -EIO; 1057 1058 return ip_die_entry_attr->show(ip_die_entry, buf); 1059 } 1060 1061 static void ip_die_entry_release(struct kobject *kobj) 1062 { 1063 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1064 1065 if (!list_empty(&ip_die_entry->ip_kset.list)) 1066 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 1067 kfree(ip_die_entry); 1068 } 1069 1070 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 1071 .show = ip_die_entry_attr_show, 1072 }; 1073 1074 static const struct kobj_type ip_die_entry_ktype = { 1075 .release = ip_die_entry_release, 1076 .sysfs_ops = &ip_die_entry_sysfs_ops, 1077 .default_groups = ip_die_entry_groups, 1078 }; 1079 1080 static const struct kobj_type die_kobj_ktype = { 1081 .release = die_kobj_release, 1082 .sysfs_ops = &kobj_sysfs_ops, 1083 }; 1084 1085 static const struct kobj_type ip_discovery_ktype = { 1086 .release = ip_disc_release, 1087 .sysfs_ops = &kobj_sysfs_ops, 1088 }; 1089 1090 struct ip_discovery_top { 1091 struct kobject kobj; /* ip_discovery/ */ 1092 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */ 1093 struct amdgpu_device *adev; 1094 }; 1095 1096 static void die_kobj_release(struct kobject *kobj) 1097 { 1098 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 1099 struct ip_discovery_top, 1100 die_kset); 1101 if (!list_empty(&ip_top->die_kset.list)) 1102 DRM_ERROR("ip_top->die_kset is not empty"); 1103 } 1104 1105 static void ip_disc_release(struct kobject *kobj) 1106 { 1107 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 1108 kobj); 1109 struct amdgpu_device *adev = ip_top->adev; 1110 1111 kfree(ip_top); 1112 adev->discovery.ip_top = NULL; 1113 } 1114 1115 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, 1116 uint16_t hw_id, uint8_t inst) 1117 { 1118 uint8_t harvest = 0; 1119 1120 /* Until a uniform way is figured, get mask based on hwid */ 1121 switch (hw_id) { 1122 case VCN_HWID: 1123 /* VCN vs UVD+VCE */ 1124 if (!amdgpu_ip_version(adev, VCE_HWIP, 0)) 1125 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 1126 break; 1127 case DMU_HWID: 1128 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) 1129 harvest = 0x1; 1130 break; 1131 case UMC_HWID: 1132 /* TODO: It needs another parsing; for now, ignore.*/ 1133 break; 1134 case GC_HWID: 1135 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; 1136 break; 1137 case SDMA0_HWID: 1138 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0; 1139 break; 1140 default: 1141 break; 1142 } 1143 1144 return harvest; 1145 } 1146 1147 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 1148 struct ip_die_entry *ip_die_entry, 1149 const size_t _ip_offset, const int num_ips, 1150 bool reg_base_64) 1151 { 1152 uint8_t *discovery_bin = adev->discovery.bin; 1153 int ii, jj, kk, res; 1154 uint16_t hw_id; 1155 uint8_t inst; 1156 1157 DRM_DEBUG("num_ips:%d", num_ips); 1158 1159 /* Find all IPs of a given HW ID, and add their instance to 1160 * #die/#hw_id/#instance/<attributes> 1161 */ 1162 for (ii = 0; ii < HW_ID_MAX; ii++) { 1163 struct ip_hw_id *ip_hw_id = NULL; 1164 size_t ip_offset = _ip_offset; 1165 1166 for (jj = 0; jj < num_ips; jj++) { 1167 struct ip_v4 *ip; 1168 struct ip_hw_instance *ip_hw_instance; 1169 1170 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1171 inst = ip->instance_number; 1172 hw_id = le16_to_cpu(ip->hw_id); 1173 if (amdgpu_discovery_validate_ip(adev, inst, hw_id) || 1174 hw_id != ii) 1175 goto next_ip; 1176 1177 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 1178 1179 /* We have a hw_id match; register the hw 1180 * block if not yet registered. 1181 */ 1182 if (!ip_hw_id) { 1183 ip_hw_id = kzalloc_obj(*ip_hw_id); 1184 if (!ip_hw_id) 1185 return -ENOMEM; 1186 ip_hw_id->hw_id = ii; 1187 1188 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 1189 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 1190 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 1191 res = kset_register(&ip_hw_id->hw_id_kset); 1192 if (res) { 1193 DRM_ERROR("Couldn't register ip_hw_id kset"); 1194 kfree(ip_hw_id); 1195 return res; 1196 } 1197 if (hw_id_names[ii]) { 1198 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 1199 &ip_hw_id->hw_id_kset.kobj, 1200 hw_id_names[ii]); 1201 if (res) { 1202 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 1203 hw_id_names[ii], 1204 kobject_name(&ip_die_entry->ip_kset.kobj)); 1205 } 1206 } 1207 } 1208 1209 /* Now register its instance. 1210 */ 1211 ip_hw_instance = kzalloc_flex(*ip_hw_instance, 1212 base_addr, 1213 ip->num_base_address); 1214 if (!ip_hw_instance) { 1215 DRM_ERROR("no memory for ip_hw_instance"); 1216 return -ENOMEM; 1217 } 1218 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 1219 ip_hw_instance->num_instance = ip->instance_number; 1220 ip_hw_instance->major = ip->major; 1221 ip_hw_instance->minor = ip->minor; 1222 ip_hw_instance->revision = ip->revision; 1223 ip_hw_instance->harvest = 1224 amdgpu_discovery_get_harvest_info( 1225 adev, ip_hw_instance->hw_id, 1226 ip_hw_instance->num_instance); 1227 ip_hw_instance->num_base_addresses = ip->num_base_address; 1228 1229 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) 1230 ip_hw_instance->base_addr[kk] = ip->base_address[kk]; 1231 1232 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 1233 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 1234 res = kobject_add(&ip_hw_instance->kobj, NULL, 1235 "%d", ip_hw_instance->num_instance); 1236 next_ip: 1237 if (reg_base_64) 1238 ip_offset += struct_size(ip, base_address_64, 1239 ip->num_base_address); 1240 else 1241 ip_offset += struct_size(ip, base_address, 1242 ip->num_base_address); 1243 } 1244 } 1245 1246 return 0; 1247 } 1248 1249 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) 1250 { 1251 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1252 uint8_t *discovery_bin = adev->discovery.bin; 1253 struct table_info *info; 1254 struct ip_discovery_header *ihdr; 1255 struct die_header *dhdr; 1256 struct kset *die_kset = &ip_top->die_kset; 1257 u16 num_dies, die_offset, num_ips; 1258 size_t ip_offset; 1259 int ii, res; 1260 1261 res = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY); 1262 if (res) 1263 return res; 1264 ihdr = (struct ip_discovery_header 1265 *)(discovery_bin + 1266 le16_to_cpu(info->offset)); 1267 num_dies = le16_to_cpu(ihdr->num_dies); 1268 1269 DRM_DEBUG("number of dies: %d\n", num_dies); 1270 1271 for (ii = 0; ii < num_dies; ii++) { 1272 struct ip_die_entry *ip_die_entry; 1273 1274 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 1275 dhdr = (struct die_header *)(discovery_bin + die_offset); 1276 num_ips = le16_to_cpu(dhdr->num_ips); 1277 ip_offset = die_offset + sizeof(*dhdr); 1278 1279 /* Add the die to the kset. 1280 * 1281 * dhdr->die_id == ii, which was checked in 1282 * amdgpu_discovery_reg_base_init(). 1283 */ 1284 1285 ip_die_entry = kzalloc_obj(*ip_die_entry); 1286 if (!ip_die_entry) 1287 return -ENOMEM; 1288 1289 ip_die_entry->num_ips = num_ips; 1290 1291 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 1292 ip_die_entry->ip_kset.kobj.kset = die_kset; 1293 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 1294 res = kset_register(&ip_die_entry->ip_kset); 1295 if (res) { 1296 DRM_ERROR("Couldn't register ip_die_entry kset"); 1297 kfree(ip_die_entry); 1298 return res; 1299 } 1300 1301 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit); 1302 } 1303 1304 return 0; 1305 } 1306 1307 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 1308 { 1309 uint8_t *discovery_bin = adev->discovery.bin; 1310 struct ip_discovery_top *ip_top; 1311 struct kset *die_kset; 1312 int res, ii; 1313 1314 if (!discovery_bin) 1315 return -EINVAL; 1316 1317 ip_top = kzalloc_obj(*ip_top); 1318 if (!ip_top) 1319 return -ENOMEM; 1320 1321 ip_top->adev = adev; 1322 adev->discovery.ip_top = ip_top; 1323 res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype, 1324 &adev->dev->kobj, "ip_discovery"); 1325 if (res) { 1326 DRM_ERROR("Couldn't init and add ip_discovery/"); 1327 goto Err; 1328 } 1329 1330 die_kset = &ip_top->die_kset; 1331 kobject_set_name(&die_kset->kobj, "%s", "die"); 1332 die_kset->kobj.parent = &ip_top->kobj; 1333 die_kset->kobj.ktype = &die_kobj_ktype; 1334 res = kset_register(&ip_top->die_kset); 1335 if (res) { 1336 DRM_ERROR("Couldn't register die_kset"); 1337 goto Err; 1338 } 1339 1340 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1341 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1342 ip_hw_instance_attrs[ii] = NULL; 1343 1344 res = amdgpu_discovery_sysfs_recurse(adev); 1345 1346 return res; 1347 Err: 1348 kobject_put(&ip_top->kobj); 1349 return res; 1350 } 1351 1352 /* -------------------------------------------------- */ 1353 1354 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1355 1356 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1357 { 1358 struct list_head *el, *tmp; 1359 struct kset *hw_id_kset; 1360 1361 hw_id_kset = &ip_hw_id->hw_id_kset; 1362 spin_lock(&hw_id_kset->list_lock); 1363 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1364 list_del_init(el); 1365 spin_unlock(&hw_id_kset->list_lock); 1366 /* kobject is embedded in ip_hw_instance */ 1367 kobject_put(list_to_kobj(el)); 1368 spin_lock(&hw_id_kset->list_lock); 1369 } 1370 spin_unlock(&hw_id_kset->list_lock); 1371 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1372 } 1373 1374 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1375 { 1376 struct list_head *el, *tmp; 1377 struct kset *ip_kset; 1378 1379 ip_kset = &ip_die_entry->ip_kset; 1380 spin_lock(&ip_kset->list_lock); 1381 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1382 list_del_init(el); 1383 spin_unlock(&ip_kset->list_lock); 1384 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1385 spin_lock(&ip_kset->list_lock); 1386 } 1387 spin_unlock(&ip_kset->list_lock); 1388 kobject_put(&ip_die_entry->ip_kset.kobj); 1389 } 1390 1391 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1392 { 1393 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1394 struct list_head *el, *tmp; 1395 struct kset *die_kset; 1396 1397 if (!ip_top) 1398 return; 1399 1400 die_kset = &ip_top->die_kset; 1401 spin_lock(&die_kset->list_lock); 1402 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1403 list_del_init(el); 1404 spin_unlock(&die_kset->list_lock); 1405 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1406 spin_lock(&die_kset->list_lock); 1407 } 1408 spin_unlock(&die_kset->list_lock); 1409 kobject_put(&ip_top->die_kset.kobj); 1410 kobject_put(&ip_top->kobj); 1411 } 1412 1413 /* devcoredump support */ 1414 void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p) 1415 { 1416 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1417 struct ip_die_entry *ip_die_entry; 1418 struct list_head *el_die, *el_hw_id, *el_hw_inst; 1419 struct ip_hw_id *hw_id; 1420 struct kset *die_kset; 1421 struct ip_hw_instance *ip_inst; 1422 int i = 0, j; 1423 1424 if (!ip_top) 1425 return; 1426 1427 die_kset = &ip_top->die_kset; 1428 1429 drm_printf(p, "\nHW IP Discovery\n"); 1430 1431 spin_lock(&die_kset->list_lock); 1432 list_for_each(el_die, &die_kset->list) { 1433 drm_printf(p, "die %d\n", i++); 1434 ip_die_entry = to_ip_die_entry(list_to_kobj(el_die)); 1435 1436 list_for_each(el_hw_id, &ip_die_entry->ip_kset.list) { 1437 hw_id = to_ip_hw_id(list_to_kobj(el_hw_id)); 1438 drm_printf(p, "hw_id %d %s\n", hw_id->hw_id, hw_id_names[hw_id->hw_id]); 1439 1440 list_for_each(el_hw_inst, &hw_id->hw_id_kset.list) { 1441 ip_inst = to_ip_hw_instance(list_to_kobj(el_hw_inst)); 1442 drm_printf(p, "\tinstance %d\n", ip_inst->num_instance); 1443 drm_printf(p, "\tmajor %d\n", ip_inst->major); 1444 drm_printf(p, "\tminor %d\n", ip_inst->minor); 1445 drm_printf(p, "\trevision %d\n", ip_inst->revision); 1446 drm_printf(p, "\tharvest 0x%01X\n", ip_inst->harvest); 1447 drm_printf(p, "\tnum_base_addresses %d\n", 1448 ip_inst->num_base_addresses); 1449 for (j = 0; j < ip_inst->num_base_addresses; j++) 1450 drm_printf(p, "\tbase_addr[%d] 0x%08X\n", 1451 j, ip_inst->base_addr[j]); 1452 } 1453 } 1454 } 1455 spin_unlock(&die_kset->list_lock); 1456 } 1457 1458 1459 /* ================================================== */ 1460 1461 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1462 { 1463 uint8_t num_base_address, subrev, variant; 1464 struct table_info *info; 1465 struct ip_discovery_header *ihdr; 1466 struct die_header *dhdr; 1467 uint8_t *discovery_bin; 1468 struct ip_v4 *ip; 1469 uint16_t die_offset; 1470 uint16_t ip_offset; 1471 uint16_t num_dies; 1472 uint32_t wafl_ver; 1473 uint16_t num_ips; 1474 uint16_t hw_id; 1475 uint8_t inst; 1476 int hw_ip; 1477 int i, j, k; 1478 int r; 1479 1480 r = amdgpu_discovery_init(adev); 1481 if (r) 1482 return r; 1483 discovery_bin = adev->discovery.bin; 1484 wafl_ver = 0; 1485 adev->gfx.xcc_mask = 0; 1486 adev->sdma.sdma_mask = 0; 1487 adev->vcn.inst_mask = 0; 1488 adev->jpeg.inst_mask = 0; 1489 r = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY); 1490 if (r) 1491 return r; 1492 ihdr = (struct ip_discovery_header 1493 *)(discovery_bin + 1494 le16_to_cpu(info->offset)); 1495 num_dies = le16_to_cpu(ihdr->num_dies); 1496 1497 DRM_DEBUG("number of dies: %d\n", num_dies); 1498 1499 for (i = 0; i < num_dies; i++) { 1500 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1501 dhdr = (struct die_header *)(discovery_bin + die_offset); 1502 num_ips = le16_to_cpu(dhdr->num_ips); 1503 ip_offset = die_offset + sizeof(*dhdr); 1504 1505 if (le16_to_cpu(dhdr->die_id) != i) { 1506 DRM_ERROR("invalid die id %d, expected %d\n", 1507 le16_to_cpu(dhdr->die_id), i); 1508 return -EINVAL; 1509 } 1510 1511 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1512 le16_to_cpu(dhdr->die_id), num_ips); 1513 1514 for (j = 0; j < num_ips; j++) { 1515 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1516 1517 inst = ip->instance_number; 1518 hw_id = le16_to_cpu(ip->hw_id); 1519 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 1520 goto next_ip; 1521 1522 num_base_address = ip->num_base_address; 1523 1524 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1525 hw_id_names[le16_to_cpu(ip->hw_id)], 1526 le16_to_cpu(ip->hw_id), 1527 ip->instance_number, 1528 ip->major, ip->minor, 1529 ip->revision); 1530 1531 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1532 /* Bit [5:0]: original revision value 1533 * Bit [7:6]: en/decode capability: 1534 * 0b00 : VCN function normally 1535 * 0b10 : encode is disabled 1536 * 0b01 : decode is disabled 1537 */ 1538 if (adev->vcn.num_vcn_inst < 1539 AMDGPU_MAX_VCN_INSTANCES) { 1540 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config = 1541 ip->revision & 0xc0; 1542 adev->vcn.num_vcn_inst++; 1543 adev->vcn.inst_mask |= 1544 (1U << ip->instance_number); 1545 adev->jpeg.inst_mask |= 1546 (1U << ip->instance_number); 1547 } else { 1548 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1549 adev->vcn.num_vcn_inst + 1, 1550 AMDGPU_MAX_VCN_INSTANCES); 1551 } 1552 ip->revision &= ~0xc0; 1553 } 1554 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1555 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1556 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1557 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1558 if (adev->sdma.num_instances < 1559 AMDGPU_MAX_SDMA_INSTANCES) { 1560 adev->sdma.num_instances++; 1561 adev->sdma.sdma_mask |= 1562 (1U << ip->instance_number); 1563 } else { 1564 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1565 adev->sdma.num_instances + 1, 1566 AMDGPU_MAX_SDMA_INSTANCES); 1567 } 1568 } 1569 1570 if (le16_to_cpu(ip->hw_id) == VPE_HWID) { 1571 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES) 1572 adev->vpe.num_instances++; 1573 else 1574 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n", 1575 adev->vpe.num_instances + 1, 1576 AMDGPU_MAX_VPE_INSTANCES); 1577 } 1578 1579 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1580 adev->gmc.num_umc++; 1581 adev->umc.node_inst_num++; 1582 } 1583 1584 if (le16_to_cpu(ip->hw_id) == GC_HWID) 1585 adev->gfx.xcc_mask |= 1586 (1U << ip->instance_number); 1587 1588 if (!wafl_ver && le16_to_cpu(ip->hw_id) == WAFLC_HWID) 1589 wafl_ver = IP_VERSION_FULL(ip->major, ip->minor, 1590 ip->revision, 0, 0); 1591 1592 for (k = 0; k < num_base_address; k++) { 1593 /* 1594 * convert the endianness of base addresses in place, 1595 * so that we don't need to convert them when accessing adev->reg_offset. 1596 */ 1597 if (ihdr->base_addr_64_bit) 1598 /* Truncate the 64bit base address from ip discovery 1599 * and only store lower 32bit ip base in reg_offset[]. 1600 * Bits > 32 follows ASIC specific format, thus just 1601 * discard them and handle it within specific ASIC. 1602 * By this way reg_offset[] and related helpers can 1603 * stay unchanged. 1604 * The base address is in dwords, thus clear the 1605 * highest 2 bits to store. 1606 */ 1607 ip->base_address[k] = 1608 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; 1609 else 1610 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1611 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1612 } 1613 1614 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1615 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && 1616 hw_id_map[hw_ip] != 0) { 1617 DRM_DEBUG("set register base offset for %s\n", 1618 hw_id_names[le16_to_cpu(ip->hw_id)]); 1619 adev->reg_offset[hw_ip][ip->instance_number] = 1620 ip->base_address; 1621 /* Instance support is somewhat inconsistent. 1622 * SDMA is a good example. Sienna cichlid has 4 total 1623 * SDMA instances, each enumerated separately (HWIDs 1624 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1625 * but they are enumerated as multiple instances of the 1626 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1627 * example. On most chips there are multiple instances 1628 * with the same HWID. 1629 */ 1630 1631 if (ihdr->version < 3) { 1632 subrev = 0; 1633 variant = 0; 1634 } else { 1635 subrev = ip->sub_revision; 1636 variant = ip->variant; 1637 } 1638 1639 adev->ip_versions[hw_ip] 1640 [ip->instance_number] = 1641 IP_VERSION_FULL(ip->major, 1642 ip->minor, 1643 ip->revision, 1644 variant, 1645 subrev); 1646 } 1647 } 1648 1649 next_ip: 1650 if (ihdr->base_addr_64_bit) 1651 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 1652 else 1653 ip_offset += struct_size(ip, base_address, ip->num_base_address); 1654 } 1655 } 1656 1657 if (wafl_ver && !adev->ip_versions[XGMI_HWIP][0]) 1658 adev->ip_versions[XGMI_HWIP][0] = wafl_ver; 1659 1660 return 0; 1661 } 1662 1663 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 1664 { 1665 uint8_t *discovery_bin = adev->discovery.bin; 1666 struct ip_discovery_header *ihdr; 1667 struct table_info *info; 1668 int vcn_harvest_count = 0; 1669 int umc_harvest_count = 0; 1670 uint16_t ihdr_ver; 1671 1672 if (amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY)) 1673 return; 1674 ihdr = (struct ip_discovery_header *)(discovery_bin + 1675 le16_to_cpu(info->offset)); 1676 ihdr_ver = le16_to_cpu(ihdr->version); 1677 /* 1678 * Harvest table does not fit Navi1x and legacy GPUs, 1679 * so read harvest bit per IP data structure to set 1680 * harvest configuration. 1681 */ 1682 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) && 1683 ihdr_ver <= 2) { 1684 if ((adev->pdev->device == 0x731E && 1685 (adev->pdev->revision == 0xC6 || 1686 adev->pdev->revision == 0xC7)) || 1687 (adev->pdev->device == 0x7340 && 1688 adev->pdev->revision == 0xC9) || 1689 (adev->pdev->device == 0x7360 && 1690 adev->pdev->revision == 0xC7)) 1691 amdgpu_discovery_read_harvest_bit_per_ip(adev, 1692 &vcn_harvest_count); 1693 } else { 1694 amdgpu_discovery_read_from_harvest_table(adev, 1695 &vcn_harvest_count, 1696 &umc_harvest_count); 1697 } 1698 1699 amdgpu_discovery_harvest_config_quirk(adev); 1700 1701 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 1702 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 1703 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 1704 } 1705 1706 if (umc_harvest_count < adev->gmc.num_umc) { 1707 adev->gmc.num_umc -= umc_harvest_count; 1708 } 1709 } 1710 1711 union gc_info { 1712 struct gc_info_v1_0 v1; 1713 struct gc_info_v1_1 v1_1; 1714 struct gc_info_v1_2 v1_2; 1715 struct gc_info_v1_3 v1_3; 1716 struct gc_info_v2_0 v2; 1717 struct gc_info_v2_1 v2_1; 1718 }; 1719 1720 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 1721 { 1722 uint8_t *discovery_bin = adev->discovery.bin; 1723 struct table_info *info; 1724 union gc_info *gc_info; 1725 u16 offset; 1726 1727 if (!discovery_bin) { 1728 DRM_ERROR("ip discovery uninitialized\n"); 1729 return -EINVAL; 1730 } 1731 1732 if (amdgpu_discovery_get_table_info(adev, &info, GC)) 1733 return -EINVAL; 1734 offset = le16_to_cpu(info->offset); 1735 1736 if (!offset) 1737 return 0; 1738 1739 gc_info = (union gc_info *)(discovery_bin + offset); 1740 1741 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 1742 case 1: 1743 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 1744 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 1745 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 1746 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1747 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 1748 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 1749 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 1750 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 1751 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 1752 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 1753 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 1754 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 1755 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 1756 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 1757 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 1758 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 1759 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 1760 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 1761 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) { 1762 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 1763 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 1764 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 1765 } 1766 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) { 1767 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 1768 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 1769 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 1770 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 1771 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 1772 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 1773 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 1774 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 1775 } 1776 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) { 1777 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu); 1778 adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size); 1779 adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc); 1780 adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size); 1781 adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc); 1782 adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size); 1783 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size); 1784 adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size); 1785 } 1786 break; 1787 case 2: 1788 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 1789 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 1790 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1791 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 1792 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 1793 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 1794 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 1795 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 1796 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 1797 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 1798 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 1799 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 1800 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 1801 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 1802 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 1803 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 1804 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 1805 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) { 1806 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); 1807 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); 1808 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */ 1809 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); 1810 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc); 1811 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc); 1812 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ 1813 } 1814 break; 1815 default: 1816 dev_err(adev->dev, 1817 "Unhandled GC info table %d.%d\n", 1818 le16_to_cpu(gc_info->v1.header.version_major), 1819 le16_to_cpu(gc_info->v1.header.version_minor)); 1820 return -EINVAL; 1821 } 1822 return 0; 1823 } 1824 1825 union mall_info { 1826 struct mall_info_v1_0 v1; 1827 struct mall_info_v2_0 v2; 1828 }; 1829 1830 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 1831 { 1832 uint8_t *discovery_bin = adev->discovery.bin; 1833 struct table_info *info; 1834 union mall_info *mall_info; 1835 u32 u, mall_size_per_umc, m_s_present, half_use; 1836 u64 mall_size; 1837 u16 offset; 1838 1839 if (!discovery_bin) { 1840 DRM_ERROR("ip discovery uninitialized\n"); 1841 return -EINVAL; 1842 } 1843 1844 if (amdgpu_discovery_get_table_info(adev, &info, MALL_INFO)) 1845 return -EINVAL; 1846 offset = le16_to_cpu(info->offset); 1847 1848 if (!offset) 1849 return 0; 1850 1851 mall_info = (union mall_info *)(discovery_bin + offset); 1852 1853 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 1854 case 1: 1855 mall_size = 0; 1856 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 1857 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 1858 half_use = le32_to_cpu(mall_info->v1.m_half_use); 1859 for (u = 0; u < adev->gmc.num_umc; u++) { 1860 if (m_s_present & (1 << u)) 1861 mall_size += mall_size_per_umc * 2; 1862 else if (half_use & (1 << u)) 1863 mall_size += mall_size_per_umc / 2; 1864 else 1865 mall_size += mall_size_per_umc; 1866 } 1867 adev->gmc.mall_size = mall_size; 1868 adev->gmc.m_half_use = half_use; 1869 break; 1870 case 2: 1871 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); 1872 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc; 1873 break; 1874 default: 1875 dev_err(adev->dev, 1876 "Unhandled MALL info table %d.%d\n", 1877 le16_to_cpu(mall_info->v1.header.version_major), 1878 le16_to_cpu(mall_info->v1.header.version_minor)); 1879 return -EINVAL; 1880 } 1881 return 0; 1882 } 1883 1884 union vcn_info { 1885 struct vcn_info_v1_0 v1; 1886 }; 1887 1888 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 1889 { 1890 uint8_t *discovery_bin = adev->discovery.bin; 1891 struct table_info *info; 1892 union vcn_info *vcn_info; 1893 u16 offset; 1894 int v; 1895 1896 if (!discovery_bin) { 1897 DRM_ERROR("ip discovery uninitialized\n"); 1898 return -EINVAL; 1899 } 1900 1901 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1902 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 1903 * but that may change in the future with new GPUs so keep this 1904 * check for defensive purposes. 1905 */ 1906 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 1907 dev_err(adev->dev, "invalid vcn instances\n"); 1908 return -EINVAL; 1909 } 1910 1911 if (amdgpu_discovery_get_table_info(adev, &info, VCN_INFO)) 1912 return -EINVAL; 1913 offset = le16_to_cpu(info->offset); 1914 1915 if (!offset) 1916 return 0; 1917 1918 vcn_info = (union vcn_info *)(discovery_bin + offset); 1919 1920 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 1921 case 1: 1922 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 1923 * so this won't overflow. 1924 */ 1925 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 1926 adev->vcn.inst[v].vcn_codec_disable_mask = 1927 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 1928 } 1929 break; 1930 default: 1931 dev_err(adev->dev, 1932 "Unhandled VCN info table %d.%d\n", 1933 le16_to_cpu(vcn_info->v1.header.version_major), 1934 le16_to_cpu(vcn_info->v1.header.version_minor)); 1935 return -EINVAL; 1936 } 1937 return 0; 1938 } 1939 1940 union nps_info { 1941 struct nps_info_v1_0 v1; 1942 }; 1943 1944 static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev, 1945 union nps_info *nps_data) 1946 { 1947 uint64_t vram_size, pos, offset; 1948 struct nps_info_header *nhdr; 1949 struct binary_header bhdr; 1950 struct binary_header_v2 bhdrv2; 1951 uint16_t checksum; 1952 1953 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 1954 pos = vram_size - DISCOVERY_TMR_OFFSET; 1955 amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false); 1956 1957 switch (bhdr.version_major) { 1958 case 2: 1959 amdgpu_device_vram_access(adev, pos, &bhdrv2, sizeof(bhdrv2), false); 1960 offset = le16_to_cpu(bhdrv2.table_list[NPS_INFO].offset); 1961 checksum = le16_to_cpu(bhdrv2.table_list[NPS_INFO].checksum); 1962 break; 1963 case 1: 1964 offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset); 1965 checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum); 1966 break; 1967 default: 1968 return -EINVAL; 1969 } 1970 1971 amdgpu_device_vram_access(adev, (pos + offset), nps_data, 1972 sizeof(*nps_data), false); 1973 1974 nhdr = (struct nps_info_header *)(nps_data); 1975 if (!amdgpu_discovery_verify_checksum(adev, (uint8_t *)nps_data, 1976 le32_to_cpu(nhdr->size_bytes), 1977 checksum)) { 1978 dev_err(adev->dev, "nps data refresh, checksum mismatch\n"); 1979 return -EINVAL; 1980 } 1981 1982 return 0; 1983 } 1984 1985 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, 1986 uint32_t *nps_type, 1987 struct amdgpu_gmc_memrange *ranges, 1988 int *range_cnt, bool refresh) 1989 { 1990 uint8_t *discovery_bin = adev->discovery.bin; 1991 struct table_info *info; 1992 union nps_info *nps_info; 1993 union nps_info nps_data; 1994 u16 offset; 1995 int i, r; 1996 1997 if (!nps_type || !range_cnt || !ranges) 1998 return -EINVAL; 1999 2000 if (refresh) { 2001 r = amdgpu_discovery_refresh_nps_info(adev, &nps_data); 2002 if (r) 2003 return r; 2004 nps_info = &nps_data; 2005 } else { 2006 if (!discovery_bin) { 2007 dev_err(adev->dev, 2008 "fetch mem range failed, ip discovery uninitialized\n"); 2009 return -EINVAL; 2010 } 2011 2012 if (amdgpu_discovery_get_table_info(adev, &info, NPS_INFO)) 2013 return -EINVAL; 2014 offset = le16_to_cpu(info->offset); 2015 2016 if (!offset) 2017 return -ENOENT; 2018 2019 /* If verification fails, return as if NPS table doesn't exist */ 2020 if (amdgpu_discovery_verify_npsinfo(adev, info)) 2021 return -ENOENT; 2022 2023 nps_info = (union nps_info *)(discovery_bin + offset); 2024 } 2025 2026 switch (le16_to_cpu(nps_info->v1.header.version_major)) { 2027 case 1: 2028 *nps_type = nps_info->v1.nps_type; 2029 if (*range_cnt < nps_info->v1.count) { 2030 dev_dbg(adev->dev, 2031 "not enough space for nps ranges: %d < %d\n", 2032 *range_cnt, nps_info->v1.count); 2033 return -ENOSPC; 2034 } 2035 *range_cnt = nps_info->v1.count; 2036 for (i = 0; i < *range_cnt; i++) { 2037 ranges[i].base_address = 2038 nps_info->v1.instance_info[i].base_address; 2039 ranges[i].limit_address = 2040 nps_info->v1.instance_info[i].limit_address; 2041 ranges[i].nid_mask = -1; 2042 ranges[i].flags = 0; 2043 } 2044 break; 2045 default: 2046 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n", 2047 le16_to_cpu(nps_info->v1.header.version_major), 2048 le16_to_cpu(nps_info->v1.header.version_minor)); 2049 return -EINVAL; 2050 } 2051 2052 return 0; 2053 } 2054 2055 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 2056 { 2057 /* what IP to use for this? */ 2058 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2059 case IP_VERSION(9, 0, 1): 2060 case IP_VERSION(9, 1, 0): 2061 case IP_VERSION(9, 2, 1): 2062 case IP_VERSION(9, 2, 2): 2063 case IP_VERSION(9, 3, 0): 2064 case IP_VERSION(9, 4, 0): 2065 case IP_VERSION(9, 4, 1): 2066 case IP_VERSION(9, 4, 2): 2067 case IP_VERSION(9, 4, 3): 2068 case IP_VERSION(9, 4, 4): 2069 case IP_VERSION(9, 5, 0): 2070 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 2071 break; 2072 case IP_VERSION(10, 1, 10): 2073 case IP_VERSION(10, 1, 1): 2074 case IP_VERSION(10, 1, 2): 2075 case IP_VERSION(10, 1, 3): 2076 case IP_VERSION(10, 1, 4): 2077 case IP_VERSION(10, 3, 0): 2078 case IP_VERSION(10, 3, 1): 2079 case IP_VERSION(10, 3, 2): 2080 case IP_VERSION(10, 3, 3): 2081 case IP_VERSION(10, 3, 4): 2082 case IP_VERSION(10, 3, 5): 2083 case IP_VERSION(10, 3, 6): 2084 case IP_VERSION(10, 3, 7): 2085 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 2086 break; 2087 case IP_VERSION(11, 0, 0): 2088 case IP_VERSION(11, 0, 1): 2089 case IP_VERSION(11, 0, 2): 2090 case IP_VERSION(11, 0, 3): 2091 case IP_VERSION(11, 0, 4): 2092 case IP_VERSION(11, 5, 0): 2093 case IP_VERSION(11, 5, 1): 2094 case IP_VERSION(11, 5, 2): 2095 case IP_VERSION(11, 5, 3): 2096 case IP_VERSION(11, 5, 4): 2097 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 2098 break; 2099 case IP_VERSION(12, 0, 0): 2100 case IP_VERSION(12, 0, 1): 2101 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block); 2102 break; 2103 case IP_VERSION(12, 1, 0): 2104 amdgpu_device_ip_block_add(adev, &soc_v1_0_common_ip_block); 2105 break; 2106 default: 2107 dev_err(adev->dev, 2108 "Failed to add common ip block(GC_HWIP:0x%x)\n", 2109 amdgpu_ip_version(adev, GC_HWIP, 0)); 2110 return -EINVAL; 2111 } 2112 return 0; 2113 } 2114 2115 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 2116 { 2117 /* use GC or MMHUB IP version */ 2118 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2119 case IP_VERSION(9, 0, 1): 2120 case IP_VERSION(9, 1, 0): 2121 case IP_VERSION(9, 2, 1): 2122 case IP_VERSION(9, 2, 2): 2123 case IP_VERSION(9, 3, 0): 2124 case IP_VERSION(9, 4, 0): 2125 case IP_VERSION(9, 4, 1): 2126 case IP_VERSION(9, 4, 2): 2127 case IP_VERSION(9, 4, 3): 2128 case IP_VERSION(9, 4, 4): 2129 case IP_VERSION(9, 5, 0): 2130 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 2131 break; 2132 case IP_VERSION(10, 1, 10): 2133 case IP_VERSION(10, 1, 1): 2134 case IP_VERSION(10, 1, 2): 2135 case IP_VERSION(10, 1, 3): 2136 case IP_VERSION(10, 1, 4): 2137 case IP_VERSION(10, 3, 0): 2138 case IP_VERSION(10, 3, 1): 2139 case IP_VERSION(10, 3, 2): 2140 case IP_VERSION(10, 3, 3): 2141 case IP_VERSION(10, 3, 4): 2142 case IP_VERSION(10, 3, 5): 2143 case IP_VERSION(10, 3, 6): 2144 case IP_VERSION(10, 3, 7): 2145 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 2146 break; 2147 case IP_VERSION(11, 0, 0): 2148 case IP_VERSION(11, 0, 1): 2149 case IP_VERSION(11, 0, 2): 2150 case IP_VERSION(11, 0, 3): 2151 case IP_VERSION(11, 0, 4): 2152 case IP_VERSION(11, 5, 0): 2153 case IP_VERSION(11, 5, 1): 2154 case IP_VERSION(11, 5, 2): 2155 case IP_VERSION(11, 5, 3): 2156 case IP_VERSION(11, 5, 4): 2157 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 2158 break; 2159 case IP_VERSION(12, 0, 0): 2160 case IP_VERSION(12, 0, 1): 2161 case IP_VERSION(12, 1, 0): 2162 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block); 2163 break; 2164 default: 2165 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 2166 amdgpu_ip_version(adev, GC_HWIP, 0)); 2167 return -EINVAL; 2168 } 2169 return 0; 2170 } 2171 2172 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 2173 { 2174 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { 2175 case IP_VERSION(4, 0, 0): 2176 case IP_VERSION(4, 0, 1): 2177 case IP_VERSION(4, 1, 0): 2178 case IP_VERSION(4, 1, 1): 2179 case IP_VERSION(4, 3, 0): 2180 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 2181 break; 2182 case IP_VERSION(4, 2, 0): 2183 case IP_VERSION(4, 2, 1): 2184 case IP_VERSION(4, 4, 0): 2185 case IP_VERSION(4, 4, 2): 2186 case IP_VERSION(4, 4, 5): 2187 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 2188 break; 2189 case IP_VERSION(5, 0, 0): 2190 case IP_VERSION(5, 0, 1): 2191 case IP_VERSION(5, 0, 2): 2192 case IP_VERSION(5, 0, 3): 2193 case IP_VERSION(5, 2, 0): 2194 case IP_VERSION(5, 2, 1): 2195 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 2196 break; 2197 case IP_VERSION(6, 0, 0): 2198 case IP_VERSION(6, 0, 1): 2199 case IP_VERSION(6, 0, 2): 2200 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 2201 break; 2202 case IP_VERSION(6, 1, 0): 2203 case IP_VERSION(6, 1, 1): 2204 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); 2205 break; 2206 case IP_VERSION(7, 0, 0): 2207 case IP_VERSION(7, 1, 0): 2208 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block); 2209 break; 2210 default: 2211 dev_err(adev->dev, 2212 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 2213 amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); 2214 return -EINVAL; 2215 } 2216 return 0; 2217 } 2218 2219 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 2220 { 2221 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2222 case IP_VERSION(9, 0, 0): 2223 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 2224 break; 2225 case IP_VERSION(10, 0, 0): 2226 case IP_VERSION(10, 0, 1): 2227 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 2228 break; 2229 case IP_VERSION(11, 0, 0): 2230 case IP_VERSION(11, 0, 2): 2231 case IP_VERSION(11, 0, 4): 2232 case IP_VERSION(11, 0, 5): 2233 case IP_VERSION(11, 0, 9): 2234 case IP_VERSION(11, 0, 7): 2235 case IP_VERSION(11, 0, 11): 2236 case IP_VERSION(11, 0, 12): 2237 case IP_VERSION(11, 0, 13): 2238 case IP_VERSION(11, 5, 0): 2239 case IP_VERSION(11, 5, 2): 2240 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 2241 break; 2242 case IP_VERSION(11, 0, 8): 2243 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 2244 break; 2245 case IP_VERSION(11, 0, 3): 2246 case IP_VERSION(12, 0, 1): 2247 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 2248 break; 2249 case IP_VERSION(13, 0, 0): 2250 case IP_VERSION(13, 0, 1): 2251 case IP_VERSION(13, 0, 2): 2252 case IP_VERSION(13, 0, 3): 2253 case IP_VERSION(13, 0, 5): 2254 case IP_VERSION(13, 0, 6): 2255 case IP_VERSION(13, 0, 7): 2256 case IP_VERSION(13, 0, 8): 2257 case IP_VERSION(13, 0, 10): 2258 case IP_VERSION(13, 0, 11): 2259 case IP_VERSION(13, 0, 12): 2260 case IP_VERSION(13, 0, 14): 2261 case IP_VERSION(13, 0, 15): 2262 case IP_VERSION(14, 0, 0): 2263 case IP_VERSION(14, 0, 1): 2264 case IP_VERSION(14, 0, 4): 2265 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 2266 break; 2267 case IP_VERSION(13, 0, 4): 2268 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 2269 break; 2270 case IP_VERSION(14, 0, 2): 2271 case IP_VERSION(14, 0, 3): 2272 case IP_VERSION(14, 0, 5): 2273 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block); 2274 break; 2275 case IP_VERSION(15, 0, 0): 2276 amdgpu_device_ip_block_add(adev, &psp_v15_0_ip_block); 2277 break; 2278 case IP_VERSION(15, 0, 8): 2279 amdgpu_device_ip_block_add(adev, &psp_v15_0_8_ip_block); 2280 break; 2281 default: 2282 dev_err(adev->dev, 2283 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 2284 amdgpu_ip_version(adev, MP0_HWIP, 0)); 2285 return -EINVAL; 2286 } 2287 return 0; 2288 } 2289 2290 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 2291 { 2292 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2293 case IP_VERSION(9, 0, 0): 2294 case IP_VERSION(10, 0, 0): 2295 case IP_VERSION(10, 0, 1): 2296 case IP_VERSION(11, 0, 2): 2297 if (adev->asic_type == CHIP_ARCTURUS) 2298 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2299 else 2300 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2301 break; 2302 case IP_VERSION(11, 0, 0): 2303 case IP_VERSION(11, 0, 5): 2304 case IP_VERSION(11, 0, 9): 2305 case IP_VERSION(11, 0, 7): 2306 case IP_VERSION(11, 0, 11): 2307 case IP_VERSION(11, 0, 12): 2308 case IP_VERSION(11, 0, 13): 2309 case IP_VERSION(11, 5, 0): 2310 case IP_VERSION(11, 5, 2): 2311 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2312 break; 2313 case IP_VERSION(11, 0, 8): 2314 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) 2315 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2316 break; 2317 case IP_VERSION(12, 0, 0): 2318 case IP_VERSION(12, 0, 1): 2319 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 2320 break; 2321 case IP_VERSION(13, 0, 0): 2322 case IP_VERSION(13, 0, 1): 2323 case IP_VERSION(13, 0, 2): 2324 case IP_VERSION(13, 0, 3): 2325 case IP_VERSION(13, 0, 4): 2326 case IP_VERSION(13, 0, 5): 2327 case IP_VERSION(13, 0, 6): 2328 case IP_VERSION(13, 0, 7): 2329 case IP_VERSION(13, 0, 8): 2330 case IP_VERSION(13, 0, 10): 2331 case IP_VERSION(13, 0, 11): 2332 case IP_VERSION(13, 0, 14): 2333 case IP_VERSION(13, 0, 12): 2334 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 2335 break; 2336 case IP_VERSION(14, 0, 0): 2337 case IP_VERSION(14, 0, 1): 2338 case IP_VERSION(14, 0, 2): 2339 case IP_VERSION(14, 0, 3): 2340 case IP_VERSION(14, 0, 4): 2341 case IP_VERSION(14, 0, 5): 2342 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block); 2343 break; 2344 case IP_VERSION(15, 0, 0): 2345 case IP_VERSION(15, 0, 8): 2346 amdgpu_device_ip_block_add(adev, &smu_v15_0_ip_block); 2347 break; 2348 default: 2349 dev_err(adev->dev, 2350 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 2351 amdgpu_ip_version(adev, MP1_HWIP, 0)); 2352 return -EINVAL; 2353 } 2354 return 0; 2355 } 2356 2357 #if defined(CONFIG_DRM_AMD_DC) 2358 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 2359 { 2360 amdgpu_device_set_sriov_virtual_display(adev); 2361 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2362 } 2363 #endif 2364 2365 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 2366 { 2367 if (adev->enable_virtual_display) { 2368 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2369 return 0; 2370 } 2371 2372 if (!amdgpu_device_has_dc_support(adev)) 2373 return 0; 2374 2375 #if defined(CONFIG_DRM_AMD_DC) 2376 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2377 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2378 case IP_VERSION(1, 0, 0): 2379 case IP_VERSION(1, 0, 1): 2380 case IP_VERSION(2, 0, 2): 2381 case IP_VERSION(2, 0, 0): 2382 case IP_VERSION(2, 0, 3): 2383 case IP_VERSION(2, 1, 0): 2384 case IP_VERSION(3, 0, 0): 2385 case IP_VERSION(3, 0, 2): 2386 case IP_VERSION(3, 0, 3): 2387 case IP_VERSION(3, 0, 1): 2388 case IP_VERSION(3, 1, 2): 2389 case IP_VERSION(3, 1, 3): 2390 case IP_VERSION(3, 1, 4): 2391 case IP_VERSION(3, 1, 5): 2392 case IP_VERSION(3, 1, 6): 2393 case IP_VERSION(3, 2, 0): 2394 case IP_VERSION(3, 2, 1): 2395 case IP_VERSION(3, 5, 0): 2396 case IP_VERSION(3, 5, 1): 2397 case IP_VERSION(3, 6, 0): 2398 case IP_VERSION(4, 1, 0): 2399 case IP_VERSION(4, 2, 0): 2400 /* TODO: Fix IP version. DC code expects version 4.0.1 */ 2401 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0)) 2402 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1); 2403 2404 if (amdgpu_sriov_vf(adev)) 2405 amdgpu_discovery_set_sriov_display(adev); 2406 else 2407 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2408 break; 2409 default: 2410 dev_err(adev->dev, 2411 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 2412 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2413 return -EINVAL; 2414 } 2415 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2416 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 2417 case IP_VERSION(12, 0, 0): 2418 case IP_VERSION(12, 0, 1): 2419 case IP_VERSION(12, 1, 0): 2420 if (amdgpu_sriov_vf(adev)) 2421 amdgpu_discovery_set_sriov_display(adev); 2422 else 2423 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2424 break; 2425 default: 2426 dev_err(adev->dev, 2427 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 2428 amdgpu_ip_version(adev, DCI_HWIP, 0)); 2429 return -EINVAL; 2430 } 2431 } 2432 #endif 2433 return 0; 2434 } 2435 2436 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 2437 { 2438 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2439 case IP_VERSION(9, 0, 1): 2440 case IP_VERSION(9, 1, 0): 2441 case IP_VERSION(9, 2, 1): 2442 case IP_VERSION(9, 2, 2): 2443 case IP_VERSION(9, 3, 0): 2444 case IP_VERSION(9, 4, 0): 2445 case IP_VERSION(9, 4, 1): 2446 case IP_VERSION(9, 4, 2): 2447 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 2448 break; 2449 case IP_VERSION(9, 4, 3): 2450 case IP_VERSION(9, 4, 4): 2451 case IP_VERSION(9, 5, 0): 2452 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block); 2453 break; 2454 case IP_VERSION(10, 1, 10): 2455 case IP_VERSION(10, 1, 2): 2456 case IP_VERSION(10, 1, 1): 2457 case IP_VERSION(10, 1, 3): 2458 case IP_VERSION(10, 1, 4): 2459 case IP_VERSION(10, 3, 0): 2460 case IP_VERSION(10, 3, 2): 2461 case IP_VERSION(10, 3, 1): 2462 case IP_VERSION(10, 3, 4): 2463 case IP_VERSION(10, 3, 5): 2464 case IP_VERSION(10, 3, 6): 2465 case IP_VERSION(10, 3, 3): 2466 case IP_VERSION(10, 3, 7): 2467 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 2468 break; 2469 case IP_VERSION(11, 0, 0): 2470 case IP_VERSION(11, 0, 1): 2471 case IP_VERSION(11, 0, 2): 2472 case IP_VERSION(11, 0, 3): 2473 case IP_VERSION(11, 0, 4): 2474 case IP_VERSION(11, 5, 0): 2475 case IP_VERSION(11, 5, 1): 2476 case IP_VERSION(11, 5, 2): 2477 case IP_VERSION(11, 5, 3): 2478 case IP_VERSION(11, 5, 4): 2479 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 2480 break; 2481 case IP_VERSION(12, 0, 0): 2482 case IP_VERSION(12, 0, 1): 2483 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block); 2484 break; 2485 case IP_VERSION(12, 1, 0): 2486 amdgpu_device_ip_block_add(adev, &gfx_v12_1_ip_block); 2487 break; 2488 default: 2489 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 2490 amdgpu_ip_version(adev, GC_HWIP, 0)); 2491 return -EINVAL; 2492 } 2493 return 0; 2494 } 2495 2496 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 2497 { 2498 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2499 case IP_VERSION(4, 0, 0): 2500 case IP_VERSION(4, 0, 1): 2501 case IP_VERSION(4, 1, 0): 2502 case IP_VERSION(4, 1, 1): 2503 case IP_VERSION(4, 1, 2): 2504 case IP_VERSION(4, 2, 0): 2505 case IP_VERSION(4, 2, 2): 2506 case IP_VERSION(4, 4, 0): 2507 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 2508 break; 2509 case IP_VERSION(4, 4, 2): 2510 case IP_VERSION(4, 4, 5): 2511 case IP_VERSION(4, 4, 4): 2512 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 2513 break; 2514 case IP_VERSION(5, 0, 0): 2515 case IP_VERSION(5, 0, 1): 2516 case IP_VERSION(5, 0, 2): 2517 case IP_VERSION(5, 0, 5): 2518 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 2519 break; 2520 case IP_VERSION(5, 2, 0): 2521 case IP_VERSION(5, 2, 2): 2522 case IP_VERSION(5, 2, 4): 2523 case IP_VERSION(5, 2, 5): 2524 case IP_VERSION(5, 2, 6): 2525 case IP_VERSION(5, 2, 3): 2526 case IP_VERSION(5, 2, 1): 2527 case IP_VERSION(5, 2, 7): 2528 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 2529 break; 2530 case IP_VERSION(6, 0, 0): 2531 case IP_VERSION(6, 0, 1): 2532 case IP_VERSION(6, 0, 2): 2533 case IP_VERSION(6, 0, 3): 2534 case IP_VERSION(6, 1, 0): 2535 case IP_VERSION(6, 1, 1): 2536 case IP_VERSION(6, 1, 2): 2537 case IP_VERSION(6, 1, 3): 2538 case IP_VERSION(6, 1, 4): 2539 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 2540 break; 2541 case IP_VERSION(7, 0, 0): 2542 case IP_VERSION(7, 0, 1): 2543 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block); 2544 break; 2545 case IP_VERSION(7, 1, 0): 2546 amdgpu_device_ip_block_add(adev, &sdma_v7_1_ip_block); 2547 break; 2548 default: 2549 dev_err(adev->dev, 2550 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 2551 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 2552 return -EINVAL; 2553 } 2554 2555 return 0; 2556 } 2557 2558 static int amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device *adev) 2559 { 2560 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2561 case IP_VERSION(13, 0, 6): 2562 case IP_VERSION(13, 0, 12): 2563 case IP_VERSION(13, 0, 14): 2564 amdgpu_device_ip_block_add(adev, &ras_v1_0_ip_block); 2565 break; 2566 default: 2567 break; 2568 } 2569 return 0; 2570 } 2571 2572 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 2573 { 2574 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2575 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2576 case IP_VERSION(7, 0, 0): 2577 case IP_VERSION(7, 2, 0): 2578 /* UVD is not supported on vega20 SR-IOV */ 2579 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2580 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 2581 break; 2582 default: 2583 dev_err(adev->dev, 2584 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 2585 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2586 return -EINVAL; 2587 } 2588 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 2589 case IP_VERSION(4, 0, 0): 2590 case IP_VERSION(4, 1, 0): 2591 /* VCE is not supported on vega20 SR-IOV */ 2592 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 2593 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 2594 break; 2595 default: 2596 dev_err(adev->dev, 2597 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 2598 amdgpu_ip_version(adev, VCE_HWIP, 0)); 2599 return -EINVAL; 2600 } 2601 } else { 2602 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 2603 case IP_VERSION(1, 0, 0): 2604 case IP_VERSION(1, 0, 1): 2605 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 2606 break; 2607 case IP_VERSION(2, 0, 0): 2608 case IP_VERSION(2, 0, 2): 2609 case IP_VERSION(2, 2, 0): 2610 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 2611 if (!amdgpu_sriov_vf(adev)) 2612 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 2613 break; 2614 case IP_VERSION(2, 0, 3): 2615 break; 2616 case IP_VERSION(2, 5, 0): 2617 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 2618 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 2619 break; 2620 case IP_VERSION(2, 6, 0): 2621 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 2622 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 2623 break; 2624 case IP_VERSION(3, 0, 0): 2625 case IP_VERSION(3, 0, 16): 2626 case IP_VERSION(3, 1, 1): 2627 case IP_VERSION(3, 1, 2): 2628 case IP_VERSION(3, 0, 2): 2629 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2630 if (!amdgpu_sriov_vf(adev)) 2631 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 2632 break; 2633 case IP_VERSION(3, 0, 33): 2634 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 2635 break; 2636 case IP_VERSION(4, 0, 0): 2637 case IP_VERSION(4, 0, 2): 2638 case IP_VERSION(4, 0, 4): 2639 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 2640 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 2641 break; 2642 case IP_VERSION(4, 0, 3): 2643 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block); 2644 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block); 2645 break; 2646 case IP_VERSION(4, 0, 5): 2647 case IP_VERSION(4, 0, 6): 2648 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block); 2649 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block); 2650 break; 2651 case IP_VERSION(5, 0, 0): 2652 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2653 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block); 2654 break; 2655 case IP_VERSION(5, 3, 0): 2656 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 2657 amdgpu_device_ip_block_add(adev, &jpeg_v5_3_0_ip_block); 2658 break; 2659 case IP_VERSION(5, 0, 1): 2660 amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block); 2661 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block); 2662 break; 2663 case IP_VERSION(5, 0, 2): 2664 amdgpu_device_ip_block_add(adev, &vcn_v5_0_2_ip_block); 2665 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_2_ip_block); 2666 break; 2667 default: 2668 dev_err(adev->dev, 2669 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 2670 amdgpu_ip_version(adev, UVD_HWIP, 0)); 2671 return -EINVAL; 2672 } 2673 } 2674 return 0; 2675 } 2676 2677 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 2678 { 2679 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2680 case IP_VERSION(11, 0, 0): 2681 case IP_VERSION(11, 0, 1): 2682 case IP_VERSION(11, 0, 2): 2683 case IP_VERSION(11, 0, 3): 2684 case IP_VERSION(11, 0, 4): 2685 case IP_VERSION(11, 5, 0): 2686 case IP_VERSION(11, 5, 1): 2687 case IP_VERSION(11, 5, 2): 2688 case IP_VERSION(11, 5, 3): 2689 case IP_VERSION(11, 5, 4): 2690 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 2691 adev->enable_mes = true; 2692 adev->enable_mes_kiq = true; 2693 break; 2694 case IP_VERSION(12, 0, 0): 2695 case IP_VERSION(12, 0, 1): 2696 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block); 2697 adev->enable_mes = true; 2698 adev->enable_mes_kiq = true; 2699 if (amdgpu_uni_mes) 2700 adev->enable_uni_mes = true; 2701 break; 2702 case IP_VERSION(12, 1, 0): 2703 amdgpu_device_ip_block_add(adev, &mes_v12_1_ip_block); 2704 adev->enable_mes = true; 2705 adev->enable_mes_kiq = true; 2706 if (amdgpu_uni_mes) 2707 adev->enable_uni_mes = true; 2708 break; 2709 default: 2710 break; 2711 } 2712 return 0; 2713 } 2714 2715 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 2716 { 2717 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2718 case IP_VERSION(9, 4, 3): 2719 case IP_VERSION(9, 4, 4): 2720 case IP_VERSION(9, 5, 0): 2721 aqua_vanjaram_init_soc_config(adev); 2722 break; 2723 case IP_VERSION(12, 1, 0): 2724 soc_v1_0_init_soc_config(adev); 2725 break; 2726 default: 2727 break; 2728 } 2729 } 2730 2731 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) 2732 { 2733 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 2734 case IP_VERSION(6, 1, 0): 2735 case IP_VERSION(6, 1, 1): 2736 case IP_VERSION(6, 1, 3): 2737 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block); 2738 break; 2739 default: 2740 break; 2741 } 2742 2743 return 0; 2744 } 2745 2746 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev) 2747 { 2748 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2749 case IP_VERSION(4, 0, 5): 2750 case IP_VERSION(4, 0, 6): 2751 if (amdgpu_umsch_mm & 0x1) { 2752 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block); 2753 adev->enable_umsch_mm = true; 2754 } 2755 break; 2756 default: 2757 break; 2758 } 2759 2760 return 0; 2761 } 2762 2763 static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev) 2764 { 2765 #if defined(CONFIG_DRM_AMD_ISP) 2766 switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) { 2767 case IP_VERSION(4, 1, 0): 2768 amdgpu_device_ip_block_add(adev, &isp_v4_1_0_ip_block); 2769 break; 2770 case IP_VERSION(4, 1, 1): 2771 amdgpu_device_ip_block_add(adev, &isp_v4_1_1_ip_block); 2772 break; 2773 default: 2774 break; 2775 } 2776 #endif 2777 2778 return 0; 2779 } 2780 2781 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 2782 { 2783 int r; 2784 2785 switch (adev->asic_type) { 2786 case CHIP_VEGA10: 2787 /* This is not fatal. We only need the discovery 2788 * binary for sysfs. We don't need it for a 2789 * functional system. 2790 */ 2791 amdgpu_discovery_init(adev); 2792 vega10_reg_base_init(adev); 2793 adev->sdma.num_instances = 2; 2794 adev->sdma.sdma_mask = 3; 2795 adev->gmc.num_umc = 4; 2796 adev->gfx.xcc_mask = 1; 2797 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2798 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 2799 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 2800 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 2801 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 2802 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 2803 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2804 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 2805 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 2806 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2807 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2808 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2809 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 2810 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 2811 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2812 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2813 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 2814 break; 2815 case CHIP_VEGA12: 2816 /* This is not fatal. We only need the discovery 2817 * binary for sysfs. We don't need it for a 2818 * functional system. 2819 */ 2820 amdgpu_discovery_init(adev); 2821 vega10_reg_base_init(adev); 2822 adev->sdma.num_instances = 2; 2823 adev->sdma.sdma_mask = 3; 2824 adev->gmc.num_umc = 4; 2825 adev->gfx.xcc_mask = 1; 2826 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2827 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 2828 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 2829 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 2830 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 2831 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 2832 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 2833 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 2834 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 2835 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 2836 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 2837 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 2838 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 2839 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 2840 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 2841 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 2842 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 2843 break; 2844 case CHIP_RAVEN: 2845 /* This is not fatal. We only need the discovery 2846 * binary for sysfs. We don't need it for a 2847 * functional system. 2848 */ 2849 amdgpu_discovery_init(adev); 2850 vega10_reg_base_init(adev); 2851 adev->sdma.num_instances = 1; 2852 adev->sdma.sdma_mask = 1; 2853 adev->vcn.num_vcn_inst = 1; 2854 adev->gmc.num_umc = 2; 2855 adev->gfx.xcc_mask = 1; 2856 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 2857 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2858 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 2859 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 2860 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 2861 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 2862 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 2863 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 2864 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 2865 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 2866 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 2867 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 2868 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 2869 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 2870 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 2871 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 2872 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2873 } else { 2874 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2875 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 2876 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 2877 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 2878 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 2879 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 2880 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 2881 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 2882 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 2883 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 2884 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 2885 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 2886 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 2887 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 2888 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 2889 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 2890 } 2891 break; 2892 case CHIP_VEGA20: 2893 /* This is not fatal. We only need the discovery 2894 * binary for sysfs. We don't need it for a 2895 * functional system. 2896 */ 2897 amdgpu_discovery_init(adev); 2898 vega20_reg_base_init(adev); 2899 adev->sdma.num_instances = 2; 2900 adev->sdma.sdma_mask = 3; 2901 adev->gmc.num_umc = 8; 2902 adev->gfx.xcc_mask = 1; 2903 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2904 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 2905 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 2906 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 2907 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 2908 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 2909 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 2910 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 2911 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 2912 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 2913 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2914 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 2915 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 2916 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 2917 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 2918 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 2919 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 2920 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 2921 break; 2922 case CHIP_ARCTURUS: 2923 /* This is not fatal. We only need the discovery 2924 * binary for sysfs. We don't need it for a 2925 * functional system. 2926 */ 2927 amdgpu_discovery_init(adev); 2928 arct_reg_base_init(adev); 2929 adev->sdma.num_instances = 8; 2930 adev->sdma.sdma_mask = 0xff; 2931 adev->vcn.num_vcn_inst = 2; 2932 adev->gmc.num_umc = 8; 2933 adev->gfx.xcc_mask = 1; 2934 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2935 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 2936 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 2937 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 2938 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 2939 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 2940 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 2941 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 2942 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 2943 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 2944 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 2945 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 2946 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 2947 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 2948 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 2949 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 2950 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 2951 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 2952 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 2953 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 2954 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 2955 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 2956 break; 2957 case CHIP_ALDEBARAN: 2958 /* This is not fatal. We only need the discovery 2959 * binary for sysfs. We don't need it for a 2960 * functional system. 2961 */ 2962 amdgpu_discovery_init(adev); 2963 aldebaran_reg_base_init(adev); 2964 adev->sdma.num_instances = 5; 2965 adev->sdma.sdma_mask = 0x1f; 2966 adev->vcn.num_vcn_inst = 2; 2967 adev->gmc.num_umc = 4; 2968 adev->gfx.xcc_mask = 1; 2969 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2970 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 2971 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 2972 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 2973 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 2974 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 2975 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 2976 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 2977 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 2978 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 2979 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 2980 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 2981 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 2982 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 2983 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 2984 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 2985 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 2986 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2987 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2988 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2989 break; 2990 case CHIP_CYAN_SKILLFISH: 2991 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 2992 r = amdgpu_discovery_reg_base_init(adev); 2993 if (r) 2994 return -EINVAL; 2995 2996 amdgpu_discovery_harvest_ip(adev); 2997 amdgpu_discovery_get_gfx_info(adev); 2998 amdgpu_discovery_get_mall_info(adev); 2999 amdgpu_discovery_get_vcn_info(adev); 3000 } else { 3001 cyan_skillfish_reg_base_init(adev); 3002 adev->sdma.num_instances = 2; 3003 adev->sdma.sdma_mask = 3; 3004 adev->gfx.xcc_mask = 1; 3005 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3); 3006 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(2, 0, 3); 3007 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(5, 0, 1); 3008 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(5, 0, 1); 3009 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(5, 0, 1); 3010 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(5, 0, 1); 3011 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 5, 0); 3012 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1); 3013 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(8, 1, 1); 3014 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 8); 3015 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 8); 3016 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 1); 3017 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 8); 3018 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 1, 3); 3019 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 0, 3); 3020 } 3021 break; 3022 default: 3023 r = amdgpu_discovery_reg_base_init(adev); 3024 if (r) { 3025 drm_err(&adev->ddev, "discovery failed: %d\n", r); 3026 return r; 3027 } 3028 3029 amdgpu_discovery_harvest_ip(adev); 3030 amdgpu_discovery_get_gfx_info(adev); 3031 amdgpu_discovery_get_mall_info(adev); 3032 amdgpu_discovery_get_vcn_info(adev); 3033 break; 3034 } 3035 3036 amdgpu_discovery_init_soc_config(adev); 3037 amdgpu_discovery_sysfs_init(adev); 3038 3039 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3040 case IP_VERSION(9, 0, 1): 3041 case IP_VERSION(9, 2, 1): 3042 case IP_VERSION(9, 4, 0): 3043 case IP_VERSION(9, 4, 1): 3044 case IP_VERSION(9, 4, 2): 3045 case IP_VERSION(9, 4, 3): 3046 case IP_VERSION(9, 4, 4): 3047 case IP_VERSION(9, 5, 0): 3048 adev->family = AMDGPU_FAMILY_AI; 3049 break; 3050 case IP_VERSION(9, 1, 0): 3051 case IP_VERSION(9, 2, 2): 3052 case IP_VERSION(9, 3, 0): 3053 adev->family = AMDGPU_FAMILY_RV; 3054 break; 3055 case IP_VERSION(10, 1, 10): 3056 case IP_VERSION(10, 1, 1): 3057 case IP_VERSION(10, 1, 2): 3058 case IP_VERSION(10, 1, 3): 3059 case IP_VERSION(10, 1, 4): 3060 case IP_VERSION(10, 3, 0): 3061 case IP_VERSION(10, 3, 2): 3062 case IP_VERSION(10, 3, 4): 3063 case IP_VERSION(10, 3, 5): 3064 adev->family = AMDGPU_FAMILY_NV; 3065 break; 3066 case IP_VERSION(10, 3, 1): 3067 adev->family = AMDGPU_FAMILY_VGH; 3068 adev->apu_flags |= AMD_APU_IS_VANGOGH; 3069 break; 3070 case IP_VERSION(10, 3, 3): 3071 adev->family = AMDGPU_FAMILY_YC; 3072 break; 3073 case IP_VERSION(10, 3, 6): 3074 adev->family = AMDGPU_FAMILY_GC_10_3_6; 3075 break; 3076 case IP_VERSION(10, 3, 7): 3077 adev->family = AMDGPU_FAMILY_GC_10_3_7; 3078 break; 3079 case IP_VERSION(11, 0, 0): 3080 case IP_VERSION(11, 0, 2): 3081 case IP_VERSION(11, 0, 3): 3082 adev->family = AMDGPU_FAMILY_GC_11_0_0; 3083 break; 3084 case IP_VERSION(11, 0, 1): 3085 case IP_VERSION(11, 0, 4): 3086 adev->family = AMDGPU_FAMILY_GC_11_0_1; 3087 break; 3088 case IP_VERSION(11, 5, 0): 3089 case IP_VERSION(11, 5, 1): 3090 case IP_VERSION(11, 5, 2): 3091 case IP_VERSION(11, 5, 3): 3092 adev->family = AMDGPU_FAMILY_GC_11_5_0; 3093 break; 3094 case IP_VERSION(11, 5, 4): 3095 adev->family = AMDGPU_FAMILY_GC_11_5_4; 3096 break; 3097 case IP_VERSION(12, 0, 0): 3098 case IP_VERSION(12, 0, 1): 3099 case IP_VERSION(12, 1, 0): 3100 adev->family = AMDGPU_FAMILY_GC_12_0_0; 3101 break; 3102 default: 3103 return -EINVAL; 3104 } 3105 3106 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3107 case IP_VERSION(9, 1, 0): 3108 case IP_VERSION(9, 2, 2): 3109 case IP_VERSION(9, 3, 0): 3110 case IP_VERSION(10, 1, 3): 3111 case IP_VERSION(10, 1, 4): 3112 case IP_VERSION(10, 3, 1): 3113 case IP_VERSION(10, 3, 3): 3114 case IP_VERSION(10, 3, 6): 3115 case IP_VERSION(10, 3, 7): 3116 case IP_VERSION(11, 0, 1): 3117 case IP_VERSION(11, 0, 4): 3118 case IP_VERSION(11, 5, 0): 3119 case IP_VERSION(11, 5, 1): 3120 case IP_VERSION(11, 5, 2): 3121 case IP_VERSION(11, 5, 3): 3122 case IP_VERSION(11, 5, 4): 3123 adev->flags |= AMD_IS_APU; 3124 break; 3125 default: 3126 break; 3127 } 3128 3129 /* set NBIO version */ 3130 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 3131 case IP_VERSION(6, 1, 0): 3132 case IP_VERSION(6, 2, 0): 3133 adev->nbio.funcs = &nbio_v6_1_funcs; 3134 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 3135 break; 3136 case IP_VERSION(7, 0, 0): 3137 case IP_VERSION(7, 0, 1): 3138 case IP_VERSION(2, 5, 0): 3139 adev->nbio.funcs = &nbio_v7_0_funcs; 3140 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 3141 break; 3142 case IP_VERSION(7, 4, 0): 3143 case IP_VERSION(7, 4, 1): 3144 case IP_VERSION(7, 4, 4): 3145 adev->nbio.funcs = &nbio_v7_4_funcs; 3146 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 3147 break; 3148 case IP_VERSION(7, 9, 0): 3149 case IP_VERSION(7, 9, 1): 3150 adev->nbio.funcs = &nbio_v7_9_funcs; 3151 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 3152 break; 3153 case IP_VERSION(7, 11, 0): 3154 case IP_VERSION(7, 11, 1): 3155 case IP_VERSION(7, 11, 2): 3156 case IP_VERSION(7, 11, 3): 3157 adev->nbio.funcs = &nbio_v7_11_funcs; 3158 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; 3159 break; 3160 case IP_VERSION(7, 2, 0): 3161 case IP_VERSION(7, 2, 1): 3162 case IP_VERSION(7, 3, 0): 3163 case IP_VERSION(7, 5, 0): 3164 case IP_VERSION(7, 5, 1): 3165 adev->nbio.funcs = &nbio_v7_2_funcs; 3166 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 3167 break; 3168 case IP_VERSION(2, 1, 1): 3169 case IP_VERSION(2, 3, 0): 3170 case IP_VERSION(2, 3, 1): 3171 case IP_VERSION(2, 3, 2): 3172 case IP_VERSION(3, 3, 0): 3173 case IP_VERSION(3, 3, 1): 3174 case IP_VERSION(3, 3, 2): 3175 case IP_VERSION(3, 3, 3): 3176 adev->nbio.funcs = &nbio_v2_3_funcs; 3177 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 3178 break; 3179 case IP_VERSION(4, 3, 0): 3180 case IP_VERSION(4, 3, 1): 3181 if (amdgpu_sriov_vf(adev)) 3182 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 3183 else 3184 adev->nbio.funcs = &nbio_v4_3_funcs; 3185 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 3186 break; 3187 case IP_VERSION(7, 7, 0): 3188 case IP_VERSION(7, 7, 1): 3189 adev->nbio.funcs = &nbio_v7_7_funcs; 3190 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 3191 break; 3192 case IP_VERSION(6, 3, 1): 3193 case IP_VERSION(7, 11, 4): 3194 adev->nbio.funcs = &nbif_v6_3_1_funcs; 3195 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; 3196 break; 3197 default: 3198 break; 3199 } 3200 3201 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { 3202 case IP_VERSION(4, 0, 0): 3203 case IP_VERSION(4, 0, 1): 3204 case IP_VERSION(4, 1, 0): 3205 case IP_VERSION(4, 1, 1): 3206 case IP_VERSION(4, 1, 2): 3207 case IP_VERSION(4, 2, 0): 3208 case IP_VERSION(4, 2, 1): 3209 case IP_VERSION(4, 4, 0): 3210 case IP_VERSION(4, 4, 2): 3211 case IP_VERSION(4, 4, 5): 3212 adev->hdp.funcs = &hdp_v4_0_funcs; 3213 break; 3214 case IP_VERSION(5, 0, 0): 3215 case IP_VERSION(5, 0, 1): 3216 case IP_VERSION(5, 0, 2): 3217 case IP_VERSION(5, 0, 3): 3218 case IP_VERSION(5, 0, 4): 3219 case IP_VERSION(5, 2, 0): 3220 adev->hdp.funcs = &hdp_v5_0_funcs; 3221 break; 3222 case IP_VERSION(5, 2, 1): 3223 adev->hdp.funcs = &hdp_v5_2_funcs; 3224 break; 3225 case IP_VERSION(6, 0, 0): 3226 case IP_VERSION(6, 0, 1): 3227 case IP_VERSION(6, 1, 0): 3228 case IP_VERSION(6, 1, 1): 3229 adev->hdp.funcs = &hdp_v6_0_funcs; 3230 break; 3231 case IP_VERSION(7, 0, 0): 3232 adev->hdp.funcs = &hdp_v7_0_funcs; 3233 break; 3234 default: 3235 break; 3236 } 3237 3238 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) { 3239 case IP_VERSION(3, 6, 0): 3240 case IP_VERSION(3, 6, 1): 3241 case IP_VERSION(3, 6, 2): 3242 adev->df.funcs = &df_v3_6_funcs; 3243 break; 3244 case IP_VERSION(2, 1, 0): 3245 case IP_VERSION(2, 1, 1): 3246 case IP_VERSION(2, 5, 0): 3247 case IP_VERSION(3, 5, 1): 3248 case IP_VERSION(3, 5, 2): 3249 adev->df.funcs = &df_v1_7_funcs; 3250 break; 3251 case IP_VERSION(4, 3, 0): 3252 adev->df.funcs = &df_v4_3_funcs; 3253 break; 3254 case IP_VERSION(4, 6, 2): 3255 adev->df.funcs = &df_v4_6_2_funcs; 3256 break; 3257 case IP_VERSION(4, 15, 0): 3258 case IP_VERSION(4, 15, 1): 3259 adev->df.funcs = &df_v4_15_funcs; 3260 break; 3261 default: 3262 break; 3263 } 3264 3265 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) { 3266 case IP_VERSION(9, 0, 0): 3267 case IP_VERSION(9, 0, 1): 3268 case IP_VERSION(10, 0, 0): 3269 case IP_VERSION(10, 0, 1): 3270 case IP_VERSION(10, 0, 2): 3271 adev->smuio.funcs = &smuio_v9_0_funcs; 3272 break; 3273 case IP_VERSION(11, 0, 0): 3274 case IP_VERSION(11, 0, 2): 3275 case IP_VERSION(11, 0, 3): 3276 case IP_VERSION(11, 0, 4): 3277 case IP_VERSION(11, 0, 7): 3278 case IP_VERSION(11, 0, 8): 3279 adev->smuio.funcs = &smuio_v11_0_funcs; 3280 break; 3281 case IP_VERSION(11, 0, 6): 3282 case IP_VERSION(11, 0, 10): 3283 case IP_VERSION(11, 0, 11): 3284 case IP_VERSION(11, 5, 0): 3285 case IP_VERSION(11, 5, 2): 3286 case IP_VERSION(13, 0, 1): 3287 case IP_VERSION(13, 0, 9): 3288 case IP_VERSION(13, 0, 10): 3289 adev->smuio.funcs = &smuio_v11_0_6_funcs; 3290 break; 3291 case IP_VERSION(13, 0, 2): 3292 adev->smuio.funcs = &smuio_v13_0_funcs; 3293 break; 3294 case IP_VERSION(13, 0, 3): 3295 case IP_VERSION(13, 0, 11): 3296 adev->smuio.funcs = &smuio_v13_0_3_funcs; 3297 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) { 3298 adev->flags |= AMD_IS_APU; 3299 } 3300 break; 3301 case IP_VERSION(13, 0, 6): 3302 case IP_VERSION(13, 0, 8): 3303 case IP_VERSION(14, 0, 0): 3304 case IP_VERSION(14, 0, 1): 3305 adev->smuio.funcs = &smuio_v13_0_6_funcs; 3306 break; 3307 case IP_VERSION(14, 0, 2): 3308 adev->smuio.funcs = &smuio_v14_0_2_funcs; 3309 break; 3310 case IP_VERSION(15, 0, 0): 3311 adev->smuio.funcs = &smuio_v15_0_0_funcs; 3312 break; 3313 case IP_VERSION(15, 0, 8): 3314 adev->smuio.funcs = &smuio_v15_0_8_funcs; 3315 break; 3316 default: 3317 break; 3318 } 3319 3320 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 3321 case IP_VERSION(6, 0, 0): 3322 case IP_VERSION(6, 0, 1): 3323 case IP_VERSION(6, 0, 2): 3324 case IP_VERSION(6, 0, 3): 3325 adev->lsdma.funcs = &lsdma_v6_0_funcs; 3326 break; 3327 case IP_VERSION(7, 0, 0): 3328 case IP_VERSION(7, 0, 1): 3329 adev->lsdma.funcs = &lsdma_v7_0_funcs; 3330 break; 3331 case IP_VERSION(7, 1, 0): 3332 adev->lsdma.funcs = &lsdma_v7_1_funcs; 3333 break; 3334 default: 3335 break; 3336 } 3337 3338 r = amdgpu_discovery_set_common_ip_blocks(adev); 3339 if (r) 3340 return r; 3341 3342 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 3343 if (r) 3344 return r; 3345 3346 /* For SR-IOV, PSP needs to be initialized before IH */ 3347 if (amdgpu_sriov_vf(adev)) { 3348 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3349 if (r) 3350 return r; 3351 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3352 if (r) 3353 return r; 3354 } else { 3355 r = amdgpu_discovery_set_ih_ip_blocks(adev); 3356 if (r) 3357 return r; 3358 3359 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3360 r = amdgpu_discovery_set_psp_ip_blocks(adev); 3361 if (r) 3362 return r; 3363 } 3364 } 3365 3366 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 3367 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3368 if (r) 3369 return r; 3370 } 3371 3372 r = amdgpu_discovery_set_display_ip_blocks(adev); 3373 if (r) 3374 return r; 3375 3376 r = amdgpu_discovery_set_gc_ip_blocks(adev); 3377 if (r) 3378 return r; 3379 3380 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 3381 if (r) 3382 return r; 3383 3384 r = amdgpu_discovery_set_ras_ip_blocks(adev); 3385 if (r) 3386 return r; 3387 3388 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 3389 !amdgpu_sriov_vf(adev) && 3390 amdgpu_dpm == 1) || 3391 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && 3392 amdgpu_dpm == 1)) { 3393 r = amdgpu_discovery_set_smu_ip_blocks(adev); 3394 if (r) 3395 return r; 3396 } 3397 3398 r = amdgpu_discovery_set_mm_ip_blocks(adev); 3399 if (r) 3400 return r; 3401 3402 r = amdgpu_discovery_set_mes_ip_blocks(adev); 3403 if (r) 3404 return r; 3405 3406 r = amdgpu_discovery_set_vpe_ip_blocks(adev); 3407 if (r) 3408 return r; 3409 3410 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev); 3411 if (r) 3412 return r; 3413 3414 r = amdgpu_discovery_set_isp_ip_blocks(adev); 3415 if (r) 3416 return r; 3417 return 0; 3418 } 3419 3420