1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_fbdev_ttm.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_managed.h> 30 #include <drm/drm_pciids.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_vblank.h> 33 34 #include <linux/cc_platform.h> 35 #include <linux/dynamic_debug.h> 36 #include <linux/module.h> 37 #include <linux/mmu_notifier.h> 38 #include <linux/pm_runtime.h> 39 #include <linux/suspend.h> 40 #include <linux/vga_switcheroo.h> 41 42 #include "amdgpu.h" 43 #include "amdgpu_amdkfd.h" 44 #include "amdgpu_dma_buf.h" 45 #include "amdgpu_drv.h" 46 #include "amdgpu_fdinfo.h" 47 #include "amdgpu_irq.h" 48 #include "amdgpu_psp.h" 49 #include "amdgpu_ras.h" 50 #include "amdgpu_reset.h" 51 #include "amdgpu_sched.h" 52 #include "amdgpu_xgmi.h" 53 #include "../amdxcp/amdgpu_xcp_drv.h" 54 55 /* 56 * KMS wrapper. 57 * - 3.0.0 - initial driver 58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 60 * at the end of IBs. 61 * - 3.3.0 - Add VM support for UVD on supported hardware. 62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 63 * - 3.5.0 - Add support for new UVD_NO_OP register. 64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 65 * - 3.7.0 - Add support for VCE clock list packet 66 * - 3.8.0 - Add support raster config init in the kernel 67 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 70 * - 3.12.0 - Add query for double offchip LDS buffers 71 * - 3.13.0 - Add PRT support 72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 73 * - 3.15.0 - Export more gpu info for gfx9 74 * - 3.16.0 - Add reserved vmid support 75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 76 * - 3.18.0 - Export gpu always on cu bitmap 77 * - 3.19.0 - Add support for UVD MJPEG decode 78 * - 3.20.0 - Add support for local BOs 79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 81 * - 3.23.0 - Add query for VRAM lost counter 82 * - 3.24.0 - Add high priority compute support for gfx9 83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 94 * - 3.36.0 - Allow reading more status registers on si/cik 95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 99 * - 3.41.0 - Add video codec query 100 * - 3.42.0 - Add 16bpc fixed point display support 101 * - 3.43.0 - Add device hot plug/unplug support 102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 103 * - 3.45.0 - Add context ioctl stable pstate interface 104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 106 * - 3.48.0 - Add IP discovery version info to HW INFO 107 * - 3.49.0 - Add gang submit into CS IOCTL 108 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 109 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 110 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 111 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 112 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 113 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 114 * 3.53.0 - Support for GFX11 CP GFX shadowing 115 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 116 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query 117 * - 3.56.0 - Update IB start address and size alignment for decode and encode 118 * - 3.57.0 - Compute tunneling on GFX10+ 119 * - 3.58.0 - Add GFX12 DCC support 120 */ 121 #define KMS_DRIVER_MAJOR 3 122 #define KMS_DRIVER_MINOR 58 123 #define KMS_DRIVER_PATCHLEVEL 0 124 125 /* 126 * amdgpu.debug module options. Are all disabled by default 127 */ 128 enum AMDGPU_DEBUG_MASK { 129 AMDGPU_DEBUG_VM = BIT(0), 130 AMDGPU_DEBUG_LARGEBAR = BIT(1), 131 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), 132 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), 133 AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4), 134 AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5), 135 }; 136 137 unsigned int amdgpu_vram_limit = UINT_MAX; 138 int amdgpu_vis_vram_limit; 139 int amdgpu_gart_size = -1; /* auto */ 140 int amdgpu_gtt_size = -1; /* auto */ 141 int amdgpu_moverate = -1; /* auto */ 142 int amdgpu_audio = -1; 143 int amdgpu_disp_priority; 144 int amdgpu_hw_i2c; 145 int amdgpu_pcie_gen2 = -1; 146 int amdgpu_msi = -1; 147 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 148 int amdgpu_dpm = -1; 149 int amdgpu_fw_load_type = -1; 150 int amdgpu_aspm = -1; 151 int amdgpu_runtime_pm = -1; 152 uint amdgpu_ip_block_mask = 0xffffffff; 153 int amdgpu_bapm = -1; 154 int amdgpu_deep_color; 155 int amdgpu_vm_size = -1; 156 int amdgpu_vm_fragment_size = -1; 157 int amdgpu_vm_block_size = -1; 158 int amdgpu_vm_fault_stop; 159 int amdgpu_vm_update_mode = -1; 160 int amdgpu_exp_hw_support; 161 int amdgpu_dc = -1; 162 int amdgpu_sched_jobs = 32; 163 int amdgpu_sched_hw_submission = 2; 164 uint amdgpu_pcie_gen_cap; 165 uint amdgpu_pcie_lane_cap; 166 u64 amdgpu_cg_mask = 0xffffffffffffffff; 167 uint amdgpu_pg_mask = 0xffffffff; 168 uint amdgpu_sdma_phase_quantum = 32; 169 char *amdgpu_disable_cu; 170 char *amdgpu_virtual_display; 171 bool enforce_isolation; 172 173 /* Specifies the default granularity for SVM, used in buffer 174 * migration and restoration of backing memory when handling 175 * recoverable page faults. 176 * 177 * The value is given as log(numPages(buffer)); for a 2 MiB 178 * buffer it computes to be 9 179 */ 180 uint amdgpu_svm_default_granularity = 9; 181 182 /* 183 * OverDrive(bit 14) disabled by default 184 * GFX DCS(bit 19) disabled by default 185 */ 186 uint amdgpu_pp_feature_mask = 0xfff7bfff; 187 uint amdgpu_force_long_training; 188 int amdgpu_lbpw = -1; 189 int amdgpu_compute_multipipe = -1; 190 int amdgpu_gpu_recovery = -1; /* auto */ 191 int amdgpu_emu_mode; 192 uint amdgpu_smu_memory_pool_size; 193 int amdgpu_smu_pptable_id = -1; 194 /* 195 * FBC (bit 0) disabled by default 196 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 197 * - With this, for multiple monitors in sync(e.g. with the same model), 198 * mclk switching will be allowed. And the mclk will be not foced to the 199 * highest. That helps saving some idle power. 200 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 201 * PSR (bit 3) disabled by default 202 * EDP NO POWER SEQUENCING (bit 4) disabled by default 203 */ 204 uint amdgpu_dc_feature_mask = 2; 205 uint amdgpu_dc_debug_mask; 206 uint amdgpu_dc_visual_confirm; 207 int amdgpu_async_gfx_ring = 1; 208 int amdgpu_mcbp = -1; 209 int amdgpu_discovery = -1; 210 int amdgpu_mes; 211 int amdgpu_mes_log_enable = 0; 212 int amdgpu_mes_kiq; 213 int amdgpu_uni_mes = 1; 214 int amdgpu_noretry = -1; 215 int amdgpu_force_asic_type = -1; 216 int amdgpu_tmz = -1; /* auto */ 217 uint amdgpu_freesync_vid_mode; 218 int amdgpu_reset_method = -1; /* auto */ 219 int amdgpu_num_kcq = -1; 220 int amdgpu_smartshift_bias; 221 int amdgpu_use_xgmi_p2p = 1; 222 int amdgpu_vcnfw_log; 223 int amdgpu_sg_display = -1; /* auto */ 224 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 225 int amdgpu_umsch_mm; 226 int amdgpu_seamless = -1; /* auto */ 227 uint amdgpu_debug_mask; 228 int amdgpu_agp = -1; /* auto */ 229 int amdgpu_wbrf = -1; 230 int amdgpu_damage_clips = -1; /* auto */ 231 int amdgpu_umsch_mm_fwlog; 232 233 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 234 235 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 236 "DRM_UT_CORE", 237 "DRM_UT_DRIVER", 238 "DRM_UT_KMS", 239 "DRM_UT_PRIME", 240 "DRM_UT_ATOMIC", 241 "DRM_UT_VBL", 242 "DRM_UT_STATE", 243 "DRM_UT_LEASE", 244 "DRM_UT_DP", 245 "DRM_UT_DRMRES"); 246 247 struct amdgpu_mgpu_info mgpu_info = { 248 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 249 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 250 mgpu_info.delayed_reset_work, 251 amdgpu_drv_delayed_reset_work_handler, 0), 252 }; 253 int amdgpu_ras_enable = -1; 254 uint amdgpu_ras_mask = 0xffffffff; 255 int amdgpu_bad_page_threshold = -1; 256 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 257 .timeout_fatal_disable = false, 258 .period = 0x0, /* default to 0x0 (timeout disable) */ 259 }; 260 261 /** 262 * DOC: vramlimit (int) 263 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 264 */ 265 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 266 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 267 268 /** 269 * DOC: vis_vramlimit (int) 270 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 271 */ 272 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 273 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 274 275 /** 276 * DOC: gartsize (uint) 277 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 278 * The default is -1 (The size depends on asic). 279 */ 280 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 281 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 282 283 /** 284 * DOC: gttsize (int) 285 * Restrict the size of GTT domain (for userspace use) in MiB for testing. 286 * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 287 */ 288 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 289 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 290 291 /** 292 * DOC: moverate (int) 293 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 294 */ 295 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 296 module_param_named(moverate, amdgpu_moverate, int, 0600); 297 298 /** 299 * DOC: audio (int) 300 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 301 */ 302 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 303 module_param_named(audio, amdgpu_audio, int, 0444); 304 305 /** 306 * DOC: disp_priority (int) 307 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 308 */ 309 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 310 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 311 312 /** 313 * DOC: hw_i2c (int) 314 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 315 */ 316 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 317 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 318 319 /** 320 * DOC: pcie_gen2 (int) 321 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 322 */ 323 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 324 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 325 326 /** 327 * DOC: msi (int) 328 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 329 */ 330 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 331 module_param_named(msi, amdgpu_msi, int, 0444); 332 333 /** 334 * DOC: svm_default_granularity (uint) 335 * Used in buffer migration and handling of recoverable page faults 336 */ 337 MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB"); 338 module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644); 339 340 /** 341 * DOC: lockup_timeout (string) 342 * Set GPU scheduler timeout value in ms. 343 * 344 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 345 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 346 * to the default timeout. 347 * 348 * - With one value specified, the setting will apply to all non-compute jobs. 349 * - With multiple values specified, the first one will be for GFX. 350 * The second one is for Compute. The third and fourth ones are 351 * for SDMA and Video. 352 * 353 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 354 * jobs is 10000. The timeout for compute is 60000. 355 */ 356 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 357 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 358 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 359 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 360 361 /** 362 * DOC: dpm (int) 363 * Override for dynamic power management setting 364 * (0 = disable, 1 = enable) 365 * The default is -1 (auto). 366 */ 367 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 368 module_param_named(dpm, amdgpu_dpm, int, 0444); 369 370 /** 371 * DOC: fw_load_type (int) 372 * Set different firmware loading type for debugging, if supported. 373 * Set to 0 to force direct loading if supported by the ASIC. Set 374 * to -1 to select the default loading mode for the ASIC, as defined 375 * by the driver. The default is -1 (auto). 376 */ 377 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 378 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 379 380 /** 381 * DOC: aspm (int) 382 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 383 */ 384 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 385 module_param_named(aspm, amdgpu_aspm, int, 0444); 386 387 /** 388 * DOC: runpm (int) 389 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 390 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 391 * Setting the value to 0 disables this functionality. 392 * Setting the value to -2 is auto enabled with power down when displays are attached. 393 */ 394 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); 395 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 396 397 /** 398 * DOC: ip_block_mask (uint) 399 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 400 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 401 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 402 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 403 */ 404 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 405 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 406 407 /** 408 * DOC: bapm (int) 409 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 410 * The default -1 (auto, enabled) 411 */ 412 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 413 module_param_named(bapm, amdgpu_bapm, int, 0444); 414 415 /** 416 * DOC: deep_color (int) 417 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 418 */ 419 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 420 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 421 422 /** 423 * DOC: vm_size (int) 424 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 425 */ 426 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 427 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 428 429 /** 430 * DOC: vm_fragment_size (int) 431 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 432 */ 433 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 434 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 435 436 /** 437 * DOC: vm_block_size (int) 438 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 439 */ 440 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 441 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 442 443 /** 444 * DOC: vm_fault_stop (int) 445 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 446 */ 447 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 448 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 449 450 /** 451 * DOC: vm_update_mode (int) 452 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 453 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 454 */ 455 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 456 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 457 458 /** 459 * DOC: exp_hw_support (int) 460 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 461 */ 462 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 463 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 464 465 /** 466 * DOC: dc (int) 467 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 468 */ 469 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 470 module_param_named(dc, amdgpu_dc, int, 0444); 471 472 /** 473 * DOC: sched_jobs (int) 474 * Override the max number of jobs supported in the sw queue. The default is 32. 475 */ 476 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 477 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 478 479 /** 480 * DOC: sched_hw_submission (int) 481 * Override the max number of HW submissions. The default is 2. 482 */ 483 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 484 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 485 486 /** 487 * DOC: ppfeaturemask (hexint) 488 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 489 * The default is the current set of stable power features. 490 */ 491 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 492 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 493 494 /** 495 * DOC: forcelongtraining (uint) 496 * Force long memory training in resume. 497 * The default is zero, indicates short training in resume. 498 */ 499 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 500 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 501 502 /** 503 * DOC: pcie_gen_cap (uint) 504 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 505 * The default is 0 (automatic for each asic). 506 */ 507 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 508 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 509 510 /** 511 * DOC: pcie_lane_cap (uint) 512 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 513 * The default is 0 (automatic for each asic). 514 */ 515 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 516 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 517 518 /** 519 * DOC: cg_mask (ullong) 520 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 521 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 522 */ 523 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 524 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 525 526 /** 527 * DOC: pg_mask (uint) 528 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 529 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 530 */ 531 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 532 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 533 534 /** 535 * DOC: sdma_phase_quantum (uint) 536 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 537 */ 538 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 539 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 540 541 /** 542 * DOC: disable_cu (charp) 543 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 544 */ 545 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 546 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 547 548 /** 549 * DOC: virtual_display (charp) 550 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 551 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 552 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 553 * device at 26:00.0. The default is NULL. 554 */ 555 MODULE_PARM_DESC(virtual_display, 556 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 557 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 558 559 /** 560 * DOC: lbpw (int) 561 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 562 */ 563 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 564 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 565 566 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 567 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 568 569 /** 570 * DOC: gpu_recovery (int) 571 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 572 */ 573 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 574 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 575 576 /** 577 * DOC: emu_mode (int) 578 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 579 */ 580 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 581 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 582 583 /** 584 * DOC: ras_enable (int) 585 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 586 */ 587 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 588 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 589 590 /** 591 * DOC: ras_mask (uint) 592 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 593 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 594 */ 595 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 596 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 597 598 /** 599 * DOC: timeout_fatal_disable (bool) 600 * Disable Watchdog timeout fatal error event 601 */ 602 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 603 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 604 605 /** 606 * DOC: timeout_period (uint) 607 * Modify the watchdog timeout max_cycles as (1 << period) 608 */ 609 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 610 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 611 612 /** 613 * DOC: si_support (int) 614 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 615 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 616 * otherwise using amdgpu driver. 617 */ 618 #ifdef CONFIG_DRM_AMDGPU_SI 619 620 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 621 int amdgpu_si_support; 622 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 623 #else 624 int amdgpu_si_support = 1; 625 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 626 #endif 627 628 module_param_named(si_support, amdgpu_si_support, int, 0444); 629 #endif 630 631 /** 632 * DOC: cik_support (int) 633 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 634 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 635 * otherwise using amdgpu driver. 636 */ 637 #ifdef CONFIG_DRM_AMDGPU_CIK 638 639 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 640 int amdgpu_cik_support; 641 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 642 #else 643 int amdgpu_cik_support = 1; 644 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 645 #endif 646 647 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 648 #endif 649 650 /** 651 * DOC: smu_memory_pool_size (uint) 652 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 653 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 654 */ 655 MODULE_PARM_DESC(smu_memory_pool_size, 656 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 657 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 658 659 /** 660 * DOC: async_gfx_ring (int) 661 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 662 */ 663 MODULE_PARM_DESC(async_gfx_ring, 664 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 665 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 666 667 /** 668 * DOC: mcbp (int) 669 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 670 */ 671 MODULE_PARM_DESC(mcbp, 672 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 673 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 674 675 /** 676 * DOC: discovery (int) 677 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 678 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 679 */ 680 MODULE_PARM_DESC(discovery, 681 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 682 module_param_named(discovery, amdgpu_discovery, int, 0444); 683 684 /** 685 * DOC: mes (int) 686 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 687 * (0 = disabled (default), 1 = enabled) 688 */ 689 MODULE_PARM_DESC(mes, 690 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 691 module_param_named(mes, amdgpu_mes, int, 0444); 692 693 /** 694 * DOC: mes_log_enable (int) 695 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. 696 * (0 = disabled (default), 1 = enabled) 697 */ 698 MODULE_PARM_DESC(mes_log_enable, 699 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); 700 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); 701 702 /** 703 * DOC: mes_kiq (int) 704 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 705 * (0 = disabled (default), 1 = enabled) 706 */ 707 MODULE_PARM_DESC(mes_kiq, 708 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 709 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 710 711 /** 712 * DOC: uni_mes (int) 713 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. 714 * (0 = disabled (default), 1 = enabled) 715 */ 716 MODULE_PARM_DESC(uni_mes, 717 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)"); 718 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444); 719 720 /** 721 * DOC: noretry (int) 722 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 723 * do not support per-process XNACK this also disables retry page faults. 724 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 725 */ 726 MODULE_PARM_DESC(noretry, 727 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 728 module_param_named(noretry, amdgpu_noretry, int, 0644); 729 730 /** 731 * DOC: force_asic_type (int) 732 * A non negative value used to specify the asic type for all supported GPUs. 733 */ 734 MODULE_PARM_DESC(force_asic_type, 735 "A non negative value used to specify the asic type for all supported GPUs"); 736 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 737 738 /** 739 * DOC: use_xgmi_p2p (int) 740 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 741 */ 742 MODULE_PARM_DESC(use_xgmi_p2p, 743 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 744 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 745 746 747 #ifdef CONFIG_HSA_AMD 748 /** 749 * DOC: sched_policy (int) 750 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 751 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 752 * assigns queues to HQDs. 753 */ 754 int sched_policy = KFD_SCHED_POLICY_HWS; 755 module_param(sched_policy, int, 0444); 756 MODULE_PARM_DESC(sched_policy, 757 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 758 759 /** 760 * DOC: hws_max_conc_proc (int) 761 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 762 * number of VMIDs assigned to the HWS, which is also the default. 763 */ 764 int hws_max_conc_proc = -1; 765 module_param(hws_max_conc_proc, int, 0444); 766 MODULE_PARM_DESC(hws_max_conc_proc, 767 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 768 769 /** 770 * DOC: cwsr_enable (int) 771 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 772 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 773 * disables it. 774 */ 775 int cwsr_enable = 1; 776 module_param(cwsr_enable, int, 0444); 777 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 778 779 /** 780 * DOC: max_num_of_queues_per_device (int) 781 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 782 * is 4096. 783 */ 784 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 785 module_param(max_num_of_queues_per_device, int, 0444); 786 MODULE_PARM_DESC(max_num_of_queues_per_device, 787 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 788 789 /** 790 * DOC: send_sigterm (int) 791 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 792 * but just print errors on dmesg. Setting 1 enables sending sigterm. 793 */ 794 int send_sigterm; 795 module_param(send_sigterm, int, 0444); 796 MODULE_PARM_DESC(send_sigterm, 797 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 798 799 /** 800 * DOC: halt_if_hws_hang (int) 801 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 802 * Setting 1 enables halt on hang. 803 */ 804 int halt_if_hws_hang; 805 module_param(halt_if_hws_hang, int, 0644); 806 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 807 808 /** 809 * DOC: hws_gws_support(bool) 810 * Assume that HWS supports GWS barriers regardless of what firmware version 811 * check says. Default value: false (rely on MEC2 firmware version check). 812 */ 813 bool hws_gws_support; 814 module_param(hws_gws_support, bool, 0444); 815 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 816 817 /** 818 * DOC: queue_preemption_timeout_ms (int) 819 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 820 */ 821 int queue_preemption_timeout_ms = 9000; 822 module_param(queue_preemption_timeout_ms, int, 0644); 823 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 824 825 /** 826 * DOC: debug_evictions(bool) 827 * Enable extra debug messages to help determine the cause of evictions 828 */ 829 bool debug_evictions; 830 module_param(debug_evictions, bool, 0644); 831 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 832 833 /** 834 * DOC: no_system_mem_limit(bool) 835 * Disable system memory limit, to support multiple process shared memory 836 */ 837 bool no_system_mem_limit; 838 module_param(no_system_mem_limit, bool, 0644); 839 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 840 841 /** 842 * DOC: no_queue_eviction_on_vm_fault (int) 843 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 844 */ 845 int amdgpu_no_queue_eviction_on_vm_fault; 846 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 847 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 848 #endif 849 850 /** 851 * DOC: mtype_local (int) 852 */ 853 int amdgpu_mtype_local; 854 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 855 module_param_named(mtype_local, amdgpu_mtype_local, int, 0444); 856 857 /** 858 * DOC: pcie_p2p (bool) 859 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 860 */ 861 #ifdef CONFIG_HSA_AMD_P2P 862 bool pcie_p2p = true; 863 module_param(pcie_p2p, bool, 0444); 864 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 865 #endif 866 867 /** 868 * DOC: dcfeaturemask (uint) 869 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 870 * The default is the current set of stable display features. 871 */ 872 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 873 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 874 875 /** 876 * DOC: dcdebugmask (uint) 877 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 878 */ 879 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 880 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 881 882 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 883 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 884 885 /** 886 * DOC: abmlevel (uint) 887 * Override the default ABM (Adaptive Backlight Management) level used for DC 888 * enabled hardware. Requires DMCU to be supported and loaded. 889 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 890 * default. Values 1-4 control the maximum allowable brightness reduction via 891 * the ABM algorithm, with 1 being the least reduction and 4 being the most 892 * reduction. 893 * 894 * Defaults to -1, or disabled. Userspace can only override this level after 895 * boot if it's set to auto. 896 */ 897 int amdgpu_dm_abm_level = -1; 898 MODULE_PARM_DESC(abmlevel, 899 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))"); 900 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444); 901 902 int amdgpu_backlight = -1; 903 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 904 module_param_named(backlight, amdgpu_backlight, bint, 0444); 905 906 /** 907 * DOC: damageclips (int) 908 * Enable or disable damage clips support. If damage clips support is disabled, 909 * we will force full frame updates, irrespective of what user space sends to 910 * us. 911 * 912 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected). 913 */ 914 MODULE_PARM_DESC(damageclips, 915 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))"); 916 module_param_named(damageclips, amdgpu_damage_clips, int, 0444); 917 918 /** 919 * DOC: tmz (int) 920 * Trusted Memory Zone (TMZ) is a method to protect data being written 921 * to or read from memory. 922 * 923 * The default value: 0 (off). TODO: change to auto till it is completed. 924 */ 925 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 926 module_param_named(tmz, amdgpu_tmz, int, 0444); 927 928 /** 929 * DOC: freesync_video (uint) 930 * Enable the optimization to adjust front porch timing to achieve seamless 931 * mode change experience when setting a freesync supported mode for which full 932 * modeset is not needed. 933 * 934 * The Display Core will add a set of modes derived from the base FreeSync 935 * video mode into the corresponding connector's mode list based on commonly 936 * used refresh rates and VRR range of the connected display, when users enable 937 * this feature. From the userspace perspective, they can see a seamless mode 938 * change experience when the change between different refresh rates under the 939 * same resolution. Additionally, userspace applications such as Video playback 940 * can read this modeset list and change the refresh rate based on the video 941 * frame rate. Finally, the userspace can also derive an appropriate mode for a 942 * particular refresh rate based on the FreeSync Mode and add it to the 943 * connector's mode list. 944 * 945 * Note: This is an experimental feature. 946 * 947 * The default value: 0 (off). 948 */ 949 MODULE_PARM_DESC( 950 freesync_video, 951 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 952 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 953 954 /** 955 * DOC: reset_method (int) 956 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 957 */ 958 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 959 module_param_named(reset_method, amdgpu_reset_method, int, 0644); 960 961 /** 962 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 963 * threshold value of faulty pages detected by RAS ECC, which may 964 * result in the GPU entering bad status when the number of total 965 * faulty pages by ECC exceeds the threshold value. 966 */ 967 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)"); 968 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 969 970 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 971 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 972 973 /** 974 * DOC: vcnfw_log (int) 975 * Enable vcnfw log output for debugging, the default is disabled. 976 */ 977 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 978 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 979 980 /** 981 * DOC: sg_display (int) 982 * Disable S/G (scatter/gather) display (i.e., display from system memory). 983 * This option is only relevant on APUs. Set this option to 0 to disable 984 * S/G display if you experience flickering or other issues under memory 985 * pressure and report the issue. 986 */ 987 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 988 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 989 990 /** 991 * DOC: umsch_mm (int) 992 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE. 993 * (0 = disabled (default), 1 = enabled) 994 */ 995 MODULE_PARM_DESC(umsch_mm, 996 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)"); 997 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444); 998 999 /** 1000 * DOC: umsch_mm_fwlog (int) 1001 * Enable umschfw log output for debugging, the default is disabled. 1002 */ 1003 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)"); 1004 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444); 1005 1006 /** 1007 * DOC: smu_pptable_id (int) 1008 * Used to override pptable id. id = 0 use VBIOS pptable. 1009 * id > 0 use the soft pptable with specicfied id. 1010 */ 1011 MODULE_PARM_DESC(smu_pptable_id, 1012 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 1013 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 1014 1015 /** 1016 * DOC: partition_mode (int) 1017 * Used to override the default SPX mode. 1018 */ 1019 MODULE_PARM_DESC( 1020 user_partt_mode, 1021 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 1022 0 = AMDGPU_SPX_PARTITION_MODE, \ 1023 1 = AMDGPU_DPX_PARTITION_MODE, \ 1024 2 = AMDGPU_TPX_PARTITION_MODE, \ 1025 3 = AMDGPU_QPX_PARTITION_MODE, \ 1026 4 = AMDGPU_CPX_PARTITION_MODE)"); 1027 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 1028 1029 1030 /** 1031 * DOC: enforce_isolation (bool) 1032 * enforce process isolation between graphics and compute via using the same reserved vmid. 1033 */ 1034 module_param(enforce_isolation, bool, 0444); 1035 MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on"); 1036 1037 /** 1038 * DOC: seamless (int) 1039 * Seamless boot will keep the image on the screen during the boot process. 1040 */ 1041 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)"); 1042 module_param_named(seamless, amdgpu_seamless, int, 0444); 1043 1044 /** 1045 * DOC: debug_mask (uint) 1046 * Debug options for amdgpu, work as a binary mask with the following options: 1047 * 1048 * - 0x1: Debug VM handling 1049 * - 0x2: Enable simulating large-bar capability on non-large bar system. This 1050 * limits the VRAM size reported to ROCm applications to the visible 1051 * size, usually 256MB. 1052 * - 0x4: Disable GPU soft recovery, always do a full reset 1053 */ 1054 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default"); 1055 module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444); 1056 1057 /** 1058 * DOC: agp (int) 1059 * Enable the AGP aperture. This provides an aperture in the GPU's internal 1060 * address space for direct access to system memory. Note that these accesses 1061 * are non-snooped, so they are only used for access to uncached memory. 1062 */ 1063 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)"); 1064 module_param_named(agp, amdgpu_agp, int, 0444); 1065 1066 /** 1067 * DOC: wbrf (int) 1068 * Enable Wifi RFI interference mitigation feature. 1069 * Due to electrical and mechanical constraints there may be likely interference of 1070 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio 1071 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference, 1072 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based 1073 * on active list of frequencies in-use (to be avoided) as part of initial setting or 1074 * P-state transition. However, there may be potential performance impact with this 1075 * feature enabled. 1076 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported)) 1077 */ 1078 MODULE_PARM_DESC(wbrf, 1079 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)"); 1080 module_param_named(wbrf, amdgpu_wbrf, int, 0444); 1081 1082 /* These devices are not supported by amdgpu. 1083 * They are supported by the mach64, r128, radeon drivers 1084 */ 1085 static const u16 amdgpu_unsupported_pciidlist[] = { 1086 /* mach64 */ 1087 0x4354, 1088 0x4358, 1089 0x4554, 1090 0x4742, 1091 0x4744, 1092 0x4749, 1093 0x474C, 1094 0x474D, 1095 0x474E, 1096 0x474F, 1097 0x4750, 1098 0x4751, 1099 0x4752, 1100 0x4753, 1101 0x4754, 1102 0x4755, 1103 0x4756, 1104 0x4757, 1105 0x4758, 1106 0x4759, 1107 0x475A, 1108 0x4C42, 1109 0x4C44, 1110 0x4C47, 1111 0x4C49, 1112 0x4C4D, 1113 0x4C4E, 1114 0x4C50, 1115 0x4C51, 1116 0x4C52, 1117 0x4C53, 1118 0x5654, 1119 0x5655, 1120 0x5656, 1121 /* r128 */ 1122 0x4c45, 1123 0x4c46, 1124 0x4d46, 1125 0x4d4c, 1126 0x5041, 1127 0x5042, 1128 0x5043, 1129 0x5044, 1130 0x5045, 1131 0x5046, 1132 0x5047, 1133 0x5048, 1134 0x5049, 1135 0x504A, 1136 0x504B, 1137 0x504C, 1138 0x504D, 1139 0x504E, 1140 0x504F, 1141 0x5050, 1142 0x5051, 1143 0x5052, 1144 0x5053, 1145 0x5054, 1146 0x5055, 1147 0x5056, 1148 0x5057, 1149 0x5058, 1150 0x5245, 1151 0x5246, 1152 0x5247, 1153 0x524b, 1154 0x524c, 1155 0x534d, 1156 0x5446, 1157 0x544C, 1158 0x5452, 1159 /* radeon */ 1160 0x3150, 1161 0x3151, 1162 0x3152, 1163 0x3154, 1164 0x3155, 1165 0x3E50, 1166 0x3E54, 1167 0x4136, 1168 0x4137, 1169 0x4144, 1170 0x4145, 1171 0x4146, 1172 0x4147, 1173 0x4148, 1174 0x4149, 1175 0x414A, 1176 0x414B, 1177 0x4150, 1178 0x4151, 1179 0x4152, 1180 0x4153, 1181 0x4154, 1182 0x4155, 1183 0x4156, 1184 0x4237, 1185 0x4242, 1186 0x4336, 1187 0x4337, 1188 0x4437, 1189 0x4966, 1190 0x4967, 1191 0x4A48, 1192 0x4A49, 1193 0x4A4A, 1194 0x4A4B, 1195 0x4A4C, 1196 0x4A4D, 1197 0x4A4E, 1198 0x4A4F, 1199 0x4A50, 1200 0x4A54, 1201 0x4B48, 1202 0x4B49, 1203 0x4B4A, 1204 0x4B4B, 1205 0x4B4C, 1206 0x4C57, 1207 0x4C58, 1208 0x4C59, 1209 0x4C5A, 1210 0x4C64, 1211 0x4C66, 1212 0x4C67, 1213 0x4E44, 1214 0x4E45, 1215 0x4E46, 1216 0x4E47, 1217 0x4E48, 1218 0x4E49, 1219 0x4E4A, 1220 0x4E4B, 1221 0x4E50, 1222 0x4E51, 1223 0x4E52, 1224 0x4E53, 1225 0x4E54, 1226 0x4E56, 1227 0x5144, 1228 0x5145, 1229 0x5146, 1230 0x5147, 1231 0x5148, 1232 0x514C, 1233 0x514D, 1234 0x5157, 1235 0x5158, 1236 0x5159, 1237 0x515A, 1238 0x515E, 1239 0x5460, 1240 0x5462, 1241 0x5464, 1242 0x5548, 1243 0x5549, 1244 0x554A, 1245 0x554B, 1246 0x554C, 1247 0x554D, 1248 0x554E, 1249 0x554F, 1250 0x5550, 1251 0x5551, 1252 0x5552, 1253 0x5554, 1254 0x564A, 1255 0x564B, 1256 0x564F, 1257 0x5652, 1258 0x5653, 1259 0x5657, 1260 0x5834, 1261 0x5835, 1262 0x5954, 1263 0x5955, 1264 0x5974, 1265 0x5975, 1266 0x5960, 1267 0x5961, 1268 0x5962, 1269 0x5964, 1270 0x5965, 1271 0x5969, 1272 0x5a41, 1273 0x5a42, 1274 0x5a61, 1275 0x5a62, 1276 0x5b60, 1277 0x5b62, 1278 0x5b63, 1279 0x5b64, 1280 0x5b65, 1281 0x5c61, 1282 0x5c63, 1283 0x5d48, 1284 0x5d49, 1285 0x5d4a, 1286 0x5d4c, 1287 0x5d4d, 1288 0x5d4e, 1289 0x5d4f, 1290 0x5d50, 1291 0x5d52, 1292 0x5d57, 1293 0x5e48, 1294 0x5e4a, 1295 0x5e4b, 1296 0x5e4c, 1297 0x5e4d, 1298 0x5e4f, 1299 0x6700, 1300 0x6701, 1301 0x6702, 1302 0x6703, 1303 0x6704, 1304 0x6705, 1305 0x6706, 1306 0x6707, 1307 0x6708, 1308 0x6709, 1309 0x6718, 1310 0x6719, 1311 0x671c, 1312 0x671d, 1313 0x671f, 1314 0x6720, 1315 0x6721, 1316 0x6722, 1317 0x6723, 1318 0x6724, 1319 0x6725, 1320 0x6726, 1321 0x6727, 1322 0x6728, 1323 0x6729, 1324 0x6738, 1325 0x6739, 1326 0x673e, 1327 0x6740, 1328 0x6741, 1329 0x6742, 1330 0x6743, 1331 0x6744, 1332 0x6745, 1333 0x6746, 1334 0x6747, 1335 0x6748, 1336 0x6749, 1337 0x674A, 1338 0x6750, 1339 0x6751, 1340 0x6758, 1341 0x6759, 1342 0x675B, 1343 0x675D, 1344 0x675F, 1345 0x6760, 1346 0x6761, 1347 0x6762, 1348 0x6763, 1349 0x6764, 1350 0x6765, 1351 0x6766, 1352 0x6767, 1353 0x6768, 1354 0x6770, 1355 0x6771, 1356 0x6772, 1357 0x6778, 1358 0x6779, 1359 0x677B, 1360 0x6840, 1361 0x6841, 1362 0x6842, 1363 0x6843, 1364 0x6849, 1365 0x684C, 1366 0x6850, 1367 0x6858, 1368 0x6859, 1369 0x6880, 1370 0x6888, 1371 0x6889, 1372 0x688A, 1373 0x688C, 1374 0x688D, 1375 0x6898, 1376 0x6899, 1377 0x689b, 1378 0x689c, 1379 0x689d, 1380 0x689e, 1381 0x68a0, 1382 0x68a1, 1383 0x68a8, 1384 0x68a9, 1385 0x68b0, 1386 0x68b8, 1387 0x68b9, 1388 0x68ba, 1389 0x68be, 1390 0x68bf, 1391 0x68c0, 1392 0x68c1, 1393 0x68c7, 1394 0x68c8, 1395 0x68c9, 1396 0x68d8, 1397 0x68d9, 1398 0x68da, 1399 0x68de, 1400 0x68e0, 1401 0x68e1, 1402 0x68e4, 1403 0x68e5, 1404 0x68e8, 1405 0x68e9, 1406 0x68f1, 1407 0x68f2, 1408 0x68f8, 1409 0x68f9, 1410 0x68fa, 1411 0x68fe, 1412 0x7100, 1413 0x7101, 1414 0x7102, 1415 0x7103, 1416 0x7104, 1417 0x7105, 1418 0x7106, 1419 0x7108, 1420 0x7109, 1421 0x710A, 1422 0x710B, 1423 0x710C, 1424 0x710E, 1425 0x710F, 1426 0x7140, 1427 0x7141, 1428 0x7142, 1429 0x7143, 1430 0x7144, 1431 0x7145, 1432 0x7146, 1433 0x7147, 1434 0x7149, 1435 0x714A, 1436 0x714B, 1437 0x714C, 1438 0x714D, 1439 0x714E, 1440 0x714F, 1441 0x7151, 1442 0x7152, 1443 0x7153, 1444 0x715E, 1445 0x715F, 1446 0x7180, 1447 0x7181, 1448 0x7183, 1449 0x7186, 1450 0x7187, 1451 0x7188, 1452 0x718A, 1453 0x718B, 1454 0x718C, 1455 0x718D, 1456 0x718F, 1457 0x7193, 1458 0x7196, 1459 0x719B, 1460 0x719F, 1461 0x71C0, 1462 0x71C1, 1463 0x71C2, 1464 0x71C3, 1465 0x71C4, 1466 0x71C5, 1467 0x71C6, 1468 0x71C7, 1469 0x71CD, 1470 0x71CE, 1471 0x71D2, 1472 0x71D4, 1473 0x71D5, 1474 0x71D6, 1475 0x71DA, 1476 0x71DE, 1477 0x7200, 1478 0x7210, 1479 0x7211, 1480 0x7240, 1481 0x7243, 1482 0x7244, 1483 0x7245, 1484 0x7246, 1485 0x7247, 1486 0x7248, 1487 0x7249, 1488 0x724A, 1489 0x724B, 1490 0x724C, 1491 0x724D, 1492 0x724E, 1493 0x724F, 1494 0x7280, 1495 0x7281, 1496 0x7283, 1497 0x7284, 1498 0x7287, 1499 0x7288, 1500 0x7289, 1501 0x728B, 1502 0x728C, 1503 0x7290, 1504 0x7291, 1505 0x7293, 1506 0x7297, 1507 0x7834, 1508 0x7835, 1509 0x791e, 1510 0x791f, 1511 0x793f, 1512 0x7941, 1513 0x7942, 1514 0x796c, 1515 0x796d, 1516 0x796e, 1517 0x796f, 1518 0x9400, 1519 0x9401, 1520 0x9402, 1521 0x9403, 1522 0x9405, 1523 0x940A, 1524 0x940B, 1525 0x940F, 1526 0x94A0, 1527 0x94A1, 1528 0x94A3, 1529 0x94B1, 1530 0x94B3, 1531 0x94B4, 1532 0x94B5, 1533 0x94B9, 1534 0x9440, 1535 0x9441, 1536 0x9442, 1537 0x9443, 1538 0x9444, 1539 0x9446, 1540 0x944A, 1541 0x944B, 1542 0x944C, 1543 0x944E, 1544 0x9450, 1545 0x9452, 1546 0x9456, 1547 0x945A, 1548 0x945B, 1549 0x945E, 1550 0x9460, 1551 0x9462, 1552 0x946A, 1553 0x946B, 1554 0x947A, 1555 0x947B, 1556 0x9480, 1557 0x9487, 1558 0x9488, 1559 0x9489, 1560 0x948A, 1561 0x948F, 1562 0x9490, 1563 0x9491, 1564 0x9495, 1565 0x9498, 1566 0x949C, 1567 0x949E, 1568 0x949F, 1569 0x94C0, 1570 0x94C1, 1571 0x94C3, 1572 0x94C4, 1573 0x94C5, 1574 0x94C6, 1575 0x94C7, 1576 0x94C8, 1577 0x94C9, 1578 0x94CB, 1579 0x94CC, 1580 0x94CD, 1581 0x9500, 1582 0x9501, 1583 0x9504, 1584 0x9505, 1585 0x9506, 1586 0x9507, 1587 0x9508, 1588 0x9509, 1589 0x950F, 1590 0x9511, 1591 0x9515, 1592 0x9517, 1593 0x9519, 1594 0x9540, 1595 0x9541, 1596 0x9542, 1597 0x954E, 1598 0x954F, 1599 0x9552, 1600 0x9553, 1601 0x9555, 1602 0x9557, 1603 0x955f, 1604 0x9580, 1605 0x9581, 1606 0x9583, 1607 0x9586, 1608 0x9587, 1609 0x9588, 1610 0x9589, 1611 0x958A, 1612 0x958B, 1613 0x958C, 1614 0x958D, 1615 0x958E, 1616 0x958F, 1617 0x9590, 1618 0x9591, 1619 0x9593, 1620 0x9595, 1621 0x9596, 1622 0x9597, 1623 0x9598, 1624 0x9599, 1625 0x959B, 1626 0x95C0, 1627 0x95C2, 1628 0x95C4, 1629 0x95C5, 1630 0x95C6, 1631 0x95C7, 1632 0x95C9, 1633 0x95CC, 1634 0x95CD, 1635 0x95CE, 1636 0x95CF, 1637 0x9610, 1638 0x9611, 1639 0x9612, 1640 0x9613, 1641 0x9614, 1642 0x9615, 1643 0x9616, 1644 0x9640, 1645 0x9641, 1646 0x9642, 1647 0x9643, 1648 0x9644, 1649 0x9645, 1650 0x9647, 1651 0x9648, 1652 0x9649, 1653 0x964a, 1654 0x964b, 1655 0x964c, 1656 0x964e, 1657 0x964f, 1658 0x9710, 1659 0x9711, 1660 0x9712, 1661 0x9713, 1662 0x9714, 1663 0x9715, 1664 0x9802, 1665 0x9803, 1666 0x9804, 1667 0x9805, 1668 0x9806, 1669 0x9807, 1670 0x9808, 1671 0x9809, 1672 0x980A, 1673 0x9900, 1674 0x9901, 1675 0x9903, 1676 0x9904, 1677 0x9905, 1678 0x9906, 1679 0x9907, 1680 0x9908, 1681 0x9909, 1682 0x990A, 1683 0x990B, 1684 0x990C, 1685 0x990D, 1686 0x990E, 1687 0x990F, 1688 0x9910, 1689 0x9913, 1690 0x9917, 1691 0x9918, 1692 0x9919, 1693 0x9990, 1694 0x9991, 1695 0x9992, 1696 0x9993, 1697 0x9994, 1698 0x9995, 1699 0x9996, 1700 0x9997, 1701 0x9998, 1702 0x9999, 1703 0x999A, 1704 0x999B, 1705 0x999C, 1706 0x999D, 1707 0x99A0, 1708 0x99A2, 1709 0x99A4, 1710 /* radeon secondary ids */ 1711 0x3171, 1712 0x3e70, 1713 0x4164, 1714 0x4165, 1715 0x4166, 1716 0x4168, 1717 0x4170, 1718 0x4171, 1719 0x4172, 1720 0x4173, 1721 0x496e, 1722 0x4a69, 1723 0x4a6a, 1724 0x4a6b, 1725 0x4a70, 1726 0x4a74, 1727 0x4b69, 1728 0x4b6b, 1729 0x4b6c, 1730 0x4c6e, 1731 0x4e64, 1732 0x4e65, 1733 0x4e66, 1734 0x4e67, 1735 0x4e68, 1736 0x4e69, 1737 0x4e6a, 1738 0x4e71, 1739 0x4f73, 1740 0x5569, 1741 0x556b, 1742 0x556d, 1743 0x556f, 1744 0x5571, 1745 0x5854, 1746 0x5874, 1747 0x5940, 1748 0x5941, 1749 0x5b70, 1750 0x5b72, 1751 0x5b73, 1752 0x5b74, 1753 0x5b75, 1754 0x5d44, 1755 0x5d45, 1756 0x5d6d, 1757 0x5d6f, 1758 0x5d72, 1759 0x5d77, 1760 0x5e6b, 1761 0x5e6d, 1762 0x7120, 1763 0x7124, 1764 0x7129, 1765 0x712e, 1766 0x712f, 1767 0x7162, 1768 0x7163, 1769 0x7166, 1770 0x7167, 1771 0x7172, 1772 0x7173, 1773 0x71a0, 1774 0x71a1, 1775 0x71a3, 1776 0x71a7, 1777 0x71bb, 1778 0x71e0, 1779 0x71e1, 1780 0x71e2, 1781 0x71e6, 1782 0x71e7, 1783 0x71f2, 1784 0x7269, 1785 0x726b, 1786 0x726e, 1787 0x72a0, 1788 0x72a8, 1789 0x72b1, 1790 0x72b3, 1791 0x793f, 1792 }; 1793 1794 static const struct pci_device_id pciidlist[] = { 1795 #ifdef CONFIG_DRM_AMDGPU_SI 1796 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1797 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1798 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1799 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1800 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1801 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1802 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1803 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1804 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1805 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1806 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1807 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1808 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1809 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1810 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1811 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1812 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1813 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1814 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1815 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1816 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1817 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1818 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1819 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1820 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1821 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1822 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1823 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1824 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1825 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1826 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1827 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1828 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1829 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1830 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1831 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1832 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1833 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1834 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1835 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1836 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1837 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1838 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1839 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1840 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1841 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1842 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1843 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1844 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1845 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1846 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1847 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1848 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1849 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1850 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1851 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1852 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1853 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1854 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1855 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1856 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1857 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1858 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1859 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1860 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1861 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1862 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1863 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1864 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1865 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1866 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1867 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1868 #endif 1869 #ifdef CONFIG_DRM_AMDGPU_CIK 1870 /* Kaveri */ 1871 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1872 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1873 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1874 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1875 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1876 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1877 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1878 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1879 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1880 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1881 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1882 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1883 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1884 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1885 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1886 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1887 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1888 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1889 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1890 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1891 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1892 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1893 /* Bonaire */ 1894 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1895 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1896 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1897 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1898 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1899 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1900 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1901 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1902 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1903 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1904 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1905 /* Hawaii */ 1906 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1907 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1908 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1909 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1910 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1911 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1912 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1913 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1914 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1915 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1916 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1917 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1918 /* Kabini */ 1919 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1920 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1921 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1922 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1923 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1924 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1925 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1926 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1927 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1928 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1929 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1930 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1931 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1932 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1933 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1934 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1935 /* mullins */ 1936 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1937 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1938 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1939 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1940 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1941 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1942 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1943 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1944 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1945 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1946 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1947 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1948 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1949 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1950 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1951 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1952 #endif 1953 /* topaz */ 1954 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1955 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1956 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1957 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1958 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1959 /* tonga */ 1960 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1961 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1962 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1963 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1964 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1965 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1966 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1967 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1968 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1969 /* fiji */ 1970 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1971 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1972 /* carrizo */ 1973 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1974 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1975 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1976 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1977 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1978 /* stoney */ 1979 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1980 /* Polaris11 */ 1981 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1982 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1983 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1984 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1985 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1986 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1987 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1988 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1989 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1990 /* Polaris10 */ 1991 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1992 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1993 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1994 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1995 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1996 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1997 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1998 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1999 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2000 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2001 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2002 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2003 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 2004 /* Polaris12 */ 2005 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2006 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2007 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2008 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2009 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2010 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2011 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2012 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 2013 /* VEGAM */ 2014 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2015 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2016 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 2017 /* Vega 10 */ 2018 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2019 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2020 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2021 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2022 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2023 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2024 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2025 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2026 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2027 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2028 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2029 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2030 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2031 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2032 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 2033 /* Vega 12 */ 2034 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2035 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2036 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2037 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2038 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 2039 /* Vega 20 */ 2040 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2041 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2042 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2043 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2044 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2045 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2046 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 2047 /* Raven */ 2048 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2049 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 2050 /* Arcturus */ 2051 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2052 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2053 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2054 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 2055 /* Navi10 */ 2056 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2057 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2058 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2059 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2060 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2061 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2062 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2063 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 2064 /* Navi14 */ 2065 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2066 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2067 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2068 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 2069 2070 /* Renoir */ 2071 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2072 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2073 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2074 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 2075 2076 /* Navi12 */ 2077 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2078 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 2079 2080 /* Sienna_Cichlid */ 2081 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2082 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2083 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2084 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2085 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2086 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2087 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2088 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2089 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2090 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2091 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2092 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2093 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 2094 2095 /* Yellow Carp */ 2096 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2097 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 2098 2099 /* Navy_Flounder */ 2100 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2101 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2102 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2103 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2104 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2105 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2106 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2107 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2108 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 2109 2110 /* DIMGREY_CAVEFISH */ 2111 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2112 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2113 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2114 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2115 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2116 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2117 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2118 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2119 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2120 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2121 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2122 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 2123 2124 /* Aldebaran */ 2125 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2126 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2127 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2128 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2129 2130 /* CYAN_SKILLFISH */ 2131 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2132 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2133 2134 /* BEIGE_GOBY */ 2135 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2136 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2137 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2138 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2139 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2140 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2141 2142 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2143 .class = PCI_CLASS_DISPLAY_VGA << 8, 2144 .class_mask = 0xffffff, 2145 .driver_data = CHIP_IP_DISCOVERY }, 2146 2147 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2148 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2149 .class_mask = 0xffffff, 2150 .driver_data = CHIP_IP_DISCOVERY }, 2151 2152 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2153 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2154 .class_mask = 0xffffff, 2155 .driver_data = CHIP_IP_DISCOVERY }, 2156 2157 {0, 0, 0} 2158 }; 2159 2160 MODULE_DEVICE_TABLE(pci, pciidlist); 2161 2162 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { 2163 /* differentiate between P10 and P11 asics with the same DID */ 2164 {0x67FF, 0xE3, CHIP_POLARIS10}, 2165 {0x67FF, 0xE7, CHIP_POLARIS10}, 2166 {0x67FF, 0xF3, CHIP_POLARIS10}, 2167 {0x67FF, 0xF7, CHIP_POLARIS10}, 2168 }; 2169 2170 static const struct drm_driver amdgpu_kms_driver; 2171 2172 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2173 { 2174 struct pci_dev *p = NULL; 2175 int i; 2176 2177 /* 0 - GPU 2178 * 1 - audio 2179 * 2 - USB 2180 * 3 - UCSI 2181 */ 2182 for (i = 1; i < 4; i++) { 2183 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2184 adev->pdev->bus->number, i); 2185 if (p) { 2186 pm_runtime_get_sync(&p->dev); 2187 pm_runtime_mark_last_busy(&p->dev); 2188 pm_runtime_put_autosuspend(&p->dev); 2189 pci_dev_put(p); 2190 } 2191 } 2192 } 2193 2194 static void amdgpu_init_debug_options(struct amdgpu_device *adev) 2195 { 2196 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) { 2197 pr_info("debug: VM handling debug enabled\n"); 2198 adev->debug_vm = true; 2199 } 2200 2201 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) { 2202 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); 2203 adev->debug_largebar = true; 2204 } 2205 2206 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) { 2207 pr_info("debug: soft reset for GPU recovery disabled\n"); 2208 adev->debug_disable_soft_recovery = true; 2209 } 2210 2211 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) { 2212 pr_info("debug: place fw in vram for frontdoor loading\n"); 2213 adev->debug_use_vram_fw_buf = true; 2214 } 2215 2216 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) { 2217 pr_info("debug: enable RAS ACA\n"); 2218 adev->debug_enable_ras_aca = true; 2219 } 2220 2221 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) { 2222 pr_info("debug: enable experimental reset features\n"); 2223 adev->debug_exp_resets = true; 2224 } 2225 } 2226 2227 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) 2228 { 2229 int i; 2230 2231 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) { 2232 if (pdev->device == asic_type_quirks[i].device && 2233 pdev->revision == asic_type_quirks[i].revision) { 2234 flags &= ~AMD_ASIC_MASK; 2235 flags |= asic_type_quirks[i].type; 2236 break; 2237 } 2238 } 2239 2240 return flags; 2241 } 2242 2243 static int amdgpu_pci_probe(struct pci_dev *pdev, 2244 const struct pci_device_id *ent) 2245 { 2246 struct drm_device *ddev; 2247 struct amdgpu_device *adev; 2248 unsigned long flags = ent->driver_data; 2249 int ret, retry = 0, i; 2250 bool supports_atomic = false; 2251 2252 /* skip devices which are owned by radeon */ 2253 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2254 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2255 return -ENODEV; 2256 } 2257 2258 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2259 amdgpu_aspm = 0; 2260 2261 if (amdgpu_virtual_display || 2262 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2263 supports_atomic = true; 2264 2265 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2266 DRM_INFO("This hardware requires experimental hardware support.\n" 2267 "See modparam exp_hw_support\n"); 2268 return -ENODEV; 2269 } 2270 2271 flags = amdgpu_fix_asic_type(pdev, flags); 2272 2273 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2274 * however, SME requires an indirect IOMMU mapping because the encryption 2275 * bit is beyond the DMA mask of the chip. 2276 */ 2277 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2278 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2279 dev_info(&pdev->dev, 2280 "SME is not compatible with RAVEN\n"); 2281 return -ENOTSUPP; 2282 } 2283 2284 #ifdef CONFIG_DRM_AMDGPU_SI 2285 if (!amdgpu_si_support) { 2286 switch (flags & AMD_ASIC_MASK) { 2287 case CHIP_TAHITI: 2288 case CHIP_PITCAIRN: 2289 case CHIP_VERDE: 2290 case CHIP_OLAND: 2291 case CHIP_HAINAN: 2292 dev_info(&pdev->dev, 2293 "SI support provided by radeon.\n"); 2294 dev_info(&pdev->dev, 2295 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2296 ); 2297 return -ENODEV; 2298 } 2299 } 2300 #endif 2301 #ifdef CONFIG_DRM_AMDGPU_CIK 2302 if (!amdgpu_cik_support) { 2303 switch (flags & AMD_ASIC_MASK) { 2304 case CHIP_KAVERI: 2305 case CHIP_BONAIRE: 2306 case CHIP_HAWAII: 2307 case CHIP_KABINI: 2308 case CHIP_MULLINS: 2309 dev_info(&pdev->dev, 2310 "CIK support provided by radeon.\n"); 2311 dev_info(&pdev->dev, 2312 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2313 ); 2314 return -ENODEV; 2315 } 2316 } 2317 #endif 2318 2319 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2320 if (IS_ERR(adev)) 2321 return PTR_ERR(adev); 2322 2323 adev->dev = &pdev->dev; 2324 adev->pdev = pdev; 2325 ddev = adev_to_drm(adev); 2326 2327 if (!supports_atomic) 2328 ddev->driver_features &= ~DRIVER_ATOMIC; 2329 2330 ret = pci_enable_device(pdev); 2331 if (ret) 2332 return ret; 2333 2334 pci_set_drvdata(pdev, ddev); 2335 2336 amdgpu_init_debug_options(adev); 2337 2338 ret = amdgpu_driver_load_kms(adev, flags); 2339 if (ret) 2340 goto err_pci; 2341 2342 retry_init: 2343 ret = drm_dev_register(ddev, flags); 2344 if (ret == -EAGAIN && ++retry <= 3) { 2345 DRM_INFO("retry init %d\n", retry); 2346 /* Don't request EX mode too frequently which is attacking */ 2347 msleep(5000); 2348 goto retry_init; 2349 } else if (ret) { 2350 goto err_pci; 2351 } 2352 2353 ret = amdgpu_xcp_dev_register(adev, ent); 2354 if (ret) 2355 goto err_pci; 2356 2357 ret = amdgpu_amdkfd_drm_client_create(adev); 2358 if (ret) 2359 goto err_pci; 2360 2361 /* 2362 * 1. don't init fbdev on hw without DCE 2363 * 2. don't init fbdev if there are no connectors 2364 */ 2365 if (adev->mode_info.mode_config_initialized && 2366 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2367 /* select 8 bpp console on low vram cards */ 2368 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2369 drm_fbdev_ttm_setup(adev_to_drm(adev), 8); 2370 else 2371 drm_fbdev_ttm_setup(adev_to_drm(adev), 32); 2372 } 2373 2374 ret = amdgpu_debugfs_init(adev); 2375 if (ret) 2376 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2377 2378 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2379 /* only need to skip on ATPX */ 2380 if (amdgpu_device_supports_px(ddev)) 2381 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2382 /* we want direct complete for BOCO */ 2383 if (amdgpu_device_supports_boco(ddev)) 2384 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2385 DPM_FLAG_SMART_SUSPEND | 2386 DPM_FLAG_MAY_SKIP_RESUME); 2387 pm_runtime_use_autosuspend(ddev->dev); 2388 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2389 2390 pm_runtime_allow(ddev->dev); 2391 2392 pm_runtime_mark_last_busy(ddev->dev); 2393 pm_runtime_put_autosuspend(ddev->dev); 2394 2395 pci_wake_from_d3(pdev, TRUE); 2396 2397 /* 2398 * For runpm implemented via BACO, PMFW will handle the 2399 * timing for BACO in and out: 2400 * - put ASIC into BACO state only when both video and 2401 * audio functions are in D3 state. 2402 * - pull ASIC out of BACO state when either video or 2403 * audio function is in D0 state. 2404 * Also, at startup, PMFW assumes both functions are in 2405 * D0 state. 2406 * 2407 * So if snd driver was loaded prior to amdgpu driver 2408 * and audio function was put into D3 state, there will 2409 * be no PMFW-aware D-state transition(D0->D3) on runpm 2410 * suspend. Thus the BACO will be not correctly kicked in. 2411 * 2412 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2413 * into D0 state. Then there will be a PMFW-aware D-state 2414 * transition(D0->D3) on runpm suspend. 2415 */ 2416 if (amdgpu_device_supports_baco(ddev) && 2417 !(adev->flags & AMD_IS_APU) && 2418 (adev->asic_type >= CHIP_NAVI10)) 2419 amdgpu_get_secondary_funcs(adev); 2420 } 2421 2422 return 0; 2423 2424 err_pci: 2425 pci_disable_device(pdev); 2426 return ret; 2427 } 2428 2429 static void 2430 amdgpu_pci_remove(struct pci_dev *pdev) 2431 { 2432 struct drm_device *dev = pci_get_drvdata(pdev); 2433 struct amdgpu_device *adev = drm_to_adev(dev); 2434 2435 amdgpu_xcp_dev_unplug(adev); 2436 drm_dev_unplug(dev); 2437 2438 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2439 pm_runtime_get_sync(dev->dev); 2440 pm_runtime_forbid(dev->dev); 2441 } 2442 2443 amdgpu_driver_unload_kms(dev); 2444 2445 /* 2446 * Flush any in flight DMA operations from device. 2447 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2448 * StatusTransactions Pending bit. 2449 */ 2450 pci_disable_device(pdev); 2451 pci_wait_for_pending_transaction(pdev); 2452 } 2453 2454 static void 2455 amdgpu_pci_shutdown(struct pci_dev *pdev) 2456 { 2457 struct drm_device *dev = pci_get_drvdata(pdev); 2458 struct amdgpu_device *adev = drm_to_adev(dev); 2459 2460 if (amdgpu_ras_intr_triggered()) 2461 return; 2462 2463 /* if we are running in a VM, make sure the device 2464 * torn down properly on reboot/shutdown. 2465 * unfortunately we can't detect certain 2466 * hypervisors so just do this all the time. 2467 */ 2468 if (!amdgpu_passthrough(adev)) 2469 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2470 amdgpu_device_ip_suspend(adev); 2471 adev->mp1_state = PP_MP1_STATE_NONE; 2472 } 2473 2474 /** 2475 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2476 * 2477 * @work: work_struct. 2478 */ 2479 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2480 { 2481 struct list_head device_list; 2482 struct amdgpu_device *adev; 2483 int i, r; 2484 struct amdgpu_reset_context reset_context; 2485 2486 memset(&reset_context, 0, sizeof(reset_context)); 2487 2488 mutex_lock(&mgpu_info.mutex); 2489 if (mgpu_info.pending_reset == true) { 2490 mutex_unlock(&mgpu_info.mutex); 2491 return; 2492 } 2493 mgpu_info.pending_reset = true; 2494 mutex_unlock(&mgpu_info.mutex); 2495 2496 /* Use a common context, just need to make sure full reset is done */ 2497 reset_context.method = AMD_RESET_METHOD_NONE; 2498 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2499 2500 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2501 adev = mgpu_info.gpu_ins[i].adev; 2502 reset_context.reset_req_dev = adev; 2503 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2504 if (r) { 2505 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2506 r, adev_to_drm(adev)->unique); 2507 } 2508 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2509 r = -EALREADY; 2510 } 2511 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2512 adev = mgpu_info.gpu_ins[i].adev; 2513 flush_work(&adev->xgmi_reset_work); 2514 adev->gmc.xgmi.pending_reset = false; 2515 } 2516 2517 /* reset function will rebuild the xgmi hive info , clear it now */ 2518 for (i = 0; i < mgpu_info.num_dgpu; i++) 2519 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2520 2521 INIT_LIST_HEAD(&device_list); 2522 2523 for (i = 0; i < mgpu_info.num_dgpu; i++) 2524 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2525 2526 /* unregister the GPU first, reset function will add them back */ 2527 list_for_each_entry(adev, &device_list, reset_list) 2528 amdgpu_unregister_gpu_instance(adev); 2529 2530 /* Use a common context, just need to make sure full reset is done */ 2531 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2532 set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags); 2533 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2534 2535 if (r) { 2536 DRM_ERROR("reinit gpus failure"); 2537 return; 2538 } 2539 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2540 adev = mgpu_info.gpu_ins[i].adev; 2541 if (!adev->kfd.init_complete) { 2542 kgd2kfd_init_zone_device(adev); 2543 amdgpu_amdkfd_device_init(adev); 2544 amdgpu_amdkfd_drm_client_create(adev); 2545 } 2546 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2547 } 2548 } 2549 2550 static int amdgpu_pmops_prepare(struct device *dev) 2551 { 2552 struct drm_device *drm_dev = dev_get_drvdata(dev); 2553 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2554 2555 /* Return a positive number here so 2556 * DPM_FLAG_SMART_SUSPEND works properly 2557 */ 2558 if (amdgpu_device_supports_boco(drm_dev) && 2559 pm_runtime_suspended(dev)) 2560 return 1; 2561 2562 /* if we will not support s3 or s2i for the device 2563 * then skip suspend 2564 */ 2565 if (!amdgpu_acpi_is_s0ix_active(adev) && 2566 !amdgpu_acpi_is_s3_active(adev)) 2567 return 1; 2568 2569 return amdgpu_device_prepare(drm_dev); 2570 } 2571 2572 static void amdgpu_pmops_complete(struct device *dev) 2573 { 2574 /* nothing to do */ 2575 } 2576 2577 static int amdgpu_pmops_suspend(struct device *dev) 2578 { 2579 struct drm_device *drm_dev = dev_get_drvdata(dev); 2580 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2581 2582 adev->suspend_complete = false; 2583 if (amdgpu_acpi_is_s0ix_active(adev)) 2584 adev->in_s0ix = true; 2585 else if (amdgpu_acpi_is_s3_active(adev)) 2586 adev->in_s3 = true; 2587 if (!adev->in_s0ix && !adev->in_s3) 2588 return 0; 2589 return amdgpu_device_suspend(drm_dev, true); 2590 } 2591 2592 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2593 { 2594 struct drm_device *drm_dev = dev_get_drvdata(dev); 2595 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2596 2597 adev->suspend_complete = true; 2598 if (amdgpu_acpi_should_gpu_reset(adev)) 2599 return amdgpu_asic_reset(adev); 2600 2601 return 0; 2602 } 2603 2604 static int amdgpu_pmops_resume(struct device *dev) 2605 { 2606 struct drm_device *drm_dev = dev_get_drvdata(dev); 2607 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2608 int r; 2609 2610 if (!adev->in_s0ix && !adev->in_s3) 2611 return 0; 2612 2613 /* Avoids registers access if device is physically gone */ 2614 if (!pci_device_is_present(adev->pdev)) 2615 adev->no_hw_access = true; 2616 2617 r = amdgpu_device_resume(drm_dev, true); 2618 if (amdgpu_acpi_is_s0ix_active(adev)) 2619 adev->in_s0ix = false; 2620 else 2621 adev->in_s3 = false; 2622 return r; 2623 } 2624 2625 static int amdgpu_pmops_freeze(struct device *dev) 2626 { 2627 struct drm_device *drm_dev = dev_get_drvdata(dev); 2628 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2629 int r; 2630 2631 adev->in_s4 = true; 2632 r = amdgpu_device_suspend(drm_dev, true); 2633 adev->in_s4 = false; 2634 if (r) 2635 return r; 2636 2637 if (amdgpu_acpi_should_gpu_reset(adev)) 2638 return amdgpu_asic_reset(adev); 2639 return 0; 2640 } 2641 2642 static int amdgpu_pmops_thaw(struct device *dev) 2643 { 2644 struct drm_device *drm_dev = dev_get_drvdata(dev); 2645 2646 return amdgpu_device_resume(drm_dev, true); 2647 } 2648 2649 static int amdgpu_pmops_poweroff(struct device *dev) 2650 { 2651 struct drm_device *drm_dev = dev_get_drvdata(dev); 2652 2653 return amdgpu_device_suspend(drm_dev, true); 2654 } 2655 2656 static int amdgpu_pmops_restore(struct device *dev) 2657 { 2658 struct drm_device *drm_dev = dev_get_drvdata(dev); 2659 2660 return amdgpu_device_resume(drm_dev, true); 2661 } 2662 2663 static int amdgpu_runtime_idle_check_display(struct device *dev) 2664 { 2665 struct pci_dev *pdev = to_pci_dev(dev); 2666 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2667 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2668 2669 if (adev->mode_info.num_crtc) { 2670 struct drm_connector *list_connector; 2671 struct drm_connector_list_iter iter; 2672 int ret = 0; 2673 2674 if (amdgpu_runtime_pm != -2) { 2675 /* XXX: Return busy if any displays are connected to avoid 2676 * possible display wakeups after runtime resume due to 2677 * hotplug events in case any displays were connected while 2678 * the GPU was in suspend. Remove this once that is fixed. 2679 */ 2680 mutex_lock(&drm_dev->mode_config.mutex); 2681 drm_connector_list_iter_begin(drm_dev, &iter); 2682 drm_for_each_connector_iter(list_connector, &iter) { 2683 if (list_connector->status == connector_status_connected) { 2684 ret = -EBUSY; 2685 break; 2686 } 2687 } 2688 drm_connector_list_iter_end(&iter); 2689 mutex_unlock(&drm_dev->mode_config.mutex); 2690 2691 if (ret) 2692 return ret; 2693 } 2694 2695 if (adev->dc_enabled) { 2696 struct drm_crtc *crtc; 2697 2698 drm_for_each_crtc(crtc, drm_dev) { 2699 drm_modeset_lock(&crtc->mutex, NULL); 2700 if (crtc->state->active) 2701 ret = -EBUSY; 2702 drm_modeset_unlock(&crtc->mutex); 2703 if (ret < 0) 2704 break; 2705 } 2706 } else { 2707 mutex_lock(&drm_dev->mode_config.mutex); 2708 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2709 2710 drm_connector_list_iter_begin(drm_dev, &iter); 2711 drm_for_each_connector_iter(list_connector, &iter) { 2712 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2713 ret = -EBUSY; 2714 break; 2715 } 2716 } 2717 2718 drm_connector_list_iter_end(&iter); 2719 2720 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2721 mutex_unlock(&drm_dev->mode_config.mutex); 2722 } 2723 if (ret) 2724 return ret; 2725 } 2726 2727 return 0; 2728 } 2729 2730 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2731 { 2732 struct pci_dev *pdev = to_pci_dev(dev); 2733 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2734 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2735 int ret, i; 2736 2737 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2738 pm_runtime_forbid(dev); 2739 return -EBUSY; 2740 } 2741 2742 ret = amdgpu_runtime_idle_check_display(dev); 2743 if (ret) 2744 return ret; 2745 2746 /* wait for all rings to drain before suspending */ 2747 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2748 struct amdgpu_ring *ring = adev->rings[i]; 2749 2750 if (ring && ring->sched.ready) { 2751 ret = amdgpu_fence_wait_empty(ring); 2752 if (ret) 2753 return -EBUSY; 2754 } 2755 } 2756 2757 adev->in_runpm = true; 2758 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2759 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2760 2761 /* 2762 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2763 * proper cleanups and put itself into a state ready for PNP. That 2764 * can address some random resuming failure observed on BOCO capable 2765 * platforms. 2766 * TODO: this may be also needed for PX capable platform. 2767 */ 2768 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2769 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2770 2771 ret = amdgpu_device_prepare(drm_dev); 2772 if (ret) 2773 return ret; 2774 ret = amdgpu_device_suspend(drm_dev, false); 2775 if (ret) { 2776 adev->in_runpm = false; 2777 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2778 adev->mp1_state = PP_MP1_STATE_NONE; 2779 return ret; 2780 } 2781 2782 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) 2783 adev->mp1_state = PP_MP1_STATE_NONE; 2784 2785 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2786 /* Only need to handle PCI state in the driver for ATPX 2787 * PCI core handles it for _PR3. 2788 */ 2789 amdgpu_device_cache_pci_state(pdev); 2790 pci_disable_device(pdev); 2791 pci_ignore_hotplug(pdev); 2792 pci_set_power_state(pdev, PCI_D3cold); 2793 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2794 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2795 /* nothing to do */ 2796 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2797 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2798 amdgpu_device_baco_enter(drm_dev); 2799 } 2800 2801 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2802 2803 return 0; 2804 } 2805 2806 static int amdgpu_pmops_runtime_resume(struct device *dev) 2807 { 2808 struct pci_dev *pdev = to_pci_dev(dev); 2809 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2810 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2811 int ret; 2812 2813 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2814 return -EINVAL; 2815 2816 /* Avoids registers access if device is physically gone */ 2817 if (!pci_device_is_present(adev->pdev)) 2818 adev->no_hw_access = true; 2819 2820 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { 2821 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2822 2823 /* Only need to handle PCI state in the driver for ATPX 2824 * PCI core handles it for _PR3. 2825 */ 2826 pci_set_power_state(pdev, PCI_D0); 2827 amdgpu_device_load_pci_state(pdev); 2828 ret = pci_enable_device(pdev); 2829 if (ret) 2830 return ret; 2831 pci_set_master(pdev); 2832 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { 2833 /* Only need to handle PCI state in the driver for ATPX 2834 * PCI core handles it for _PR3. 2835 */ 2836 pci_set_master(pdev); 2837 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || 2838 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { 2839 amdgpu_device_baco_exit(drm_dev); 2840 } 2841 ret = amdgpu_device_resume(drm_dev, false); 2842 if (ret) { 2843 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2844 pci_disable_device(pdev); 2845 return ret; 2846 } 2847 2848 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) 2849 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2850 adev->in_runpm = false; 2851 return 0; 2852 } 2853 2854 static int amdgpu_pmops_runtime_idle(struct device *dev) 2855 { 2856 struct drm_device *drm_dev = dev_get_drvdata(dev); 2857 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2858 int ret; 2859 2860 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2861 pm_runtime_forbid(dev); 2862 return -EBUSY; 2863 } 2864 2865 ret = amdgpu_runtime_idle_check_display(dev); 2866 2867 pm_runtime_mark_last_busy(dev); 2868 pm_runtime_autosuspend(dev); 2869 return ret; 2870 } 2871 2872 long amdgpu_drm_ioctl(struct file *filp, 2873 unsigned int cmd, unsigned long arg) 2874 { 2875 struct drm_file *file_priv = filp->private_data; 2876 struct drm_device *dev; 2877 long ret; 2878 2879 dev = file_priv->minor->dev; 2880 ret = pm_runtime_get_sync(dev->dev); 2881 if (ret < 0) 2882 goto out; 2883 2884 ret = drm_ioctl(filp, cmd, arg); 2885 2886 pm_runtime_mark_last_busy(dev->dev); 2887 out: 2888 pm_runtime_put_autosuspend(dev->dev); 2889 return ret; 2890 } 2891 2892 static const struct dev_pm_ops amdgpu_pm_ops = { 2893 .prepare = amdgpu_pmops_prepare, 2894 .complete = amdgpu_pmops_complete, 2895 .suspend = amdgpu_pmops_suspend, 2896 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2897 .resume = amdgpu_pmops_resume, 2898 .freeze = amdgpu_pmops_freeze, 2899 .thaw = amdgpu_pmops_thaw, 2900 .poweroff = amdgpu_pmops_poweroff, 2901 .restore = amdgpu_pmops_restore, 2902 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2903 .runtime_resume = amdgpu_pmops_runtime_resume, 2904 .runtime_idle = amdgpu_pmops_runtime_idle, 2905 }; 2906 2907 static int amdgpu_flush(struct file *f, fl_owner_t id) 2908 { 2909 struct drm_file *file_priv = f->private_data; 2910 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2911 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2912 2913 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2914 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2915 2916 return timeout >= 0 ? 0 : timeout; 2917 } 2918 2919 static const struct file_operations amdgpu_driver_kms_fops = { 2920 .owner = THIS_MODULE, 2921 .open = drm_open, 2922 .flush = amdgpu_flush, 2923 .release = drm_release, 2924 .unlocked_ioctl = amdgpu_drm_ioctl, 2925 .mmap = drm_gem_mmap, 2926 .poll = drm_poll, 2927 .read = drm_read, 2928 #ifdef CONFIG_COMPAT 2929 .compat_ioctl = amdgpu_kms_compat_ioctl, 2930 #endif 2931 #ifdef CONFIG_PROC_FS 2932 .show_fdinfo = drm_show_fdinfo, 2933 #endif 2934 .fop_flags = FOP_UNSIGNED_OFFSET, 2935 }; 2936 2937 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2938 { 2939 struct drm_file *file; 2940 2941 if (!filp) 2942 return -EINVAL; 2943 2944 if (filp->f_op != &amdgpu_driver_kms_fops) 2945 return -EINVAL; 2946 2947 file = filp->private_data; 2948 *fpriv = file->driver_priv; 2949 return 0; 2950 } 2951 2952 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2953 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2954 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2955 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2956 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2957 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2958 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2959 /* KMS */ 2960 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2961 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2962 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2963 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2964 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2965 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2966 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2967 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2968 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2969 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2970 }; 2971 2972 static const struct drm_driver amdgpu_kms_driver = { 2973 .driver_features = 2974 DRIVER_ATOMIC | 2975 DRIVER_GEM | 2976 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2977 DRIVER_SYNCOBJ_TIMELINE, 2978 .open = amdgpu_driver_open_kms, 2979 .postclose = amdgpu_driver_postclose_kms, 2980 .ioctls = amdgpu_ioctls_kms, 2981 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2982 .dumb_create = amdgpu_mode_dumb_create, 2983 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2984 .fops = &amdgpu_driver_kms_fops, 2985 .release = &amdgpu_driver_release_kms, 2986 #ifdef CONFIG_PROC_FS 2987 .show_fdinfo = amdgpu_show_fdinfo, 2988 #endif 2989 2990 .gem_prime_import = amdgpu_gem_prime_import, 2991 2992 .name = DRIVER_NAME, 2993 .desc = DRIVER_DESC, 2994 .date = DRIVER_DATE, 2995 .major = KMS_DRIVER_MAJOR, 2996 .minor = KMS_DRIVER_MINOR, 2997 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2998 }; 2999 3000 const struct drm_driver amdgpu_partition_driver = { 3001 .driver_features = 3002 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 3003 DRIVER_SYNCOBJ_TIMELINE, 3004 .open = amdgpu_driver_open_kms, 3005 .postclose = amdgpu_driver_postclose_kms, 3006 .ioctls = amdgpu_ioctls_kms, 3007 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 3008 .dumb_create = amdgpu_mode_dumb_create, 3009 .dumb_map_offset = amdgpu_mode_dumb_mmap, 3010 .fops = &amdgpu_driver_kms_fops, 3011 .release = &amdgpu_driver_release_kms, 3012 3013 .gem_prime_import = amdgpu_gem_prime_import, 3014 3015 .name = DRIVER_NAME, 3016 .desc = DRIVER_DESC, 3017 .date = DRIVER_DATE, 3018 .major = KMS_DRIVER_MAJOR, 3019 .minor = KMS_DRIVER_MINOR, 3020 .patchlevel = KMS_DRIVER_PATCHLEVEL, 3021 }; 3022 3023 static struct pci_error_handlers amdgpu_pci_err_handler = { 3024 .error_detected = amdgpu_pci_error_detected, 3025 .mmio_enabled = amdgpu_pci_mmio_enabled, 3026 .slot_reset = amdgpu_pci_slot_reset, 3027 .resume = amdgpu_pci_resume, 3028 }; 3029 3030 static const struct attribute_group *amdgpu_sysfs_groups[] = { 3031 &amdgpu_vram_mgr_attr_group, 3032 &amdgpu_gtt_mgr_attr_group, 3033 &amdgpu_flash_attr_group, 3034 NULL, 3035 }; 3036 3037 static struct pci_driver amdgpu_kms_pci_driver = { 3038 .name = DRIVER_NAME, 3039 .id_table = pciidlist, 3040 .probe = amdgpu_pci_probe, 3041 .remove = amdgpu_pci_remove, 3042 .shutdown = amdgpu_pci_shutdown, 3043 .driver.pm = &amdgpu_pm_ops, 3044 .err_handler = &amdgpu_pci_err_handler, 3045 .dev_groups = amdgpu_sysfs_groups, 3046 }; 3047 3048 static int __init amdgpu_init(void) 3049 { 3050 int r; 3051 3052 if (drm_firmware_drivers_only()) 3053 return -EINVAL; 3054 3055 r = amdgpu_sync_init(); 3056 if (r) 3057 goto error_sync; 3058 3059 r = amdgpu_fence_slab_init(); 3060 if (r) 3061 goto error_fence; 3062 3063 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 3064 amdgpu_register_atpx_handler(); 3065 amdgpu_acpi_detect(); 3066 3067 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 3068 amdgpu_amdkfd_init(); 3069 3070 /* let modprobe override vga console setting */ 3071 return pci_register_driver(&amdgpu_kms_pci_driver); 3072 3073 error_fence: 3074 amdgpu_sync_fini(); 3075 3076 error_sync: 3077 return r; 3078 } 3079 3080 static void __exit amdgpu_exit(void) 3081 { 3082 amdgpu_amdkfd_fini(); 3083 pci_unregister_driver(&amdgpu_kms_pci_driver); 3084 amdgpu_unregister_atpx_handler(); 3085 amdgpu_acpi_release(); 3086 amdgpu_sync_fini(); 3087 amdgpu_fence_slab_fini(); 3088 mmu_notifier_synchronize(); 3089 amdgpu_xcp_drv_release(); 3090 } 3091 3092 module_init(amdgpu_init); 3093 module_exit(amdgpu_exit); 3094 3095 MODULE_AUTHOR(DRIVER_AUTHOR); 3096 MODULE_DESCRIPTION(DRIVER_DESC); 3097 MODULE_LICENSE("GPL and additional rights"); 3098