1 /*
2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include <drm/amdgpu_drm.h>
26 #include <drm/clients/drm_client_setup.h>
27 #include <drm/drm_drv.h>
28 #include <drm/drm_fbdev_ttm.h>
29 #include <drm/drm_gem.h>
30 #include <drm/drm_managed.h>
31 #include <drm/drm_pciids.h>
32 #include <drm/drm_probe_helper.h>
33 #include <drm/drm_vblank.h>
34
35 #include <linux/cc_platform.h>
36 #include <linux/dynamic_debug.h>
37 #include <linux/module.h>
38 #include <linux/mmu_notifier.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/suspend.h>
41 #include <linux/vga_switcheroo.h>
42
43 #include "amdgpu.h"
44 #include "amdgpu_amdkfd.h"
45 #include "amdgpu_dma_buf.h"
46 #include "amdgpu_drv.h"
47 #include "amdgpu_fdinfo.h"
48 #include "amdgpu_irq.h"
49 #include "amdgpu_psp.h"
50 #include "amdgpu_ras.h"
51 #include "amdgpu_reset.h"
52 #include "amdgpu_sched.h"
53 #include "amdgpu_xgmi.h"
54 #include "amdgpu_userq.h"
55 #include "amdgpu_userq_fence.h"
56 #include "../amdxcp/amdgpu_xcp_drv.h"
57
58 /*
59 * KMS wrapper.
60 * - 3.0.0 - initial driver
61 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
62 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
63 * at the end of IBs.
64 * - 3.3.0 - Add VM support for UVD on supported hardware.
65 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
66 * - 3.5.0 - Add support for new UVD_NO_OP register.
67 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
68 * - 3.7.0 - Add support for VCE clock list packet
69 * - 3.8.0 - Add support raster config init in the kernel
70 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
71 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
72 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
73 * - 3.12.0 - Add query for double offchip LDS buffers
74 * - 3.13.0 - Add PRT support
75 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
76 * - 3.15.0 - Export more gpu info for gfx9
77 * - 3.16.0 - Add reserved vmid support
78 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
79 * - 3.18.0 - Export gpu always on cu bitmap
80 * - 3.19.0 - Add support for UVD MJPEG decode
81 * - 3.20.0 - Add support for local BOs
82 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
83 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
84 * - 3.23.0 - Add query for VRAM lost counter
85 * - 3.24.0 - Add high priority compute support for gfx9
86 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
87 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
88 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
89 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
90 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
91 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
92 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
93 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
94 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
95 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
96 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
97 * - 3.36.0 - Allow reading more status registers on si/cik
98 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
99 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
100 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
101 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
102 * - 3.41.0 - Add video codec query
103 * - 3.42.0 - Add 16bpc fixed point display support
104 * - 3.43.0 - Add device hot plug/unplug support
105 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
106 * - 3.45.0 - Add context ioctl stable pstate interface
107 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm
108 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
109 * - 3.48.0 - Add IP discovery version info to HW INFO
110 * - 3.49.0 - Add gang submit into CS IOCTL
111 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock
112 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock
113 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl
114 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields:
115 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size,
116 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi
117 * 3.53.0 - Support for GFX11 CP GFX shadowing
118 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support
119 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query
120 * - 3.56.0 - Update IB start address and size alignment for decode and encode
121 * - 3.57.0 - Compute tunneling on GFX10+
122 * - 3.58.0 - Add GFX12 DCC support
123 * - 3.59.0 - Cleared VRAM
124 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement)
125 * - 3.61.0 - Contains fix for RV/PCO compute queues
126 * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT
127 * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size
128 * - 3.64.0 - Userq IP support query
129 */
130 #define KMS_DRIVER_MAJOR 3
131 #define KMS_DRIVER_MINOR 64
132 #define KMS_DRIVER_PATCHLEVEL 0
133
134 /*
135 * amdgpu.debug module options. Are all disabled by default
136 */
137 enum AMDGPU_DEBUG_MASK {
138 AMDGPU_DEBUG_VM = BIT(0),
139 AMDGPU_DEBUG_LARGEBAR = BIT(1),
140 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2),
141 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3),
142 AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4),
143 AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5),
144 AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6),
145 AMDGPU_DEBUG_SMU_POOL = BIT(7),
146 AMDGPU_DEBUG_VM_USERPTR = BIT(8),
147 };
148
149 unsigned int amdgpu_vram_limit = UINT_MAX;
150 int amdgpu_vis_vram_limit;
151 int amdgpu_gart_size = -1; /* auto */
152 int amdgpu_gtt_size = -1; /* auto */
153 int amdgpu_moverate = -1; /* auto */
154 int amdgpu_audio = -1;
155 int amdgpu_disp_priority;
156 int amdgpu_hw_i2c;
157 int amdgpu_pcie_gen2 = -1;
158 int amdgpu_msi = -1;
159 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
160 int amdgpu_dpm = -1;
161 int amdgpu_fw_load_type = -1;
162 int amdgpu_aspm = -1;
163 int amdgpu_runtime_pm = -1;
164 uint amdgpu_ip_block_mask = 0xffffffff;
165 int amdgpu_bapm = -1;
166 int amdgpu_deep_color;
167 int amdgpu_vm_size = -1;
168 int amdgpu_vm_fragment_size = -1;
169 int amdgpu_vm_block_size = -1;
170 int amdgpu_vm_fault_stop;
171 int amdgpu_vm_update_mode = -1;
172 int amdgpu_exp_hw_support;
173 int amdgpu_dc = -1;
174 int amdgpu_sched_jobs = 32;
175 int amdgpu_sched_hw_submission = 2;
176 uint amdgpu_pcie_gen_cap;
177 uint amdgpu_pcie_lane_cap;
178 u64 amdgpu_cg_mask = 0xffffffffffffffff;
179 uint amdgpu_pg_mask = 0xffffffff;
180 uint amdgpu_sdma_phase_quantum = 32;
181 char *amdgpu_disable_cu;
182 char *amdgpu_virtual_display;
183 int amdgpu_enforce_isolation = -1;
184 int amdgpu_modeset = -1;
185
186 /* Specifies the default granularity for SVM, used in buffer
187 * migration and restoration of backing memory when handling
188 * recoverable page faults.
189 *
190 * The value is given as log(numPages(buffer)); for a 2 MiB
191 * buffer it computes to be 9
192 */
193 uint amdgpu_svm_default_granularity = 9;
194
195 /*
196 * OverDrive(bit 14) disabled by default
197 * GFX DCS(bit 19) disabled by default
198 */
199 uint amdgpu_pp_feature_mask = 0xfff7bfff;
200 uint amdgpu_force_long_training;
201 int amdgpu_lbpw = -1;
202 int amdgpu_compute_multipipe = -1;
203 int amdgpu_gpu_recovery = -1; /* auto */
204 int amdgpu_emu_mode;
205 uint amdgpu_smu_memory_pool_size;
206 int amdgpu_smu_pptable_id = -1;
207 /*
208 * FBC (bit 0) disabled by default
209 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
210 * - With this, for multiple monitors in sync(e.g. with the same model),
211 * mclk switching will be allowed. And the mclk will be not foced to the
212 * highest. That helps saving some idle power.
213 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
214 * PSR (bit 3) disabled by default
215 * EDP NO POWER SEQUENCING (bit 4) disabled by default
216 */
217 uint amdgpu_dc_feature_mask = 2;
218 uint amdgpu_dc_debug_mask;
219 uint amdgpu_dc_visual_confirm;
220 int amdgpu_async_gfx_ring = 1;
221 int amdgpu_mcbp = -1;
222 int amdgpu_discovery = -1;
223 int amdgpu_mes;
224 int amdgpu_mes_log_enable = 0;
225 int amdgpu_mes_kiq;
226 int amdgpu_uni_mes = 1;
227 int amdgpu_noretry = -1;
228 int amdgpu_force_asic_type = -1;
229 int amdgpu_tmz = -1; /* auto */
230 uint amdgpu_freesync_vid_mode;
231 int amdgpu_reset_method = -1; /* auto */
232 int amdgpu_num_kcq = -1;
233 int amdgpu_smartshift_bias;
234 int amdgpu_use_xgmi_p2p = 1;
235 int amdgpu_vcnfw_log;
236 int amdgpu_sg_display = -1; /* auto */
237 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE;
238 int amdgpu_umsch_mm;
239 int amdgpu_seamless = -1; /* auto */
240 uint amdgpu_debug_mask;
241 int amdgpu_agp = -1; /* auto */
242 int amdgpu_wbrf = -1;
243 int amdgpu_damage_clips = -1; /* auto */
244 int amdgpu_umsch_mm_fwlog;
245 int amdgpu_rebar = -1; /* auto */
246 int amdgpu_user_queue = -1;
247
248 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
249 "DRM_UT_CORE",
250 "DRM_UT_DRIVER",
251 "DRM_UT_KMS",
252 "DRM_UT_PRIME",
253 "DRM_UT_ATOMIC",
254 "DRM_UT_VBL",
255 "DRM_UT_STATE",
256 "DRM_UT_LEASE",
257 "DRM_UT_DP",
258 "DRM_UT_DRMRES");
259
260 struct amdgpu_mgpu_info mgpu_info = {
261 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
262 };
263 int amdgpu_ras_enable = -1;
264 uint amdgpu_ras_mask = 0xffffffff;
265 int amdgpu_bad_page_threshold = -1;
266 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
267 .timeout_fatal_disable = false,
268 .period = 0x0, /* default to 0x0 (timeout disable) */
269 };
270
271 /**
272 * DOC: vramlimit (int)
273 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
274 */
275 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
276 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
277
278 /**
279 * DOC: vis_vramlimit (int)
280 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
281 */
282 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
283 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
284
285 /**
286 * DOC: gartsize (uint)
287 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing.
288 * The default is -1 (The size depends on asic).
289 */
290 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)");
291 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
292
293 /**
294 * DOC: gttsize (int)
295 * Restrict the size of GTT domain (for userspace use) in MiB for testing.
296 * The default is -1 (Use value specified by TTM).
297 * This parameter is deprecated and will be removed in the future.
298 */
299 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)");
300 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
301
302 /**
303 * DOC: moverate (int)
304 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
305 */
306 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
307 module_param_named(moverate, amdgpu_moverate, int, 0600);
308
309 /**
310 * DOC: audio (int)
311 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
312 */
313 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
314 module_param_named(audio, amdgpu_audio, int, 0444);
315
316 /**
317 * DOC: disp_priority (int)
318 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
319 */
320 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
321 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
322
323 /**
324 * DOC: hw_i2c (int)
325 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
326 */
327 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
328 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
329
330 /**
331 * DOC: pcie_gen2 (int)
332 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
333 */
334 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
335 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
336
337 /**
338 * DOC: msi (int)
339 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
340 */
341 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
342 module_param_named(msi, amdgpu_msi, int, 0444);
343
344 /**
345 * DOC: svm_default_granularity (uint)
346 * Used in buffer migration and handling of recoverable page faults
347 */
348 MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB");
349 module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644);
350
351 /**
352 * DOC: lockup_timeout (string)
353 * Set GPU scheduler timeout value in ms.
354 *
355 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
356 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
357 * to the default timeout.
358 *
359 * - With one value specified, the setting will apply to all non-compute jobs.
360 * - With multiple values specified, the first one will be for GFX.
361 * The second one is for Compute. The third and fourth ones are
362 * for SDMA and Video.
363 *
364 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
365 * jobs is 10000. The timeout for compute is 60000.
366 */
367 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; "
368 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
369 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
370 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
371
372 /**
373 * DOC: dpm (int)
374 * Override for dynamic power management setting
375 * (0 = disable, 1 = enable)
376 * The default is -1 (auto).
377 */
378 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
379 module_param_named(dpm, amdgpu_dpm, int, 0444);
380
381 /**
382 * DOC: fw_load_type (int)
383 * Set different firmware loading type for debugging, if supported.
384 * Set to 0 to force direct loading if supported by the ASIC. Set
385 * to -1 to select the default loading mode for the ASIC, as defined
386 * by the driver. The default is -1 (auto).
387 */
388 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)");
389 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
390
391 /**
392 * DOC: aspm (int)
393 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
394 */
395 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
396 module_param_named(aspm, amdgpu_aspm, int, 0444);
397
398 /**
399 * DOC: runpm (int)
400 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
401 * the dGPUs when they are idle if supported. The default is -1 (auto enable).
402 * Setting the value to 0 disables this functionality.
403 * Setting the value to -2 is auto enabled with power down when displays are attached.
404 */
405 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)");
406 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
407
408 /**
409 * DOC: ip_block_mask (uint)
410 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
411 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
412 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
413 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
414 */
415 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
416 module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
417
418 /**
419 * DOC: bapm (int)
420 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
421 * The default -1 (auto, enabled)
422 */
423 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
424 module_param_named(bapm, amdgpu_bapm, int, 0444);
425
426 /**
427 * DOC: deep_color (int)
428 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
429 */
430 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
431 module_param_named(deep_color, amdgpu_deep_color, int, 0444);
432
433 /**
434 * DOC: vm_size (int)
435 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
436 */
437 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
438 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
439
440 /**
441 * DOC: vm_fragment_size (int)
442 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
443 */
444 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
445 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
446
447 /**
448 * DOC: vm_block_size (int)
449 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
450 */
451 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
452 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
453
454 /**
455 * DOC: vm_fault_stop (int)
456 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
457 */
458 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
459 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
460
461 /**
462 * DOC: vm_update_mode (int)
463 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
464 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
465 */
466 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
467 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
468
469 /**
470 * DOC: exp_hw_support (int)
471 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
472 */
473 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
474 module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
475
476 /**
477 * DOC: dc (int)
478 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
479 */
480 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
481 module_param_named(dc, amdgpu_dc, int, 0444);
482
483 /**
484 * DOC: sched_jobs (int)
485 * Override the max number of jobs supported in the sw queue. The default is 32.
486 */
487 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
488 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
489
490 /**
491 * DOC: sched_hw_submission (int)
492 * Override the max number of HW submissions. The default is 2.
493 */
494 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
495 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
496
497 /**
498 * DOC: ppfeaturemask (hexint)
499 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
500 * The default is the current set of stable power features.
501 */
502 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
503 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
504
505 /**
506 * DOC: forcelongtraining (uint)
507 * Force long memory training in resume.
508 * The default is zero, indicates short training in resume.
509 */
510 MODULE_PARM_DESC(forcelongtraining, "force memory long training");
511 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
512
513 /**
514 * DOC: pcie_gen_cap (uint)
515 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
516 * The default is 0 (automatic for each asic).
517 */
518 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
519 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
520
521 /**
522 * DOC: pcie_lane_cap (uint)
523 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
524 * The default is 0 (automatic for each asic).
525 */
526 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
527 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
528
529 /**
530 * DOC: cg_mask (ullong)
531 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
532 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled).
533 */
534 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
535 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444);
536
537 /**
538 * DOC: pg_mask (uint)
539 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
540 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
541 */
542 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
543 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
544
545 /**
546 * DOC: sdma_phase_quantum (uint)
547 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
548 */
549 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
550 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
551
552 /**
553 * DOC: disable_cu (charp)
554 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
555 */
556 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
557 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
558
559 /**
560 * DOC: virtual_display (charp)
561 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
562 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
563 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
564 * device at 26:00.0. The default is NULL.
565 */
566 MODULE_PARM_DESC(virtual_display,
567 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
568 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
569
570 /**
571 * DOC: lbpw (int)
572 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
573 */
574 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
575 module_param_named(lbpw, amdgpu_lbpw, int, 0444);
576
577 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
578 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
579
580 /**
581 * DOC: gpu_recovery (int)
582 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
583 */
584 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
585 module_param_named_unsafe(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
586
587 /**
588 * DOC: emu_mode (int)
589 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
590 */
591 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
592 module_param_named_unsafe(emu_mode, amdgpu_emu_mode, int, 0444);
593
594 /**
595 * DOC: ras_enable (int)
596 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
597 */
598 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
599 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
600
601 /**
602 * DOC: ras_mask (uint)
603 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
604 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
605 */
606 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
607 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
608
609 /**
610 * DOC: timeout_fatal_disable (bool)
611 * Disable Watchdog timeout fatal error event
612 */
613 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
614 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
615
616 /**
617 * DOC: timeout_period (uint)
618 * Modify the watchdog timeout max_cycles as (1 << period)
619 */
620 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
621 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
622
623 /**
624 * DOC: si_support (int)
625 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
626 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
627 * otherwise using amdgpu driver.
628 */
629 #ifdef CONFIG_DRM_AMDGPU_SI
630
631 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE)
632 int amdgpu_si_support;
633 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
634 #else
635 int amdgpu_si_support = 1;
636 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
637 #endif
638
639 module_param_named(si_support, amdgpu_si_support, int, 0444);
640 #endif
641
642 /**
643 * DOC: cik_support (int)
644 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
645 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
646 * otherwise using amdgpu driver.
647 */
648 #ifdef CONFIG_DRM_AMDGPU_CIK
649
650 #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE)
651 int amdgpu_cik_support;
652 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
653 #else
654 int amdgpu_cik_support = 1;
655 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
656 #endif
657
658 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
659 #endif
660
661 /**
662 * DOC: smu_memory_pool_size (uint)
663 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
664 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
665 */
666 MODULE_PARM_DESC(smu_memory_pool_size,
667 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
668 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
669
670 /**
671 * DOC: async_gfx_ring (int)
672 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
673 */
674 MODULE_PARM_DESC(async_gfx_ring,
675 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
676 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
677
678 /**
679 * DOC: mcbp (int)
680 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default))
681 */
682 MODULE_PARM_DESC(mcbp,
683 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)");
684 module_param_named(mcbp, amdgpu_mcbp, int, 0444);
685
686 /**
687 * DOC: discovery (int)
688 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
689 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
690 */
691 MODULE_PARM_DESC(discovery,
692 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
693 module_param_named(discovery, amdgpu_discovery, int, 0444);
694
695 /**
696 * DOC: mes (int)
697 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
698 * (0 = disabled (default), 1 = enabled)
699 */
700 MODULE_PARM_DESC(mes,
701 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
702 module_param_named(mes, amdgpu_mes, int, 0444);
703
704 /**
705 * DOC: mes_log_enable (int)
706 * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log.
707 * (0 = disabled (default), 1 = enabled)
708 */
709 MODULE_PARM_DESC(mes_log_enable,
710 "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)");
711 module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444);
712
713 /**
714 * DOC: mes_kiq (int)
715 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq.
716 * (0 = disabled (default), 1 = enabled)
717 */
718 MODULE_PARM_DESC(mes_kiq,
719 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)");
720 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444);
721
722 /**
723 * DOC: uni_mes (int)
724 * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler.
725 * (0 = disabled (default), 1 = enabled)
726 */
727 MODULE_PARM_DESC(uni_mes,
728 "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)");
729 module_param_named(uni_mes, amdgpu_uni_mes, int, 0444);
730
731 /**
732 * DOC: noretry (int)
733 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
734 * do not support per-process XNACK this also disables retry page faults.
735 * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
736 */
737 MODULE_PARM_DESC(noretry,
738 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
739 module_param_named(noretry, amdgpu_noretry, int, 0644);
740
741 /**
742 * DOC: force_asic_type (int)
743 * A non negative value used to specify the asic type for all supported GPUs.
744 */
745 MODULE_PARM_DESC(force_asic_type,
746 "A non negative value used to specify the asic type for all supported GPUs");
747 module_param_named_unsafe(force_asic_type, amdgpu_force_asic_type, int, 0444);
748
749 /**
750 * DOC: use_xgmi_p2p (int)
751 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable).
752 */
753 MODULE_PARM_DESC(use_xgmi_p2p,
754 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))");
755 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444);
756
757
758 #ifdef CONFIG_HSA_AMD
759 /**
760 * DOC: sched_policy (int)
761 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
762 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
763 * assigns queues to HQDs.
764 */
765 int sched_policy = KFD_SCHED_POLICY_HWS;
766 module_param_unsafe(sched_policy, int, 0444);
767 MODULE_PARM_DESC(sched_policy,
768 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
769
770 /**
771 * DOC: hws_max_conc_proc (int)
772 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
773 * number of VMIDs assigned to the HWS, which is also the default.
774 */
775 int hws_max_conc_proc = -1;
776 module_param(hws_max_conc_proc, int, 0444);
777 MODULE_PARM_DESC(hws_max_conc_proc,
778 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
779
780 /**
781 * DOC: cwsr_enable (int)
782 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
783 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
784 * disables it.
785 */
786 int cwsr_enable = 1;
787 module_param(cwsr_enable, int, 0444);
788 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
789
790 /**
791 * DOC: max_num_of_queues_per_device (int)
792 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
793 * is 4096.
794 */
795 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
796 module_param(max_num_of_queues_per_device, int, 0444);
797 MODULE_PARM_DESC(max_num_of_queues_per_device,
798 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
799
800 /**
801 * DOC: send_sigterm (int)
802 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
803 * but just print errors on dmesg. Setting 1 enables sending sigterm.
804 */
805 int send_sigterm;
806 module_param(send_sigterm, int, 0444);
807 MODULE_PARM_DESC(send_sigterm,
808 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
809
810 /**
811 * DOC: halt_if_hws_hang (int)
812 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
813 * Setting 1 enables halt on hang.
814 */
815 int halt_if_hws_hang;
816 module_param_unsafe(halt_if_hws_hang, int, 0644);
817 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
818
819 /**
820 * DOC: hws_gws_support(bool)
821 * Assume that HWS supports GWS barriers regardless of what firmware version
822 * check says. Default value: false (rely on MEC2 firmware version check).
823 */
824 bool hws_gws_support;
825 module_param_unsafe(hws_gws_support, bool, 0444);
826 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
827
828 /**
829 * DOC: queue_preemption_timeout_ms (int)
830 * queue preemption timeout in ms (1 = Minimum, 9000 = default)
831 */
832 int queue_preemption_timeout_ms = 9000;
833 module_param(queue_preemption_timeout_ms, int, 0644);
834 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
835
836 /**
837 * DOC: debug_evictions(bool)
838 * Enable extra debug messages to help determine the cause of evictions
839 */
840 bool debug_evictions;
841 module_param(debug_evictions, bool, 0644);
842 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
843
844 /**
845 * DOC: no_system_mem_limit(bool)
846 * Disable system memory limit, to support multiple process shared memory
847 */
848 bool no_system_mem_limit;
849 module_param(no_system_mem_limit, bool, 0644);
850 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
851
852 /**
853 * DOC: no_queue_eviction_on_vm_fault (int)
854 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
855 */
856 int amdgpu_no_queue_eviction_on_vm_fault;
857 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
858 module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
859 #endif
860
861 /**
862 * DOC: mtype_local (int)
863 */
864 int amdgpu_mtype_local;
865 MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)");
866 module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444);
867
868 /**
869 * DOC: pcie_p2p (bool)
870 * Enable PCIe P2P (requires large-BAR). Default value: true (on)
871 */
872 #ifdef CONFIG_HSA_AMD_P2P
873 bool pcie_p2p = true;
874 module_param(pcie_p2p, bool, 0444);
875 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))");
876 #endif
877
878 /**
879 * DOC: dcfeaturemask (uint)
880 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
881 * The default is the current set of stable display features.
882 */
883 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
884 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
885
886 /**
887 * DOC: dcdebugmask (uint)
888 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
889 */
890 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
891 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
892
893 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)");
894 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444);
895
896 /**
897 * DOC: abmlevel (uint)
898 * Override the default ABM (Adaptive Backlight Management) level used for DC
899 * enabled hardware. Requires DMCU to be supported and loaded.
900 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
901 * default. Values 1-4 control the maximum allowable brightness reduction via
902 * the ABM algorithm, with 1 being the least reduction and 4 being the most
903 * reduction.
904 *
905 * Defaults to -1, or auto. Userspace can only override this level after
906 * boot if it's set to auto.
907 */
908 int amdgpu_dm_abm_level = -1;
909 MODULE_PARM_DESC(abmlevel,
910 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))");
911 module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444);
912
913 int amdgpu_backlight = -1;
914 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
915 module_param_named(backlight, amdgpu_backlight, bint, 0444);
916
917 /**
918 * DOC: damageclips (int)
919 * Enable or disable damage clips support. If damage clips support is disabled,
920 * we will force full frame updates, irrespective of what user space sends to
921 * us.
922 *
923 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected).
924 */
925 MODULE_PARM_DESC(damageclips,
926 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))");
927 module_param_named(damageclips, amdgpu_damage_clips, int, 0444);
928
929 /**
930 * DOC: tmz (int)
931 * Trusted Memory Zone (TMZ) is a method to protect data being written
932 * to or read from memory.
933 *
934 * The default value: 0 (off). TODO: change to auto till it is completed.
935 */
936 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
937 module_param_named(tmz, amdgpu_tmz, int, 0444);
938
939 /**
940 * DOC: freesync_video (uint)
941 * Enable the optimization to adjust front porch timing to achieve seamless
942 * mode change experience when setting a freesync supported mode for which full
943 * modeset is not needed.
944 *
945 * The Display Core will add a set of modes derived from the base FreeSync
946 * video mode into the corresponding connector's mode list based on commonly
947 * used refresh rates and VRR range of the connected display, when users enable
948 * this feature. From the userspace perspective, they can see a seamless mode
949 * change experience when the change between different refresh rates under the
950 * same resolution. Additionally, userspace applications such as Video playback
951 * can read this modeset list and change the refresh rate based on the video
952 * frame rate. Finally, the userspace can also derive an appropriate mode for a
953 * particular refresh rate based on the FreeSync Mode and add it to the
954 * connector's mode list.
955 *
956 * Note: This is an experimental feature.
957 *
958 * The default value: 0 (off).
959 */
960 MODULE_PARM_DESC(
961 freesync_video,
962 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)");
963 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);
964
965 /**
966 * DOC: reset_method (int)
967 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
968 */
969 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
970 module_param_named_unsafe(reset_method, amdgpu_reset_method, int, 0644);
971
972 /**
973 * DOC: bad_page_threshold (int) Bad page threshold is specifies the
974 * threshold value of faulty pages detected by RAS ECC, which may
975 * result in the GPU entering bad status when the number of total
976 * faulty pages by ECC exceeds the threshold value.
977 */
978 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = threshold determined by a formula, 0 < threshold < max records, user-defined threshold)");
979 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
980
981 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
982 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
983
984 /**
985 * DOC: vcnfw_log (int)
986 * Enable vcnfw log output for debugging, the default is disabled.
987 */
988 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)");
989 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
990
991 /**
992 * DOC: sg_display (int)
993 * Disable S/G (scatter/gather) display (i.e., display from system memory).
994 * This option is only relevant on APUs. Set this option to 0 to disable
995 * S/G display if you experience flickering or other issues under memory
996 * pressure and report the issue.
997 */
998 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)");
999 module_param_named(sg_display, amdgpu_sg_display, int, 0444);
1000
1001 /**
1002 * DOC: umsch_mm (int)
1003 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE.
1004 * (0 = disabled (default), 1 = enabled)
1005 */
1006 MODULE_PARM_DESC(umsch_mm,
1007 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)");
1008 module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444);
1009
1010 /**
1011 * DOC: umsch_mm_fwlog (int)
1012 * Enable umschfw log output for debugging, the default is disabled.
1013 */
1014 MODULE_PARM_DESC(umsch_mm_fwlog, "Enable umschfw log(0 = disable (default value), 1 = enable)");
1015 module_param_named(umsch_mm_fwlog, amdgpu_umsch_mm_fwlog, int, 0444);
1016
1017 /**
1018 * DOC: smu_pptable_id (int)
1019 * Used to override pptable id. id = 0 use VBIOS pptable.
1020 * id > 0 use the soft pptable with specicfied id.
1021 */
1022 MODULE_PARM_DESC(smu_pptable_id,
1023 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
1024 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
1025
1026 /**
1027 * DOC: partition_mode (int)
1028 * Used to override the default SPX mode.
1029 */
1030 MODULE_PARM_DESC(
1031 user_partt_mode,
1032 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \
1033 0 = AMDGPU_SPX_PARTITION_MODE, \
1034 1 = AMDGPU_DPX_PARTITION_MODE, \
1035 2 = AMDGPU_TPX_PARTITION_MODE, \
1036 3 = AMDGPU_QPX_PARTITION_MODE, \
1037 4 = AMDGPU_CPX_PARTITION_MODE)");
1038 module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444);
1039
1040
1041 /**
1042 * DOC: enforce_isolation (int)
1043 * enforce process isolation between graphics and compute.
1044 * (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader)
1045 */
1046 module_param_named(enforce_isolation, amdgpu_enforce_isolation, int, 0444);
1047 MODULE_PARM_DESC(enforce_isolation,
1048 "enforce process isolation between graphics and compute. (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader)");
1049
1050 /**
1051 * DOC: modeset (int)
1052 * Override nomodeset (1 = override, -1 = auto). The default is -1 (auto).
1053 */
1054 MODULE_PARM_DESC(modeset, "Override nomodeset (1 = enable, -1 = auto)");
1055 module_param_named(modeset, amdgpu_modeset, int, 0444);
1056
1057 /**
1058 * DOC: seamless (int)
1059 * Seamless boot will keep the image on the screen during the boot process.
1060 */
1061 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)");
1062 module_param_named(seamless, amdgpu_seamless, int, 0444);
1063
1064 /**
1065 * DOC: debug_mask (uint)
1066 * Debug options for amdgpu, work as a binary mask with the following options:
1067 *
1068 * - 0x1: Debug VM handling
1069 * - 0x2: Enable simulating large-bar capability on non-large bar system. This
1070 * limits the VRAM size reported to ROCm applications to the visible
1071 * size, usually 256MB.
1072 * - 0x4: Disable GPU soft recovery, always do a full reset
1073 * - 0x8: Use VRAM for firmware loading
1074 * - 0x10: Enable ACA based RAS logging
1075 * - 0x20: Enable experimental resets
1076 * - 0x40: Disable ring resets
1077 * - 0x80: Use VRAM for SMU pool
1078 */
1079 MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default");
1080 module_param_named_unsafe(debug_mask, amdgpu_debug_mask, uint, 0444);
1081
1082 /**
1083 * DOC: agp (int)
1084 * Enable the AGP aperture. This provides an aperture in the GPU's internal
1085 * address space for direct access to system memory. Note that these accesses
1086 * are non-snooped, so they are only used for access to uncached memory.
1087 */
1088 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)");
1089 module_param_named(agp, amdgpu_agp, int, 0444);
1090
1091 /**
1092 * DOC: wbrf (int)
1093 * Enable Wifi RFI interference mitigation feature.
1094 * Due to electrical and mechanical constraints there may be likely interference of
1095 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio
1096 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference,
1097 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based
1098 * on active list of frequencies in-use (to be avoided) as part of initial setting or
1099 * P-state transition. However, there may be potential performance impact with this
1100 * feature enabled.
1101 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported))
1102 */
1103 MODULE_PARM_DESC(wbrf,
1104 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)");
1105 module_param_named(wbrf, amdgpu_wbrf, int, 0444);
1106
1107 /**
1108 * DOC: rebar (int)
1109 * Allow BAR resizing. Disable this to prevent the driver from attempting
1110 * to resize the BAR if the GPU supports it and there is available MMIO space.
1111 * Note that this just prevents the driver from resizing the BAR. The BIOS
1112 * may have already resized the BAR at boot time.
1113 */
1114 MODULE_PARM_DESC(rebar, "Resizable BAR (-1 = auto (default), 0 = disable, 1 = enable)");
1115 module_param_named(rebar, amdgpu_rebar, int, 0444);
1116
1117 /**
1118 * DOC: user_queue (int)
1119 * Enable user queues on systems that support user queues. Possible values:
1120 *
1121 * - -1 = auto (ASIC specific default)
1122 * - 0 = user queues disabled
1123 * - 1 = user queues enabled and kernel queues enabled (if supported)
1124 * - 2 = user queues enabled and kernel queues disabled
1125 */
1126 MODULE_PARM_DESC(user_queue, "Enable user queues (-1 = auto (default), 0 = disable, 1 = enable, 2 = enable UQs and disable KQs)");
1127 module_param_named(user_queue, amdgpu_user_queue, int, 0444);
1128
1129 /* These devices are not supported by amdgpu.
1130 * They are supported by the mach64, r128, radeon drivers
1131 */
1132 static const u16 amdgpu_unsupported_pciidlist[] = {
1133 /* mach64 */
1134 0x4354,
1135 0x4358,
1136 0x4554,
1137 0x4742,
1138 0x4744,
1139 0x4749,
1140 0x474C,
1141 0x474D,
1142 0x474E,
1143 0x474F,
1144 0x4750,
1145 0x4751,
1146 0x4752,
1147 0x4753,
1148 0x4754,
1149 0x4755,
1150 0x4756,
1151 0x4757,
1152 0x4758,
1153 0x4759,
1154 0x475A,
1155 0x4C42,
1156 0x4C44,
1157 0x4C47,
1158 0x4C49,
1159 0x4C4D,
1160 0x4C4E,
1161 0x4C50,
1162 0x4C51,
1163 0x4C52,
1164 0x4C53,
1165 0x5654,
1166 0x5655,
1167 0x5656,
1168 /* r128 */
1169 0x4c45,
1170 0x4c46,
1171 0x4d46,
1172 0x4d4c,
1173 0x5041,
1174 0x5042,
1175 0x5043,
1176 0x5044,
1177 0x5045,
1178 0x5046,
1179 0x5047,
1180 0x5048,
1181 0x5049,
1182 0x504A,
1183 0x504B,
1184 0x504C,
1185 0x504D,
1186 0x504E,
1187 0x504F,
1188 0x5050,
1189 0x5051,
1190 0x5052,
1191 0x5053,
1192 0x5054,
1193 0x5055,
1194 0x5056,
1195 0x5057,
1196 0x5058,
1197 0x5245,
1198 0x5246,
1199 0x5247,
1200 0x524b,
1201 0x524c,
1202 0x534d,
1203 0x5446,
1204 0x544C,
1205 0x5452,
1206 /* radeon */
1207 0x3150,
1208 0x3151,
1209 0x3152,
1210 0x3154,
1211 0x3155,
1212 0x3E50,
1213 0x3E54,
1214 0x4136,
1215 0x4137,
1216 0x4144,
1217 0x4145,
1218 0x4146,
1219 0x4147,
1220 0x4148,
1221 0x4149,
1222 0x414A,
1223 0x414B,
1224 0x4150,
1225 0x4151,
1226 0x4152,
1227 0x4153,
1228 0x4154,
1229 0x4155,
1230 0x4156,
1231 0x4237,
1232 0x4242,
1233 0x4336,
1234 0x4337,
1235 0x4437,
1236 0x4966,
1237 0x4967,
1238 0x4A48,
1239 0x4A49,
1240 0x4A4A,
1241 0x4A4B,
1242 0x4A4C,
1243 0x4A4D,
1244 0x4A4E,
1245 0x4A4F,
1246 0x4A50,
1247 0x4A54,
1248 0x4B48,
1249 0x4B49,
1250 0x4B4A,
1251 0x4B4B,
1252 0x4B4C,
1253 0x4C57,
1254 0x4C58,
1255 0x4C59,
1256 0x4C5A,
1257 0x4C64,
1258 0x4C66,
1259 0x4C67,
1260 0x4E44,
1261 0x4E45,
1262 0x4E46,
1263 0x4E47,
1264 0x4E48,
1265 0x4E49,
1266 0x4E4A,
1267 0x4E4B,
1268 0x4E50,
1269 0x4E51,
1270 0x4E52,
1271 0x4E53,
1272 0x4E54,
1273 0x4E56,
1274 0x5144,
1275 0x5145,
1276 0x5146,
1277 0x5147,
1278 0x5148,
1279 0x514C,
1280 0x514D,
1281 0x5157,
1282 0x5158,
1283 0x5159,
1284 0x515A,
1285 0x515E,
1286 0x5460,
1287 0x5462,
1288 0x5464,
1289 0x5548,
1290 0x5549,
1291 0x554A,
1292 0x554B,
1293 0x554C,
1294 0x554D,
1295 0x554E,
1296 0x554F,
1297 0x5550,
1298 0x5551,
1299 0x5552,
1300 0x5554,
1301 0x564A,
1302 0x564B,
1303 0x564F,
1304 0x5652,
1305 0x5653,
1306 0x5657,
1307 0x5834,
1308 0x5835,
1309 0x5954,
1310 0x5955,
1311 0x5974,
1312 0x5975,
1313 0x5960,
1314 0x5961,
1315 0x5962,
1316 0x5964,
1317 0x5965,
1318 0x5969,
1319 0x5a41,
1320 0x5a42,
1321 0x5a61,
1322 0x5a62,
1323 0x5b60,
1324 0x5b62,
1325 0x5b63,
1326 0x5b64,
1327 0x5b65,
1328 0x5c61,
1329 0x5c63,
1330 0x5d48,
1331 0x5d49,
1332 0x5d4a,
1333 0x5d4c,
1334 0x5d4d,
1335 0x5d4e,
1336 0x5d4f,
1337 0x5d50,
1338 0x5d52,
1339 0x5d57,
1340 0x5e48,
1341 0x5e4a,
1342 0x5e4b,
1343 0x5e4c,
1344 0x5e4d,
1345 0x5e4f,
1346 0x6700,
1347 0x6701,
1348 0x6702,
1349 0x6703,
1350 0x6704,
1351 0x6705,
1352 0x6706,
1353 0x6707,
1354 0x6708,
1355 0x6709,
1356 0x6718,
1357 0x6719,
1358 0x671c,
1359 0x671d,
1360 0x671f,
1361 0x6720,
1362 0x6721,
1363 0x6722,
1364 0x6723,
1365 0x6724,
1366 0x6725,
1367 0x6726,
1368 0x6727,
1369 0x6728,
1370 0x6729,
1371 0x6738,
1372 0x6739,
1373 0x673e,
1374 0x6740,
1375 0x6741,
1376 0x6742,
1377 0x6743,
1378 0x6744,
1379 0x6745,
1380 0x6746,
1381 0x6747,
1382 0x6748,
1383 0x6749,
1384 0x674A,
1385 0x6750,
1386 0x6751,
1387 0x6758,
1388 0x6759,
1389 0x675B,
1390 0x675D,
1391 0x675F,
1392 0x6760,
1393 0x6761,
1394 0x6762,
1395 0x6763,
1396 0x6764,
1397 0x6765,
1398 0x6766,
1399 0x6767,
1400 0x6768,
1401 0x6770,
1402 0x6771,
1403 0x6772,
1404 0x6778,
1405 0x6779,
1406 0x677B,
1407 0x6840,
1408 0x6841,
1409 0x6842,
1410 0x6843,
1411 0x6849,
1412 0x684C,
1413 0x6850,
1414 0x6858,
1415 0x6859,
1416 0x6880,
1417 0x6888,
1418 0x6889,
1419 0x688A,
1420 0x688C,
1421 0x688D,
1422 0x6898,
1423 0x6899,
1424 0x689b,
1425 0x689c,
1426 0x689d,
1427 0x689e,
1428 0x68a0,
1429 0x68a1,
1430 0x68a8,
1431 0x68a9,
1432 0x68b0,
1433 0x68b8,
1434 0x68b9,
1435 0x68ba,
1436 0x68be,
1437 0x68bf,
1438 0x68c0,
1439 0x68c1,
1440 0x68c7,
1441 0x68c8,
1442 0x68c9,
1443 0x68d8,
1444 0x68d9,
1445 0x68da,
1446 0x68de,
1447 0x68e0,
1448 0x68e1,
1449 0x68e4,
1450 0x68e5,
1451 0x68e8,
1452 0x68e9,
1453 0x68f1,
1454 0x68f2,
1455 0x68f8,
1456 0x68f9,
1457 0x68fa,
1458 0x68fe,
1459 0x7100,
1460 0x7101,
1461 0x7102,
1462 0x7103,
1463 0x7104,
1464 0x7105,
1465 0x7106,
1466 0x7108,
1467 0x7109,
1468 0x710A,
1469 0x710B,
1470 0x710C,
1471 0x710E,
1472 0x710F,
1473 0x7140,
1474 0x7141,
1475 0x7142,
1476 0x7143,
1477 0x7144,
1478 0x7145,
1479 0x7146,
1480 0x7147,
1481 0x7149,
1482 0x714A,
1483 0x714B,
1484 0x714C,
1485 0x714D,
1486 0x714E,
1487 0x714F,
1488 0x7151,
1489 0x7152,
1490 0x7153,
1491 0x715E,
1492 0x715F,
1493 0x7180,
1494 0x7181,
1495 0x7183,
1496 0x7186,
1497 0x7187,
1498 0x7188,
1499 0x718A,
1500 0x718B,
1501 0x718C,
1502 0x718D,
1503 0x718F,
1504 0x7193,
1505 0x7196,
1506 0x719B,
1507 0x719F,
1508 0x71C0,
1509 0x71C1,
1510 0x71C2,
1511 0x71C3,
1512 0x71C4,
1513 0x71C5,
1514 0x71C6,
1515 0x71C7,
1516 0x71CD,
1517 0x71CE,
1518 0x71D2,
1519 0x71D4,
1520 0x71D5,
1521 0x71D6,
1522 0x71DA,
1523 0x71DE,
1524 0x7200,
1525 0x7210,
1526 0x7211,
1527 0x7240,
1528 0x7243,
1529 0x7244,
1530 0x7245,
1531 0x7246,
1532 0x7247,
1533 0x7248,
1534 0x7249,
1535 0x724A,
1536 0x724B,
1537 0x724C,
1538 0x724D,
1539 0x724E,
1540 0x724F,
1541 0x7280,
1542 0x7281,
1543 0x7283,
1544 0x7284,
1545 0x7287,
1546 0x7288,
1547 0x7289,
1548 0x728B,
1549 0x728C,
1550 0x7290,
1551 0x7291,
1552 0x7293,
1553 0x7297,
1554 0x7834,
1555 0x7835,
1556 0x791e,
1557 0x791f,
1558 0x793f,
1559 0x7941,
1560 0x7942,
1561 0x796c,
1562 0x796d,
1563 0x796e,
1564 0x796f,
1565 0x9400,
1566 0x9401,
1567 0x9402,
1568 0x9403,
1569 0x9405,
1570 0x940A,
1571 0x940B,
1572 0x940F,
1573 0x94A0,
1574 0x94A1,
1575 0x94A3,
1576 0x94B1,
1577 0x94B3,
1578 0x94B4,
1579 0x94B5,
1580 0x94B9,
1581 0x9440,
1582 0x9441,
1583 0x9442,
1584 0x9443,
1585 0x9444,
1586 0x9446,
1587 0x944A,
1588 0x944B,
1589 0x944C,
1590 0x944E,
1591 0x9450,
1592 0x9452,
1593 0x9456,
1594 0x945A,
1595 0x945B,
1596 0x945E,
1597 0x9460,
1598 0x9462,
1599 0x946A,
1600 0x946B,
1601 0x947A,
1602 0x947B,
1603 0x9480,
1604 0x9487,
1605 0x9488,
1606 0x9489,
1607 0x948A,
1608 0x948F,
1609 0x9490,
1610 0x9491,
1611 0x9495,
1612 0x9498,
1613 0x949C,
1614 0x949E,
1615 0x949F,
1616 0x94C0,
1617 0x94C1,
1618 0x94C3,
1619 0x94C4,
1620 0x94C5,
1621 0x94C6,
1622 0x94C7,
1623 0x94C8,
1624 0x94C9,
1625 0x94CB,
1626 0x94CC,
1627 0x94CD,
1628 0x9500,
1629 0x9501,
1630 0x9504,
1631 0x9505,
1632 0x9506,
1633 0x9507,
1634 0x9508,
1635 0x9509,
1636 0x950F,
1637 0x9511,
1638 0x9515,
1639 0x9517,
1640 0x9519,
1641 0x9540,
1642 0x9541,
1643 0x9542,
1644 0x954E,
1645 0x954F,
1646 0x9552,
1647 0x9553,
1648 0x9555,
1649 0x9557,
1650 0x955f,
1651 0x9580,
1652 0x9581,
1653 0x9583,
1654 0x9586,
1655 0x9587,
1656 0x9588,
1657 0x9589,
1658 0x958A,
1659 0x958B,
1660 0x958C,
1661 0x958D,
1662 0x958E,
1663 0x958F,
1664 0x9590,
1665 0x9591,
1666 0x9593,
1667 0x9595,
1668 0x9596,
1669 0x9597,
1670 0x9598,
1671 0x9599,
1672 0x959B,
1673 0x95C0,
1674 0x95C2,
1675 0x95C4,
1676 0x95C5,
1677 0x95C6,
1678 0x95C7,
1679 0x95C9,
1680 0x95CC,
1681 0x95CD,
1682 0x95CE,
1683 0x95CF,
1684 0x9610,
1685 0x9611,
1686 0x9612,
1687 0x9613,
1688 0x9614,
1689 0x9615,
1690 0x9616,
1691 0x9640,
1692 0x9641,
1693 0x9642,
1694 0x9643,
1695 0x9644,
1696 0x9645,
1697 0x9647,
1698 0x9648,
1699 0x9649,
1700 0x964a,
1701 0x964b,
1702 0x964c,
1703 0x964e,
1704 0x964f,
1705 0x9710,
1706 0x9711,
1707 0x9712,
1708 0x9713,
1709 0x9714,
1710 0x9715,
1711 0x9802,
1712 0x9803,
1713 0x9804,
1714 0x9805,
1715 0x9806,
1716 0x9807,
1717 0x9808,
1718 0x9809,
1719 0x980A,
1720 0x9900,
1721 0x9901,
1722 0x9903,
1723 0x9904,
1724 0x9905,
1725 0x9906,
1726 0x9907,
1727 0x9908,
1728 0x9909,
1729 0x990A,
1730 0x990B,
1731 0x990C,
1732 0x990D,
1733 0x990E,
1734 0x990F,
1735 0x9910,
1736 0x9913,
1737 0x9917,
1738 0x9918,
1739 0x9919,
1740 0x9990,
1741 0x9991,
1742 0x9992,
1743 0x9993,
1744 0x9994,
1745 0x9995,
1746 0x9996,
1747 0x9997,
1748 0x9998,
1749 0x9999,
1750 0x999A,
1751 0x999B,
1752 0x999C,
1753 0x999D,
1754 0x99A0,
1755 0x99A2,
1756 0x99A4,
1757 /* radeon secondary ids */
1758 0x3171,
1759 0x3e70,
1760 0x4164,
1761 0x4165,
1762 0x4166,
1763 0x4168,
1764 0x4170,
1765 0x4171,
1766 0x4172,
1767 0x4173,
1768 0x496e,
1769 0x4a69,
1770 0x4a6a,
1771 0x4a6b,
1772 0x4a70,
1773 0x4a74,
1774 0x4b69,
1775 0x4b6b,
1776 0x4b6c,
1777 0x4c6e,
1778 0x4e64,
1779 0x4e65,
1780 0x4e66,
1781 0x4e67,
1782 0x4e68,
1783 0x4e69,
1784 0x4e6a,
1785 0x4e71,
1786 0x4f73,
1787 0x5569,
1788 0x556b,
1789 0x556d,
1790 0x556f,
1791 0x5571,
1792 0x5854,
1793 0x5874,
1794 0x5940,
1795 0x5941,
1796 0x5b70,
1797 0x5b72,
1798 0x5b73,
1799 0x5b74,
1800 0x5b75,
1801 0x5d44,
1802 0x5d45,
1803 0x5d6d,
1804 0x5d6f,
1805 0x5d72,
1806 0x5d77,
1807 0x5e6b,
1808 0x5e6d,
1809 0x7120,
1810 0x7124,
1811 0x7129,
1812 0x712e,
1813 0x712f,
1814 0x7162,
1815 0x7163,
1816 0x7166,
1817 0x7167,
1818 0x7172,
1819 0x7173,
1820 0x71a0,
1821 0x71a1,
1822 0x71a3,
1823 0x71a7,
1824 0x71bb,
1825 0x71e0,
1826 0x71e1,
1827 0x71e2,
1828 0x71e6,
1829 0x71e7,
1830 0x71f2,
1831 0x7269,
1832 0x726b,
1833 0x726e,
1834 0x72a0,
1835 0x72a8,
1836 0x72b1,
1837 0x72b3,
1838 0x793f,
1839 };
1840
1841 static const struct pci_device_id pciidlist[] = {
1842 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1843 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1844 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1845 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1846 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1847 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1848 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1849 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1850 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1851 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1852 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1853 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1854 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1855 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1856 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1857 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1858 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1859 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1860 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1861 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1862 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1863 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1864 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1865 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1866 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1867 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1868 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1869 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1870 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1871 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1872 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1873 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1874 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1875 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1876 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1877 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1878 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1879 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1880 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1881 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1882 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1883 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1884 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1885 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1886 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1887 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1888 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1889 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1890 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1891 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1892 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1893 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1894 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1895 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1896 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1897 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1898 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1899 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1900 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1901 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1902 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1903 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1904 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1905 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1906 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1907 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1908 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1909 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1910 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1911 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1912 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1913 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1914 /* Kaveri */
1915 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1916 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1917 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1918 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1919 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1920 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1921 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1922 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1923 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1924 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1925 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1926 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1927 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1928 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1929 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1930 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1931 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1932 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1933 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1934 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1935 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1936 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1937 /* Bonaire */
1938 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1939 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1940 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1941 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1942 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1943 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1944 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1945 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1946 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1947 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1948 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1949 /* Hawaii */
1950 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1951 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1952 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1953 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1954 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1955 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1956 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1957 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1958 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1959 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1960 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1961 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1962 /* Kabini */
1963 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1964 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1965 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1966 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1967 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1968 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1969 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1970 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1971 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1972 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1973 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1974 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1975 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1976 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1977 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1978 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1979 /* mullins */
1980 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1981 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1982 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1983 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1984 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1985 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1986 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1987 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1988 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1989 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1990 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1991 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1992 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1993 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1994 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1995 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1996 /* topaz */
1997 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1998 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1999 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
2000 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
2001 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
2002 /* tonga */
2003 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2004 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2005 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2006 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2007 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2008 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2009 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2010 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2011 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2012 /* fiji */
2013 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
2014 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
2015 /* carrizo */
2016 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
2017 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
2018 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
2019 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
2020 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
2021 /* stoney */
2022 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
2023 /* Polaris11 */
2024 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2025 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2026 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2027 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2028 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2029 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2030 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2031 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2032 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2033 /* Polaris10 */
2034 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2035 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2036 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2037 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2038 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2039 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2040 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2041 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2042 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2043 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2044 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2045 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2046 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2047 /* Polaris12 */
2048 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2049 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2050 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2051 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2052 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2053 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2054 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2055 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
2056 /* VEGAM */
2057 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
2058 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
2059 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
2060 /* Vega 10 */
2061 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2062 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2063 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2064 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2065 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2066 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2067 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2068 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2069 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2070 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2071 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2072 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2073 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2074 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2075 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2076 /* Vega 12 */
2077 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
2078 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
2079 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
2080 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
2081 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
2082 /* Vega 20 */
2083 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
2084 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
2085 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
2086 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
2087 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
2088 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
2089 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
2090 /* Raven */
2091 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
2092 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
2093 /* Arcturus */
2094 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
2095 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
2096 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
2097 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
2098 /* Navi10 */
2099 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2100 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2101 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2102 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2103 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2104 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2105 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2106 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2107 /* Navi14 */
2108 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
2109 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
2110 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
2111 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
2112
2113 /* Renoir */
2114 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
2115 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
2116 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
2117 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
2118
2119 /* Navi12 */
2120 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
2121 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
2122
2123 /* Sienna_Cichlid */
2124 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2125 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2126 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2127 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2128 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2129 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2130 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2131 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2132 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2133 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2134 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2135 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2136 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2137
2138 /* Yellow Carp */
2139 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
2140 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
2141
2142 /* Navy_Flounder */
2143 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2144 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2145 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2146 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2147 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2148 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2149 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2150 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2151 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2152
2153 /* DIMGREY_CAVEFISH */
2154 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2155 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2156 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2157 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2158 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2159 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2160 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2161 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2162 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2163 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2164 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2165 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2166
2167 /* Aldebaran */
2168 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2169 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2170 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2171 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2172
2173 /* CYAN_SKILLFISH */
2174 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2175 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2176
2177 /* BEIGE_GOBY */
2178 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2179 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2180 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2181 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2182 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2183 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2184
2185 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2186 .class = PCI_CLASS_DISPLAY_VGA << 8,
2187 .class_mask = 0xffffff,
2188 .driver_data = CHIP_IP_DISCOVERY },
2189
2190 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2191 .class = PCI_CLASS_DISPLAY_OTHER << 8,
2192 .class_mask = 0xffffff,
2193 .driver_data = CHIP_IP_DISCOVERY },
2194
2195 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2196 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8,
2197 .class_mask = 0xffffff,
2198 .driver_data = CHIP_IP_DISCOVERY },
2199
2200 {0, 0, 0}
2201 };
2202
2203 MODULE_DEVICE_TABLE(pci, pciidlist);
2204
2205 static const struct amdgpu_asic_type_quirk asic_type_quirks[] = {
2206 /* differentiate between P10 and P11 asics with the same DID */
2207 {0x67FF, 0xE3, CHIP_POLARIS10},
2208 {0x67FF, 0xE7, CHIP_POLARIS10},
2209 {0x67FF, 0xF3, CHIP_POLARIS10},
2210 {0x67FF, 0xF7, CHIP_POLARIS10},
2211 };
2212
2213 static const struct drm_driver amdgpu_kms_driver;
2214
amdgpu_get_secondary_funcs(struct amdgpu_device * adev)2215 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
2216 {
2217 struct pci_dev *p = NULL;
2218 int i;
2219
2220 /* 0 - GPU
2221 * 1 - audio
2222 * 2 - USB
2223 * 3 - UCSI
2224 */
2225 for (i = 1; i < 4; i++) {
2226 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
2227 adev->pdev->bus->number, i);
2228 if (p) {
2229 pm_runtime_get_sync(&p->dev);
2230 pm_runtime_mark_last_busy(&p->dev);
2231 pm_runtime_put_autosuspend(&p->dev);
2232 pci_dev_put(p);
2233 }
2234 }
2235 }
2236
amdgpu_init_debug_options(struct amdgpu_device * adev)2237 static void amdgpu_init_debug_options(struct amdgpu_device *adev)
2238 {
2239 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) {
2240 pr_info("debug: VM handling debug enabled\n");
2241 adev->debug_vm = true;
2242 }
2243
2244 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) {
2245 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n");
2246 adev->debug_largebar = true;
2247 }
2248
2249 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) {
2250 pr_info("debug: soft reset for GPU recovery disabled\n");
2251 adev->debug_disable_soft_recovery = true;
2252 }
2253
2254 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) {
2255 pr_info("debug: place fw in vram for frontdoor loading\n");
2256 adev->debug_use_vram_fw_buf = true;
2257 }
2258
2259 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) {
2260 pr_info("debug: enable RAS ACA\n");
2261 adev->debug_enable_ras_aca = true;
2262 }
2263
2264 if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) {
2265 pr_info("debug: enable experimental reset features\n");
2266 adev->debug_exp_resets = true;
2267 }
2268
2269 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_RING_RESET) {
2270 pr_info("debug: ring reset disabled\n");
2271 adev->debug_disable_gpu_ring_reset = true;
2272 }
2273 if (amdgpu_debug_mask & AMDGPU_DEBUG_SMU_POOL) {
2274 pr_info("debug: use vram for smu pool\n");
2275 adev->pm.smu_debug_mask |= SMU_DEBUG_POOL_USE_VRAM;
2276 }
2277 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM_USERPTR) {
2278 pr_info("debug: VM mode debug for userptr is enabled\n");
2279 adev->debug_vm_userptr = true;
2280 }
2281 }
2282
amdgpu_fix_asic_type(struct pci_dev * pdev,unsigned long flags)2283 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags)
2284 {
2285 int i;
2286
2287 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) {
2288 if (pdev->device == asic_type_quirks[i].device &&
2289 pdev->revision == asic_type_quirks[i].revision) {
2290 flags &= ~AMD_ASIC_MASK;
2291 flags |= asic_type_quirks[i].type;
2292 break;
2293 }
2294 }
2295
2296 return flags;
2297 }
2298
amdgpu_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)2299 static int amdgpu_pci_probe(struct pci_dev *pdev,
2300 const struct pci_device_id *ent)
2301 {
2302 struct drm_device *ddev;
2303 struct amdgpu_device *adev;
2304 unsigned long flags = ent->driver_data;
2305 int ret, retry = 0, i;
2306 bool supports_atomic = false;
2307
2308 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA ||
2309 (pdev->class >> 8) == PCI_CLASS_DISPLAY_OTHER) {
2310 if (drm_firmware_drivers_only() && amdgpu_modeset == -1)
2311 return -EINVAL;
2312 }
2313
2314 /* skip devices which are owned by radeon */
2315 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
2316 if (amdgpu_unsupported_pciidlist[i] == pdev->device)
2317 return -ENODEV;
2318 }
2319
2320 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))
2321 amdgpu_aspm = 0;
2322
2323 if (amdgpu_virtual_display ||
2324 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
2325 supports_atomic = true;
2326
2327 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
2328 DRM_INFO("This hardware requires experimental hardware support.\n"
2329 "See modparam exp_hw_support\n");
2330 return -ENODEV;
2331 }
2332
2333 flags = amdgpu_fix_asic_type(pdev, flags);
2334
2335 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
2336 * however, SME requires an indirect IOMMU mapping because the encryption
2337 * bit is beyond the DMA mask of the chip.
2338 */
2339 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
2340 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
2341 dev_info(&pdev->dev,
2342 "SME is not compatible with RAVEN\n");
2343 return -ENOTSUPP;
2344 }
2345
2346 switch (flags & AMD_ASIC_MASK) {
2347 case CHIP_TAHITI:
2348 case CHIP_PITCAIRN:
2349 case CHIP_VERDE:
2350 case CHIP_OLAND:
2351 case CHIP_HAINAN:
2352 #ifdef CONFIG_DRM_AMDGPU_SI
2353 if (!amdgpu_si_support) {
2354 dev_info(&pdev->dev,
2355 "SI support provided by radeon.\n");
2356 dev_info(&pdev->dev,
2357 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
2358 );
2359 return -ENODEV;
2360 }
2361 break;
2362 #else
2363 dev_info(&pdev->dev, "amdgpu is built without SI support.\n");
2364 return -ENODEV;
2365 #endif
2366 case CHIP_KAVERI:
2367 case CHIP_BONAIRE:
2368 case CHIP_HAWAII:
2369 case CHIP_KABINI:
2370 case CHIP_MULLINS:
2371 #ifdef CONFIG_DRM_AMDGPU_CIK
2372 if (!amdgpu_cik_support) {
2373 dev_info(&pdev->dev,
2374 "CIK support provided by radeon.\n");
2375 dev_info(&pdev->dev,
2376 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
2377 );
2378 return -ENODEV;
2379 }
2380 break;
2381 #else
2382 dev_info(&pdev->dev, "amdgpu is built without CIK support.\n");
2383 return -ENODEV;
2384 #endif
2385 default:
2386 break;
2387 }
2388
2389 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
2390 if (IS_ERR(adev))
2391 return PTR_ERR(adev);
2392
2393 adev->dev = &pdev->dev;
2394 adev->pdev = pdev;
2395 ddev = adev_to_drm(adev);
2396
2397 if (!supports_atomic)
2398 ddev->driver_features &= ~DRIVER_ATOMIC;
2399
2400 ret = pci_enable_device(pdev);
2401 if (ret)
2402 return ret;
2403
2404 pci_set_drvdata(pdev, ddev);
2405
2406 amdgpu_init_debug_options(adev);
2407
2408 ret = amdgpu_driver_load_kms(adev, flags);
2409 if (ret)
2410 goto err_pci;
2411
2412 retry_init:
2413 ret = drm_dev_register(ddev, flags);
2414 if (ret == -EAGAIN && ++retry <= 3) {
2415 DRM_INFO("retry init %d\n", retry);
2416 /* Don't request EX mode too frequently which is attacking */
2417 msleep(5000);
2418 goto retry_init;
2419 } else if (ret) {
2420 goto err_pci;
2421 }
2422
2423 ret = amdgpu_xcp_dev_register(adev, ent);
2424 if (ret)
2425 goto err_pci;
2426
2427 ret = amdgpu_amdkfd_drm_client_create(adev);
2428 if (ret)
2429 goto err_pci;
2430
2431 /*
2432 * 1. don't init fbdev on hw without DCE
2433 * 2. don't init fbdev if there are no connectors
2434 */
2435 if (adev->mode_info.mode_config_initialized &&
2436 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
2437 const struct drm_format_info *format;
2438
2439 /* select 8 bpp console on low vram cards */
2440 if (adev->gmc.real_vram_size <= (32*1024*1024))
2441 format = drm_format_info(DRM_FORMAT_C8);
2442 else
2443 format = NULL;
2444
2445 drm_client_setup(adev_to_drm(adev), format);
2446 }
2447
2448 ret = amdgpu_debugfs_init(adev);
2449 if (ret)
2450 DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
2451
2452 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2453 /* only need to skip on ATPX */
2454 if (amdgpu_device_supports_px(ddev))
2455 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
2456 /* we want direct complete for BOCO */
2457 if (amdgpu_device_supports_boco(ddev))
2458 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE |
2459 DPM_FLAG_SMART_SUSPEND |
2460 DPM_FLAG_MAY_SKIP_RESUME);
2461 pm_runtime_use_autosuspend(ddev->dev);
2462 pm_runtime_set_autosuspend_delay(ddev->dev, 5000);
2463
2464 pm_runtime_allow(ddev->dev);
2465
2466 pm_runtime_mark_last_busy(ddev->dev);
2467 pm_runtime_put_autosuspend(ddev->dev);
2468
2469 pci_wake_from_d3(pdev, TRUE);
2470
2471 /*
2472 * For runpm implemented via BACO, PMFW will handle the
2473 * timing for BACO in and out:
2474 * - put ASIC into BACO state only when both video and
2475 * audio functions are in D3 state.
2476 * - pull ASIC out of BACO state when either video or
2477 * audio function is in D0 state.
2478 * Also, at startup, PMFW assumes both functions are in
2479 * D0 state.
2480 *
2481 * So if snd driver was loaded prior to amdgpu driver
2482 * and audio function was put into D3 state, there will
2483 * be no PMFW-aware D-state transition(D0->D3) on runpm
2484 * suspend. Thus the BACO will be not correctly kicked in.
2485 *
2486 * Via amdgpu_get_secondary_funcs(), the audio dev is put
2487 * into D0 state. Then there will be a PMFW-aware D-state
2488 * transition(D0->D3) on runpm suspend.
2489 */
2490 if (amdgpu_device_supports_baco(ddev) &&
2491 !(adev->flags & AMD_IS_APU) &&
2492 (adev->asic_type >= CHIP_NAVI10))
2493 amdgpu_get_secondary_funcs(adev);
2494 }
2495
2496 return 0;
2497
2498 err_pci:
2499 pci_disable_device(pdev);
2500 return ret;
2501 }
2502
2503 static void
amdgpu_pci_remove(struct pci_dev * pdev)2504 amdgpu_pci_remove(struct pci_dev *pdev)
2505 {
2506 struct drm_device *dev = pci_get_drvdata(pdev);
2507 struct amdgpu_device *adev = drm_to_adev(dev);
2508
2509 amdgpu_xcp_dev_unplug(adev);
2510 amdgpu_gmc_prepare_nps_mode_change(adev);
2511 drm_dev_unplug(dev);
2512
2513 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2514 pm_runtime_get_sync(dev->dev);
2515 pm_runtime_forbid(dev->dev);
2516 }
2517
2518 amdgpu_driver_unload_kms(dev);
2519
2520 /*
2521 * Flush any in flight DMA operations from device.
2522 * Clear the Bus Master Enable bit and then wait on the PCIe Device
2523 * StatusTransactions Pending bit.
2524 */
2525 pci_disable_device(pdev);
2526 pci_wait_for_pending_transaction(pdev);
2527 }
2528
2529 static void
amdgpu_pci_shutdown(struct pci_dev * pdev)2530 amdgpu_pci_shutdown(struct pci_dev *pdev)
2531 {
2532 struct drm_device *dev = pci_get_drvdata(pdev);
2533 struct amdgpu_device *adev = drm_to_adev(dev);
2534
2535 if (amdgpu_ras_intr_triggered())
2536 return;
2537
2538 /* if we are running in a VM, make sure the device
2539 * torn down properly on reboot/shutdown.
2540 * unfortunately we can't detect certain
2541 * hypervisors so just do this all the time.
2542 */
2543 if (!amdgpu_passthrough(adev))
2544 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2545 amdgpu_device_ip_suspend(adev);
2546 adev->mp1_state = PP_MP1_STATE_NONE;
2547 }
2548
amdgpu_pmops_prepare(struct device * dev)2549 static int amdgpu_pmops_prepare(struct device *dev)
2550 {
2551 struct drm_device *drm_dev = dev_get_drvdata(dev);
2552 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2553
2554 /* Return a positive number here so
2555 * DPM_FLAG_SMART_SUSPEND works properly
2556 */
2557 if (amdgpu_device_supports_boco(drm_dev) &&
2558 pm_runtime_suspended(dev))
2559 return 1;
2560
2561 /* if we will not support s3 or s2i for the device
2562 * then skip suspend
2563 */
2564 if (!amdgpu_acpi_is_s0ix_active(adev) &&
2565 !amdgpu_acpi_is_s3_active(adev))
2566 return 1;
2567
2568 return amdgpu_device_prepare(drm_dev);
2569 }
2570
amdgpu_pmops_complete(struct device * dev)2571 static void amdgpu_pmops_complete(struct device *dev)
2572 {
2573 /* nothing to do */
2574 }
2575
amdgpu_pmops_suspend(struct device * dev)2576 static int amdgpu_pmops_suspend(struct device *dev)
2577 {
2578 struct drm_device *drm_dev = dev_get_drvdata(dev);
2579 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2580
2581 if (amdgpu_acpi_is_s0ix_active(adev))
2582 adev->in_s0ix = true;
2583 else if (amdgpu_acpi_is_s3_active(adev))
2584 adev->in_s3 = true;
2585 if (!adev->in_s0ix && !adev->in_s3) {
2586 /* don't allow going deep first time followed by s2idle the next time */
2587 if (adev->last_suspend_state != PM_SUSPEND_ON &&
2588 adev->last_suspend_state != pm_suspend_target_state) {
2589 drm_err_once(drm_dev, "Unsupported suspend state %d\n",
2590 pm_suspend_target_state);
2591 return -EINVAL;
2592 }
2593 return 0;
2594 }
2595
2596 /* cache the state last used for suspend */
2597 adev->last_suspend_state = pm_suspend_target_state;
2598
2599 return amdgpu_device_suspend(drm_dev, true);
2600 }
2601
amdgpu_pmops_suspend_noirq(struct device * dev)2602 static int amdgpu_pmops_suspend_noirq(struct device *dev)
2603 {
2604 struct drm_device *drm_dev = dev_get_drvdata(dev);
2605 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2606
2607 if (amdgpu_acpi_should_gpu_reset(adev))
2608 return amdgpu_asic_reset(adev);
2609
2610 return 0;
2611 }
2612
amdgpu_pmops_resume(struct device * dev)2613 static int amdgpu_pmops_resume(struct device *dev)
2614 {
2615 struct drm_device *drm_dev = dev_get_drvdata(dev);
2616 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2617 int r;
2618
2619 if (!adev->in_s0ix && !adev->in_s3)
2620 return 0;
2621
2622 /* Avoids registers access if device is physically gone */
2623 if (!pci_device_is_present(adev->pdev))
2624 adev->no_hw_access = true;
2625
2626 r = amdgpu_device_resume(drm_dev, true);
2627 if (amdgpu_acpi_is_s0ix_active(adev))
2628 adev->in_s0ix = false;
2629 else
2630 adev->in_s3 = false;
2631 return r;
2632 }
2633
amdgpu_pmops_freeze(struct device * dev)2634 static int amdgpu_pmops_freeze(struct device *dev)
2635 {
2636 struct drm_device *drm_dev = dev_get_drvdata(dev);
2637 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2638 int r;
2639
2640 r = amdgpu_device_suspend(drm_dev, true);
2641 if (r)
2642 return r;
2643
2644 if (amdgpu_acpi_should_gpu_reset(adev))
2645 return amdgpu_asic_reset(adev);
2646 return 0;
2647 }
2648
amdgpu_pmops_thaw(struct device * dev)2649 static int amdgpu_pmops_thaw(struct device *dev)
2650 {
2651 struct drm_device *drm_dev = dev_get_drvdata(dev);
2652
2653 return amdgpu_device_resume(drm_dev, true);
2654 }
2655
amdgpu_pmops_poweroff(struct device * dev)2656 static int amdgpu_pmops_poweroff(struct device *dev)
2657 {
2658 struct drm_device *drm_dev = dev_get_drvdata(dev);
2659
2660 return amdgpu_device_suspend(drm_dev, true);
2661 }
2662
amdgpu_pmops_restore(struct device * dev)2663 static int amdgpu_pmops_restore(struct device *dev)
2664 {
2665 struct drm_device *drm_dev = dev_get_drvdata(dev);
2666
2667 return amdgpu_device_resume(drm_dev, true);
2668 }
2669
amdgpu_runtime_idle_check_display(struct device * dev)2670 static int amdgpu_runtime_idle_check_display(struct device *dev)
2671 {
2672 struct pci_dev *pdev = to_pci_dev(dev);
2673 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2674 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2675
2676 if (adev->mode_info.num_crtc) {
2677 struct drm_connector *list_connector;
2678 struct drm_connector_list_iter iter;
2679 int ret = 0;
2680
2681 if (amdgpu_runtime_pm != -2) {
2682 /* XXX: Return busy if any displays are connected to avoid
2683 * possible display wakeups after runtime resume due to
2684 * hotplug events in case any displays were connected while
2685 * the GPU was in suspend. Remove this once that is fixed.
2686 */
2687 mutex_lock(&drm_dev->mode_config.mutex);
2688 drm_connector_list_iter_begin(drm_dev, &iter);
2689 drm_for_each_connector_iter(list_connector, &iter) {
2690 if (list_connector->status == connector_status_connected) {
2691 ret = -EBUSY;
2692 break;
2693 }
2694 }
2695 drm_connector_list_iter_end(&iter);
2696 mutex_unlock(&drm_dev->mode_config.mutex);
2697
2698 if (ret)
2699 return ret;
2700 }
2701
2702 if (adev->dc_enabled) {
2703 struct drm_crtc *crtc;
2704
2705 drm_for_each_crtc(crtc, drm_dev) {
2706 drm_modeset_lock(&crtc->mutex, NULL);
2707 if (crtc->state->active)
2708 ret = -EBUSY;
2709 drm_modeset_unlock(&crtc->mutex);
2710 if (ret < 0)
2711 break;
2712 }
2713 } else {
2714 mutex_lock(&drm_dev->mode_config.mutex);
2715 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2716
2717 drm_connector_list_iter_begin(drm_dev, &iter);
2718 drm_for_each_connector_iter(list_connector, &iter) {
2719 if (list_connector->dpms == DRM_MODE_DPMS_ON) {
2720 ret = -EBUSY;
2721 break;
2722 }
2723 }
2724
2725 drm_connector_list_iter_end(&iter);
2726
2727 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2728 mutex_unlock(&drm_dev->mode_config.mutex);
2729 }
2730 if (ret)
2731 return ret;
2732 }
2733
2734 return 0;
2735 }
2736
amdgpu_runtime_idle_check_userq(struct device * dev)2737 static int amdgpu_runtime_idle_check_userq(struct device *dev)
2738 {
2739 struct pci_dev *pdev = to_pci_dev(dev);
2740 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2741 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2742 struct amdgpu_usermode_queue *queue;
2743 struct amdgpu_userq_mgr *uqm, *tmp;
2744 int queue_id;
2745 int ret = 0;
2746
2747 mutex_lock(&adev->userq_mutex);
2748 list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) {
2749 idr_for_each_entry(&uqm->userq_idr, queue, queue_id) {
2750 ret = -EBUSY;
2751 goto done;
2752 }
2753 }
2754 done:
2755 mutex_unlock(&adev->userq_mutex);
2756
2757 return ret;
2758 }
2759
amdgpu_pmops_runtime_suspend(struct device * dev)2760 static int amdgpu_pmops_runtime_suspend(struct device *dev)
2761 {
2762 struct pci_dev *pdev = to_pci_dev(dev);
2763 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2764 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2765 int ret, i;
2766
2767 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2768 pm_runtime_forbid(dev);
2769 return -EBUSY;
2770 }
2771
2772 ret = amdgpu_runtime_idle_check_display(dev);
2773 if (ret)
2774 return ret;
2775 ret = amdgpu_runtime_idle_check_userq(dev);
2776 if (ret)
2777 return ret;
2778
2779 /* wait for all rings to drain before suspending */
2780 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2781 struct amdgpu_ring *ring = adev->rings[i];
2782
2783 if (ring && ring->sched.ready) {
2784 ret = amdgpu_fence_wait_empty(ring);
2785 if (ret)
2786 return -EBUSY;
2787 }
2788 }
2789
2790 adev->in_runpm = true;
2791 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)
2792 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2793
2794 /*
2795 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
2796 * proper cleanups and put itself into a state ready for PNP. That
2797 * can address some random resuming failure observed on BOCO capable
2798 * platforms.
2799 * TODO: this may be also needed for PX capable platform.
2800 */
2801 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)
2802 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2803
2804 ret = amdgpu_device_prepare(drm_dev);
2805 if (ret)
2806 return ret;
2807 ret = amdgpu_device_suspend(drm_dev, false);
2808 if (ret) {
2809 adev->in_runpm = false;
2810 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)
2811 adev->mp1_state = PP_MP1_STATE_NONE;
2812 return ret;
2813 }
2814
2815 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)
2816 adev->mp1_state = PP_MP1_STATE_NONE;
2817
2818 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) {
2819 /* Only need to handle PCI state in the driver for ATPX
2820 * PCI core handles it for _PR3.
2821 */
2822 amdgpu_device_cache_pci_state(pdev);
2823 pci_disable_device(pdev);
2824 pci_ignore_hotplug(pdev);
2825 pci_set_power_state(pdev, PCI_D3cold);
2826 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
2827 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) {
2828 /* nothing to do */
2829 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) ||
2830 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) {
2831 amdgpu_device_baco_enter(drm_dev);
2832 }
2833
2834 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n");
2835
2836 return 0;
2837 }
2838
amdgpu_pmops_runtime_resume(struct device * dev)2839 static int amdgpu_pmops_runtime_resume(struct device *dev)
2840 {
2841 struct pci_dev *pdev = to_pci_dev(dev);
2842 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2843 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2844 int ret;
2845
2846 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE)
2847 return -EINVAL;
2848
2849 /* Avoids registers access if device is physically gone */
2850 if (!pci_device_is_present(adev->pdev))
2851 adev->no_hw_access = true;
2852
2853 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) {
2854 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2855
2856 /* Only need to handle PCI state in the driver for ATPX
2857 * PCI core handles it for _PR3.
2858 */
2859 pci_set_power_state(pdev, PCI_D0);
2860 amdgpu_device_load_pci_state(pdev);
2861 ret = pci_enable_device(pdev);
2862 if (ret)
2863 return ret;
2864 pci_set_master(pdev);
2865 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) {
2866 /* Only need to handle PCI state in the driver for ATPX
2867 * PCI core handles it for _PR3.
2868 */
2869 pci_set_master(pdev);
2870 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) ||
2871 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) {
2872 amdgpu_device_baco_exit(drm_dev);
2873 }
2874 ret = amdgpu_device_resume(drm_dev, false);
2875 if (ret) {
2876 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)
2877 pci_disable_device(pdev);
2878 return ret;
2879 }
2880
2881 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)
2882 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
2883 adev->in_runpm = false;
2884 return 0;
2885 }
2886
amdgpu_pmops_runtime_idle(struct device * dev)2887 static int amdgpu_pmops_runtime_idle(struct device *dev)
2888 {
2889 struct drm_device *drm_dev = dev_get_drvdata(dev);
2890 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2891 int ret;
2892
2893 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2894 pm_runtime_forbid(dev);
2895 return -EBUSY;
2896 }
2897
2898 ret = amdgpu_runtime_idle_check_display(dev);
2899 if (ret)
2900 goto done;
2901
2902 ret = amdgpu_runtime_idle_check_userq(dev);
2903 done:
2904 pm_runtime_mark_last_busy(dev);
2905 pm_runtime_autosuspend(dev);
2906 return ret;
2907 }
2908
amdgpu_drm_release(struct inode * inode,struct file * filp)2909 static int amdgpu_drm_release(struct inode *inode, struct file *filp)
2910 {
2911 struct drm_file *file_priv = filp->private_data;
2912 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
2913
2914 if (fpriv) {
2915 fpriv->evf_mgr.fd_closing = true;
2916 amdgpu_eviction_fence_destroy(&fpriv->evf_mgr);
2917 amdgpu_userq_mgr_fini(&fpriv->userq_mgr);
2918 }
2919
2920 return drm_release(inode, filp);
2921 }
2922
amdgpu_drm_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)2923 long amdgpu_drm_ioctl(struct file *filp,
2924 unsigned int cmd, unsigned long arg)
2925 {
2926 struct drm_file *file_priv = filp->private_data;
2927 struct drm_device *dev;
2928 long ret;
2929
2930 dev = file_priv->minor->dev;
2931 ret = pm_runtime_get_sync(dev->dev);
2932 if (ret < 0)
2933 goto out;
2934
2935 ret = drm_ioctl(filp, cmd, arg);
2936
2937 pm_runtime_mark_last_busy(dev->dev);
2938 out:
2939 pm_runtime_put_autosuspend(dev->dev);
2940 return ret;
2941 }
2942
2943 static const struct dev_pm_ops amdgpu_pm_ops = {
2944 .prepare = amdgpu_pmops_prepare,
2945 .complete = amdgpu_pmops_complete,
2946 .suspend = amdgpu_pmops_suspend,
2947 .suspend_noirq = amdgpu_pmops_suspend_noirq,
2948 .resume = amdgpu_pmops_resume,
2949 .freeze = amdgpu_pmops_freeze,
2950 .thaw = amdgpu_pmops_thaw,
2951 .poweroff = amdgpu_pmops_poweroff,
2952 .restore = amdgpu_pmops_restore,
2953 .runtime_suspend = amdgpu_pmops_runtime_suspend,
2954 .runtime_resume = amdgpu_pmops_runtime_resume,
2955 .runtime_idle = amdgpu_pmops_runtime_idle,
2956 };
2957
amdgpu_flush(struct file * f,fl_owner_t id)2958 static int amdgpu_flush(struct file *f, fl_owner_t id)
2959 {
2960 struct drm_file *file_priv = f->private_data;
2961 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
2962 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
2963
2964 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
2965 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
2966
2967 return timeout >= 0 ? 0 : timeout;
2968 }
2969
2970 static const struct file_operations amdgpu_driver_kms_fops = {
2971 .owner = THIS_MODULE,
2972 .open = drm_open,
2973 .flush = amdgpu_flush,
2974 .release = amdgpu_drm_release,
2975 .unlocked_ioctl = amdgpu_drm_ioctl,
2976 .mmap = drm_gem_mmap,
2977 .poll = drm_poll,
2978 .read = drm_read,
2979 #ifdef CONFIG_COMPAT
2980 .compat_ioctl = amdgpu_kms_compat_ioctl,
2981 #endif
2982 #ifdef CONFIG_PROC_FS
2983 .show_fdinfo = drm_show_fdinfo,
2984 #endif
2985 .fop_flags = FOP_UNSIGNED_OFFSET,
2986 };
2987
amdgpu_file_to_fpriv(struct file * filp,struct amdgpu_fpriv ** fpriv)2988 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
2989 {
2990 struct drm_file *file;
2991
2992 if (!filp)
2993 return -EINVAL;
2994
2995 if (filp->f_op != &amdgpu_driver_kms_fops)
2996 return -EINVAL;
2997
2998 file = filp->private_data;
2999 *fpriv = file->driver_priv;
3000 return 0;
3001 }
3002
3003 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
3004 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3005 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3006 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3007 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
3008 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3009 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3010 /* KMS */
3011 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3012 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3013 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3014 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3015 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3016 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3017 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3018 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3019 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3020 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3021 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ, amdgpu_userq_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3022 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3023 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3024 };
3025
3026 static const struct drm_driver amdgpu_kms_driver = {
3027 .driver_features =
3028 DRIVER_ATOMIC |
3029 DRIVER_GEM |
3030 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
3031 DRIVER_SYNCOBJ_TIMELINE,
3032 .open = amdgpu_driver_open_kms,
3033 .postclose = amdgpu_driver_postclose_kms,
3034 .ioctls = amdgpu_ioctls_kms,
3035 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
3036 .dumb_create = amdgpu_mode_dumb_create,
3037 .dumb_map_offset = amdgpu_mode_dumb_mmap,
3038 DRM_FBDEV_TTM_DRIVER_OPS,
3039 .fops = &amdgpu_driver_kms_fops,
3040 .release = &amdgpu_driver_release_kms,
3041 #ifdef CONFIG_PROC_FS
3042 .show_fdinfo = amdgpu_show_fdinfo,
3043 #endif
3044
3045 .gem_prime_import = amdgpu_gem_prime_import,
3046
3047 .name = DRIVER_NAME,
3048 .desc = DRIVER_DESC,
3049 .major = KMS_DRIVER_MAJOR,
3050 .minor = KMS_DRIVER_MINOR,
3051 .patchlevel = KMS_DRIVER_PATCHLEVEL,
3052 };
3053
3054 const struct drm_driver amdgpu_partition_driver = {
3055 .driver_features =
3056 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ |
3057 DRIVER_SYNCOBJ_TIMELINE,
3058 .open = amdgpu_driver_open_kms,
3059 .postclose = amdgpu_driver_postclose_kms,
3060 .ioctls = amdgpu_ioctls_kms,
3061 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
3062 .dumb_create = amdgpu_mode_dumb_create,
3063 .dumb_map_offset = amdgpu_mode_dumb_mmap,
3064 DRM_FBDEV_TTM_DRIVER_OPS,
3065 .fops = &amdgpu_driver_kms_fops,
3066 .release = &amdgpu_driver_release_kms,
3067
3068 .gem_prime_import = amdgpu_gem_prime_import,
3069
3070 .name = DRIVER_NAME,
3071 .desc = DRIVER_DESC,
3072 .major = KMS_DRIVER_MAJOR,
3073 .minor = KMS_DRIVER_MINOR,
3074 .patchlevel = KMS_DRIVER_PATCHLEVEL,
3075 };
3076
3077 static struct pci_error_handlers amdgpu_pci_err_handler = {
3078 .error_detected = amdgpu_pci_error_detected,
3079 .mmio_enabled = amdgpu_pci_mmio_enabled,
3080 .slot_reset = amdgpu_pci_slot_reset,
3081 .resume = amdgpu_pci_resume,
3082 };
3083
3084 static const struct attribute_group *amdgpu_sysfs_groups[] = {
3085 &amdgpu_vram_mgr_attr_group,
3086 &amdgpu_gtt_mgr_attr_group,
3087 &amdgpu_flash_attr_group,
3088 NULL,
3089 };
3090
3091 static struct pci_driver amdgpu_kms_pci_driver = {
3092 .name = DRIVER_NAME,
3093 .id_table = pciidlist,
3094 .probe = amdgpu_pci_probe,
3095 .remove = amdgpu_pci_remove,
3096 .shutdown = amdgpu_pci_shutdown,
3097 .driver.pm = &amdgpu_pm_ops,
3098 .err_handler = &amdgpu_pci_err_handler,
3099 .dev_groups = amdgpu_sysfs_groups,
3100 };
3101
amdgpu_init(void)3102 static int __init amdgpu_init(void)
3103 {
3104 int r;
3105
3106 r = amdgpu_sync_init();
3107 if (r)
3108 goto error_sync;
3109
3110 r = amdgpu_fence_slab_init();
3111 if (r)
3112 goto error_fence;
3113
3114 r = amdgpu_userq_fence_slab_init();
3115 if (r)
3116 goto error_fence;
3117
3118 DRM_INFO("amdgpu kernel modesetting enabled.\n");
3119 amdgpu_register_atpx_handler();
3120 amdgpu_acpi_detect();
3121
3122 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
3123 amdgpu_amdkfd_init();
3124
3125 if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) {
3126 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
3127 pr_crit("Overdrive is enabled, please disable it before "
3128 "reporting any bugs unrelated to overdrive.\n");
3129 }
3130
3131 /* let modprobe override vga console setting */
3132 return pci_register_driver(&amdgpu_kms_pci_driver);
3133
3134 error_fence:
3135 amdgpu_sync_fini();
3136
3137 error_sync:
3138 return r;
3139 }
3140
amdgpu_exit(void)3141 static void __exit amdgpu_exit(void)
3142 {
3143 amdgpu_amdkfd_fini();
3144 pci_unregister_driver(&amdgpu_kms_pci_driver);
3145 amdgpu_unregister_atpx_handler();
3146 amdgpu_acpi_release();
3147 amdgpu_sync_fini();
3148 amdgpu_fence_slab_fini();
3149 amdgpu_userq_fence_slab_fini();
3150 mmu_notifier_synchronize();
3151 amdgpu_xcp_drv_release();
3152 }
3153
3154 module_init(amdgpu_init);
3155 module_exit(amdgpu_exit);
3156
3157 MODULE_AUTHOR(DRIVER_AUTHOR);
3158 MODULE_DESCRIPTION(DRIVER_DESC);
3159 MODULE_LICENSE("GPL and additional rights");
3160