1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * GPIO driver for AMD
4 *
5 * Copyright (c) 2014,2015 AMD Corporation.
6 * Authors: Ken Xue <Ken.Xue@amd.com>
7 * Wu, Jeff <Jeff.Wu@amd.com>
8 *
9 */
10
11 #include <linux/err.h>
12 #include <linux/bug.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/spinlock.h>
16 #include <linux/compiler.h>
17 #include <linux/types.h>
18 #include <linux/errno.h>
19 #include <linux/log2.h>
20 #include <linux/io.h>
21 #include <linux/gpio/driver.h>
22 #include <linux/slab.h>
23 #include <linux/platform_device.h>
24 #include <linux/acpi.h>
25 #include <linux/seq_file.h>
26 #include <linux/interrupt.h>
27 #include <linux/bitops.h>
28 #include <linux/pinctrl/pinconf.h>
29 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/pinctrl/pinmux.h>
31 #include <linux/string_choices.h>
32 #include <linux/suspend.h>
33
34 #include "core.h"
35 #include "pinctrl-utils.h"
36 #include "pinctrl-amd.h"
37
38 #ifdef CONFIG_SUSPEND
39 static struct amd_gpio *pinctrl_dev;
40 #endif
41
amd_gpio_get_direction(struct gpio_chip * gc,unsigned offset)42 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
43 {
44 unsigned long flags;
45 u32 pin_reg;
46 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
47
48 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
49 pin_reg = readl(gpio_dev->base + offset * 4);
50 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
51
52 if (pin_reg & BIT(OUTPUT_ENABLE_OFF))
53 return GPIO_LINE_DIRECTION_OUT;
54
55 return GPIO_LINE_DIRECTION_IN;
56 }
57
amd_gpio_direction_input(struct gpio_chip * gc,unsigned offset)58 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
59 {
60 unsigned long flags;
61 u32 pin_reg;
62 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
63
64 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
65 pin_reg = readl(gpio_dev->base + offset * 4);
66 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
67 writel(pin_reg, gpio_dev->base + offset * 4);
68 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
69
70 return 0;
71 }
72
amd_gpio_direction_output(struct gpio_chip * gc,unsigned offset,int value)73 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
74 int value)
75 {
76 u32 pin_reg;
77 unsigned long flags;
78 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
79
80 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
81 pin_reg = readl(gpio_dev->base + offset * 4);
82 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
83 if (value)
84 pin_reg |= BIT(OUTPUT_VALUE_OFF);
85 else
86 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
87 writel(pin_reg, gpio_dev->base + offset * 4);
88 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
89
90 return 0;
91 }
92
amd_gpio_get_value(struct gpio_chip * gc,unsigned offset)93 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
94 {
95 u32 pin_reg;
96 unsigned long flags;
97 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
98
99 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
100 pin_reg = readl(gpio_dev->base + offset * 4);
101 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
102
103 return !!(pin_reg & BIT(PIN_STS_OFF));
104 }
105
amd_gpio_set_value(struct gpio_chip * gc,unsigned int offset,int value)106 static int amd_gpio_set_value(struct gpio_chip *gc, unsigned int offset,
107 int value)
108 {
109 u32 pin_reg;
110 unsigned long flags;
111 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
112
113 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
114 pin_reg = readl(gpio_dev->base + offset * 4);
115 if (value)
116 pin_reg |= BIT(OUTPUT_VALUE_OFF);
117 else
118 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
119 writel(pin_reg, gpio_dev->base + offset * 4);
120 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
121
122 return 0;
123 }
124
amd_gpio_set_debounce(struct amd_gpio * gpio_dev,unsigned int offset,unsigned int debounce)125 static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned int offset,
126 unsigned int debounce)
127 {
128 u32 time;
129 u32 pin_reg;
130 int ret = 0;
131
132 /* Use special handling for Pin0 debounce */
133 if (offset == 0) {
134 pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
135 if (pin_reg & INTERNAL_GPIO0_DEBOUNCE)
136 debounce = 0;
137 }
138
139 pin_reg = readl(gpio_dev->base + offset * 4);
140
141 if (debounce) {
142 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
143 pin_reg &= ~DB_TMR_OUT_MASK;
144 /*
145 Debounce Debounce Timer Max
146 TmrLarge TmrOutUnit Unit Debounce
147 Time
148 0 0 61 usec (2 RtcClk) 976 usec
149 0 1 244 usec (8 RtcClk) 3.9 msec
150 1 0 15.6 msec (512 RtcClk) 250 msec
151 1 1 62.5 msec (2048 RtcClk) 1 sec
152 */
153
154 if (debounce < 61) {
155 pin_reg |= 1;
156 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
157 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
158 } else if (debounce < 976) {
159 time = debounce / 61;
160 pin_reg |= time & DB_TMR_OUT_MASK;
161 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
162 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
163 } else if (debounce < 3900) {
164 time = debounce / 244;
165 pin_reg |= time & DB_TMR_OUT_MASK;
166 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
167 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
168 } else if (debounce < 250000) {
169 time = debounce / 15625;
170 pin_reg |= time & DB_TMR_OUT_MASK;
171 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
172 pin_reg |= BIT(DB_TMR_LARGE_OFF);
173 } else if (debounce < 1000000) {
174 time = debounce / 62500;
175 pin_reg |= time & DB_TMR_OUT_MASK;
176 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
177 pin_reg |= BIT(DB_TMR_LARGE_OFF);
178 } else {
179 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
180 ret = -EINVAL;
181 }
182 } else {
183 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
184 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
185 pin_reg &= ~DB_TMR_OUT_MASK;
186 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
187 }
188 writel(pin_reg, gpio_dev->base + offset * 4);
189
190 return ret;
191 }
192
193 #ifdef CONFIG_DEBUG_FS
amd_gpio_dbg_show(struct seq_file * s,struct gpio_chip * gc)194 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
195 {
196 u32 pin_reg;
197 u32 db_cntrl;
198 unsigned long flags;
199 unsigned int bank, i, pin_num;
200 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
201
202 bool tmr_out_unit;
203 bool tmr_large;
204
205 char *level_trig;
206 char *active_level;
207 char *interrupt_mask;
208 char *wake_cntrl0;
209 char *wake_cntrl1;
210 char *wake_cntrl2;
211 char *pin_sts;
212 char *interrupt_sts;
213 char *wake_sts;
214 char *orientation;
215 char debounce_value[40];
216 char *debounce_enable;
217 char *wake_cntrlz;
218
219 seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG));
220 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
221 unsigned int time = 0;
222 unsigned int unit = 0;
223
224 switch (bank) {
225 case 0:
226 i = 0;
227 pin_num = AMD_GPIO_PINS_BANK0;
228 break;
229 case 1:
230 i = 64;
231 pin_num = AMD_GPIO_PINS_BANK1 + i;
232 break;
233 case 2:
234 i = 128;
235 pin_num = AMD_GPIO_PINS_BANK2 + i;
236 break;
237 case 3:
238 i = 192;
239 pin_num = AMD_GPIO_PINS_BANK3 + i;
240 break;
241 default:
242 /* Illegal bank number, ignore */
243 continue;
244 }
245 seq_printf(s, "GPIO bank%d\n", bank);
246 seq_puts(s, "gpio\t int|active|trigger|S0i3| S3|S4/S5| Z|wake|pull| orient| debounce|reg\n");
247 for (; i < pin_num; i++) {
248 seq_printf(s, "#%d\t", i);
249 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
250 pin_reg = readl(gpio_dev->base + i * 4);
251 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
252
253 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
254 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
255 ACTIVE_LEVEL_MASK;
256
257 if (level == ACTIVE_LEVEL_HIGH)
258 active_level = "↑";
259 else if (level == ACTIVE_LEVEL_LOW)
260 active_level = "↓";
261 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
262 level == ACTIVE_LEVEL_BOTH)
263 active_level = "b";
264 else
265 active_level = "?";
266
267 if (pin_reg & BIT(LEVEL_TRIG_OFF))
268 level_trig = "level";
269 else
270 level_trig = " edge";
271
272 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
273 interrupt_mask = "��";
274 else
275 interrupt_mask = "��";
276
277 if (pin_reg & BIT(INTERRUPT_STS_OFF))
278 interrupt_sts = "��";
279 else
280 interrupt_sts = " ";
281
282 seq_printf(s, "%s %s| %s| %s|",
283 interrupt_sts,
284 interrupt_mask,
285 active_level,
286 level_trig);
287 } else
288 seq_puts(s, " ∅| | |");
289
290 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
291 wake_cntrl0 = "⏰";
292 else
293 wake_cntrl0 = " ";
294 seq_printf(s, " %s| ", wake_cntrl0);
295
296 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
297 wake_cntrl1 = "⏰";
298 else
299 wake_cntrl1 = " ";
300 seq_printf(s, "%s|", wake_cntrl1);
301
302 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
303 wake_cntrl2 = "⏰";
304 else
305 wake_cntrl2 = " ";
306 seq_printf(s, " %s|", wake_cntrl2);
307
308 if (pin_reg & BIT(WAKECNTRL_Z_OFF))
309 wake_cntrlz = "⏰";
310 else
311 wake_cntrlz = " ";
312 seq_printf(s, "%s|", wake_cntrlz);
313
314 if (pin_reg & BIT(WAKE_STS_OFF))
315 wake_sts = "��";
316 else
317 wake_sts = " ";
318 seq_printf(s, " %s|", wake_sts);
319
320 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
321 seq_puts(s, " ↑ |");
322 } else if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) {
323 seq_puts(s, " ↓ |");
324 } else {
325 seq_puts(s, " |");
326 }
327
328 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
329 pin_sts = "output";
330 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
331 orientation = "↑";
332 else
333 orientation = "↓";
334 } else {
335 pin_sts = "input ";
336 if (pin_reg & BIT(PIN_STS_OFF))
337 orientation = "↑";
338 else
339 orientation = "↓";
340 }
341 seq_printf(s, "%s %s|", pin_sts, orientation);
342
343 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg;
344 if (db_cntrl) {
345 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF);
346 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF);
347 time = pin_reg & DB_TMR_OUT_MASK;
348 if (tmr_large) {
349 if (tmr_out_unit)
350 unit = 62500;
351 else
352 unit = 15625;
353 } else {
354 if (tmr_out_unit)
355 unit = 244;
356 else
357 unit = 61;
358 }
359 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl)
360 debounce_enable = "b";
361 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl)
362 debounce_enable = "↓";
363 else
364 debounce_enable = "↑";
365 snprintf(debounce_value, sizeof(debounce_value), "%06u", time * unit);
366 seq_printf(s, "%s (�� %sus)|", debounce_enable, debounce_value);
367 } else {
368 seq_puts(s, " |");
369 }
370 seq_printf(s, "0x%x\n", pin_reg);
371 }
372 }
373 }
374 #else
375 #define amd_gpio_dbg_show NULL
376 #endif
377
amd_gpio_irq_enable(struct irq_data * d)378 static void amd_gpio_irq_enable(struct irq_data *d)
379 {
380 u32 pin_reg;
381 unsigned long flags;
382 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
383 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
384 irq_hw_number_t hwirq = irqd_to_hwirq(d);
385
386 gpiochip_enable_irq(gc, hwirq);
387
388 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
389 pin_reg = readl(gpio_dev->base + hwirq * 4);
390 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
391 pin_reg |= BIT(INTERRUPT_MASK_OFF);
392 writel(pin_reg, gpio_dev->base + hwirq * 4);
393 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
394 }
395
amd_gpio_irq_disable(struct irq_data * d)396 static void amd_gpio_irq_disable(struct irq_data *d)
397 {
398 u32 pin_reg;
399 unsigned long flags;
400 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
401 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
402 irq_hw_number_t hwirq = irqd_to_hwirq(d);
403
404 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
405 pin_reg = readl(gpio_dev->base + hwirq * 4);
406 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
407 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
408 writel(pin_reg, gpio_dev->base + hwirq * 4);
409 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
410
411 gpiochip_disable_irq(gc, hwirq);
412 }
413
amd_gpio_irq_mask(struct irq_data * d)414 static void amd_gpio_irq_mask(struct irq_data *d)
415 {
416 u32 pin_reg;
417 unsigned long flags;
418 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
419 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
420 irq_hw_number_t hwirq = irqd_to_hwirq(d);
421
422 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
423 pin_reg = readl(gpio_dev->base + hwirq * 4);
424 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
425 writel(pin_reg, gpio_dev->base + hwirq * 4);
426 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
427 }
428
amd_gpio_irq_unmask(struct irq_data * d)429 static void amd_gpio_irq_unmask(struct irq_data *d)
430 {
431 u32 pin_reg;
432 unsigned long flags;
433 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
434 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
435 irq_hw_number_t hwirq = irqd_to_hwirq(d);
436
437 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
438 pin_reg = readl(gpio_dev->base + hwirq * 4);
439 pin_reg |= BIT(INTERRUPT_MASK_OFF);
440 writel(pin_reg, gpio_dev->base + hwirq * 4);
441 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
442 }
443
amd_gpio_irq_set_wake(struct irq_data * d,unsigned int on)444 static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
445 {
446 u32 pin_reg;
447 unsigned long flags;
448 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
449 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
450 u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3);
451 irq_hw_number_t hwirq = irqd_to_hwirq(d);
452 int err;
453
454 pm_pr_dbg("Setting wake for GPIO %lu to %s\n",
455 hwirq, str_enable_disable(on));
456
457 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
458 pin_reg = readl(gpio_dev->base + hwirq * 4);
459
460 if (on)
461 pin_reg |= wake_mask;
462 else
463 pin_reg &= ~wake_mask;
464
465 writel(pin_reg, gpio_dev->base + hwirq * 4);
466 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
467
468 if (on)
469 err = enable_irq_wake(gpio_dev->irq);
470 else
471 err = disable_irq_wake(gpio_dev->irq);
472
473 if (err)
474 dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n",
475 str_enable_disable(on));
476
477 return 0;
478 }
479
amd_gpio_irq_eoi(struct irq_data * d)480 static void amd_gpio_irq_eoi(struct irq_data *d)
481 {
482 u32 reg;
483 unsigned long flags;
484 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
485 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
486
487 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
488 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
489 reg |= EOI_MASK;
490 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
491 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
492 }
493
amd_gpio_irq_set_type(struct irq_data * d,unsigned int type)494 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
495 {
496 int ret = 0;
497 u32 pin_reg, pin_reg_irq_en, mask;
498 unsigned long flags;
499 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
500 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
501 irq_hw_number_t hwirq = irqd_to_hwirq(d);
502
503 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
504 pin_reg = readl(gpio_dev->base + hwirq * 4);
505
506 switch (type & IRQ_TYPE_SENSE_MASK) {
507 case IRQ_TYPE_EDGE_RISING:
508 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
509 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
510 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
511 irq_set_handler_locked(d, handle_edge_irq);
512 break;
513
514 case IRQ_TYPE_EDGE_FALLING:
515 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
516 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
517 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
518 irq_set_handler_locked(d, handle_edge_irq);
519 break;
520
521 case IRQ_TYPE_EDGE_BOTH:
522 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
523 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
524 pin_reg |= BOTH_EDGES << ACTIVE_LEVEL_OFF;
525 irq_set_handler_locked(d, handle_edge_irq);
526 break;
527
528 case IRQ_TYPE_LEVEL_HIGH:
529 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
530 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
531 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
532 irq_set_handler_locked(d, handle_level_irq);
533 break;
534
535 case IRQ_TYPE_LEVEL_LOW:
536 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
537 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
538 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
539 irq_set_handler_locked(d, handle_level_irq);
540 break;
541
542 case IRQ_TYPE_NONE:
543 break;
544
545 default:
546 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
547 ret = -EINVAL;
548 }
549
550 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
551 /*
552 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
553 * debounce registers of any GPIO will block wake/interrupt status
554 * generation for *all* GPIOs for a length of time that depends on
555 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the
556 * INTERRUPT_ENABLE bit will read as 0.
557 *
558 * We temporarily enable irq for the GPIO whose configuration is
559 * changing, and then wait for it to read back as 1 to know when
560 * debounce has settled and then disable the irq again.
561 * We do this polling with the spinlock held to ensure other GPIO
562 * access routines do not read an incorrect value for the irq enable
563 * bit of other GPIOs. We keep the GPIO masked while polling to avoid
564 * spurious irqs, and disable the irq again after polling.
565 */
566 mask = BIT(INTERRUPT_ENABLE_OFF);
567 pin_reg_irq_en = pin_reg;
568 pin_reg_irq_en |= mask;
569 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
570 writel(pin_reg_irq_en, gpio_dev->base + hwirq * 4);
571 while ((readl(gpio_dev->base + hwirq * 4) & mask) != mask)
572 continue;
573 writel(pin_reg, gpio_dev->base + hwirq * 4);
574 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
575
576 return ret;
577 }
578
amd_irq_ack(struct irq_data * d)579 static void amd_irq_ack(struct irq_data *d)
580 {
581 /*
582 * based on HW design,there is no need to ack HW
583 * before handle current irq. But this routine is
584 * necessary for handle_edge_irq
585 */
586 }
587
588 static const struct irq_chip amd_gpio_irqchip = {
589 .name = "amd_gpio",
590 .irq_ack = amd_irq_ack,
591 .irq_enable = amd_gpio_irq_enable,
592 .irq_disable = amd_gpio_irq_disable,
593 .irq_mask = amd_gpio_irq_mask,
594 .irq_unmask = amd_gpio_irq_unmask,
595 .irq_set_wake = amd_gpio_irq_set_wake,
596 .irq_eoi = amd_gpio_irq_eoi,
597 .irq_set_type = amd_gpio_irq_set_type,
598 /*
599 * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event
600 * also generates an IRQ. We need the IRQ so the irq_handler can clear
601 * the wake event. Otherwise the wake event will never clear and
602 * prevent the system from suspending.
603 */
604 .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE,
605 GPIOCHIP_IRQ_RESOURCE_HELPERS,
606 };
607
608 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
609
do_amd_gpio_irq_handler(int irq,void * dev_id)610 static bool do_amd_gpio_irq_handler(int irq, void *dev_id)
611 {
612 struct amd_gpio *gpio_dev = dev_id;
613 struct gpio_chip *gc = &gpio_dev->gc;
614 unsigned int i, irqnr;
615 unsigned long flags;
616 u32 __iomem *regs;
617 bool ret = false;
618 u32 regval;
619 u64 status, mask;
620
621 /* Read the wake status */
622 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
623 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
624 status <<= 32;
625 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
626 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
627
628 /* Bit 0-45 contain the relevant status bits */
629 status &= (1ULL << 46) - 1;
630 regs = gpio_dev->base;
631 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
632 if (!(status & mask))
633 continue;
634 status &= ~mask;
635
636 /* Each status bit covers four pins */
637 for (i = 0; i < 4; i++) {
638 regval = readl(regs + i);
639
640 if (regval & PIN_IRQ_PENDING)
641 pm_pr_dbg("GPIO %d is active: 0x%x",
642 irqnr + i, regval);
643
644 /* caused wake on resume context for shared IRQ */
645 if (irq < 0 && (regval & BIT(WAKE_STS_OFF)))
646 return true;
647
648 if (!(regval & PIN_IRQ_PENDING) ||
649 !(regval & BIT(INTERRUPT_MASK_OFF)))
650 continue;
651 generic_handle_domain_irq_safe(gc->irq.domain, irqnr + i);
652
653 /* Clear interrupt.
654 * We must read the pin register again, in case the
655 * value was changed while executing
656 * generic_handle_domain_irq() above.
657 * If the line is not an irq, disable it in order to
658 * avoid a system hang caused by an interrupt storm.
659 */
660 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
661 regval = readl(regs + i);
662 if (!gpiochip_line_is_irq(gc, irqnr + i)) {
663 regval &= ~BIT(INTERRUPT_MASK_OFF);
664 dev_dbg(&gpio_dev->pdev->dev,
665 "Disabling spurious GPIO IRQ %d\n",
666 irqnr + i);
667 } else {
668 ret = true;
669 }
670 writel(regval, regs + i);
671 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
672 }
673 }
674 /* did not cause wake on resume context for shared IRQ */
675 if (irq < 0)
676 return false;
677
678 /* Signal EOI to the GPIO unit */
679 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
680 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
681 regval |= EOI_MASK;
682 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
683 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
684
685 return ret;
686 }
687
amd_gpio_irq_handler(int irq,void * dev_id)688 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
689 {
690 return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id));
691 }
692
amd_gpio_check_wake(void * dev_id)693 static bool __maybe_unused amd_gpio_check_wake(void *dev_id)
694 {
695 return do_amd_gpio_irq_handler(-1, dev_id);
696 }
697
amd_get_groups_count(struct pinctrl_dev * pctldev)698 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
699 {
700 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
701
702 return gpio_dev->ngroups;
703 }
704
amd_get_group_name(struct pinctrl_dev * pctldev,unsigned group)705 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
706 unsigned group)
707 {
708 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
709
710 return gpio_dev->groups[group].name;
711 }
712
amd_get_group_pins(struct pinctrl_dev * pctldev,unsigned group,const unsigned ** pins,unsigned * num_pins)713 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
714 unsigned group,
715 const unsigned **pins,
716 unsigned *num_pins)
717 {
718 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
719
720 *pins = gpio_dev->groups[group].pins;
721 *num_pins = gpio_dev->groups[group].npins;
722 return 0;
723 }
724
725 static const struct pinctrl_ops amd_pinctrl_ops = {
726 .get_groups_count = amd_get_groups_count,
727 .get_group_name = amd_get_group_name,
728 .get_group_pins = amd_get_group_pins,
729 #ifdef CONFIG_OF
730 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
731 .dt_free_map = pinctrl_utils_free_map,
732 #endif
733 };
734
amd_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)735 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
736 unsigned int pin,
737 unsigned long *config)
738 {
739 u32 pin_reg;
740 unsigned arg;
741 unsigned long flags;
742 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
743 enum pin_config_param param = pinconf_to_config_param(*config);
744
745 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
746 pin_reg = readl(gpio_dev->base + pin*4);
747 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
748 switch (param) {
749 case PIN_CONFIG_INPUT_DEBOUNCE:
750 arg = pin_reg & DB_TMR_OUT_MASK;
751 break;
752
753 case PIN_CONFIG_BIAS_PULL_DOWN:
754 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
755 break;
756
757 case PIN_CONFIG_BIAS_PULL_UP:
758 arg = (pin_reg >> PULL_UP_ENABLE_OFF) & BIT(0);
759 break;
760
761 case PIN_CONFIG_DRIVE_STRENGTH:
762 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
763 break;
764
765 default:
766 dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
767 param);
768 return -ENOTSUPP;
769 }
770
771 *config = pinconf_to_config_packed(param, arg);
772
773 return 0;
774 }
775
amd_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)776 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
777 unsigned long *configs, unsigned int num_configs)
778 {
779 int i;
780 u32 arg;
781 int ret = 0;
782 u32 pin_reg;
783 unsigned long flags;
784 enum pin_config_param param;
785 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
786
787 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
788 for (i = 0; i < num_configs; i++) {
789 param = pinconf_to_config_param(configs[i]);
790 arg = pinconf_to_config_argument(configs[i]);
791 pin_reg = readl(gpio_dev->base + pin*4);
792
793 switch (param) {
794 case PIN_CONFIG_INPUT_DEBOUNCE:
795 ret = amd_gpio_set_debounce(gpio_dev, pin, arg);
796 goto out_unlock;
797
798 case PIN_CONFIG_BIAS_PULL_DOWN:
799 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
800 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
801 break;
802
803 case PIN_CONFIG_BIAS_PULL_UP:
804 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
805 pin_reg |= (arg & BIT(0)) << PULL_UP_ENABLE_OFF;
806 break;
807
808 case PIN_CONFIG_DRIVE_STRENGTH:
809 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
810 << DRV_STRENGTH_SEL_OFF);
811 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
812 << DRV_STRENGTH_SEL_OFF;
813 break;
814
815 default:
816 dev_dbg(&gpio_dev->pdev->dev,
817 "Invalid config param %04x\n", param);
818 ret = -ENOTSUPP;
819 }
820
821 writel(pin_reg, gpio_dev->base + pin*4);
822 }
823 out_unlock:
824 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
825
826 return ret;
827 }
828
amd_pinconf_group_get(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * config)829 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
830 unsigned int group,
831 unsigned long *config)
832 {
833 const unsigned *pins;
834 unsigned npins;
835 int ret;
836
837 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
838 if (ret)
839 return ret;
840
841 if (amd_pinconf_get(pctldev, pins[0], config))
842 return -ENOTSUPP;
843
844 return 0;
845 }
846
amd_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned group,unsigned long * configs,unsigned num_configs)847 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
848 unsigned group, unsigned long *configs,
849 unsigned num_configs)
850 {
851 const unsigned *pins;
852 unsigned npins;
853 int i, ret;
854
855 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
856 if (ret)
857 return ret;
858 for (i = 0; i < npins; i++) {
859 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
860 return -ENOTSUPP;
861 }
862 return 0;
863 }
864
amd_gpio_set_config(struct gpio_chip * gc,unsigned int pin,unsigned long config)865 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin,
866 unsigned long config)
867 {
868 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
869
870 return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1);
871 }
872
873 static const struct pinconf_ops amd_pinconf_ops = {
874 .pin_config_get = amd_pinconf_get,
875 .pin_config_set = amd_pinconf_set,
876 .pin_config_group_get = amd_pinconf_group_get,
877 .pin_config_group_set = amd_pinconf_group_set,
878 };
879
amd_gpio_irq_init(struct amd_gpio * gpio_dev)880 static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
881 {
882 const struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
883 unsigned long flags;
884 u32 pin_reg, mask;
885 int i;
886
887 mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3);
888
889 for (i = 0; i < desc->npins; i++) {
890 int pin = desc->pins[i].number;
891 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
892
893 if (!pd)
894 continue;
895
896 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
897
898 pin_reg = readl(gpio_dev->base + pin * 4);
899 pin_reg &= ~mask;
900 writel(pin_reg, gpio_dev->base + pin * 4);
901
902 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
903 }
904 }
905
906 #if defined(CONFIG_SUSPEND) && defined(CONFIG_ACPI)
amd_gpio_check_pending(void)907 static void amd_gpio_check_pending(void)
908 {
909 struct amd_gpio *gpio_dev = pinctrl_dev;
910 const struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
911 int i;
912
913 if (!pm_debug_messages_on)
914 return;
915
916 for (i = 0; i < desc->npins; i++) {
917 int pin = desc->pins[i].number;
918 u32 tmp;
919
920 tmp = readl(gpio_dev->base + pin * 4);
921 if (tmp & PIN_IRQ_PENDING)
922 pm_pr_dbg("%s: GPIO %d is active: 0x%x.\n", __func__, pin, tmp);
923 }
924 }
925
926 static struct acpi_s2idle_dev_ops pinctrl_amd_s2idle_dev_ops = {
927 .check = amd_gpio_check_pending,
928 };
929
amd_gpio_register_s2idle_ops(void)930 static void amd_gpio_register_s2idle_ops(void)
931 {
932 acpi_register_lps0_dev(&pinctrl_amd_s2idle_dev_ops);
933 }
934
amd_gpio_unregister_s2idle_ops(void)935 static void amd_gpio_unregister_s2idle_ops(void)
936 {
937 acpi_unregister_lps0_dev(&pinctrl_amd_s2idle_dev_ops);
938 }
939 #else
amd_gpio_register_s2idle_ops(void)940 static inline void amd_gpio_register_s2idle_ops(void) {}
amd_gpio_unregister_s2idle_ops(void)941 static inline void amd_gpio_unregister_s2idle_ops(void) {}
942 #endif
943
944 #ifdef CONFIG_PM_SLEEP
amd_gpio_should_save(struct amd_gpio * gpio_dev,unsigned int pin)945 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
946 {
947 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
948
949 if (!pd)
950 return false;
951
952 /*
953 * Only restore the pin if it is actually in use by the kernel (or
954 * by userspace).
955 */
956 if (pd->mux_owner || pd->gpio_owner ||
957 gpiochip_line_is_irq(&gpio_dev->gc, pin))
958 return true;
959
960 return false;
961 }
962
amd_gpio_suspend_hibernate_common(struct device * dev,bool is_suspend)963 static int amd_gpio_suspend_hibernate_common(struct device *dev, bool is_suspend)
964 {
965 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
966 const struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
967 unsigned long flags;
968 int i;
969 u32 wake_mask = is_suspend ? WAKE_SOURCE_SUSPEND : WAKE_SOURCE_HIBERNATE;
970
971 for (i = 0; i < desc->npins; i++) {
972 int pin = desc->pins[i].number;
973
974 if (!amd_gpio_should_save(gpio_dev, pin))
975 continue;
976
977 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
978 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING;
979
980 /* mask any interrupts not intended to be a wake source */
981 if (!(gpio_dev->saved_regs[i] & wake_mask)) {
982 writel(gpio_dev->saved_regs[i] & ~BIT(INTERRUPT_MASK_OFF),
983 gpio_dev->base + pin * 4);
984 pm_pr_dbg("Disabling GPIO #%d interrupt for %s.\n",
985 pin, is_suspend ? "suspend" : "hibernate");
986 }
987
988 /*
989 * debounce enabled over suspend has shown issues with a GPIO
990 * being unable to wake the system, as we're only interested in
991 * the actual wakeup event, clear it.
992 */
993 if (gpio_dev->saved_regs[i] & (DB_CNTRl_MASK << DB_CNTRL_OFF)) {
994 amd_gpio_set_debounce(gpio_dev, pin, 0);
995 pm_pr_dbg("Clearing debounce for GPIO #%d during %s.\n",
996 pin, is_suspend ? "suspend" : "hibernate");
997 }
998
999 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
1000 }
1001
1002 return 0;
1003 }
1004
amd_gpio_suspend(struct device * dev)1005 static int amd_gpio_suspend(struct device *dev)
1006 {
1007 #ifdef CONFIG_SUSPEND
1008 pinctrl_dev = dev_get_drvdata(dev);
1009 #endif
1010 return amd_gpio_suspend_hibernate_common(dev, true);
1011 }
1012
amd_gpio_hibernate(struct device * dev)1013 static int amd_gpio_hibernate(struct device *dev)
1014 {
1015 return amd_gpio_suspend_hibernate_common(dev, false);
1016 }
1017
amd_gpio_resume(struct device * dev)1018 static int amd_gpio_resume(struct device *dev)
1019 {
1020 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
1021 const struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
1022 unsigned long flags;
1023 int i;
1024
1025 for (i = 0; i < desc->npins; i++) {
1026 int pin = desc->pins[i].number;
1027
1028 if (!amd_gpio_should_save(gpio_dev, pin))
1029 continue;
1030
1031 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
1032 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;
1033 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4);
1034 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
1035 }
1036
1037 return 0;
1038 }
1039
1040 static const struct dev_pm_ops amd_gpio_pm_ops = {
1041 .suspend_late = amd_gpio_suspend,
1042 .resume_early = amd_gpio_resume,
1043 .freeze_late = amd_gpio_hibernate,
1044 .thaw_early = amd_gpio_resume,
1045 .poweroff_late = amd_gpio_hibernate,
1046 .restore_early = amd_gpio_resume,
1047 };
1048 #endif
1049
amd_get_functions_count(struct pinctrl_dev * pctldev)1050 static int amd_get_functions_count(struct pinctrl_dev *pctldev)
1051 {
1052 return ARRAY_SIZE(pmx_functions);
1053 }
1054
amd_get_fname(struct pinctrl_dev * pctrldev,unsigned int selector)1055 static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector)
1056 {
1057 return pmx_functions[selector].name;
1058 }
1059
amd_get_groups(struct pinctrl_dev * pctrldev,unsigned int selector,const char * const ** groups,unsigned int * const num_groups)1060 static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector,
1061 const char * const **groups,
1062 unsigned int * const num_groups)
1063 {
1064 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
1065
1066 if (!gpio_dev->iomux_base) {
1067 dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector);
1068 return -EINVAL;
1069 }
1070
1071 *groups = pmx_functions[selector].groups;
1072 *num_groups = pmx_functions[selector].ngroups;
1073 return 0;
1074 }
1075
amd_set_mux(struct pinctrl_dev * pctrldev,unsigned int function,unsigned int group)1076 static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group)
1077 {
1078 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
1079 struct device *dev = &gpio_dev->pdev->dev;
1080 struct pin_desc *pd;
1081 int ind, index;
1082
1083 if (!gpio_dev->iomux_base)
1084 return -EINVAL;
1085
1086 for (index = 0; index < NSELECTS; index++) {
1087 if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index]))
1088 continue;
1089
1090 if (readb(gpio_dev->iomux_base + pmx_functions[function].index) ==
1091 FUNCTION_INVALID) {
1092 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n",
1093 pmx_functions[function].index);
1094 return -EINVAL;
1095 }
1096
1097 writeb(index, gpio_dev->iomux_base + pmx_functions[function].index);
1098
1099 if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) &
1100 FUNCTION_MASK)) {
1101 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n",
1102 pmx_functions[function].index);
1103 return -EINVAL;
1104 }
1105
1106 for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) {
1107 if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F")))
1108 continue;
1109
1110 pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]);
1111 pd->mux_owner = gpio_dev->groups[group].name;
1112 }
1113 break;
1114 }
1115
1116 return 0;
1117 }
1118
1119 static const struct pinmux_ops amd_pmxops = {
1120 .get_functions_count = amd_get_functions_count,
1121 .get_function_name = amd_get_fname,
1122 .get_function_groups = amd_get_groups,
1123 .set_mux = amd_set_mux,
1124 };
1125
1126 static struct pinctrl_desc amd_pinctrl_desc = {
1127 .pins = kerncz_pins,
1128 .npins = ARRAY_SIZE(kerncz_pins),
1129 .pctlops = &amd_pinctrl_ops,
1130 .pmxops = &amd_pmxops,
1131 .confops = &amd_pinconf_ops,
1132 .owner = THIS_MODULE,
1133 };
1134
amd_get_iomux_res(struct amd_gpio * gpio_dev)1135 static void amd_get_iomux_res(struct amd_gpio *gpio_dev)
1136 {
1137 struct pinctrl_desc *desc = &amd_pinctrl_desc;
1138 struct device *dev = &gpio_dev->pdev->dev;
1139 int index;
1140
1141 index = device_property_match_string(dev, "pinctrl-resource-names", "iomux");
1142 if (index < 0) {
1143 dev_dbg(dev, "iomux not supported\n");
1144 goto out_no_pinmux;
1145 }
1146
1147 gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index);
1148 if (IS_ERR(gpio_dev->iomux_base)) {
1149 dev_dbg(dev, "iomux not supported %d io resource\n", index);
1150 goto out_no_pinmux;
1151 }
1152
1153 return;
1154
1155 out_no_pinmux:
1156 desc->pmxops = NULL;
1157 }
1158
amd_gpio_probe(struct platform_device * pdev)1159 static int amd_gpio_probe(struct platform_device *pdev)
1160 {
1161 int ret = 0;
1162 struct resource *res;
1163 struct amd_gpio *gpio_dev;
1164 struct gpio_irq_chip *girq;
1165
1166 gpio_dev = devm_kzalloc(&pdev->dev,
1167 sizeof(struct amd_gpio), GFP_KERNEL);
1168 if (!gpio_dev)
1169 return -ENOMEM;
1170
1171 raw_spin_lock_init(&gpio_dev->lock);
1172
1173 gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1174 if (IS_ERR(gpio_dev->base)) {
1175 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
1176 return PTR_ERR(gpio_dev->base);
1177 }
1178
1179 gpio_dev->irq = platform_get_irq(pdev, 0);
1180 if (gpio_dev->irq < 0)
1181 return gpio_dev->irq;
1182
1183 #ifdef CONFIG_SUSPEND
1184 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
1185 sizeof(*gpio_dev->saved_regs),
1186 GFP_KERNEL);
1187 if (!gpio_dev->saved_regs)
1188 return -ENOMEM;
1189 #endif
1190
1191 gpio_dev->pdev = pdev;
1192 gpio_dev->gc.get_direction = amd_gpio_get_direction;
1193 gpio_dev->gc.direction_input = amd_gpio_direction_input;
1194 gpio_dev->gc.direction_output = amd_gpio_direction_output;
1195 gpio_dev->gc.get = amd_gpio_get_value;
1196 gpio_dev->gc.set = amd_gpio_set_value;
1197 gpio_dev->gc.set_config = amd_gpio_set_config;
1198 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
1199
1200 gpio_dev->gc.base = -1;
1201 gpio_dev->gc.label = pdev->name;
1202 gpio_dev->gc.owner = THIS_MODULE;
1203 gpio_dev->gc.parent = &pdev->dev;
1204 gpio_dev->gc.ngpio = resource_size(res) / 4;
1205
1206 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
1207 gpio_dev->groups = kerncz_groups;
1208 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
1209
1210 amd_pinctrl_desc.name = dev_name(&pdev->dev);
1211 amd_get_iomux_res(gpio_dev);
1212 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
1213 gpio_dev);
1214 if (IS_ERR(gpio_dev->pctrl)) {
1215 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1216 return PTR_ERR(gpio_dev->pctrl);
1217 }
1218
1219 /* Disable and mask interrupts */
1220 amd_gpio_irq_init(gpio_dev);
1221
1222 girq = &gpio_dev->gc.irq;
1223 gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip);
1224 /* This will let us handle the parent IRQ in the driver */
1225 girq->parent_handler = NULL;
1226 girq->num_parents = 0;
1227 girq->parents = NULL;
1228 girq->default_type = IRQ_TYPE_NONE;
1229 girq->handler = handle_simple_irq;
1230
1231 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
1232 if (ret)
1233 return ret;
1234
1235 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
1236 0, 0, gpio_dev->gc.ngpio);
1237 if (ret) {
1238 dev_err(&pdev->dev, "Failed to add pin range\n");
1239 goto out2;
1240 }
1241
1242 ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler,
1243 IRQF_SHARED | IRQF_COND_ONESHOT, KBUILD_MODNAME, gpio_dev);
1244 if (ret)
1245 goto out2;
1246
1247 platform_set_drvdata(pdev, gpio_dev);
1248 acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev);
1249 amd_gpio_register_s2idle_ops();
1250
1251 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
1252 return ret;
1253
1254 out2:
1255 gpiochip_remove(&gpio_dev->gc);
1256
1257 return ret;
1258 }
1259
amd_gpio_remove(struct platform_device * pdev)1260 static void amd_gpio_remove(struct platform_device *pdev)
1261 {
1262 struct amd_gpio *gpio_dev;
1263
1264 gpio_dev = platform_get_drvdata(pdev);
1265
1266 gpiochip_remove(&gpio_dev->gc);
1267 acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev);
1268 amd_gpio_unregister_s2idle_ops();
1269 }
1270
1271 #ifdef CONFIG_ACPI
1272 static const struct acpi_device_id amd_gpio_acpi_match[] = {
1273 { "AMD0030", 0 },
1274 { "AMDI0030", 0},
1275 { "AMDI0031", 0},
1276 { "AMDI0033", 0},
1277 { },
1278 };
1279 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
1280 #endif
1281
1282 static struct platform_driver amd_gpio_driver = {
1283 .driver = {
1284 .name = "amd_gpio",
1285 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
1286 #ifdef CONFIG_PM_SLEEP
1287 .pm = &amd_gpio_pm_ops,
1288 #endif
1289 },
1290 .probe = amd_gpio_probe,
1291 .remove = amd_gpio_remove,
1292 };
1293
1294 module_platform_driver(amd_gpio_driver);
1295
1296 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
1297 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
1298