1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * AMD SoC Power Management Controller Driver
4 *
5 * Copyright (c) 2020, Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
9 */
10
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13 #include <linux/acpi.h>
14 #include <linux/array_size.h>
15 #include <linux/bitfield.h>
16 #include <linux/bits.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/io.h>
20 #include <linux/iopoll.h>
21 #include <linux/limits.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/platform_device.h>
25 #include <linux/rtc.h>
26 #include <linux/serio.h>
27 #include <linux/suspend.h>
28 #include <linux/seq_file.h>
29 #include <linux/uaccess.h>
30
31 #include <asm/amd/node.h>
32
33 #include "pmc.h"
34
35 static const struct amd_pmc_bit_map soc15_ip_blk_v2[] = {
36 {"DISPLAY", BIT(0)},
37 {"CPU", BIT(1)},
38 {"GFX", BIT(2)},
39 {"VDD", BIT(3)},
40 {"VDD_CCX", BIT(4)},
41 {"ACP", BIT(5)},
42 {"VCN_0", BIT(6)},
43 {"VCN_1", BIT(7)},
44 {"ISP", BIT(8)},
45 {"NBIO", BIT(9)},
46 {"DF", BIT(10)},
47 {"USB3_0", BIT(11)},
48 {"USB3_1", BIT(12)},
49 {"LAPIC", BIT(13)},
50 {"USB3_2", BIT(14)},
51 {"USB4_RT0", BIT(15)},
52 {"USB4_RT1", BIT(16)},
53 {"USB4_0", BIT(17)},
54 {"USB4_1", BIT(18)},
55 {"MPM", BIT(19)},
56 {"JPEG_0", BIT(20)},
57 {"JPEG_1", BIT(21)},
58 {"IPU", BIT(22)},
59 {"UMSCH", BIT(23)},
60 {"VPE", BIT(24)},
61 };
62
63 static const struct amd_pmc_bit_map soc15_ip_blk[] = {
64 {"DISPLAY", BIT(0)},
65 {"CPU", BIT(1)},
66 {"GFX", BIT(2)},
67 {"VDD", BIT(3)},
68 {"ACP", BIT(4)},
69 {"VCN", BIT(5)},
70 {"ISP", BIT(6)},
71 {"NBIO", BIT(7)},
72 {"DF", BIT(8)},
73 {"USB3_0", BIT(9)},
74 {"USB3_1", BIT(10)},
75 {"LAPIC", BIT(11)},
76 {"USB3_2", BIT(12)},
77 {"USB3_3", BIT(13)},
78 {"USB3_4", BIT(14)},
79 {"USB4_0", BIT(15)},
80 {"USB4_1", BIT(16)},
81 {"MPM", BIT(17)},
82 {"JPEG", BIT(18)},
83 {"IPU", BIT(19)},
84 {"UMSCH", BIT(20)},
85 {"VPE", BIT(21)},
86 };
87
88 static bool disable_workarounds;
89 module_param(disable_workarounds, bool, 0644);
90 MODULE_PARM_DESC(disable_workarounds, "Disable workarounds for platform bugs");
91
92 static struct amd_pmc_dev pmc;
93
amd_pmc_reg_read(struct amd_pmc_dev * dev,int reg_offset)94 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
95 {
96 return ioread32(dev->regbase + reg_offset);
97 }
98
amd_pmc_reg_write(struct amd_pmc_dev * dev,int reg_offset,u32 val)99 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
100 {
101 iowrite32(val, dev->regbase + reg_offset);
102 }
103
amd_pmc_get_ip_info(struct amd_pmc_dev * dev)104 static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
105 {
106 switch (dev->cpu_id) {
107 case AMD_CPU_ID_PCO:
108 case AMD_CPU_ID_RN:
109 case AMD_CPU_ID_YC:
110 case AMD_CPU_ID_CB:
111 dev->num_ips = 12;
112 dev->ips_ptr = soc15_ip_blk;
113 dev->smu_msg = 0x538;
114 break;
115 case AMD_CPU_ID_PS:
116 dev->num_ips = 21;
117 dev->ips_ptr = soc15_ip_blk;
118 dev->smu_msg = 0x538;
119 break;
120 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
121 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
122 if (boot_cpu_data.x86_model == 0x70) {
123 dev->num_ips = ARRAY_SIZE(soc15_ip_blk_v2);
124 dev->ips_ptr = soc15_ip_blk_v2;
125 } else {
126 dev->num_ips = ARRAY_SIZE(soc15_ip_blk);
127 dev->ips_ptr = soc15_ip_blk;
128 }
129 dev->smu_msg = 0x938;
130 break;
131 }
132 }
133
amd_pmc_setup_smu_logging(struct amd_pmc_dev * dev)134 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
135 {
136 if (dev->cpu_id == AMD_CPU_ID_PCO) {
137 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n");
138 return -EINVAL;
139 }
140
141 /* Get Active devices list from SMU */
142 if (!dev->active_ips)
143 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, true);
144
145 /* Get dram address */
146 if (!dev->smu_virt_addr) {
147 u32 phys_addr_low, phys_addr_hi;
148 u64 smu_phys_addr;
149
150 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, true);
151 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, true);
152 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
153
154 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr,
155 sizeof(struct smu_metrics));
156 if (!dev->smu_virt_addr)
157 return -ENOMEM;
158 }
159
160 memset_io(dev->smu_virt_addr, 0, sizeof(struct smu_metrics));
161
162 /* Start the logging */
163 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, false);
164 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, false);
165
166 return 0;
167 }
168
get_metrics_table(struct amd_pmc_dev * pdev,struct smu_metrics * table)169 static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table)
170 {
171 int rc;
172
173 if (!pdev->smu_virt_addr) {
174 rc = amd_pmc_setup_smu_logging(pdev);
175 if (rc)
176 return rc;
177 }
178
179 if (pdev->cpu_id == AMD_CPU_ID_PCO)
180 return -ENODEV;
181 memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics));
182 return 0;
183 }
184
amd_pmc_validate_deepest(struct amd_pmc_dev * pdev)185 static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev)
186 {
187 struct smu_metrics table;
188
189 if (get_metrics_table(pdev, &table))
190 return;
191
192 if (!table.s0i3_last_entry_status)
193 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n");
194 pm_report_hw_sleep_time(table.s0i3_last_entry_status ?
195 table.timein_s0i3_lastcapture : 0);
196 }
197
amd_pmc_get_smu_version(struct amd_pmc_dev * dev)198 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
199 {
200 int rc;
201 u32 val;
202
203 if (dev->cpu_id == AMD_CPU_ID_PCO)
204 return -ENODEV;
205
206 rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, true);
207 if (rc)
208 return rc;
209
210 dev->smu_program = (val >> 24) & GENMASK(7, 0);
211 dev->major = (val >> 16) & GENMASK(7, 0);
212 dev->minor = (val >> 8) & GENMASK(7, 0);
213 dev->rev = (val >> 0) & GENMASK(7, 0);
214
215 dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n",
216 dev->smu_program, dev->major, dev->minor, dev->rev);
217
218 return 0;
219 }
220
smu_fw_version_show(struct device * d,struct device_attribute * attr,char * buf)221 static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr,
222 char *buf)
223 {
224 struct amd_pmc_dev *dev = dev_get_drvdata(d);
225 int rc;
226
227 if (!dev->major) {
228 rc = amd_pmc_get_smu_version(dev);
229 if (rc)
230 return rc;
231 }
232 return sysfs_emit(buf, "%u.%u.%u\n", dev->major, dev->minor, dev->rev);
233 }
234
smu_program_show(struct device * d,struct device_attribute * attr,char * buf)235 static ssize_t smu_program_show(struct device *d, struct device_attribute *attr,
236 char *buf)
237 {
238 struct amd_pmc_dev *dev = dev_get_drvdata(d);
239 int rc;
240
241 if (!dev->major) {
242 rc = amd_pmc_get_smu_version(dev);
243 if (rc)
244 return rc;
245 }
246 return sysfs_emit(buf, "%u\n", dev->smu_program);
247 }
248
249 static DEVICE_ATTR_RO(smu_fw_version);
250 static DEVICE_ATTR_RO(smu_program);
251
pmc_attr_is_visible(struct kobject * kobj,struct attribute * attr,int idx)252 static umode_t pmc_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
253 {
254 struct device *dev = kobj_to_dev(kobj);
255 struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
256
257 if (pdev->cpu_id == AMD_CPU_ID_PCO)
258 return 0;
259 return 0444;
260 }
261
262 static struct attribute *pmc_attrs[] = {
263 &dev_attr_smu_fw_version.attr,
264 &dev_attr_smu_program.attr,
265 NULL,
266 };
267
268 static struct attribute_group pmc_attr_group = {
269 .attrs = pmc_attrs,
270 .is_visible = pmc_attr_is_visible,
271 };
272
273 static const struct attribute_group *pmc_groups[] = {
274 &pmc_attr_group,
275 NULL,
276 };
277
smu_fw_info_show(struct seq_file * s,void * unused)278 static int smu_fw_info_show(struct seq_file *s, void *unused)
279 {
280 struct amd_pmc_dev *dev = s->private;
281 struct smu_metrics table;
282 int idx;
283
284 if (get_metrics_table(dev, &table))
285 return -EINVAL;
286
287 seq_puts(s, "\n=== SMU Statistics ===\n");
288 seq_printf(s, "Table Version: %d\n", table.table_version);
289 seq_printf(s, "Hint Count: %d\n", table.hint_count);
290 seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
291 "Unknown/Fail");
292 seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
293 seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
294 seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
295 table.timeto_resume_to_os_lastcapture);
296
297 seq_puts(s, "\n=== Active time (in us) ===\n");
298 for (idx = 0 ; idx < dev->num_ips ; idx++) {
299 if (dev->ips_ptr[idx].bit_mask & dev->active_ips)
300 seq_printf(s, "%-8s : %lld\n", dev->ips_ptr[idx].name,
301 table.timecondition_notmet_lastcapture[idx]);
302 }
303
304 return 0;
305 }
306 DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
307
s0ix_stats_show(struct seq_file * s,void * unused)308 static int s0ix_stats_show(struct seq_file *s, void *unused)
309 {
310 struct amd_pmc_dev *dev = s->private;
311 u64 entry_time, exit_time, residency;
312
313 /* Use FCH registers to get the S0ix stats */
314 if (!dev->fch_virt_addr) {
315 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
316 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
317 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
318
319 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
320 if (!dev->fch_virt_addr)
321 return -ENOMEM;
322 }
323
324 entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
325 entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
326
327 exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
328 exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
329
330 /* It's in 48MHz. We need to convert it */
331 residency = exit_time - entry_time;
332 do_div(residency, 48);
333
334 seq_puts(s, "=== S0ix statistics ===\n");
335 seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
336 seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
337 seq_printf(s, "Residency Time: %lld\n", residency);
338
339 return 0;
340 }
341 DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
342
amd_pmc_idlemask_read(struct amd_pmc_dev * pdev,struct device * dev,struct seq_file * s)343 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
344 struct seq_file *s)
345 {
346 u32 val;
347 int rc;
348
349 switch (pdev->cpu_id) {
350 case AMD_CPU_ID_CZN:
351 /* we haven't yet read SMU version */
352 if (!pdev->major) {
353 rc = amd_pmc_get_smu_version(pdev);
354 if (rc)
355 return rc;
356 }
357 if (pdev->major > 56 || (pdev->major >= 55 && pdev->minor >= 37))
358 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
359 else
360 return -EINVAL;
361 break;
362 case AMD_CPU_ID_YC:
363 case AMD_CPU_ID_CB:
364 case AMD_CPU_ID_PS:
365 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
366 break;
367 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
368 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
369 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_1AH);
370 break;
371 default:
372 return -EINVAL;
373 }
374
375 if (dev)
376 pm_pr_dbg("SMU idlemask s0i3: 0x%x\n", val);
377
378 if (s)
379 seq_printf(s, "SMU idlemask : 0x%x\n", val);
380
381 return 0;
382 }
383
amd_pmc_idlemask_show(struct seq_file * s,void * unused)384 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
385 {
386 return amd_pmc_idlemask_read(s->private, NULL, s);
387 }
388 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
389
amd_pmc_dbgfs_unregister(struct amd_pmc_dev * dev)390 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
391 {
392 debugfs_remove_recursive(dev->dbgfs_dir);
393 }
394
amd_pmc_dbgfs_register(struct amd_pmc_dev * dev)395 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
396 {
397 dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
398 debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
399 &smu_fw_info_fops);
400 debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
401 &s0ix_stats_fops);
402 debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
403 &amd_pmc_idlemask_fops);
404 }
405
amd_pmc_get_msg_port(struct amd_pmc_dev * dev)406 static char *amd_pmc_get_msg_port(struct amd_pmc_dev *dev)
407 {
408 switch (dev->msg_port) {
409 case MSG_PORT_PMC:
410 return "PMC";
411 case MSG_PORT_S2D:
412 return "S2D";
413 default:
414 return "Invalid message port";
415 }
416 }
417
amd_pmc_dump_registers(struct amd_pmc_dev * dev)418 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
419 {
420 u32 value, message, argument, response;
421
422 if (dev->msg_port == MSG_PORT_S2D) {
423 message = dev->stb_arg.msg;
424 argument = dev->stb_arg.arg;
425 response = dev->stb_arg.resp;
426 } else {
427 message = dev->smu_msg;
428 argument = AMD_PMC_REGISTER_ARGUMENT;
429 response = AMD_PMC_REGISTER_RESPONSE;
430 }
431
432 value = amd_pmc_reg_read(dev, response);
433 dev_dbg(dev->dev, "AMD_%s_REGISTER_RESPONSE:%x\n", amd_pmc_get_msg_port(dev), value);
434
435 value = amd_pmc_reg_read(dev, argument);
436 dev_dbg(dev->dev, "AMD_%s_REGISTER_ARGUMENT:%x\n", amd_pmc_get_msg_port(dev), value);
437
438 value = amd_pmc_reg_read(dev, message);
439 dev_dbg(dev->dev, "AMD_%s_REGISTER_MESSAGE:%x\n", amd_pmc_get_msg_port(dev), value);
440 }
441
amd_pmc_send_cmd(struct amd_pmc_dev * dev,u32 arg,u32 * data,u8 msg,bool ret)442 int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
443 {
444 int rc;
445 u32 val, message, argument, response;
446
447 guard(mutex)(&dev->lock);
448
449 if (dev->msg_port == MSG_PORT_S2D) {
450 message = dev->stb_arg.msg;
451 argument = dev->stb_arg.arg;
452 response = dev->stb_arg.resp;
453 } else {
454 message = dev->smu_msg;
455 argument = AMD_PMC_REGISTER_ARGUMENT;
456 response = AMD_PMC_REGISTER_RESPONSE;
457 }
458
459 /* Wait until we get a valid response */
460 rc = readx_poll_timeout(ioread32, dev->regbase + response,
461 val, val != 0, PMC_MSG_DELAY_MIN_US,
462 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
463 if (rc) {
464 dev_err(dev->dev, "failed to talk to SMU\n");
465 return rc;
466 }
467
468 /* Write zero to response register */
469 amd_pmc_reg_write(dev, response, 0);
470
471 /* Write argument into response register */
472 amd_pmc_reg_write(dev, argument, arg);
473
474 /* Write message ID to message ID register */
475 amd_pmc_reg_write(dev, message, msg);
476
477 /* Wait until we get a valid response */
478 rc = readx_poll_timeout(ioread32, dev->regbase + response,
479 val, val != 0, PMC_MSG_DELAY_MIN_US,
480 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
481 if (rc) {
482 dev_err(dev->dev, "SMU response timed out\n");
483 return rc;
484 }
485
486 switch (val) {
487 case AMD_PMC_RESULT_OK:
488 if (ret) {
489 /* PMFW may take longer time to return back the data */
490 usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
491 *data = amd_pmc_reg_read(dev, argument);
492 }
493 break;
494 case AMD_PMC_RESULT_CMD_REJECT_BUSY:
495 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
496 rc = -EBUSY;
497 break;
498 case AMD_PMC_RESULT_CMD_UNKNOWN:
499 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
500 rc = -EINVAL;
501 break;
502 case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
503 case AMD_PMC_RESULT_FAILED:
504 default:
505 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
506 rc = -EIO;
507 break;
508 }
509
510 amd_pmc_dump_registers(dev);
511 return rc;
512 }
513
amd_pmc_get_os_hint(struct amd_pmc_dev * dev)514 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
515 {
516 switch (dev->cpu_id) {
517 case AMD_CPU_ID_PCO:
518 return MSG_OS_HINT_PCO;
519 case AMD_CPU_ID_RN:
520 case AMD_CPU_ID_YC:
521 case AMD_CPU_ID_CB:
522 case AMD_CPU_ID_PS:
523 case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
524 case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
525 return MSG_OS_HINT_RN;
526 }
527 return -EINVAL;
528 }
529
amd_pmc_wa_irq1(struct amd_pmc_dev * pdev)530 static int amd_pmc_wa_irq1(struct amd_pmc_dev *pdev)
531 {
532 struct device *d;
533 int rc;
534
535 /* cezanne platform firmware has a fix in 64.66.0 */
536 if (pdev->cpu_id == AMD_CPU_ID_CZN) {
537 if (!pdev->major) {
538 rc = amd_pmc_get_smu_version(pdev);
539 if (rc)
540 return rc;
541 }
542
543 if (pdev->major > 64 || (pdev->major == 64 && pdev->minor > 65))
544 return 0;
545 }
546
547 d = bus_find_device_by_name(&serio_bus, NULL, "serio0");
548 if (!d)
549 return 0;
550 if (device_may_wakeup(d)) {
551 dev_info_once(d, "Disabling IRQ1 wakeup source to avoid platform firmware bug\n");
552 disable_irq_wake(1);
553 device_set_wakeup_enable(d, false);
554 }
555 put_device(d);
556
557 return 0;
558 }
559
amd_pmc_verify_czn_rtc(struct amd_pmc_dev * pdev,u32 * arg)560 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
561 {
562 struct rtc_device *rtc_device;
563 time64_t then, now, duration;
564 struct rtc_wkalrm alarm;
565 struct rtc_time tm;
566 int rc;
567
568 /* we haven't yet read SMU version */
569 if (!pdev->major) {
570 rc = amd_pmc_get_smu_version(pdev);
571 if (rc)
572 return rc;
573 }
574
575 if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
576 return 0;
577
578 rtc_device = rtc_class_open("rtc0");
579 if (!rtc_device)
580 return 0;
581 rc = rtc_read_alarm(rtc_device, &alarm);
582 if (rc)
583 return rc;
584 if (!alarm.enabled) {
585 dev_dbg(pdev->dev, "alarm not enabled\n");
586 return 0;
587 }
588 rc = rtc_read_time(rtc_device, &tm);
589 if (rc)
590 return rc;
591 then = rtc_tm_to_time64(&alarm.time);
592 now = rtc_tm_to_time64(&tm);
593 duration = then-now;
594
595 /* in the past */
596 if (then < now)
597 return 0;
598
599 /* will be stored in upper 16 bits of s0i3 hint argument,
600 * so timer wakeup from s0i3 is limited to ~18 hours or less
601 */
602 if (duration <= 4 || duration > U16_MAX)
603 return -EINVAL;
604
605 *arg |= (duration << 16);
606 rc = rtc_alarm_irq_enable(rtc_device, 0);
607 pm_pr_dbg("wakeup timer programmed for %lld seconds\n", duration);
608
609 return rc;
610 }
611
amd_pmc_s2idle_prepare(void)612 static void amd_pmc_s2idle_prepare(void)
613 {
614 struct amd_pmc_dev *pdev = &pmc;
615 int rc;
616 u8 msg;
617 u32 arg = 1;
618
619 /* Reset and Start SMU logging - to monitor the s0i3 stats */
620 amd_pmc_setup_smu_logging(pdev);
621
622 /* Activate CZN specific platform bug workarounds */
623 if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) {
624 rc = amd_pmc_verify_czn_rtc(pdev, &arg);
625 if (rc) {
626 dev_err(pdev->dev, "failed to set RTC: %d\n", rc);
627 return;
628 }
629 }
630
631 msg = amd_pmc_get_os_hint(pdev);
632 rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, false);
633 if (rc) {
634 dev_err(pdev->dev, "suspend failed: %d\n", rc);
635 return;
636 }
637
638 rc = amd_stb_write(pdev, AMD_PMC_STB_S2IDLE_PREPARE);
639 if (rc)
640 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
641 }
642
amd_pmc_s2idle_check(void)643 static void amd_pmc_s2idle_check(void)
644 {
645 struct amd_pmc_dev *pdev = &pmc;
646 struct smu_metrics table;
647 int rc;
648
649 /* Avoid triggering OVP */
650 if (!get_metrics_table(pdev, &table) && table.s0i3_last_entry_status)
651 msleep(2500);
652
653 /* Dump the IdleMask before we add to the STB */
654 amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
655
656 rc = amd_stb_write(pdev, AMD_PMC_STB_S2IDLE_CHECK);
657 if (rc)
658 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
659 }
660
amd_pmc_dump_data(struct amd_pmc_dev * pdev)661 static int amd_pmc_dump_data(struct amd_pmc_dev *pdev)
662 {
663 if (pdev->cpu_id == AMD_CPU_ID_PCO)
664 return -ENODEV;
665
666 return amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, false);
667 }
668
amd_pmc_s2idle_restore(void)669 static void amd_pmc_s2idle_restore(void)
670 {
671 struct amd_pmc_dev *pdev = &pmc;
672 int rc;
673 u8 msg;
674
675 msg = amd_pmc_get_os_hint(pdev);
676 rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, false);
677 if (rc)
678 dev_err(pdev->dev, "resume failed: %d\n", rc);
679
680 /* Let SMU know that we are looking for stats */
681 amd_pmc_dump_data(pdev);
682
683 rc = amd_stb_write(pdev, AMD_PMC_STB_S2IDLE_RESTORE);
684 if (rc)
685 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
686
687 /* Notify on failed entry */
688 amd_pmc_validate_deepest(pdev);
689
690 amd_pmc_process_restore_quirks(pdev);
691 }
692
693 static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = {
694 .prepare = amd_pmc_s2idle_prepare,
695 .check = amd_pmc_s2idle_check,
696 .restore = amd_pmc_s2idle_restore,
697 };
698
amd_pmc_suspend_handler(struct device * dev)699 static int amd_pmc_suspend_handler(struct device *dev)
700 {
701 struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
702 int rc;
703
704 /*
705 * Must be called only from the same set of dev_pm_ops handlers
706 * as i8042_pm_suspend() is called: currently just from .suspend.
707 */
708 if (pdev->disable_8042_wakeup && !disable_workarounds) {
709 rc = amd_pmc_wa_irq1(pdev);
710 if (rc) {
711 dev_err(pdev->dev, "failed to adjust keyboard wakeup: %d\n", rc);
712 return rc;
713 }
714 }
715
716 return 0;
717 }
718
719 static const struct dev_pm_ops amd_pmc_pm = {
720 .suspend = amd_pmc_suspend_handler,
721 };
722
723 static const struct pci_device_id pmc_pci_ids[] = {
724 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) },
725 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CB) },
726 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
727 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
728 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
729 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
730 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
731 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
732 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SHP) },
733 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
734 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) },
735 { }
736 };
737
amd_pmc_probe(struct platform_device * pdev)738 static int amd_pmc_probe(struct platform_device *pdev)
739 {
740 struct amd_pmc_dev *dev = &pmc;
741 struct pci_dev *rdev;
742 u32 base_addr_lo, base_addr_hi;
743 u64 base_addr;
744 int err;
745 u32 val;
746
747 dev->dev = &pdev->dev;
748 rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
749 if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
750 err = -ENODEV;
751 goto err_pci_dev_put;
752 }
753
754 dev->cpu_id = rdev->device;
755 if (dev->cpu_id == AMD_CPU_ID_SP || dev->cpu_id == AMD_CPU_ID_SHP) {
756 dev_warn_once(dev->dev, "S0i3 is not supported on this hardware\n");
757 err = -ENODEV;
758 goto err_pci_dev_put;
759 }
760
761 dev->rdev = rdev;
762 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_LO, &val);
763 if (err) {
764 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_LO);
765 err = pcibios_err_to_errno(err);
766 goto err_pci_dev_put;
767 }
768
769 base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
770 err = amd_smn_read(0, AMD_PMC_BASE_ADDR_HI, &val);
771 if (err) {
772 dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_HI);
773 err = pcibios_err_to_errno(err);
774 goto err_pci_dev_put;
775 }
776
777 base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
778 base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
779
780 dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
781 AMD_PMC_MAPPING_SIZE);
782 if (!dev->regbase) {
783 err = -ENOMEM;
784 goto err_pci_dev_put;
785 }
786
787 err = devm_mutex_init(dev->dev, &dev->lock);
788 if (err)
789 goto err_pci_dev_put;
790
791 /* Get num of IP blocks within the SoC */
792 amd_pmc_get_ip_info(dev);
793
794 platform_set_drvdata(pdev, dev);
795 if (IS_ENABLED(CONFIG_SUSPEND)) {
796 err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
797 if (err)
798 dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n");
799 if (!disable_workarounds)
800 amd_pmc_quirks_init(dev);
801 }
802
803 amd_pmc_dbgfs_register(dev);
804 err = amd_stb_s2d_init(dev);
805 if (err)
806 goto err_pci_dev_put;
807
808 if (IS_ENABLED(CONFIG_AMD_MP2_STB))
809 amd_mp2_stb_init(dev);
810 pm_report_max_hw_sleep(U64_MAX);
811 return 0;
812
813 err_pci_dev_put:
814 pci_dev_put(rdev);
815 return err;
816 }
817
amd_pmc_remove(struct platform_device * pdev)818 static void amd_pmc_remove(struct platform_device *pdev)
819 {
820 struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
821
822 if (IS_ENABLED(CONFIG_SUSPEND))
823 acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops);
824 amd_pmc_dbgfs_unregister(dev);
825 pci_dev_put(dev->rdev);
826 if (IS_ENABLED(CONFIG_AMD_MP2_STB))
827 amd_mp2_stb_deinit(dev);
828 }
829
830 static const struct acpi_device_id amd_pmc_acpi_ids[] = {
831 {"AMDI0005", 0},
832 {"AMDI0006", 0},
833 {"AMDI0007", 0},
834 {"AMDI0008", 0},
835 {"AMDI0009", 0},
836 {"AMDI000A", 0},
837 {"AMDI000B", 0},
838 {"AMD0004", 0},
839 {"AMD0005", 0},
840 { }
841 };
842 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
843
844 static struct platform_driver amd_pmc_driver = {
845 .driver = {
846 .name = "amd_pmc",
847 .acpi_match_table = amd_pmc_acpi_ids,
848 .dev_groups = pmc_groups,
849 .pm = pm_sleep_ptr(&amd_pmc_pm),
850 },
851 .probe = amd_pmc_probe,
852 .remove = amd_pmc_remove,
853 };
854 module_platform_driver(amd_pmc_driver);
855
856 MODULE_LICENSE("GPL v2");
857 MODULE_DESCRIPTION("AMD PMC Driver");
858