1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
3
4 #ifndef __RTL_PCI_H__
5 #define __RTL_PCI_H__
6
7 #include <linux/pci.h>
8 /* 1: MSDU packet queue,
9 * 2: Rx Command Queue
10 */
11 #define RTL_PCI_RX_MPDU_QUEUE 0
12 #define RTL_PCI_RX_CMD_QUEUE 1
13 #define RTL_PCI_MAX_RX_QUEUE 2
14
15 #define RTL_PCI_MAX_RX_COUNT 512/*64*/
16 #define RTL_PCI_MAX_TX_QUEUE_COUNT 9
17
18 #define RT_TXDESC_NUM 128
19 #define TX_DESC_NUM_92E 512
20 #define TX_DESC_NUM_8822B 512
21 #define RT_TXDESC_NUM_BE_QUEUE 256
22
23 #define BK_QUEUE 0
24 #define BE_QUEUE 1
25 #define VI_QUEUE 2
26 #define VO_QUEUE 3
27 #define BEACON_QUEUE 4
28 #define TXCMD_QUEUE 5
29 #define MGNT_QUEUE 6
30 #define HIGH_QUEUE 7
31 #define HCCA_QUEUE 8
32 #define H2C_QUEUE TXCMD_QUEUE /* In 8822B */
33
34 #define RTL_PCI_DEVICE(vend, dev, cfg) \
35 .vendor = (vend), \
36 .device = (dev), \
37 .subvendor = PCI_ANY_ID, \
38 .subdevice = PCI_ANY_ID,\
39 .driver_data = (kernel_ulong_t)&(cfg)
40
41 #define INTEL_VENDOR_ID 0x8086
42 #define SIS_VENDOR_ID 0x1039
43 #define ATI_VENDOR_ID 0x1002
44 #define ATI_DEVICE_ID 0x7914
45 #define AMD_VENDOR_ID 0x1022
46
47 #define U1DONTCARE 0xFF
48 #define U2DONTCARE 0xFFFF
49 #define U4DONTCARE 0xFFFFFFFF
50
51 #define RTL_PCI_8192_DID 0x8192 /*8192 PCI-E */
52 #define RTL_PCI_8192SE_DID 0x8192 /*8192 SE */
53 #define RTL_PCI_8174_DID 0x8174 /*8192 SE */
54 #define RTL_PCI_8173_DID 0x8173 /*8191 SE Crab */
55 #define RTL_PCI_8172_DID 0x8172 /*8191 SE RE */
56 #define RTL_PCI_8171_DID 0x8171 /*8191 SE Unicron */
57 #define RTL_PCI_8723AE_DID 0x8723 /*8723AE */
58 #define RTL_PCI_0045_DID 0x0045 /*8190 PCI for Ceraga */
59 #define RTL_PCI_0046_DID 0x0046 /*8190 Cardbus for Ceraga */
60 #define RTL_PCI_0044_DID 0x0044 /*8192e PCIE for Ceraga */
61 #define RTL_PCI_0047_DID 0x0047 /*8192e Express Card for Ceraga */
62 #define RTL_PCI_700F_DID 0x700F
63 #define RTL_PCI_701F_DID 0x701F
64 #define RTL_PCI_DLINK_DID 0x3304
65 #define RTL_PCI_8723AE_DID 0x8723 /*8723e */
66 #define RTL_PCI_8192CET_DID 0x8191 /*8192ce */
67 #define RTL_PCI_8192CE_DID 0x8178 /*8192ce */
68 #define RTL_PCI_8191CE_DID 0x8177 /*8192ce */
69 #define RTL_PCI_8188CE_DID 0x8176 /*8192ce */
70 #define RTL_PCI_8192CU_DID 0x8191 /*8192ce */
71 #define RTL_PCI_8192DE_DID 0x8193 /*8192de */
72 #define RTL_PCI_8192DE_DID2 0x002B /*92DE*/
73 #define RTL_PCI_8188EE_DID 0x8179 /*8188ee*/
74 #define RTL_PCI_8723BE_DID 0xB723 /*8723be*/
75 #define RTL_PCI_8192EE_DID 0x818B /*8192ee*/
76 #define RTL_PCI_8821AE_DID 0x8821 /*8821ae*/
77 #define RTL_PCI_8812AE_DID 0x8812 /*8812ae*/
78 #define RTL_PCI_8822BE_DID 0xB822 /*8822be*/
79
80 /*8192 support 16 pages of IO registers*/
81 #define RTL_MEM_MAPPED_IO_RANGE_8190PCI 0x1000
82 #define RTL_MEM_MAPPED_IO_RANGE_8192PCIE 0x4000
83 #define RTL_MEM_MAPPED_IO_RANGE_8192SE 0x4000
84 #define RTL_MEM_MAPPED_IO_RANGE_8192CE 0x4000
85 #define RTL_MEM_MAPPED_IO_RANGE_8192DE 0x4000
86
87 #define RTL_PCI_REVISION_ID_8190PCI 0x00
88 #define RTL_PCI_REVISION_ID_8192PCIE 0x01
89 #define RTL_PCI_REVISION_ID_8192SE 0x10
90 #define RTL_PCI_REVISION_ID_8192CE 0x1
91 #define RTL_PCI_REVISION_ID_8192DE 0x0
92
93 #define RTL_DEFAULT_HARDWARE_TYPE HARDWARE_TYPE_RTL8192CE
94
95 enum pci_bridge_vendor {
96 PCI_BRIDGE_VENDOR_INTEL = 0x0, /*0b'0000,0001 */
97 PCI_BRIDGE_VENDOR_ATI, /*0b'0000,0010*/
98 PCI_BRIDGE_VENDOR_AMD, /*0b'0000,0100*/
99 PCI_BRIDGE_VENDOR_SIS, /*0b'0000,1000*/
100 PCI_BRIDGE_VENDOR_UNKNOWN, /*0b'0100,0000*/
101 PCI_BRIDGE_VENDOR_MAX,
102 };
103
104 /* In new TRX flow, Buffer_desc is new concept
105 * But TX wifi info == TX descriptor in old flow
106 * RX wifi info == RX descriptor in old flow
107 */
108 struct rtl_tx_buffer_desc {
109 u32 dword[4 * (1 << (BUFDESC_SEG_NUM + 1))];
110 } __packed;
111
112 struct rtl_tx_desc {
113 u32 dword[16];
114 } __packed;
115
116 struct rtl_rx_buffer_desc { /*rx buffer desc*/
117 u32 dword[4];
118 } __packed;
119
120 struct rtl_rx_desc { /*old: rx desc new: rx wifi info*/
121 u32 dword[8];
122 } __packed;
123
124 struct rtl_tx_cmd_desc {
125 u32 dword[16];
126 } __packed;
127
128 struct rtl8192_tx_ring {
129 struct rtl_tx_desc *desc;
130 dma_addr_t dma;
131 unsigned int idx;
132 unsigned int entries;
133 struct sk_buff_head queue;
134 /*add for new trx flow*/
135 struct rtl_tx_buffer_desc *buffer_desc; /*tx buffer descriptor*/
136 dma_addr_t buffer_desc_dma; /*tx bufferd desc dma memory*/
137 u16 cur_tx_wp; /* current_tx_write_point */
138 u16 cur_tx_rp; /* current_tx_read_point */
139 };
140
141 struct rtl8192_rx_ring {
142 struct rtl_rx_desc *desc;
143 dma_addr_t dma;
144 unsigned int idx;
145 struct sk_buff *rx_buf[RTL_PCI_MAX_RX_COUNT];
146 /*add for new trx flow*/
147 struct rtl_rx_buffer_desc *buffer_desc; /*rx buffer descriptor*/
148 u16 next_rx_rp; /* next_rx_read_point */
149 };
150
151 struct rtl_pci {
152 struct pci_dev *pdev;
153 bool irq_enabled;
154
155 bool driver_is_goingto_unload;
156 bool up_first_time;
157 bool first_init;
158 bool being_init_adapter;
159 bool init_ready;
160
161 /*Tx */
162 struct rtl8192_tx_ring tx_ring[RTL_PCI_MAX_TX_QUEUE_COUNT];
163 int txringcount[RTL_PCI_MAX_TX_QUEUE_COUNT];
164 u32 transmit_config;
165
166 /*Rx */
167 struct rtl8192_rx_ring rx_ring[RTL_PCI_MAX_RX_QUEUE];
168 int rxringcount;
169 u16 rxbuffersize;
170 u32 receive_config;
171
172 /*irq */
173 u8 irq_alloc;
174 u32 irq_mask[4]; /* 0-1: normal, 2: unused, 3: h2c */
175 u32 sys_irq_mask;
176
177 /*Bcn control register setting */
178 u32 reg_bcn_ctrl_val;
179
180 /*ASPM*/ u8 const_pci_aspm;
181 u8 const_hwsw_rfoff_d3;
182 u8 const_support_pciaspm;
183 /*pci-e bridge */
184 u8 const_hostpci_aspm_setting;
185 /*pci-e device */
186 u8 const_devicepci_aspm_setting;
187 /* If it supports ASPM, Offset[560h] = 0x40,
188 * otherwise Offset[560h] = 0x00.
189 */
190 bool support_aspm;
191 bool support_backdoor;
192
193 /*QOS & EDCA */
194 enum acm_method acm_method;
195
196 u16 shortretry_limit;
197 u16 longretry_limit;
198
199 /* MSI support */
200 bool msi_support;
201 bool using_msi;
202 /* interrupt clear before set */
203 bool int_clear;
204 };
205
206 struct mp_adapter {
207 u8 linkctrl_reg;
208
209 u8 busnumber;
210 u8 devnumber;
211 u8 funcnumber;
212
213 u8 pcibridge_busnum;
214 u8 pcibridge_devnum;
215 u8 pcibridge_funcnum;
216
217 u8 pcibridge_vendor;
218
219 bool amd_l1_patch;
220 };
221
222 struct rtl_pci_priv {
223 struct bt_coexist_info bt_coexist;
224 struct rtl_led_ctl ledctl;
225 struct rtl_pci dev;
226 struct mp_adapter ndis_adapter;
227 };
228
229 #define rtl_pcipriv(hw) (((struct rtl_pci_priv *)(rtl_priv(hw))->priv))
230 #define rtl_pcidev(pcipriv) (&((pcipriv)->dev))
231
232 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw);
233
234 extern const struct rtl_intf_ops rtl_pci_ops;
235
236 int rtl_pci_probe(struct pci_dev *pdev,
237 const struct pci_device_id *id);
238 void rtl_pci_disconnect(struct pci_dev *pdev);
239 #ifdef CONFIG_PM_SLEEP
240 int rtl_pci_suspend(struct device *dev);
241 int rtl_pci_resume(struct device *dev);
242 #endif /* CONFIG_PM_SLEEP */
pci_read8_sync(struct rtl_priv * rtlpriv,u32 addr)243 static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr)
244 {
245 return readb((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
246 }
247
pci_read16_sync(struct rtl_priv * rtlpriv,u32 addr)248 static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr)
249 {
250 return readw((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
251 }
252
pci_read32_sync(struct rtl_priv * rtlpriv,u32 addr)253 static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr)
254 {
255 return readl((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
256 }
257
pci_write8_async(struct rtl_priv * rtlpriv,u32 addr,u8 val)258 static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val)
259 {
260 writeb(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
261 }
262
pci_write16_async(struct rtl_priv * rtlpriv,u32 addr,u16 val)263 static inline void pci_write16_async(struct rtl_priv *rtlpriv,
264 u32 addr, u16 val)
265 {
266 writew(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
267 }
268
pci_write32_async(struct rtl_priv * rtlpriv,u32 addr,u32 val)269 static inline void pci_write32_async(struct rtl_priv *rtlpriv,
270 u32 addr, u32 val)
271 {
272 writel(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
273 }
274
calc_fifo_space(u16 rp,u16 wp,u16 size)275 static inline u16 calc_fifo_space(u16 rp, u16 wp, u16 size)
276 {
277 if (rp <= wp)
278 return size - 1 + rp - wp;
279 return rp - wp - 1;
280 }
281
282 #endif
283