1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2009-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 */
6
7 #ifndef AMD_IOMMU_H
8 #define AMD_IOMMU_H
9
10 #include <linux/iommu.h>
11
12 #include "amd_iommu_types.h"
13
14 extern int amd_iommu_evtlog_size;
15 extern int amd_iommu_pprlog_size;
16
17 irqreturn_t amd_iommu_int_thread(int irq, void *data);
18 irqreturn_t amd_iommu_int_thread_evtlog(int irq, void *data);
19 irqreturn_t amd_iommu_int_thread_pprlog(int irq, void *data);
20 irqreturn_t amd_iommu_int_thread_galog(int irq, void *data);
21 void amd_iommu_restart_log(struct amd_iommu *iommu, const char *evt_type,
22 u8 cntrl_intr, u8 cntrl_log,
23 u32 status_run_mask, u32 status_overflow_mask);
24 void amd_iommu_restart_event_logging(struct amd_iommu *iommu);
25 void amd_iommu_restart_ga_log(struct amd_iommu *iommu);
26 void amd_iommu_restart_ppr_log(struct amd_iommu *iommu);
27 void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid);
28 void iommu_feature_enable(struct amd_iommu *iommu, u8 bit);
29 void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu,
30 gfp_t gfp, size_t size);
31
32 #ifdef CONFIG_AMD_IOMMU_DEBUGFS
33 void amd_iommu_debugfs_setup(void);
34 #else
amd_iommu_debugfs_setup(void)35 static inline void amd_iommu_debugfs_setup(void) {}
36 #endif
37
38 /* Needed for interrupt remapping */
39 int amd_iommu_prepare(void);
40 int amd_iommu_enable(void);
41 void amd_iommu_disable(void);
42 int amd_iommu_reenable(int mode);
43 int amd_iommu_enable_faulting(unsigned int cpu);
44 extern int amd_iommu_guest_ir;
45 extern enum protection_domain_mode amd_iommu_pgtable;
46 extern int amd_iommu_gpt_level;
47 extern u8 amd_iommu_hpt_level;
48 extern unsigned long amd_iommu_pgsize_bitmap;
49 extern bool amd_iommu_hatdis;
50
51 /* Protection domain ops */
52 void amd_iommu_init_identity_domain(void);
53 struct protection_domain *protection_domain_alloc(void);
54 struct iommu_domain *amd_iommu_domain_alloc_sva(struct device *dev,
55 struct mm_struct *mm);
56 void amd_iommu_domain_free(struct iommu_domain *dom);
57 int iommu_sva_set_dev_pasid(struct iommu_domain *domain,
58 struct device *dev, ioasid_t pasid,
59 struct iommu_domain *old);
60 void amd_iommu_remove_dev_pasid(struct device *dev, ioasid_t pasid,
61 struct iommu_domain *domain);
62
63 /* SVA/PASID */
64 bool amd_iommu_pasid_supported(void);
65
66 /* IOPF */
67 int amd_iommu_iopf_init(struct amd_iommu *iommu);
68 void amd_iommu_iopf_uninit(struct amd_iommu *iommu);
69 void amd_iommu_page_response(struct device *dev, struct iopf_fault *evt,
70 struct iommu_page_response *resp);
71 int amd_iommu_iopf_add_device(struct amd_iommu *iommu,
72 struct iommu_dev_data *dev_data);
73 void amd_iommu_iopf_remove_device(struct amd_iommu *iommu,
74 struct iommu_dev_data *dev_data);
75
76 /* GCR3 setup */
77 int amd_iommu_set_gcr3(struct iommu_dev_data *dev_data,
78 ioasid_t pasid, unsigned long gcr3);
79 int amd_iommu_clear_gcr3(struct iommu_dev_data *dev_data, ioasid_t pasid);
80
81 /* PPR */
82 int __init amd_iommu_alloc_ppr_log(struct amd_iommu *iommu);
83 void __init amd_iommu_free_ppr_log(struct amd_iommu *iommu);
84 void amd_iommu_enable_ppr_log(struct amd_iommu *iommu);
85 void amd_iommu_poll_ppr_log(struct amd_iommu *iommu);
86 int amd_iommu_complete_ppr(struct device *dev, u32 pasid, int status, int tag);
87
88 /*
89 * This function flushes all internal caches of
90 * the IOMMU used by this driver.
91 */
92 void amd_iommu_flush_all_caches(struct amd_iommu *iommu);
93 void amd_iommu_domain_flush_pages(struct protection_domain *domain,
94 u64 address, size_t size);
95 void amd_iommu_dev_flush_pasid_pages(struct iommu_dev_data *dev_data,
96 ioasid_t pasid, u64 address, size_t size);
97
98 #ifdef CONFIG_IRQ_REMAP
99 int amd_iommu_create_irq_domain(struct amd_iommu *iommu);
100 #else
amd_iommu_create_irq_domain(struct amd_iommu * iommu)101 static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
102 {
103 return 0;
104 }
105 #endif
106
is_rd890_iommu(struct pci_dev * pdev)107 static inline bool is_rd890_iommu(struct pci_dev *pdev)
108 {
109 return (pdev->vendor == PCI_VENDOR_ID_ATI) &&
110 (pdev->device == PCI_DEVICE_ID_RD890_IOMMU);
111 }
112
check_feature(u64 mask)113 static inline bool check_feature(u64 mask)
114 {
115 return (amd_iommu_efr & mask);
116 }
117
check_feature2(u64 mask)118 static inline bool check_feature2(u64 mask)
119 {
120 return (amd_iommu_efr2 & mask);
121 }
122
amd_iommu_v2_pgtbl_supported(void)123 static inline bool amd_iommu_v2_pgtbl_supported(void)
124 {
125 return (check_feature(FEATURE_GIOSUP) && check_feature(FEATURE_GT));
126 }
127
amd_iommu_gt_ppr_supported(void)128 static inline bool amd_iommu_gt_ppr_supported(void)
129 {
130 return (amd_iommu_v2_pgtbl_supported() &&
131 check_feature(FEATURE_PPR) &&
132 check_feature(FEATURE_EPHSUP));
133 }
134
iommu_virt_to_phys(void * vaddr)135 static inline u64 iommu_virt_to_phys(void *vaddr)
136 {
137 return (u64)__sme_set(virt_to_phys(vaddr));
138 }
139
iommu_phys_to_virt(unsigned long paddr)140 static inline void *iommu_phys_to_virt(unsigned long paddr)
141 {
142 return phys_to_virt(__sme_clr(paddr));
143 }
144
get_pci_sbdf_id(struct pci_dev * pdev)145 static inline int get_pci_sbdf_id(struct pci_dev *pdev)
146 {
147 int seg = pci_domain_nr(pdev->bus);
148 u16 devid = pci_dev_id(pdev);
149
150 return PCI_SEG_DEVID_TO_SBDF(seg, devid);
151 }
152
153 bool amd_iommu_ht_range_ignore(void);
154
155 /*
156 * This must be called after device probe completes. During probe
157 * use rlookup_amd_iommu() get the iommu.
158 */
get_amd_iommu_from_dev(struct device * dev)159 static inline struct amd_iommu *get_amd_iommu_from_dev(struct device *dev)
160 {
161 return iommu_get_iommu_dev(dev, struct amd_iommu, iommu);
162 }
163
164 /* This must be called after device probe completes. */
get_amd_iommu_from_dev_data(struct iommu_dev_data * dev_data)165 static inline struct amd_iommu *get_amd_iommu_from_dev_data(struct iommu_dev_data *dev_data)
166 {
167 return iommu_get_iommu_dev(dev_data->dev, struct amd_iommu, iommu);
168 }
169
to_pdomain(struct iommu_domain * dom)170 static inline struct protection_domain *to_pdomain(struct iommu_domain *dom)
171 {
172 return container_of(dom, struct protection_domain, domain);
173 }
174
175 bool translation_pre_enabled(struct amd_iommu *iommu);
176 int __init add_special_device(u8 type, u8 id, u32 *devid, bool cmd_line);
177
178 int amd_iommu_pdom_id_alloc(void);
179 int amd_iommu_pdom_id_reserve(u16 id, gfp_t gfp);
180 void amd_iommu_pdom_id_free(int id);
181 void amd_iommu_pdom_id_destroy(void);
182
183 #ifdef CONFIG_DMI
184 void amd_iommu_apply_ivrs_quirks(void);
185 #else
amd_iommu_apply_ivrs_quirks(void)186 static inline void amd_iommu_apply_ivrs_quirks(void) { }
187 #endif
188 struct dev_table_entry *amd_iommu_get_ivhd_dte_flags(u16 segid, u16 devid);
189
190 void amd_iommu_domain_set_pgtable(struct protection_domain *domain,
191 u64 *root, int mode);
192 struct dev_table_entry *get_dev_table(struct amd_iommu *iommu);
193 struct iommu_dev_data *search_dev_data(struct amd_iommu *iommu, u16 devid);
194
195 void amd_iommu_set_dte_v1(struct iommu_dev_data *dev_data,
196 struct protection_domain *domain, u16 domid,
197 struct pt_iommu_amdv1_hw_info *pt_info,
198 struct dev_table_entry *new);
199 void amd_iommu_update_dte(struct amd_iommu *iommu,
200 struct iommu_dev_data *dev_data,
201 struct dev_table_entry *new);
202
203 static inline void
amd_iommu_make_clear_dte(struct iommu_dev_data * dev_data,struct dev_table_entry * new)204 amd_iommu_make_clear_dte(struct iommu_dev_data *dev_data, struct dev_table_entry *new)
205 {
206 struct dev_table_entry *initial_dte;
207 struct amd_iommu *iommu = get_amd_iommu_from_dev(dev_data->dev);
208
209 /* All existing DTE must have V bit set */
210 new->data128[0] = DTE_FLAG_V;
211 new->data128[1] = 0;
212
213 /*
214 * Restore cached persistent DTE bits, which can be set by information
215 * in IVRS table. See set_dev_entry_from_acpi().
216 */
217 initial_dte = amd_iommu_get_ivhd_dte_flags(iommu->pci_seg->id, dev_data->devid);
218 if (initial_dte) {
219 new->data128[0] |= initial_dte->data128[0];
220 new->data128[1] |= initial_dte->data128[1];
221 }
222 }
223
224 /* NESTED */
225 struct iommu_domain *
226 amd_iommu_alloc_domain_nested(struct iommufd_viommu *viommu, u32 flags,
227 const struct iommu_user_data *user_data);
228 #endif /* AMD_IOMMU_H */
229