1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/log2.h> 35 #include <linux/etherdevice.h> 36 #include <net/ip.h> 37 #include <linux/slab.h> 38 #include <linux/netdevice.h> 39 40 #include <rdma/ib_cache.h> 41 #include <rdma/ib_pack.h> 42 #include <rdma/ib_addr.h> 43 #include <rdma/ib_mad.h> 44 #include <rdma/uverbs_ioctl.h> 45 46 #include <linux/mlx4/driver.h> 47 #include <linux/mlx4/qp.h> 48 49 #include "mlx4_ib.h" 50 #include <rdma/mlx4-abi.h> 51 52 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, 53 struct mlx4_ib_cq *recv_cq); 54 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, 55 struct mlx4_ib_cq *recv_cq); 56 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state, 57 struct ib_udata *udata); 58 59 enum { 60 MLX4_IB_ACK_REQ_FREQ = 8, 61 }; 62 63 enum { 64 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83, 65 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 66 MLX4_IB_LINK_TYPE_IB = 0, 67 MLX4_IB_LINK_TYPE_ETH = 1 68 }; 69 70 enum { 71 MLX4_IB_MIN_SQ_STRIDE = 6, 72 MLX4_IB_CACHE_LINE_SIZE = 64, 73 }; 74 75 enum { 76 MLX4_RAW_QP_MTU = 7, 77 MLX4_RAW_QP_MSGMAX = 31, 78 }; 79 80 #ifndef ETH_ALEN 81 #define ETH_ALEN 6 82 #endif 83 84 static const __be32 mlx4_ib_opcode[] = { 85 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND), 86 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO), 87 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM), 88 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE), 89 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM), 90 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ), 91 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS), 92 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA), 93 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL), 94 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL), 95 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR), 96 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS), 97 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA), 98 }; 99 100 enum mlx4_ib_source_type { 101 MLX4_IB_QP_SRC = 0, 102 MLX4_IB_RWQ_SRC = 1, 103 }; 104 105 struct mlx4_ib_qp_event_work { 106 struct work_struct work; 107 struct mlx4_qp *qp; 108 enum mlx4_event type; 109 }; 110 111 static struct workqueue_struct *mlx4_ib_qp_event_wq; 112 113 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 114 { 115 if (!mlx4_is_master(dev->dev)) 116 return 0; 117 118 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn && 119 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn + 120 8 * MLX4_MFUNC_MAX; 121 } 122 123 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 124 { 125 int proxy_sqp = 0; 126 int real_sqp = 0; 127 int i; 128 /* PPF or Native -- real SQP */ 129 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 130 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 131 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3); 132 if (real_sqp) 133 return 1; 134 /* VF or PF -- proxy SQP */ 135 if (mlx4_is_mfunc(dev->dev)) { 136 for (i = 0; i < dev->dev->caps.num_ports; i++) { 137 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy || 138 qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) { 139 proxy_sqp = 1; 140 break; 141 } 142 } 143 } 144 if (proxy_sqp) 145 return 1; 146 147 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP); 148 } 149 150 /* used for INIT/CLOSE port logic */ 151 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 152 { 153 int proxy_qp0 = 0; 154 int real_qp0 = 0; 155 int i; 156 /* PPF or Native -- real QP0 */ 157 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 158 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 159 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1); 160 if (real_qp0) 161 return 1; 162 /* VF or PF -- proxy QP0 */ 163 if (mlx4_is_mfunc(dev->dev)) { 164 for (i = 0; i < dev->dev->caps.num_ports; i++) { 165 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) { 166 proxy_qp0 = 1; 167 break; 168 } 169 } 170 } 171 return proxy_qp0; 172 } 173 174 static void *get_wqe(struct mlx4_ib_qp *qp, int offset) 175 { 176 return mlx4_buf_offset(&qp->buf, offset); 177 } 178 179 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n) 180 { 181 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 182 } 183 184 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n) 185 { 186 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift)); 187 } 188 189 /* 190 * Stamp a SQ WQE so that it is invalid if prefetched by marking the 191 * first four bytes of every 64 byte chunk with 0xffffffff, except for 192 * the very first chunk of the WQE. 193 */ 194 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n) 195 { 196 __be32 *wqe; 197 int i; 198 int s; 199 void *buf; 200 struct mlx4_wqe_ctrl_seg *ctrl; 201 202 buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); 203 ctrl = (struct mlx4_wqe_ctrl_seg *)buf; 204 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4; 205 for (i = 64; i < s; i += 64) { 206 wqe = buf + i; 207 *wqe = cpu_to_be32(0xffffffff); 208 } 209 } 210 211 static void mlx4_ib_handle_qp_event(struct work_struct *_work) 212 { 213 struct mlx4_ib_qp_event_work *qpe_work = 214 container_of(_work, struct mlx4_ib_qp_event_work, work); 215 struct ib_qp *ibqp = &to_mibqp(qpe_work->qp)->ibqp; 216 struct ib_event event = {}; 217 218 event.device = ibqp->device; 219 event.element.qp = ibqp; 220 221 switch (qpe_work->type) { 222 case MLX4_EVENT_TYPE_PATH_MIG: 223 event.event = IB_EVENT_PATH_MIG; 224 break; 225 case MLX4_EVENT_TYPE_COMM_EST: 226 event.event = IB_EVENT_COMM_EST; 227 break; 228 case MLX4_EVENT_TYPE_SQ_DRAINED: 229 event.event = IB_EVENT_SQ_DRAINED; 230 break; 231 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: 232 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 233 break; 234 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: 235 event.event = IB_EVENT_QP_FATAL; 236 break; 237 case MLX4_EVENT_TYPE_PATH_MIG_FAILED: 238 event.event = IB_EVENT_PATH_MIG_ERR; 239 break; 240 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 241 event.event = IB_EVENT_QP_REQ_ERR; 242 break; 243 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: 244 event.event = IB_EVENT_QP_ACCESS_ERR; 245 break; 246 default: 247 pr_warn("Unexpected event type %d on QP %06x\n", 248 qpe_work->type, qpe_work->qp->qpn); 249 goto out; 250 } 251 252 ibqp->event_handler(&event, ibqp->qp_context); 253 254 out: 255 mlx4_put_qp(qpe_work->qp); 256 kfree(qpe_work); 257 } 258 259 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type) 260 { 261 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 262 struct mlx4_ib_qp_event_work *qpe_work; 263 264 if (type == MLX4_EVENT_TYPE_PATH_MIG) 265 to_mibqp(qp)->port = to_mibqp(qp)->alt_port; 266 267 if (!ibqp->event_handler) 268 goto out_no_handler; 269 270 qpe_work = kzalloc_obj(*qpe_work, GFP_ATOMIC); 271 if (!qpe_work) 272 goto out_no_handler; 273 274 qpe_work->qp = qp; 275 qpe_work->type = type; 276 INIT_WORK(&qpe_work->work, mlx4_ib_handle_qp_event); 277 queue_work(mlx4_ib_qp_event_wq, &qpe_work->work); 278 return; 279 280 out_no_handler: 281 mlx4_put_qp(qp); 282 } 283 284 static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type) 285 { 286 pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n", 287 type, qp->qpn); 288 } 289 290 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags) 291 { 292 /* 293 * UD WQEs must have a datagram segment. 294 * RC and UC WQEs might have a remote address segment. 295 * MLX WQEs need two extra inline data segments (for the UD 296 * header and space for the ICRC). 297 */ 298 switch (type) { 299 case MLX4_IB_QPT_UD: 300 return sizeof (struct mlx4_wqe_ctrl_seg) + 301 sizeof (struct mlx4_wqe_datagram_seg) + 302 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0); 303 case MLX4_IB_QPT_PROXY_SMI_OWNER: 304 case MLX4_IB_QPT_PROXY_SMI: 305 case MLX4_IB_QPT_PROXY_GSI: 306 return sizeof (struct mlx4_wqe_ctrl_seg) + 307 sizeof (struct mlx4_wqe_datagram_seg) + 64; 308 case MLX4_IB_QPT_TUN_SMI_OWNER: 309 case MLX4_IB_QPT_TUN_GSI: 310 return sizeof (struct mlx4_wqe_ctrl_seg) + 311 sizeof (struct mlx4_wqe_datagram_seg); 312 313 case MLX4_IB_QPT_UC: 314 return sizeof (struct mlx4_wqe_ctrl_seg) + 315 sizeof (struct mlx4_wqe_raddr_seg); 316 case MLX4_IB_QPT_RC: 317 return sizeof (struct mlx4_wqe_ctrl_seg) + 318 sizeof (struct mlx4_wqe_masked_atomic_seg) + 319 sizeof (struct mlx4_wqe_raddr_seg); 320 case MLX4_IB_QPT_SMI: 321 case MLX4_IB_QPT_GSI: 322 return sizeof (struct mlx4_wqe_ctrl_seg) + 323 ALIGN(MLX4_IB_UD_HEADER_SIZE + 324 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE, 325 MLX4_INLINE_ALIGN) * 326 sizeof (struct mlx4_wqe_inline_seg), 327 sizeof (struct mlx4_wqe_data_seg)) + 328 ALIGN(4 + 329 sizeof (struct mlx4_wqe_inline_seg), 330 sizeof (struct mlx4_wqe_data_seg)); 331 default: 332 return sizeof (struct mlx4_wqe_ctrl_seg); 333 } 334 } 335 336 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 337 bool is_user, bool has_rq, struct mlx4_ib_qp *qp, 338 u32 inl_recv_sz) 339 { 340 /* Sanity check RQ size before proceeding */ 341 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE || 342 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg)) 343 return -EINVAL; 344 345 if (!has_rq) { 346 if (cap->max_recv_wr || inl_recv_sz) 347 return -EINVAL; 348 349 qp->rq.wqe_cnt = qp->rq.max_gs = 0; 350 } else { 351 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg * 352 sizeof(struct mlx4_wqe_data_seg); 353 u32 wqe_size; 354 355 /* HW requires >= 1 RQ entry with >= 1 gather entry */ 356 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge || 357 inl_recv_sz > max_inl_recv_sz)) 358 return -EINVAL; 359 360 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr)); 361 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge)); 362 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg); 363 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz)); 364 } 365 366 /* leave userspace return values as they were, so as not to break ABI */ 367 if (is_user) { 368 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt; 369 cap->max_recv_sge = qp->rq.max_gs; 370 } else { 371 cap->max_recv_wr = qp->rq.max_post = 372 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt); 373 cap->max_recv_sge = min(qp->rq.max_gs, 374 min(dev->dev->caps.max_sq_sg, 375 dev->dev->caps.max_rq_sg)); 376 } 377 378 return 0; 379 } 380 381 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 382 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp) 383 { 384 int s; 385 386 /* Sanity check SQ size before proceeding */ 387 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) || 388 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) || 389 cap->max_inline_data + send_wqe_overhead(type, qp->flags) + 390 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz) 391 return -EINVAL; 392 393 /* 394 * For MLX transport we need 2 extra S/G entries: 395 * one for the header and one for the checksum at the end 396 */ 397 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI || 398 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) && 399 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg) 400 return -EINVAL; 401 402 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg), 403 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) + 404 send_wqe_overhead(type, qp->flags); 405 406 if (s > dev->dev->caps.max_sq_desc_sz) 407 return -EINVAL; 408 409 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s)); 410 411 /* 412 * We need to leave 2 KB + 1 WR of headroom in the SQ to 413 * allow HW to prefetch. 414 */ 415 qp->sq_spare_wqes = MLX4_IB_SQ_HEADROOM(qp->sq.wqe_shift); 416 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr + 417 qp->sq_spare_wqes); 418 419 qp->sq.max_gs = 420 (min(dev->dev->caps.max_sq_desc_sz, 421 (1 << qp->sq.wqe_shift)) - 422 send_wqe_overhead(type, qp->flags)) / 423 sizeof (struct mlx4_wqe_data_seg); 424 425 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 426 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 427 if (qp->rq.wqe_shift > qp->sq.wqe_shift) { 428 qp->rq.offset = 0; 429 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 430 } else { 431 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift; 432 qp->sq.offset = 0; 433 } 434 435 cap->max_send_wr = qp->sq.max_post = 436 qp->sq.wqe_cnt - qp->sq_spare_wqes; 437 cap->max_send_sge = min(qp->sq.max_gs, 438 min(dev->dev->caps.max_sq_sg, 439 dev->dev->caps.max_rq_sg)); 440 /* We don't support inline sends for kernel QPs (yet) */ 441 cap->max_inline_data = 0; 442 443 return 0; 444 } 445 446 static int set_user_sq_size(struct mlx4_ib_dev *dev, 447 struct mlx4_ib_qp *qp, 448 struct mlx4_ib_create_qp *ucmd) 449 { 450 u32 cnt; 451 452 /* Sanity check SQ size before proceeding */ 453 if (check_shl_overflow(1, ucmd->log_sq_bb_count, &cnt) || 454 cnt > dev->dev->caps.max_wqes) 455 return -EINVAL; 456 if (ucmd->log_sq_stride > 457 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) || 458 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE) 459 return -EINVAL; 460 461 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count; 462 qp->sq.wqe_shift = ucmd->log_sq_stride; 463 464 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 465 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 466 467 return 0; 468 } 469 470 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 471 { 472 int i; 473 474 qp->sqp_proxy_rcv = 475 kmalloc_objs(struct mlx4_ib_buf, qp->rq.wqe_cnt); 476 if (!qp->sqp_proxy_rcv) 477 return -ENOMEM; 478 for (i = 0; i < qp->rq.wqe_cnt; i++) { 479 qp->sqp_proxy_rcv[i].addr = 480 kmalloc_obj(struct mlx4_ib_proxy_sqp_hdr); 481 if (!qp->sqp_proxy_rcv[i].addr) 482 goto err; 483 qp->sqp_proxy_rcv[i].map = 484 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr, 485 sizeof (struct mlx4_ib_proxy_sqp_hdr), 486 DMA_FROM_DEVICE); 487 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) { 488 kfree(qp->sqp_proxy_rcv[i].addr); 489 goto err; 490 } 491 } 492 return 0; 493 494 err: 495 while (i > 0) { 496 --i; 497 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 498 sizeof (struct mlx4_ib_proxy_sqp_hdr), 499 DMA_FROM_DEVICE); 500 kfree(qp->sqp_proxy_rcv[i].addr); 501 } 502 kfree(qp->sqp_proxy_rcv); 503 qp->sqp_proxy_rcv = NULL; 504 return -ENOMEM; 505 } 506 507 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 508 { 509 int i; 510 511 for (i = 0; i < qp->rq.wqe_cnt; i++) { 512 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 513 sizeof (struct mlx4_ib_proxy_sqp_hdr), 514 DMA_FROM_DEVICE); 515 kfree(qp->sqp_proxy_rcv[i].addr); 516 } 517 kfree(qp->sqp_proxy_rcv); 518 } 519 520 static bool qp_has_rq(struct ib_qp_init_attr *attr) 521 { 522 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT) 523 return false; 524 525 return !attr->srq; 526 } 527 528 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn) 529 { 530 int i; 531 for (i = 0; i < dev->caps.num_ports; i++) { 532 if (qpn == dev->caps.spec_qps[i].qp0_proxy) 533 return !!dev->caps.spec_qps[i].qp0_qkey; 534 } 535 return 0; 536 } 537 538 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev, 539 struct mlx4_ib_qp *qp) 540 { 541 mutex_lock(&dev->counters_table[qp->port - 1].mutex); 542 mlx4_counter_free(dev->dev, qp->counter_index->index); 543 list_del(&qp->counter_index->list); 544 mutex_unlock(&dev->counters_table[qp->port - 1].mutex); 545 546 kfree(qp->counter_index); 547 qp->counter_index = NULL; 548 } 549 550 static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx, 551 struct ib_qp_init_attr *init_attr, 552 struct mlx4_ib_create_qp_rss *ucmd) 553 { 554 rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num | 555 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24); 556 557 if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) && 558 (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) { 559 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key, 560 MLX4_EN_RSS_KEY_SIZE); 561 } else { 562 pr_debug("RX Hash function is not supported\n"); 563 return (-EOPNOTSUPP); 564 } 565 566 if (ucmd->rx_hash_fields_mask & ~(u64)(MLX4_IB_RX_HASH_SRC_IPV4 | 567 MLX4_IB_RX_HASH_DST_IPV4 | 568 MLX4_IB_RX_HASH_SRC_IPV6 | 569 MLX4_IB_RX_HASH_DST_IPV6 | 570 MLX4_IB_RX_HASH_SRC_PORT_TCP | 571 MLX4_IB_RX_HASH_DST_PORT_TCP | 572 MLX4_IB_RX_HASH_SRC_PORT_UDP | 573 MLX4_IB_RX_HASH_DST_PORT_UDP | 574 MLX4_IB_RX_HASH_INNER)) { 575 pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n", 576 ucmd->rx_hash_fields_mask); 577 return (-EOPNOTSUPP); 578 } 579 580 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) && 581 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) { 582 rss_ctx->flags = MLX4_RSS_IPV4; 583 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) || 584 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) { 585 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n"); 586 return (-EOPNOTSUPP); 587 } 588 589 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) && 590 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) { 591 rss_ctx->flags |= MLX4_RSS_IPV6; 592 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) || 593 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) { 594 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n"); 595 return (-EOPNOTSUPP); 596 } 597 598 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) && 599 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) { 600 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) { 601 pr_debug("RX Hash fields_mask for UDP is not supported\n"); 602 return (-EOPNOTSUPP); 603 } 604 605 if (rss_ctx->flags & MLX4_RSS_IPV4) 606 rss_ctx->flags |= MLX4_RSS_UDP_IPV4; 607 if (rss_ctx->flags & MLX4_RSS_IPV6) 608 rss_ctx->flags |= MLX4_RSS_UDP_IPV6; 609 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) { 610 pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n"); 611 return (-EOPNOTSUPP); 612 } 613 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) || 614 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) { 615 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n"); 616 return (-EOPNOTSUPP); 617 } 618 619 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) && 620 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) { 621 if (rss_ctx->flags & MLX4_RSS_IPV4) 622 rss_ctx->flags |= MLX4_RSS_TCP_IPV4; 623 if (rss_ctx->flags & MLX4_RSS_IPV6) 624 rss_ctx->flags |= MLX4_RSS_TCP_IPV6; 625 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) { 626 pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n"); 627 return (-EOPNOTSUPP); 628 } 629 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) || 630 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) { 631 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n"); 632 return (-EOPNOTSUPP); 633 } 634 635 if (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_INNER) { 636 if (dev->dev->caps.tunnel_offload_mode == 637 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 638 /* 639 * Hash according to inner headers if exist, otherwise 640 * according to outer headers. 641 */ 642 rss_ctx->flags |= MLX4_RSS_BY_INNER_HEADERS_IPONLY; 643 } else { 644 pr_debug("RSS Hash for inner headers isn't supported\n"); 645 return (-EOPNOTSUPP); 646 } 647 } 648 649 return 0; 650 } 651 652 static int create_qp_rss(struct mlx4_ib_dev *dev, 653 struct ib_qp_init_attr *init_attr, 654 struct mlx4_ib_create_qp_rss *ucmd, 655 struct mlx4_ib_qp *qp) 656 { 657 int qpn; 658 int err; 659 660 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS; 661 662 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage); 663 if (err) 664 return err; 665 666 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp); 667 if (err) 668 goto err_qpn; 669 670 INIT_LIST_HEAD(&qp->gid_list); 671 INIT_LIST_HEAD(&qp->steering_rules); 672 673 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET; 674 qp->state = IB_QPS_RESET; 675 676 /* Set dummy send resources to be compatible with HV and PRM */ 677 qp->sq_no_prefetch = 1; 678 qp->sq.wqe_cnt = 1; 679 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE; 680 qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE; 681 qp->mtt = (to_mqp( 682 (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt; 683 684 qp->rss_ctx = kzalloc_obj(*qp->rss_ctx); 685 if (!qp->rss_ctx) { 686 err = -ENOMEM; 687 goto err_qp_alloc; 688 } 689 690 err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd); 691 if (err) 692 goto err; 693 694 return 0; 695 696 err: 697 kfree(qp->rss_ctx); 698 699 err_qp_alloc: 700 mlx4_qp_remove(dev->dev, &qp->mqp); 701 mlx4_qp_free(dev->dev, &qp->mqp); 702 703 err_qpn: 704 mlx4_qp_release_range(dev->dev, qpn, 1); 705 return err; 706 } 707 708 static int _mlx4_ib_create_qp_rss(struct ib_pd *pd, struct mlx4_ib_qp *qp, 709 struct ib_qp_init_attr *init_attr, 710 struct ib_udata *udata) 711 { 712 struct mlx4_ib_create_qp_rss ucmd = {}; 713 size_t required_cmd_sz; 714 int err; 715 716 if (!udata) { 717 pr_debug("RSS QP with NULL udata\n"); 718 return -EINVAL; 719 } 720 721 if (udata->outlen) 722 return -EOPNOTSUPP; 723 724 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + 725 sizeof(ucmd.reserved1); 726 if (udata->inlen < required_cmd_sz) { 727 pr_debug("invalid inlen\n"); 728 return -EINVAL; 729 } 730 731 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 732 pr_debug("copy failed\n"); 733 return -EFAULT; 734 } 735 736 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved))) 737 return -EOPNOTSUPP; 738 739 if (ucmd.comp_mask || ucmd.reserved1) 740 return -EOPNOTSUPP; 741 742 if (udata->inlen > sizeof(ucmd) && 743 !ib_is_udata_cleared(udata, sizeof(ucmd), 744 udata->inlen - sizeof(ucmd))) { 745 pr_debug("inlen is not supported\n"); 746 return -EOPNOTSUPP; 747 } 748 749 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 750 pr_debug("RSS QP with unsupported QP type %d\n", 751 init_attr->qp_type); 752 return -EOPNOTSUPP; 753 } 754 755 if (init_attr->create_flags) { 756 pr_debug("RSS QP doesn't support create flags\n"); 757 return -EOPNOTSUPP; 758 } 759 760 if (init_attr->send_cq || init_attr->cap.max_send_wr) { 761 pr_debug("RSS QP with unsupported send attributes\n"); 762 return -EOPNOTSUPP; 763 } 764 765 qp->pri.vid = 0xFFFF; 766 qp->alt.vid = 0xFFFF; 767 768 err = create_qp_rss(to_mdev(pd->device), init_attr, &ucmd, qp); 769 if (err) 770 return err; 771 772 qp->ibqp.qp_num = qp->mqp.qpn; 773 return 0; 774 } 775 776 /* 777 * This function allocates a WQN from a range which is consecutive and aligned 778 * to its size. In case the range is full, then it creates a new range and 779 * allocates WQN from it. The new range will be used for following allocations. 780 */ 781 static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context, 782 struct mlx4_ib_qp *qp, int range_size, int *wqn) 783 { 784 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device); 785 struct mlx4_wqn_range *range; 786 int err = 0; 787 788 mutex_lock(&context->wqn_ranges_mutex); 789 790 range = list_first_entry_or_null(&context->wqn_ranges_list, 791 struct mlx4_wqn_range, list); 792 793 if (!range || (range->refcount == range->size) || range->dirty) { 794 range = kzalloc_obj(*range); 795 if (!range) { 796 err = -ENOMEM; 797 goto out; 798 } 799 800 err = mlx4_qp_reserve_range(dev->dev, range_size, 801 range_size, &range->base_wqn, 0, 802 qp->mqp.usage); 803 if (err) { 804 kfree(range); 805 goto out; 806 } 807 808 range->size = range_size; 809 list_add(&range->list, &context->wqn_ranges_list); 810 } else if (range_size != 1) { 811 /* 812 * Requesting a new range (>1) when last range is still open, is 813 * not valid. 814 */ 815 err = -EINVAL; 816 goto out; 817 } 818 819 qp->wqn_range = range; 820 821 *wqn = range->base_wqn + range->refcount; 822 823 range->refcount++; 824 825 out: 826 mutex_unlock(&context->wqn_ranges_mutex); 827 828 return err; 829 } 830 831 static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context, 832 struct mlx4_ib_qp *qp, bool dirty_release) 833 { 834 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device); 835 struct mlx4_wqn_range *range; 836 837 mutex_lock(&context->wqn_ranges_mutex); 838 839 range = qp->wqn_range; 840 841 range->refcount--; 842 if (!range->refcount) { 843 mlx4_qp_release_range(dev->dev, range->base_wqn, 844 range->size); 845 list_del(&range->list); 846 kfree(range); 847 } else if (dirty_release) { 848 /* 849 * A range which one of its WQNs is destroyed, won't be able to be 850 * reused for further WQN allocations. 851 * The next created WQ will allocate a new range. 852 */ 853 range->dirty = true; 854 } 855 856 mutex_unlock(&context->wqn_ranges_mutex); 857 } 858 859 static int create_rq(struct ib_pd *pd, struct ib_qp_init_attr *init_attr, 860 struct ib_udata *udata, struct mlx4_ib_qp *qp) 861 { 862 struct mlx4_ib_dev *dev = to_mdev(pd->device); 863 int qpn; 864 int err; 865 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context( 866 udata, struct mlx4_ib_ucontext, ibucontext); 867 struct mlx4_ib_cq *mcq; 868 unsigned long flags; 869 int range_size; 870 struct mlx4_ib_create_wq wq; 871 size_t copy_len; 872 int shift; 873 int n; 874 875 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET; 876 877 spin_lock_init(&qp->sq.lock); 878 spin_lock_init(&qp->rq.lock); 879 INIT_LIST_HEAD(&qp->gid_list); 880 INIT_LIST_HEAD(&qp->steering_rules); 881 882 qp->state = IB_QPS_RESET; 883 884 copy_len = min(sizeof(struct mlx4_ib_create_wq), udata->inlen); 885 886 if (ib_copy_from_udata(&wq, udata, copy_len)) { 887 err = -EFAULT; 888 goto err; 889 } 890 891 if (wq.comp_mask || wq.reserved[0] || wq.reserved[1] || 892 wq.reserved[2]) { 893 pr_debug("user command isn't supported\n"); 894 err = -EOPNOTSUPP; 895 goto err; 896 } 897 898 if (wq.log_range_size > ilog2(dev->dev->caps.max_rss_tbl_sz)) { 899 pr_debug("WQN range size must be equal or smaller than %d\n", 900 dev->dev->caps.max_rss_tbl_sz); 901 err = -EOPNOTSUPP; 902 goto err; 903 } 904 range_size = 1 << wq.log_range_size; 905 906 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) 907 qp->flags |= MLX4_IB_QP_SCATTER_FCS; 908 909 err = set_rq_size(dev, &init_attr->cap, true, true, qp, qp->inl_recv_sz); 910 if (err) 911 goto err; 912 913 qp->sq_no_prefetch = 1; 914 qp->sq.wqe_cnt = 1; 915 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE; 916 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 917 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 918 919 qp->umem = ib_umem_get(pd->device, wq.buf_addr, qp->buf_size, 0); 920 if (IS_ERR(qp->umem)) { 921 err = PTR_ERR(qp->umem); 922 goto err; 923 } 924 925 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n); 926 if (shift < 0) { 927 err = shift; 928 goto err_buf; 929 } 930 931 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt); 932 if (err) 933 goto err_buf; 934 935 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem); 936 if (err) 937 goto err_mtt; 938 939 err = mlx4_ib_db_map_user(udata, wq.db_addr, &qp->db); 940 if (err) 941 goto err_mtt; 942 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS; 943 944 err = mlx4_ib_alloc_wqn(context, qp, range_size, &qpn); 945 if (err) 946 goto err_wrid; 947 948 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp); 949 if (err) 950 goto err_qpn; 951 952 /* 953 * Hardware wants QPN written in big-endian order (after 954 * shifting) for send doorbell. Precompute this value to save 955 * a little bit when posting sends. 956 */ 957 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8); 958 959 qp->mqp.event = mlx4_ib_wq_event; 960 961 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 962 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq), 963 to_mcq(init_attr->recv_cq)); 964 /* Maintain device to QPs access, needed for further handling 965 * via reset flow 966 */ 967 list_add_tail(&qp->qps_list, &dev->qp_list); 968 /* Maintain CQ to QPs access, needed for further handling 969 * via reset flow 970 */ 971 mcq = to_mcq(init_attr->send_cq); 972 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list); 973 mcq = to_mcq(init_attr->recv_cq); 974 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list); 975 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq), 976 to_mcq(init_attr->recv_cq)); 977 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 978 return 0; 979 980 err_qpn: 981 mlx4_ib_release_wqn(context, qp, 0); 982 err_wrid: 983 mlx4_ib_db_unmap_user(context, &qp->db); 984 985 err_mtt: 986 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 987 err_buf: 988 ib_umem_release(qp->umem); 989 err: 990 return err; 991 } 992 993 static int create_qp_common(struct ib_pd *pd, struct ib_qp_init_attr *init_attr, 994 struct ib_udata *udata, int sqpn, 995 struct mlx4_ib_qp *qp) 996 { 997 struct mlx4_ib_dev *dev = to_mdev(pd->device); 998 int qpn; 999 int err; 1000 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context( 1001 udata, struct mlx4_ib_ucontext, ibucontext); 1002 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type; 1003 struct mlx4_ib_cq *mcq; 1004 unsigned long flags; 1005 1006 /* When tunneling special qps, we use a plain UD qp */ 1007 if (sqpn) { 1008 if (mlx4_is_mfunc(dev->dev) && 1009 (!mlx4_is_master(dev->dev) || 1010 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) { 1011 if (init_attr->qp_type == IB_QPT_GSI) 1012 qp_type = MLX4_IB_QPT_PROXY_GSI; 1013 else { 1014 if (mlx4_is_master(dev->dev) || 1015 qp0_enabled_vf(dev->dev, sqpn)) 1016 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER; 1017 else 1018 qp_type = MLX4_IB_QPT_PROXY_SMI; 1019 } 1020 } 1021 qpn = sqpn; 1022 /* add extra sg entry for tunneling */ 1023 init_attr->cap.max_recv_sge++; 1024 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) { 1025 struct mlx4_ib_qp_tunnel_init_attr *tnl_init = 1026 container_of(init_attr, 1027 struct mlx4_ib_qp_tunnel_init_attr, init_attr); 1028 if ((tnl_init->proxy_qp_type != IB_QPT_SMI && 1029 tnl_init->proxy_qp_type != IB_QPT_GSI) || 1030 !mlx4_is_master(dev->dev)) 1031 return -EINVAL; 1032 if (tnl_init->proxy_qp_type == IB_QPT_GSI) 1033 qp_type = MLX4_IB_QPT_TUN_GSI; 1034 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) || 1035 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave, 1036 tnl_init->port)) 1037 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER; 1038 else 1039 qp_type = MLX4_IB_QPT_TUN_SMI; 1040 /* we are definitely in the PPF here, since we are creating 1041 * tunnel QPs. base_tunnel_sqpn is therefore valid. */ 1042 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave 1043 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1; 1044 sqpn = qpn; 1045 } 1046 1047 if (init_attr->qp_type == IB_QPT_SMI || 1048 init_attr->qp_type == IB_QPT_GSI || qp_type == MLX4_IB_QPT_SMI || 1049 qp_type == MLX4_IB_QPT_GSI || 1050 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER | 1051 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) { 1052 qp->sqp = kzalloc_obj(struct mlx4_ib_sqp); 1053 if (!qp->sqp) 1054 return -ENOMEM; 1055 } 1056 1057 qp->mlx4_ib_qp_type = qp_type; 1058 1059 spin_lock_init(&qp->sq.lock); 1060 spin_lock_init(&qp->rq.lock); 1061 INIT_LIST_HEAD(&qp->gid_list); 1062 INIT_LIST_HEAD(&qp->steering_rules); 1063 1064 qp->state = IB_QPS_RESET; 1065 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1066 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 1067 1068 if (udata) { 1069 struct mlx4_ib_create_qp ucmd; 1070 size_t copy_len; 1071 int shift; 1072 int n; 1073 1074 copy_len = sizeof(struct mlx4_ib_create_qp); 1075 1076 if (ib_copy_from_udata(&ucmd, udata, copy_len)) { 1077 err = -EFAULT; 1078 goto err; 1079 } 1080 1081 qp->inl_recv_sz = ucmd.inl_recv_sz; 1082 1083 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1084 if (!(dev->dev->caps.flags & 1085 MLX4_DEV_CAP_FLAG_FCS_KEEP)) { 1086 pr_debug("scatter FCS is unsupported\n"); 1087 err = -EOPNOTSUPP; 1088 goto err; 1089 } 1090 1091 qp->flags |= MLX4_IB_QP_SCATTER_FCS; 1092 } 1093 1094 err = set_rq_size(dev, &init_attr->cap, udata, 1095 qp_has_rq(init_attr), qp, qp->inl_recv_sz); 1096 if (err) 1097 goto err; 1098 1099 qp->sq_no_prefetch = ucmd.sq_no_prefetch; 1100 1101 err = set_user_sq_size(dev, qp, &ucmd); 1102 if (err) 1103 goto err; 1104 1105 qp->umem = 1106 ib_umem_get(pd->device, ucmd.buf_addr, qp->buf_size, 0); 1107 if (IS_ERR(qp->umem)) { 1108 err = PTR_ERR(qp->umem); 1109 goto err; 1110 } 1111 1112 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n); 1113 if (shift < 0) { 1114 err = shift; 1115 goto err_buf; 1116 } 1117 1118 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt); 1119 if (err) 1120 goto err_buf; 1121 1122 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem); 1123 if (err) 1124 goto err_mtt; 1125 1126 if (qp_has_rq(init_attr)) { 1127 err = mlx4_ib_db_map_user(udata, ucmd.db_addr, &qp->db); 1128 if (err) 1129 goto err_mtt; 1130 } 1131 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS; 1132 } else { 1133 err = set_rq_size(dev, &init_attr->cap, udata, 1134 qp_has_rq(init_attr), qp, 0); 1135 if (err) 1136 goto err; 1137 1138 qp->sq_no_prefetch = 0; 1139 1140 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 1141 qp->flags |= MLX4_IB_QP_LSO; 1142 1143 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 1144 if (dev->steering_support == 1145 MLX4_STEERING_MODE_DEVICE_MANAGED) 1146 qp->flags |= MLX4_IB_QP_NETIF; 1147 else { 1148 err = -EINVAL; 1149 goto err; 1150 } 1151 } 1152 1153 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp); 1154 if (err) 1155 goto err; 1156 1157 if (qp_has_rq(init_attr)) { 1158 err = mlx4_db_alloc(dev->dev, &qp->db, 0); 1159 if (err) 1160 goto err; 1161 1162 *qp->db.db = 0; 1163 } 1164 1165 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, 1166 &qp->buf)) { 1167 err = -ENOMEM; 1168 goto err_db; 1169 } 1170 1171 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift, 1172 &qp->mtt); 1173 if (err) 1174 goto err_buf; 1175 1176 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf); 1177 if (err) 1178 goto err_mtt; 1179 1180 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1181 sizeof(u64), GFP_KERNEL); 1182 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1183 sizeof(u64), GFP_KERNEL); 1184 if (!qp->sq.wrid || !qp->rq.wrid) { 1185 err = -ENOMEM; 1186 goto err_wrid; 1187 } 1188 qp->mqp.usage = MLX4_RES_USAGE_DRIVER; 1189 } 1190 1191 if (sqpn) { 1192 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1193 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 1194 if (alloc_proxy_bufs(pd->device, qp)) { 1195 err = -ENOMEM; 1196 goto err_wrid; 1197 } 1198 } 1199 } else { 1200 /* Raw packet QPNs may not have bits 6,7 set in their qp_num; 1201 * otherwise, the WQE BlueFlame setup flow wrongly causes 1202 * VLAN insertion. */ 1203 if (init_attr->qp_type == IB_QPT_RAW_PACKET) 1204 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 1205 (init_attr->cap.max_send_wr ? 1206 MLX4_RESERVE_ETH_BF_QP : 0) | 1207 (init_attr->cap.max_recv_wr ? 1208 MLX4_RESERVE_A0_QP : 0), 1209 qp->mqp.usage); 1210 else 1211 if (qp->flags & MLX4_IB_QP_NETIF) 1212 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn); 1213 else 1214 err = mlx4_qp_reserve_range(dev->dev, 1, 1, 1215 &qpn, 0, qp->mqp.usage); 1216 if (err) 1217 goto err_proxy; 1218 } 1219 1220 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 1221 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1222 1223 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp); 1224 if (err) 1225 goto err_qpn; 1226 1227 if (init_attr->qp_type == IB_QPT_XRC_TGT) 1228 qp->mqp.qpn |= (1 << 23); 1229 1230 /* 1231 * Hardware wants QPN written in big-endian order (after 1232 * shifting) for send doorbell. Precompute this value to save 1233 * a little bit when posting sends. 1234 */ 1235 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8); 1236 1237 qp->mqp.event = mlx4_ib_qp_event; 1238 1239 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1240 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq), 1241 to_mcq(init_attr->recv_cq)); 1242 /* Maintain device to QPs access, needed for further handling 1243 * via reset flow 1244 */ 1245 list_add_tail(&qp->qps_list, &dev->qp_list); 1246 /* Maintain CQ to QPs access, needed for further handling 1247 * via reset flow 1248 */ 1249 mcq = to_mcq(init_attr->send_cq); 1250 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list); 1251 mcq = to_mcq(init_attr->recv_cq); 1252 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list); 1253 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq), 1254 to_mcq(init_attr->recv_cq)); 1255 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1256 return 0; 1257 1258 err_qpn: 1259 if (!sqpn) { 1260 if (qp->flags & MLX4_IB_QP_NETIF) 1261 mlx4_ib_steer_qp_free(dev, qpn, 1); 1262 else 1263 mlx4_qp_release_range(dev->dev, qpn, 1); 1264 } 1265 err_proxy: 1266 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 1267 free_proxy_bufs(pd->device, qp); 1268 err_wrid: 1269 if (udata) { 1270 if (qp_has_rq(init_attr)) 1271 mlx4_ib_db_unmap_user(context, &qp->db); 1272 } else { 1273 kvfree(qp->sq.wrid); 1274 kvfree(qp->rq.wrid); 1275 } 1276 1277 err_mtt: 1278 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1279 1280 err_buf: 1281 if (!qp->umem) 1282 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1283 ib_umem_release(qp->umem); 1284 1285 err_db: 1286 if (!udata && qp_has_rq(init_attr)) 1287 mlx4_db_free(dev->dev, &qp->db); 1288 1289 err: 1290 kfree(qp->sqp); 1291 return err; 1292 } 1293 1294 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state) 1295 { 1296 switch (state) { 1297 case IB_QPS_RESET: return MLX4_QP_STATE_RST; 1298 case IB_QPS_INIT: return MLX4_QP_STATE_INIT; 1299 case IB_QPS_RTR: return MLX4_QP_STATE_RTR; 1300 case IB_QPS_RTS: return MLX4_QP_STATE_RTS; 1301 case IB_QPS_SQD: return MLX4_QP_STATE_SQD; 1302 case IB_QPS_SQE: return MLX4_QP_STATE_SQER; 1303 case IB_QPS_ERR: return MLX4_QP_STATE_ERR; 1304 default: return -1; 1305 } 1306 } 1307 1308 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 1309 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1310 { 1311 if (send_cq == recv_cq) { 1312 spin_lock(&send_cq->lock); 1313 __acquire(&recv_cq->lock); 1314 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1315 spin_lock(&send_cq->lock); 1316 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); 1317 } else { 1318 spin_lock(&recv_cq->lock); 1319 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); 1320 } 1321 } 1322 1323 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 1324 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1325 { 1326 if (send_cq == recv_cq) { 1327 __release(&recv_cq->lock); 1328 spin_unlock(&send_cq->lock); 1329 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1330 spin_unlock(&recv_cq->lock); 1331 spin_unlock(&send_cq->lock); 1332 } else { 1333 spin_unlock(&send_cq->lock); 1334 spin_unlock(&recv_cq->lock); 1335 } 1336 } 1337 1338 static void del_gid_entries(struct mlx4_ib_qp *qp) 1339 { 1340 struct mlx4_ib_gid_entry *ge, *tmp; 1341 1342 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1343 list_del(&ge->list); 1344 kfree(ge); 1345 } 1346 } 1347 1348 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp) 1349 { 1350 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT) 1351 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd); 1352 else 1353 return to_mpd(qp->ibqp.pd); 1354 } 1355 1356 static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src, 1357 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq) 1358 { 1359 switch (qp->ibqp.qp_type) { 1360 case IB_QPT_XRC_TGT: 1361 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq); 1362 *recv_cq = *send_cq; 1363 break; 1364 case IB_QPT_XRC_INI: 1365 *send_cq = to_mcq(qp->ibqp.send_cq); 1366 *recv_cq = *send_cq; 1367 break; 1368 default: 1369 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) : 1370 to_mcq(qp->ibwq.cq); 1371 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) : 1372 *recv_cq; 1373 break; 1374 } 1375 } 1376 1377 static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1378 { 1379 if (qp->state != IB_QPS_RESET) { 1380 int i; 1381 1382 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size); 1383 i++) { 1384 struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i]; 1385 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 1386 1387 mutex_lock(&wq->mutex); 1388 1389 wq->rss_usecnt--; 1390 1391 mutex_unlock(&wq->mutex); 1392 } 1393 1394 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), 1395 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) 1396 pr_warn("modify QP %06x to RESET failed.\n", 1397 qp->mqp.qpn); 1398 } 1399 1400 mlx4_qp_remove(dev->dev, &qp->mqp); 1401 mlx4_qp_free(dev->dev, &qp->mqp); 1402 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1); 1403 del_gid_entries(qp); 1404 } 1405 1406 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, 1407 enum mlx4_ib_source_type src, 1408 struct ib_udata *udata) 1409 { 1410 struct mlx4_ib_cq *send_cq, *recv_cq; 1411 unsigned long flags; 1412 1413 if (qp->state != IB_QPS_RESET) { 1414 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), 1415 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) 1416 pr_warn("modify QP %06x to RESET failed.\n", 1417 qp->mqp.qpn); 1418 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) { 1419 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 1420 qp->pri.smac = 0; 1421 qp->pri.smac_port = 0; 1422 } 1423 if (qp->alt.smac) { 1424 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 1425 qp->alt.smac = 0; 1426 } 1427 if (qp->pri.vid < 0x1000) { 1428 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 1429 qp->pri.vid = 0xFFFF; 1430 qp->pri.candidate_vid = 0xFFFF; 1431 qp->pri.update_vid = 0; 1432 } 1433 if (qp->alt.vid < 0x1000) { 1434 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 1435 qp->alt.vid = 0xFFFF; 1436 qp->alt.candidate_vid = 0xFFFF; 1437 qp->alt.update_vid = 0; 1438 } 1439 } 1440 1441 get_cqs(qp, src, &send_cq, &recv_cq); 1442 1443 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1444 mlx4_ib_lock_cqs(send_cq, recv_cq); 1445 1446 /* del from lists under both locks above to protect reset flow paths */ 1447 list_del(&qp->qps_list); 1448 list_del(&qp->cq_send_list); 1449 list_del(&qp->cq_recv_list); 1450 if (!udata) { 1451 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 1452 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL); 1453 if (send_cq != recv_cq) 1454 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 1455 } 1456 1457 mlx4_qp_remove(dev->dev, &qp->mqp); 1458 1459 mlx4_ib_unlock_cqs(send_cq, recv_cq); 1460 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1461 1462 mlx4_qp_free(dev->dev, &qp->mqp); 1463 1464 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) { 1465 if (qp->flags & MLX4_IB_QP_NETIF) 1466 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1); 1467 else if (src == MLX4_IB_RWQ_SRC) 1468 mlx4_ib_release_wqn( 1469 rdma_udata_to_drv_context( 1470 udata, 1471 struct mlx4_ib_ucontext, 1472 ibucontext), 1473 qp, 1); 1474 else 1475 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1); 1476 } 1477 1478 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1479 1480 if (udata) { 1481 if (qp->rq.wqe_cnt) { 1482 struct mlx4_ib_ucontext *mcontext = 1483 rdma_udata_to_drv_context( 1484 udata, 1485 struct mlx4_ib_ucontext, 1486 ibucontext); 1487 1488 mlx4_ib_db_unmap_user(mcontext, &qp->db); 1489 } 1490 } else { 1491 kvfree(qp->sq.wrid); 1492 kvfree(qp->rq.wrid); 1493 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1494 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) 1495 free_proxy_bufs(&dev->ib_dev, qp); 1496 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1497 if (qp->rq.wqe_cnt) 1498 mlx4_db_free(dev->dev, &qp->db); 1499 } 1500 ib_umem_release(qp->umem); 1501 1502 del_gid_entries(qp); 1503 } 1504 1505 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr) 1506 { 1507 /* Native or PPF */ 1508 if (!mlx4_is_mfunc(dev->dev) || 1509 (mlx4_is_master(dev->dev) && 1510 attr->create_flags & MLX4_IB_SRIOV_SQP)) { 1511 return dev->dev->phys_caps.base_sqpn + 1512 (attr->qp_type == IB_QPT_SMI ? 0 : 2) + 1513 attr->port_num - 1; 1514 } 1515 /* PF or VF -- creating proxies */ 1516 if (attr->qp_type == IB_QPT_SMI) 1517 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy; 1518 else 1519 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy; 1520 } 1521 1522 static int _mlx4_ib_create_qp(struct ib_pd *pd, struct mlx4_ib_qp *qp, 1523 struct ib_qp_init_attr *init_attr, 1524 struct ib_udata *udata) 1525 { 1526 int err; 1527 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1528 u16 xrcdn = 0; 1529 1530 if (init_attr->rwq_ind_tbl) 1531 return _mlx4_ib_create_qp_rss(pd, qp, init_attr, udata); 1532 1533 /* 1534 * We only support LSO, vendor flag1, and multicast loopback blocking, 1535 * and only for kernel UD QPs. 1536 */ 1537 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO | 1538 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK | 1539 MLX4_IB_SRIOV_TUNNEL_QP | 1540 MLX4_IB_SRIOV_SQP | 1541 MLX4_IB_QP_NETIF | 1542 MLX4_IB_QP_CREATE_ROCE_V2_GSI)) 1543 return -EOPNOTSUPP; 1544 1545 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 1546 if (init_attr->qp_type != IB_QPT_UD) 1547 return -EINVAL; 1548 } 1549 1550 if (init_attr->create_flags) { 1551 if (udata && init_attr->create_flags & ~(sup_u_create_flags)) 1552 return -EINVAL; 1553 1554 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP | 1555 MLX4_IB_QP_CREATE_ROCE_V2_GSI | 1556 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) && 1557 init_attr->qp_type != IB_QPT_UD) || 1558 (init_attr->create_flags & MLX4_IB_SRIOV_SQP && 1559 init_attr->qp_type > IB_QPT_GSI) || 1560 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI && 1561 init_attr->qp_type != IB_QPT_GSI)) 1562 return -EINVAL; 1563 } 1564 1565 switch (init_attr->qp_type) { 1566 case IB_QPT_XRC_TGT: 1567 pd = to_mxrcd(init_attr->xrcd)->pd; 1568 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 1569 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq; 1570 fallthrough; 1571 case IB_QPT_XRC_INI: 1572 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1573 return -ENOSYS; 1574 init_attr->recv_cq = init_attr->send_cq; 1575 fallthrough; 1576 case IB_QPT_RC: 1577 case IB_QPT_UC: 1578 case IB_QPT_RAW_PACKET: 1579 case IB_QPT_UD: 1580 qp->pri.vid = 0xFFFF; 1581 qp->alt.vid = 0xFFFF; 1582 err = create_qp_common(pd, init_attr, udata, 0, qp); 1583 if (err) 1584 return err; 1585 1586 qp->ibqp.qp_num = qp->mqp.qpn; 1587 qp->xrcdn = xrcdn; 1588 break; 1589 case IB_QPT_SMI: 1590 case IB_QPT_GSI: 1591 { 1592 int sqpn; 1593 1594 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) { 1595 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev, 1596 1, 1, &sqpn, 0, 1597 MLX4_RES_USAGE_DRIVER); 1598 1599 if (res) 1600 return res; 1601 } else { 1602 sqpn = get_sqp_num(to_mdev(pd->device), init_attr); 1603 } 1604 1605 qp->pri.vid = 0xFFFF; 1606 qp->alt.vid = 0xFFFF; 1607 err = create_qp_common(pd, init_attr, udata, sqpn, qp); 1608 if (err) 1609 return err; 1610 1611 if (init_attr->create_flags & 1612 (MLX4_IB_SRIOV_SQP | MLX4_IB_SRIOV_TUNNEL_QP)) 1613 /* Internal QP created with ib_create_qp */ 1614 rdma_restrack_no_track(&qp->ibqp.res); 1615 1616 qp->port = init_attr->port_num; 1617 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1618 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1; 1619 break; 1620 } 1621 default: 1622 /* Don't support raw QPs */ 1623 return -EOPNOTSUPP; 1624 } 1625 return 0; 1626 } 1627 1628 int mlx4_ib_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *init_attr, 1629 struct ib_udata *udata) 1630 { 1631 struct ib_device *device = ibqp->device; 1632 struct mlx4_ib_dev *dev = to_mdev(device); 1633 struct mlx4_ib_qp *qp = to_mqp(ibqp); 1634 struct ib_pd *pd = ibqp->pd; 1635 int ret; 1636 1637 mutex_init(&qp->mutex); 1638 ret = _mlx4_ib_create_qp(pd, qp, init_attr, udata); 1639 if (ret) 1640 return ret; 1641 1642 if (init_attr->qp_type == IB_QPT_GSI && 1643 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) { 1644 struct mlx4_ib_sqp *sqp = qp->sqp; 1645 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num); 1646 1647 if (is_eth && 1648 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) { 1649 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI; 1650 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr); 1651 1652 if (IS_ERR(sqp->roce_v2_gsi)) { 1653 pr_err("Failed to create GSI QP for RoCEv2 (%pe)\n", 1654 sqp->roce_v2_gsi); 1655 sqp->roce_v2_gsi = NULL; 1656 } else { 1657 to_mqp(sqp->roce_v2_gsi)->flags |= 1658 MLX4_IB_ROCE_V2_GSI_QP; 1659 } 1660 1661 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI; 1662 } 1663 } 1664 return 0; 1665 } 1666 1667 static int _mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 1668 { 1669 struct mlx4_ib_dev *dev = to_mdev(qp->device); 1670 struct mlx4_ib_qp *mqp = to_mqp(qp); 1671 1672 if (is_qp0(dev, mqp)) 1673 mlx4_CLOSE_PORT(dev->dev, mqp->port); 1674 1675 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI && 1676 dev->qp1_proxy[mqp->port - 1] == mqp) { 1677 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]); 1678 dev->qp1_proxy[mqp->port - 1] = NULL; 1679 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]); 1680 } 1681 1682 if (mqp->counter_index) 1683 mlx4_ib_free_qp_counter(dev, mqp); 1684 1685 if (qp->rwq_ind_tbl) { 1686 destroy_qp_rss(dev, mqp); 1687 } else { 1688 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, udata); 1689 } 1690 1691 kfree(mqp->sqp); 1692 return 0; 1693 } 1694 1695 int mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 1696 { 1697 struct mlx4_ib_qp *mqp = to_mqp(qp); 1698 1699 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 1700 struct mlx4_ib_sqp *sqp = mqp->sqp; 1701 1702 if (sqp->roce_v2_gsi) 1703 ib_destroy_qp(sqp->roce_v2_gsi); 1704 } 1705 1706 return _mlx4_ib_destroy_qp(qp, udata); 1707 } 1708 1709 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type) 1710 { 1711 switch (type) { 1712 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC; 1713 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC; 1714 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD; 1715 case MLX4_IB_QPT_XRC_INI: 1716 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC; 1717 case MLX4_IB_QPT_SMI: 1718 case MLX4_IB_QPT_GSI: 1719 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX; 1720 1721 case MLX4_IB_QPT_PROXY_SMI_OWNER: 1722 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ? 1723 MLX4_QP_ST_MLX : -1); 1724 case MLX4_IB_QPT_PROXY_SMI: 1725 case MLX4_IB_QPT_TUN_SMI: 1726 case MLX4_IB_QPT_PROXY_GSI: 1727 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ? 1728 MLX4_QP_ST_UD : -1); 1729 default: return -1; 1730 } 1731 } 1732 1733 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr, 1734 int attr_mask) 1735 { 1736 u8 dest_rd_atomic; 1737 u32 access_flags; 1738 u32 hw_access_flags = 0; 1739 1740 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1741 dest_rd_atomic = attr->max_dest_rd_atomic; 1742 else 1743 dest_rd_atomic = qp->resp_depth; 1744 1745 if (attr_mask & IB_QP_ACCESS_FLAGS) 1746 access_flags = attr->qp_access_flags; 1747 else 1748 access_flags = qp->atomic_rd_en; 1749 1750 if (!dest_rd_atomic) 1751 access_flags &= IB_ACCESS_REMOTE_WRITE; 1752 1753 if (access_flags & IB_ACCESS_REMOTE_READ) 1754 hw_access_flags |= MLX4_QP_BIT_RRE; 1755 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 1756 hw_access_flags |= MLX4_QP_BIT_RAE; 1757 if (access_flags & IB_ACCESS_REMOTE_WRITE) 1758 hw_access_flags |= MLX4_QP_BIT_RWE; 1759 1760 return cpu_to_be32(hw_access_flags); 1761 } 1762 1763 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr, 1764 int attr_mask) 1765 { 1766 if (attr_mask & IB_QP_PKEY_INDEX) 1767 sqp->pkey_index = attr->pkey_index; 1768 if (attr_mask & IB_QP_QKEY) 1769 sqp->qkey = attr->qkey; 1770 if (attr_mask & IB_QP_SQ_PSN) 1771 sqp->send_psn = attr->sq_psn; 1772 } 1773 1774 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port) 1775 { 1776 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6); 1777 } 1778 1779 static int _mlx4_set_path(struct mlx4_ib_dev *dev, 1780 const struct rdma_ah_attr *ah, 1781 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path, 1782 struct mlx4_roce_smac_vlan_info *smac_info, u8 port) 1783 { 1784 int vidx; 1785 int smac_index; 1786 int err; 1787 1788 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f; 1789 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 1790 if (rdma_ah_get_static_rate(ah)) { 1791 path->static_rate = rdma_ah_get_static_rate(ah) + 1792 MLX4_STAT_RATE_OFFSET; 1793 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET && 1794 !(1 << path->static_rate & dev->dev->caps.stat_rate_support)) 1795 --path->static_rate; 1796 } else 1797 path->static_rate = 0; 1798 1799 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) { 1800 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 1801 int real_sgid_index = 1802 mlx4_ib_gid_index_to_real_index(dev, grh->sgid_attr); 1803 1804 if (real_sgid_index < 0) 1805 return real_sgid_index; 1806 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) { 1807 pr_err("sgid_index (%u) too large. max is %d\n", 1808 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1); 1809 return -1; 1810 } 1811 1812 path->grh_mylmc |= 1 << 7; 1813 path->mgid_index = real_sgid_index; 1814 path->hop_limit = grh->hop_limit; 1815 path->tclass_flowlabel = 1816 cpu_to_be32((grh->traffic_class << 20) | 1817 (grh->flow_label)); 1818 memcpy(path->rgid, grh->dgid.raw, 16); 1819 } 1820 1821 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 1822 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH)) 1823 return -1; 1824 1825 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1826 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3); 1827 1828 path->feup |= MLX4_FEUP_FORCE_ETH_UP; 1829 if (vlan_tag < 0x1000) { 1830 if (smac_info->vid < 0x1000) { 1831 /* both valid vlan ids */ 1832 if (smac_info->vid != vlan_tag) { 1833 /* different VIDs. unreg old and reg new */ 1834 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1835 if (err) 1836 return err; 1837 smac_info->candidate_vid = vlan_tag; 1838 smac_info->candidate_vlan_index = vidx; 1839 smac_info->candidate_vlan_port = port; 1840 smac_info->update_vid = 1; 1841 path->vlan_index = vidx; 1842 } else { 1843 path->vlan_index = smac_info->vlan_index; 1844 } 1845 } else { 1846 /* no current vlan tag in qp */ 1847 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1848 if (err) 1849 return err; 1850 smac_info->candidate_vid = vlan_tag; 1851 smac_info->candidate_vlan_index = vidx; 1852 smac_info->candidate_vlan_port = port; 1853 smac_info->update_vid = 1; 1854 path->vlan_index = vidx; 1855 } 1856 path->feup |= MLX4_FVL_FORCE_ETH_VLAN; 1857 path->fl = 1 << 6; 1858 } else { 1859 /* have current vlan tag. unregister it at modify-qp success */ 1860 if (smac_info->vid < 0x1000) { 1861 smac_info->candidate_vid = 0xFFFF; 1862 smac_info->update_vid = 1; 1863 } 1864 } 1865 1866 /* get smac_index for RoCE use. 1867 * If no smac was yet assigned, register one. 1868 * If one was already assigned, but the new mac differs, 1869 * unregister the old one and register the new one. 1870 */ 1871 if ((!smac_info->smac && !smac_info->smac_port) || 1872 smac_info->smac != smac) { 1873 /* register candidate now, unreg if needed, after success */ 1874 smac_index = mlx4_register_mac(dev->dev, port, smac); 1875 if (smac_index >= 0) { 1876 smac_info->candidate_smac_index = smac_index; 1877 smac_info->candidate_smac = smac; 1878 smac_info->candidate_smac_port = port; 1879 } else { 1880 return -EINVAL; 1881 } 1882 } else { 1883 smac_index = smac_info->smac_index; 1884 } 1885 memcpy(path->dmac, ah->roce.dmac, 6); 1886 path->ackto = MLX4_IB_LINK_TYPE_ETH; 1887 /* put MAC table smac index for IBoE */ 1888 path->grh_mylmc = (u8) (smac_index) | 0x80; 1889 } else { 1890 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1891 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2); 1892 } 1893 1894 return 0; 1895 } 1896 1897 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp, 1898 enum ib_qp_attr_mask qp_attr_mask, 1899 struct mlx4_ib_qp *mqp, 1900 struct mlx4_qp_path *path, u8 port, 1901 u16 vlan_id, u8 *smac) 1902 { 1903 return _mlx4_set_path(dev, &qp->ah_attr, 1904 ether_addr_to_u64(smac), 1905 vlan_id, 1906 path, &mqp->pri, port); 1907 } 1908 1909 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev, 1910 const struct ib_qp_attr *qp, 1911 enum ib_qp_attr_mask qp_attr_mask, 1912 struct mlx4_ib_qp *mqp, 1913 struct mlx4_qp_path *path, u8 port) 1914 { 1915 return _mlx4_set_path(dev, &qp->alt_ah_attr, 1916 0, 1917 0xffff, 1918 path, &mqp->alt, port); 1919 } 1920 1921 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1922 { 1923 struct mlx4_ib_gid_entry *ge, *tmp; 1924 1925 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1926 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) { 1927 ge->added = 1; 1928 ge->port = qp->port; 1929 } 1930 } 1931 } 1932 1933 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, 1934 struct mlx4_ib_qp *qp, 1935 struct mlx4_qp_context *context) 1936 { 1937 u64 u64_mac; 1938 int smac_index; 1939 1940 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]); 1941 1942 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6); 1943 if (!qp->pri.smac && !qp->pri.smac_port) { 1944 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac); 1945 if (smac_index >= 0) { 1946 qp->pri.candidate_smac_index = smac_index; 1947 qp->pri.candidate_smac = u64_mac; 1948 qp->pri.candidate_smac_port = qp->port; 1949 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index; 1950 } else { 1951 return -ENOENT; 1952 } 1953 } 1954 return 0; 1955 } 1956 1957 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1958 { 1959 struct counter_index *new_counter_index; 1960 int err; 1961 u32 tmp_idx; 1962 1963 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) != 1964 IB_LINK_LAYER_ETHERNET || 1965 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) || 1966 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK)) 1967 return 0; 1968 1969 err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER); 1970 if (err) 1971 return err; 1972 1973 new_counter_index = kmalloc_obj(*new_counter_index); 1974 if (!new_counter_index) { 1975 mlx4_counter_free(dev->dev, tmp_idx); 1976 return -ENOMEM; 1977 } 1978 1979 new_counter_index->index = tmp_idx; 1980 new_counter_index->allocated = 1; 1981 qp->counter_index = new_counter_index; 1982 1983 mutex_lock(&dev->counters_table[qp->port - 1].mutex); 1984 list_add_tail(&new_counter_index->list, 1985 &dev->counters_table[qp->port - 1].counters_list); 1986 mutex_unlock(&dev->counters_table[qp->port - 1].mutex); 1987 1988 return 0; 1989 } 1990 1991 enum { 1992 MLX4_QPC_ROCE_MODE_1 = 0, 1993 MLX4_QPC_ROCE_MODE_2 = 2, 1994 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff 1995 }; 1996 1997 static u8 gid_type_to_qpc(enum ib_gid_type gid_type) 1998 { 1999 switch (gid_type) { 2000 case IB_GID_TYPE_ROCE: 2001 return MLX4_QPC_ROCE_MODE_1; 2002 case IB_GID_TYPE_ROCE_UDP_ENCAP: 2003 return MLX4_QPC_ROCE_MODE_2; 2004 default: 2005 return MLX4_QPC_ROCE_MODE_UNDEFINED; 2006 } 2007 } 2008 2009 /* 2010 * Go over all RSS QP's childes (WQs) and apply their HW state according to 2011 * their logic state if the RSS QP is the first RSS QP associated for the WQ. 2012 */ 2013 static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num, 2014 struct ib_udata *udata) 2015 { 2016 int err = 0; 2017 int i; 2018 2019 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) { 2020 struct ib_wq *ibwq = ind_tbl->ind_tbl[i]; 2021 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 2022 2023 mutex_lock(&wq->mutex); 2024 2025 /* Mlx4_ib restrictions: 2026 * WQ's is associated to a port according to the RSS QP it is 2027 * associates to. 2028 * In case the WQ is associated to a different port by another 2029 * RSS QP, return a failure. 2030 */ 2031 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) { 2032 err = -EINVAL; 2033 mutex_unlock(&wq->mutex); 2034 break; 2035 } 2036 wq->port = port_num; 2037 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) { 2038 err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY, udata); 2039 if (err) { 2040 mutex_unlock(&wq->mutex); 2041 break; 2042 } 2043 } 2044 wq->rss_usecnt++; 2045 2046 mutex_unlock(&wq->mutex); 2047 } 2048 2049 if (i && err) { 2050 int j; 2051 2052 for (j = (i - 1); j >= 0; j--) { 2053 struct ib_wq *ibwq = ind_tbl->ind_tbl[j]; 2054 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 2055 2056 mutex_lock(&wq->mutex); 2057 2058 if ((wq->rss_usecnt == 1) && 2059 (ibwq->state == IB_WQS_RDY)) 2060 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET, 2061 udata)) 2062 pr_warn("failed to reverse WQN=0x%06x\n", 2063 ibwq->wq_num); 2064 wq->rss_usecnt--; 2065 2066 mutex_unlock(&wq->mutex); 2067 } 2068 } 2069 2070 return err; 2071 } 2072 2073 static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, 2074 struct ib_udata *udata) 2075 { 2076 int i; 2077 2078 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) { 2079 struct ib_wq *ibwq = ind_tbl->ind_tbl[i]; 2080 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 2081 2082 mutex_lock(&wq->mutex); 2083 2084 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY)) 2085 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET, udata)) 2086 pr_warn("failed to reverse WQN=%x\n", 2087 ibwq->wq_num); 2088 wq->rss_usecnt--; 2089 2090 mutex_unlock(&wq->mutex); 2091 } 2092 } 2093 2094 static void fill_qp_rss_context(struct mlx4_qp_context *context, 2095 struct mlx4_ib_qp *qp) 2096 { 2097 struct mlx4_rss_context *rss_context; 2098 2099 rss_context = (void *)context + offsetof(struct mlx4_qp_context, 2100 pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; 2101 2102 rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz); 2103 rss_context->default_qpn = 2104 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff); 2105 if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6)) 2106 rss_context->base_qpn_udp = rss_context->default_qpn; 2107 rss_context->flags = qp->rss_ctx->flags; 2108 /* Currently support just toeplitz */ 2109 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 2110 2111 memcpy(rss_context->rss_key, qp->rss_ctx->rss_key, 2112 MLX4_EN_RSS_KEY_SIZE); 2113 } 2114 2115 static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type, 2116 const struct ib_qp_attr *attr, int attr_mask, 2117 enum ib_qp_state cur_state, 2118 enum ib_qp_state new_state, 2119 struct ib_udata *udata) 2120 { 2121 struct ib_srq *ibsrq; 2122 const struct ib_gid_attr *gid_attr = NULL; 2123 struct ib_rwq_ind_table *rwq_ind_tbl; 2124 enum ib_qp_type qp_type; 2125 struct mlx4_ib_dev *dev; 2126 struct mlx4_ib_qp *qp; 2127 struct mlx4_ib_pd *pd; 2128 struct mlx4_ib_cq *send_cq, *recv_cq; 2129 struct mlx4_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2130 udata, struct mlx4_ib_ucontext, ibucontext); 2131 struct mlx4_qp_context *context; 2132 enum mlx4_qp_optpar optpar = 0; 2133 int sqd_event; 2134 int steer_qp = 0; 2135 int err = -EINVAL; 2136 int counter_index; 2137 2138 if (src_type == MLX4_IB_RWQ_SRC) { 2139 struct ib_wq *ibwq; 2140 2141 ibwq = (struct ib_wq *)src; 2142 ibsrq = NULL; 2143 rwq_ind_tbl = NULL; 2144 qp_type = IB_QPT_RAW_PACKET; 2145 qp = to_mqp((struct ib_qp *)ibwq); 2146 dev = to_mdev(ibwq->device); 2147 pd = to_mpd(ibwq->pd); 2148 } else { 2149 struct ib_qp *ibqp; 2150 2151 ibqp = (struct ib_qp *)src; 2152 ibsrq = ibqp->srq; 2153 rwq_ind_tbl = ibqp->rwq_ind_tbl; 2154 qp_type = ibqp->qp_type; 2155 qp = to_mqp(ibqp); 2156 dev = to_mdev(ibqp->device); 2157 pd = get_pd(qp); 2158 } 2159 2160 /* APM is not supported under RoCE */ 2161 if (attr_mask & IB_QP_ALT_PATH && 2162 rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 2163 IB_LINK_LAYER_ETHERNET) 2164 return -ENOTSUPP; 2165 2166 context = kzalloc_obj(*context); 2167 if (!context) 2168 return -ENOMEM; 2169 2170 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) | 2171 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16)); 2172 2173 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) 2174 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 2175 else { 2176 optpar |= MLX4_QP_OPTPAR_PM_STATE; 2177 switch (attr->path_mig_state) { 2178 case IB_MIG_MIGRATED: 2179 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 2180 break; 2181 case IB_MIG_REARM: 2182 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11); 2183 break; 2184 case IB_MIG_ARMED: 2185 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11); 2186 break; 2187 } 2188 } 2189 2190 if (qp->inl_recv_sz) 2191 context->param3 |= cpu_to_be32(1 << 25); 2192 2193 if (qp->flags & MLX4_IB_QP_SCATTER_FCS) 2194 context->param3 |= cpu_to_be32(1 << 29); 2195 2196 if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI) 2197 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11; 2198 else if (qp_type == IB_QPT_RAW_PACKET) 2199 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX; 2200 else if (qp_type == IB_QPT_UD) { 2201 if (qp->flags & MLX4_IB_QP_LSO) 2202 context->mtu_msgmax = (IB_MTU_4096 << 5) | 2203 ilog2(dev->dev->caps.max_gso_sz); 2204 else 2205 context->mtu_msgmax = (IB_MTU_4096 << 5) | 13; 2206 } else if (attr_mask & IB_QP_PATH_MTU) { 2207 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) { 2208 pr_err("path MTU (%u) is invalid\n", 2209 attr->path_mtu); 2210 goto out; 2211 } 2212 context->mtu_msgmax = (attr->path_mtu << 5) | 2213 ilog2(dev->dev->caps.max_msg_sz); 2214 } 2215 2216 if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */ 2217 if (qp->rq.wqe_cnt) 2218 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3; 2219 context->rq_size_stride |= qp->rq.wqe_shift - 4; 2220 } 2221 2222 if (qp->sq.wqe_cnt) 2223 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3; 2224 context->sq_size_stride |= qp->sq.wqe_shift - 4; 2225 2226 if (new_state == IB_QPS_RESET && qp->counter_index) 2227 mlx4_ib_free_qp_counter(dev, qp); 2228 2229 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2230 context->sq_size_stride |= !!qp->sq_no_prefetch << 7; 2231 context->xrcd = cpu_to_be32((u32) qp->xrcdn); 2232 if (qp_type == IB_QPT_RAW_PACKET) 2233 context->param3 |= cpu_to_be32(1 << 30); 2234 } 2235 2236 if (ucontext) 2237 context->usr_page = cpu_to_be32( 2238 mlx4_to_hw_uar_index(dev->dev, ucontext->uar.index)); 2239 else 2240 context->usr_page = cpu_to_be32( 2241 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index)); 2242 2243 if (attr_mask & IB_QP_DEST_QPN) 2244 context->remote_qpn = cpu_to_be32(attr->dest_qp_num); 2245 2246 if (attr_mask & IB_QP_PORT) { 2247 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD && 2248 !(attr_mask & IB_QP_AV)) { 2249 mlx4_set_sched(&context->pri_path, attr->port_num); 2250 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE; 2251 } 2252 } 2253 2254 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 2255 err = create_qp_lb_counter(dev, qp); 2256 if (err) 2257 goto out; 2258 2259 counter_index = 2260 dev->counters_table[qp->port - 1].default_counter; 2261 if (qp->counter_index) 2262 counter_index = qp->counter_index->index; 2263 2264 if (counter_index != -1) { 2265 context->pri_path.counter_index = counter_index; 2266 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX; 2267 if (qp->counter_index) { 2268 context->pri_path.fl |= 2269 MLX4_FL_ETH_SRC_CHECK_MC_LB; 2270 context->pri_path.vlan_control |= 2271 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER; 2272 } 2273 } else 2274 context->pri_path.counter_index = 2275 MLX4_SINK_COUNTER_INDEX(dev->dev); 2276 2277 if (qp->flags & MLX4_IB_QP_NETIF) { 2278 mlx4_ib_steer_qp_reg(dev, qp, 1); 2279 steer_qp = 1; 2280 } 2281 2282 if (qp_type == IB_QPT_GSI) { 2283 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ? 2284 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE; 2285 u8 qpc_roce_mode = gid_type_to_qpc(gid_type); 2286 2287 context->rlkey_roce_mode |= (qpc_roce_mode << 6); 2288 } 2289 } 2290 2291 if (attr_mask & IB_QP_PKEY_INDEX) { 2292 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 2293 context->pri_path.disable_pkey_check = 0x40; 2294 context->pri_path.pkey_index = attr->pkey_index; 2295 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX; 2296 } 2297 2298 if (attr_mask & IB_QP_AV) { 2299 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 : 2300 attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2301 u16 vlan = 0xffff; 2302 u8 smac[ETH_ALEN]; 2303 int is_eth = 2304 rdma_cap_eth_ah(&dev->ib_dev, port_num) && 2305 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 2306 2307 if (is_eth) { 2308 gid_attr = attr->ah_attr.grh.sgid_attr; 2309 err = rdma_read_gid_l2_fields(gid_attr, &vlan, 2310 &smac[0]); 2311 if (err) 2312 goto out; 2313 } 2314 2315 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path, 2316 port_num, vlan, smac)) 2317 goto out; 2318 2319 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | 2320 MLX4_QP_OPTPAR_SCHED_QUEUE); 2321 2322 if (is_eth && 2323 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) { 2324 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr->gid_type); 2325 2326 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) { 2327 err = -EINVAL; 2328 goto out; 2329 } 2330 context->rlkey_roce_mode |= (qpc_roce_mode << 6); 2331 } 2332 2333 } 2334 2335 if (attr_mask & IB_QP_TIMEOUT) { 2336 context->pri_path.ackto |= attr->timeout << 3; 2337 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT; 2338 } 2339 2340 if (attr_mask & IB_QP_ALT_PATH) { 2341 if (attr->alt_port_num == 0 || 2342 attr->alt_port_num > dev->dev->caps.num_ports) 2343 goto out; 2344 2345 if (attr->alt_pkey_index >= 2346 dev->dev->caps.pkey_table_len[attr->alt_port_num]) 2347 goto out; 2348 2349 if (mlx4_set_alt_path(dev, attr, attr_mask, qp, 2350 &context->alt_path, 2351 attr->alt_port_num)) 2352 goto out; 2353 2354 context->alt_path.pkey_index = attr->alt_pkey_index; 2355 context->alt_path.ackto = attr->alt_timeout << 3; 2356 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH; 2357 } 2358 2359 context->pd = cpu_to_be32(pd->pdn); 2360 2361 if (!rwq_ind_tbl) { 2362 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28); 2363 get_cqs(qp, src_type, &send_cq, &recv_cq); 2364 } else { /* Set dummy CQs to be compatible with HV and PRM */ 2365 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq); 2366 recv_cq = send_cq; 2367 } 2368 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn); 2369 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn); 2370 2371 /* Set "fast registration enabled" for all kernel QPs */ 2372 if (!ucontext) 2373 context->params1 |= cpu_to_be32(1 << 11); 2374 2375 if (attr_mask & IB_QP_RNR_RETRY) { 2376 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 2377 optpar |= MLX4_QP_OPTPAR_RNR_RETRY; 2378 } 2379 2380 if (attr_mask & IB_QP_RETRY_CNT) { 2381 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 2382 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT; 2383 } 2384 2385 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2386 if (attr->max_rd_atomic) 2387 context->params1 |= 2388 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 2389 optpar |= MLX4_QP_OPTPAR_SRA_MAX; 2390 } 2391 2392 if (attr_mask & IB_QP_SQ_PSN) 2393 context->next_send_psn = cpu_to_be32(attr->sq_psn); 2394 2395 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2396 if (attr->max_dest_rd_atomic) 2397 context->params2 |= 2398 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 2399 optpar |= MLX4_QP_OPTPAR_RRA_MAX; 2400 } 2401 2402 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 2403 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask); 2404 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE; 2405 } 2406 2407 if (ibsrq) 2408 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC); 2409 2410 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 2411 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 2412 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT; 2413 } 2414 if (attr_mask & IB_QP_RQ_PSN) 2415 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 2416 2417 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */ 2418 if (attr_mask & IB_QP_QKEY) { 2419 if (qp->mlx4_ib_qp_type & 2420 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) 2421 context->qkey = cpu_to_be32(IB_QP_SET_QKEY); 2422 else { 2423 if (mlx4_is_mfunc(dev->dev) && 2424 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) && 2425 (attr->qkey & MLX4_RESERVED_QKEY_MASK) == 2426 MLX4_RESERVED_QKEY_BASE) { 2427 pr_err("Cannot use reserved QKEY" 2428 " 0x%x (range 0xffff0000..0xffffffff" 2429 " is reserved)\n", attr->qkey); 2430 err = -EINVAL; 2431 goto out; 2432 } 2433 context->qkey = cpu_to_be32(attr->qkey); 2434 } 2435 optpar |= MLX4_QP_OPTPAR_Q_KEY; 2436 } 2437 2438 if (ibsrq) 2439 context->srqn = cpu_to_be32(1 << 24 | 2440 to_msrq(ibsrq)->msrq.srqn); 2441 2442 if (qp->rq.wqe_cnt && 2443 cur_state == IB_QPS_RESET && 2444 new_state == IB_QPS_INIT) 2445 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2446 2447 if (cur_state == IB_QPS_INIT && 2448 new_state == IB_QPS_RTR && 2449 (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI || 2450 qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) { 2451 context->pri_path.sched_queue = (qp->port - 1) << 6; 2452 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 2453 qp->mlx4_ib_qp_type & 2454 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) { 2455 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE; 2456 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI) 2457 context->pri_path.fl = 0x80; 2458 } else { 2459 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 2460 context->pri_path.fl = 0x80; 2461 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE; 2462 } 2463 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 2464 IB_LINK_LAYER_ETHERNET) { 2465 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI || 2466 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) 2467 context->pri_path.feup = 1 << 7; /* don't fsm */ 2468 /* handle smac_index */ 2469 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD || 2470 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI || 2471 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) { 2472 err = handle_eth_ud_smac_index(dev, qp, context); 2473 if (err) { 2474 err = -EINVAL; 2475 goto out; 2476 } 2477 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 2478 dev->qp1_proxy[qp->port - 1] = qp; 2479 } 2480 } 2481 } 2482 2483 if (qp_type == IB_QPT_RAW_PACKET) { 2484 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) | 2485 MLX4_IB_LINK_TYPE_ETH; 2486 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 2487 /* set QP to receive both tunneled & non-tunneled packets */ 2488 if (!rwq_ind_tbl) 2489 context->srqn = cpu_to_be32(7 << 28); 2490 } 2491 } 2492 2493 if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) { 2494 int is_eth = rdma_port_get_link_layer( 2495 &dev->ib_dev, qp->port) == 2496 IB_LINK_LAYER_ETHERNET; 2497 if (is_eth) { 2498 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH; 2499 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH; 2500 } 2501 } 2502 2503 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 2504 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 2505 sqd_event = 1; 2506 else 2507 sqd_event = 0; 2508 2509 if (!ucontext && 2510 cur_state == IB_QPS_RESET && 2511 new_state == IB_QPS_INIT) 2512 context->rlkey_roce_mode |= (1 << 4); 2513 2514 /* 2515 * Before passing a kernel QP to the HW, make sure that the 2516 * ownership bits of the send queue are set and the SQ 2517 * headroom is stamped so that the hardware doesn't start 2518 * processing stale work requests. 2519 */ 2520 if (!ucontext && 2521 cur_state == IB_QPS_RESET && 2522 new_state == IB_QPS_INIT) { 2523 struct mlx4_wqe_ctrl_seg *ctrl; 2524 int i; 2525 2526 for (i = 0; i < qp->sq.wqe_cnt; ++i) { 2527 ctrl = get_send_wqe(qp, i); 2528 ctrl->owner_opcode = cpu_to_be32(1 << 31); 2529 ctrl->qpn_vlan.fence_size = 2530 1 << (qp->sq.wqe_shift - 4); 2531 stamp_send_wqe(qp, i); 2532 } 2533 } 2534 2535 if (rwq_ind_tbl && 2536 cur_state == IB_QPS_RESET && 2537 new_state == IB_QPS_INIT) { 2538 fill_qp_rss_context(context, qp); 2539 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET); 2540 } 2541 2542 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state), 2543 to_mlx4_state(new_state), context, optpar, 2544 sqd_event, &qp->mqp); 2545 if (err) 2546 goto out; 2547 2548 qp->state = new_state; 2549 2550 if (attr_mask & IB_QP_ACCESS_FLAGS) 2551 qp->atomic_rd_en = attr->qp_access_flags; 2552 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2553 qp->resp_depth = attr->max_dest_rd_atomic; 2554 if (attr_mask & IB_QP_PORT) { 2555 qp->port = attr->port_num; 2556 update_mcg_macs(dev, qp); 2557 } 2558 if (attr_mask & IB_QP_ALT_PATH) 2559 qp->alt_port = attr->alt_port_num; 2560 2561 if (is_sqp(dev, qp)) 2562 store_sqp_attrs(qp->sqp, attr, attr_mask); 2563 2564 /* 2565 * If we moved QP0 to RTR, bring the IB link up; if we moved 2566 * QP0 to RESET or ERROR, bring the link back down. 2567 */ 2568 if (is_qp0(dev, qp)) { 2569 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR) 2570 if (mlx4_INIT_PORT(dev->dev, qp->port)) 2571 pr_warn("INIT_PORT failed for port %d\n", 2572 qp->port); 2573 2574 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 2575 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR)) 2576 mlx4_CLOSE_PORT(dev->dev, qp->port); 2577 } 2578 2579 /* 2580 * If we moved a kernel QP to RESET, clean up all old CQ 2581 * entries and reinitialize the QP. 2582 */ 2583 if (new_state == IB_QPS_RESET) { 2584 if (!ucontext) { 2585 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 2586 ibsrq ? to_msrq(ibsrq) : NULL); 2587 if (send_cq != recv_cq) 2588 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 2589 2590 qp->rq.head = 0; 2591 qp->rq.tail = 0; 2592 qp->sq.head = 0; 2593 qp->sq.tail = 0; 2594 qp->sq_next_wqe = 0; 2595 if (qp->rq.wqe_cnt) 2596 *qp->db.db = 0; 2597 2598 if (qp->flags & MLX4_IB_QP_NETIF) 2599 mlx4_ib_steer_qp_reg(dev, qp, 0); 2600 } 2601 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) { 2602 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2603 qp->pri.smac = 0; 2604 qp->pri.smac_port = 0; 2605 } 2606 if (qp->alt.smac) { 2607 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2608 qp->alt.smac = 0; 2609 } 2610 if (qp->pri.vid < 0x1000) { 2611 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 2612 qp->pri.vid = 0xFFFF; 2613 qp->pri.candidate_vid = 0xFFFF; 2614 qp->pri.update_vid = 0; 2615 } 2616 2617 if (qp->alt.vid < 0x1000) { 2618 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 2619 qp->alt.vid = 0xFFFF; 2620 qp->alt.candidate_vid = 0xFFFF; 2621 qp->alt.update_vid = 0; 2622 } 2623 } 2624 out: 2625 if (err && qp->counter_index) 2626 mlx4_ib_free_qp_counter(dev, qp); 2627 if (err && steer_qp) 2628 mlx4_ib_steer_qp_reg(dev, qp, 0); 2629 kfree(context); 2630 if (qp->pri.candidate_smac || 2631 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) { 2632 if (err) { 2633 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac); 2634 } else { 2635 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) 2636 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2637 qp->pri.smac = qp->pri.candidate_smac; 2638 qp->pri.smac_index = qp->pri.candidate_smac_index; 2639 qp->pri.smac_port = qp->pri.candidate_smac_port; 2640 } 2641 qp->pri.candidate_smac = 0; 2642 qp->pri.candidate_smac_index = 0; 2643 qp->pri.candidate_smac_port = 0; 2644 } 2645 if (qp->alt.candidate_smac) { 2646 if (err) { 2647 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac); 2648 } else { 2649 if (qp->alt.smac) 2650 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2651 qp->alt.smac = qp->alt.candidate_smac; 2652 qp->alt.smac_index = qp->alt.candidate_smac_index; 2653 qp->alt.smac_port = qp->alt.candidate_smac_port; 2654 } 2655 qp->alt.candidate_smac = 0; 2656 qp->alt.candidate_smac_index = 0; 2657 qp->alt.candidate_smac_port = 0; 2658 } 2659 2660 if (qp->pri.update_vid) { 2661 if (err) { 2662 if (qp->pri.candidate_vid < 0x1000) 2663 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port, 2664 qp->pri.candidate_vid); 2665 } else { 2666 if (qp->pri.vid < 0x1000) 2667 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, 2668 qp->pri.vid); 2669 qp->pri.vid = qp->pri.candidate_vid; 2670 qp->pri.vlan_port = qp->pri.candidate_vlan_port; 2671 qp->pri.vlan_index = qp->pri.candidate_vlan_index; 2672 } 2673 qp->pri.candidate_vid = 0xFFFF; 2674 qp->pri.update_vid = 0; 2675 } 2676 2677 if (qp->alt.update_vid) { 2678 if (err) { 2679 if (qp->alt.candidate_vid < 0x1000) 2680 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port, 2681 qp->alt.candidate_vid); 2682 } else { 2683 if (qp->alt.vid < 0x1000) 2684 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, 2685 qp->alt.vid); 2686 qp->alt.vid = qp->alt.candidate_vid; 2687 qp->alt.vlan_port = qp->alt.candidate_vlan_port; 2688 qp->alt.vlan_index = qp->alt.candidate_vlan_index; 2689 } 2690 qp->alt.candidate_vid = 0xFFFF; 2691 qp->alt.update_vid = 0; 2692 } 2693 2694 return err; 2695 } 2696 2697 enum { 2698 MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE | 2699 IB_QP_PORT), 2700 }; 2701 2702 static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2703 int attr_mask, struct ib_udata *udata) 2704 { 2705 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 2706 struct mlx4_ib_qp *qp = to_mqp(ibqp); 2707 enum ib_qp_state cur_state, new_state; 2708 int err = -EINVAL; 2709 mutex_lock(&qp->mutex); 2710 2711 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2712 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2713 2714 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, 2715 attr_mask)) { 2716 pr_debug("qpn 0x%x: invalid attribute mask specified " 2717 "for transition %d to %d. qp_type %d," 2718 " attr_mask 0x%x\n", 2719 ibqp->qp_num, cur_state, new_state, 2720 ibqp->qp_type, attr_mask); 2721 goto out; 2722 } 2723 2724 if (ibqp->rwq_ind_tbl) { 2725 if (!(((cur_state == IB_QPS_RESET) && 2726 (new_state == IB_QPS_INIT)) || 2727 ((cur_state == IB_QPS_INIT) && 2728 (new_state == IB_QPS_RTR)))) { 2729 pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n", 2730 ibqp->qp_num, cur_state, new_state); 2731 2732 err = -EOPNOTSUPP; 2733 goto out; 2734 } 2735 2736 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) { 2737 pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n", 2738 ibqp->qp_num, attr_mask, cur_state, new_state); 2739 2740 err = -EOPNOTSUPP; 2741 goto out; 2742 } 2743 } 2744 2745 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) { 2746 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 2747 if ((ibqp->qp_type == IB_QPT_RC) || 2748 (ibqp->qp_type == IB_QPT_UD) || 2749 (ibqp->qp_type == IB_QPT_UC) || 2750 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 2751 (ibqp->qp_type == IB_QPT_XRC_INI)) { 2752 attr->port_num = mlx4_ib_bond_next_port(dev); 2753 } 2754 } else { 2755 /* no sense in changing port_num 2756 * when ports are bonded */ 2757 attr_mask &= ~IB_QP_PORT; 2758 } 2759 } 2760 2761 if ((attr_mask & IB_QP_PORT) && 2762 (attr->port_num == 0 || attr->port_num > dev->num_ports)) { 2763 pr_debug("qpn 0x%x: invalid port number (%d) specified " 2764 "for transition %d to %d. qp_type %d\n", 2765 ibqp->qp_num, attr->port_num, cur_state, 2766 new_state, ibqp->qp_type); 2767 goto out; 2768 } 2769 2770 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) && 2771 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) != 2772 IB_LINK_LAYER_ETHERNET)) 2773 goto out; 2774 2775 if (attr_mask & IB_QP_PKEY_INDEX) { 2776 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2777 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) { 2778 pr_debug("qpn 0x%x: invalid pkey index (%d) specified " 2779 "for transition %d to %d. qp_type %d\n", 2780 ibqp->qp_num, attr->pkey_index, cur_state, 2781 new_state, ibqp->qp_type); 2782 goto out; 2783 } 2784 } 2785 2786 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 2787 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) { 2788 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. " 2789 "Transition %d to %d. qp_type %d\n", 2790 ibqp->qp_num, attr->max_rd_atomic, cur_state, 2791 new_state, ibqp->qp_type); 2792 goto out; 2793 } 2794 2795 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 2796 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) { 2797 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. " 2798 "Transition %d to %d. qp_type %d\n", 2799 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state, 2800 new_state, ibqp->qp_type); 2801 goto out; 2802 } 2803 2804 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 2805 err = 0; 2806 goto out; 2807 } 2808 2809 if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) { 2810 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num, 2811 udata); 2812 if (err) 2813 goto out; 2814 } 2815 2816 err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask, 2817 cur_state, new_state, udata); 2818 2819 if (ibqp->rwq_ind_tbl && err) 2820 bring_down_rss_rwqs(ibqp->rwq_ind_tbl, udata); 2821 2822 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) 2823 attr->port_num = 1; 2824 2825 out: 2826 mutex_unlock(&qp->mutex); 2827 return err; 2828 } 2829 2830 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2831 int attr_mask, struct ib_udata *udata) 2832 { 2833 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 2834 int ret; 2835 2836 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 2837 return -EOPNOTSUPP; 2838 2839 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata); 2840 2841 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 2842 struct mlx4_ib_sqp *sqp = mqp->sqp; 2843 int err = 0; 2844 2845 if (sqp->roce_v2_gsi) 2846 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask); 2847 if (err) 2848 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n", 2849 err); 2850 } 2851 return ret; 2852 } 2853 2854 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey) 2855 { 2856 int i; 2857 for (i = 0; i < dev->caps.num_ports; i++) { 2858 if (qpn == dev->caps.spec_qps[i].qp0_proxy || 2859 qpn == dev->caps.spec_qps[i].qp0_tunnel) { 2860 *qkey = dev->caps.spec_qps[i].qp0_qkey; 2861 return 0; 2862 } 2863 } 2864 return -EINVAL; 2865 } 2866 2867 static int build_sriov_qp0_header(struct mlx4_ib_qp *qp, 2868 const struct ib_ud_wr *wr, 2869 void *wqe, unsigned *mlx_seg_len) 2870 { 2871 struct mlx4_ib_dev *mdev = to_mdev(qp->ibqp.device); 2872 struct mlx4_ib_sqp *sqp = qp->sqp; 2873 struct ib_device *ib_dev = qp->ibqp.device; 2874 struct mlx4_wqe_mlx_seg *mlx = wqe; 2875 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 2876 struct mlx4_ib_ah *ah = to_mah(wr->ah); 2877 u16 pkey; 2878 u32 qkey; 2879 int send_size; 2880 int header_size; 2881 int spc; 2882 int err; 2883 int i; 2884 2885 if (wr->wr.opcode != IB_WR_SEND) 2886 return -EINVAL; 2887 2888 send_size = 0; 2889 2890 for (i = 0; i < wr->wr.num_sge; ++i) 2891 send_size += wr->wr.sg_list[i].length; 2892 2893 /* for proxy-qp0 sends, need to add in size of tunnel header */ 2894 /* for tunnel-qp0 sends, tunnel header is already in s/g list */ 2895 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) 2896 send_size += sizeof (struct mlx4_ib_tunnel_header); 2897 2898 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header); 2899 2900 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) { 2901 sqp->ud_header.lrh.service_level = 2902 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 2903 sqp->ud_header.lrh.destination_lid = 2904 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2905 sqp->ud_header.lrh.source_lid = 2906 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2907 } 2908 2909 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 2910 2911 /* force loopback */ 2912 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR); 2913 mlx->rlid = sqp->ud_header.lrh.destination_lid; 2914 2915 sqp->ud_header.lrh.virtual_lane = 0; 2916 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED); 2917 err = ib_get_cached_pkey(ib_dev, qp->port, 0, &pkey); 2918 if (err) 2919 return err; 2920 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 2921 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER) 2922 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn); 2923 else 2924 sqp->ud_header.bth.destination_qpn = 2925 cpu_to_be32(mdev->dev->caps.spec_qps[qp->port - 1].qp0_tunnel); 2926 2927 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 2928 if (mlx4_is_master(mdev->dev)) { 2929 if (mlx4_get_parav_qkey(mdev->dev, qp->mqp.qpn, &qkey)) 2930 return -EINVAL; 2931 } else { 2932 if (vf_get_qp0_qkey(mdev->dev, qp->mqp.qpn, &qkey)) 2933 return -EINVAL; 2934 } 2935 sqp->ud_header.deth.qkey = cpu_to_be32(qkey); 2936 sqp->ud_header.deth.source_qpn = cpu_to_be32(qp->mqp.qpn); 2937 2938 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2939 sqp->ud_header.immediate_present = 0; 2940 2941 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 2942 2943 /* 2944 * Inline data segments may not cross a 64 byte boundary. If 2945 * our UD header is bigger than the space available up to the 2946 * next 64 byte boundary in the WQE, use two inline data 2947 * segments to hold the UD header. 2948 */ 2949 spc = MLX4_INLINE_ALIGN - 2950 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2951 if (header_size <= spc) { 2952 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 2953 memcpy(inl + 1, sqp->header_buf, header_size); 2954 i = 1; 2955 } else { 2956 inl->byte_count = cpu_to_be32(1 << 31 | spc); 2957 memcpy(inl + 1, sqp->header_buf, spc); 2958 2959 inl = (void *) (inl + 1) + spc; 2960 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 2961 /* 2962 * Need a barrier here to make sure all the data is 2963 * visible before the byte_count field is set. 2964 * Otherwise the HCA prefetcher could grab the 64-byte 2965 * chunk with this inline segment and get a valid (!= 2966 * 0xffffffff) byte count but stale data, and end up 2967 * generating a packet with bad headers. 2968 * 2969 * The first inline segment's byte_count field doesn't 2970 * need a barrier, because it comes after a 2971 * control/MLX segment and therefore is at an offset 2972 * of 16 mod 64. 2973 */ 2974 wmb(); 2975 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 2976 i = 2; 2977 } 2978 2979 *mlx_seg_len = 2980 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 2981 return 0; 2982 } 2983 2984 static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num) 2985 { 2986 union sl2vl_tbl_to_u64 tmp_vltab; 2987 u8 vl; 2988 2989 if (sl > 15) 2990 return 0xf; 2991 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]); 2992 vl = tmp_vltab.sl8[sl >> 1]; 2993 if (sl & 1) 2994 vl &= 0x0f; 2995 else 2996 vl >>= 4; 2997 return vl; 2998 } 2999 3000 static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num, 3001 int index, union ib_gid *gid, 3002 enum ib_gid_type *gid_type) 3003 { 3004 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 3005 struct mlx4_port_gid_table *port_gid_table; 3006 unsigned long flags; 3007 3008 port_gid_table = &iboe->gids[port_num - 1]; 3009 spin_lock_irqsave(&iboe->lock, flags); 3010 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid)); 3011 *gid_type = port_gid_table->gids[index].gid_type; 3012 spin_unlock_irqrestore(&iboe->lock, flags); 3013 if (rdma_is_zero_gid(gid)) 3014 return -ENOENT; 3015 3016 return 0; 3017 } 3018 3019 #define MLX4_ROCEV2_QP1_SPORT 0xC000 3020 static int build_mlx_header(struct mlx4_ib_qp *qp, const struct ib_ud_wr *wr, 3021 void *wqe, unsigned *mlx_seg_len) 3022 { 3023 struct mlx4_ib_sqp *sqp = qp->sqp; 3024 struct ib_device *ib_dev = qp->ibqp.device; 3025 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev); 3026 struct mlx4_wqe_mlx_seg *mlx = wqe; 3027 struct mlx4_wqe_ctrl_seg *ctrl = wqe; 3028 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 3029 struct mlx4_ib_ah *ah = to_mah(wr->ah); 3030 union ib_gid sgid; 3031 u16 pkey; 3032 int send_size; 3033 int header_size; 3034 int spc; 3035 int i; 3036 int err = 0; 3037 u16 vlan = 0xffff; 3038 bool is_eth; 3039 bool is_vlan = false; 3040 bool is_grh; 3041 bool is_udp = false; 3042 int ip_version = 0; 3043 3044 send_size = 0; 3045 for (i = 0; i < wr->wr.num_sge; ++i) 3046 send_size += wr->wr.sg_list[i].length; 3047 3048 is_eth = rdma_port_get_link_layer(qp->ibqp.device, qp->port) == IB_LINK_LAYER_ETHERNET; 3049 is_grh = mlx4_ib_ah_grh_present(ah); 3050 if (is_eth) { 3051 enum ib_gid_type gid_type; 3052 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 3053 /* When multi-function is enabled, the ib_core gid 3054 * indexes don't necessarily match the hw ones, so 3055 * we must use our own cache */ 3056 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev, 3057 be32_to_cpu(ah->av.ib.port_pd) >> 24, 3058 ah->av.ib.gid_index, &sgid.raw[0]); 3059 if (err) 3060 return err; 3061 } else { 3062 err = fill_gid_by_hw_index(ibdev, qp->port, 3063 ah->av.ib.gid_index, &sgid, 3064 &gid_type); 3065 if (!err) { 3066 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 3067 if (is_udp) { 3068 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid)) 3069 ip_version = 4; 3070 else 3071 ip_version = 6; 3072 is_grh = false; 3073 } 3074 } else { 3075 return err; 3076 } 3077 } 3078 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) { 3079 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff; 3080 is_vlan = true; 3081 } 3082 } 3083 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 3084 ip_version, is_udp, 0, &sqp->ud_header); 3085 if (err) 3086 return err; 3087 3088 if (!is_eth) { 3089 sqp->ud_header.lrh.service_level = 3090 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 3091 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid; 3092 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f); 3093 } 3094 3095 if (is_grh || (ip_version == 6)) { 3096 sqp->ud_header.grh.traffic_class = 3097 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 3098 sqp->ud_header.grh.flow_label = 3099 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff); 3100 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit; 3101 if (is_eth) { 3102 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16); 3103 } else { 3104 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 3105 /* When multi-function is enabled, the ib_core gid 3106 * indexes don't necessarily match the hw ones, so 3107 * we must use our own cache 3108 */ 3109 sqp->ud_header.grh.source_gid.global 3110 .subnet_prefix = 3111 cpu_to_be64(atomic64_read( 3112 &(to_mdev(ib_dev) 3113 ->sriov 3114 .demux[qp->port - 1] 3115 .subnet_prefix))); 3116 sqp->ud_header.grh.source_gid.global 3117 .interface_id = 3118 to_mdev(ib_dev) 3119 ->sriov.demux[qp->port - 1] 3120 .guid_cache[ah->av.ib.gid_index]; 3121 } else { 3122 sqp->ud_header.grh.source_gid = 3123 ah->ibah.sgid_attr->gid; 3124 } 3125 } 3126 memcpy(sqp->ud_header.grh.destination_gid.raw, 3127 ah->av.ib.dgid, 16); 3128 } 3129 3130 if (ip_version == 4) { 3131 sqp->ud_header.ip4.tos = 3132 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 3133 sqp->ud_header.ip4.id = 0; 3134 sqp->ud_header.ip4.frag_off = htons(IP_DF); 3135 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit; 3136 3137 memcpy(&sqp->ud_header.ip4.saddr, 3138 sgid.raw + 12, 4); 3139 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4); 3140 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header); 3141 } 3142 3143 if (is_udp) { 3144 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT); 3145 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT); 3146 sqp->ud_header.udp.csum = 0; 3147 } 3148 3149 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 3150 3151 if (!is_eth) { 3152 mlx->flags |= 3153 cpu_to_be32((!qp->ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) | 3154 (sqp->ud_header.lrh.destination_lid == 3155 IB_LID_PERMISSIVE ? 3156 MLX4_WQE_MLX_SLR : 3157 0) | 3158 (sqp->ud_header.lrh.service_level << 8)); 3159 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000)) 3160 mlx->flags |= cpu_to_be32(0x1); /* force loopback */ 3161 mlx->rlid = sqp->ud_header.lrh.destination_lid; 3162 } 3163 3164 switch (wr->wr.opcode) { 3165 case IB_WR_SEND: 3166 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 3167 sqp->ud_header.immediate_present = 0; 3168 break; 3169 case IB_WR_SEND_WITH_IMM: 3170 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 3171 sqp->ud_header.immediate_present = 1; 3172 sqp->ud_header.immediate_data = wr->wr.ex.imm_data; 3173 break; 3174 default: 3175 return -EINVAL; 3176 } 3177 3178 if (is_eth) { 3179 u16 ether_type; 3180 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13; 3181 3182 ether_type = (!is_udp) ? ETH_P_IBOE: 3183 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6); 3184 3185 mlx->sched_prio = cpu_to_be16(pcp); 3186 3187 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac); 3188 ether_addr_copy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac); 3189 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2); 3190 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4); 3191 3192 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6)) 3193 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK); 3194 if (!is_vlan) { 3195 sqp->ud_header.eth.type = cpu_to_be16(ether_type); 3196 } else { 3197 sqp->ud_header.vlan.type = cpu_to_be16(ether_type); 3198 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp); 3199 } 3200 } else { 3201 sqp->ud_header.lrh.virtual_lane = 3202 !qp->ibqp.qp_num ? 3203 15 : 3204 sl_to_vl(to_mdev(ib_dev), 3205 sqp->ud_header.lrh.service_level, 3206 qp->port); 3207 if (qp->ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15) 3208 return -EINVAL; 3209 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE) 3210 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE; 3211 } 3212 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED); 3213 if (!qp->ibqp.qp_num) 3214 err = ib_get_cached_pkey(ib_dev, qp->port, sqp->pkey_index, 3215 &pkey); 3216 else 3217 err = ib_get_cached_pkey(ib_dev, qp->port, wr->pkey_index, 3218 &pkey); 3219 if (err) 3220 return err; 3221 3222 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 3223 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn); 3224 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 3225 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ? 3226 sqp->qkey : wr->remote_qkey); 3227 sqp->ud_header.deth.source_qpn = cpu_to_be32(qp->ibqp.qp_num); 3228 3229 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 3230 3231 if (0) { 3232 pr_err("built UD header of size %d:\n", header_size); 3233 for (i = 0; i < header_size / 4; ++i) { 3234 if (i % 8 == 0) 3235 pr_err(" [%02x] ", i * 4); 3236 pr_cont(" %08x", 3237 be32_to_cpu(((__be32 *) sqp->header_buf)[i])); 3238 if ((i + 1) % 8 == 0) 3239 pr_cont("\n"); 3240 } 3241 pr_err("\n"); 3242 } 3243 3244 /* 3245 * Inline data segments may not cross a 64 byte boundary. If 3246 * our UD header is bigger than the space available up to the 3247 * next 64 byte boundary in the WQE, use two inline data 3248 * segments to hold the UD header. 3249 */ 3250 spc = MLX4_INLINE_ALIGN - 3251 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 3252 if (header_size <= spc) { 3253 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 3254 memcpy(inl + 1, sqp->header_buf, header_size); 3255 i = 1; 3256 } else { 3257 inl->byte_count = cpu_to_be32(1 << 31 | spc); 3258 memcpy(inl + 1, sqp->header_buf, spc); 3259 3260 inl = (void *) (inl + 1) + spc; 3261 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 3262 /* 3263 * Need a barrier here to make sure all the data is 3264 * visible before the byte_count field is set. 3265 * Otherwise the HCA prefetcher could grab the 64-byte 3266 * chunk with this inline segment and get a valid (!= 3267 * 0xffffffff) byte count but stale data, and end up 3268 * generating a packet with bad headers. 3269 * 3270 * The first inline segment's byte_count field doesn't 3271 * need a barrier, because it comes after a 3272 * control/MLX segment and therefore is at an offset 3273 * of 16 mod 64. 3274 */ 3275 wmb(); 3276 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 3277 i = 2; 3278 } 3279 3280 *mlx_seg_len = 3281 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 3282 return 0; 3283 } 3284 3285 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3286 { 3287 unsigned cur; 3288 struct mlx4_ib_cq *cq; 3289 3290 cur = wq->head - wq->tail; 3291 if (likely(cur + nreq < wq->max_post)) 3292 return 0; 3293 3294 cq = to_mcq(ib_cq); 3295 spin_lock(&cq->lock); 3296 cur = wq->head - wq->tail; 3297 spin_unlock(&cq->lock); 3298 3299 return cur + nreq >= wq->max_post; 3300 } 3301 3302 static __be32 convert_access(int acc) 3303 { 3304 return (acc & IB_ACCESS_REMOTE_ATOMIC ? 3305 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) | 3306 (acc & IB_ACCESS_REMOTE_WRITE ? 3307 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) | 3308 (acc & IB_ACCESS_REMOTE_READ ? 3309 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) | 3310 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) | 3311 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ); 3312 } 3313 3314 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg, 3315 const struct ib_reg_wr *wr) 3316 { 3317 struct mlx4_ib_mr *mr = to_mmr(wr->mr); 3318 3319 fseg->flags = convert_access(wr->access); 3320 fseg->mem_key = cpu_to_be32(wr->key); 3321 fseg->buf_list = cpu_to_be64(mr->page_map); 3322 fseg->start_addr = cpu_to_be64(mr->ibmr.iova); 3323 fseg->reg_len = cpu_to_be64(mr->ibmr.length); 3324 fseg->offset = 0; /* XXX -- is this just for ZBVA? */ 3325 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size)); 3326 fseg->reserved[0] = 0; 3327 fseg->reserved[1] = 0; 3328 } 3329 3330 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey) 3331 { 3332 memset(iseg, 0, sizeof(*iseg)); 3333 iseg->mem_key = cpu_to_be32(rkey); 3334 } 3335 3336 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg, 3337 u64 remote_addr, u32 rkey) 3338 { 3339 rseg->raddr = cpu_to_be64(remote_addr); 3340 rseg->rkey = cpu_to_be32(rkey); 3341 rseg->reserved = 0; 3342 } 3343 3344 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, 3345 const struct ib_atomic_wr *wr) 3346 { 3347 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 3348 aseg->swap_add = cpu_to_be64(wr->swap); 3349 aseg->compare = cpu_to_be64(wr->compare_add); 3350 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) { 3351 aseg->swap_add = cpu_to_be64(wr->compare_add); 3352 aseg->compare = cpu_to_be64(wr->compare_add_mask); 3353 } else { 3354 aseg->swap_add = cpu_to_be64(wr->compare_add); 3355 aseg->compare = 0; 3356 } 3357 3358 } 3359 3360 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg, 3361 const struct ib_atomic_wr *wr) 3362 { 3363 aseg->swap_add = cpu_to_be64(wr->swap); 3364 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask); 3365 aseg->compare = cpu_to_be64(wr->compare_add); 3366 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask); 3367 } 3368 3369 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg, 3370 const struct ib_ud_wr *wr) 3371 { 3372 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av)); 3373 dseg->dqpn = cpu_to_be32(wr->remote_qpn); 3374 dseg->qkey = cpu_to_be32(wr->remote_qkey); 3375 dseg->vlan = to_mah(wr->ah)->av.eth.vlan; 3376 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6); 3377 } 3378 3379 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev, 3380 struct mlx4_wqe_datagram_seg *dseg, 3381 const struct ib_ud_wr *wr, 3382 enum mlx4_ib_qp_type qpt) 3383 { 3384 union mlx4_ext_av *av = &to_mah(wr->ah)->av; 3385 struct mlx4_av sqp_av = {0}; 3386 int port = *((u8 *) &av->ib.port_pd) & 0x3; 3387 3388 /* force loopback */ 3389 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000); 3390 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */ 3391 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel & 3392 cpu_to_be32(0xf0000000); 3393 3394 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av)); 3395 if (qpt == MLX4_IB_QPT_PROXY_GSI) 3396 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel); 3397 else 3398 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel); 3399 /* Use QKEY from the QP context, which is set by master */ 3400 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY); 3401 } 3402 3403 static void build_tunnel_header(const struct ib_ud_wr *wr, void *wqe, 3404 unsigned *mlx_seg_len) 3405 { 3406 struct mlx4_wqe_inline_seg *inl = wqe; 3407 struct mlx4_ib_tunnel_header hdr; 3408 struct mlx4_ib_ah *ah = to_mah(wr->ah); 3409 int spc; 3410 int i; 3411 3412 memcpy(&hdr.av, &ah->av, sizeof hdr.av); 3413 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn); 3414 hdr.pkey_index = cpu_to_be16(wr->pkey_index); 3415 hdr.qkey = cpu_to_be32(wr->remote_qkey); 3416 memcpy(hdr.mac, ah->av.eth.mac, 6); 3417 hdr.vlan = ah->av.eth.vlan; 3418 3419 spc = MLX4_INLINE_ALIGN - 3420 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 3421 if (sizeof (hdr) <= spc) { 3422 memcpy(inl + 1, &hdr, sizeof (hdr)); 3423 wmb(); 3424 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr)); 3425 i = 1; 3426 } else { 3427 memcpy(inl + 1, &hdr, spc); 3428 wmb(); 3429 inl->byte_count = cpu_to_be32(1 << 31 | spc); 3430 3431 inl = (void *) (inl + 1) + spc; 3432 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc); 3433 wmb(); 3434 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc)); 3435 i = 2; 3436 } 3437 3438 *mlx_seg_len = 3439 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16); 3440 } 3441 3442 static void set_mlx_icrc_seg(void *dseg) 3443 { 3444 u32 *t = dseg; 3445 struct mlx4_wqe_inline_seg *iseg = dseg; 3446 3447 t[1] = 0; 3448 3449 /* 3450 * Need a barrier here before writing the byte_count field to 3451 * make sure that all the data is visible before the 3452 * byte_count field is set. Otherwise, if the segment begins 3453 * a new cacheline, the HCA prefetcher could grab the 64-byte 3454 * chunk and get a valid (!= * 0xffffffff) byte count but 3455 * stale data, and end up sending the wrong data. 3456 */ 3457 wmb(); 3458 3459 iseg->byte_count = cpu_to_be32((1 << 31) | 4); 3460 } 3461 3462 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 3463 { 3464 dseg->lkey = cpu_to_be32(sg->lkey); 3465 dseg->addr = cpu_to_be64(sg->addr); 3466 3467 /* 3468 * Need a barrier here before writing the byte_count field to 3469 * make sure that all the data is visible before the 3470 * byte_count field is set. Otherwise, if the segment begins 3471 * a new cacheline, the HCA prefetcher could grab the 64-byte 3472 * chunk and get a valid (!= * 0xffffffff) byte count but 3473 * stale data, and end up sending the wrong data. 3474 */ 3475 wmb(); 3476 3477 dseg->byte_count = cpu_to_be32(sg->length); 3478 } 3479 3480 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 3481 { 3482 dseg->byte_count = cpu_to_be32(sg->length); 3483 dseg->lkey = cpu_to_be32(sg->lkey); 3484 dseg->addr = cpu_to_be64(sg->addr); 3485 } 3486 3487 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, 3488 const struct ib_ud_wr *wr, struct mlx4_ib_qp *qp, 3489 unsigned *lso_seg_len, __be32 *lso_hdr_sz, __be32 *blh) 3490 { 3491 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16); 3492 3493 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE)) 3494 *blh = cpu_to_be32(1 << 6); 3495 3496 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) && 3497 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4))) 3498 return -EINVAL; 3499 3500 memcpy(wqe->header, wr->header, wr->hlen); 3501 3502 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen); 3503 *lso_seg_len = halign; 3504 return 0; 3505 } 3506 3507 static __be32 send_ieth(const struct ib_send_wr *wr) 3508 { 3509 switch (wr->opcode) { 3510 case IB_WR_SEND_WITH_IMM: 3511 case IB_WR_RDMA_WRITE_WITH_IMM: 3512 return wr->ex.imm_data; 3513 3514 case IB_WR_SEND_WITH_INV: 3515 return cpu_to_be32(wr->ex.invalidate_rkey); 3516 3517 default: 3518 return 0; 3519 } 3520 } 3521 3522 static void add_zero_len_inline(void *wqe) 3523 { 3524 struct mlx4_wqe_inline_seg *inl = wqe; 3525 memset(wqe, 0, 16); 3526 inl->byte_count = cpu_to_be32(1 << 31); 3527 } 3528 3529 static int _mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 3530 const struct ib_send_wr **bad_wr, bool drain) 3531 { 3532 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3533 void *wqe; 3534 struct mlx4_wqe_ctrl_seg *ctrl; 3535 struct mlx4_wqe_data_seg *dseg; 3536 unsigned long flags; 3537 int nreq; 3538 int err = 0; 3539 unsigned ind; 3540 int size; 3541 unsigned seglen; 3542 __be32 dummy; 3543 __be32 *lso_wqe; 3544 __be32 lso_hdr_sz; 3545 __be32 blh; 3546 int i; 3547 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 3548 3549 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 3550 struct mlx4_ib_sqp *sqp = qp->sqp; 3551 3552 if (sqp->roce_v2_gsi) { 3553 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah); 3554 enum ib_gid_type gid_type; 3555 union ib_gid gid; 3556 3557 if (!fill_gid_by_hw_index(mdev, qp->port, 3558 ah->av.ib.gid_index, 3559 &gid, &gid_type)) 3560 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ? 3561 to_mqp(sqp->roce_v2_gsi) : qp; 3562 else 3563 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n", 3564 ah->av.ib.gid_index); 3565 } 3566 } 3567 3568 spin_lock_irqsave(&qp->sq.lock, flags); 3569 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR && 3570 !drain) { 3571 err = -EIO; 3572 *bad_wr = wr; 3573 nreq = 0; 3574 goto out; 3575 } 3576 3577 ind = qp->sq_next_wqe; 3578 3579 for (nreq = 0; wr; ++nreq, wr = wr->next) { 3580 lso_wqe = &dummy; 3581 blh = 0; 3582 3583 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 3584 err = -ENOMEM; 3585 *bad_wr = wr; 3586 goto out; 3587 } 3588 3589 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 3590 err = -EINVAL; 3591 *bad_wr = wr; 3592 goto out; 3593 } 3594 3595 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 3596 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id; 3597 3598 ctrl->srcrb_flags = 3599 (wr->send_flags & IB_SEND_SIGNALED ? 3600 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) | 3601 (wr->send_flags & IB_SEND_SOLICITED ? 3602 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) | 3603 ((wr->send_flags & IB_SEND_IP_CSUM) ? 3604 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 3605 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) | 3606 qp->sq_signal_bits; 3607 3608 ctrl->imm = send_ieth(wr); 3609 3610 wqe += sizeof *ctrl; 3611 size = sizeof *ctrl / 16; 3612 3613 switch (qp->mlx4_ib_qp_type) { 3614 case MLX4_IB_QPT_RC: 3615 case MLX4_IB_QPT_UC: 3616 switch (wr->opcode) { 3617 case IB_WR_ATOMIC_CMP_AND_SWP: 3618 case IB_WR_ATOMIC_FETCH_AND_ADD: 3619 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD: 3620 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr, 3621 atomic_wr(wr)->rkey); 3622 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3623 3624 set_atomic_seg(wqe, atomic_wr(wr)); 3625 wqe += sizeof (struct mlx4_wqe_atomic_seg); 3626 3627 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3628 sizeof (struct mlx4_wqe_atomic_seg)) / 16; 3629 3630 break; 3631 3632 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3633 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr, 3634 atomic_wr(wr)->rkey); 3635 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3636 3637 set_masked_atomic_seg(wqe, atomic_wr(wr)); 3638 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg); 3639 3640 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3641 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16; 3642 3643 break; 3644 3645 case IB_WR_RDMA_READ: 3646 case IB_WR_RDMA_WRITE: 3647 case IB_WR_RDMA_WRITE_WITH_IMM: 3648 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr, 3649 rdma_wr(wr)->rkey); 3650 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3651 size += sizeof (struct mlx4_wqe_raddr_seg) / 16; 3652 break; 3653 3654 case IB_WR_LOCAL_INV: 3655 ctrl->srcrb_flags |= 3656 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3657 set_local_inv_seg(wqe, wr->ex.invalidate_rkey); 3658 wqe += sizeof (struct mlx4_wqe_local_inval_seg); 3659 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16; 3660 break; 3661 3662 case IB_WR_REG_MR: 3663 ctrl->srcrb_flags |= 3664 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3665 set_reg_seg(wqe, reg_wr(wr)); 3666 wqe += sizeof(struct mlx4_wqe_fmr_seg); 3667 size += sizeof(struct mlx4_wqe_fmr_seg) / 16; 3668 break; 3669 3670 default: 3671 /* No extra segments required for sends */ 3672 break; 3673 } 3674 break; 3675 3676 case MLX4_IB_QPT_TUN_SMI_OWNER: 3677 err = build_sriov_qp0_header(qp, ud_wr(wr), ctrl, 3678 &seglen); 3679 if (unlikely(err)) { 3680 *bad_wr = wr; 3681 goto out; 3682 } 3683 wqe += seglen; 3684 size += seglen / 16; 3685 break; 3686 case MLX4_IB_QPT_TUN_SMI: 3687 case MLX4_IB_QPT_TUN_GSI: 3688 /* this is a UD qp used in MAD responses to slaves. */ 3689 set_datagram_seg(wqe, ud_wr(wr)); 3690 /* set the forced-loopback bit in the data seg av */ 3691 *(__be32 *) wqe |= cpu_to_be32(0x80000000); 3692 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3693 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3694 break; 3695 case MLX4_IB_QPT_UD: 3696 set_datagram_seg(wqe, ud_wr(wr)); 3697 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3698 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3699 3700 if (wr->opcode == IB_WR_LSO) { 3701 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen, 3702 &lso_hdr_sz, &blh); 3703 if (unlikely(err)) { 3704 *bad_wr = wr; 3705 goto out; 3706 } 3707 lso_wqe = (__be32 *) wqe; 3708 wqe += seglen; 3709 size += seglen / 16; 3710 } 3711 break; 3712 3713 case MLX4_IB_QPT_PROXY_SMI_OWNER: 3714 err = build_sriov_qp0_header(qp, ud_wr(wr), ctrl, 3715 &seglen); 3716 if (unlikely(err)) { 3717 *bad_wr = wr; 3718 goto out; 3719 } 3720 wqe += seglen; 3721 size += seglen / 16; 3722 /* to start tunnel header on a cache-line boundary */ 3723 add_zero_len_inline(wqe); 3724 wqe += 16; 3725 size++; 3726 build_tunnel_header(ud_wr(wr), wqe, &seglen); 3727 wqe += seglen; 3728 size += seglen / 16; 3729 break; 3730 case MLX4_IB_QPT_PROXY_SMI: 3731 case MLX4_IB_QPT_PROXY_GSI: 3732 /* If we are tunneling special qps, this is a UD qp. 3733 * In this case we first add a UD segment targeting 3734 * the tunnel qp, and then add a header with address 3735 * information */ 3736 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, 3737 ud_wr(wr), 3738 qp->mlx4_ib_qp_type); 3739 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3740 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3741 build_tunnel_header(ud_wr(wr), wqe, &seglen); 3742 wqe += seglen; 3743 size += seglen / 16; 3744 break; 3745 3746 case MLX4_IB_QPT_SMI: 3747 case MLX4_IB_QPT_GSI: 3748 err = build_mlx_header(qp, ud_wr(wr), ctrl, &seglen); 3749 if (unlikely(err)) { 3750 *bad_wr = wr; 3751 goto out; 3752 } 3753 wqe += seglen; 3754 size += seglen / 16; 3755 break; 3756 3757 default: 3758 break; 3759 } 3760 3761 /* 3762 * Write data segments in reverse order, so as to 3763 * overwrite cacheline stamp last within each 3764 * cacheline. This avoids issues with WQE 3765 * prefetching. 3766 */ 3767 3768 dseg = wqe; 3769 dseg += wr->num_sge - 1; 3770 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16); 3771 3772 /* Add one more inline data segment for ICRC for MLX sends */ 3773 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 3774 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI || 3775 qp->mlx4_ib_qp_type & 3776 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) { 3777 set_mlx_icrc_seg(dseg + 1); 3778 size += sizeof (struct mlx4_wqe_data_seg) / 16; 3779 } 3780 3781 for (i = wr->num_sge - 1; i >= 0; --i, --dseg) 3782 set_data_seg(dseg, wr->sg_list + i); 3783 3784 /* 3785 * Possibly overwrite stamping in cacheline with LSO 3786 * segment only after making sure all data segments 3787 * are written. 3788 */ 3789 wmb(); 3790 *lso_wqe = lso_hdr_sz; 3791 3792 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ? 3793 MLX4_WQE_CTRL_FENCE : 0) | size; 3794 3795 /* 3796 * Make sure descriptor is fully written before 3797 * setting ownership bit (because HW can start 3798 * executing as soon as we do). 3799 */ 3800 wmb(); 3801 3802 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) { 3803 *bad_wr = wr; 3804 err = -EINVAL; 3805 goto out; 3806 } 3807 3808 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] | 3809 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh; 3810 3811 /* 3812 * We can improve latency by not stamping the last 3813 * send queue WQE until after ringing the doorbell, so 3814 * only stamp here if there are still more WQEs to post. 3815 */ 3816 if (wr->next) 3817 stamp_send_wqe(qp, ind + qp->sq_spare_wqes); 3818 ind++; 3819 } 3820 3821 out: 3822 if (likely(nreq)) { 3823 qp->sq.head += nreq; 3824 3825 /* 3826 * Make sure that descriptors are written before 3827 * doorbell record. 3828 */ 3829 wmb(); 3830 3831 writel_relaxed(qp->doorbell_qpn, 3832 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL); 3833 3834 stamp_send_wqe(qp, ind + qp->sq_spare_wqes - 1); 3835 3836 qp->sq_next_wqe = ind; 3837 } 3838 3839 spin_unlock_irqrestore(&qp->sq.lock, flags); 3840 3841 return err; 3842 } 3843 3844 int mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 3845 const struct ib_send_wr **bad_wr) 3846 { 3847 return _mlx4_ib_post_send(ibqp, wr, bad_wr, false); 3848 } 3849 3850 static int _mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 3851 const struct ib_recv_wr **bad_wr, bool drain) 3852 { 3853 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3854 struct mlx4_wqe_data_seg *scat; 3855 unsigned long flags; 3856 int err = 0; 3857 int nreq; 3858 int ind; 3859 int max_gs; 3860 int i; 3861 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 3862 3863 max_gs = qp->rq.max_gs; 3864 spin_lock_irqsave(&qp->rq.lock, flags); 3865 3866 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR && 3867 !drain) { 3868 err = -EIO; 3869 *bad_wr = wr; 3870 nreq = 0; 3871 goto out; 3872 } 3873 3874 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 3875 3876 for (nreq = 0; wr; ++nreq, wr = wr->next) { 3877 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 3878 err = -ENOMEM; 3879 *bad_wr = wr; 3880 goto out; 3881 } 3882 3883 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 3884 err = -EINVAL; 3885 *bad_wr = wr; 3886 goto out; 3887 } 3888 3889 scat = get_recv_wqe(qp, ind); 3890 3891 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 3892 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 3893 ib_dma_sync_single_for_device(ibqp->device, 3894 qp->sqp_proxy_rcv[ind].map, 3895 sizeof (struct mlx4_ib_proxy_sqp_hdr), 3896 DMA_FROM_DEVICE); 3897 scat->byte_count = 3898 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr)); 3899 /* use dma lkey from upper layer entry */ 3900 scat->lkey = cpu_to_be32(wr->sg_list->lkey); 3901 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map); 3902 scat++; 3903 max_gs--; 3904 } 3905 3906 for (i = 0; i < wr->num_sge; ++i) 3907 __set_data_seg(scat + i, wr->sg_list + i); 3908 3909 if (i < max_gs) { 3910 scat[i].byte_count = 0; 3911 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY); 3912 scat[i].addr = 0; 3913 } 3914 3915 qp->rq.wrid[ind] = wr->wr_id; 3916 3917 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 3918 } 3919 3920 out: 3921 if (likely(nreq)) { 3922 qp->rq.head += nreq; 3923 3924 /* 3925 * Make sure that descriptors are written before 3926 * doorbell record. 3927 */ 3928 wmb(); 3929 3930 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 3931 } 3932 3933 spin_unlock_irqrestore(&qp->rq.lock, flags); 3934 3935 return err; 3936 } 3937 3938 int mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 3939 const struct ib_recv_wr **bad_wr) 3940 { 3941 return _mlx4_ib_post_recv(ibqp, wr, bad_wr, false); 3942 } 3943 3944 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state) 3945 { 3946 switch (mlx4_state) { 3947 case MLX4_QP_STATE_RST: return IB_QPS_RESET; 3948 case MLX4_QP_STATE_INIT: return IB_QPS_INIT; 3949 case MLX4_QP_STATE_RTR: return IB_QPS_RTR; 3950 case MLX4_QP_STATE_RTS: return IB_QPS_RTS; 3951 case MLX4_QP_STATE_SQ_DRAINING: 3952 case MLX4_QP_STATE_SQD: return IB_QPS_SQD; 3953 case MLX4_QP_STATE_SQER: return IB_QPS_SQE; 3954 case MLX4_QP_STATE_ERR: return IB_QPS_ERR; 3955 default: return -1; 3956 } 3957 } 3958 3959 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state) 3960 { 3961 switch (mlx4_mig_state) { 3962 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED; 3963 case MLX4_QP_PM_REARM: return IB_MIG_REARM; 3964 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 3965 default: return -1; 3966 } 3967 } 3968 3969 static int to_ib_qp_access_flags(int mlx4_flags) 3970 { 3971 int ib_flags = 0; 3972 3973 if (mlx4_flags & MLX4_QP_BIT_RRE) 3974 ib_flags |= IB_ACCESS_REMOTE_READ; 3975 if (mlx4_flags & MLX4_QP_BIT_RWE) 3976 ib_flags |= IB_ACCESS_REMOTE_WRITE; 3977 if (mlx4_flags & MLX4_QP_BIT_RAE) 3978 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 3979 3980 return ib_flags; 3981 } 3982 3983 static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev, 3984 struct rdma_ah_attr *ah_attr, 3985 struct mlx4_qp_path *path) 3986 { 3987 struct mlx4_dev *dev = ibdev->dev; 3988 u8 port_num = path->sched_queue & 0x40 ? 2 : 1; 3989 3990 memset(ah_attr, 0, sizeof(*ah_attr)); 3991 if (port_num == 0 || port_num > dev->caps.num_ports) 3992 return; 3993 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num); 3994 3995 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) 3996 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) | 3997 ((path->sched_queue & 4) << 1)); 3998 else 3999 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf); 4000 rdma_ah_set_port_num(ah_attr, port_num); 4001 4002 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 4003 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f); 4004 rdma_ah_set_static_rate(ah_attr, 4005 path->static_rate ? path->static_rate - 5 : 0); 4006 if (path->grh_mylmc & (1 << 7)) { 4007 rdma_ah_set_grh(ah_attr, NULL, 4008 be32_to_cpu(path->tclass_flowlabel) & 0xfffff, 4009 path->mgid_index, 4010 path->hop_limit, 4011 (be32_to_cpu(path->tclass_flowlabel) 4012 >> 20) & 0xff); 4013 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 4014 } 4015 } 4016 4017 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 4018 struct ib_qp_init_attr *qp_init_attr) 4019 { 4020 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 4021 struct mlx4_ib_qp *qp = to_mqp(ibqp); 4022 struct mlx4_qp_context context; 4023 int mlx4_state; 4024 int err = 0; 4025 4026 if (ibqp->rwq_ind_tbl) 4027 return -EOPNOTSUPP; 4028 4029 mutex_lock(&qp->mutex); 4030 4031 if (qp->state == IB_QPS_RESET) { 4032 qp_attr->qp_state = IB_QPS_RESET; 4033 goto done; 4034 } 4035 4036 err = mlx4_qp_query(dev->dev, &qp->mqp, &context); 4037 if (err) { 4038 err = -EINVAL; 4039 goto out; 4040 } 4041 4042 mlx4_state = be32_to_cpu(context.flags) >> 28; 4043 4044 qp->state = to_ib_qp_state(mlx4_state); 4045 qp_attr->qp_state = qp->state; 4046 qp_attr->path_mtu = context.mtu_msgmax >> 5; 4047 qp_attr->path_mig_state = 4048 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3); 4049 qp_attr->qkey = be32_to_cpu(context.qkey); 4050 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff; 4051 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff; 4052 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff; 4053 qp_attr->qp_access_flags = 4054 to_ib_qp_access_flags(be32_to_cpu(context.params2)); 4055 4056 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC || 4057 qp->ibqp.qp_type == IB_QPT_XRC_INI || 4058 qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 4059 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path); 4060 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path); 4061 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f; 4062 qp_attr->alt_port_num = 4063 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 4064 } 4065 4066 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f; 4067 if (qp_attr->qp_state == IB_QPS_INIT) 4068 qp_attr->port_num = qp->port; 4069 else 4070 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1; 4071 4072 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 4073 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING; 4074 4075 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7); 4076 4077 qp_attr->max_dest_rd_atomic = 4078 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7); 4079 qp_attr->min_rnr_timer = 4080 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f; 4081 qp_attr->timeout = context.pri_path.ackto >> 3; 4082 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7; 4083 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7; 4084 qp_attr->alt_timeout = context.alt_path.ackto >> 3; 4085 4086 done: 4087 qp_attr->cur_qp_state = qp_attr->qp_state; 4088 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4089 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4090 4091 if (!ibqp->uobject) { 4092 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt; 4093 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4094 } else { 4095 qp_attr->cap.max_send_wr = 0; 4096 qp_attr->cap.max_send_sge = 0; 4097 } 4098 4099 /* 4100 * We don't support inline sends for kernel QPs (yet), and we 4101 * don't know what userspace's value should be. 4102 */ 4103 qp_attr->cap.max_inline_data = 0; 4104 4105 qp_init_attr->cap = qp_attr->cap; 4106 4107 qp_init_attr->create_flags = 0; 4108 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) 4109 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 4110 4111 if (qp->flags & MLX4_IB_QP_LSO) 4112 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO; 4113 4114 if (qp->flags & MLX4_IB_QP_NETIF) 4115 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP; 4116 4117 qp_init_attr->sq_sig_type = 4118 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ? 4119 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4120 4121 out: 4122 mutex_unlock(&qp->mutex); 4123 return err; 4124 } 4125 4126 struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd, 4127 struct ib_wq_init_attr *init_attr, 4128 struct ib_udata *udata) 4129 { 4130 struct mlx4_dev *dev = to_mdev(pd->device)->dev; 4131 struct ib_qp_init_attr ib_qp_init_attr = {}; 4132 struct mlx4_ib_qp *qp; 4133 struct mlx4_ib_create_wq ucmd; 4134 int err, required_cmd_sz; 4135 4136 if (!udata) 4137 return ERR_PTR(-EINVAL); 4138 4139 required_cmd_sz = offsetof(typeof(ucmd), comp_mask) + 4140 sizeof(ucmd.comp_mask); 4141 if (udata->inlen < required_cmd_sz) { 4142 pr_debug("invalid inlen\n"); 4143 return ERR_PTR(-EINVAL); 4144 } 4145 4146 if (udata->inlen > sizeof(ucmd) && 4147 !ib_is_udata_cleared(udata, sizeof(ucmd), 4148 udata->inlen - sizeof(ucmd))) { 4149 pr_debug("inlen is not supported\n"); 4150 return ERR_PTR(-EOPNOTSUPP); 4151 } 4152 4153 if (udata->outlen) 4154 return ERR_PTR(-EOPNOTSUPP); 4155 4156 if (init_attr->wq_type != IB_WQT_RQ) { 4157 pr_debug("unsupported wq type %d\n", init_attr->wq_type); 4158 return ERR_PTR(-EOPNOTSUPP); 4159 } 4160 4161 if (init_attr->create_flags & ~IB_WQ_FLAGS_SCATTER_FCS || 4162 !(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) { 4163 pr_debug("unsupported create_flags %u\n", 4164 init_attr->create_flags); 4165 return ERR_PTR(-EOPNOTSUPP); 4166 } 4167 4168 qp = kzalloc_obj(*qp); 4169 if (!qp) 4170 return ERR_PTR(-ENOMEM); 4171 4172 mutex_init(&qp->mutex); 4173 qp->pri.vid = 0xFFFF; 4174 qp->alt.vid = 0xFFFF; 4175 4176 ib_qp_init_attr.qp_context = init_attr->wq_context; 4177 ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET; 4178 ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr; 4179 ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge; 4180 ib_qp_init_attr.recv_cq = init_attr->cq; 4181 ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */ 4182 4183 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) 4184 ib_qp_init_attr.create_flags |= IB_QP_CREATE_SCATTER_FCS; 4185 4186 err = create_rq(pd, &ib_qp_init_attr, udata, qp); 4187 if (err) { 4188 kfree(qp); 4189 return ERR_PTR(err); 4190 } 4191 4192 qp->ibwq.event_handler = init_attr->event_handler; 4193 qp->ibwq.wq_num = qp->mqp.qpn; 4194 qp->ibwq.state = IB_WQS_RESET; 4195 4196 return &qp->ibwq; 4197 } 4198 4199 static int ib_wq2qp_state(enum ib_wq_state state) 4200 { 4201 switch (state) { 4202 case IB_WQS_RESET: 4203 return IB_QPS_RESET; 4204 case IB_WQS_RDY: 4205 return IB_QPS_RTR; 4206 default: 4207 return IB_QPS_ERR; 4208 } 4209 } 4210 4211 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state, 4212 struct ib_udata *udata) 4213 { 4214 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4215 enum ib_qp_state qp_cur_state; 4216 enum ib_qp_state qp_new_state; 4217 int attr_mask; 4218 int err; 4219 4220 /* ib_qp.state represents the WQ HW state while ib_wq.state represents 4221 * the WQ logic state. 4222 */ 4223 qp_cur_state = qp->state; 4224 qp_new_state = ib_wq2qp_state(new_state); 4225 4226 if (ib_wq2qp_state(new_state) == qp_cur_state) 4227 return 0; 4228 4229 if (new_state == IB_WQS_RDY) { 4230 struct ib_qp_attr attr = {}; 4231 4232 attr.port_num = qp->port; 4233 attr_mask = IB_QP_PORT; 4234 4235 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr, 4236 attr_mask, IB_QPS_RESET, IB_QPS_INIT, 4237 udata); 4238 if (err) { 4239 pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n", 4240 ibwq->wq_num); 4241 return err; 4242 } 4243 4244 qp_cur_state = IB_QPS_INIT; 4245 } 4246 4247 attr_mask = 0; 4248 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask, 4249 qp_cur_state, qp_new_state, udata); 4250 4251 if (err && (qp_cur_state == IB_QPS_INIT)) { 4252 qp_new_state = IB_QPS_RESET; 4253 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, 4254 attr_mask, IB_QPS_INIT, IB_QPS_RESET, 4255 udata)) { 4256 pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n", 4257 ibwq->wq_num); 4258 qp_new_state = IB_QPS_INIT; 4259 } 4260 } 4261 4262 qp->state = qp_new_state; 4263 4264 return err; 4265 } 4266 4267 int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr, 4268 u32 wq_attr_mask, struct ib_udata *udata) 4269 { 4270 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4271 struct mlx4_ib_modify_wq ucmd = {}; 4272 size_t required_cmd_sz; 4273 enum ib_wq_state cur_state, new_state; 4274 int err = 0; 4275 4276 required_cmd_sz = offsetof(typeof(ucmd), reserved) + 4277 sizeof(ucmd.reserved); 4278 if (udata->inlen < required_cmd_sz) 4279 return -EINVAL; 4280 4281 if (udata->inlen > sizeof(ucmd) && 4282 !ib_is_udata_cleared(udata, sizeof(ucmd), 4283 udata->inlen - sizeof(ucmd))) 4284 return -EOPNOTSUPP; 4285 4286 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 4287 return -EFAULT; 4288 4289 if (ucmd.comp_mask || ucmd.reserved) 4290 return -EOPNOTSUPP; 4291 4292 if (wq_attr_mask & IB_WQ_FLAGS) 4293 return -EOPNOTSUPP; 4294 4295 cur_state = wq_attr->curr_wq_state; 4296 new_state = wq_attr->wq_state; 4297 4298 if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR)) 4299 return -EINVAL; 4300 4301 if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET)) 4302 return -EINVAL; 4303 4304 /* Need to protect against the parent RSS which also may modify WQ 4305 * state. 4306 */ 4307 mutex_lock(&qp->mutex); 4308 4309 /* Can update HW state only if a RSS QP has already associated to this 4310 * WQ, so we can apply its port on the WQ. 4311 */ 4312 if (qp->rss_usecnt) 4313 err = _mlx4_ib_modify_wq(ibwq, new_state, udata); 4314 4315 if (!err) 4316 ibwq->state = new_state; 4317 4318 mutex_unlock(&qp->mutex); 4319 4320 return err; 4321 } 4322 4323 int mlx4_ib_destroy_wq(struct ib_wq *ibwq, struct ib_udata *udata) 4324 { 4325 struct mlx4_ib_dev *dev = to_mdev(ibwq->device); 4326 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4327 4328 if (qp->counter_index) 4329 mlx4_ib_free_qp_counter(dev, qp); 4330 4331 destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, udata); 4332 4333 kfree(qp); 4334 return 0; 4335 } 4336 4337 int mlx4_ib_create_rwq_ind_table(struct ib_rwq_ind_table *rwq_ind_table, 4338 struct ib_rwq_ind_table_init_attr *init_attr, 4339 struct ib_udata *udata) 4340 { 4341 struct mlx4_ib_create_rwq_ind_tbl_resp resp = {}; 4342 unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size; 4343 struct ib_device *device = rwq_ind_table->device; 4344 unsigned int base_wqn; 4345 size_t min_resp_len; 4346 int i, err = 0; 4347 4348 if (udata->inlen > 0 && 4349 !ib_is_udata_cleared(udata, 0, 4350 udata->inlen)) 4351 return -EOPNOTSUPP; 4352 4353 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4354 if (udata->outlen && udata->outlen < min_resp_len) 4355 return -EINVAL; 4356 4357 if (ind_tbl_size > 4358 device->attrs.rss_caps.max_rwq_indirection_table_size) { 4359 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n", 4360 ind_tbl_size, 4361 device->attrs.rss_caps.max_rwq_indirection_table_size); 4362 return -EINVAL; 4363 } 4364 4365 base_wqn = init_attr->ind_tbl[0]->wq_num; 4366 4367 if (base_wqn % ind_tbl_size) { 4368 pr_debug("WQN=0x%x isn't aligned with indirection table size\n", 4369 base_wqn); 4370 return -EINVAL; 4371 } 4372 4373 for (i = 1; i < ind_tbl_size; i++) { 4374 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) { 4375 pr_debug("indirection table's WQNs aren't consecutive\n"); 4376 return -EINVAL; 4377 } 4378 } 4379 4380 if (udata->outlen) { 4381 resp.response_length = offsetof(typeof(resp), response_length) + 4382 sizeof(resp.response_length); 4383 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4384 } 4385 4386 return err; 4387 } 4388 4389 struct mlx4_ib_drain_cqe { 4390 struct ib_cqe cqe; 4391 struct completion done; 4392 }; 4393 4394 static void mlx4_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 4395 { 4396 struct mlx4_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 4397 struct mlx4_ib_drain_cqe, 4398 cqe); 4399 4400 complete(&cqe->done); 4401 } 4402 4403 /* This function returns only once the drained WR was completed */ 4404 static void handle_drain_completion(struct ib_cq *cq, 4405 struct mlx4_ib_drain_cqe *sdrain, 4406 struct mlx4_ib_dev *dev) 4407 { 4408 struct mlx4_dev *mdev = dev->dev; 4409 4410 if (cq->poll_ctx == IB_POLL_DIRECT) { 4411 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 4412 ib_process_cq_direct(cq, -1); 4413 return; 4414 } 4415 4416 if (mdev->persist->state == MLX4_DEVICE_STATE_INTERNAL_ERROR) { 4417 struct mlx4_ib_cq *mcq = to_mcq(cq); 4418 bool triggered = false; 4419 unsigned long flags; 4420 4421 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 4422 /* Make sure that the CQ handler won't run if wasn't run yet */ 4423 if (!mcq->mcq.reset_notify_added) 4424 mcq->mcq.reset_notify_added = 1; 4425 else 4426 triggered = true; 4427 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 4428 4429 if (triggered) { 4430 /* Wait for any scheduled/running task to be ended */ 4431 switch (cq->poll_ctx) { 4432 case IB_POLL_SOFTIRQ: 4433 irq_poll_disable(&cq->iop); 4434 irq_poll_enable(&cq->iop); 4435 break; 4436 case IB_POLL_WORKQUEUE: 4437 cancel_work_sync(&cq->work); 4438 break; 4439 default: 4440 WARN_ON_ONCE(1); 4441 } 4442 } 4443 4444 /* Run the CQ handler - this makes sure that the drain WR will 4445 * be processed if wasn't processed yet. 4446 */ 4447 mcq->mcq.comp(&mcq->mcq); 4448 } 4449 4450 wait_for_completion(&sdrain->done); 4451 } 4452 4453 void mlx4_ib_drain_sq(struct ib_qp *qp) 4454 { 4455 struct ib_cq *cq = qp->send_cq; 4456 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 4457 struct mlx4_ib_drain_cqe sdrain; 4458 const struct ib_send_wr *bad_swr; 4459 struct ib_rdma_wr swr = { 4460 .wr = { 4461 .next = NULL, 4462 { .wr_cqe = &sdrain.cqe, }, 4463 .opcode = IB_WR_RDMA_WRITE, 4464 }, 4465 }; 4466 int ret; 4467 struct mlx4_ib_dev *dev = to_mdev(qp->device); 4468 struct mlx4_dev *mdev = dev->dev; 4469 4470 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 4471 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) { 4472 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 4473 return; 4474 } 4475 4476 sdrain.cqe.done = mlx4_ib_drain_qp_done; 4477 init_completion(&sdrain.done); 4478 4479 ret = _mlx4_ib_post_send(qp, &swr.wr, &bad_swr, true); 4480 if (ret) { 4481 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 4482 return; 4483 } 4484 4485 handle_drain_completion(cq, &sdrain, dev); 4486 } 4487 4488 void mlx4_ib_drain_rq(struct ib_qp *qp) 4489 { 4490 struct ib_cq *cq = qp->recv_cq; 4491 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 4492 struct mlx4_ib_drain_cqe rdrain; 4493 struct ib_recv_wr rwr = {}; 4494 const struct ib_recv_wr *bad_rwr; 4495 int ret; 4496 struct mlx4_ib_dev *dev = to_mdev(qp->device); 4497 struct mlx4_dev *mdev = dev->dev; 4498 4499 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 4500 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) { 4501 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 4502 return; 4503 } 4504 4505 rwr.wr_cqe = &rdrain.cqe; 4506 rdrain.cqe.done = mlx4_ib_drain_qp_done; 4507 init_completion(&rdrain.done); 4508 4509 ret = _mlx4_ib_post_recv(qp, &rwr, &bad_rwr, true); 4510 if (ret) { 4511 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 4512 return; 4513 } 4514 4515 handle_drain_completion(cq, &rdrain, dev); 4516 } 4517 4518 int mlx4_ib_qp_event_init(void) 4519 { 4520 mlx4_ib_qp_event_wq = alloc_ordered_workqueue("mlx4_ib_qp_event_wq", 0); 4521 if (!mlx4_ib_qp_event_wq) 4522 return -ENOMEM; 4523 4524 return 0; 4525 } 4526 4527 void mlx4_ib_qp_event_cleanup(void) 4528 { 4529 destroy_workqueue(mlx4_ib_qp_event_wq); 4530 } 4531