1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/cleanup.h> 35 #include <linux/etherdevice.h> 36 #include <linux/interrupt.h> 37 #include <linux/iopoll.h> 38 #include <linux/kernel.h> 39 #include <linux/types.h> 40 #include <linux/workqueue.h> 41 #include <net/addrconf.h> 42 #include <rdma/ib_addr.h> 43 #include <rdma/ib_cache.h> 44 #include <rdma/ib_umem.h> 45 #include <rdma/uverbs_ioctl.h> 46 47 #include "hclge_main.h" 48 #include "hns_roce_common.h" 49 #include "hns_roce_device.h" 50 #include "hns_roce_cmd.h" 51 #include "hns_roce_hem.h" 52 #include "hns_roce_hw_v2.h" 53 #include "hns_roce_bond.h" 54 55 #define CREATE_TRACE_POINTS 56 #include "hns_roce_trace.h" 57 58 enum { 59 CMD_RST_PRC_OTHERS, 60 CMD_RST_PRC_SUCCESS, 61 CMD_RST_PRC_EBUSY, 62 }; 63 64 enum ecc_resource_type { 65 ECC_RESOURCE_QPC, 66 ECC_RESOURCE_CQC, 67 ECC_RESOURCE_MPT, 68 ECC_RESOURCE_SRQC, 69 ECC_RESOURCE_GMV, 70 ECC_RESOURCE_QPC_TIMER, 71 ECC_RESOURCE_CQC_TIMER, 72 ECC_RESOURCE_SCCC, 73 ECC_RESOURCE_COUNT, 74 }; 75 76 static const struct { 77 const char *name; 78 u8 read_bt0_op; 79 u8 write_bt0_op; 80 } fmea_ram_res[] = { 81 { "ECC_RESOURCE_QPC", 82 HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 }, 83 { "ECC_RESOURCE_CQC", 84 HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 }, 85 { "ECC_RESOURCE_MPT", 86 HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 }, 87 { "ECC_RESOURCE_SRQC", 88 HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 }, 89 /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */ 90 { "ECC_RESOURCE_GMV", 91 0, 0 }, 92 { "ECC_RESOURCE_QPC_TIMER", 93 HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 }, 94 { "ECC_RESOURCE_CQC_TIMER", 95 HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 }, 96 { "ECC_RESOURCE_SCCC", 97 HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 }, 98 }; 99 100 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 101 struct ib_sge *sg) 102 { 103 dseg->lkey = cpu_to_le32(sg->lkey); 104 dseg->addr = cpu_to_le64(sg->addr); 105 dseg->len = cpu_to_le32(sg->length); 106 } 107 108 /* 109 * mapped-value = 1 + real-value 110 * The hns wr opcode real value is start from 0, In order to distinguish between 111 * initialized and uninitialized map values, we plus 1 to the actual value when 112 * defining the mapping, so that the validity can be identified by checking the 113 * mapped value is greater than 0. 114 */ 115 #define HR_OPC_MAP(ib_key, hr_key) \ 116 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 117 118 static const u32 hns_roce_op_code[] = { 119 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 120 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 121 HR_OPC_MAP(SEND, SEND), 122 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 123 HR_OPC_MAP(RDMA_READ, RDMA_READ), 124 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 125 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 126 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 127 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 128 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 129 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 130 }; 131 132 static u32 to_hr_opcode(u32 ib_opcode) 133 { 134 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 135 return HNS_ROCE_V2_WQE_OP_MASK; 136 137 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 138 HNS_ROCE_V2_WQE_OP_MASK; 139 } 140 141 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 142 const struct ib_reg_wr *wr) 143 { 144 struct hns_roce_wqe_frmr_seg *fseg = 145 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 146 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 147 u64 pbl_ba; 148 149 /* use ib_access_flags */ 150 hr_reg_write_bool(fseg, FRMR_BIND_EN, 0); 151 hr_reg_write_bool(fseg, FRMR_ATOMIC, 152 wr->access & IB_ACCESS_REMOTE_ATOMIC); 153 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ); 154 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE); 155 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE); 156 157 /* Data structure reuse may lead to confusion */ 158 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 159 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 160 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 161 162 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 163 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 164 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 165 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 166 167 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages); 168 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ, 169 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 170 hr_reg_clear(fseg, FRMR_BLK_MODE); 171 hr_reg_clear(fseg, FRMR_BLOCK_SIZE); 172 hr_reg_clear(fseg, FRMR_ZBVA); 173 } 174 175 static void set_atomic_seg(const struct ib_send_wr *wr, 176 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 177 unsigned int valid_num_sge) 178 { 179 struct hns_roce_v2_wqe_data_seg *dseg = 180 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 181 struct hns_roce_wqe_atomic_seg *aseg = 182 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg); 183 184 set_data_seg_v2(dseg, wr->sg_list); 185 186 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 187 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 188 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 189 } else { 190 aseg->fetchadd_swap_data = 191 cpu_to_le64(atomic_wr(wr)->compare_add); 192 aseg->cmp_data = 0; 193 } 194 195 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 196 } 197 198 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp, 199 const struct ib_send_wr *wr, 200 unsigned int *sge_idx, u32 msg_len) 201 { 202 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev; 203 unsigned int left_len_in_pg; 204 unsigned int idx = *sge_idx; 205 unsigned int i = 0; 206 unsigned int len; 207 void *addr; 208 void *dseg; 209 210 if (msg_len > qp->sq.ext_sge_cnt * HNS_ROCE_SGE_SIZE) { 211 ibdev_err(ibdev, 212 "no enough extended sge space for inline data.\n"); 213 return -EINVAL; 214 } 215 216 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 217 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg; 218 len = wr->sg_list[0].length; 219 addr = (void *)(unsigned long)(wr->sg_list[0].addr); 220 221 /* When copying data to extended sge space, the left length in page may 222 * not long enough for current user's sge. So the data should be 223 * splited into several parts, one in the first page, and the others in 224 * the subsequent pages. 225 */ 226 while (1) { 227 if (len <= left_len_in_pg) { 228 memcpy(dseg, addr, len); 229 230 idx += len / HNS_ROCE_SGE_SIZE; 231 232 i++; 233 if (i >= wr->num_sge) 234 break; 235 236 left_len_in_pg -= len; 237 len = wr->sg_list[i].length; 238 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 239 dseg += len; 240 } else { 241 memcpy(dseg, addr, left_len_in_pg); 242 243 len -= left_len_in_pg; 244 addr += left_len_in_pg; 245 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE; 246 dseg = hns_roce_get_extend_sge(qp, 247 idx & (qp->sge.sge_cnt - 1)); 248 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT; 249 } 250 } 251 252 *sge_idx = idx; 253 254 return 0; 255 } 256 257 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge, 258 unsigned int *sge_ind, unsigned int cnt) 259 { 260 struct hns_roce_v2_wqe_data_seg *dseg; 261 unsigned int idx = *sge_ind; 262 263 while (cnt > 0) { 264 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 265 if (likely(sge->length)) { 266 set_data_seg_v2(dseg, sge); 267 idx++; 268 cnt--; 269 } 270 sge++; 271 } 272 273 *sge_ind = idx; 274 } 275 276 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len) 277 { 278 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 279 int mtu = ib_mtu_enum_to_int(qp->path_mtu); 280 281 if (mtu < 0 || len > qp->max_inline_data || len > mtu) { 282 ibdev_err(&hr_dev->ib_dev, 283 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", 284 len, qp->max_inline_data, mtu); 285 return false; 286 } 287 288 return true; 289 } 290 291 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 292 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 293 unsigned int *sge_idx) 294 { 295 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 296 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len); 297 struct ib_device *ibdev = &hr_dev->ib_dev; 298 unsigned int curr_idx = *sge_idx; 299 void *dseg = rc_sq_wqe; 300 unsigned int i; 301 int ret; 302 303 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 304 ibdev_err(ibdev, "invalid inline parameters!\n"); 305 return -EINVAL; 306 } 307 308 if (!check_inl_data_len(qp, msg_len)) 309 return -EINVAL; 310 311 dseg += sizeof(struct hns_roce_v2_rc_send_wqe); 312 313 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) { 314 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 315 316 for (i = 0; i < wr->num_sge; i++) { 317 memcpy(dseg, ((void *)wr->sg_list[i].addr), 318 wr->sg_list[i].length); 319 dseg += wr->sg_list[i].length; 320 } 321 } else { 322 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 323 324 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len); 325 if (ret) 326 return ret; 327 328 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx); 329 } 330 331 *sge_idx = curr_idx; 332 333 return 0; 334 } 335 336 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 337 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 338 unsigned int *sge_ind, 339 unsigned int valid_num_sge) 340 { 341 struct hns_roce_v2_wqe_data_seg *dseg = 342 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 343 struct hns_roce_qp *qp = to_hr_qp(ibqp); 344 int j = 0; 345 int i; 346 347 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE, 348 !!(wr->send_flags & IB_SEND_INLINE)); 349 if (wr->send_flags & IB_SEND_INLINE) 350 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind); 351 352 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 353 for (i = 0; i < wr->num_sge; i++) { 354 if (likely(wr->sg_list[i].length)) { 355 set_data_seg_v2(dseg, wr->sg_list + i); 356 dseg++; 357 } 358 } 359 } else { 360 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) { 361 if (likely(wr->sg_list[i].length)) { 362 set_data_seg_v2(dseg, wr->sg_list + i); 363 dseg++; 364 j++; 365 } 366 } 367 368 set_extend_sge(qp, wr->sg_list + i, sge_ind, 369 valid_num_sge - HNS_ROCE_SGE_IN_WQE); 370 } 371 372 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 373 374 return 0; 375 } 376 377 static int check_send_valid(struct hns_roce_dev *hr_dev, 378 struct hns_roce_qp *hr_qp) 379 { 380 if (unlikely(hr_qp->state == IB_QPS_RESET || 381 hr_qp->state == IB_QPS_INIT || 382 hr_qp->state == IB_QPS_RTR)) 383 return -EINVAL; 384 else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 385 return -EIO; 386 387 return 0; 388 } 389 390 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 391 unsigned int *sge_len) 392 { 393 unsigned int valid_num = 0; 394 unsigned int len = 0; 395 int i; 396 397 for (i = 0; i < wr->num_sge; i++) { 398 if (likely(wr->sg_list[i].length)) { 399 len += wr->sg_list[i].length; 400 valid_num++; 401 } 402 } 403 404 *sge_len = len; 405 return valid_num; 406 } 407 408 static __le32 get_immtdata(const struct ib_send_wr *wr) 409 { 410 switch (wr->opcode) { 411 case IB_WR_SEND_WITH_IMM: 412 case IB_WR_RDMA_WRITE_WITH_IMM: 413 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 414 default: 415 return 0; 416 } 417 } 418 419 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 420 const struct ib_send_wr *wr) 421 { 422 u32 ib_op = wr->opcode; 423 424 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM) 425 return -EINVAL; 426 427 ud_sq_wqe->immtdata = get_immtdata(wr); 428 429 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 430 431 return 0; 432 } 433 434 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 435 struct hns_roce_ah *ah) 436 { 437 struct ib_device *ib_dev = ah->ibah.device; 438 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 439 440 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport); 441 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit); 442 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass); 443 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel); 444 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl); 445 446 ud_sq_wqe->sgid_index = ah->av.gid_index; 447 448 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN); 449 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2); 450 451 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 452 return 0; 453 454 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en); 455 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id); 456 457 return 0; 458 } 459 460 static inline int set_ud_wqe(struct hns_roce_qp *qp, 461 const struct ib_send_wr *wr, 462 void *wqe, unsigned int *sge_idx, 463 unsigned int owner_bit) 464 { 465 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 466 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 467 unsigned int curr_idx = *sge_idx; 468 unsigned int valid_num_sge; 469 u32 msg_len = 0; 470 int ret; 471 472 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 473 474 ret = set_ud_opcode(ud_sq_wqe, wr); 475 if (WARN_ON_ONCE(ret)) 476 return ret; 477 478 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 479 480 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE, 481 !!(wr->send_flags & IB_SEND_SIGNALED)); 482 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE, 483 !!(wr->send_flags & IB_SEND_SOLICITED)); 484 485 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn); 486 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge); 487 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX, 488 curr_idx & (qp->sge.sge_cnt - 1)); 489 490 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 491 qp->qkey : ud_wr(wr)->remote_qkey); 492 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn); 493 494 ret = fill_ud_av(ud_sq_wqe, ah); 495 if (ret) 496 return ret; 497 498 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; 499 500 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); 501 502 /* 503 * The pipeline can sequentially post all valid WQEs into WQ buffer, 504 * including new WQEs waiting for the doorbell to update the PI again. 505 * Therefore, the owner bit of WQE MUST be updated after all fields 506 * and extSGEs have been written into DDR instead of cache. 507 */ 508 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 509 dma_wmb(); 510 511 *sge_idx = curr_idx; 512 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit); 513 514 return 0; 515 } 516 517 static int set_rc_opcode(struct hns_roce_dev *hr_dev, 518 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 519 const struct ib_send_wr *wr) 520 { 521 u32 ib_op = wr->opcode; 522 int ret = 0; 523 524 rc_sq_wqe->immtdata = get_immtdata(wr); 525 526 switch (ib_op) { 527 case IB_WR_RDMA_READ: 528 case IB_WR_RDMA_WRITE: 529 case IB_WR_RDMA_WRITE_WITH_IMM: 530 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 531 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 532 break; 533 case IB_WR_SEND: 534 case IB_WR_SEND_WITH_IMM: 535 break; 536 case IB_WR_ATOMIC_CMP_AND_SWP: 537 case IB_WR_ATOMIC_FETCH_AND_ADD: 538 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 539 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 540 break; 541 case IB_WR_REG_MR: 542 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 543 set_frmr_seg(rc_sq_wqe, reg_wr(wr)); 544 else 545 ret = -EOPNOTSUPP; 546 break; 547 case IB_WR_SEND_WITH_INV: 548 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 549 break; 550 default: 551 ret = -EINVAL; 552 } 553 554 if (unlikely(ret)) 555 return ret; 556 557 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 558 559 return ret; 560 } 561 562 static inline int set_rc_wqe(struct hns_roce_qp *qp, 563 const struct ib_send_wr *wr, 564 void *wqe, unsigned int *sge_idx, 565 unsigned int owner_bit) 566 { 567 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 568 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 569 unsigned int curr_idx = *sge_idx; 570 unsigned int valid_num_sge; 571 u32 msg_len = 0; 572 int ret; 573 574 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 575 576 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 577 578 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr); 579 if (WARN_ON_ONCE(ret)) 580 return ret; 581 582 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SO, 583 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 584 585 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE, 586 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 587 588 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE, 589 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 590 591 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX, 592 curr_idx & (qp->sge.sge_cnt - 1)); 593 594 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 595 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) { 596 if (msg_len != ATOMIC_WR_LEN) 597 return -EINVAL; 598 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge); 599 } else if (wr->opcode != IB_WR_REG_MR) { 600 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 601 &curr_idx, valid_num_sge); 602 if (ret) 603 return ret; 604 } 605 606 /* 607 * The pipeline can sequentially post all valid WQEs into WQ buffer, 608 * including new WQEs waiting for the doorbell to update the PI again. 609 * Therefore, the owner bit of WQE MUST be updated after all fields 610 * and extSGEs have been written into DDR instead of cache. 611 */ 612 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 613 dma_wmb(); 614 615 *sge_idx = curr_idx; 616 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit); 617 618 return ret; 619 } 620 621 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 622 struct hns_roce_qp *qp) 623 { 624 if (unlikely(qp->state == IB_QPS_ERR)) { 625 flush_cqe(hr_dev, qp); 626 } else { 627 struct hns_roce_v2_db sq_db = {}; 628 629 hr_reg_write(&sq_db, DB_TAG, qp->qpn); 630 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB); 631 hr_reg_write(&sq_db, DB_PI, qp->sq.head); 632 hr_reg_write(&sq_db, DB_SL, qp->sl); 633 634 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg); 635 } 636 } 637 638 static inline void update_rq_db(struct hns_roce_dev *hr_dev, 639 struct hns_roce_qp *qp) 640 { 641 if (unlikely(qp->state == IB_QPS_ERR)) { 642 flush_cqe(hr_dev, qp); 643 } else { 644 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) { 645 *qp->rdb.db_record = 646 qp->rq.head & V2_DB_PRODUCER_IDX_M; 647 } else { 648 struct hns_roce_v2_db rq_db = {}; 649 650 hr_reg_write(&rq_db, DB_TAG, qp->qpn); 651 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB); 652 hr_reg_write(&rq_db, DB_PI, qp->rq.head); 653 654 hns_roce_write64(hr_dev, (__le32 *)&rq_db, 655 qp->rq.db_reg); 656 } 657 } 658 } 659 660 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, 661 u64 __iomem *dest) 662 { 663 #define HNS_ROCE_WRITE_TIMES 8 664 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 665 struct hnae3_handle *handle = priv->handle; 666 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 667 int i; 668 669 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) 670 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) 671 writeq_relaxed(*(val + i), dest + i); 672 } 673 674 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 675 void *wqe) 676 { 677 #define HNS_ROCE_SL_SHIFT 2 678 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 679 680 if (unlikely(qp->state == IB_QPS_ERR)) { 681 flush_cqe(hr_dev, qp); 682 return; 683 } 684 /* All kinds of DirectWQE have the same header field layout */ 685 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG); 686 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl); 687 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H, 688 qp->sl >> HNS_ROCE_SL_SHIFT); 689 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head); 690 691 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg); 692 } 693 694 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 695 const struct ib_send_wr *wr, 696 const struct ib_send_wr **bad_wr) 697 { 698 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 699 struct ib_device *ibdev = &hr_dev->ib_dev; 700 struct hns_roce_qp *qp = to_hr_qp(ibqp); 701 unsigned long flags = 0; 702 unsigned int owner_bit; 703 unsigned int sge_idx; 704 unsigned int wqe_idx; 705 void *wqe = NULL; 706 u32 nreq; 707 int ret; 708 709 spin_lock_irqsave(&qp->sq.lock, flags); 710 711 ret = check_send_valid(hr_dev, qp); 712 if (unlikely(ret)) { 713 *bad_wr = wr; 714 nreq = 0; 715 goto out; 716 } 717 718 sge_idx = qp->next_sge; 719 720 for (nreq = 0; wr; ++nreq, wr = wr->next) { 721 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 722 ret = -ENOMEM; 723 *bad_wr = wr; 724 goto out; 725 } 726 727 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 728 729 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 730 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n", 731 wr->num_sge, qp->sq.max_gs); 732 ret = -EINVAL; 733 *bad_wr = wr; 734 goto out; 735 } 736 737 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 738 qp->sq.wrid[wqe_idx] = wr->wr_id; 739 owner_bit = 740 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 741 742 /* RC and UD share the same DirectWQE field layout */ 743 ((struct hns_roce_v2_rc_send_wqe *)wqe)->byte_4 = 0; 744 745 /* Corresponding to the QP type, wqe process separately */ 746 if (ibqp->qp_type == IB_QPT_RC) 747 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 748 else 749 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 750 751 trace_hns_sq_wqe(qp->qpn, wqe_idx, wqe, 1 << qp->sq.wqe_shift, 752 wr->wr_id, TRACE_SQ); 753 if (unlikely(ret)) { 754 *bad_wr = wr; 755 goto out; 756 } 757 } 758 759 out: 760 if (likely(nreq)) { 761 qp->sq.head += nreq; 762 qp->next_sge = sge_idx; 763 764 if (nreq == 1 && !ret && 765 (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) 766 write_dwqe(hr_dev, qp, wqe); 767 else 768 update_sq_db(hr_dev, qp); 769 } 770 771 spin_unlock_irqrestore(&qp->sq.lock, flags); 772 773 return ret; 774 } 775 776 static int check_recv_valid(struct hns_roce_dev *hr_dev, 777 struct hns_roce_qp *hr_qp) 778 { 779 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 780 return -EIO; 781 782 if (hr_qp->state == IB_QPS_RESET) 783 return -EINVAL; 784 785 return 0; 786 } 787 788 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe, 789 u32 max_sge, bool rsv) 790 { 791 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 792 u32 i, cnt; 793 794 for (i = 0, cnt = 0; i < wr->num_sge; i++) { 795 /* Skip zero-length sge */ 796 if (!wr->sg_list[i].length) 797 continue; 798 set_data_seg_v2(dseg + cnt, wr->sg_list + i); 799 cnt++; 800 } 801 802 /* Fill a reserved sge to make hw stop reading remaining segments */ 803 if (rsv) { 804 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 805 dseg[cnt].addr = 0; 806 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 807 } else { 808 /* Clear remaining segments to make ROCEE ignore sges */ 809 if (cnt < max_sge) 810 memset(dseg + cnt, 0, 811 (max_sge - cnt) * HNS_ROCE_SGE_SIZE); 812 } 813 } 814 815 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr, 816 u32 wqe_idx, u32 max_sge) 817 { 818 void *wqe = NULL; 819 820 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 821 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge); 822 823 trace_hns_rq_wqe(hr_qp->qpn, wqe_idx, wqe, 1 << hr_qp->rq.wqe_shift, 824 wr->wr_id, TRACE_RQ); 825 } 826 827 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 828 const struct ib_recv_wr *wr, 829 const struct ib_recv_wr **bad_wr) 830 { 831 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 832 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 833 struct ib_device *ibdev = &hr_dev->ib_dev; 834 u32 wqe_idx, nreq, max_sge; 835 unsigned long flags; 836 int ret; 837 838 spin_lock_irqsave(&hr_qp->rq.lock, flags); 839 840 ret = check_recv_valid(hr_dev, hr_qp); 841 if (unlikely(ret)) { 842 *bad_wr = wr; 843 nreq = 0; 844 goto out; 845 } 846 847 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 848 for (nreq = 0; wr; ++nreq, wr = wr->next) { 849 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 850 hr_qp->ibqp.recv_cq))) { 851 ret = -ENOMEM; 852 *bad_wr = wr; 853 goto out; 854 } 855 856 if (unlikely(wr->num_sge > max_sge)) { 857 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n", 858 wr->num_sge, max_sge); 859 ret = -EINVAL; 860 *bad_wr = wr; 861 goto out; 862 } 863 864 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 865 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge); 866 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 867 } 868 869 out: 870 if (likely(nreq)) { 871 hr_qp->rq.head += nreq; 872 873 update_rq_db(hr_dev, hr_qp); 874 } 875 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 876 877 return ret; 878 } 879 880 static int hns_roce_push_drain_wr(struct hns_roce_wq *wq, struct ib_cq *cq, 881 u64 wr_id) 882 { 883 unsigned long flags; 884 int ret = 0; 885 886 spin_lock_irqsave(&wq->lock, flags); 887 if (hns_roce_wq_overflow(wq, 1, cq)) { 888 ret = -ENOMEM; 889 goto out; 890 } 891 892 wq->wrid[wq->head & (wq->wqe_cnt - 1)] = wr_id; 893 wq->head++; 894 895 out: 896 spin_unlock_irqrestore(&wq->lock, flags); 897 return ret; 898 } 899 900 struct hns_roce_drain_cqe { 901 struct ib_cqe cqe; 902 struct completion done; 903 }; 904 905 static void hns_roce_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 906 { 907 struct hns_roce_drain_cqe *cqe = container_of(wc->wr_cqe, 908 struct hns_roce_drain_cqe, 909 cqe); 910 complete(&cqe->done); 911 } 912 913 static void handle_drain_completion(struct ib_cq *ibcq, 914 struct hns_roce_drain_cqe *drain, 915 struct hns_roce_dev *hr_dev) 916 { 917 #define TIMEOUT (HZ / 10) 918 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 919 unsigned long flags; 920 bool triggered; 921 922 if (ibcq->poll_ctx == IB_POLL_DIRECT) { 923 while (wait_for_completion_timeout(&drain->done, TIMEOUT) <= 0) 924 ib_process_cq_direct(ibcq, -1); 925 return; 926 } 927 928 if (hr_dev->state < HNS_ROCE_DEVICE_STATE_RST_DOWN) 929 goto waiting_done; 930 931 spin_lock_irqsave(&hr_cq->lock, flags); 932 triggered = hr_cq->is_armed; 933 hr_cq->is_armed = 1; 934 spin_unlock_irqrestore(&hr_cq->lock, flags); 935 936 /* Triggered means this cq is processing or has been processed 937 * by hns_roce_handle_device_err() or this function. We need to 938 * cancel the already invoked comp_handler() to avoid concurrency. 939 * If it has not been triggered, we can directly invoke 940 * comp_handler(). 941 */ 942 if (triggered) { 943 switch (ibcq->poll_ctx) { 944 case IB_POLL_SOFTIRQ: 945 irq_poll_disable(&ibcq->iop); 946 irq_poll_enable(&ibcq->iop); 947 break; 948 case IB_POLL_WORKQUEUE: 949 case IB_POLL_UNBOUND_WORKQUEUE: 950 cancel_work_sync(&ibcq->work); 951 break; 952 default: 953 WARN_ON_ONCE(1); 954 } 955 } 956 957 if (ibcq->comp_handler) 958 ibcq->comp_handler(ibcq, ibcq->cq_context); 959 960 waiting_done: 961 if (ibcq->comp_handler) 962 wait_for_completion(&drain->done); 963 } 964 965 static void hns_roce_v2_drain_rq(struct ib_qp *ibqp) 966 { 967 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 968 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 969 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 970 struct hns_roce_drain_cqe rdrain = {}; 971 const struct ib_recv_wr *bad_rwr; 972 struct ib_cq *cq = ibqp->recv_cq; 973 struct ib_recv_wr rwr = {}; 974 int ret; 975 976 ret = ib_modify_qp(ibqp, &attr, IB_QP_STATE); 977 if (ret && hr_dev->state < HNS_ROCE_DEVICE_STATE_RST_DOWN) { 978 ibdev_err_ratelimited(&hr_dev->ib_dev, 979 "failed to modify qp during drain rq, ret = %d.\n", 980 ret); 981 return; 982 } 983 984 rwr.wr_cqe = &rdrain.cqe; 985 rdrain.cqe.done = hns_roce_drain_qp_done; 986 init_completion(&rdrain.done); 987 988 if (hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN) 989 ret = hns_roce_push_drain_wr(&hr_qp->rq, cq, rwr.wr_id); 990 else 991 ret = hns_roce_v2_post_recv(ibqp, &rwr, &bad_rwr); 992 if (ret) { 993 ibdev_err_ratelimited(&hr_dev->ib_dev, 994 "failed to post recv for drain rq, ret = %d.\n", 995 ret); 996 return; 997 } 998 999 handle_drain_completion(cq, &rdrain, hr_dev); 1000 } 1001 1002 static void hns_roce_v2_drain_sq(struct ib_qp *ibqp) 1003 { 1004 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 1005 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 1006 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 1007 struct hns_roce_drain_cqe sdrain = {}; 1008 const struct ib_send_wr *bad_swr; 1009 struct ib_cq *cq = ibqp->send_cq; 1010 struct ib_rdma_wr swr = { 1011 .wr = { 1012 .next = NULL, 1013 { .wr_cqe = &sdrain.cqe, }, 1014 .opcode = IB_WR_RDMA_WRITE, 1015 }, 1016 }; 1017 int ret; 1018 1019 ret = ib_modify_qp(ibqp, &attr, IB_QP_STATE); 1020 if (ret && hr_dev->state < HNS_ROCE_DEVICE_STATE_RST_DOWN) { 1021 ibdev_err_ratelimited(&hr_dev->ib_dev, 1022 "failed to modify qp during drain sq, ret = %d.\n", 1023 ret); 1024 return; 1025 } 1026 1027 sdrain.cqe.done = hns_roce_drain_qp_done; 1028 init_completion(&sdrain.done); 1029 1030 if (hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN) 1031 ret = hns_roce_push_drain_wr(&hr_qp->sq, cq, swr.wr.wr_id); 1032 else 1033 ret = hns_roce_v2_post_send(ibqp, &swr.wr, &bad_swr); 1034 if (ret) { 1035 ibdev_err_ratelimited(&hr_dev->ib_dev, 1036 "failed to post send for drain sq, ret = %d.\n", 1037 ret); 1038 return; 1039 } 1040 1041 handle_drain_completion(cq, &sdrain, hr_dev); 1042 } 1043 1044 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n) 1045 { 1046 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 1047 } 1048 1049 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n) 1050 { 1051 return hns_roce_buf_offset(idx_que->mtr.kmem, 1052 n << idx_que->entry_shift); 1053 } 1054 1055 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index) 1056 { 1057 /* always called with interrupts disabled. */ 1058 spin_lock(&srq->lock); 1059 1060 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 1061 srq->idx_que.tail++; 1062 1063 spin_unlock(&srq->lock); 1064 } 1065 1066 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq) 1067 { 1068 struct hns_roce_idx_que *idx_que = &srq->idx_que; 1069 1070 return idx_que->head - idx_que->tail >= srq->wqe_cnt; 1071 } 1072 1073 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge, 1074 const struct ib_recv_wr *wr) 1075 { 1076 struct ib_device *ib_dev = srq->ibsrq.device; 1077 1078 if (unlikely(wr->num_sge > max_sge)) { 1079 ibdev_err(ib_dev, 1080 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n", 1081 wr->num_sge, max_sge); 1082 return -EINVAL; 1083 } 1084 1085 if (unlikely(hns_roce_srqwq_overflow(srq))) { 1086 ibdev_err(ib_dev, 1087 "failed to check srqwq status, srqwq is full.\n"); 1088 return -ENOMEM; 1089 } 1090 1091 return 0; 1092 } 1093 1094 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx) 1095 { 1096 struct hns_roce_idx_que *idx_que = &srq->idx_que; 1097 u32 pos; 1098 1099 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt); 1100 if (unlikely(pos == srq->wqe_cnt)) 1101 return -ENOSPC; 1102 1103 bitmap_set(idx_que->bitmap, pos, 1); 1104 *wqe_idx = pos; 1105 return 0; 1106 } 1107 1108 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx) 1109 { 1110 struct hns_roce_idx_que *idx_que = &srq->idx_que; 1111 unsigned int head; 1112 __le32 *buf; 1113 1114 head = idx_que->head & (srq->wqe_cnt - 1); 1115 1116 buf = get_idx_buf(idx_que, head); 1117 *buf = cpu_to_le32(wqe_idx); 1118 1119 idx_que->head++; 1120 } 1121 1122 static void update_srq_db(struct hns_roce_srq *srq) 1123 { 1124 struct hns_roce_dev *hr_dev = to_hr_dev(srq->ibsrq.device); 1125 struct hns_roce_v2_db db = {}; 1126 1127 hr_reg_write(&db, DB_TAG, srq->srqn); 1128 hr_reg_write(&db, DB_CMD, HNS_ROCE_V2_SRQ_DB); 1129 hr_reg_write(&db, DB_PI, srq->idx_que.head); 1130 1131 hns_roce_write64(hr_dev, (__le32 *)&db, srq->db_reg); 1132 } 1133 1134 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 1135 const struct ib_recv_wr *wr, 1136 const struct ib_recv_wr **bad_wr) 1137 { 1138 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 1139 unsigned long flags; 1140 int ret = 0; 1141 u32 max_sge; 1142 u32 wqe_idx; 1143 void *wqe; 1144 u32 nreq; 1145 1146 spin_lock_irqsave(&srq->lock, flags); 1147 1148 max_sge = srq->max_gs - srq->rsv_sge; 1149 for (nreq = 0; wr; ++nreq, wr = wr->next) { 1150 ret = check_post_srq_valid(srq, max_sge, wr); 1151 if (ret) { 1152 *bad_wr = wr; 1153 break; 1154 } 1155 1156 ret = get_srq_wqe_idx(srq, &wqe_idx); 1157 if (unlikely(ret)) { 1158 *bad_wr = wr; 1159 break; 1160 } 1161 1162 wqe = get_srq_wqe_buf(srq, wqe_idx); 1163 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge); 1164 fill_wqe_idx(srq, wqe_idx); 1165 srq->wrid[wqe_idx] = wr->wr_id; 1166 1167 trace_hns_srq_wqe(srq->srqn, wqe_idx, wqe, 1 << srq->wqe_shift, 1168 wr->wr_id, TRACE_SRQ); 1169 } 1170 1171 if (likely(nreq)) { 1172 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) 1173 *srq->rdb.db_record = srq->idx_que.head & 1174 V2_DB_PRODUCER_IDX_M; 1175 else 1176 update_srq_db(srq); 1177 } 1178 1179 spin_unlock_irqrestore(&srq->lock, flags); 1180 1181 return ret; 1182 } 1183 1184 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 1185 unsigned long instance_stage, 1186 unsigned long reset_stage) 1187 { 1188 /* When hardware reset has been completed once or more, we should stop 1189 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 1190 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 1191 * stage of soft reset process, we should exit with error, and then 1192 * HNAE3_INIT_CLIENT related process can rollback the operation like 1193 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 1194 * process will exit with error to notify NIC driver to reschedule soft 1195 * reset process once again. 1196 */ 1197 hr_dev->is_reset = true; 1198 hr_dev->dis_db = true; 1199 1200 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 1201 instance_stage == HNS_ROCE_STATE_INIT) 1202 return CMD_RST_PRC_EBUSY; 1203 1204 return CMD_RST_PRC_SUCCESS; 1205 } 1206 1207 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 1208 unsigned long instance_stage, 1209 unsigned long reset_stage) 1210 { 1211 #define HW_RESET_TIMEOUT_US 1000000 1212 #define HW_RESET_SLEEP_US 1000 1213 1214 struct hns_roce_v2_priv *priv = hr_dev->priv; 1215 struct hnae3_handle *handle = priv->handle; 1216 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1217 unsigned long val; 1218 int ret; 1219 1220 /* When hardware reset is detected, we should stop sending mailbox&cmq& 1221 * doorbell to hardware. If now in .init_instance() function, we should 1222 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 1223 * process, we should exit with error, and then HNAE3_INIT_CLIENT 1224 * related process can rollback the operation like notifing hardware to 1225 * free resources, HNAE3_INIT_CLIENT related process will exit with 1226 * error to notify NIC driver to reschedule soft reset process once 1227 * again. 1228 */ 1229 hr_dev->dis_db = true; 1230 1231 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val, 1232 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US, 1233 HW_RESET_TIMEOUT_US, false, handle); 1234 if (!ret) 1235 hr_dev->is_reset = true; 1236 1237 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 1238 instance_stage == HNS_ROCE_STATE_INIT) 1239 return CMD_RST_PRC_EBUSY; 1240 1241 return CMD_RST_PRC_SUCCESS; 1242 } 1243 1244 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 1245 { 1246 struct hns_roce_v2_priv *priv = hr_dev->priv; 1247 struct hnae3_handle *handle = priv->handle; 1248 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1249 1250 /* When software reset is detected at .init_instance() function, we 1251 * should stop sending mailbox&cmq&doorbell to hardware, and exit 1252 * with error. 1253 */ 1254 hr_dev->dis_db = true; 1255 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 1256 hr_dev->is_reset = true; 1257 1258 return CMD_RST_PRC_EBUSY; 1259 } 1260 1261 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev, 1262 struct hnae3_handle *handle) 1263 { 1264 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1265 unsigned long instance_stage; /* the current instance stage */ 1266 unsigned long reset_stage; /* the current reset stage */ 1267 unsigned long reset_cnt; 1268 bool sw_resetting; 1269 bool hw_resetting; 1270 1271 /* Get information about reset from NIC driver or RoCE driver itself, 1272 * the meaning of the following variables from NIC driver are described 1273 * as below: 1274 * reset_cnt -- The count value of completed hardware reset. 1275 * hw_resetting -- Whether hardware device is resetting now. 1276 * sw_resetting -- Whether NIC's software reset process is running now. 1277 */ 1278 instance_stage = handle->rinfo.instance_state; 1279 reset_stage = handle->rinfo.reset_state; 1280 reset_cnt = ops->ae_dev_reset_cnt(handle); 1281 if (reset_cnt != hr_dev->reset_cnt) 1282 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 1283 reset_stage); 1284 1285 hw_resetting = ops->get_cmdq_stat(handle); 1286 if (hw_resetting) 1287 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 1288 reset_stage); 1289 1290 sw_resetting = ops->ae_dev_resetting(handle); 1291 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 1292 return hns_roce_v2_cmd_sw_resetting(hr_dev); 1293 1294 return CMD_RST_PRC_OTHERS; 1295 } 1296 1297 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev) 1298 { 1299 struct hns_roce_v2_priv *priv = hr_dev->priv; 1300 struct hnae3_handle *handle = priv->handle; 1301 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1302 1303 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle)) 1304 return true; 1305 1306 if (ops->get_hw_reset_stat(handle)) 1307 return true; 1308 1309 if (ops->ae_dev_resetting(handle)) 1310 return true; 1311 1312 return false; 1313 } 1314 1315 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy) 1316 { 1317 struct hns_roce_v2_priv *priv = hr_dev->priv; 1318 u32 status; 1319 1320 if (hr_dev->is_reset) 1321 status = CMD_RST_PRC_SUCCESS; 1322 else 1323 status = check_aedev_reset_status(hr_dev, priv->handle); 1324 1325 *busy = (status == CMD_RST_PRC_EBUSY); 1326 1327 return status == CMD_RST_PRC_OTHERS; 1328 } 1329 1330 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 1331 struct hns_roce_v2_cmq_ring *ring) 1332 { 1333 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 1334 1335 ring->desc = dma_alloc_coherent(hr_dev->dev, size, 1336 &ring->desc_dma_addr, GFP_KERNEL); 1337 if (!ring->desc) 1338 return -ENOMEM; 1339 1340 return 0; 1341 } 1342 1343 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 1344 struct hns_roce_v2_cmq_ring *ring) 1345 { 1346 dma_free_coherent(hr_dev->dev, 1347 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 1348 ring->desc, ring->desc_dma_addr); 1349 1350 ring->desc_dma_addr = 0; 1351 } 1352 1353 static int init_csq(struct hns_roce_dev *hr_dev, 1354 struct hns_roce_v2_cmq_ring *csq) 1355 { 1356 dma_addr_t dma; 1357 int ret; 1358 1359 csq->desc_num = CMD_CSQ_DESC_NUM; 1360 spin_lock_init(&csq->lock); 1361 csq->flag = TYPE_CSQ; 1362 csq->head = 0; 1363 1364 ret = hns_roce_alloc_cmq_desc(hr_dev, csq); 1365 if (ret) 1366 return ret; 1367 1368 dma = csq->desc_dma_addr; 1369 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma)); 1370 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma)); 1371 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 1372 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1373 1374 /* Make sure to write CI first and then PI */ 1375 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0); 1376 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0); 1377 1378 return 0; 1379 } 1380 1381 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1382 { 1383 struct hns_roce_v2_priv *priv = hr_dev->priv; 1384 int ret; 1385 1386 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1387 1388 ret = init_csq(hr_dev, &priv->cmq.csq); 1389 if (ret) 1390 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret); 1391 1392 return ret; 1393 } 1394 1395 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1396 { 1397 struct hns_roce_v2_priv *priv = hr_dev->priv; 1398 1399 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1400 } 1401 1402 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1403 enum hns_roce_opcode_type opcode, 1404 bool is_read) 1405 { 1406 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1407 desc->opcode = cpu_to_le16(opcode); 1408 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1409 if (is_read) 1410 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1411 else 1412 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1413 } 1414 1415 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1416 { 1417 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1418 struct hns_roce_v2_priv *priv = hr_dev->priv; 1419 1420 return tail == priv->cmq.csq.head; 1421 } 1422 1423 static void update_cmdq_status(struct hns_roce_dev *hr_dev) 1424 { 1425 struct hns_roce_v2_priv *priv = hr_dev->priv; 1426 struct hnae3_handle *handle = priv->handle; 1427 1428 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 1429 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) 1430 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR; 1431 } 1432 1433 static int hns_roce_cmd_err_convert_errno(u16 desc_ret) 1434 { 1435 struct hns_roce_cmd_errcode errcode_table[] = { 1436 {CMD_EXEC_SUCCESS, 0}, 1437 {CMD_NO_AUTH, -EPERM}, 1438 {CMD_NOT_EXIST, -EOPNOTSUPP}, 1439 {CMD_CRQ_FULL, -EXFULL}, 1440 {CMD_NEXT_ERR, -ENOSR}, 1441 {CMD_NOT_EXEC, -ENOTBLK}, 1442 {CMD_PARA_ERR, -EINVAL}, 1443 {CMD_RESULT_ERR, -ERANGE}, 1444 {CMD_TIMEOUT, -ETIME}, 1445 {CMD_HILINK_ERR, -ENOLINK}, 1446 {CMD_INFO_ILLEGAL, -ENXIO}, 1447 {CMD_INVALID, -EBADR}, 1448 }; 1449 u16 i; 1450 1451 for (i = 0; i < ARRAY_SIZE(errcode_table); i++) 1452 if (desc_ret == errcode_table[i].return_status) 1453 return errcode_table[i].errno; 1454 return -EIO; 1455 } 1456 1457 static u32 hns_roce_cmdq_tx_timeout(u16 opcode, u32 tx_timeout) 1458 { 1459 static const struct hns_roce_cmdq_tx_timeout_map cmdq_tx_timeout[] = { 1460 {HNS_ROCE_OPC_POST_MB, HNS_ROCE_OPC_POST_MB_TIMEOUT}, 1461 }; 1462 int i; 1463 1464 for (i = 0; i < ARRAY_SIZE(cmdq_tx_timeout); i++) 1465 if (cmdq_tx_timeout[i].opcode == opcode) 1466 return cmdq_tx_timeout[i].tx_timeout; 1467 1468 return tx_timeout; 1469 } 1470 1471 static void hns_roce_wait_csq_done(struct hns_roce_dev *hr_dev, u32 tx_timeout) 1472 { 1473 u32 timeout = 0; 1474 1475 do { 1476 if (hns_roce_cmq_csq_done(hr_dev)) 1477 break; 1478 udelay(1); 1479 } while (++timeout < tx_timeout); 1480 } 1481 1482 static int __hns_roce_cmq_send_one(struct hns_roce_dev *hr_dev, 1483 struct hns_roce_cmq_desc *desc, 1484 int num, u32 tx_timeout) 1485 { 1486 struct hns_roce_v2_priv *priv = hr_dev->priv; 1487 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1488 u16 desc_ret; 1489 u32 tail; 1490 int ret; 1491 int i; 1492 1493 tail = csq->head; 1494 1495 for (i = 0; i < num; i++) { 1496 trace_hns_cmdq_req(hr_dev, &desc[i]); 1497 1498 csq->desc[csq->head++] = desc[i]; 1499 if (csq->head == csq->desc_num) 1500 csq->head = 0; 1501 } 1502 1503 /* Write to hardware */ 1504 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head); 1505 1506 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_CNT]); 1507 1508 hns_roce_wait_csq_done(hr_dev, tx_timeout); 1509 if (hns_roce_cmq_csq_done(hr_dev)) { 1510 ret = 0; 1511 for (i = 0; i < num; i++) { 1512 trace_hns_cmdq_resp(hr_dev, &csq->desc[tail]); 1513 1514 /* check the result of hardware write back */ 1515 desc_ret = le16_to_cpu(csq->desc[tail++].retval); 1516 if (tail == csq->desc_num) 1517 tail = 0; 1518 if (likely(desc_ret == CMD_EXEC_SUCCESS)) 1519 continue; 1520 1521 ret = hns_roce_cmd_err_convert_errno(desc_ret); 1522 } 1523 } else { 1524 /* FW/HW reset or incorrect number of desc */ 1525 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1526 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n", 1527 csq->head, tail); 1528 csq->head = tail; 1529 1530 update_cmdq_status(hr_dev); 1531 1532 ret = -EAGAIN; 1533 } 1534 1535 if (ret) 1536 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_ERR_CNT]); 1537 1538 return ret; 1539 } 1540 1541 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1542 struct hns_roce_cmq_desc *desc, int num) 1543 { 1544 struct hns_roce_v2_priv *priv = hr_dev->priv; 1545 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1546 u16 opcode = le16_to_cpu(desc->opcode); 1547 u32 tx_timeout = hns_roce_cmdq_tx_timeout(opcode, priv->cmq.tx_timeout); 1548 u8 try_cnt = HNS_ROCE_OPC_POST_MB_TRY_CNT; 1549 u32 rsv_tail; 1550 int ret; 1551 int i; 1552 1553 while (try_cnt) { 1554 try_cnt--; 1555 1556 spin_lock_bh(&csq->lock); 1557 rsv_tail = csq->head; 1558 ret = __hns_roce_cmq_send_one(hr_dev, desc, num, tx_timeout); 1559 if (opcode == HNS_ROCE_OPC_POST_MB && ret == -ETIME && 1560 try_cnt) { 1561 spin_unlock_bh(&csq->lock); 1562 mdelay(HNS_ROCE_OPC_POST_MB_RETRY_GAP_MSEC); 1563 continue; 1564 } 1565 1566 for (i = 0; i < num; i++) { 1567 desc[i] = csq->desc[rsv_tail++]; 1568 if (rsv_tail == csq->desc_num) 1569 rsv_tail = 0; 1570 } 1571 spin_unlock_bh(&csq->lock); 1572 break; 1573 } 1574 1575 if (ret) 1576 dev_err_ratelimited(hr_dev->dev, 1577 "Cmdq IO error, opcode = 0x%x, return = %d.\n", 1578 opcode, ret); 1579 1580 return ret; 1581 } 1582 1583 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1584 struct hns_roce_cmq_desc *desc, int num) 1585 { 1586 bool busy; 1587 int ret; 1588 1589 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1590 return -EIO; 1591 1592 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1593 return busy ? -EBUSY : 0; 1594 1595 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1596 if (ret) { 1597 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1598 return busy ? -EBUSY : 0; 1599 } 1600 1601 return ret; 1602 } 1603 1604 static enum hns_roce_opcode_type 1605 get_bond_opcode(enum hns_roce_bond_cmd_type bond_type) 1606 { 1607 switch (bond_type) { 1608 case HNS_ROCE_SET_BOND: 1609 return HNS_ROCE_OPC_SET_BOND_INFO; 1610 case HNS_ROCE_CHANGE_BOND: 1611 return HNS_ROCE_OPC_CHANGE_ACTIVE_PORT; 1612 case HNS_ROCE_CLEAR_BOND: 1613 return HNS_ROCE_OPC_CLEAR_BOND_INFO; 1614 default: 1615 WARN(true, "Invalid bond type %d!\n", bond_type); 1616 return HNS_ROCE_OPC_SET_BOND_INFO; 1617 } 1618 } 1619 1620 static enum hns_roce_bond_hashtype 1621 get_bond_hashtype(enum netdev_lag_hash netdev_hashtype) 1622 { 1623 switch (netdev_hashtype) { 1624 case NETDEV_LAG_HASH_L2: 1625 return BOND_HASH_L2; 1626 case NETDEV_LAG_HASH_L34: 1627 return BOND_HASH_L34; 1628 case NETDEV_LAG_HASH_L23: 1629 return BOND_HASH_L23; 1630 default: 1631 WARN(true, "Invalid hash type %d!\n", netdev_hashtype); 1632 return BOND_HASH_L2; 1633 } 1634 } 1635 1636 int hns_roce_cmd_bond(struct hns_roce_bond_group *bond_grp, 1637 enum hns_roce_bond_cmd_type bond_type) 1638 { 1639 enum hns_roce_opcode_type opcode = get_bond_opcode(bond_type); 1640 struct hns_roce_bond_info *slave_info; 1641 struct hns_roce_cmq_desc desc = {}; 1642 int ret; 1643 1644 slave_info = (struct hns_roce_bond_info *)desc.data; 1645 hns_roce_cmq_setup_basic_desc(&desc, opcode, false); 1646 1647 slave_info->bond_id = cpu_to_le32(bond_grp->bond_id); 1648 if (bond_type == HNS_ROCE_CLEAR_BOND) 1649 goto out; 1650 1651 if (bond_grp->tx_type == NETDEV_LAG_TX_TYPE_ACTIVEBACKUP) { 1652 slave_info->bond_mode = cpu_to_le32(BOND_MODE_1); 1653 if (bond_grp->active_slave_num != 1) 1654 ibdev_warn(&bond_grp->main_hr_dev->ib_dev, 1655 "active slave cnt(%u) in Mode 1 is invalid.\n", 1656 bond_grp->active_slave_num); 1657 } else { 1658 slave_info->bond_mode = cpu_to_le32(BOND_MODE_2_4); 1659 slave_info->hash_policy = 1660 cpu_to_le32(get_bond_hashtype(bond_grp->hash_type)); 1661 } 1662 1663 slave_info->active_slave_cnt = cpu_to_le32(bond_grp->active_slave_num); 1664 slave_info->active_slave_mask = cpu_to_le32(bond_grp->active_slave_map); 1665 slave_info->slave_mask = cpu_to_le32(bond_grp->slave_map); 1666 1667 out: 1668 ret = hns_roce_cmq_send(bond_grp->main_hr_dev, &desc, 1); 1669 if (ret) 1670 ibdev_err(&bond_grp->main_hr_dev->ib_dev, 1671 "cmq bond type(%d) failed, ret = %d.\n", 1672 bond_type, ret); 1673 1674 return ret; 1675 } 1676 1677 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, 1678 dma_addr_t base_addr, u8 cmd, unsigned long tag) 1679 { 1680 struct hns_roce_cmd_mailbox *mbox; 1681 int ret; 1682 1683 mbox = hns_roce_alloc_cmd_mailbox(hr_dev); 1684 if (IS_ERR(mbox)) 1685 return PTR_ERR(mbox); 1686 1687 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag); 1688 hns_roce_free_cmd_mailbox(hr_dev, mbox); 1689 return ret; 1690 } 1691 1692 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1693 { 1694 struct hns_roce_query_version *resp; 1695 struct hns_roce_cmq_desc desc; 1696 int ret; 1697 1698 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1699 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1700 if (ret) 1701 return ret; 1702 1703 resp = (struct hns_roce_query_version *)desc.data; 1704 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1705 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1706 1707 return 0; 1708 } 1709 1710 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev, 1711 struct hnae3_handle *handle) 1712 { 1713 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1714 unsigned long end; 1715 1716 hr_dev->dis_db = true; 1717 1718 dev_warn(hr_dev->dev, 1719 "func clear is pending, device in resetting state.\n"); 1720 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1721 while (end) { 1722 if (!ops->get_hw_reset_stat(handle)) { 1723 hr_dev->is_reset = true; 1724 dev_info(hr_dev->dev, 1725 "func clear success after reset.\n"); 1726 return; 1727 } 1728 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1729 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1730 } 1731 1732 dev_warn(hr_dev->dev, "func clear failed.\n"); 1733 } 1734 1735 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev, 1736 struct hnae3_handle *handle) 1737 { 1738 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1739 unsigned long end; 1740 1741 hr_dev->dis_db = true; 1742 1743 dev_warn(hr_dev->dev, 1744 "func clear is pending, device in resetting state.\n"); 1745 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1746 while (end) { 1747 if (ops->ae_dev_reset_cnt(handle) != 1748 hr_dev->reset_cnt) { 1749 hr_dev->is_reset = true; 1750 dev_info(hr_dev->dev, 1751 "func clear success after sw reset\n"); 1752 return; 1753 } 1754 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1755 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1756 } 1757 1758 dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n"); 1759 } 1760 1761 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval, 1762 int flag) 1763 { 1764 struct hns_roce_v2_priv *priv = hr_dev->priv; 1765 struct hnae3_handle *handle = priv->handle; 1766 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1767 1768 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) { 1769 hr_dev->dis_db = true; 1770 hr_dev->is_reset = true; 1771 dev_info(hr_dev->dev, "func clear success after reset.\n"); 1772 return; 1773 } 1774 1775 if (ops->get_hw_reset_stat(handle)) { 1776 func_clr_hw_resetting_state(hr_dev, handle); 1777 return; 1778 } 1779 1780 if (ops->ae_dev_resetting(handle) && 1781 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) { 1782 func_clr_sw_resetting_state(hr_dev, handle); 1783 return; 1784 } 1785 1786 if (retval && !flag) 1787 dev_warn(hr_dev->dev, 1788 "func clear read failed, ret = %d.\n", retval); 1789 1790 dev_warn(hr_dev->dev, "func clear failed.\n"); 1791 } 1792 1793 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id) 1794 { 1795 bool fclr_write_fail_flag = false; 1796 struct hns_roce_func_clear *resp; 1797 struct hns_roce_cmq_desc desc; 1798 unsigned long end; 1799 int ret = 0; 1800 1801 if (check_device_is_in_reset(hr_dev)) 1802 goto out; 1803 1804 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1805 resp = (struct hns_roce_func_clear *)desc.data; 1806 resp->rst_funcid_en = cpu_to_le32(vf_id); 1807 1808 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1809 if (ret) { 1810 fclr_write_fail_flag = true; 1811 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n", 1812 ret); 1813 goto out; 1814 } 1815 1816 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1817 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1818 while (end) { 1819 if (check_device_is_in_reset(hr_dev)) 1820 goto out; 1821 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1822 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1823 1824 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1825 true); 1826 1827 resp->rst_funcid_en = cpu_to_le32(vf_id); 1828 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1829 if (ret) 1830 continue; 1831 1832 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) { 1833 if (vf_id == 0) 1834 hr_dev->is_reset = true; 1835 return; 1836 } 1837 } 1838 1839 out: 1840 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag); 1841 } 1842 1843 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id) 1844 { 1845 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1846 struct hns_roce_cmq_desc desc[2]; 1847 struct hns_roce_cmq_req *req_a; 1848 1849 req_a = (struct hns_roce_cmq_req *)desc[0].data; 1850 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1851 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1852 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1853 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id); 1854 1855 return hns_roce_cmq_send(hr_dev, desc, 2); 1856 } 1857 1858 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1859 { 1860 int ret; 1861 int i; 1862 1863 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1864 return; 1865 1866 for (i = hr_dev->func_num - 1; i >= 0; i--) { 1867 __hns_roce_function_clear(hr_dev, i); 1868 1869 if (i == 0) 1870 continue; 1871 1872 ret = hns_roce_free_vf_resource(hr_dev, i); 1873 if (ret) 1874 ibdev_err(&hr_dev->ib_dev, 1875 "failed to free vf resource, vf_id = %d, ret = %d.\n", 1876 i, ret); 1877 } 1878 } 1879 1880 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev) 1881 { 1882 struct hns_roce_cmq_desc desc; 1883 int ret; 1884 1885 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO, 1886 false); 1887 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1888 if (ret) 1889 ibdev_err(&hr_dev->ib_dev, 1890 "failed to clear extended doorbell info, ret = %d.\n", 1891 ret); 1892 1893 return ret; 1894 } 1895 1896 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1897 { 1898 struct hns_roce_query_fw_info *resp; 1899 struct hns_roce_cmq_desc desc; 1900 int ret; 1901 1902 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1903 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1904 if (ret) 1905 return ret; 1906 1907 resp = (struct hns_roce_query_fw_info *)desc.data; 1908 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1909 1910 return 0; 1911 } 1912 1913 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev) 1914 { 1915 struct hns_roce_cmq_desc desc; 1916 int ret; 1917 1918 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 1919 hr_dev->func_num = 1; 1920 return 0; 1921 } 1922 1923 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO, 1924 true); 1925 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1926 if (ret) { 1927 hr_dev->func_num = 1; 1928 return ret; 1929 } 1930 1931 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num); 1932 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id); 1933 1934 return 0; 1935 } 1936 1937 static int hns_roce_hw_v2_query_counter(struct hns_roce_dev *hr_dev, 1938 u64 *stats, u32 port, int *num_counters) 1939 { 1940 #define CNT_PER_DESC 3 1941 struct hns_roce_cmq_desc *desc; 1942 int bd_idx, cnt_idx; 1943 __le64 *cnt_data; 1944 int desc_num; 1945 int ret; 1946 int i; 1947 1948 if (port > hr_dev->caps.num_ports) 1949 return -EINVAL; 1950 1951 desc_num = DIV_ROUND_UP(HNS_ROCE_HW_CNT_TOTAL, CNT_PER_DESC); 1952 desc = kzalloc_objs(*desc, desc_num); 1953 if (!desc) 1954 return -ENOMEM; 1955 1956 for (i = 0; i < desc_num; i++) { 1957 hns_roce_cmq_setup_basic_desc(&desc[i], 1958 HNS_ROCE_OPC_QUERY_COUNTER, true); 1959 if (i != desc_num - 1) 1960 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1961 } 1962 1963 ret = hns_roce_cmq_send(hr_dev, desc, desc_num); 1964 if (ret) { 1965 ibdev_err(&hr_dev->ib_dev, 1966 "failed to get counter, ret = %d.\n", ret); 1967 goto err_out; 1968 } 1969 1970 for (i = 0; i < HNS_ROCE_HW_CNT_TOTAL && i < *num_counters; i++) { 1971 bd_idx = i / CNT_PER_DESC; 1972 if (bd_idx != HNS_ROCE_HW_CNT_TOTAL / CNT_PER_DESC && 1973 !(desc[bd_idx].flag & cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT))) 1974 break; 1975 1976 cnt_data = (__le64 *)&desc[bd_idx].data[0]; 1977 cnt_idx = i % CNT_PER_DESC; 1978 stats[i] = le64_to_cpu(cnt_data[cnt_idx]); 1979 } 1980 *num_counters = i; 1981 1982 err_out: 1983 kfree(desc); 1984 return ret; 1985 } 1986 1987 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1988 { 1989 struct hns_roce_cmq_desc desc; 1990 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1991 u32 clock_cycles_of_1us; 1992 1993 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1994 false); 1995 1996 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 1997 clock_cycles_of_1us = HNS_ROCE_1NS_CFG; 1998 else 1999 clock_cycles_of_1us = HNS_ROCE_1US_CFG; 2000 2001 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us); 2002 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT); 2003 2004 return hns_roce_cmq_send(hr_dev, &desc, 1); 2005 } 2006 2007 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf) 2008 { 2009 struct hns_roce_cmq_desc desc[2]; 2010 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2011 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2012 struct hns_roce_caps *caps = &hr_dev->caps; 2013 enum hns_roce_opcode_type opcode; 2014 u32 func_num; 2015 int ret; 2016 2017 if (is_vf) { 2018 opcode = HNS_ROCE_OPC_QUERY_VF_RES; 2019 func_num = 1; 2020 } else { 2021 opcode = HNS_ROCE_OPC_QUERY_PF_RES; 2022 func_num = hr_dev->func_num; 2023 } 2024 2025 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true); 2026 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2027 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true); 2028 2029 ret = hns_roce_cmq_send(hr_dev, desc, 2); 2030 if (ret) 2031 return ret; 2032 2033 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num; 2034 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num; 2035 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num; 2036 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num; 2037 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num; 2038 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num; 2039 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num; 2040 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num; 2041 2042 if (is_vf) { 2043 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num; 2044 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) / 2045 func_num; 2046 } else { 2047 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num; 2048 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) / 2049 func_num; 2050 } 2051 2052 return 0; 2053 } 2054 2055 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev) 2056 { 2057 struct hns_roce_cmq_desc desc; 2058 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2059 struct hns_roce_caps *caps = &hr_dev->caps; 2060 int ret; 2061 2062 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 2063 true); 2064 2065 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 2066 if (ret) 2067 return ret; 2068 2069 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM); 2070 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM); 2071 2072 return 0; 2073 } 2074 2075 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 2076 { 2077 struct device *dev = hr_dev->dev; 2078 int ret; 2079 2080 ret = load_func_res_caps(hr_dev, false); 2081 if (ret) { 2082 dev_err(dev, "failed to load pf res caps, ret = %d.\n", ret); 2083 return ret; 2084 } 2085 2086 ret = load_pf_timer_res_caps(hr_dev); 2087 if (ret) 2088 dev_err(dev, "failed to load pf timer resource, ret = %d.\n", 2089 ret); 2090 2091 return ret; 2092 } 2093 2094 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev) 2095 { 2096 struct device *dev = hr_dev->dev; 2097 int ret; 2098 2099 ret = load_func_res_caps(hr_dev, true); 2100 if (ret) 2101 dev_err(dev, "failed to load vf res caps, ret = %d.\n", ret); 2102 2103 return ret; 2104 } 2105 2106 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, 2107 u32 vf_id) 2108 { 2109 struct hns_roce_vf_switch *swt; 2110 struct hns_roce_cmq_desc desc; 2111 int ret; 2112 2113 swt = (struct hns_roce_vf_switch *)desc.data; 2114 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 2115 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 2116 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id); 2117 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 2118 if (ret) 2119 return ret; 2120 2121 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 2122 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 2123 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK); 2124 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK); 2125 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD); 2126 2127 return hns_roce_cmq_send(hr_dev, &desc, 1); 2128 } 2129 2130 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev) 2131 { 2132 u32 vf_id; 2133 int ret; 2134 2135 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) { 2136 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id); 2137 if (ret) 2138 return ret; 2139 } 2140 return 0; 2141 } 2142 2143 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id) 2144 { 2145 struct hns_roce_cmq_desc desc[2]; 2146 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2147 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2148 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 2149 struct hns_roce_caps *caps = &hr_dev->caps; 2150 2151 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 2152 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2153 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 2154 2155 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id); 2156 2157 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num); 2158 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num); 2159 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num); 2160 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num); 2161 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num); 2162 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num); 2163 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num); 2164 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num); 2165 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num); 2166 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num); 2167 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num); 2168 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num); 2169 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num); 2170 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num); 2171 2172 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2173 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num); 2174 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX, 2175 vf_id * caps->gmv_bt_num); 2176 } else { 2177 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num); 2178 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX, 2179 vf_id * caps->sgid_bt_num); 2180 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num); 2181 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX, 2182 vf_id * caps->smac_bt_num); 2183 } 2184 2185 return hns_roce_cmq_send(hr_dev, desc, 2); 2186 } 2187 2188 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 2189 { 2190 u32 func_num = max_t(u32, 1, hr_dev->func_num); 2191 u32 vf_id; 2192 int ret; 2193 2194 for (vf_id = 0; vf_id < func_num; vf_id++) { 2195 ret = config_vf_hem_resource(hr_dev, vf_id); 2196 if (ret) { 2197 dev_err(hr_dev->dev, 2198 "failed to config vf-%u hem res, ret = %d.\n", 2199 vf_id, ret); 2200 return ret; 2201 } 2202 } 2203 2204 return 0; 2205 } 2206 2207 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 2208 { 2209 struct hns_roce_cmq_desc desc; 2210 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2211 struct hns_roce_caps *caps = &hr_dev->caps; 2212 2213 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 2214 2215 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ, 2216 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET); 2217 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ, 2218 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET); 2219 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM, 2220 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps)); 2221 2222 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ, 2223 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET); 2224 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ, 2225 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET); 2226 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM, 2227 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs)); 2228 2229 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ, 2230 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET); 2231 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ, 2232 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET); 2233 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM, 2234 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs)); 2235 2236 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ, 2237 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET); 2238 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ, 2239 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET); 2240 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM, 2241 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts)); 2242 2243 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ, 2244 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET); 2245 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ, 2246 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET); 2247 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM, 2248 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps)); 2249 2250 return hns_roce_cmq_send(hr_dev, &desc, 1); 2251 } 2252 2253 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num, 2254 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type) 2255 { 2256 u64 obj_per_chunk; 2257 u64 bt_chunk_size = PAGE_SIZE; 2258 u64 buf_chunk_size = PAGE_SIZE; 2259 u64 obj_per_chunk_default = buf_chunk_size / obj_size; 2260 2261 *buf_page_size = 0; 2262 *bt_page_size = 0; 2263 2264 switch (hop_num) { 2265 case 3: 2266 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2267 (bt_chunk_size / BA_BYTE_LEN) * 2268 (bt_chunk_size / BA_BYTE_LEN) * 2269 obj_per_chunk_default; 2270 break; 2271 case 2: 2272 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2273 (bt_chunk_size / BA_BYTE_LEN) * 2274 obj_per_chunk_default; 2275 break; 2276 case 1: 2277 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2278 obj_per_chunk_default; 2279 break; 2280 case HNS_ROCE_HOP_NUM_0: 2281 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 2282 break; 2283 default: 2284 pr_err("table %u not support hop_num = %u!\n", hem_type, 2285 hop_num); 2286 return; 2287 } 2288 2289 if (hem_type >= HEM_TYPE_MTT) 2290 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2291 else 2292 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2293 } 2294 2295 static void set_hem_page_size(struct hns_roce_dev *hr_dev) 2296 { 2297 struct hns_roce_caps *caps = &hr_dev->caps; 2298 2299 /* EQ */ 2300 caps->eqe_ba_pg_sz = 0; 2301 caps->eqe_buf_pg_sz = 0; 2302 2303 /* Link Table */ 2304 caps->llm_buf_pg_sz = 0; 2305 2306 /* MR */ 2307 caps->mpt_ba_pg_sz = 0; 2308 caps->mpt_buf_pg_sz = 0; 2309 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 2310 caps->pbl_buf_pg_sz = 0; 2311 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 2312 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 2313 HEM_TYPE_MTPT); 2314 2315 /* QP */ 2316 caps->qpc_ba_pg_sz = 0; 2317 caps->qpc_buf_pg_sz = 0; 2318 caps->qpc_timer_ba_pg_sz = 0; 2319 caps->qpc_timer_buf_pg_sz = 0; 2320 caps->sccc_ba_pg_sz = 0; 2321 caps->sccc_buf_pg_sz = 0; 2322 caps->mtt_ba_pg_sz = 0; 2323 caps->mtt_buf_pg_sz = 0; 2324 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num, 2325 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 2326 HEM_TYPE_QPC); 2327 2328 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 2329 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num, 2330 caps->sccc_bt_num, &caps->sccc_buf_pg_sz, 2331 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC); 2332 2333 /* CQ */ 2334 caps->cqc_ba_pg_sz = 0; 2335 caps->cqc_buf_pg_sz = 0; 2336 caps->cqc_timer_ba_pg_sz = 0; 2337 caps->cqc_timer_buf_pg_sz = 0; 2338 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 2339 caps->cqe_buf_pg_sz = 0; 2340 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 2341 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 2342 HEM_TYPE_CQC); 2343 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num, 2344 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2345 2346 /* SRQ */ 2347 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) { 2348 caps->srqc_ba_pg_sz = 0; 2349 caps->srqc_buf_pg_sz = 0; 2350 caps->srqwqe_ba_pg_sz = 0; 2351 caps->srqwqe_buf_pg_sz = 0; 2352 caps->idx_ba_pg_sz = 0; 2353 caps->idx_buf_pg_sz = 0; 2354 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, 2355 caps->srqc_hop_num, caps->srqc_bt_num, 2356 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz, 2357 HEM_TYPE_SRQC); 2358 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2359 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2360 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2361 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, 2362 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz, 2363 &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2364 } 2365 2366 /* GMV */ 2367 caps->gmv_ba_pg_sz = 0; 2368 caps->gmv_buf_pg_sz = 0; 2369 } 2370 2371 /* Apply all loaded caps before setting to hardware */ 2372 static void apply_func_caps(struct hns_roce_dev *hr_dev) 2373 { 2374 #define MAX_GID_TBL_LEN 256 2375 struct hns_roce_caps *caps = &hr_dev->caps; 2376 struct hns_roce_v2_priv *priv = hr_dev->priv; 2377 2378 /* The following configurations don't need to be got from firmware. */ 2379 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 2380 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 2381 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 2382 2383 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2384 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2385 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2386 2387 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 2388 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 2389 2390 if (!caps->num_comp_vectors) 2391 caps->num_comp_vectors = 2392 min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM, 2393 (u32)priv->handle->rinfo.num_vectors - 2394 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM)); 2395 2396 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2397 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM; 2398 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE; 2399 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE; 2400 2401 /* The following configurations will be overwritten */ 2402 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ; 2403 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE; 2404 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ; 2405 2406 /* The following configurations are not got from firmware */ 2407 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ; 2408 2409 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0; 2410 2411 /* It's meaningless to support excessively large gid_table_len, 2412 * as the type of sgid_index in kernel struct ib_global_route 2413 * and userspace struct ibv_global_route are u8/uint8_t (0-255). 2414 */ 2415 caps->gid_table_len[0] = min_t(u32, MAX_GID_TBL_LEN, 2416 caps->gmv_bt_num * 2417 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz)); 2418 2419 caps->gmv_entry_num = caps->gmv_bt_num * (HNS_HW_PAGE_SIZE / 2420 caps->gmv_entry_sz); 2421 } else { 2422 u32 func_num = max_t(u32, 1, hr_dev->func_num); 2423 2424 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM; 2425 caps->ceqe_size = HNS_ROCE_CEQE_SIZE; 2426 caps->aeqe_size = HNS_ROCE_AEQE_SIZE; 2427 caps->gid_table_len[0] /= func_num; 2428 } 2429 2430 if (hr_dev->is_vf) { 2431 caps->default_aeq_arm_st = 0x3; 2432 caps->default_ceq_arm_st = 0x3; 2433 caps->default_ceq_max_cnt = 0x1; 2434 caps->default_ceq_period = 0x10; 2435 caps->default_aeq_max_cnt = 0x1; 2436 caps->default_aeq_period = 0x10; 2437 } 2438 2439 set_hem_page_size(hr_dev); 2440 } 2441 2442 static int hns_roce_query_caps(struct hns_roce_dev *hr_dev) 2443 { 2444 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM] = {}; 2445 struct hns_roce_caps *caps = &hr_dev->caps; 2446 struct hns_roce_query_pf_caps_a *resp_a; 2447 struct hns_roce_query_pf_caps_b *resp_b; 2448 struct hns_roce_query_pf_caps_c *resp_c; 2449 struct hns_roce_query_pf_caps_d *resp_d; 2450 struct hns_roce_query_pf_caps_e *resp_e; 2451 struct hns_roce_query_pf_caps_f *resp_f; 2452 enum hns_roce_opcode_type cmd; 2453 int ctx_hop_num; 2454 int pbl_hop_num; 2455 int cmd_num; 2456 int ret; 2457 int i; 2458 2459 cmd = hr_dev->is_vf ? HNS_ROCE_OPC_QUERY_VF_CAPS_NUM : 2460 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM; 2461 cmd_num = hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ? 2462 HNS_ROCE_QUERY_PF_CAPS_CMD_NUM_HIP08 : 2463 HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; 2464 2465 for (i = 0; i < cmd_num - 1; i++) { 2466 hns_roce_cmq_setup_basic_desc(&desc[i], cmd, true); 2467 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2468 } 2469 2470 hns_roce_cmq_setup_basic_desc(&desc[cmd_num - 1], cmd, true); 2471 desc[cmd_num - 1].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2472 2473 ret = hns_roce_cmq_send(hr_dev, desc, cmd_num); 2474 if (ret) 2475 return ret; 2476 2477 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 2478 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 2479 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 2480 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 2481 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 2482 resp_f = (struct hns_roce_query_pf_caps_f *)desc[5].data; 2483 2484 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 2485 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 2486 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 2487 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 2488 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg); 2489 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 2490 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges); 2491 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 2492 caps->num_other_vectors = resp_a->num_other_vectors; 2493 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 2494 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 2495 2496 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 2497 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 2498 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 2499 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 2500 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 2501 caps->idx_entry_sz = resp_b->idx_entry_sz; 2502 caps->sccc_sz = resp_b->sccc_sz; 2503 caps->max_mtu = resp_b->max_mtu; 2504 caps->min_cqes = resp_b->min_cqes; 2505 caps->min_wqes = resp_b->min_wqes; 2506 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 2507 caps->pkey_table_len[0] = resp_b->pkey_table_len; 2508 caps->phy_num_uars = resp_b->phy_num_uars; 2509 ctx_hop_num = resp_b->ctx_hop_num; 2510 pbl_hop_num = resp_b->pbl_hop_num; 2511 2512 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS); 2513 2514 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS); 2515 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 2516 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 2517 2518 if (hr_dev->is_vf) 2519 caps->flags &= ~HNS_ROCE_CAP_FLAG_BOND; 2520 2521 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS); 2522 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID); 2523 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH); 2524 caps->num_xrcds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_XRCDS); 2525 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS); 2526 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS); 2527 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD); 2528 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 2529 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 2530 2531 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS); 2532 caps->cong_cap = hr_reg_read(resp_d, PF_CAPS_D_CONG_CAP); 2533 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 2534 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH); 2535 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS); 2536 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH); 2537 caps->default_cong_type = hr_reg_read(resp_d, PF_CAPS_D_DEFAULT_ALG); 2538 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS); 2539 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS); 2540 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS); 2541 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS); 2542 2543 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS); 2544 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT); 2545 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS); 2546 caps->reserved_xrcds = hr_reg_read(resp_e, PF_CAPS_E_RSV_XRCDS); 2547 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS); 2548 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS); 2549 2550 caps->max_ack_req_msg_len = le32_to_cpu(resp_f->max_ack_req_msg_len); 2551 2552 caps->qpc_hop_num = ctx_hop_num; 2553 caps->sccc_hop_num = ctx_hop_num; 2554 caps->srqc_hop_num = ctx_hop_num; 2555 caps->cqc_hop_num = ctx_hop_num; 2556 caps->mpt_hop_num = ctx_hop_num; 2557 caps->mtt_hop_num = pbl_hop_num; 2558 caps->cqe_hop_num = pbl_hop_num; 2559 caps->srqwqe_hop_num = pbl_hop_num; 2560 caps->idx_hop_num = pbl_hop_num; 2561 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM); 2562 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM); 2563 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM); 2564 2565 if (!(caps->page_size_cap & PAGE_SIZE)) 2566 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 2567 2568 if (!hr_dev->is_vf) { 2569 caps->cqe_sz = resp_a->cqe_sz; 2570 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz); 2571 caps->default_aeq_arm_st = 2572 hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST); 2573 caps->default_ceq_arm_st = 2574 hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST); 2575 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 2576 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 2577 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 2578 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 2579 } 2580 2581 return 0; 2582 } 2583 2584 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val) 2585 { 2586 struct hns_roce_cmq_desc desc; 2587 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2588 2589 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE, 2590 false); 2591 2592 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type); 2593 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val); 2594 2595 return hns_roce_cmq_send(hr_dev, &desc, 1); 2596 } 2597 2598 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev) 2599 { 2600 struct hns_roce_caps *caps = &hr_dev->caps; 2601 int ret; 2602 2603 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 2604 return 0; 2605 2606 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE, 2607 caps->qpc_sz); 2608 if (ret) { 2609 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret); 2610 return ret; 2611 } 2612 2613 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE, 2614 caps->sccc_sz); 2615 if (ret) 2616 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret); 2617 2618 return ret; 2619 } 2620 2621 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev) 2622 { 2623 struct device *dev = hr_dev->dev; 2624 int ret; 2625 2626 hr_dev->func_num = 1; 2627 2628 ret = hns_roce_query_caps(hr_dev); 2629 if (ret) { 2630 dev_err(dev, "failed to query VF caps, ret = %d.\n", ret); 2631 return ret; 2632 } 2633 2634 ret = hns_roce_query_vf_resource(hr_dev); 2635 if (ret) { 2636 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret); 2637 return ret; 2638 } 2639 2640 apply_func_caps(hr_dev); 2641 2642 ret = hns_roce_v2_set_bt(hr_dev); 2643 if (ret) 2644 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret); 2645 2646 return ret; 2647 } 2648 2649 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev) 2650 { 2651 struct device *dev = hr_dev->dev; 2652 int ret; 2653 2654 ret = hns_roce_query_func_info(hr_dev); 2655 if (ret) { 2656 dev_err(dev, "failed to query func info, ret = %d.\n", ret); 2657 return ret; 2658 } 2659 2660 ret = hns_roce_config_global_param(hr_dev); 2661 if (ret) { 2662 dev_err(dev, "failed to config global param, ret = %d.\n", ret); 2663 return ret; 2664 } 2665 2666 ret = hns_roce_set_vf_switch_param(hr_dev); 2667 if (ret) { 2668 dev_err(dev, "failed to set switch param, ret = %d.\n", ret); 2669 return ret; 2670 } 2671 2672 ret = hns_roce_query_caps(hr_dev); 2673 if (ret) { 2674 dev_err(dev, "failed to query PF caps, ret = %d.\n", ret); 2675 return ret; 2676 } 2677 2678 ret = hns_roce_query_pf_resource(hr_dev); 2679 if (ret) { 2680 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret); 2681 return ret; 2682 } 2683 2684 apply_func_caps(hr_dev); 2685 2686 ret = hns_roce_alloc_vf_resource(hr_dev); 2687 if (ret) { 2688 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret); 2689 return ret; 2690 } 2691 2692 ret = hns_roce_v2_set_bt(hr_dev); 2693 if (ret) { 2694 dev_err(dev, "failed to config BA table, ret = %d.\n", ret); 2695 return ret; 2696 } 2697 2698 /* Configure the size of QPC, SCCC, etc. */ 2699 return hns_roce_config_entry_size(hr_dev); 2700 } 2701 2702 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2703 { 2704 struct device *dev = hr_dev->dev; 2705 int ret; 2706 2707 ret = hns_roce_cmq_query_hw_info(hr_dev); 2708 if (ret) { 2709 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret); 2710 return ret; 2711 } 2712 2713 ret = hns_roce_query_fw_ver(hr_dev); 2714 if (ret) { 2715 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret); 2716 return ret; 2717 } 2718 2719 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2720 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2721 2722 if (hr_dev->is_vf) 2723 return hns_roce_v2_vf_profile(hr_dev); 2724 else 2725 return hns_roce_v2_pf_profile(hr_dev); 2726 } 2727 2728 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf) 2729 { 2730 u32 i, next_ptr, page_num; 2731 __le64 *entry = cfg_buf; 2732 dma_addr_t addr; 2733 u64 val; 2734 2735 page_num = data_buf->npages; 2736 for (i = 0; i < page_num; i++) { 2737 addr = hns_roce_buf_page(data_buf, i); 2738 if (i == (page_num - 1)) 2739 next_ptr = 0; 2740 else 2741 next_ptr = i + 1; 2742 2743 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr); 2744 entry[i] = cpu_to_le64(val); 2745 } 2746 } 2747 2748 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev, 2749 struct hns_roce_link_table *table) 2750 { 2751 struct hns_roce_cmq_desc desc[2]; 2752 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2753 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2754 struct hns_roce_buf *buf = table->buf; 2755 enum hns_roce_opcode_type opcode; 2756 dma_addr_t addr; 2757 2758 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2759 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 2760 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2761 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 2762 2763 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map)); 2764 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map)); 2765 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages); 2766 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift)); 2767 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN); 2768 2769 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0)); 2770 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr)); 2771 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr)); 2772 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1); 2773 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0); 2774 2775 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1)); 2776 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr)); 2777 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr)); 2778 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1); 2779 2780 return hns_roce_cmq_send(hr_dev, desc, 2); 2781 } 2782 2783 static struct hns_roce_link_table * 2784 alloc_link_table_buf(struct hns_roce_dev *hr_dev) 2785 { 2786 u16 total_sl = hr_dev->caps.sl_num * hr_dev->func_num; 2787 struct hns_roce_v2_priv *priv = hr_dev->priv; 2788 struct hns_roce_link_table *link_tbl; 2789 u32 pg_shift, size, min_size; 2790 2791 link_tbl = &priv->ext_llm; 2792 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT; 2793 size = hr_dev->caps.num_qps * hr_dev->func_num * 2794 HNS_ROCE_V2_EXT_LLM_ENTRY_SZ; 2795 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(total_sl) << pg_shift; 2796 2797 /* Alloc data table */ 2798 size = max(size, min_size); 2799 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0); 2800 if (IS_ERR(link_tbl->buf)) 2801 return ERR_PTR(-ENOMEM); 2802 2803 /* Alloc config table */ 2804 size = link_tbl->buf->npages * sizeof(u64); 2805 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size, 2806 &link_tbl->table.map, 2807 GFP_KERNEL); 2808 if (!link_tbl->table.buf) { 2809 hns_roce_buf_free(hr_dev, link_tbl->buf); 2810 return ERR_PTR(-ENOMEM); 2811 } 2812 2813 return link_tbl; 2814 } 2815 2816 static void free_link_table_buf(struct hns_roce_dev *hr_dev, 2817 struct hns_roce_link_table *tbl) 2818 { 2819 if (tbl->buf) { 2820 u32 size = tbl->buf->npages * sizeof(u64); 2821 2822 dma_free_coherent(hr_dev->dev, size, tbl->table.buf, 2823 tbl->table.map); 2824 } 2825 2826 hns_roce_buf_free(hr_dev, tbl->buf); 2827 } 2828 2829 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev) 2830 { 2831 struct hns_roce_link_table *link_tbl; 2832 int ret; 2833 2834 link_tbl = alloc_link_table_buf(hr_dev); 2835 if (IS_ERR(link_tbl)) 2836 return -ENOMEM; 2837 2838 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) { 2839 ret = -EINVAL; 2840 goto err_alloc; 2841 } 2842 2843 config_llm_table(link_tbl->buf, link_tbl->table.buf); 2844 ret = set_llm_cfg_to_hw(hr_dev, link_tbl); 2845 if (ret) 2846 goto err_alloc; 2847 2848 return 0; 2849 2850 err_alloc: 2851 free_link_table_buf(hr_dev, link_tbl); 2852 return ret; 2853 } 2854 2855 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev) 2856 { 2857 struct hns_roce_v2_priv *priv = hr_dev->priv; 2858 2859 free_link_table_buf(hr_dev, &priv->ext_llm); 2860 } 2861 2862 static void free_dip_entry(struct hns_roce_dev *hr_dev) 2863 { 2864 struct hns_roce_dip *hr_dip; 2865 unsigned long idx; 2866 2867 xa_lock(&hr_dev->qp_table.dip_xa); 2868 2869 xa_for_each(&hr_dev->qp_table.dip_xa, idx, hr_dip) { 2870 __xa_erase(&hr_dev->qp_table.dip_xa, hr_dip->dip_idx); 2871 kfree(hr_dip); 2872 } 2873 2874 xa_unlock(&hr_dev->qp_table.dip_xa); 2875 } 2876 2877 static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev) 2878 { 2879 struct hns_roce_v2_priv *priv = hr_dev->priv; 2880 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2881 struct ib_device *ibdev = &hr_dev->ib_dev; 2882 struct hns_roce_pd *hr_pd; 2883 struct ib_pd *pd; 2884 2885 hr_pd = kzalloc_obj(*hr_pd); 2886 if (!hr_pd) 2887 return NULL; 2888 pd = &hr_pd->ibpd; 2889 pd->device = ibdev; 2890 2891 if (hns_roce_alloc_pd(pd, NULL)) { 2892 ibdev_err(ibdev, "failed to create pd for free mr.\n"); 2893 kfree(hr_pd); 2894 return NULL; 2895 } 2896 free_mr->rsv_pd = to_hr_pd(pd); 2897 free_mr->rsv_pd->ibpd.device = &hr_dev->ib_dev; 2898 free_mr->rsv_pd->ibpd.uobject = NULL; 2899 free_mr->rsv_pd->ibpd.__internal_mr = NULL; 2900 atomic_set(&free_mr->rsv_pd->ibpd.usecnt, 0); 2901 2902 return pd; 2903 } 2904 2905 static struct ib_cq *free_mr_init_cq(struct hns_roce_dev *hr_dev) 2906 { 2907 struct hns_roce_v2_priv *priv = hr_dev->priv; 2908 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2909 struct ib_device *ibdev = &hr_dev->ib_dev; 2910 struct ib_cq_init_attr cq_init_attr = {}; 2911 struct hns_roce_cq *hr_cq; 2912 struct ib_cq *cq; 2913 2914 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM; 2915 2916 hr_cq = kzalloc_obj(*hr_cq); 2917 if (!hr_cq) 2918 return NULL; 2919 2920 cq = &hr_cq->ib_cq; 2921 cq->device = ibdev; 2922 2923 if (hns_roce_create_cq(cq, &cq_init_attr, NULL)) { 2924 ibdev_err(ibdev, "failed to create cq for free mr.\n"); 2925 kfree(hr_cq); 2926 return NULL; 2927 } 2928 free_mr->rsv_cq = to_hr_cq(cq); 2929 free_mr->rsv_cq->ib_cq.device = &hr_dev->ib_dev; 2930 free_mr->rsv_cq->ib_cq.uobject = NULL; 2931 free_mr->rsv_cq->ib_cq.comp_handler = NULL; 2932 free_mr->rsv_cq->ib_cq.event_handler = NULL; 2933 free_mr->rsv_cq->ib_cq.cq_context = NULL; 2934 atomic_set(&free_mr->rsv_cq->ib_cq.usecnt, 0); 2935 2936 return cq; 2937 } 2938 2939 static int free_mr_init_qp(struct hns_roce_dev *hr_dev, struct ib_cq *cq, 2940 struct ib_qp_init_attr *init_attr, int i) 2941 { 2942 struct hns_roce_v2_priv *priv = hr_dev->priv; 2943 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2944 struct ib_device *ibdev = &hr_dev->ib_dev; 2945 struct hns_roce_qp *hr_qp; 2946 struct ib_qp *qp; 2947 int ret; 2948 2949 hr_qp = kzalloc_obj(*hr_qp); 2950 if (!hr_qp) 2951 return -ENOMEM; 2952 2953 qp = &hr_qp->ibqp; 2954 qp->device = ibdev; 2955 2956 ret = hns_roce_create_qp(qp, init_attr, NULL); 2957 if (ret) { 2958 ibdev_err(ibdev, "failed to create qp for free mr.\n"); 2959 kfree(hr_qp); 2960 return ret; 2961 } 2962 2963 free_mr->rsv_qp[i] = hr_qp; 2964 free_mr->rsv_qp[i]->ibqp.recv_cq = cq; 2965 free_mr->rsv_qp[i]->ibqp.send_cq = cq; 2966 2967 return 0; 2968 } 2969 2970 static void free_mr_exit(struct hns_roce_dev *hr_dev) 2971 { 2972 struct hns_roce_v2_priv *priv = hr_dev->priv; 2973 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2974 struct ib_qp *qp; 2975 int i; 2976 2977 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2978 if (free_mr->rsv_qp[i]) { 2979 qp = &free_mr->rsv_qp[i]->ibqp; 2980 hns_roce_v2_destroy_qp(qp, NULL); 2981 kfree(free_mr->rsv_qp[i]); 2982 free_mr->rsv_qp[i] = NULL; 2983 } 2984 } 2985 2986 if (free_mr->rsv_cq) { 2987 hns_roce_destroy_cq(&free_mr->rsv_cq->ib_cq, NULL); 2988 kfree(free_mr->rsv_cq); 2989 free_mr->rsv_cq = NULL; 2990 } 2991 2992 if (free_mr->rsv_pd) { 2993 hns_roce_dealloc_pd(&free_mr->rsv_pd->ibpd, NULL); 2994 kfree(free_mr->rsv_pd); 2995 free_mr->rsv_pd = NULL; 2996 } 2997 2998 mutex_destroy(&free_mr->mutex); 2999 } 3000 3001 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev) 3002 { 3003 struct hns_roce_v2_priv *priv = hr_dev->priv; 3004 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3005 struct ib_qp_init_attr qp_init_attr = {}; 3006 struct ib_pd *pd; 3007 struct ib_cq *cq; 3008 int ret; 3009 int i; 3010 3011 pd = free_mr_init_pd(hr_dev); 3012 if (!pd) 3013 return -ENOMEM; 3014 3015 cq = free_mr_init_cq(hr_dev); 3016 if (!cq) { 3017 ret = -ENOMEM; 3018 goto create_failed_cq; 3019 } 3020 3021 qp_init_attr.qp_type = IB_QPT_RC; 3022 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR; 3023 qp_init_attr.send_cq = cq; 3024 qp_init_attr.recv_cq = cq; 3025 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 3026 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM; 3027 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM; 3028 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM; 3029 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM; 3030 3031 ret = free_mr_init_qp(hr_dev, cq, &qp_init_attr, i); 3032 if (ret) 3033 goto create_failed_qp; 3034 } 3035 3036 return 0; 3037 3038 create_failed_qp: 3039 for (i--; i >= 0; i--) { 3040 hns_roce_v2_destroy_qp(&free_mr->rsv_qp[i]->ibqp, NULL); 3041 kfree(free_mr->rsv_qp[i]); 3042 } 3043 hns_roce_destroy_cq(cq, NULL); 3044 kfree(cq); 3045 3046 create_failed_cq: 3047 hns_roce_dealloc_pd(pd, NULL); 3048 kfree(pd); 3049 3050 return ret; 3051 } 3052 3053 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev, 3054 struct ib_qp_attr *attr, int sl_num) 3055 { 3056 struct hns_roce_v2_priv *priv = hr_dev->priv; 3057 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3058 struct ib_device *ibdev = &hr_dev->ib_dev; 3059 struct hns_roce_qp *hr_qp; 3060 int loopback; 3061 int mask; 3062 int ret; 3063 3064 hr_qp = to_hr_qp(&free_mr->rsv_qp[sl_num]->ibqp); 3065 hr_qp->free_mr_en = 1; 3066 hr_qp->ibqp.device = ibdev; 3067 hr_qp->ibqp.qp_type = IB_QPT_RC; 3068 3069 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS; 3070 attr->qp_state = IB_QPS_INIT; 3071 attr->port_num = 1; 3072 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE; 3073 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 3074 IB_QPS_INIT, NULL); 3075 if (ret) { 3076 ibdev_err_ratelimited(ibdev, "failed to modify qp to init, ret = %d.\n", 3077 ret); 3078 return ret; 3079 } 3080 3081 loopback = hr_dev->loop_idc; 3082 /* Set qpc lbi = 1 incidate loopback IO */ 3083 hr_dev->loop_idc = 1; 3084 3085 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN | 3086 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER; 3087 attr->qp_state = IB_QPS_RTR; 3088 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 3089 attr->path_mtu = IB_MTU_256; 3090 attr->dest_qp_num = hr_qp->qpn; 3091 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN; 3092 3093 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num); 3094 3095 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 3096 IB_QPS_RTR, NULL); 3097 hr_dev->loop_idc = loopback; 3098 if (ret) { 3099 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n", 3100 ret); 3101 return ret; 3102 } 3103 3104 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT | 3105 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC; 3106 attr->qp_state = IB_QPS_RTS; 3107 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN; 3108 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT; 3109 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT; 3110 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_RTR, 3111 IB_QPS_RTS, NULL); 3112 if (ret) 3113 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n", 3114 ret); 3115 3116 return ret; 3117 } 3118 3119 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev) 3120 { 3121 struct hns_roce_v2_priv *priv = hr_dev->priv; 3122 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3123 struct ib_qp_attr attr = {}; 3124 int ret; 3125 int i; 3126 3127 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0); 3128 rdma_ah_set_static_rate(&attr.ah_attr, 3); 3129 rdma_ah_set_port_num(&attr.ah_attr, 1); 3130 3131 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 3132 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i); 3133 if (ret) 3134 return ret; 3135 } 3136 3137 return 0; 3138 } 3139 3140 static int free_mr_init(struct hns_roce_dev *hr_dev) 3141 { 3142 struct hns_roce_v2_priv *priv = hr_dev->priv; 3143 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3144 int ret; 3145 3146 mutex_init(&free_mr->mutex); 3147 3148 ret = free_mr_alloc_res(hr_dev); 3149 if (ret) { 3150 mutex_destroy(&free_mr->mutex); 3151 return ret; 3152 } 3153 3154 ret = free_mr_modify_qp(hr_dev); 3155 if (ret) 3156 goto err_modify_qp; 3157 3158 return 0; 3159 3160 err_modify_qp: 3161 free_mr_exit(hr_dev); 3162 3163 return ret; 3164 } 3165 3166 static int get_hem_table(struct hns_roce_dev *hr_dev) 3167 { 3168 unsigned int qpc_count; 3169 unsigned int cqc_count; 3170 unsigned int gmv_count; 3171 int ret; 3172 int i; 3173 3174 /* Alloc memory for source address table buffer space chunk */ 3175 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num; 3176 gmv_count++) { 3177 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count); 3178 if (ret) 3179 goto err_gmv_failed; 3180 } 3181 3182 if (hr_dev->is_vf) 3183 return 0; 3184 3185 /* Alloc memory for QPC Timer buffer space chunk */ 3186 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 3187 qpc_count++) { 3188 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 3189 qpc_count); 3190 if (ret) { 3191 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 3192 goto err_qpc_timer_failed; 3193 } 3194 } 3195 3196 /* Alloc memory for CQC Timer buffer space chunk */ 3197 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 3198 cqc_count++) { 3199 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 3200 cqc_count); 3201 if (ret) { 3202 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 3203 goto err_cqc_timer_failed; 3204 } 3205 } 3206 3207 return 0; 3208 3209 err_cqc_timer_failed: 3210 for (i = 0; i < cqc_count; i++) 3211 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 3212 3213 err_qpc_timer_failed: 3214 for (i = 0; i < qpc_count; i++) 3215 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 3216 3217 err_gmv_failed: 3218 for (i = 0; i < gmv_count; i++) 3219 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 3220 3221 return ret; 3222 } 3223 3224 static void put_hem_table(struct hns_roce_dev *hr_dev) 3225 { 3226 int i; 3227 3228 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++) 3229 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 3230 3231 if (hr_dev->is_vf) 3232 return; 3233 3234 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++) 3235 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 3236 3237 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++) 3238 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 3239 } 3240 3241 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 3242 { 3243 int ret; 3244 3245 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 3246 ret = free_mr_init(hr_dev); 3247 if (ret) { 3248 dev_err(hr_dev->dev, "failed to init free mr!\n"); 3249 return ret; 3250 } 3251 } 3252 3253 /* The hns ROCEE requires the extdb info to be cleared before using */ 3254 ret = hns_roce_clear_extdb_list_info(hr_dev); 3255 if (ret) 3256 goto err_clear_extdb_failed; 3257 3258 ret = get_hem_table(hr_dev); 3259 if (ret) 3260 goto err_get_hem_table_failed; 3261 3262 if (hr_dev->is_vf) 3263 return 0; 3264 3265 ret = hns_roce_init_link_table(hr_dev); 3266 if (ret) { 3267 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret); 3268 goto err_llm_init_failed; 3269 } 3270 3271 return 0; 3272 3273 err_llm_init_failed: 3274 put_hem_table(hr_dev); 3275 err_get_hem_table_failed: 3276 hns_roce_function_clear(hr_dev); 3277 err_clear_extdb_failed: 3278 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3279 free_mr_exit(hr_dev); 3280 3281 return ret; 3282 } 3283 3284 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 3285 { 3286 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3287 free_mr_exit(hr_dev); 3288 3289 hns_roce_function_clear(hr_dev); 3290 3291 if (!hr_dev->is_vf) 3292 hns_roce_free_link_table(hr_dev); 3293 3294 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 3295 free_dip_entry(hr_dev); 3296 } 3297 3298 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, 3299 struct hns_roce_mbox_msg *mbox_msg) 3300 { 3301 struct hns_roce_cmq_desc desc; 3302 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 3303 3304 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 3305 3306 mb->in_param_l = cpu_to_le32(mbox_msg->in_param); 3307 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32); 3308 mb->out_param_l = cpu_to_le32(mbox_msg->out_param); 3309 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32); 3310 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd); 3311 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 | 3312 mbox_msg->token); 3313 3314 return hns_roce_cmq_send(hr_dev, &desc, 1); 3315 } 3316 3317 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout, 3318 u8 *complete_status) 3319 { 3320 struct hns_roce_mbox_status *mb_st; 3321 struct hns_roce_cmq_desc desc; 3322 unsigned long end; 3323 int ret = -EBUSY; 3324 u32 status; 3325 bool busy; 3326 3327 mb_st = (struct hns_roce_mbox_status *)desc.data; 3328 end = msecs_to_jiffies(timeout) + jiffies; 3329 while (v2_chk_mbox_is_avail(hr_dev, &busy)) { 3330 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 3331 return -EIO; 3332 3333 status = 0; 3334 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, 3335 true); 3336 ret = __hns_roce_cmq_send(hr_dev, &desc, 1); 3337 if (!ret) { 3338 status = le32_to_cpu(mb_st->mb_status_hw_run); 3339 /* No pending message exists in ROCEE mbox. */ 3340 if (!(status & MB_ST_HW_RUN_M)) 3341 break; 3342 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3343 break; 3344 } 3345 3346 if (time_after(jiffies, end)) { 3347 dev_err_ratelimited(hr_dev->dev, 3348 "failed to wait mbox status 0x%x\n", 3349 status); 3350 return -ETIMEDOUT; 3351 } 3352 3353 cond_resched(); 3354 ret = -EBUSY; 3355 } 3356 3357 if (!ret) { 3358 *complete_status = (u8)(status & MB_ST_COMPLETE_M); 3359 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3360 /* Ignore all errors if the mbox is unavailable. */ 3361 ret = 0; 3362 *complete_status = MB_ST_COMPLETE_M; 3363 } 3364 3365 return ret; 3366 } 3367 3368 static int v2_post_mbox(struct hns_roce_dev *hr_dev, 3369 struct hns_roce_mbox_msg *mbox_msg) 3370 { 3371 u8 status = 0; 3372 int ret; 3373 3374 /* Waiting for the mbox to be idle */ 3375 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS, 3376 &status); 3377 if (unlikely(ret)) { 3378 dev_err_ratelimited(hr_dev->dev, 3379 "failed to check post mbox status = 0x%x, ret = %d.\n", 3380 status, ret); 3381 return ret; 3382 } 3383 3384 /* Post new message to mbox */ 3385 ret = hns_roce_mbox_post(hr_dev, mbox_msg); 3386 if (ret) 3387 dev_err_ratelimited(hr_dev->dev, 3388 "failed to post mailbox, ret = %d.\n", ret); 3389 3390 return ret; 3391 } 3392 3393 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev) 3394 { 3395 u8 status = 0; 3396 int ret; 3397 3398 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS, 3399 &status); 3400 if (!ret) { 3401 if (status != MB_ST_COMPLETE_SUCC) 3402 return -EBUSY; 3403 } else { 3404 dev_err_ratelimited(hr_dev->dev, 3405 "failed to check mbox status = 0x%x, ret = %d.\n", 3406 status, ret); 3407 } 3408 3409 return ret; 3410 } 3411 3412 static void copy_gid(void *dest, const union ib_gid *gid) 3413 { 3414 #define GID_SIZE 4 3415 const union ib_gid *src = gid; 3416 __le32 (*p)[GID_SIZE] = dest; 3417 int i; 3418 3419 if (!gid) 3420 src = &zgid; 3421 3422 for (i = 0; i < GID_SIZE; i++) 3423 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]); 3424 } 3425 3426 static int config_sgid_table(struct hns_roce_dev *hr_dev, 3427 int gid_index, const union ib_gid *gid, 3428 enum hns_roce_sgid_type sgid_type) 3429 { 3430 struct hns_roce_cmq_desc desc; 3431 struct hns_roce_cfg_sgid_tb *sgid_tb = 3432 (struct hns_roce_cfg_sgid_tb *)desc.data; 3433 3434 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 3435 3436 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index); 3437 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type); 3438 3439 copy_gid(&sgid_tb->vf_sgid_l, gid); 3440 3441 return hns_roce_cmq_send(hr_dev, &desc, 1); 3442 } 3443 3444 static int config_gmv_table(struct hns_roce_dev *hr_dev, 3445 int gid_index, const union ib_gid *gid, 3446 enum hns_roce_sgid_type sgid_type, 3447 const struct ib_gid_attr *attr) 3448 { 3449 struct hns_roce_cmq_desc desc[2]; 3450 struct hns_roce_cfg_gmv_tb_a *tb_a = 3451 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data; 3452 struct hns_roce_cfg_gmv_tb_b *tb_b = 3453 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data; 3454 3455 u16 vlan_id = VLAN_CFI_MASK; 3456 u8 mac[ETH_ALEN] = {}; 3457 int ret; 3458 3459 if (gid) { 3460 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac); 3461 if (ret) 3462 return ret; 3463 } 3464 3465 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3466 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 3467 3468 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3469 3470 copy_gid(&tb_a->vf_sgid_l, gid); 3471 3472 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type); 3473 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK); 3474 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id); 3475 3476 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac); 3477 3478 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]); 3479 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index); 3480 3481 return hns_roce_cmq_send(hr_dev, desc, 2); 3482 } 3483 3484 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index, 3485 const union ib_gid *gid, 3486 const struct ib_gid_attr *attr) 3487 { 3488 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 3489 int ret; 3490 3491 if (gid) { 3492 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 3493 if (ipv6_addr_v4mapped((void *)gid)) 3494 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 3495 else 3496 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 3497 } else if (attr->gid_type == IB_GID_TYPE_ROCE) { 3498 sgid_type = GID_TYPE_FLAG_ROCE_V1; 3499 } 3500 } 3501 3502 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 3503 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr); 3504 else 3505 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type); 3506 3507 if (ret) 3508 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n", 3509 ret); 3510 3511 return ret; 3512 } 3513 3514 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 3515 const u8 *addr) 3516 { 3517 struct hns_roce_cmq_desc desc; 3518 struct hns_roce_cfg_smac_tb *smac_tb = 3519 (struct hns_roce_cfg_smac_tb *)desc.data; 3520 u16 reg_smac_h; 3521 u32 reg_smac_l; 3522 3523 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 3524 3525 reg_smac_l = *(u32 *)(&addr[0]); 3526 reg_smac_h = *(u16 *)(&addr[4]); 3527 3528 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port); 3529 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h); 3530 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 3531 3532 return hns_roce_cmq_send(hr_dev, &desc, 1); 3533 } 3534 3535 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 3536 struct hns_roce_v2_mpt_entry *mpt_entry, 3537 struct hns_roce_mr *mr) 3538 { 3539 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 3540 struct ib_device *ibdev = &hr_dev->ib_dev; 3541 dma_addr_t pbl_ba; 3542 int ret; 3543 int i; 3544 3545 ret = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 3546 min_t(int, ARRAY_SIZE(pages), mr->npages)); 3547 if (ret) { 3548 ibdev_err(ibdev, "failed to find PBL mtr, ret = %d.\n", ret); 3549 return ret; 3550 } 3551 3552 /* Aligned to the hardware address access unit */ 3553 for (i = 0; i < ARRAY_SIZE(pages); i++) 3554 pages[i] >>= MPT_PBL_BUF_ADDR_S; 3555 3556 pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr); 3557 3558 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3559 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> MPT_PBL_BA_ADDR_S); 3560 hr_reg_write(mpt_entry, MPT_PBL_BA_H, 3561 upper_32_bits(pbl_ba >> MPT_PBL_BA_ADDR_S)); 3562 3563 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 3564 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0])); 3565 3566 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 3567 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1])); 3568 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3569 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3570 3571 return 0; 3572 } 3573 3574 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, 3575 void *mb_buf, struct hns_roce_mr *mr) 3576 { 3577 struct hns_roce_v2_mpt_entry *mpt_entry; 3578 3579 mpt_entry = mb_buf; 3580 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3581 3582 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3583 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3584 3585 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN, 3586 mr->access & IB_ACCESS_REMOTE_ATOMIC); 3587 hr_reg_write_bool(mpt_entry, MPT_RR_EN, 3588 mr->access & IB_ACCESS_REMOTE_READ); 3589 hr_reg_write_bool(mpt_entry, MPT_RW_EN, 3590 mr->access & IB_ACCESS_REMOTE_WRITE); 3591 hr_reg_write_bool(mpt_entry, MPT_LW_EN, 3592 mr->access & IB_ACCESS_LOCAL_WRITE); 3593 3594 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3595 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3596 mpt_entry->lkey = cpu_to_le32(mr->key); 3597 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3598 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3599 3600 if (mr->type != MR_TYPE_MR) 3601 hr_reg_enable(mpt_entry, MPT_PA); 3602 3603 if (mr->type == MR_TYPE_DMA) 3604 return 0; 3605 3606 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0) 3607 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num); 3608 3609 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3610 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3611 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD); 3612 3613 return set_mtpt_pbl(hr_dev, mpt_entry, mr); 3614 } 3615 3616 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 3617 struct hns_roce_mr *mr, int flags, 3618 void *mb_buf) 3619 { 3620 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 3621 u32 mr_access_flags = mr->access; 3622 int ret = 0; 3623 3624 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3625 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3626 3627 if (flags & IB_MR_REREG_ACCESS) { 3628 hr_reg_write(mpt_entry, MPT_ATOMIC_EN, 3629 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 3630 hr_reg_write(mpt_entry, MPT_RR_EN, 3631 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 3632 hr_reg_write(mpt_entry, MPT_RW_EN, 3633 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 3634 hr_reg_write(mpt_entry, MPT_LW_EN, 3635 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 3636 } 3637 3638 if (flags & IB_MR_REREG_TRANS) { 3639 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3640 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3641 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3642 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3643 3644 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 3645 } 3646 3647 return ret; 3648 } 3649 3650 static int hns_roce_v2_frmr_write_mtpt(void *mb_buf, struct hns_roce_mr *mr) 3651 { 3652 dma_addr_t pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr); 3653 struct hns_roce_v2_mpt_entry *mpt_entry; 3654 3655 mpt_entry = mb_buf; 3656 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3657 3658 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3659 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3660 3661 hr_reg_enable(mpt_entry, MPT_RA_EN); 3662 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3663 3664 hr_reg_enable(mpt_entry, MPT_FRE); 3665 hr_reg_enable(mpt_entry, MPT_BPD); 3666 hr_reg_clear(mpt_entry, MPT_PA); 3667 3668 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1); 3669 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3670 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3671 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3672 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3673 3674 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3675 3676 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3677 MPT_PBL_BA_ADDR_S)); 3678 hr_reg_write(mpt_entry, MPT_PBL_BA_H, 3679 upper_32_bits(pbl_ba >> MPT_PBL_BA_ADDR_S)); 3680 3681 return 0; 3682 } 3683 3684 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp) 3685 { 3686 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device); 3687 struct ib_device *ibdev = &hr_dev->ib_dev; 3688 const struct ib_send_wr *bad_wr; 3689 struct ib_rdma_wr rdma_wr = {}; 3690 struct ib_send_wr *send_wr; 3691 int ret; 3692 3693 send_wr = &rdma_wr.wr; 3694 send_wr->opcode = IB_WR_RDMA_WRITE; 3695 3696 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr); 3697 if (ret) { 3698 ibdev_err_ratelimited(ibdev, "failed to post wqe for free mr, ret = %d.\n", 3699 ret); 3700 return ret; 3701 } 3702 3703 return 0; 3704 } 3705 3706 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3707 struct ib_wc *wc); 3708 3709 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev) 3710 { 3711 struct hns_roce_v2_priv *priv = hr_dev->priv; 3712 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3713 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)]; 3714 struct ib_device *ibdev = &hr_dev->ib_dev; 3715 struct hns_roce_qp *hr_qp; 3716 unsigned long end; 3717 int cqe_cnt = 0; 3718 int npolled; 3719 int ret; 3720 int i; 3721 3722 /* 3723 * If the device initialization is not complete or in the uninstall 3724 * process, then there is no need to execute free mr. 3725 */ 3726 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 3727 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT || 3728 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) 3729 return; 3730 3731 mutex_lock(&free_mr->mutex); 3732 3733 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 3734 hr_qp = free_mr->rsv_qp[i]; 3735 3736 ret = free_mr_post_send_lp_wqe(hr_qp); 3737 if (ret) { 3738 ibdev_err_ratelimited(ibdev, 3739 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n", 3740 hr_qp->qpn, ret); 3741 break; 3742 } 3743 3744 cqe_cnt++; 3745 } 3746 3747 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies; 3748 while (cqe_cnt) { 3749 npolled = hns_roce_v2_poll_cq(&free_mr->rsv_cq->ib_cq, cqe_cnt, wc); 3750 if (npolled < 0) { 3751 ibdev_err_ratelimited(ibdev, 3752 "failed to poll cqe for free mr, remain %d cqe.\n", 3753 cqe_cnt); 3754 goto out; 3755 } 3756 3757 if (time_after(jiffies, end)) { 3758 ibdev_err_ratelimited(ibdev, 3759 "failed to poll cqe for free mr and timeout, remain %d cqe.\n", 3760 cqe_cnt); 3761 goto out; 3762 } 3763 cqe_cnt -= npolled; 3764 } 3765 3766 out: 3767 mutex_unlock(&free_mr->mutex); 3768 } 3769 3770 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev) 3771 { 3772 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3773 free_mr_send_cmd_to_hw(hr_dev); 3774 } 3775 3776 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 3777 { 3778 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size); 3779 } 3780 3781 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n) 3782 { 3783 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 3784 3785 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 3786 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe : 3787 NULL; 3788 } 3789 3790 static inline void update_cq_db(struct hns_roce_dev *hr_dev, 3791 struct hns_roce_cq *hr_cq) 3792 { 3793 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) { 3794 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M; 3795 } else { 3796 struct hns_roce_v2_db cq_db = {}; 3797 3798 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3799 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB); 3800 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3801 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1); 3802 3803 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3804 } 3805 } 3806 3807 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3808 struct hns_roce_srq *srq) 3809 { 3810 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3811 struct hns_roce_v2_cqe *cqe, *dest; 3812 u32 prod_index; 3813 int nfreed = 0; 3814 int wqe_index; 3815 u8 owner_bit; 3816 3817 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 3818 ++prod_index) { 3819 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 3820 break; 3821 } 3822 3823 /* 3824 * Now backwards through the CQ, removing CQ entries 3825 * that match our QP by overwriting them with next entries. 3826 */ 3827 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 3828 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 3829 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) { 3830 if (srq && hr_reg_read(cqe, CQE_S_R)) { 3831 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX); 3832 hns_roce_free_srq_wqe(srq, wqe_index); 3833 } 3834 ++nfreed; 3835 } else if (nfreed) { 3836 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 3837 hr_cq->ib_cq.cqe); 3838 owner_bit = hr_reg_read(dest, CQE_OWNER); 3839 memcpy(dest, cqe, hr_cq->cqe_size); 3840 hr_reg_write(dest, CQE_OWNER, owner_bit); 3841 } 3842 } 3843 3844 if (nfreed) { 3845 hr_cq->cons_index += nfreed; 3846 update_cq_db(hr_dev, hr_cq); 3847 } 3848 } 3849 3850 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3851 struct hns_roce_srq *srq) 3852 { 3853 spin_lock_irq(&hr_cq->lock); 3854 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 3855 spin_unlock_irq(&hr_cq->lock); 3856 } 3857 3858 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 3859 struct hns_roce_cq *hr_cq, void *mb_buf, 3860 u64 *mtts, dma_addr_t dma_handle) 3861 { 3862 struct hns_roce_v2_cq_context *cq_context; 3863 3864 cq_context = mb_buf; 3865 memset(cq_context, 0, sizeof(*cq_context)); 3866 3867 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID); 3868 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED); 3869 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth)); 3870 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector); 3871 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn); 3872 3873 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE) 3874 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B); 3875 3876 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 3877 hr_reg_enable(cq_context, CQC_STASH); 3878 3879 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L, 3880 to_hr_hw_page_addr(mtts[0])); 3881 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H, 3882 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3883 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num == 3884 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 3885 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L, 3886 to_hr_hw_page_addr(mtts[1])); 3887 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H, 3888 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3889 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ, 3890 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 3891 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ, 3892 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 3893 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> CQC_CQE_BA_L_S); 3894 hr_reg_write(cq_context, CQC_CQE_BA_H, dma_handle >> CQC_CQE_BA_H_S); 3895 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN, 3896 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB); 3897 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L, 3898 ((u32)hr_cq->db.dma) >> 1); 3899 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H, 3900 hr_cq->db.dma >> CQC_CQE_DB_RECORD_ADDR_H_S); 3901 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, 3902 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 3903 hr_reg_write(cq_context, CQC_CQ_PERIOD, 3904 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 3905 } 3906 3907 static bool left_sw_wc(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq) 3908 { 3909 struct hns_roce_qp *hr_qp; 3910 3911 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3912 if (hr_qp->sq.head != hr_qp->sq.tail) 3913 return true; 3914 } 3915 3916 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3917 if (hr_qp->rq.head != hr_qp->rq.tail) 3918 return true; 3919 } 3920 3921 return false; 3922 } 3923 3924 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 3925 enum ib_cq_notify_flags flags) 3926 { 3927 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3928 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3929 struct hns_roce_v2_db cq_db = {}; 3930 u32 notify_flag; 3931 3932 if (hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN) { 3933 if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && 3934 left_sw_wc(hr_dev, hr_cq)) 3935 return 1; 3936 return 0; 3937 } 3938 /* 3939 * flags = 0, then notify_flag : next 3940 * flags = 1, then notify flag : solocited 3941 */ 3942 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 3943 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 3944 3945 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3946 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY); 3947 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3948 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn); 3949 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag); 3950 3951 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3952 3953 return 0; 3954 } 3955 3956 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 3957 int num_entries, struct ib_wc *wc) 3958 { 3959 unsigned int left; 3960 int npolled = 0; 3961 3962 left = wq->head - wq->tail; 3963 if (left == 0) 3964 return 0; 3965 3966 left = min_t(unsigned int, (unsigned int)num_entries, left); 3967 while (npolled < left) { 3968 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3969 wc->status = IB_WC_WR_FLUSH_ERR; 3970 wc->vendor_err = 0; 3971 wc->qp = &hr_qp->ibqp; 3972 3973 wq->tail++; 3974 wc++; 3975 npolled++; 3976 } 3977 3978 return npolled; 3979 } 3980 3981 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3982 struct ib_wc *wc) 3983 { 3984 struct hns_roce_qp *hr_qp; 3985 int npolled = 0; 3986 3987 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3988 npolled += sw_comp(hr_qp, &hr_qp->sq, 3989 num_entries - npolled, wc + npolled); 3990 if (npolled >= num_entries) 3991 goto out; 3992 } 3993 3994 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3995 npolled += sw_comp(hr_qp, &hr_qp->rq, 3996 num_entries - npolled, wc + npolled); 3997 if (npolled >= num_entries) 3998 goto out; 3999 } 4000 4001 out: 4002 return npolled; 4003 } 4004 4005 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 4006 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe, 4007 struct ib_wc *wc) 4008 { 4009 static const struct { 4010 u32 cqe_status; 4011 enum ib_wc_status wc_status; 4012 } map[] = { 4013 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 4014 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 4015 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 4016 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 4017 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 4018 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 4019 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 4020 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 4021 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 4022 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 4023 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 4024 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 4025 IB_WC_RETRY_EXC_ERR }, 4026 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 4027 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 4028 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR} 4029 }; 4030 4031 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS); 4032 int i; 4033 4034 wc->status = IB_WC_GENERAL_ERR; 4035 for (i = 0; i < ARRAY_SIZE(map); i++) 4036 if (cqe_status == map[i].cqe_status) { 4037 wc->status = map[i].wc_status; 4038 break; 4039 } 4040 4041 if (likely(wc->status == IB_WC_SUCCESS || 4042 wc->status == IB_WC_WR_FLUSH_ERR)) 4043 return; 4044 4045 ibdev_err_ratelimited(&hr_dev->ib_dev, "error cqe status 0x%x:\n", 4046 cqe_status); 4047 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_NONE, 16, 4, cqe, 4048 cq->cqe_size, false); 4049 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS); 4050 4051 /* 4052 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in 4053 * the standard protocol, the driver must ignore it and needn't to set 4054 * the QP to an error state. 4055 */ 4056 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR) 4057 return; 4058 4059 flush_cqe(hr_dev, qp); 4060 } 4061 4062 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe, 4063 struct hns_roce_qp **cur_qp) 4064 { 4065 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 4066 struct hns_roce_qp *hr_qp = *cur_qp; 4067 u32 qpn; 4068 4069 qpn = hr_reg_read(cqe, CQE_LCL_QPN); 4070 4071 if (!hr_qp || qpn != hr_qp->qpn) { 4072 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 4073 if (unlikely(!hr_qp)) { 4074 ibdev_err(&hr_dev->ib_dev, 4075 "CQ %06lx with entry for unknown QPN %06x\n", 4076 hr_cq->cqn, qpn); 4077 return -EINVAL; 4078 } 4079 *cur_qp = hr_qp; 4080 } 4081 4082 return 0; 4083 } 4084 4085 /* 4086 * mapped-value = 1 + real-value 4087 * The ib wc opcode's real value is start from 0, In order to distinguish 4088 * between initialized and uninitialized map values, we plus 1 to the actual 4089 * value when defining the mapping, so that the validity can be identified by 4090 * checking whether the mapped value is greater than 0. 4091 */ 4092 #define HR_WC_OP_MAP(hr_key, ib_key) \ 4093 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key 4094 4095 static const u32 wc_send_op_map[] = { 4096 HR_WC_OP_MAP(SEND, SEND), 4097 HR_WC_OP_MAP(SEND_WITH_INV, SEND), 4098 HR_WC_OP_MAP(SEND_WITH_IMM, SEND), 4099 HR_WC_OP_MAP(RDMA_READ, RDMA_READ), 4100 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE), 4101 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE), 4102 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP), 4103 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD), 4104 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP), 4105 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD), 4106 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR), 4107 }; 4108 4109 static int to_ib_wc_send_op(u32 hr_opcode) 4110 { 4111 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map)) 4112 return -EINVAL; 4113 4114 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 : 4115 -EINVAL; 4116 } 4117 4118 static const u32 wc_recv_op_map[] = { 4119 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM), 4120 HR_WC_OP_MAP(SEND, RECV), 4121 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM), 4122 HR_WC_OP_MAP(SEND_WITH_INV, RECV), 4123 }; 4124 4125 static int to_ib_wc_recv_op(u32 hr_opcode) 4126 { 4127 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map)) 4128 return -EINVAL; 4129 4130 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 : 4131 -EINVAL; 4132 } 4133 4134 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 4135 { 4136 u32 hr_opcode; 4137 int ib_opcode; 4138 4139 wc->wc_flags = 0; 4140 4141 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 4142 switch (hr_opcode) { 4143 case HNS_ROCE_V2_WQE_OP_RDMA_READ: 4144 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 4145 break; 4146 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM: 4147 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM: 4148 wc->wc_flags |= IB_WC_WITH_IMM; 4149 break; 4150 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP: 4151 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD: 4152 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP: 4153 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD: 4154 wc->byte_len = 8; 4155 break; 4156 default: 4157 break; 4158 } 4159 4160 ib_opcode = to_ib_wc_send_op(hr_opcode); 4161 if (ib_opcode < 0) 4162 wc->status = IB_WC_GENERAL_ERR; 4163 else 4164 wc->opcode = ib_opcode; 4165 } 4166 4167 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 4168 { 4169 u32 hr_opcode; 4170 int ib_opcode; 4171 4172 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 4173 4174 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 4175 switch (hr_opcode) { 4176 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 4177 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 4178 wc->wc_flags = IB_WC_WITH_IMM; 4179 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata)); 4180 break; 4181 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 4182 wc->wc_flags = IB_WC_WITH_INVALIDATE; 4183 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 4184 break; 4185 default: 4186 wc->wc_flags = 0; 4187 } 4188 4189 ib_opcode = to_ib_wc_recv_op(hr_opcode); 4190 if (ib_opcode < 0) 4191 wc->status = IB_WC_GENERAL_ERR; 4192 else 4193 wc->opcode = ib_opcode; 4194 4195 wc->sl = hr_reg_read(cqe, CQE_SL); 4196 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN); 4197 wc->slid = 0; 4198 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0; 4199 wc->port_num = hr_reg_read(cqe, CQE_PORTN); 4200 wc->pkey_index = 0; 4201 4202 if (hr_reg_read(cqe, CQE_VID_VLD)) { 4203 wc->vlan_id = hr_reg_read(cqe, CQE_VID); 4204 wc->wc_flags |= IB_WC_WITH_VLAN; 4205 } else { 4206 wc->vlan_id = 0xffff; 4207 } 4208 4209 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE); 4210 4211 return 0; 4212 } 4213 4214 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 4215 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 4216 { 4217 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 4218 struct hns_roce_qp *qp = *cur_qp; 4219 struct hns_roce_srq *srq = NULL; 4220 struct hns_roce_v2_cqe *cqe; 4221 struct hns_roce_wq *wq; 4222 int is_send; 4223 u16 wqe_idx; 4224 int ret; 4225 4226 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 4227 if (!cqe) 4228 return -EAGAIN; 4229 4230 ++hr_cq->cons_index; 4231 /* Memory barrier */ 4232 rmb(); 4233 4234 ret = get_cur_qp(hr_cq, cqe, &qp); 4235 if (ret) 4236 return ret; 4237 4238 wc->qp = &qp->ibqp; 4239 wc->vendor_err = 0; 4240 4241 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX); 4242 4243 is_send = !hr_reg_read(cqe, CQE_S_R); 4244 if (is_send) { 4245 wq = &qp->sq; 4246 4247 /* If sg_signal_bit is set, tail pointer will be updated to 4248 * the WQE corresponding to the current CQE. 4249 */ 4250 if (qp->sq_signal_bits) 4251 wq->tail += (wqe_idx - (u16)wq->tail) & 4252 (wq->wqe_cnt - 1); 4253 4254 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 4255 ++wq->tail; 4256 4257 fill_send_wc(wc, cqe); 4258 } else { 4259 if (qp->ibqp.srq) { 4260 srq = to_hr_srq(qp->ibqp.srq); 4261 wc->wr_id = srq->wrid[wqe_idx]; 4262 hns_roce_free_srq_wqe(srq, wqe_idx); 4263 } else { 4264 wq = &qp->rq; 4265 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 4266 ++wq->tail; 4267 } 4268 4269 ret = fill_recv_wc(wc, cqe); 4270 } 4271 4272 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc); 4273 if (unlikely(wc->status != IB_WC_SUCCESS)) 4274 return 0; 4275 4276 return ret; 4277 } 4278 4279 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 4280 struct ib_wc *wc) 4281 { 4282 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 4283 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 4284 struct hns_roce_qp *cur_qp = NULL; 4285 unsigned long flags; 4286 int npolled; 4287 4288 spin_lock_irqsave(&hr_cq->lock, flags); 4289 4290 /* 4291 * When the device starts to reset, the state is RST_DOWN. At this time, 4292 * there may still be some valid CQEs in the hardware that are not 4293 * polled. Therefore, it is not allowed to switch to the software mode 4294 * immediately. When the state changes to UNINIT, CQE no longer exists 4295 * in the hardware, and then switch to software mode. 4296 */ 4297 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 4298 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 4299 goto out; 4300 } 4301 4302 for (npolled = 0; npolled < num_entries; ++npolled) { 4303 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 4304 break; 4305 } 4306 4307 if (npolled) 4308 update_cq_db(hr_dev, hr_cq); 4309 4310 out: 4311 spin_unlock_irqrestore(&hr_cq->lock, flags); 4312 4313 return npolled; 4314 } 4315 4316 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 4317 u32 step_idx, u8 *mbox_cmd) 4318 { 4319 u8 cmd; 4320 4321 switch (type) { 4322 case HEM_TYPE_QPC: 4323 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0; 4324 break; 4325 case HEM_TYPE_MTPT: 4326 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0; 4327 break; 4328 case HEM_TYPE_CQC: 4329 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0; 4330 break; 4331 case HEM_TYPE_SRQC: 4332 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0; 4333 break; 4334 case HEM_TYPE_SCCC: 4335 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0; 4336 break; 4337 case HEM_TYPE_QPC_TIMER: 4338 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 4339 break; 4340 case HEM_TYPE_CQC_TIMER: 4341 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 4342 break; 4343 default: 4344 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type); 4345 return -EINVAL; 4346 } 4347 4348 *mbox_cmd = cmd + step_idx; 4349 4350 return 0; 4351 } 4352 4353 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, 4354 dma_addr_t base_addr) 4355 { 4356 struct hns_roce_cmq_desc desc; 4357 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 4358 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz); 4359 u64 addr = to_hr_hw_page_addr(base_addr); 4360 4361 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 4362 4363 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr)); 4364 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr)); 4365 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 4366 4367 return hns_roce_cmq_send(hr_dev, &desc, 1); 4368 } 4369 4370 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, 4371 dma_addr_t base_addr, u32 hem_type, u32 step_idx) 4372 { 4373 int ret; 4374 u8 cmd; 4375 4376 if (unlikely(hem_type == HEM_TYPE_GMV)) 4377 return config_gmv_ba_to_hw(hr_dev, obj, base_addr); 4378 4379 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx)) 4380 return 0; 4381 4382 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd); 4383 if (ret < 0) 4384 return ret; 4385 4386 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj); 4387 } 4388 4389 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 4390 struct hns_roce_hem_table *table, int obj, 4391 u32 step_idx) 4392 { 4393 struct hns_roce_hem_mhop mhop; 4394 struct hns_roce_hem *hem; 4395 unsigned long mhop_obj = obj; 4396 int i, j, k; 4397 int ret = 0; 4398 u64 hem_idx = 0; 4399 u64 l1_idx = 0; 4400 u64 bt_ba = 0; 4401 u32 chunk_ba_num; 4402 u32 hop_num; 4403 4404 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4405 return 0; 4406 4407 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 4408 i = mhop.l0_idx; 4409 j = mhop.l1_idx; 4410 k = mhop.l2_idx; 4411 hop_num = mhop.hop_num; 4412 chunk_ba_num = mhop.bt_chunk_size / 8; 4413 4414 if (hop_num == 2) { 4415 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 4416 k; 4417 l1_idx = i * chunk_ba_num + j; 4418 } else if (hop_num == 1) { 4419 hem_idx = i * chunk_ba_num + j; 4420 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 4421 hem_idx = i; 4422 } 4423 4424 if (table->type == HEM_TYPE_SCCC) 4425 obj = mhop.l0_idx; 4426 4427 if (check_whether_last_step(hop_num, step_idx)) { 4428 hem = table->hem[hem_idx]; 4429 4430 ret = set_hem_to_hw(hr_dev, obj, hem->dma, table->type, step_idx); 4431 } else { 4432 if (step_idx == 0) 4433 bt_ba = table->bt_l0_dma_addr[i]; 4434 else if (step_idx == 1 && hop_num == 2) 4435 bt_ba = table->bt_l1_dma_addr[l1_idx]; 4436 4437 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx); 4438 } 4439 4440 return ret; 4441 } 4442 4443 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 4444 struct hns_roce_hem_table *table, 4445 int tag, u32 step_idx) 4446 { 4447 struct hns_roce_cmd_mailbox *mailbox; 4448 struct device *dev = hr_dev->dev; 4449 u8 cmd = 0xff; 4450 int ret; 4451 4452 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4453 return 0; 4454 4455 switch (table->type) { 4456 case HEM_TYPE_QPC: 4457 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0; 4458 break; 4459 case HEM_TYPE_MTPT: 4460 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0; 4461 break; 4462 case HEM_TYPE_CQC: 4463 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0; 4464 break; 4465 case HEM_TYPE_SRQC: 4466 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 4467 break; 4468 case HEM_TYPE_SCCC: 4469 case HEM_TYPE_QPC_TIMER: 4470 case HEM_TYPE_CQC_TIMER: 4471 case HEM_TYPE_GMV: 4472 return 0; 4473 default: 4474 dev_warn(dev, "table %u not to be destroyed by mailbox!\n", 4475 table->type); 4476 return 0; 4477 } 4478 4479 cmd += step_idx; 4480 4481 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4482 if (IS_ERR(mailbox)) 4483 return PTR_ERR(mailbox); 4484 4485 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag); 4486 4487 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4488 return ret; 4489 } 4490 4491 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 4492 struct hns_roce_v2_qp_context *context, 4493 struct hns_roce_v2_qp_context *qpc_mask, 4494 struct hns_roce_qp *hr_qp) 4495 { 4496 struct hns_roce_cmd_mailbox *mailbox; 4497 int qpc_size; 4498 int ret; 4499 4500 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4501 if (IS_ERR(mailbox)) 4502 return PTR_ERR(mailbox); 4503 4504 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */ 4505 qpc_size = hr_dev->caps.qpc_sz; 4506 memcpy(mailbox->buf, context, qpc_size); 4507 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size); 4508 4509 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 4510 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn); 4511 4512 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4513 4514 return ret; 4515 } 4516 4517 static void set_access_flags(struct hns_roce_qp *hr_qp, 4518 struct hns_roce_v2_qp_context *context, 4519 struct hns_roce_v2_qp_context *qpc_mask, 4520 const struct ib_qp_attr *attr, int attr_mask) 4521 { 4522 u8 dest_rd_atomic; 4523 u32 access_flags; 4524 4525 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 4526 attr->max_dest_rd_atomic : hr_qp->resp_depth; 4527 4528 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 4529 attr->qp_access_flags : hr_qp->atomic_rd_en; 4530 4531 if (!dest_rd_atomic) 4532 access_flags &= IB_ACCESS_REMOTE_WRITE; 4533 4534 hr_reg_write_bool(context, QPC_RRE, 4535 access_flags & IB_ACCESS_REMOTE_READ); 4536 hr_reg_clear(qpc_mask, QPC_RRE); 4537 4538 hr_reg_write_bool(context, QPC_RWE, 4539 access_flags & IB_ACCESS_REMOTE_WRITE); 4540 hr_reg_clear(qpc_mask, QPC_RWE); 4541 4542 hr_reg_write_bool(context, QPC_ATE, 4543 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4544 hr_reg_clear(qpc_mask, QPC_ATE); 4545 hr_reg_write_bool(context, QPC_EXT_ATE, 4546 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4547 hr_reg_clear(qpc_mask, QPC_EXT_ATE); 4548 } 4549 4550 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 4551 struct hns_roce_v2_qp_context *context) 4552 { 4553 hr_reg_write(context, QPC_SGE_SHIFT, 4554 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 4555 hr_qp->sge.sge_shift)); 4556 4557 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt)); 4558 4559 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt)); 4560 } 4561 4562 static inline int get_cqn(struct ib_cq *ib_cq) 4563 { 4564 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0; 4565 } 4566 4567 static inline int get_pdn(struct ib_pd *ib_pd) 4568 { 4569 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0; 4570 } 4571 4572 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 4573 struct hns_roce_v2_qp_context *context) 4574 { 4575 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4576 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4577 4578 /* 4579 * In v2 engine, software pass context and context mask to hardware 4580 * when modifying qp. If software need modify some fields in context, 4581 * we should set all bits of the relevant fields in context mask to 4582 * 0 at the same time, else set them to 0x1. 4583 */ 4584 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4585 4586 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4587 4588 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs)); 4589 4590 set_qpc_wqe_cnt(hr_qp, context); 4591 4592 /* No VLAN need to set 0xFFF */ 4593 hr_reg_write(context, QPC_VLAN_ID, 0xfff); 4594 4595 if (ibqp->qp_type == IB_QPT_XRC_TGT) { 4596 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); 4597 4598 hr_reg_enable(context, QPC_XRC_QP_TYPE); 4599 } 4600 4601 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 4602 hr_reg_enable(context, QPC_RQ_RECORD_EN); 4603 4604 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 4605 hr_reg_enable(context, QPC_OWNER_MODE); 4606 4607 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L, 4608 lower_32_bits(hr_qp->rdb.dma) >> 1); 4609 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H, 4610 upper_32_bits(hr_qp->rdb.dma)); 4611 4612 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4613 4614 if (ibqp->srq) { 4615 hr_reg_enable(context, QPC_SRQ_EN); 4616 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4617 } 4618 4619 hr_reg_enable(context, QPC_FRE); 4620 4621 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4622 4623 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ) 4624 return; 4625 4626 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 4627 hr_reg_enable(&context->ext, QPCEX_STASH); 4628 } 4629 4630 static void modify_qp_init_to_init(struct ib_qp *ibqp, 4631 struct hns_roce_v2_qp_context *context, 4632 struct hns_roce_v2_qp_context *qpc_mask) 4633 { 4634 /* 4635 * In v2 engine, software pass context and context mask to hardware 4636 * when modifying qp. If software need modify some fields in context, 4637 * we should set all bits of the relevant fields in context mask to 4638 * 0 at the same time, else set them to 0x1. 4639 */ 4640 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4641 hr_reg_clear(qpc_mask, QPC_TST); 4642 4643 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4644 hr_reg_clear(qpc_mask, QPC_PD); 4645 4646 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4647 hr_reg_clear(qpc_mask, QPC_RX_CQN); 4648 4649 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4650 hr_reg_clear(qpc_mask, QPC_TX_CQN); 4651 4652 if (ibqp->srq) { 4653 hr_reg_enable(context, QPC_SRQ_EN); 4654 hr_reg_clear(qpc_mask, QPC_SRQ_EN); 4655 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4656 hr_reg_clear(qpc_mask, QPC_SRQN); 4657 } 4658 } 4659 4660 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 4661 struct hns_roce_qp *hr_qp, 4662 struct hns_roce_v2_qp_context *context, 4663 struct hns_roce_v2_qp_context *qpc_mask) 4664 { 4665 u64 mtts[MTT_MIN_COUNT] = { 0 }; 4666 u64 wqe_sge_ba; 4667 int ret; 4668 4669 /* Search qp buf's mtts */ 4670 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, 4671 MTT_MIN_COUNT); 4672 if (hr_qp->rq.wqe_cnt && ret) { 4673 ibdev_err(&hr_dev->ib_dev, 4674 "failed to find QP(0x%lx) RQ WQE buf, ret = %d.\n", 4675 hr_qp->qpn, ret); 4676 return ret; 4677 } 4678 4679 wqe_sge_ba = hns_roce_get_mtr_ba(&hr_qp->mtr); 4680 4681 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 4682 qpc_mask->wqe_sge_ba = 0; 4683 4684 /* 4685 * In v2 engine, software pass context and context mask to hardware 4686 * when modifying qp. If software need modify some fields in context, 4687 * we should set all bits of the relevant fields in context mask to 4688 * 0 at the same time, else set them to 0x1. 4689 */ 4690 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3)); 4691 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H); 4692 4693 hr_reg_write(context, QPC_SQ_HOP_NUM, 4694 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 4695 hr_qp->sq.wqe_cnt)); 4696 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM); 4697 4698 hr_reg_write(context, QPC_SGE_HOP_NUM, 4699 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 4700 hr_qp->sge.sge_cnt)); 4701 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM); 4702 4703 hr_reg_write(context, QPC_RQ_HOP_NUM, 4704 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 4705 hr_qp->rq.wqe_cnt)); 4706 4707 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM); 4708 4709 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ, 4710 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 4711 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ); 4712 4713 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ, 4714 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 4715 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ); 4716 4717 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 4718 qpc_mask->rq_cur_blk_addr = 0; 4719 4720 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H, 4721 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 4722 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H); 4723 4724 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4725 context->rq_nxt_blk_addr = 4726 cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 4727 qpc_mask->rq_nxt_blk_addr = 0; 4728 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H, 4729 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 4730 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H); 4731 } 4732 4733 return 0; 4734 } 4735 4736 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 4737 struct hns_roce_qp *hr_qp, 4738 struct hns_roce_v2_qp_context *context, 4739 struct hns_roce_v2_qp_context *qpc_mask) 4740 { 4741 struct ib_device *ibdev = &hr_dev->ib_dev; 4742 u64 sge_cur_blk = 0; 4743 u64 sq_cur_blk = 0; 4744 int ret; 4745 4746 /* search qp buf's mtts */ 4747 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->sq.offset, 4748 &sq_cur_blk, 1); 4749 if (ret) { 4750 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ WQE buf, ret = %d.\n", 4751 hr_qp->qpn, ret); 4752 return ret; 4753 } 4754 if (hr_qp->sge.sge_cnt > 0) { 4755 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 4756 hr_qp->sge.offset, &sge_cur_blk, 1); 4757 if (ret) { 4758 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf, ret = %d.\n", 4759 hr_qp->qpn, ret); 4760 return ret; 4761 } 4762 } 4763 4764 /* 4765 * In v2 engine, software pass context and context mask to hardware 4766 * when modifying qp. If software need modify some fields in context, 4767 * we should set all bits of the relevant fields in context mask to 4768 * 0 at the same time, else set them to 0x1. 4769 */ 4770 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L, 4771 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4772 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H, 4773 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4774 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L); 4775 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H); 4776 4777 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L, 4778 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4779 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H, 4780 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4781 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L); 4782 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H); 4783 4784 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L, 4785 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4786 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H, 4787 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4788 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L); 4789 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H); 4790 4791 return 0; 4792 } 4793 4794 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, 4795 const struct ib_qp_attr *attr) 4796 { 4797 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 4798 return IB_MTU_4096; 4799 4800 return attr->path_mtu; 4801 } 4802 4803 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 4804 const struct ib_qp_attr *attr, int attr_mask, 4805 struct hns_roce_v2_qp_context *context, 4806 struct hns_roce_v2_qp_context *qpc_mask, 4807 struct ib_udata *udata) 4808 { 4809 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata, 4810 struct hns_roce_ucontext, ibucontext); 4811 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4812 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4813 struct ib_device *ibdev = &hr_dev->ib_dev; 4814 dma_addr_t trrl_ba; 4815 dma_addr_t irrl_ba; 4816 enum ib_mtu ib_mtu; 4817 u8 ack_req_freq; 4818 const u8 *smac; 4819 int lp_msg_len; 4820 u8 lp_pktn_ini; 4821 u64 *mtts; 4822 u8 *dmac; 4823 u32 port; 4824 int mtu; 4825 int ret; 4826 4827 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 4828 if (ret) { 4829 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 4830 return ret; 4831 } 4832 4833 /* Search IRRL's mtts */ 4834 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 4835 hr_qp->qpn, &irrl_ba); 4836 if (!mtts) { 4837 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 4838 return -EINVAL; 4839 } 4840 4841 /* Search TRRL's mtts */ 4842 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 4843 hr_qp->qpn, &trrl_ba); 4844 if (!mtts) { 4845 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 4846 return -EINVAL; 4847 } 4848 4849 if (attr_mask & IB_QP_ALT_PATH) { 4850 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 4851 attr_mask); 4852 return -EINVAL; 4853 } 4854 4855 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> QPC_TRRL_BA_L_S); 4856 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L); 4857 context->trrl_ba = cpu_to_le32(trrl_ba >> QPC_TRRL_BA_M_S); 4858 qpc_mask->trrl_ba = 0; 4859 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> QPC_TRRL_BA_H_S); 4860 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H); 4861 4862 context->irrl_ba = cpu_to_le32(irrl_ba >> QPC_IRRL_BA_L_S); 4863 qpc_mask->irrl_ba = 0; 4864 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> QPC_IRRL_BA_H_S); 4865 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H); 4866 4867 hr_reg_enable(context, QPC_RMT_E2E); 4868 hr_reg_clear(qpc_mask, QPC_RMT_E2E); 4869 4870 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits); 4871 hr_reg_clear(qpc_mask, QPC_SIG_TYPE); 4872 4873 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4874 4875 smac = (const u8 *)hr_dev->dev_addr[port]; 4876 dmac = (u8 *)attr->ah_attr.roce.dmac; 4877 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4878 if (ether_addr_equal_unaligned(dmac, smac) || 4879 hr_dev->loop_idc == 0x1) { 4880 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc); 4881 hr_reg_clear(qpc_mask, QPC_LBI); 4882 } 4883 4884 if (attr_mask & IB_QP_DEST_QPN) { 4885 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num); 4886 hr_reg_clear(qpc_mask, QPC_DQPN); 4887 } 4888 4889 memcpy(&context->dmac, dmac, sizeof(u32)); 4890 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4]))); 4891 qpc_mask->dmac = 0; 4892 hr_reg_clear(qpc_mask, QPC_DMAC_H); 4893 4894 ib_mtu = get_mtu(ibqp, attr); 4895 hr_qp->path_mtu = ib_mtu; 4896 4897 mtu = ib_mtu_enum_to_int(ib_mtu); 4898 if (WARN_ON(mtu <= 0)) 4899 return -EINVAL; 4900 #define MIN_LP_MSG_LEN 1024 4901 /* mtu * (2 ^ lp_pktn_ini) should be in the range of 1024 to mtu */ 4902 lp_msg_len = max(mtu, MIN_LP_MSG_LEN); 4903 lp_pktn_ini = ilog2(lp_msg_len / mtu); 4904 4905 if (attr_mask & IB_QP_PATH_MTU) { 4906 hr_reg_write(context, QPC_MTU, ib_mtu); 4907 hr_reg_clear(qpc_mask, QPC_MTU); 4908 } 4909 4910 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini); 4911 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI); 4912 4913 /* 4914 * There are several constraints for ACK_REQ_FREQ: 4915 * 1. mtu * (2 ^ ACK_REQ_FREQ) should not be too large, otherwise 4916 * it may cause some unexpected retries when sending large 4917 * payload. 4918 * 2. ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI. 4919 * 3. ACK_REQ_FREQ must be equal to LP_PKTN_INI when using LDCP 4920 * or HC3 congestion control algorithm. 4921 */ 4922 if (hr_qp->cong_type == CONG_TYPE_LDCP || 4923 hr_qp->cong_type == CONG_TYPE_HC3 || 4924 hr_dev->caps.max_ack_req_msg_len < lp_msg_len) 4925 ack_req_freq = lp_pktn_ini; 4926 else 4927 ack_req_freq = ilog2(hr_dev->caps.max_ack_req_msg_len / mtu); 4928 hr_reg_write(context, QPC_ACK_REQ_FREQ, ack_req_freq); 4929 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ); 4930 4931 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR); 4932 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN); 4933 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE); 4934 4935 context->rq_rnr_timer = 0; 4936 qpc_mask->rq_rnr_timer = 0; 4937 4938 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX); 4939 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX); 4940 4941 #define MAX_LP_SGEN 3 4942 /* rocee send 2^lp_sgen_ini segs every time */ 4943 hr_reg_write(context, QPC_LP_SGEN_INI, MAX_LP_SGEN); 4944 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI); 4945 4946 if (udata && ibqp->qp_type == IB_QPT_RC && 4947 (uctx->config & HNS_ROCE_RQ_INLINE_FLAGS)) { 4948 hr_reg_write_bool(context, QPC_RQIE, 4949 hr_dev->caps.flags & 4950 HNS_ROCE_CAP_FLAG_RQ_INLINE); 4951 hr_reg_clear(qpc_mask, QPC_RQIE); 4952 } 4953 4954 if (udata && 4955 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_XRC_TGT) && 4956 (uctx->config & HNS_ROCE_CQE_INLINE_FLAGS)) { 4957 hr_reg_write_bool(context, QPC_CQEIE, 4958 hr_dev->caps.flags & 4959 HNS_ROCE_CAP_FLAG_CQE_INLINE); 4960 hr_reg_clear(qpc_mask, QPC_CQEIE); 4961 4962 hr_reg_write(context, QPC_CQEIS, 0); 4963 hr_reg_clear(qpc_mask, QPC_CQEIS); 4964 } 4965 4966 return 0; 4967 } 4968 4969 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, int attr_mask, 4970 struct hns_roce_v2_qp_context *context, 4971 struct hns_roce_v2_qp_context *qpc_mask) 4972 { 4973 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4974 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4975 struct ib_device *ibdev = &hr_dev->ib_dev; 4976 int ret; 4977 4978 /* Not support alternate path and path migration */ 4979 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4980 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4981 return -EINVAL; 4982 } 4983 4984 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4985 if (ret) { 4986 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret); 4987 return ret; 4988 } 4989 4990 /* 4991 * Set some fields in context to zero, Because the default values 4992 * of all fields in context are zero, we need not set them to 0 again. 4993 * but we should set the relevant fields of context mask to 0. 4994 */ 4995 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX); 4996 4997 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN); 4998 4999 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE); 5000 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD); 5001 hr_reg_clear(qpc_mask, QPC_IRRL_PSN); 5002 5003 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL); 5004 5005 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN); 5006 5007 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG); 5008 5009 hr_reg_clear(qpc_mask, QPC_CHECK_FLG); 5010 5011 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD); 5012 5013 return 0; 5014 } 5015 5016 static int alloc_dip_entry(struct xarray *dip_xa, u32 qpn) 5017 { 5018 struct hns_roce_dip *hr_dip; 5019 int ret; 5020 5021 hr_dip = xa_load(dip_xa, qpn); 5022 if (hr_dip) 5023 return 0; 5024 5025 hr_dip = kzalloc_obj(*hr_dip); 5026 if (!hr_dip) 5027 return -ENOMEM; 5028 5029 ret = xa_err(xa_store(dip_xa, qpn, hr_dip, GFP_KERNEL)); 5030 if (ret) 5031 kfree(hr_dip); 5032 5033 return ret; 5034 } 5035 5036 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 5037 u32 *dip_idx) 5038 { 5039 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 5040 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5041 struct xarray *dip_xa = &hr_dev->qp_table.dip_xa; 5042 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5043 struct hns_roce_dip *hr_dip; 5044 unsigned long idx; 5045 int ret = 0; 5046 5047 ret = alloc_dip_entry(dip_xa, ibqp->qp_num); 5048 if (ret) 5049 return ret; 5050 5051 xa_lock(dip_xa); 5052 5053 xa_for_each(dip_xa, idx, hr_dip) { 5054 if (hr_dip->qp_cnt && 5055 !memcmp(grh->dgid.raw, hr_dip->dgid, GID_LEN_V2)) { 5056 *dip_idx = hr_dip->dip_idx; 5057 hr_dip->qp_cnt++; 5058 hr_qp->dip = hr_dip; 5059 goto out; 5060 } 5061 } 5062 5063 /* If no dgid is found, a new dip and a mapping between dgid and 5064 * dip_idx will be created. 5065 */ 5066 xa_for_each(dip_xa, idx, hr_dip) { 5067 if (hr_dip->qp_cnt) 5068 continue; 5069 5070 *dip_idx = idx; 5071 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 5072 hr_dip->dip_idx = idx; 5073 hr_dip->qp_cnt++; 5074 hr_qp->dip = hr_dip; 5075 break; 5076 } 5077 5078 /* This should never happen. */ 5079 if (WARN_ON_ONCE(!hr_qp->dip)) 5080 ret = -ENOSPC; 5081 5082 out: 5083 xa_unlock(dip_xa); 5084 return ret; 5085 } 5086 5087 enum { 5088 CONG_DCQCN, 5089 CONG_WINDOW, 5090 }; 5091 5092 enum { 5093 UNSUPPORT_CONG_LEVEL, 5094 SUPPORT_CONG_LEVEL, 5095 }; 5096 5097 enum { 5098 CONG_LDCP, 5099 CONG_HC3, 5100 }; 5101 5102 enum { 5103 DIP_INVALID, 5104 DIP_VALID, 5105 }; 5106 5107 enum { 5108 WND_LIMIT, 5109 WND_UNLIMIT, 5110 }; 5111 5112 static int check_cong_type(struct ib_qp *ibqp, 5113 struct hns_roce_congestion_algorithm *cong_alg) 5114 { 5115 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5116 5117 /* different congestion types match different configurations */ 5118 switch (hr_qp->cong_type) { 5119 case CONG_TYPE_DCQCN: 5120 cong_alg->alg_sel = CONG_DCQCN; 5121 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 5122 cong_alg->dip_vld = DIP_INVALID; 5123 cong_alg->wnd_mode_sel = WND_LIMIT; 5124 break; 5125 case CONG_TYPE_LDCP: 5126 cong_alg->alg_sel = CONG_WINDOW; 5127 cong_alg->alg_sub_sel = CONG_LDCP; 5128 cong_alg->dip_vld = DIP_INVALID; 5129 cong_alg->wnd_mode_sel = WND_UNLIMIT; 5130 break; 5131 case CONG_TYPE_HC3: 5132 cong_alg->alg_sel = CONG_WINDOW; 5133 cong_alg->alg_sub_sel = CONG_HC3; 5134 cong_alg->dip_vld = DIP_INVALID; 5135 cong_alg->wnd_mode_sel = WND_LIMIT; 5136 break; 5137 case CONG_TYPE_DIP: 5138 cong_alg->alg_sel = CONG_DCQCN; 5139 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 5140 cong_alg->dip_vld = DIP_VALID; 5141 cong_alg->wnd_mode_sel = WND_LIMIT; 5142 break; 5143 default: 5144 hr_qp->cong_type = CONG_TYPE_DCQCN; 5145 cong_alg->alg_sel = CONG_DCQCN; 5146 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 5147 cong_alg->dip_vld = DIP_INVALID; 5148 cong_alg->wnd_mode_sel = WND_LIMIT; 5149 break; 5150 } 5151 5152 return 0; 5153 } 5154 5155 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 5156 struct hns_roce_v2_qp_context *context, 5157 struct hns_roce_v2_qp_context *qpc_mask) 5158 { 5159 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 5160 struct hns_roce_congestion_algorithm cong_field; 5161 struct ib_device *ibdev = ibqp->device; 5162 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5163 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5164 u32 dip_idx = 0; 5165 int ret; 5166 5167 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 || 5168 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE) 5169 return 0; 5170 5171 ret = check_cong_type(ibqp, &cong_field); 5172 if (ret) 5173 return ret; 5174 5175 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id + 5176 hr_qp->cong_type * HNS_ROCE_CONG_SIZE); 5177 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID); 5178 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel); 5179 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL); 5180 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL, 5181 cong_field.alg_sub_sel); 5182 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL); 5183 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld); 5184 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD); 5185 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN, 5186 cong_field.wnd_mode_sel); 5187 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN); 5188 5189 /* if dip is disabled, there is no need to set dip idx */ 5190 if (cong_field.dip_vld == 0) 5191 return 0; 5192 5193 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx); 5194 if (ret) { 5195 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret); 5196 return ret; 5197 } 5198 5199 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx); 5200 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0); 5201 5202 return 0; 5203 } 5204 5205 static int hns_roce_hw_v2_get_dscp(struct hns_roce_dev *hr_dev, u8 dscp, 5206 u8 *tc_mode, u8 *priority) 5207 { 5208 struct hns_roce_v2_priv *priv = hr_dev->priv; 5209 struct hnae3_handle *handle = priv->handle; 5210 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 5211 5212 if (!ops->get_dscp_prio) 5213 return -EOPNOTSUPP; 5214 5215 return ops->get_dscp_prio(handle, dscp, tc_mode, priority); 5216 } 5217 5218 bool check_sl_valid(struct hns_roce_dev *hr_dev, u8 sl) 5219 { 5220 u32 max_sl; 5221 5222 max_sl = min_t(u32, MAX_SERVICE_LEVEL, hr_dev->caps.sl_num - 1); 5223 if (unlikely(sl > max_sl)) { 5224 ibdev_err_ratelimited(&hr_dev->ib_dev, 5225 "failed to set SL(%u). Shouldn't be larger than %u.\n", 5226 sl, max_sl); 5227 return false; 5228 } 5229 5230 return true; 5231 } 5232 5233 static int hns_roce_set_sl(struct ib_qp *ibqp, 5234 const struct ib_qp_attr *attr, 5235 struct hns_roce_v2_qp_context *context, 5236 struct hns_roce_v2_qp_context *qpc_mask) 5237 { 5238 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 5239 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5240 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5241 struct ib_device *ibdev = &hr_dev->ib_dev; 5242 int ret; 5243 5244 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 5245 5246 if (grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 5247 ret = hns_roce_hw_v2_get_dscp(hr_dev, 5248 get_tclass(&attr->ah_attr.grh), 5249 &hr_qp->tc_mode, &hr_qp->priority); 5250 if (ret && ret != -EOPNOTSUPP) { 5251 ibdev_err_ratelimited(ibdev, 5252 "failed to get dscp, ret = %d.\n", 5253 ret); 5254 return ret; 5255 } 5256 5257 if (hr_qp->tc_mode == HNAE3_TC_MAP_MODE_DSCP) 5258 hr_qp->sl = hr_qp->priority; 5259 } 5260 5261 if (!check_sl_valid(hr_dev, hr_qp->sl)) 5262 return -EINVAL; 5263 5264 hr_reg_write(context, QPC_SL, hr_qp->sl); 5265 hr_reg_clear(qpc_mask, QPC_SL); 5266 5267 return 0; 5268 } 5269 5270 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 5271 const struct ib_qp_attr *attr, 5272 int attr_mask, 5273 struct hns_roce_v2_qp_context *context, 5274 struct hns_roce_v2_qp_context *qpc_mask) 5275 { 5276 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 5277 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5278 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5279 struct ib_device *ibdev = &hr_dev->ib_dev; 5280 const struct ib_gid_attr *gid_attr = NULL; 5281 u8 sl = rdma_ah_get_sl(&attr->ah_attr); 5282 int is_roce_protocol; 5283 u16 vlan_id = 0xffff; 5284 bool is_udp = false; 5285 u8 ib_port; 5286 u8 hr_port; 5287 int ret; 5288 5289 /* 5290 * If free_mr_en of qp is set, it means that this qp comes from 5291 * free mr. This qp will perform the loopback operation. 5292 * In the loopback scenario, only sl needs to be set. 5293 */ 5294 if (hr_qp->free_mr_en) { 5295 if (!check_sl_valid(hr_dev, sl)) 5296 return -EINVAL; 5297 hr_reg_write(context, QPC_SL, sl); 5298 hr_reg_clear(qpc_mask, QPC_SL); 5299 hr_qp->sl = sl; 5300 return 0; 5301 } 5302 5303 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 5304 hr_port = ib_port - 1; 5305 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 5306 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 5307 5308 if (is_roce_protocol) { 5309 gid_attr = attr->ah_attr.grh.sgid_attr; 5310 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 5311 if (ret) 5312 return ret; 5313 5314 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP); 5315 } 5316 5317 /* Only HIP08 needs to set the vlan_en bits in QPC */ 5318 if (vlan_id < VLAN_N_VID && 5319 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5320 hr_reg_enable(context, QPC_RQ_VLAN_EN); 5321 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN); 5322 hr_reg_enable(context, QPC_SQ_VLAN_EN); 5323 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN); 5324 } 5325 5326 hr_reg_write(context, QPC_VLAN_ID, vlan_id); 5327 hr_reg_clear(qpc_mask, QPC_VLAN_ID); 5328 5329 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 5330 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 5331 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 5332 return -EINVAL; 5333 } 5334 5335 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 5336 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 5337 return -EINVAL; 5338 } 5339 5340 hr_reg_write(context, QPC_UDPSPN, 5341 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num, 5342 attr->dest_qp_num) : 5343 0); 5344 5345 hr_reg_clear(qpc_mask, QPC_UDPSPN); 5346 5347 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index); 5348 5349 hr_reg_clear(qpc_mask, QPC_GMV_IDX); 5350 5351 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit); 5352 hr_reg_clear(qpc_mask, QPC_HOPLIMIT); 5353 5354 ret = fill_cong_field(ibqp, attr, context, qpc_mask); 5355 if (ret) 5356 return ret; 5357 5358 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh)); 5359 hr_reg_clear(qpc_mask, QPC_TC); 5360 5361 hr_reg_write(context, QPC_FL, grh->flow_label); 5362 hr_reg_clear(qpc_mask, QPC_FL); 5363 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 5364 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 5365 5366 return hns_roce_set_sl(ibqp, attr, context, qpc_mask); 5367 } 5368 5369 static bool check_qp_state(enum ib_qp_state cur_state, 5370 enum ib_qp_state new_state) 5371 { 5372 static const bool sm[][IB_QPS_ERR + 1] = { 5373 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 5374 [IB_QPS_INIT] = true }, 5375 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 5376 [IB_QPS_INIT] = true, 5377 [IB_QPS_RTR] = true, 5378 [IB_QPS_ERR] = true }, 5379 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 5380 [IB_QPS_RTS] = true, 5381 [IB_QPS_ERR] = true }, 5382 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, 5383 [IB_QPS_RTS] = true, 5384 [IB_QPS_ERR] = true }, 5385 [IB_QPS_SQD] = {}, 5386 [IB_QPS_SQE] = {}, 5387 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, 5388 [IB_QPS_ERR] = true } 5389 }; 5390 5391 return sm[cur_state][new_state]; 5392 } 5393 5394 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 5395 const struct ib_qp_attr *attr, 5396 int attr_mask, 5397 enum ib_qp_state cur_state, 5398 enum ib_qp_state new_state, 5399 struct hns_roce_v2_qp_context *context, 5400 struct hns_roce_v2_qp_context *qpc_mask, 5401 struct ib_udata *udata) 5402 { 5403 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5404 int ret = 0; 5405 5406 if (!check_qp_state(cur_state, new_state)) 5407 return -EINVAL; 5408 5409 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 5410 memset(qpc_mask, 0, hr_dev->caps.qpc_sz); 5411 modify_qp_reset_to_init(ibqp, context); 5412 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 5413 modify_qp_init_to_init(ibqp, context, qpc_mask); 5414 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 5415 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 5416 qpc_mask, udata); 5417 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 5418 ret = modify_qp_rtr_to_rts(ibqp, attr_mask, context, qpc_mask); 5419 } 5420 5421 return ret; 5422 } 5423 5424 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout) 5425 { 5426 #define QP_ACK_TIMEOUT_MAX_HIP08 20 5427 #define QP_ACK_TIMEOUT_MAX 31 5428 5429 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5430 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) { 5431 ibdev_warn(&hr_dev->ib_dev, 5432 "local ACK timeout shall be 0 to 20.\n"); 5433 return false; 5434 } 5435 *timeout += HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5436 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) { 5437 if (*timeout > QP_ACK_TIMEOUT_MAX) { 5438 ibdev_warn(&hr_dev->ib_dev, 5439 "local ACK timeout shall be 0 to 31.\n"); 5440 return false; 5441 } 5442 } 5443 5444 return true; 5445 } 5446 5447 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 5448 const struct ib_qp_attr *attr, 5449 int attr_mask, 5450 struct hns_roce_v2_qp_context *context, 5451 struct hns_roce_v2_qp_context *qpc_mask) 5452 { 5453 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5454 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5455 int ret = 0; 5456 u8 timeout; 5457 5458 if (attr_mask & IB_QP_AV) { 5459 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 5460 qpc_mask); 5461 if (ret) 5462 return ret; 5463 } 5464 5465 if (attr_mask & IB_QP_TIMEOUT) { 5466 timeout = attr->timeout; 5467 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) { 5468 hr_reg_write(context, QPC_AT, timeout); 5469 hr_reg_clear(qpc_mask, QPC_AT); 5470 } 5471 } 5472 5473 if (attr_mask & IB_QP_RETRY_CNT) { 5474 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt); 5475 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT); 5476 5477 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt); 5478 hr_reg_clear(qpc_mask, QPC_RETRY_CNT); 5479 } 5480 5481 if (attr_mask & IB_QP_RNR_RETRY) { 5482 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry); 5483 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT); 5484 5485 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry); 5486 hr_reg_clear(qpc_mask, QPC_RNR_CNT); 5487 } 5488 5489 if (attr_mask & IB_QP_SQ_PSN) { 5490 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn); 5491 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN); 5492 5493 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn); 5494 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN); 5495 5496 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn); 5497 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L); 5498 5499 hr_reg_write(context, QPC_RETRY_MSG_PSN_H, 5500 attr->sq_psn >> RETRY_MSG_PSN_SHIFT); 5501 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H); 5502 5503 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn); 5504 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN); 5505 5506 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn); 5507 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN); 5508 } 5509 5510 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 5511 attr->max_dest_rd_atomic) { 5512 hr_reg_write(context, QPC_RR_MAX, 5513 fls(attr->max_dest_rd_atomic - 1)); 5514 hr_reg_clear(qpc_mask, QPC_RR_MAX); 5515 } 5516 5517 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 5518 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1)); 5519 hr_reg_clear(qpc_mask, QPC_SR_MAX); 5520 } 5521 5522 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 5523 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 5524 5525 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 5526 hr_reg_write(context, QPC_MIN_RNR_TIME, 5527 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ? 5528 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer); 5529 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME); 5530 } 5531 5532 if (attr_mask & IB_QP_RQ_PSN) { 5533 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn); 5534 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN); 5535 5536 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1); 5537 hr_reg_clear(qpc_mask, QPC_RAQ_PSN); 5538 } 5539 5540 if (attr_mask & IB_QP_QKEY) { 5541 context->qkey_xrcd = cpu_to_le32(attr->qkey); 5542 qpc_mask->qkey_xrcd = 0; 5543 hr_qp->qkey = attr->qkey; 5544 } 5545 5546 return ret; 5547 } 5548 5549 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 5550 const struct ib_qp_attr *attr, 5551 int attr_mask) 5552 { 5553 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5554 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5555 5556 if (attr_mask & IB_QP_ACCESS_FLAGS) 5557 hr_qp->atomic_rd_en = attr->qp_access_flags; 5558 5559 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 5560 hr_qp->resp_depth = attr->max_dest_rd_atomic; 5561 if (attr_mask & IB_QP_PORT) { 5562 hr_qp->port = attr->port_num - 1; 5563 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 5564 } 5565 } 5566 5567 static void clear_qp(struct hns_roce_qp *hr_qp) 5568 { 5569 struct ib_qp *ibqp = &hr_qp->ibqp; 5570 5571 if (ibqp->send_cq) 5572 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 5573 hr_qp->qpn, NULL); 5574 5575 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq) 5576 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), 5577 hr_qp->qpn, ibqp->srq ? 5578 to_hr_srq(ibqp->srq) : NULL); 5579 5580 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 5581 *hr_qp->rdb.db_record = 0; 5582 5583 hr_qp->rq.head = 0; 5584 hr_qp->rq.tail = 0; 5585 hr_qp->sq.head = 0; 5586 hr_qp->sq.tail = 0; 5587 hr_qp->next_sge = 0; 5588 } 5589 5590 static void v2_set_flushed_fields(struct ib_qp *ibqp, 5591 struct hns_roce_v2_qp_context *context, 5592 struct hns_roce_v2_qp_context *qpc_mask) 5593 { 5594 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5595 unsigned long sq_flag = 0; 5596 unsigned long rq_flag = 0; 5597 5598 if (ibqp->qp_type == IB_QPT_XRC_TGT) 5599 return; 5600 5601 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 5602 trace_hns_sq_flush_cqe(hr_qp->qpn, hr_qp->sq.head, TRACE_SQ); 5603 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head); 5604 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX); 5605 hr_qp->state = IB_QPS_ERR; 5606 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 5607 5608 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */ 5609 return; 5610 5611 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 5612 trace_hns_rq_flush_cqe(hr_qp->qpn, hr_qp->rq.head, TRACE_RQ); 5613 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head); 5614 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX); 5615 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 5616 } 5617 5618 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 5619 const struct ib_qp_attr *attr, 5620 int attr_mask, enum ib_qp_state cur_state, 5621 enum ib_qp_state new_state, struct ib_udata *udata) 5622 { 5623 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5624 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5625 struct hns_roce_v2_qp_context *context; 5626 struct hns_roce_v2_qp_context *qpc_mask; 5627 struct ib_device *ibdev = &hr_dev->ib_dev; 5628 int ret = -ENOMEM; 5629 5630 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 5631 return -EOPNOTSUPP; 5632 5633 /* 5634 * In v2 engine, software pass context and context mask to hardware 5635 * when modifying qp. If software need modify some fields in context, 5636 * we should set all bits of the relevant fields in context mask to 5637 * 0 at the same time, else set them to 0x1. 5638 */ 5639 context = kvzalloc_obj(*context); 5640 qpc_mask = kvzalloc_obj(*qpc_mask); 5641 if (!context || !qpc_mask) 5642 goto out; 5643 5644 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz); 5645 5646 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 5647 new_state, context, qpc_mask, udata); 5648 if (ret) 5649 goto out; 5650 5651 /* When QP state is err, SQ and RQ WQE should be flushed */ 5652 if (new_state == IB_QPS_ERR) 5653 v2_set_flushed_fields(ibqp, context, qpc_mask); 5654 5655 /* Configure the optional fields */ 5656 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 5657 qpc_mask); 5658 if (ret) 5659 goto out; 5660 5661 hr_reg_write_bool(context, QPC_INV_CREDIT, 5662 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC || 5663 ibqp->srq); 5664 hr_reg_clear(qpc_mask, QPC_INV_CREDIT); 5665 5666 /* Every status migrate must change state */ 5667 hr_reg_write(context, QPC_QP_ST, new_state); 5668 hr_reg_clear(qpc_mask, QPC_QP_ST); 5669 5670 /* SW pass context to HW */ 5671 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp); 5672 if (ret) { 5673 ibdev_err_ratelimited(ibdev, "failed to modify QP, ret = %d.\n", ret); 5674 goto out; 5675 } 5676 5677 hr_qp->state = new_state; 5678 5679 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 5680 5681 if (new_state == IB_QPS_RESET && !ibqp->uobject) 5682 clear_qp(hr_qp); 5683 5684 out: 5685 kvfree(qpc_mask); 5686 kvfree(context); 5687 return ret; 5688 } 5689 5690 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 5691 { 5692 static const enum ib_qp_state map[] = { 5693 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 5694 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 5695 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 5696 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 5697 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 5698 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 5699 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 5700 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 5701 }; 5702 5703 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 5704 } 5705 5706 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn, 5707 void *buffer) 5708 { 5709 struct hns_roce_cmd_mailbox *mailbox; 5710 int ret; 5711 5712 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5713 if (IS_ERR(mailbox)) 5714 return PTR_ERR(mailbox); 5715 5716 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC, 5717 qpn); 5718 if (ret) 5719 goto out; 5720 5721 memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz); 5722 5723 out: 5724 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5725 return ret; 5726 } 5727 5728 static int hns_roce_v2_query_srqc(struct hns_roce_dev *hr_dev, u32 srqn, 5729 void *buffer) 5730 { 5731 struct hns_roce_srq_context *context; 5732 struct hns_roce_cmd_mailbox *mailbox; 5733 int ret; 5734 5735 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5736 if (IS_ERR(mailbox)) 5737 return PTR_ERR(mailbox); 5738 5739 context = mailbox->buf; 5740 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SRQC, 5741 srqn); 5742 if (ret) 5743 goto out; 5744 5745 memcpy(buffer, context, sizeof(*context)); 5746 5747 out: 5748 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5749 return ret; 5750 } 5751 5752 static int hns_roce_v2_query_sccc(struct hns_roce_dev *hr_dev, u32 sccn, 5753 void *buffer) 5754 { 5755 struct hns_roce_v2_scc_context *context; 5756 struct hns_roce_cmd_mailbox *mailbox; 5757 int ret; 5758 5759 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5760 if (IS_ERR(mailbox)) 5761 return PTR_ERR(mailbox); 5762 5763 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SCCC, 5764 sccn); 5765 if (ret) 5766 goto out; 5767 5768 context = mailbox->buf; 5769 memcpy(buffer, context, sizeof(*context)); 5770 5771 out: 5772 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5773 return ret; 5774 } 5775 5776 static u8 get_qp_timeout_attr(struct hns_roce_dev *hr_dev, 5777 struct hns_roce_v2_qp_context *context) 5778 { 5779 u8 timeout; 5780 5781 timeout = (u8)hr_reg_read(context, QPC_AT); 5782 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 5783 timeout -= HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5784 5785 return timeout; 5786 } 5787 5788 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5789 int qp_attr_mask, 5790 struct ib_qp_init_attr *qp_init_attr) 5791 { 5792 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5793 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5794 struct hns_roce_v2_qp_context context = {}; 5795 struct ib_device *ibdev = &hr_dev->ib_dev; 5796 int tmp_qp_state; 5797 int state; 5798 int ret; 5799 5800 memset(qp_attr, 0, sizeof(*qp_attr)); 5801 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5802 5803 mutex_lock(&hr_qp->mutex); 5804 5805 if (hr_qp->state == IB_QPS_RESET) { 5806 qp_attr->qp_state = IB_QPS_RESET; 5807 ret = 0; 5808 goto done; 5809 } 5810 5811 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context); 5812 if (ret) { 5813 ibdev_err_ratelimited(ibdev, 5814 "failed to query QPC, ret = %d.\n", 5815 ret); 5816 ret = -EINVAL; 5817 goto out; 5818 } 5819 5820 state = hr_reg_read(&context, QPC_QP_ST); 5821 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 5822 if (tmp_qp_state == -1) { 5823 ibdev_err_ratelimited(ibdev, "Illegal ib_qp_state\n"); 5824 ret = -EINVAL; 5825 goto out; 5826 } 5827 hr_qp->state = (u8)tmp_qp_state; 5828 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 5829 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU); 5830 qp_attr->path_mig_state = IB_MIG_ARMED; 5831 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 5832 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 5833 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 5834 5835 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN); 5836 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN); 5837 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN); 5838 qp_attr->qp_access_flags = 5839 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) | 5840 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) | 5841 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S); 5842 5843 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 5844 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5845 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 5846 struct ib_global_route *grh = 5847 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 5848 5849 rdma_ah_set_sl(&qp_attr->ah_attr, 5850 hr_reg_read(&context, QPC_SL)); 5851 rdma_ah_set_port_num(&qp_attr->ah_attr, hr_qp->port + 1); 5852 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH); 5853 grh->flow_label = hr_reg_read(&context, QPC_FL); 5854 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX); 5855 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT); 5856 grh->traffic_class = hr_reg_read(&context, QPC_TC); 5857 5858 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 5859 } 5860 5861 qp_attr->port_num = hr_qp->port + 1; 5862 qp_attr->sq_draining = 0; 5863 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX); 5864 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX); 5865 5866 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME); 5867 qp_attr->timeout = get_qp_timeout_attr(hr_dev, &context); 5868 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT); 5869 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT); 5870 5871 done: 5872 qp_attr->cur_qp_state = qp_attr->qp_state; 5873 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 5874 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 5875 qp_attr->cap.max_inline_data = hr_qp->max_inline_data; 5876 5877 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 5878 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 5879 5880 qp_init_attr->qp_context = ibqp->qp_context; 5881 qp_init_attr->qp_type = ibqp->qp_type; 5882 qp_init_attr->recv_cq = ibqp->recv_cq; 5883 qp_init_attr->send_cq = ibqp->send_cq; 5884 qp_init_attr->srq = ibqp->srq; 5885 qp_init_attr->cap = qp_attr->cap; 5886 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits; 5887 5888 out: 5889 mutex_unlock(&hr_qp->mutex); 5890 return ret; 5891 } 5892 5893 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp) 5894 { 5895 return ((hr_qp->ibqp.qp_type == IB_QPT_RC || 5896 hr_qp->ibqp.qp_type == IB_QPT_UD || 5897 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5898 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 5899 hr_qp->state != IB_QPS_RESET); 5900 } 5901 5902 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 5903 struct hns_roce_qp *hr_qp, 5904 struct ib_udata *udata) 5905 { 5906 struct ib_device *ibdev = &hr_dev->ib_dev; 5907 struct hns_roce_cq *send_cq, *recv_cq; 5908 unsigned long flags; 5909 int ret = 0; 5910 5911 if (modify_qp_is_ok(hr_qp)) { 5912 /* Modify qp to reset before destroying qp */ 5913 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 5914 hr_qp->state, IB_QPS_RESET, udata); 5915 if (ret) 5916 ibdev_err_ratelimited(ibdev, 5917 "failed to modify QP to RST, ret = %d.\n", 5918 ret); 5919 } 5920 5921 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 5922 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 5923 5924 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 5925 hns_roce_lock_cqs(send_cq, recv_cq); 5926 5927 if (!udata) { 5928 if (recv_cq) 5929 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 5930 (hr_qp->ibqp.srq ? 5931 to_hr_srq(hr_qp->ibqp.srq) : 5932 NULL)); 5933 5934 if (send_cq && send_cq != recv_cq) 5935 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 5936 } 5937 5938 hns_roce_qp_remove(hr_dev, hr_qp); 5939 5940 hns_roce_unlock_cqs(send_cq, recv_cq); 5941 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 5942 5943 return ret; 5944 } 5945 5946 static void put_dip_ctx_idx(struct hns_roce_dev *hr_dev, 5947 struct hns_roce_qp *hr_qp) 5948 { 5949 struct hns_roce_dip *hr_dip = hr_qp->dip; 5950 5951 if (!hr_dip) 5952 return; 5953 5954 xa_lock(&hr_dev->qp_table.dip_xa); 5955 5956 hr_dip->qp_cnt--; 5957 if (!hr_dip->qp_cnt) 5958 memset(hr_dip->dgid, 0, GID_LEN_V2); 5959 5960 xa_unlock(&hr_dev->qp_table.dip_xa); 5961 } 5962 5963 int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 5964 { 5965 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5966 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5967 unsigned long flags; 5968 int ret; 5969 5970 /* Make sure flush_cqe() is completed */ 5971 spin_lock_irqsave(&hr_qp->flush_lock, flags); 5972 set_bit(HNS_ROCE_STOP_FLUSH_FLAG, &hr_qp->flush_flag); 5973 spin_unlock_irqrestore(&hr_qp->flush_lock, flags); 5974 flush_work(&hr_qp->flush_work.work); 5975 5976 if (hr_qp->cong_type == CONG_TYPE_DIP) 5977 put_dip_ctx_idx(hr_dev, hr_qp); 5978 5979 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 5980 if (ret) 5981 ibdev_err_ratelimited(&hr_dev->ib_dev, 5982 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n", 5983 hr_qp->qpn, ret); 5984 5985 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 5986 5987 return 0; 5988 } 5989 5990 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 5991 struct hns_roce_qp *hr_qp) 5992 { 5993 struct ib_device *ibdev = &hr_dev->ib_dev; 5994 struct hns_roce_sccc_clr_done *resp; 5995 struct hns_roce_sccc_clr *clr; 5996 struct hns_roce_cmq_desc desc; 5997 int ret, i; 5998 5999 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 6000 return 0; 6001 6002 mutex_lock(&hr_dev->qp_table.scc_mutex); 6003 6004 /* set scc ctx clear done flag */ 6005 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 6006 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6007 if (ret) { 6008 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret); 6009 goto out; 6010 } 6011 6012 /* clear scc context */ 6013 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 6014 clr = (struct hns_roce_sccc_clr *)desc.data; 6015 clr->qpn = cpu_to_le32(hr_qp->qpn); 6016 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6017 if (ret) { 6018 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret); 6019 goto out; 6020 } 6021 6022 /* query scc context clear is done or not */ 6023 resp = (struct hns_roce_sccc_clr_done *)desc.data; 6024 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 6025 hns_roce_cmq_setup_basic_desc(&desc, 6026 HNS_ROCE_OPC_QUERY_SCCC, true); 6027 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6028 if (ret) { 6029 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 6030 ret); 6031 goto out; 6032 } 6033 6034 if (resp->clr_done) 6035 goto out; 6036 6037 msleep(20); 6038 } 6039 6040 ibdev_err(ibdev, "query SCC clr done flag overtime.\n"); 6041 ret = -ETIMEDOUT; 6042 6043 out: 6044 mutex_unlock(&hr_dev->qp_table.scc_mutex); 6045 return ret; 6046 } 6047 6048 #define DMA_IDX_SHIFT 3 6049 #define DMA_WQE_SHIFT 3 6050 6051 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq, 6052 struct hns_roce_srq_context *ctx) 6053 { 6054 struct hns_roce_idx_que *idx_que = &srq->idx_que; 6055 struct ib_device *ibdev = srq->ibsrq.device; 6056 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 6057 u64 mtts_idx[MTT_MIN_COUNT] = {}; 6058 dma_addr_t dma_handle_idx; 6059 int ret; 6060 6061 /* Get physical address of idx que buf */ 6062 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx, 6063 ARRAY_SIZE(mtts_idx)); 6064 if (ret) { 6065 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n", 6066 ret); 6067 return ret; 6068 } 6069 6070 dma_handle_idx = hns_roce_get_mtr_ba(&idx_que->mtr); 6071 6072 hr_reg_write(ctx, SRQC_IDX_HOP_NUM, 6073 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt)); 6074 6075 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT); 6076 hr_reg_write(ctx, SRQC_IDX_BT_BA_H, 6077 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT)); 6078 6079 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ, 6080 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift)); 6081 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ, 6082 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift)); 6083 6084 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L, 6085 to_hr_hw_page_addr(mtts_idx[0])); 6086 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H, 6087 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 6088 6089 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L, 6090 to_hr_hw_page_addr(mtts_idx[1])); 6091 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H, 6092 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 6093 6094 return 0; 6095 } 6096 6097 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) 6098 { 6099 struct ib_device *ibdev = srq->ibsrq.device; 6100 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 6101 struct hns_roce_srq_context *ctx = mb_buf; 6102 u64 mtts_wqe[MTT_MIN_COUNT] = {}; 6103 dma_addr_t dma_handle_wqe; 6104 int ret; 6105 6106 memset(ctx, 0, sizeof(*ctx)); 6107 6108 /* Get the physical address of srq buf */ 6109 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe, 6110 ARRAY_SIZE(mtts_wqe)); 6111 if (ret) { 6112 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n", 6113 ret); 6114 return ret; 6115 } 6116 6117 dma_handle_wqe = hns_roce_get_mtr_ba(&srq->buf_mtr); 6118 6119 hr_reg_write(ctx, SRQC_SRQ_ST, 1); 6120 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE, 6121 srq->ibsrq.srq_type == IB_SRQT_XRC); 6122 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); 6123 hr_reg_write(ctx, SRQC_SRQN, srq->srqn); 6124 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn); 6125 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn); 6126 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt)); 6127 hr_reg_write(ctx, SRQC_RQWS, 6128 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1)); 6129 6130 hr_reg_write(ctx, SRQC_WQE_HOP_NUM, 6131 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 6132 srq->wqe_cnt)); 6133 6134 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT); 6135 hr_reg_write(ctx, SRQC_WQE_BT_BA_H, 6136 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT)); 6137 6138 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ, 6139 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 6140 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ, 6141 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 6142 6143 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) { 6144 hr_reg_enable(ctx, SRQC_DB_RECORD_EN); 6145 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_L, 6146 lower_32_bits(srq->rdb.dma) >> 1); 6147 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_H, 6148 upper_32_bits(srq->rdb.dma)); 6149 } 6150 6151 return hns_roce_v2_write_srqc_index_queue(srq, ctx); 6152 } 6153 6154 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 6155 struct ib_srq_attr *srq_attr, 6156 enum ib_srq_attr_mask srq_attr_mask, 6157 struct ib_udata *udata) 6158 { 6159 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 6160 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 6161 struct hns_roce_srq_context *srq_context; 6162 struct hns_roce_srq_context *srqc_mask; 6163 struct hns_roce_cmd_mailbox *mailbox; 6164 int ret = 0; 6165 6166 /* Resizing SRQs is not supported yet */ 6167 if (srq_attr_mask & IB_SRQ_MAX_WR) { 6168 ret = -EOPNOTSUPP; 6169 goto out; 6170 } 6171 6172 if (srq_attr_mask & IB_SRQ_LIMIT) { 6173 if (srq_attr->srq_limit > srq->wqe_cnt) { 6174 ret = -EINVAL; 6175 goto out; 6176 } 6177 6178 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6179 if (IS_ERR(mailbox)) { 6180 ret = PTR_ERR(mailbox); 6181 goto out; 6182 } 6183 6184 srq_context = mailbox->buf; 6185 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 6186 6187 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 6188 6189 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit); 6190 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL); 6191 6192 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 6193 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn); 6194 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6195 if (ret) 6196 ibdev_err_ratelimited(&hr_dev->ib_dev, 6197 "failed to handle cmd of modifying SRQ, ret = %d.\n", 6198 ret); 6199 } 6200 6201 out: 6202 if (ret) 6203 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_SRQ_MODIFY_ERR_CNT]); 6204 6205 return ret; 6206 } 6207 6208 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 6209 { 6210 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 6211 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 6212 struct hns_roce_srq_context *srq_context; 6213 struct hns_roce_cmd_mailbox *mailbox; 6214 int ret; 6215 6216 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6217 if (IS_ERR(mailbox)) 6218 return PTR_ERR(mailbox); 6219 6220 srq_context = mailbox->buf; 6221 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 6222 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn); 6223 if (ret) { 6224 ibdev_err_ratelimited(&hr_dev->ib_dev, 6225 "failed to process cmd of querying SRQ, ret = %d.\n", 6226 ret); 6227 goto out; 6228 } 6229 6230 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL); 6231 attr->max_wr = srq->wqe_cnt; 6232 attr->max_sge = srq->max_gs - srq->rsv_sge; 6233 6234 out: 6235 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6236 return ret; 6237 } 6238 6239 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 6240 { 6241 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 6242 struct hns_roce_v2_cq_context *cq_context; 6243 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 6244 struct hns_roce_v2_cq_context *cqc_mask; 6245 struct hns_roce_cmd_mailbox *mailbox; 6246 int ret; 6247 6248 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6249 ret = PTR_ERR_OR_ZERO(mailbox); 6250 if (ret) 6251 goto err_out; 6252 6253 cq_context = mailbox->buf; 6254 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 6255 6256 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 6257 6258 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count); 6259 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT); 6260 6261 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6262 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 6263 dev_info(hr_dev->dev, 6264 "cq_period(%u) reached the upper limit, adjusted to 65.\n", 6265 cq_period); 6266 cq_period = HNS_ROCE_MAX_CQ_PERIOD_HIP08; 6267 } 6268 cq_period *= HNS_ROCE_CLOCK_ADJUST; 6269 } 6270 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period); 6271 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD); 6272 6273 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 6274 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn); 6275 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6276 if (ret) 6277 ibdev_err_ratelimited(&hr_dev->ib_dev, 6278 "failed to process cmd when modifying CQ, ret = %d.\n", 6279 ret); 6280 6281 err_out: 6282 if (ret) 6283 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CQ_MODIFY_ERR_CNT]); 6284 6285 return ret; 6286 } 6287 6288 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn, 6289 void *buffer) 6290 { 6291 struct hns_roce_v2_cq_context *context; 6292 struct hns_roce_cmd_mailbox *mailbox; 6293 int ret; 6294 6295 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6296 if (IS_ERR(mailbox)) 6297 return PTR_ERR(mailbox); 6298 6299 context = mailbox->buf; 6300 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 6301 HNS_ROCE_CMD_QUERY_CQC, cqn); 6302 if (ret) { 6303 ibdev_err_ratelimited(&hr_dev->ib_dev, 6304 "failed to process cmd when querying CQ, ret = %d.\n", 6305 ret); 6306 goto err_mailbox; 6307 } 6308 6309 memcpy(buffer, context, sizeof(*context)); 6310 6311 err_mailbox: 6312 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6313 6314 return ret; 6315 } 6316 6317 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key, 6318 void *buffer) 6319 { 6320 struct hns_roce_v2_mpt_entry *context; 6321 struct hns_roce_cmd_mailbox *mailbox; 6322 int ret; 6323 6324 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6325 if (IS_ERR(mailbox)) 6326 return PTR_ERR(mailbox); 6327 6328 context = mailbox->buf; 6329 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT, 6330 key_to_hw_index(key)); 6331 if (ret) { 6332 ibdev_err_ratelimited(&hr_dev->ib_dev, 6333 "failed to process cmd when querying MPT, ret = %d.\n", 6334 ret); 6335 goto err_mailbox; 6336 } 6337 6338 memcpy(buffer, context, sizeof(*context)); 6339 6340 err_mailbox: 6341 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6342 6343 return ret; 6344 } 6345 6346 static void dump_aeqe_log(struct hns_roce_work *irq_work) 6347 { 6348 struct hns_roce_dev *hr_dev = irq_work->hr_dev; 6349 struct ib_device *ibdev = &hr_dev->ib_dev; 6350 6351 switch (irq_work->event_type) { 6352 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 6353 ibdev_info(ibdev, "path migrated succeeded.\n"); 6354 break; 6355 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 6356 ibdev_warn(ibdev, "path migration failed.\n"); 6357 break; 6358 case HNS_ROCE_EVENT_TYPE_COMM_EST: 6359 break; 6360 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 6361 ibdev_dbg(ibdev, "send queue drained.\n"); 6362 break; 6363 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 6364 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n", 6365 irq_work->queue_num, irq_work->sub_type); 6366 break; 6367 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 6368 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n", 6369 irq_work->queue_num); 6370 break; 6371 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 6372 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n", 6373 irq_work->queue_num, irq_work->sub_type); 6374 break; 6375 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 6376 ibdev_dbg(ibdev, "SRQ limit reach.\n"); 6377 break; 6378 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 6379 ibdev_dbg(ibdev, "SRQ last wqe reach.\n"); 6380 break; 6381 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 6382 ibdev_err(ibdev, "SRQ catas error.\n"); 6383 break; 6384 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 6385 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num); 6386 break; 6387 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 6388 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num); 6389 break; 6390 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 6391 ibdev_warn(ibdev, "DB overflow.\n"); 6392 break; 6393 case HNS_ROCE_EVENT_TYPE_MB: 6394 break; 6395 case HNS_ROCE_EVENT_TYPE_FLR: 6396 ibdev_warn(ibdev, "function level reset.\n"); 6397 break; 6398 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 6399 ibdev_err(ibdev, "xrc domain violation error.\n"); 6400 break; 6401 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 6402 ibdev_err(ibdev, "invalid xrceth error.\n"); 6403 break; 6404 default: 6405 ibdev_info(ibdev, "Undefined event %d.\n", 6406 irq_work->event_type); 6407 break; 6408 } 6409 } 6410 6411 static void hns_roce_irq_work_handle(struct work_struct *work) 6412 { 6413 struct hns_roce_work *irq_work = 6414 container_of(work, struct hns_roce_work, work); 6415 struct hns_roce_dev *hr_dev = irq_work->hr_dev; 6416 int event_type = irq_work->event_type; 6417 u32 queue_num = irq_work->queue_num; 6418 6419 switch (event_type) { 6420 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 6421 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 6422 case HNS_ROCE_EVENT_TYPE_COMM_EST: 6423 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 6424 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 6425 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 6426 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 6427 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 6428 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 6429 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 6430 hns_roce_qp_event(hr_dev, queue_num, event_type); 6431 break; 6432 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 6433 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 6434 hns_roce_srq_event(hr_dev, queue_num, event_type); 6435 break; 6436 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 6437 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 6438 hns_roce_cq_event(hr_dev, queue_num, event_type); 6439 break; 6440 default: 6441 break; 6442 } 6443 6444 dump_aeqe_log(irq_work); 6445 6446 kfree(irq_work); 6447 } 6448 6449 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 6450 struct hns_roce_eq *eq, u32 queue_num) 6451 { 6452 struct hns_roce_work *irq_work; 6453 6454 irq_work = kzalloc_obj(struct hns_roce_work, GFP_ATOMIC); 6455 if (!irq_work) 6456 return; 6457 6458 INIT_WORK(&irq_work->work, hns_roce_irq_work_handle); 6459 irq_work->hr_dev = hr_dev; 6460 irq_work->event_type = eq->event_type; 6461 irq_work->sub_type = eq->sub_type; 6462 irq_work->queue_num = queue_num; 6463 queue_work(hr_dev->irq_workq, &irq_work->work); 6464 } 6465 6466 static void update_eq_db(struct hns_roce_eq *eq) 6467 { 6468 struct hns_roce_dev *hr_dev = eq->hr_dev; 6469 struct hns_roce_v2_db eq_db = {}; 6470 6471 if (eq->type_flag == HNS_ROCE_AEQ) { 6472 hr_reg_write(&eq_db, EQ_DB_CMD, 6473 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 6474 HNS_ROCE_EQ_DB_CMD_AEQ : 6475 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 6476 } else { 6477 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn); 6478 6479 hr_reg_write(&eq_db, EQ_DB_CMD, 6480 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 6481 HNS_ROCE_EQ_DB_CMD_CEQ : 6482 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 6483 } 6484 6485 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index); 6486 6487 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg); 6488 } 6489 6490 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 6491 { 6492 struct hns_roce_aeqe *aeqe; 6493 6494 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 6495 (eq->cons_index & (eq->entries - 1)) * 6496 eq->eqe_size); 6497 6498 return (hr_reg_read(aeqe, AEQE_OWNER) ^ 6499 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 6500 } 6501 6502 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 6503 struct hns_roce_eq *eq) 6504 { 6505 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 6506 irqreturn_t aeqe_found = IRQ_NONE; 6507 int num_aeqes = 0; 6508 int event_type; 6509 u32 queue_num; 6510 int sub_type; 6511 6512 while (aeqe && num_aeqes < HNS_AEQ_POLLING_BUDGET) { 6513 /* Make sure we read AEQ entry after we have checked the 6514 * ownership bit 6515 */ 6516 dma_rmb(); 6517 6518 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE); 6519 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE); 6520 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM); 6521 6522 switch (event_type) { 6523 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 6524 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 6525 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 6526 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 6527 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 6528 hns_roce_flush_cqe(hr_dev, queue_num); 6529 break; 6530 case HNS_ROCE_EVENT_TYPE_MB: 6531 hns_roce_cmd_event(hr_dev, 6532 le16_to_cpu(aeqe->event.cmd.token), 6533 aeqe->event.cmd.status, 6534 le64_to_cpu(aeqe->event.cmd.out_param)); 6535 break; 6536 default: 6537 break; 6538 } 6539 6540 eq->event_type = event_type; 6541 eq->sub_type = sub_type; 6542 ++eq->cons_index; 6543 aeqe_found = IRQ_HANDLED; 6544 trace_hns_ae_info(event_type, aeqe, eq->eqe_size); 6545 6546 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_AEQE_CNT]); 6547 6548 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num); 6549 6550 aeqe = next_aeqe_sw_v2(eq); 6551 ++num_aeqes; 6552 } 6553 6554 update_eq_db(eq); 6555 6556 return IRQ_RETVAL(aeqe_found); 6557 } 6558 6559 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 6560 { 6561 struct hns_roce_ceqe *ceqe; 6562 6563 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 6564 (eq->cons_index & (eq->entries - 1)) * 6565 eq->eqe_size); 6566 6567 return (hr_reg_read(ceqe, CEQE_OWNER) ^ 6568 !!(eq->cons_index & eq->entries)) ? ceqe : NULL; 6569 } 6570 6571 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_eq *eq) 6572 { 6573 queue_work(system_bh_wq, &eq->work); 6574 6575 return IRQ_HANDLED; 6576 } 6577 6578 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 6579 { 6580 struct hns_roce_eq *eq = eq_ptr; 6581 struct hns_roce_dev *hr_dev = eq->hr_dev; 6582 irqreturn_t int_work; 6583 6584 if (eq->type_flag == HNS_ROCE_CEQ) 6585 /* Completion event interrupt */ 6586 int_work = hns_roce_v2_ceq_int(eq); 6587 else 6588 /* Asynchronous event interrupt */ 6589 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 6590 6591 return IRQ_RETVAL(int_work); 6592 } 6593 6594 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev, 6595 u32 int_st) 6596 { 6597 struct pci_dev *pdev = hr_dev->pci_dev; 6598 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 6599 const struct hnae3_ae_ops *ops = ae_dev->ops; 6600 enum hnae3_reset_type reset_type; 6601 irqreturn_t int_work = IRQ_NONE; 6602 u32 int_en; 6603 6604 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 6605 6606 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 6607 dev_err(hr_dev->dev, "AEQ overflow!\n"); 6608 6609 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, 6610 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S); 6611 6612 reset_type = hr_dev->is_vf ? 6613 HNAE3_VF_FUNC_RESET : HNAE3_FUNC_RESET; 6614 6615 /* Set reset level for reset_event() */ 6616 if (ops->set_default_reset_request) 6617 ops->set_default_reset_request(ae_dev, reset_type); 6618 if (ops->reset_event) 6619 ops->reset_event(pdev, NULL); 6620 6621 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 6622 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 6623 6624 int_work = IRQ_HANDLED; 6625 } else { 6626 dev_err(hr_dev->dev, "there is no basic abn irq found.\n"); 6627 } 6628 6629 return IRQ_RETVAL(int_work); 6630 } 6631 6632 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev, 6633 struct fmea_ram_ecc *ecc_info) 6634 { 6635 struct hns_roce_cmq_desc desc; 6636 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6637 int ret; 6638 6639 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true); 6640 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6641 if (ret) 6642 return ret; 6643 6644 ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR); 6645 ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE); 6646 ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG); 6647 6648 return 0; 6649 } 6650 6651 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx) 6652 { 6653 struct hns_roce_cmq_desc desc; 6654 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6655 u32 addr_upper; 6656 u32 addr_low; 6657 int ret; 6658 6659 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true); 6660 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6661 6662 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6663 if (ret) { 6664 dev_err(hr_dev->dev, 6665 "failed to execute cmd to read gmv, ret = %d.\n", ret); 6666 return ret; 6667 } 6668 6669 addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L); 6670 addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H); 6671 6672 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 6673 hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low); 6674 hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper); 6675 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6676 6677 return hns_roce_cmq_send(hr_dev, &desc, 1); 6678 } 6679 6680 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data) 6681 { 6682 if (res_type == ECC_RESOURCE_QPC_TIMER || 6683 res_type == ECC_RESOURCE_CQC_TIMER || 6684 res_type == ECC_RESOURCE_SCCC) 6685 return le64_to_cpu(*data); 6686 6687 return le64_to_cpu(*data) << HNS_HW_PAGE_SHIFT; 6688 } 6689 6690 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type, 6691 u32 index) 6692 { 6693 u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op; 6694 u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op; 6695 struct hns_roce_cmd_mailbox *mailbox; 6696 u64 addr; 6697 int ret; 6698 6699 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6700 if (IS_ERR(mailbox)) 6701 return PTR_ERR(mailbox); 6702 6703 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index); 6704 if (ret) { 6705 dev_err(hr_dev->dev, 6706 "failed to execute cmd to read fmea ram, ret = %d.\n", 6707 ret); 6708 goto out; 6709 } 6710 6711 addr = fmea_get_ram_res_addr(res_type, mailbox->buf); 6712 6713 ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index); 6714 if (ret) 6715 dev_err(hr_dev->dev, 6716 "failed to execute cmd to write fmea ram, ret = %d.\n", 6717 ret); 6718 6719 out: 6720 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6721 return ret; 6722 } 6723 6724 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev, 6725 struct fmea_ram_ecc *ecc_info) 6726 { 6727 u32 res_type = ecc_info->res_type; 6728 u32 index = ecc_info->index; 6729 int ret; 6730 6731 BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT); 6732 6733 if (res_type >= ECC_RESOURCE_COUNT) { 6734 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n", 6735 res_type); 6736 return; 6737 } 6738 6739 if (res_type == ECC_RESOURCE_GMV) 6740 ret = fmea_recover_gmv(hr_dev, index); 6741 else 6742 ret = fmea_recover_others(hr_dev, res_type, index); 6743 if (ret) 6744 dev_err(hr_dev->dev, 6745 "failed to recover %s, index = %u, ret = %d.\n", 6746 fmea_ram_res[res_type].name, index, ret); 6747 } 6748 6749 static void fmea_ram_ecc_work(struct work_struct *ecc_work) 6750 { 6751 struct hns_roce_dev *hr_dev = 6752 container_of(ecc_work, struct hns_roce_dev, ecc_work); 6753 struct fmea_ram_ecc ecc_info = {}; 6754 6755 if (fmea_ram_ecc_query(hr_dev, &ecc_info)) { 6756 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n"); 6757 return; 6758 } 6759 6760 if (!ecc_info.is_ecc_err) { 6761 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n"); 6762 return; 6763 } 6764 6765 fmea_ram_ecc_recover(hr_dev, &ecc_info); 6766 } 6767 6768 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 6769 { 6770 struct hns_roce_dev *hr_dev = dev_id; 6771 irqreturn_t int_work = IRQ_NONE; 6772 u32 int_st; 6773 6774 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 6775 6776 if (int_st) { 6777 int_work = abnormal_interrupt_basic(hr_dev, int_st); 6778 } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 6779 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work); 6780 int_work = IRQ_HANDLED; 6781 } else { 6782 dev_err(hr_dev->dev, "there is no abnormal irq found.\n"); 6783 } 6784 6785 return IRQ_RETVAL(int_work); 6786 } 6787 6788 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 6789 int eq_num, u32 enable_flag) 6790 { 6791 int i; 6792 6793 for (i = 0; i < eq_num; i++) 6794 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 6795 i * EQ_REG_OFFSET, enable_flag); 6796 6797 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag); 6798 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag); 6799 } 6800 6801 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6802 { 6803 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 6804 } 6805 6806 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, 6807 struct hns_roce_eq *eq) 6808 { 6809 struct device *dev = hr_dev->dev; 6810 int eqn = eq->eqn; 6811 int ret; 6812 u8 cmd; 6813 6814 if (eqn < hr_dev->caps.num_comp_vectors) 6815 cmd = HNS_ROCE_CMD_DESTROY_CEQC; 6816 else 6817 cmd = HNS_ROCE_CMD_DESTROY_AEQC; 6818 6819 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M); 6820 if (ret) 6821 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn); 6822 6823 free_eq_buf(hr_dev, eq); 6824 } 6825 6826 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6827 { 6828 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 6829 eq->cons_index = 0; 6830 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 6831 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 6832 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 6833 eq->shift = ilog2((unsigned int)eq->entries); 6834 } 6835 6836 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 6837 void *mb_buf) 6838 { 6839 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 6840 struct hns_roce_eq_context *eqc; 6841 u64 bt_ba = 0; 6842 int ret; 6843 6844 eqc = mb_buf; 6845 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 6846 6847 init_eq_config(hr_dev, eq); 6848 6849 /* if not multi-hop, eqe buffer only use one trunk */ 6850 ret = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, 6851 ARRAY_SIZE(eqe_ba)); 6852 if (ret) { 6853 dev_err(hr_dev->dev, "failed to find EQE mtr, ret = %d\n", ret); 6854 return ret; 6855 } 6856 6857 bt_ba = hns_roce_get_mtr_ba(&eq->mtr); 6858 6859 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID); 6860 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num); 6861 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore); 6862 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce); 6863 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st); 6864 hr_reg_write(eqc, EQC_EQN, eq->eqn); 6865 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT); 6866 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ, 6867 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 6868 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ, 6869 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 6870 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX); 6871 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt); 6872 6873 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6874 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 6875 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n", 6876 eq->eq_period); 6877 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD; 6878 } 6879 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST; 6880 } 6881 6882 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period); 6883 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER); 6884 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3); 6885 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35); 6886 hr_reg_write(eqc, EQC_SHIFT, eq->shift); 6887 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX); 6888 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12); 6889 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28); 6890 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60); 6891 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX); 6892 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12); 6893 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44); 6894 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE); 6895 6896 return 0; 6897 } 6898 6899 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6900 { 6901 struct hns_roce_buf_attr buf_attr = {}; 6902 int err; 6903 6904 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 6905 eq->hop_num = 0; 6906 else 6907 eq->hop_num = hr_dev->caps.eqe_hop_num; 6908 6909 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT; 6910 buf_attr.region[0].size = eq->entries * eq->eqe_size; 6911 buf_attr.region[0].hopnum = eq->hop_num; 6912 buf_attr.region_count = 1; 6913 6914 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 6915 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL, 6916 0); 6917 if (err) 6918 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err); 6919 6920 return err; 6921 } 6922 6923 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 6924 struct hns_roce_eq *eq, u8 eq_cmd) 6925 { 6926 struct hns_roce_cmd_mailbox *mailbox; 6927 int ret; 6928 6929 /* Allocate mailbox memory */ 6930 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6931 if (IS_ERR(mailbox)) 6932 return PTR_ERR(mailbox); 6933 6934 ret = alloc_eq_buf(hr_dev, eq); 6935 if (ret) 6936 goto free_cmd_mbox; 6937 6938 ret = config_eqc(hr_dev, eq, mailbox->buf); 6939 if (ret) 6940 goto err_cmd_mbox; 6941 6942 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn); 6943 if (ret) { 6944 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 6945 goto err_cmd_mbox; 6946 } 6947 6948 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6949 6950 return 0; 6951 6952 err_cmd_mbox: 6953 free_eq_buf(hr_dev, eq); 6954 6955 free_cmd_mbox: 6956 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6957 6958 return ret; 6959 } 6960 6961 static void hns_roce_ceq_work(struct work_struct *work) 6962 { 6963 struct hns_roce_eq *eq = from_work(eq, work, work); 6964 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 6965 struct hns_roce_dev *hr_dev = eq->hr_dev; 6966 int ceqe_num = 0; 6967 u32 cqn; 6968 6969 while (ceqe && ceqe_num < hr_dev->caps.ceqe_depth) { 6970 /* Make sure we read CEQ entry after we have checked the 6971 * ownership bit 6972 */ 6973 dma_rmb(); 6974 6975 cqn = hr_reg_read(ceqe, CEQE_CQN); 6976 6977 hns_roce_cq_completion(hr_dev, cqn); 6978 6979 ++eq->cons_index; 6980 ++ceqe_num; 6981 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CEQE_CNT]); 6982 6983 ceqe = next_ceqe_sw_v2(eq); 6984 } 6985 6986 update_eq_db(eq); 6987 } 6988 6989 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 6990 int comp_num, int aeq_num, int other_num) 6991 { 6992 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6993 int i, j; 6994 int ret; 6995 6996 for (i = 0; i < irq_num; i++) { 6997 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 6998 GFP_KERNEL); 6999 if (!hr_dev->irq_names[i]) { 7000 ret = -ENOMEM; 7001 goto err_kzalloc_failed; 7002 } 7003 } 7004 7005 /* irq contains: abnormal + AEQ + CEQ */ 7006 for (j = 0; j < other_num; j++) 7007 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 7008 "hns-%s-abn-%d", pci_name(hr_dev->pci_dev), j); 7009 7010 for (j = other_num; j < (other_num + aeq_num); j++) 7011 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 7012 "hns-%s-aeq-%d", pci_name(hr_dev->pci_dev), j - other_num); 7013 7014 for (j = (other_num + aeq_num); j < irq_num; j++) 7015 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 7016 "hns-%s-ceq-%d", pci_name(hr_dev->pci_dev), 7017 j - other_num - aeq_num); 7018 7019 for (j = 0; j < irq_num; j++) { 7020 if (j < other_num) { 7021 ret = request_irq(hr_dev->irq[j], 7022 hns_roce_v2_msix_interrupt_abn, 7023 0, hr_dev->irq_names[j], hr_dev); 7024 } else if (j < (other_num + comp_num)) { 7025 INIT_WORK(&eq_table->eq[j - other_num].work, 7026 hns_roce_ceq_work); 7027 ret = request_irq(eq_table->eq[j - other_num].irq, 7028 hns_roce_v2_msix_interrupt_eq, 7029 0, hr_dev->irq_names[j + aeq_num], 7030 &eq_table->eq[j - other_num]); 7031 } else { 7032 ret = request_irq(eq_table->eq[j - other_num].irq, 7033 hns_roce_v2_msix_interrupt_eq, 7034 0, hr_dev->irq_names[j - comp_num], 7035 &eq_table->eq[j - other_num]); 7036 } 7037 7038 if (ret) { 7039 dev_err(hr_dev->dev, "request irq error!\n"); 7040 goto err_request_failed; 7041 } 7042 } 7043 7044 return 0; 7045 7046 err_request_failed: 7047 for (j -= 1; j >= 0; j--) { 7048 if (j < other_num) { 7049 free_irq(hr_dev->irq[j], hr_dev); 7050 continue; 7051 } 7052 free_irq(eq_table->eq[j - other_num].irq, 7053 &eq_table->eq[j - other_num]); 7054 if (j < other_num + comp_num) 7055 cancel_work_sync(&eq_table->eq[j - other_num].work); 7056 } 7057 7058 err_kzalloc_failed: 7059 for (i -= 1; i >= 0; i--) 7060 kfree(hr_dev->irq_names[i]); 7061 7062 return ret; 7063 } 7064 7065 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 7066 { 7067 int irq_num; 7068 int eq_num; 7069 int i; 7070 7071 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 7072 irq_num = eq_num + hr_dev->caps.num_other_vectors; 7073 7074 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 7075 free_irq(hr_dev->irq[i], hr_dev); 7076 7077 for (i = 0; i < eq_num; i++) { 7078 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 7079 if (i < hr_dev->caps.num_comp_vectors) 7080 cancel_work_sync(&hr_dev->eq_table.eq[i].work); 7081 } 7082 7083 for (i = 0; i < irq_num; i++) 7084 kfree(hr_dev->irq_names[i]); 7085 } 7086 7087 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 7088 { 7089 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 7090 struct device *dev = hr_dev->dev; 7091 struct hns_roce_eq *eq; 7092 int other_num; 7093 int comp_num; 7094 int aeq_num; 7095 int irq_num; 7096 int eq_num; 7097 u8 eq_cmd; 7098 int ret; 7099 int i; 7100 7101 if (hr_dev->caps.aeqe_depth < HNS_AEQ_POLLING_BUDGET) 7102 return -EINVAL; 7103 7104 other_num = hr_dev->caps.num_other_vectors; 7105 comp_num = hr_dev->caps.num_comp_vectors; 7106 aeq_num = hr_dev->caps.num_aeq_vectors; 7107 7108 eq_num = comp_num + aeq_num; 7109 irq_num = eq_num + other_num; 7110 7111 eq_table->eq = kzalloc_objs(*eq_table->eq, eq_num); 7112 if (!eq_table->eq) 7113 return -ENOMEM; 7114 7115 /* create eq */ 7116 for (i = 0; i < eq_num; i++) { 7117 eq = &eq_table->eq[i]; 7118 eq->hr_dev = hr_dev; 7119 eq->eqn = i; 7120 if (i < comp_num) { 7121 /* CEQ */ 7122 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 7123 eq->type_flag = HNS_ROCE_CEQ; 7124 eq->entries = hr_dev->caps.ceqe_depth; 7125 eq->eqe_size = hr_dev->caps.ceqe_size; 7126 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 7127 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 7128 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 7129 } else { 7130 /* AEQ */ 7131 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 7132 eq->type_flag = HNS_ROCE_AEQ; 7133 eq->entries = hr_dev->caps.aeqe_depth; 7134 eq->eqe_size = hr_dev->caps.aeqe_size; 7135 eq->irq = hr_dev->irq[i - comp_num + other_num]; 7136 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 7137 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 7138 } 7139 7140 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 7141 if (ret) { 7142 dev_err(dev, "failed to create eq.\n"); 7143 goto err_create_eq_fail; 7144 } 7145 } 7146 7147 INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work); 7148 7149 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 7150 WQ_MEM_RECLAIM); 7151 if (!hr_dev->irq_workq) { 7152 dev_err(dev, "failed to create irq workqueue.\n"); 7153 ret = -ENOMEM; 7154 goto err_create_eq_fail; 7155 } 7156 7157 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num, 7158 other_num); 7159 if (ret) { 7160 dev_err(dev, "failed to request irq.\n"); 7161 goto err_request_irq_fail; 7162 } 7163 7164 /* enable irq */ 7165 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 7166 7167 return 0; 7168 7169 err_request_irq_fail: 7170 destroy_workqueue(hr_dev->irq_workq); 7171 7172 err_create_eq_fail: 7173 for (i -= 1; i >= 0; i--) 7174 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]); 7175 kfree(eq_table->eq); 7176 7177 return ret; 7178 } 7179 7180 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 7181 { 7182 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 7183 int eq_num; 7184 int i; 7185 7186 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 7187 7188 /* Disable irq */ 7189 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 7190 7191 __hns_roce_free_irq(hr_dev); 7192 destroy_workqueue(hr_dev->irq_workq); 7193 7194 for (i = 0; i < eq_num; i++) 7195 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]); 7196 7197 kfree(eq_table->eq); 7198 } 7199 7200 static const enum hns_roce_opcode_type scc_opcode[] = { 7201 HNS_ROCE_OPC_CFG_DCQCN_PARAM, 7202 HNS_ROCE_OPC_CFG_LDCP_PARAM, 7203 HNS_ROCE_OPC_CFG_HC3_PARAM, 7204 HNS_ROCE_OPC_CFG_DIP_PARAM, 7205 }; 7206 7207 static int hns_roce_v2_config_scc_param(struct hns_roce_dev *hr_dev, 7208 enum hns_roce_scc_algo algo) 7209 { 7210 struct hns_roce_scc_param *scc_param = &hr_dev->scc_param[algo]; 7211 struct hns_roce_cmq_desc desc; 7212 int ret; 7213 7214 lockdep_assert_held(&scc_param->scc_mutex); 7215 7216 hns_roce_cmq_setup_basic_desc(&desc, scc_opcode[algo], false); 7217 memcpy(&desc.data, scc_param->param, sizeof(scc_param->param)); 7218 7219 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 7220 if (ret) 7221 ibdev_err_ratelimited(&hr_dev->ib_dev, 7222 "failed to configure scc param, opcode: 0x%x, ret = %d.\n", 7223 le16_to_cpu(desc.opcode), ret); 7224 7225 return ret; 7226 } 7227 7228 static int hns_roce_v2_query_scc_param(struct hns_roce_dev *hr_dev, 7229 enum hns_roce_scc_algo algo) 7230 { 7231 struct hns_roce_scc_param *scc_param; 7232 struct hns_roce_cmq_desc desc; 7233 int ret; 7234 7235 hns_roce_cmq_setup_basic_desc(&desc, scc_opcode[algo], true); 7236 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 7237 if (ret) { 7238 ibdev_err_ratelimited(&hr_dev->ib_dev, 7239 "failed to query scc param, opcode: 0x%x, ret = %d.\n", 7240 le16_to_cpu(desc.opcode), ret); 7241 return ret; 7242 } 7243 7244 scc_param = &hr_dev->scc_param[algo]; 7245 scoped_guard(mutex, &scc_param->scc_mutex) 7246 memcpy(scc_param->param, &desc.data, sizeof(scc_param->param)); 7247 7248 return 0; 7249 } 7250 7251 static const struct ib_device_ops hns_roce_v2_dev_ops = { 7252 .destroy_qp = hns_roce_v2_destroy_qp, 7253 .modify_cq = hns_roce_v2_modify_cq, 7254 .poll_cq = hns_roce_v2_poll_cq, 7255 .post_recv = hns_roce_v2_post_recv, 7256 .post_send = hns_roce_v2_post_send, 7257 .query_qp = hns_roce_v2_query_qp, 7258 .req_notify_cq = hns_roce_v2_req_notify_cq, 7259 .drain_rq = hns_roce_v2_drain_rq, 7260 .drain_sq = hns_roce_v2_drain_sq, 7261 }; 7262 7263 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 7264 .modify_srq = hns_roce_v2_modify_srq, 7265 .post_srq_recv = hns_roce_v2_post_srq_recv, 7266 .query_srq = hns_roce_v2_query_srq, 7267 }; 7268 7269 static const struct hns_roce_hw hns_roce_hw_v2 = { 7270 .cmq_init = hns_roce_v2_cmq_init, 7271 .cmq_exit = hns_roce_v2_cmq_exit, 7272 .hw_profile = hns_roce_v2_profile, 7273 .hw_init = hns_roce_v2_init, 7274 .hw_exit = hns_roce_v2_exit, 7275 .post_mbox = v2_post_mbox, 7276 .poll_mbox_done = v2_poll_mbox_done, 7277 .chk_mbox_avail = v2_chk_mbox_is_avail, 7278 .set_gid = hns_roce_v2_set_gid, 7279 .set_mac = hns_roce_v2_set_mac, 7280 .write_mtpt = hns_roce_v2_write_mtpt, 7281 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 7282 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 7283 .write_cqc = hns_roce_v2_write_cqc, 7284 .set_hem = hns_roce_v2_set_hem, 7285 .clear_hem = hns_roce_v2_clear_hem, 7286 .modify_qp = hns_roce_v2_modify_qp, 7287 .dereg_mr = hns_roce_v2_dereg_mr, 7288 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 7289 .init_eq = hns_roce_v2_init_eq_table, 7290 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 7291 .write_srqc = hns_roce_v2_write_srqc, 7292 .query_cqc = hns_roce_v2_query_cqc, 7293 .query_qpc = hns_roce_v2_query_qpc, 7294 .query_mpt = hns_roce_v2_query_mpt, 7295 .query_srqc = hns_roce_v2_query_srqc, 7296 .query_sccc = hns_roce_v2_query_sccc, 7297 .query_hw_counter = hns_roce_hw_v2_query_counter, 7298 .get_dscp = hns_roce_hw_v2_get_dscp, 7299 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 7300 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 7301 .config_scc_param = hns_roce_v2_config_scc_param, 7302 .query_scc_param = hns_roce_v2_query_scc_param, 7303 }; 7304 7305 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 7306 { 7307 PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 7308 .driver_data = 0, 7309 }, { 7310 PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 7311 .driver_data = 0, 7312 }, { 7313 PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 7314 .driver_data = 0, 7315 }, { 7316 PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 7317 .driver_data = 0, 7318 }, { 7319 PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 7320 .driver_data = 0, 7321 }, { 7322 PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 7323 .driver_data = 0, 7324 }, { 7325 PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 7326 .driver_data = HNAE3_DEV_SUPPORT_ROCE_DCB_BITS, 7327 }, 7328 /* required last entry */ 7329 { } 7330 }; 7331 7332 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 7333 7334 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 7335 struct hnae3_handle *handle) 7336 { 7337 struct hns_roce_v2_priv *priv = hr_dev->priv; 7338 const struct pci_device_id *id; 7339 int i; 7340 7341 hr_dev->pci_dev = handle->pdev; 7342 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 7343 hr_dev->is_vf = id->driver_data; 7344 hr_dev->dev = &handle->pdev->dev; 7345 hr_dev->hw = &hns_roce_hw_v2; 7346 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 7347 hr_dev->odb_offset = hr_dev->sdb_offset; 7348 7349 /* Get info from NIC driver. */ 7350 hr_dev->reg_base = handle->rinfo.roce_io_base; 7351 hr_dev->mem_base = handle->rinfo.roce_mem_base; 7352 hr_dev->caps.num_ports = 1; 7353 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 7354 hr_dev->iboe.phy_port[0] = 0; 7355 7356 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 7357 hr_dev->iboe.netdevs[0]->dev_addr); 7358 7359 for (i = 0; i < handle->rinfo.num_vectors; i++) 7360 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 7361 i + handle->rinfo.base_vector); 7362 7363 /* cmd issue mode: 0 is poll, 1 is event */ 7364 hr_dev->cmd_mod = 1; 7365 hr_dev->loop_idc = 0; 7366 7367 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 7368 priv->handle = handle; 7369 } 7370 7371 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 7372 { 7373 struct hns_roce_dev *hr_dev; 7374 int ret; 7375 7376 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 7377 if (!hr_dev) 7378 return -ENOMEM; 7379 7380 hr_dev->priv = kzalloc_obj(struct hns_roce_v2_priv); 7381 if (!hr_dev->priv) { 7382 ret = -ENOMEM; 7383 goto error_failed_kzalloc; 7384 } 7385 7386 hns_roce_hw_v2_get_cfg(hr_dev, handle); 7387 7388 ret = hns_roce_init(hr_dev); 7389 if (ret) { 7390 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 7391 goto error_failed_roce_init; 7392 } 7393 7394 handle->priv = hr_dev; 7395 7396 return 0; 7397 7398 error_failed_roce_init: 7399 kfree(hr_dev->priv); 7400 7401 error_failed_kzalloc: 7402 ib_dealloc_device(&hr_dev->ib_dev); 7403 7404 return ret; 7405 } 7406 7407 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 7408 bool reset, bool bond_cleanup) 7409 { 7410 struct hns_roce_dev *hr_dev = handle->priv; 7411 7412 if (!hr_dev) 7413 return; 7414 7415 handle->priv = NULL; 7416 7417 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 7418 hns_roce_handle_device_err(hr_dev); 7419 7420 hns_roce_exit(hr_dev, bond_cleanup); 7421 kfree(hr_dev->priv); 7422 ib_dealloc_device(&hr_dev->ib_dev); 7423 } 7424 7425 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 7426 { 7427 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 7428 const struct pci_device_id *id; 7429 struct device *dev = &handle->pdev->dev; 7430 int ret; 7431 7432 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 7433 7434 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 7435 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 7436 goto reset_chk_err; 7437 } 7438 7439 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 7440 if (!id) 7441 return 0; 7442 7443 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08) 7444 return 0; 7445 7446 ret = __hns_roce_hw_v2_init_instance(handle); 7447 if (ret) { 7448 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 7449 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 7450 if (ops->ae_dev_resetting(handle) || 7451 ops->get_hw_reset_stat(handle)) 7452 goto reset_chk_err; 7453 else 7454 return ret; 7455 } 7456 7457 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 7458 7459 return 0; 7460 7461 reset_chk_err: 7462 dev_err(dev, "Device is busy in resetting state.\n" 7463 "please retry later.\n"); 7464 7465 return -EBUSY; 7466 } 7467 7468 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 7469 bool reset) 7470 { 7471 /* Suspend bond to avoid concurrency */ 7472 hns_roce_bond_suspend(handle); 7473 7474 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 7475 goto out; 7476 7477 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 7478 7479 __hns_roce_hw_v2_uninit_instance(handle, reset, true); 7480 7481 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 7482 7483 out: 7484 hns_roce_bond_resume(handle); 7485 } 7486 7487 struct hns_roce_dev 7488 *hns_roce_bond_init_client(struct hns_roce_bond_group *bond_grp, 7489 int func_idx) 7490 { 7491 struct hnae3_handle *handle; 7492 int ret; 7493 7494 handle = bond_grp->bond_func_info[func_idx].handle; 7495 if (!handle || !handle->client) 7496 return NULL; 7497 7498 ret = hns_roce_hw_v2_init_instance(handle); 7499 if (ret) 7500 return NULL; 7501 7502 return handle->priv; 7503 } 7504 7505 void hns_roce_bond_uninit_client(struct hns_roce_bond_group *bond_grp, 7506 int func_idx) 7507 { 7508 struct hnae3_handle *handle = bond_grp->bond_func_info[func_idx].handle; 7509 7510 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 7511 return; 7512 7513 handle->rinfo.instance_state = HNS_ROCE_STATE_BOND_UNINIT; 7514 7515 __hns_roce_hw_v2_uninit_instance(handle, false, false); 7516 7517 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 7518 } 7519 7520 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 7521 { 7522 struct hns_roce_dev *hr_dev; 7523 7524 /* Suspend bond to avoid concurrency */ 7525 hns_roce_bond_suspend(handle); 7526 7527 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 7528 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 7529 return 0; 7530 } 7531 7532 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 7533 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 7534 7535 hr_dev = handle->priv; 7536 if (!hr_dev) 7537 return 0; 7538 7539 hr_dev->active = false; 7540 hr_dev->dis_db = true; 7541 7542 rdma_user_mmap_disassociate(&hr_dev->ib_dev); 7543 7544 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 7545 7546 return 0; 7547 } 7548 7549 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 7550 { 7551 struct device *dev = &handle->pdev->dev; 7552 int ret; 7553 7554 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 7555 &handle->rinfo.state)) { 7556 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 7557 hns_roce_bond_resume(handle); 7558 return 0; 7559 } 7560 7561 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 7562 7563 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 7564 ret = __hns_roce_hw_v2_init_instance(handle); 7565 if (ret) { 7566 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 7567 * callback function, RoCE Engine reinitialize. If RoCE reinit 7568 * failed, we should inform NIC driver. 7569 */ 7570 handle->priv = NULL; 7571 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 7572 } else { 7573 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 7574 dev_info(dev, "reset done, RoCE client reinit finished.\n"); 7575 } 7576 7577 hns_roce_bond_resume(handle); 7578 return ret; 7579 } 7580 7581 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 7582 { 7583 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 7584 return 0; 7585 7586 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 7587 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 7588 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 7589 __hns_roce_hw_v2_uninit_instance(handle, false, false); 7590 7591 return 0; 7592 } 7593 7594 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 7595 enum hnae3_reset_notify_type type) 7596 { 7597 int ret = 0; 7598 7599 switch (type) { 7600 case HNAE3_DOWN_CLIENT: 7601 ret = hns_roce_hw_v2_reset_notify_down(handle); 7602 break; 7603 case HNAE3_INIT_CLIENT: 7604 ret = hns_roce_hw_v2_reset_notify_init(handle); 7605 break; 7606 case HNAE3_UNINIT_CLIENT: 7607 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 7608 break; 7609 default: 7610 break; 7611 } 7612 7613 return ret; 7614 } 7615 7616 static void hns_roce_hw_v2_link_status_change(struct hnae3_handle *handle, 7617 bool linkup) 7618 { 7619 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv; 7620 struct net_device *netdev = handle->rinfo.netdev; 7621 7622 if (linkup || !hr_dev) 7623 return; 7624 7625 /* For bond device, the link status depends on the upper netdev, 7626 * and the upper device's link status depends on all the slaves' 7627 * netdev but not only one. So bond device cannot get a correct 7628 * link status from this path. 7629 */ 7630 if (hns_roce_get_bond_grp(netdev, get_hr_bus_num(hr_dev))) 7631 return; 7632 7633 ib_dispatch_port_state_event(&hr_dev->ib_dev, netdev); 7634 } 7635 7636 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 7637 .init_instance = hns_roce_hw_v2_init_instance, 7638 .uninit_instance = hns_roce_hw_v2_uninit_instance, 7639 .link_status_change = hns_roce_hw_v2_link_status_change, 7640 .reset_notify = hns_roce_hw_v2_reset_notify, 7641 }; 7642 7643 static struct hnae3_client hns_roce_hw_v2_client = { 7644 .name = "hns_roce_hw_v2", 7645 .type = HNAE3_CLIENT_ROCE, 7646 .ops = &hns_roce_hw_v2_ops, 7647 }; 7648 7649 static int __init hns_roce_hw_v2_init(void) 7650 { 7651 hns_roce_init_debugfs(); 7652 return hnae3_register_client(&hns_roce_hw_v2_client); 7653 } 7654 7655 static void __exit hns_roce_hw_v2_exit(void) 7656 { 7657 hnae3_unregister_client(&hns_roce_hw_v2_client); 7658 hns_roce_dealloc_bond_grp(); 7659 hns_roce_cleanup_debugfs(); 7660 } 7661 7662 module_init(hns_roce_hw_v2_init); 7663 module_exit(hns_roce_hw_v2_exit); 7664 7665 MODULE_LICENSE("Dual BSD/GPL"); 7666 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 7667 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 7668 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 7669 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 7670