1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83TD510 PHY
3 * Copyright (c) 2022 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
4 */
5
6 #include <linux/bitfield.h>
7 #include <linux/ethtool_netlink.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/phy.h>
11
12 #define DP83TD510E_PHY_ID 0x20000181
13
14 /* MDIO_MMD_VEND2 registers */
15 #define DP83TD510E_PHY_STS 0x10
16 /* Bit 7 - mii_interrupt, active high. Clears on read.
17 * Note: Clearing does not necessarily deactivate IRQ pin if interrupts pending.
18 * This differs from the DP83TD510E datasheet (2020) which states this bit
19 * clears on write 0.
20 */
21 #define DP83TD510E_STS_MII_INT BIT(7)
22 #define DP83TD510E_LINK_STATUS BIT(0)
23
24 #define DP83TD510E_GEN_CFG 0x11
25 #define DP83TD510E_GENCFG_INT_POLARITY BIT(3)
26 #define DP83TD510E_GENCFG_INT_EN BIT(1)
27 #define DP83TD510E_GENCFG_INT_OE BIT(0)
28
29 #define DP83TD510E_INTERRUPT_REG_1 0x12
30 #define DP83TD510E_INT1_LINK BIT(13)
31 #define DP83TD510E_INT1_LINK_EN BIT(5)
32
33 #define DP83TD510E_CTRL 0x1f
34 #define DP83TD510E_CTRL_HW_RESET BIT(15)
35 #define DP83TD510E_CTRL_SW_RESET BIT(14)
36
37 /*
38 * DP83TD510E_PKT_STAT_x registers correspond to similarly named registers
39 * in the datasheet (PKT_STAT_1 through PKT_STAT_6). These registers store
40 * 32-bit or 16-bit counters for TX and RX statistics and must be read in
41 * sequence to ensure the counters are cleared correctly.
42 *
43 * - DP83TD510E_PKT_STAT_1: Contains TX packet count bits [15:0].
44 * - DP83TD510E_PKT_STAT_2: Contains TX packet count bits [31:16].
45 * - DP83TD510E_PKT_STAT_3: Contains TX error packet count.
46 * - DP83TD510E_PKT_STAT_4: Contains RX packet count bits [15:0].
47 * - DP83TD510E_PKT_STAT_5: Contains RX packet count bits [31:16].
48 * - DP83TD510E_PKT_STAT_6: Contains RX error packet count.
49 *
50 * Keeping the register names as defined in the datasheet helps maintain
51 * clarity and alignment with the documentation.
52 */
53 #define DP83TD510E_PKT_STAT_1 0x12b
54 #define DP83TD510E_PKT_STAT_2 0x12c
55 #define DP83TD510E_PKT_STAT_3 0x12d
56 #define DP83TD510E_PKT_STAT_4 0x12e
57 #define DP83TD510E_PKT_STAT_5 0x12f
58 #define DP83TD510E_PKT_STAT_6 0x130
59
60 #define DP83TD510E_AN_STAT_1 0x60c
61 #define DP83TD510E_MASTER_SLAVE_RESOL_FAIL BIT(15)
62
63 #define DP83TD510E_MSE_DETECT 0xa85
64 #define DP83TD510E_MSE_MAX U16_MAX
65
66 #define DP83TD510_SQI_MAX 7
67
68 /* Register values are converted to SNR(dB) as suggested by
69 * "Application Report - DP83TD510E Cable Diagnostics Toolkit":
70 * SNR(dB) = -10 * log10 (VAL/2^17) - 1.76 dB.
71 * SQI ranges are implemented according to "OPEN ALLIANCE - Advanced diagnostic
72 * features for 100BASE-T1 automotive Ethernet PHYs"
73 */
74 static const u16 dp83td510_mse_sqi_map[] = {
75 0x0569, /* < 18dB */
76 0x044c, /* 18dB =< SNR < 19dB */
77 0x0369, /* 19dB =< SNR < 20dB */
78 0x02b6, /* 20dB =< SNR < 21dB */
79 0x0227, /* 21dB =< SNR < 22dB */
80 0x01b6, /* 22dB =< SNR < 23dB */
81 0x015b, /* 23dB =< SNR < 24dB */
82 0x0000 /* 24dB =< SNR */
83 };
84
85 struct dp83td510_stats {
86 u64 tx_pkt_cnt;
87 u64 tx_err_pkt_cnt;
88 u64 rx_pkt_cnt;
89 u64 rx_err_pkt_cnt;
90 };
91
92 struct dp83td510_priv {
93 bool alcd_test_active;
94 struct dp83td510_stats stats;
95 };
96
97 /* Time Domain Reflectometry (TDR) Functionality of DP83TD510 PHY
98 *
99 * I assume that this PHY is using a variation of Spread Spectrum Time Domain
100 * Reflectometry (SSTDR) rather than the commonly used TDR found in many PHYs.
101 * Here are the following observations which likely confirm this:
102 * - The DP83TD510 PHY transmits a modulated signal of configurable length
103 * (default 16000 µs) instead of a single pulse pattern, which is typical
104 * for traditional TDR.
105 * - The pulse observed on the wire, triggered by the HW RESET register, is not
106 * part of the cable testing process.
107 *
108 * I assume that SSTDR seems to be a logical choice for the 10BaseT1L
109 * environment due to improved noise resistance, making it suitable for
110 * environments with significant electrical noise, such as long 10BaseT1L cable
111 * runs.
112 *
113 * Configuration Variables:
114 * The SSTDR variation used in this PHY involves more configuration variables
115 * that can dramatically affect the functionality and precision of cable
116 * testing. Since most of these configuration options are either not well
117 * documented or documented with minimal details, the following sections
118 * describe my understanding and observations of these variables and their
119 * impact on TDR functionality.
120 *
121 * Timeline:
122 * ,<--cfg_pre_silence_time
123 * | ,<-SSTDR Modulated Transmission
124 * | | ,<--cfg_post_silence_time
125 * | | | ,<--Force Link Mode
126 * |<--'-->|<-------'------->|<--'-->|<--------'------->|
127 *
128 * - cfg_pre_silence_time: Optional silence time before TDR transmission starts.
129 * - SSTDR Modulated Transmission: Transmission duration configured by
130 * cfg_tdr_tx_duration and amplitude configured by cfg_tdr_tx_type.
131 * - cfg_post_silence_time: Silence time after TDR transmission.
132 * - Force Link Mode: If nothing is configured after cfg_post_silence_time,
133 * the PHY continues in force link mode without autonegotiation.
134 */
135
136 #define DP83TD510E_TDR_CFG 0x1e
137 #define DP83TD510E_TDR_START BIT(15)
138 #define DP83TD510E_TDR_DONE BIT(1)
139 #define DP83TD510E_TDR_FAIL BIT(0)
140
141 #define DP83TD510E_TDR_CFG1 0x300
142 /* cfg_tdr_tx_type: Transmit voltage level for TDR.
143 * 0 = 1V, 1 = 2.4V
144 * Note: Using different voltage levels may not work
145 * in all configuration variations. For example, setting
146 * 2.4V may give different cable length measurements.
147 * Other settings may be needed to make it work properly.
148 */
149 #define DP83TD510E_TDR_TX_TYPE BIT(12)
150 #define DP83TD510E_TDR_TX_TYPE_1V 0
151 #define DP83TD510E_TDR_TX_TYPE_2_4V 1
152 /* cfg_post_silence_time: Time after the TDR sequence. Since we force master mode
153 * for the TDR will proceed with forced link state after this time. For Linux
154 * it is better to set max value to avoid false link state detection.
155 */
156 #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME GENMASK(3, 2)
157 #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_0MS 0
158 #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_10MS 1
159 #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_100MS 2
160 #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_1000MS 3
161 /* cfg_pre_silence_time: Time before the TDR sequence. It should be enough to
162 * settle down all pulses and reflections. Since for 10BASE-T1L we have
163 * maximum 2000m cable length, we can set it to 1ms.
164 */
165 #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME GENMASK(1, 0)
166 #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_0MS 0
167 #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_10MS 1
168 #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_100MS 2
169 #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_1000MS 3
170
171 #define DP83TD510E_TDR_CFG2 0x301
172 #define DP83TD510E_TDR_END_TAP_INDEX_1 GENMASK(14, 8)
173 #define DP83TD510E_TDR_END_TAP_INDEX_1_DEF 36
174 #define DP83TD510E_TDR_START_TAP_INDEX_1 GENMASK(6, 0)
175 #define DP83TD510E_TDR_START_TAP_INDEX_1_DEF 4
176
177 #define DP83TD510E_TDR_CFG3 0x302
178 /* cfg_tdr_tx_duration: Duration of the TDR transmission in microseconds.
179 * This value sets the duration of the modulated signal used for TDR
180 * measurements.
181 * - Default: 16000 µs
182 * - Observation: A minimum duration of 6000 µs is recommended to ensure
183 * accurate detection of cable faults. Durations shorter than 6000 µs may
184 * result in incomplete data, especially for shorter cables (e.g., 20 meters),
185 * leading to false "OK" results. Longer durations (e.g., 6000 µs or more)
186 * provide better accuracy, particularly for detecting open circuits.
187 */
188 #define DP83TD510E_TDR_TX_DURATION_US GENMASK(15, 0)
189 #define DP83TD510E_TDR_TX_DURATION_US_DEF 16000
190
191 #define DP83TD510E_TDR_FAULT_CFG1 0x303
192 #define DP83TD510E_TDR_FLT_LOC_OFFSET_1 GENMASK(14, 8)
193 #define DP83TD510E_TDR_FLT_LOC_OFFSET_1_DEF 4
194 #define DP83TD510E_TDR_FLT_INIT_1 GENMASK(7, 0)
195 #define DP83TD510E_TDR_FLT_INIT_1_DEF 62
196
197 #define DP83TD510E_TDR_FAULT_STAT 0x30c
198 #define DP83TD510E_TDR_PEAK_DETECT BIT(11)
199 #define DP83TD510E_TDR_PEAK_SIGN BIT(10)
200 #define DP83TD510E_TDR_PEAK_LOCATION GENMASK(9, 0)
201
202 /* Not documented registers and values but recommended according to
203 * "DP83TD510E Cable Diagnostics Toolkit revC"
204 */
205 #define DP83TD510E_UNKN_030E 0x30e
206 #define DP83TD510E_030E_VAL 0x2520
207
208 #define DP83TD510E_LEDS_CFG_1 0x460
209 #define DP83TD510E_LED_FN(idx, val) (((val) & 0xf) << ((idx) * 4))
210 #define DP83TD510E_LED_FN_MASK(idx) (0xf << ((idx) * 4))
211 /* link OK */
212 #define DP83TD510E_LED_MODE_LINK_OK 0x0
213 /* TX/RX activity */
214 #define DP83TD510E_LED_MODE_TX_RX_ACTIVITY 0x1
215 /* TX activity */
216 #define DP83TD510E_LED_MODE_TX_ACTIVITY 0x2
217 /* RX activity */
218 #define DP83TD510E_LED_MODE_RX_ACTIVITY 0x3
219 /* LR */
220 #define DP83TD510E_LED_MODE_LR 0x4
221 /* SR */
222 #define DP83TD510E_LED_MODE_SR 0x5
223 /* LED SPEED: High for 10Base-T */
224 #define DP83TD510E_LED_MODE_LED_SPEED 0x6
225 /* Duplex mode */
226 #define DP83TD510E_LED_MODE_DUPLEX 0x7
227 /* link + blink on activity with stretch option */
228 #define DP83TD510E_LED_MODE_LINK_BLINK 0x8
229 /* blink on activity with stretch option */
230 #define DP83TD510E_LED_MODE_BLINK_ACTIVITY 0x9
231 /* blink on tx activity with stretch option */
232 #define DP83TD510E_LED_MODE_BLINK_TX 0xa
233 /* blink on rx activity with stretch option */
234 #define DP83TD510E_LED_MODE_BLINK_RX 0xb
235 /* link_lost */
236 #define DP83TD510E_LED_MODE_LINK_LOST 0xc
237 /* PRBS error: toggles on error */
238 #define DP83TD510E_LED_MODE_PRBS_ERROR 0xd
239 /* XMII TX/RX Error with stretch option */
240 #define DP83TD510E_LED_MODE_XMII_ERR 0xe
241
242 #define DP83TD510E_LED_COUNT 4
243
244 #define DP83TD510E_LEDS_CFG_2 0x469
245 #define DP83TD510E_LED_POLARITY(idx) BIT((idx) * 4 + 2)
246 #define DP83TD510E_LED_DRV_VAL(idx) BIT((idx) * 4 + 1)
247 #define DP83TD510E_LED_DRV_EN(idx) BIT((idx) * 4)
248
249 #define DP83TD510E_ALCD_STAT 0xa9f
250 #define DP83TD510E_ALCD_COMPLETE BIT(15)
251 #define DP83TD510E_ALCD_CABLE_LENGTH GENMASK(10, 0)
252
dp83td510_get_mse_capability(struct phy_device * phydev,struct phy_mse_capability * cap)253 static int dp83td510_get_mse_capability(struct phy_device *phydev,
254 struct phy_mse_capability *cap)
255 {
256 /* DP83TD510E documents only a single (average) MSE register
257 * (used to derive SQI); no peak or worst-peak counters are
258 * described. Advertise only PHY_MSE_CAP_AVG.
259 */
260 cap->supported_caps = PHY_MSE_CAP_AVG;
261 /* 10BASE-T1L is a single-pair medium, so there are no B/C/D channels.
262 * We still advertise PHY_MSE_CAP_CHANNEL_A to indicate that the PHY
263 * can attribute the measurement to a specific pair (the only one),
264 * rather than exposing it only as a link-aggregate.
265 *
266 * Rationale:
267 * - Keeps the ethtool MSE_GET selection logic consistent: per-channel
268 * (A/B/C/D) is preferred over WORST/LINK, so userspace receives a
269 * CHANNEL_A nest instead of LINK.
270 * - Signals to tools that "per-pair" data is available (even if there's
271 * just one pair), avoiding the impression that only aggregate values
272 * are supported.
273 * - Remains compatible with multi-pair PHYs and uniform UI handling.
274 *
275 * Note: WORST and other channels are not advertised on 10BASE-T1L.
276 */
277 cap->supported_caps |= PHY_MSE_CHANNEL_A | PHY_MSE_CAP_LINK;
278 cap->max_average_mse = DP83TD510E_MSE_MAX;
279
280 /* The datasheet does not specify the refresh rate or symbol count,
281 * but based on similar PHYs and standards, we can assume a common
282 * value. For 10BASE-T1L, the symbol rate is 7.5 MBd. A common
283 * diagnostic interval is around 1ms.
284 * 7.5e6 symbols/sec * 0.001 sec = 7500 symbols.
285 */
286 cap->refresh_rate_ps = 1000000000; /* 1 ms */
287 cap->num_symbols = 7500;
288
289 return 0;
290 }
291
dp83td510_get_mse_snapshot(struct phy_device * phydev,enum phy_mse_channel channel,struct phy_mse_snapshot * snapshot)292 static int dp83td510_get_mse_snapshot(struct phy_device *phydev,
293 enum phy_mse_channel channel,
294 struct phy_mse_snapshot *snapshot)
295 {
296 int ret;
297
298 if (channel != PHY_MSE_CHANNEL_LINK &&
299 channel != PHY_MSE_CHANNEL_A)
300 return -EOPNOTSUPP;
301
302 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_MSE_DETECT);
303 if (ret < 0)
304 return ret;
305
306 snapshot->average_mse = ret;
307
308 return 0;
309 }
310
dp83td510_led_brightness_set(struct phy_device * phydev,u8 index,enum led_brightness brightness)311 static int dp83td510_led_brightness_set(struct phy_device *phydev, u8 index,
312 enum led_brightness brightness)
313 {
314 u32 val;
315
316 if (index >= DP83TD510E_LED_COUNT)
317 return -EINVAL;
318
319 val = DP83TD510E_LED_DRV_EN(index);
320
321 if (brightness)
322 val |= DP83TD510E_LED_DRV_VAL(index);
323
324 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_2,
325 DP83TD510E_LED_DRV_VAL(index) |
326 DP83TD510E_LED_DRV_EN(index), val);
327 }
328
dp83td510_led_mode(u8 index,unsigned long rules)329 static int dp83td510_led_mode(u8 index, unsigned long rules)
330 {
331 if (index >= DP83TD510E_LED_COUNT)
332 return -EINVAL;
333
334 switch (rules) {
335 case BIT(TRIGGER_NETDEV_LINK):
336 return DP83TD510E_LED_MODE_LINK_OK;
337 case BIT(TRIGGER_NETDEV_LINK_10):
338 return DP83TD510E_LED_MODE_LED_SPEED;
339 case BIT(TRIGGER_NETDEV_FULL_DUPLEX):
340 return DP83TD510E_LED_MODE_DUPLEX;
341 case BIT(TRIGGER_NETDEV_TX):
342 return DP83TD510E_LED_MODE_TX_ACTIVITY;
343 case BIT(TRIGGER_NETDEV_RX):
344 return DP83TD510E_LED_MODE_RX_ACTIVITY;
345 case BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX):
346 return DP83TD510E_LED_MODE_TX_RX_ACTIVITY;
347 case BIT(TRIGGER_NETDEV_LINK) | BIT(TRIGGER_NETDEV_TX) |
348 BIT(TRIGGER_NETDEV_RX):
349 return DP83TD510E_LED_MODE_LINK_BLINK;
350 default:
351 return -EOPNOTSUPP;
352 }
353 }
354
dp83td510_led_hw_is_supported(struct phy_device * phydev,u8 index,unsigned long rules)355 static int dp83td510_led_hw_is_supported(struct phy_device *phydev, u8 index,
356 unsigned long rules)
357 {
358 int ret;
359
360 ret = dp83td510_led_mode(index, rules);
361 if (ret < 0)
362 return ret;
363
364 return 0;
365 }
366
dp83td510_led_hw_control_set(struct phy_device * phydev,u8 index,unsigned long rules)367 static int dp83td510_led_hw_control_set(struct phy_device *phydev, u8 index,
368 unsigned long rules)
369 {
370 int mode, ret;
371
372 mode = dp83td510_led_mode(index, rules);
373 if (mode < 0)
374 return mode;
375
376 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_1,
377 DP83TD510E_LED_FN_MASK(index),
378 DP83TD510E_LED_FN(index, mode));
379 if (ret)
380 return ret;
381
382 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_2,
383 DP83TD510E_LED_DRV_EN(index), 0);
384 }
385
dp83td510_led_hw_control_get(struct phy_device * phydev,u8 index,unsigned long * rules)386 static int dp83td510_led_hw_control_get(struct phy_device *phydev,
387 u8 index, unsigned long *rules)
388 {
389 int val;
390
391 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_1);
392 if (val < 0)
393 return val;
394
395 val &= DP83TD510E_LED_FN_MASK(index);
396 val >>= index * 4;
397
398 switch (val) {
399 case DP83TD510E_LED_MODE_LINK_OK:
400 *rules = BIT(TRIGGER_NETDEV_LINK);
401 break;
402 /* LED mode: LED SPEED (10BaseT1L indicator) */
403 case DP83TD510E_LED_MODE_LED_SPEED:
404 *rules = BIT(TRIGGER_NETDEV_LINK_10);
405 break;
406 case DP83TD510E_LED_MODE_DUPLEX:
407 *rules = BIT(TRIGGER_NETDEV_FULL_DUPLEX);
408 break;
409 case DP83TD510E_LED_MODE_TX_ACTIVITY:
410 *rules = BIT(TRIGGER_NETDEV_TX);
411 break;
412 case DP83TD510E_LED_MODE_RX_ACTIVITY:
413 *rules = BIT(TRIGGER_NETDEV_RX);
414 break;
415 case DP83TD510E_LED_MODE_TX_RX_ACTIVITY:
416 *rules = BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX);
417 break;
418 case DP83TD510E_LED_MODE_LINK_BLINK:
419 *rules = BIT(TRIGGER_NETDEV_LINK) |
420 BIT(TRIGGER_NETDEV_TX) |
421 BIT(TRIGGER_NETDEV_RX);
422 break;
423 default:
424 *rules = 0;
425 break;
426 }
427
428 return 0;
429 }
430
dp83td510_led_polarity_set(struct phy_device * phydev,int index,unsigned long modes)431 static int dp83td510_led_polarity_set(struct phy_device *phydev, int index,
432 unsigned long modes)
433 {
434 u16 polarity = DP83TD510E_LED_POLARITY(index);
435 u32 mode;
436
437 for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
438 switch (mode) {
439 case PHY_LED_ACTIVE_LOW:
440 polarity = 0;
441 break;
442 case PHY_LED_ACTIVE_HIGH:
443 polarity = DP83TD510E_LED_POLARITY(index);
444 break;
445 default:
446 return -EINVAL;
447 }
448 }
449
450 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_LEDS_CFG_2,
451 DP83TD510E_LED_POLARITY(index), polarity);
452 }
453
454 /**
455 * dp83td510_update_stats - Update the PHY statistics for the DP83TD510 PHY.
456 * @phydev: Pointer to the phy_device structure.
457 *
458 * The function reads the PHY statistics registers and updates the statistics
459 * structure.
460 *
461 * Returns: 0 on success or a negative error code on failure.
462 */
dp83td510_update_stats(struct phy_device * phydev)463 static int dp83td510_update_stats(struct phy_device *phydev)
464 {
465 struct dp83td510_priv *priv = phydev->priv;
466 u32 count;
467 int ret;
468
469 /* The DP83TD510E_PKT_STAT registers are divided into two groups:
470 * - Group 1 (TX stats): DP83TD510E_PKT_STAT_1 to DP83TD510E_PKT_STAT_3
471 * - Group 2 (RX stats): DP83TD510E_PKT_STAT_4 to DP83TD510E_PKT_STAT_6
472 *
473 * Registers in each group are cleared only after reading them in a
474 * plain sequence (e.g., 1, 2, 3 for Group 1 or 4, 5, 6 for Group 2).
475 * Any deviation from the sequence, such as reading 1, 2, 1, 2, 3, will
476 * prevent the group from being cleared. Additionally, the counters
477 * for a group are frozen as soon as the first register in that group
478 * is accessed.
479 */
480 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_1);
481 if (ret < 0)
482 return ret;
483 /* tx_pkt_cnt_15_0 */
484 count = ret;
485
486 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_2);
487 if (ret < 0)
488 return ret;
489 /* tx_pkt_cnt_31_16 */
490 count |= ret << 16;
491 priv->stats.tx_pkt_cnt += count;
492
493 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_3);
494 if (ret < 0)
495 return ret;
496 /* tx_err_pkt_cnt */
497 priv->stats.tx_err_pkt_cnt += ret;
498
499 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_4);
500 if (ret < 0)
501 return ret;
502 /* rx_pkt_cnt_15_0 */
503 count = ret;
504
505 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_5);
506 if (ret < 0)
507 return ret;
508 /* rx_pkt_cnt_31_16 */
509 count |= ret << 16;
510 priv->stats.rx_pkt_cnt += count;
511
512 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_6);
513 if (ret < 0)
514 return ret;
515 /* rx_err_pkt_cnt */
516 priv->stats.rx_err_pkt_cnt += ret;
517
518 return 0;
519 }
520
dp83td510_get_phy_stats(struct phy_device * phydev,struct ethtool_eth_phy_stats * eth_stats,struct ethtool_phy_stats * stats)521 static void dp83td510_get_phy_stats(struct phy_device *phydev,
522 struct ethtool_eth_phy_stats *eth_stats,
523 struct ethtool_phy_stats *stats)
524 {
525 struct dp83td510_priv *priv = phydev->priv;
526
527 stats->tx_packets = priv->stats.tx_pkt_cnt;
528 stats->tx_errors = priv->stats.tx_err_pkt_cnt;
529 stats->rx_packets = priv->stats.rx_pkt_cnt;
530 stats->rx_errors = priv->stats.rx_err_pkt_cnt;
531 }
532
dp83td510_config_intr(struct phy_device * phydev)533 static int dp83td510_config_intr(struct phy_device *phydev)
534 {
535 int ret;
536
537 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
538 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
539 DP83TD510E_INTERRUPT_REG_1,
540 DP83TD510E_INT1_LINK_EN);
541 if (ret)
542 return ret;
543
544 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
545 DP83TD510E_GEN_CFG,
546 DP83TD510E_GENCFG_INT_POLARITY |
547 DP83TD510E_GENCFG_INT_EN |
548 DP83TD510E_GENCFG_INT_OE);
549 } else {
550 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
551 DP83TD510E_INTERRUPT_REG_1, 0x0);
552 if (ret)
553 return ret;
554
555 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
556 DP83TD510E_GEN_CFG,
557 DP83TD510E_GENCFG_INT_EN);
558 if (ret)
559 return ret;
560 }
561
562 return ret;
563 }
564
dp83td510_handle_interrupt(struct phy_device * phydev)565 static irqreturn_t dp83td510_handle_interrupt(struct phy_device *phydev)
566 {
567 int ret;
568
569 /* Read the current enabled interrupts */
570 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_INTERRUPT_REG_1);
571 if (ret < 0) {
572 phy_error(phydev);
573 return IRQ_NONE;
574 } else if (!(ret & DP83TD510E_INT1_LINK_EN) ||
575 !(ret & DP83TD510E_INT1_LINK)) {
576 return IRQ_NONE;
577 }
578
579 phy_trigger_machine(phydev);
580
581 return IRQ_HANDLED;
582 }
583
dp83td510_read_status(struct phy_device * phydev)584 static int dp83td510_read_status(struct phy_device *phydev)
585 {
586 u16 phy_sts;
587 int ret;
588
589 phydev->speed = SPEED_UNKNOWN;
590 phydev->duplex = DUPLEX_UNKNOWN;
591 phydev->pause = 0;
592 phydev->asym_pause = 0;
593 linkmode_zero(phydev->lp_advertising);
594
595 phy_sts = phy_read(phydev, DP83TD510E_PHY_STS);
596
597 phydev->link = !!(phy_sts & DP83TD510E_LINK_STATUS);
598 if (phydev->link) {
599 /* This PHY supports only one link mode: 10BaseT1L_Full */
600 phydev->duplex = DUPLEX_FULL;
601 phydev->speed = SPEED_10;
602
603 if (phydev->autoneg == AUTONEG_ENABLE) {
604 ret = genphy_c45_read_lpa(phydev);
605 if (ret)
606 return ret;
607
608 phy_resolve_aneg_linkmode(phydev);
609 }
610 }
611
612 if (phydev->autoneg == AUTONEG_ENABLE) {
613 ret = genphy_c45_baset1_read_status(phydev);
614 if (ret < 0)
615 return ret;
616
617 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
618 DP83TD510E_AN_STAT_1);
619 if (ret < 0)
620 return ret;
621
622 if (ret & DP83TD510E_MASTER_SLAVE_RESOL_FAIL)
623 phydev->master_slave_state = MASTER_SLAVE_STATE_ERR;
624 } else {
625 return genphy_c45_pma_baset1_read_master_slave(phydev);
626 }
627
628 return 0;
629 }
630
dp83td510_config_aneg(struct phy_device * phydev)631 static int dp83td510_config_aneg(struct phy_device *phydev)
632 {
633 bool changed = false;
634 int ret;
635
636 ret = genphy_c45_pma_baset1_setup_master_slave(phydev);
637 if (ret < 0)
638 return ret;
639
640 if (phydev->autoneg == AUTONEG_DISABLE)
641 return genphy_c45_an_disable_aneg(phydev);
642
643 ret = genphy_c45_an_config_aneg(phydev);
644 if (ret < 0)
645 return ret;
646 if (ret > 0)
647 changed = true;
648
649 return genphy_c45_check_and_restart_aneg(phydev, changed);
650 }
651
dp83td510_get_sqi(struct phy_device * phydev)652 static int dp83td510_get_sqi(struct phy_device *phydev)
653 {
654 int sqi, ret;
655 u16 mse_val;
656
657 if (!phydev->link)
658 return 0;
659
660 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_MSE_DETECT);
661 if (ret < 0)
662 return ret;
663
664 mse_val = 0xFFFF & ret;
665 for (sqi = 0; sqi < ARRAY_SIZE(dp83td510_mse_sqi_map); sqi++) {
666 if (mse_val >= dp83td510_mse_sqi_map[sqi])
667 return sqi;
668 }
669
670 return -EINVAL;
671 }
672
dp83td510_get_sqi_max(struct phy_device * phydev)673 static int dp83td510_get_sqi_max(struct phy_device *phydev)
674 {
675 return DP83TD510_SQI_MAX;
676 }
677
678 /**
679 * dp83td510_cable_test_start - Start the cable test for the DP83TD510 PHY.
680 * @phydev: Pointer to the phy_device structure.
681 *
682 * This sequence is implemented according to the "Application Note DP83TD510E
683 * Cable Diagnostics Toolkit revC".
684 *
685 * Returns: 0 on success, a negative error code on failure.
686 */
dp83td510_cable_test_start(struct phy_device * phydev)687 static int dp83td510_cable_test_start(struct phy_device *phydev)
688 {
689 struct dp83td510_priv *priv = phydev->priv;
690 int ret;
691
692 /* If link partner is active, we won't be able to use TDR, since
693 * we can't force link partner to be silent. The autonegotiation
694 * pulses will be too frequent and the TDR sequence will be
695 * too long. So, TDR will always fail. Since the link is established
696 * we already know that the cable is working, so we can get some
697 * extra information line the cable length using ALCD.
698 */
699 if (phydev->link) {
700 priv->alcd_test_active = true;
701 return 0;
702 }
703
704 priv->alcd_test_active = false;
705
706 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_CTRL,
707 DP83TD510E_CTRL_HW_RESET);
708 if (ret)
709 return ret;
710
711 ret = genphy_c45_an_disable_aneg(phydev);
712 if (ret)
713 return ret;
714
715 /* Force master mode */
716 ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
717 MDIO_PMA_PMD_BT1_CTRL_CFG_MST);
718 if (ret)
719 return ret;
720
721 /* There is no official recommendation for this register, but it is
722 * better to use 1V for TDR since other values seems to be optimized
723 * for this amplitude. Except of amplitude, it is better to configure
724 * pre TDR silence time to 10ms to avoid false reflections (value 0
725 * seems to be too short, otherwise we need to implement own silence
726 * time). Also, post TDR silence time should be set to 1000ms to avoid
727 * false link state detection, it fits to the polling time of the
728 * PHY framework. The idea is to wait until
729 * dp83td510_cable_test_get_status() will be called and reconfigure
730 * the PHY to the default state within the post silence time window.
731 */
732 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG1,
733 DP83TD510E_TDR_TX_TYPE |
734 DP83TD510E_TDR_CFG1_POST_SILENCE_TIME |
735 DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME,
736 DP83TD510E_TDR_TX_TYPE_1V |
737 DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_10MS |
738 DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_1000MS);
739 if (ret)
740 return ret;
741
742 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG2,
743 FIELD_PREP(DP83TD510E_TDR_END_TAP_INDEX_1,
744 DP83TD510E_TDR_END_TAP_INDEX_1_DEF) |
745 FIELD_PREP(DP83TD510E_TDR_START_TAP_INDEX_1,
746 DP83TD510E_TDR_START_TAP_INDEX_1_DEF));
747 if (ret)
748 return ret;
749
750 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_FAULT_CFG1,
751 FIELD_PREP(DP83TD510E_TDR_FLT_LOC_OFFSET_1,
752 DP83TD510E_TDR_FLT_LOC_OFFSET_1_DEF) |
753 FIELD_PREP(DP83TD510E_TDR_FLT_INIT_1,
754 DP83TD510E_TDR_FLT_INIT_1_DEF));
755 if (ret)
756 return ret;
757
758 /* Undocumented register, from the "Application Note DP83TD510E Cable
759 * Diagnostics Toolkit revC".
760 */
761 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_UNKN_030E,
762 DP83TD510E_030E_VAL);
763 if (ret)
764 return ret;
765
766 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG3,
767 DP83TD510E_TDR_TX_DURATION_US_DEF);
768 if (ret)
769 return ret;
770
771 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_CTRL,
772 DP83TD510E_CTRL_SW_RESET);
773 if (ret)
774 return ret;
775
776 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG,
777 DP83TD510E_TDR_START);
778 }
779
780 /**
781 * dp83td510_cable_test_get_tdr_status - Get the status of the TDR test for the
782 * DP83TD510 PHY.
783 * @phydev: Pointer to the phy_device structure.
784 * @finished: Pointer to a boolean that indicates whether the test is finished.
785 *
786 * The function sets the @finished flag to true if the test is complete.
787 *
788 * Returns: 0 on success or a negative error code on failure.
789 */
dp83td510_cable_test_get_tdr_status(struct phy_device * phydev,bool * finished)790 static int dp83td510_cable_test_get_tdr_status(struct phy_device *phydev,
791 bool *finished)
792 {
793 int ret, stat;
794
795 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG);
796 if (ret < 0)
797 return ret;
798
799 if (!(ret & DP83TD510E_TDR_DONE))
800 return 0;
801
802 if (!(ret & DP83TD510E_TDR_FAIL)) {
803 int location;
804
805 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
806 DP83TD510E_TDR_FAULT_STAT);
807 if (ret < 0)
808 return ret;
809
810 if (ret & DP83TD510E_TDR_PEAK_DETECT) {
811 if (ret & DP83TD510E_TDR_PEAK_SIGN)
812 stat = ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
813 else
814 stat = ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
815
816 location = FIELD_GET(DP83TD510E_TDR_PEAK_LOCATION,
817 ret) * 100;
818 ethnl_cable_test_fault_length(phydev,
819 ETHTOOL_A_CABLE_PAIR_A,
820 location);
821 } else {
822 stat = ETHTOOL_A_CABLE_RESULT_CODE_OK;
823 }
824 } else {
825 /* Most probably we have active link partner */
826 stat = ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
827 }
828
829 *finished = true;
830
831 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, stat);
832
833 return phy_init_hw(phydev);
834 }
835
836 /**
837 * dp83td510_cable_test_get_alcd_status - Get the status of the ALCD test for the
838 * DP83TD510 PHY.
839 * @phydev: Pointer to the phy_device structure.
840 * @finished: Pointer to a boolean that indicates whether the test is finished.
841 *
842 * The function sets the @finished flag to true if the test is complete.
843 * The function reads the cable length and reports it to the user.
844 *
845 * Returns: 0 on success or a negative error code on failure.
846 */
dp83td510_cable_test_get_alcd_status(struct phy_device * phydev,bool * finished)847 static int dp83td510_cable_test_get_alcd_status(struct phy_device *phydev,
848 bool *finished)
849 {
850 unsigned int location;
851 int ret, phy_sts;
852
853 phy_sts = phy_read(phydev, DP83TD510E_PHY_STS);
854
855 if (!(phy_sts & DP83TD510E_LINK_STATUS)) {
856 /* If the link is down, we can't do any thing usable now */
857 ethnl_cable_test_result_with_src(phydev, ETHTOOL_A_CABLE_PAIR_A,
858 ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC,
859 ETHTOOL_A_CABLE_INF_SRC_ALCD);
860 *finished = true;
861 return 0;
862 }
863
864 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_ALCD_STAT);
865 if (ret < 0)
866 return ret;
867
868 if (!(ret & DP83TD510E_ALCD_COMPLETE))
869 return 0;
870
871 location = FIELD_GET(DP83TD510E_ALCD_CABLE_LENGTH, ret) * 100;
872
873 ethnl_cable_test_fault_length_with_src(phydev, ETHTOOL_A_CABLE_PAIR_A,
874 location,
875 ETHTOOL_A_CABLE_INF_SRC_ALCD);
876
877 ethnl_cable_test_result_with_src(phydev, ETHTOOL_A_CABLE_PAIR_A,
878 ETHTOOL_A_CABLE_RESULT_CODE_OK,
879 ETHTOOL_A_CABLE_INF_SRC_ALCD);
880 *finished = true;
881
882 return 0;
883 }
884
885 /**
886 * dp83td510_cable_test_get_status - Get the status of the cable test for the
887 * DP83TD510 PHY.
888 * @phydev: Pointer to the phy_device structure.
889 * @finished: Pointer to a boolean that indicates whether the test is finished.
890 *
891 * The function sets the @finished flag to true if the test is complete.
892 *
893 * Returns: 0 on success or a negative error code on failure.
894 */
dp83td510_cable_test_get_status(struct phy_device * phydev,bool * finished)895 static int dp83td510_cable_test_get_status(struct phy_device *phydev,
896 bool *finished)
897 {
898 struct dp83td510_priv *priv = phydev->priv;
899 *finished = false;
900
901 if (priv->alcd_test_active)
902 return dp83td510_cable_test_get_alcd_status(phydev, finished);
903
904 return dp83td510_cable_test_get_tdr_status(phydev, finished);
905 }
906
dp83td510_get_features(struct phy_device * phydev)907 static int dp83td510_get_features(struct phy_device *phydev)
908 {
909 /* This PHY can't respond on MDIO bus if no RMII clock is enabled.
910 * In case RMII mode is used (most meaningful mode for this PHY) and
911 * the PHY do not have own XTAL, and CLK providing MAC is not probed,
912 * we won't be able to read all needed ability registers.
913 * So provide it manually.
914 */
915
916 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
917 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
918 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
919 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
920 phydev->supported);
921
922 return 0;
923 }
924
dp83td510_probe(struct phy_device * phydev)925 static int dp83td510_probe(struct phy_device *phydev)
926 {
927 struct device *dev = &phydev->mdio.dev;
928 struct dp83td510_priv *priv;
929
930 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
931 if (!priv)
932 return -ENOMEM;
933
934 phydev->priv = priv;
935
936 return 0;
937 }
938
939 static struct phy_driver dp83td510_driver[] = {
940 {
941 PHY_ID_MATCH_MODEL(DP83TD510E_PHY_ID),
942 .name = "TI DP83TD510E",
943
944 .flags = PHY_POLL_CABLE_TEST,
945 .probe = dp83td510_probe,
946 .config_aneg = dp83td510_config_aneg,
947 .read_status = dp83td510_read_status,
948 .get_features = dp83td510_get_features,
949 .config_intr = dp83td510_config_intr,
950 .handle_interrupt = dp83td510_handle_interrupt,
951 .get_sqi = dp83td510_get_sqi,
952 .get_sqi_max = dp83td510_get_sqi_max,
953 .cable_test_start = dp83td510_cable_test_start,
954 .cable_test_get_status = dp83td510_cable_test_get_status,
955 .get_phy_stats = dp83td510_get_phy_stats,
956 .update_stats = dp83td510_update_stats,
957
958 .get_mse_capability = dp83td510_get_mse_capability,
959 .get_mse_snapshot = dp83td510_get_mse_snapshot,
960
961 .led_brightness_set = dp83td510_led_brightness_set,
962 .led_hw_is_supported = dp83td510_led_hw_is_supported,
963 .led_hw_control_set = dp83td510_led_hw_control_set,
964 .led_hw_control_get = dp83td510_led_hw_control_get,
965 .led_polarity_set = dp83td510_led_polarity_set,
966
967 .suspend = genphy_suspend,
968 .resume = genphy_resume,
969 } };
970 module_phy_driver(dp83td510_driver);
971
972 static const struct mdio_device_id __maybe_unused dp83td510_tbl[] = {
973 { PHY_ID_MATCH_MODEL(DP83TD510E_PHY_ID) },
974 { }
975 };
976 MODULE_DEVICE_TABLE(mdio, dp83td510_tbl);
977
978 MODULE_DESCRIPTION("Texas Instruments DP83TD510E PHY driver");
979 MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>");
980 MODULE_LICENSE("GPL v2");
981