1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024 AIROHA Inc 4 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 5 */ 6 #include <linux/of.h> 7 #include <linux/of_net.h> 8 #include <linux/of_reserved_mem.h> 9 #include <linux/platform_device.h> 10 #include <linux/tcp.h> 11 #include <linux/u64_stats_sync.h> 12 #include <net/dst_metadata.h> 13 #include <net/page_pool/helpers.h> 14 #include <net/pkt_cls.h> 15 #include <uapi/linux/ppp_defs.h> 16 17 #include "airoha_regs.h" 18 #include "airoha_eth.h" 19 20 u32 airoha_rr(void __iomem *base, u32 offset) 21 { 22 return readl(base + offset); 23 } 24 25 void airoha_wr(void __iomem *base, u32 offset, u32 val) 26 { 27 writel(val, base + offset); 28 } 29 30 u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val) 31 { 32 val |= (airoha_rr(base, offset) & ~mask); 33 airoha_wr(base, offset, val); 34 35 return val; 36 } 37 38 static void airoha_qdma_set_irqmask(struct airoha_irq_bank *irq_bank, 39 int index, u32 clear, u32 set) 40 { 41 struct airoha_qdma *qdma = irq_bank->qdma; 42 int bank = irq_bank - &qdma->irq_banks[0]; 43 unsigned long flags; 44 45 if (WARN_ON_ONCE(index >= ARRAY_SIZE(irq_bank->irqmask))) 46 return; 47 48 spin_lock_irqsave(&irq_bank->irq_lock, flags); 49 50 irq_bank->irqmask[index] &= ~clear; 51 irq_bank->irqmask[index] |= set; 52 airoha_qdma_wr(qdma, REG_INT_ENABLE(bank, index), 53 irq_bank->irqmask[index]); 54 /* Read irq_enable register in order to guarantee the update above 55 * completes in the spinlock critical section. 56 */ 57 airoha_qdma_rr(qdma, REG_INT_ENABLE(bank, index)); 58 59 spin_unlock_irqrestore(&irq_bank->irq_lock, flags); 60 } 61 62 static void airoha_qdma_irq_enable(struct airoha_irq_bank *irq_bank, 63 int index, u32 mask) 64 { 65 airoha_qdma_set_irqmask(irq_bank, index, 0, mask); 66 } 67 68 static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank, 69 int index, u32 mask) 70 { 71 airoha_qdma_set_irqmask(irq_bank, index, mask, 0); 72 } 73 74 static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr) 75 { 76 struct airoha_eth *eth = port->qdma->eth; 77 u32 val, reg; 78 79 reg = airoha_is_lan_gdm_port(port) ? REG_FE_LAN_MAC_H 80 : REG_FE_WAN_MAC_H; 81 val = (addr[0] << 16) | (addr[1] << 8) | addr[2]; 82 airoha_fe_wr(eth, reg, val); 83 84 val = (addr[3] << 16) | (addr[4] << 8) | addr[5]; 85 airoha_fe_wr(eth, REG_FE_MAC_LMIN(reg), val); 86 airoha_fe_wr(eth, REG_FE_MAC_LMAX(reg), val); 87 88 airoha_ppe_init_upd_mem(port); 89 } 90 91 static void airoha_set_gdm_port_fwd_cfg(struct airoha_eth *eth, u32 addr, 92 u32 val) 93 { 94 airoha_fe_rmw(eth, addr, GDM_OCFQ_MASK, 95 FIELD_PREP(GDM_OCFQ_MASK, val)); 96 airoha_fe_rmw(eth, addr, GDM_MCFQ_MASK, 97 FIELD_PREP(GDM_MCFQ_MASK, val)); 98 airoha_fe_rmw(eth, addr, GDM_BCFQ_MASK, 99 FIELD_PREP(GDM_BCFQ_MASK, val)); 100 airoha_fe_rmw(eth, addr, GDM_UCFQ_MASK, 101 FIELD_PREP(GDM_UCFQ_MASK, val)); 102 } 103 104 static int airoha_set_vip_for_gdm_port(struct airoha_gdm_port *port, 105 bool enable) 106 { 107 struct airoha_eth *eth = port->qdma->eth; 108 u32 vip_port; 109 110 vip_port = eth->soc->ops.get_vip_port(port, port->nbq); 111 if (enable) { 112 airoha_fe_set(eth, REG_FE_VIP_PORT_EN, vip_port); 113 airoha_fe_set(eth, REG_FE_IFC_PORT_EN, vip_port); 114 } else { 115 airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, vip_port); 116 airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, vip_port); 117 } 118 119 return 0; 120 } 121 122 static void airoha_fe_maccr_init(struct airoha_eth *eth) 123 { 124 int p; 125 126 for (p = 1; p <= ARRAY_SIZE(eth->ports); p++) 127 airoha_fe_set(eth, REG_GDM_FWD_CFG(p), 128 GDM_TCP_CKSUM_MASK | GDM_UDP_CKSUM_MASK | 129 GDM_IP4_CKSUM_MASK | GDM_DROP_CRC_ERR_MASK); 130 131 airoha_fe_rmw(eth, REG_CDM_VLAN_CTRL(1), CDM_VLAN_MASK, 132 FIELD_PREP(CDM_VLAN_MASK, 0x8100)); 133 134 airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PAD); 135 } 136 137 static void airoha_fe_vip_setup(struct airoha_eth *eth) 138 { 139 airoha_fe_wr(eth, REG_FE_VIP_PATN(3), ETH_P_PPP_DISC); 140 airoha_fe_wr(eth, REG_FE_VIP_EN(3), PATN_FCPU_EN_MASK | PATN_EN_MASK); 141 142 airoha_fe_wr(eth, REG_FE_VIP_PATN(4), PPP_LCP); 143 airoha_fe_wr(eth, REG_FE_VIP_EN(4), 144 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 145 PATN_EN_MASK); 146 147 airoha_fe_wr(eth, REG_FE_VIP_PATN(6), PPP_IPCP); 148 airoha_fe_wr(eth, REG_FE_VIP_EN(6), 149 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 150 PATN_EN_MASK); 151 152 airoha_fe_wr(eth, REG_FE_VIP_PATN(7), PPP_CHAP); 153 airoha_fe_wr(eth, REG_FE_VIP_EN(7), 154 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 155 PATN_EN_MASK); 156 157 /* BOOTP (0x43) */ 158 airoha_fe_wr(eth, REG_FE_VIP_PATN(8), 0x43); 159 airoha_fe_wr(eth, REG_FE_VIP_EN(8), 160 PATN_FCPU_EN_MASK | PATN_SP_EN_MASK | 161 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 162 163 /* BOOTP (0x44) */ 164 airoha_fe_wr(eth, REG_FE_VIP_PATN(9), 0x44); 165 airoha_fe_wr(eth, REG_FE_VIP_EN(9), 166 PATN_FCPU_EN_MASK | PATN_SP_EN_MASK | 167 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 168 169 /* ISAKMP */ 170 airoha_fe_wr(eth, REG_FE_VIP_PATN(10), 0x1f401f4); 171 airoha_fe_wr(eth, REG_FE_VIP_EN(10), 172 PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK | 173 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 174 175 airoha_fe_wr(eth, REG_FE_VIP_PATN(11), PPP_IPV6CP); 176 airoha_fe_wr(eth, REG_FE_VIP_EN(11), 177 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 178 PATN_EN_MASK); 179 180 /* DHCPv6 */ 181 airoha_fe_wr(eth, REG_FE_VIP_PATN(12), 0x2220223); 182 airoha_fe_wr(eth, REG_FE_VIP_EN(12), 183 PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK | 184 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 185 186 airoha_fe_wr(eth, REG_FE_VIP_PATN(19), PPP_PAP); 187 airoha_fe_wr(eth, REG_FE_VIP_EN(19), 188 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 189 PATN_EN_MASK); 190 191 /* ETH->ETH_P_1905 (0x893a) */ 192 airoha_fe_wr(eth, REG_FE_VIP_PATN(20), 0x893a); 193 airoha_fe_wr(eth, REG_FE_VIP_EN(20), 194 PATN_FCPU_EN_MASK | PATN_EN_MASK); 195 196 airoha_fe_wr(eth, REG_FE_VIP_PATN(21), ETH_P_LLDP); 197 airoha_fe_wr(eth, REG_FE_VIP_EN(21), 198 PATN_FCPU_EN_MASK | PATN_EN_MASK); 199 } 200 201 static u32 airoha_fe_get_pse_queue_rsv_pages(struct airoha_eth *eth, 202 u32 port, u32 queue) 203 { 204 u32 val; 205 206 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR, 207 PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK, 208 FIELD_PREP(PSE_CFG_PORT_ID_MASK, port) | 209 FIELD_PREP(PSE_CFG_QUEUE_ID_MASK, queue)); 210 val = airoha_fe_rr(eth, REG_FE_PSE_QUEUE_CFG_VAL); 211 212 return FIELD_GET(PSE_CFG_OQ_RSV_MASK, val); 213 } 214 215 static void airoha_fe_set_pse_queue_rsv_pages(struct airoha_eth *eth, 216 u32 port, u32 queue, u32 val) 217 { 218 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_VAL, PSE_CFG_OQ_RSV_MASK, 219 FIELD_PREP(PSE_CFG_OQ_RSV_MASK, val)); 220 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR, 221 PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK | 222 PSE_CFG_WR_EN_MASK | PSE_CFG_OQRSV_SEL_MASK, 223 FIELD_PREP(PSE_CFG_PORT_ID_MASK, port) | 224 FIELD_PREP(PSE_CFG_QUEUE_ID_MASK, queue) | 225 PSE_CFG_WR_EN_MASK | PSE_CFG_OQRSV_SEL_MASK); 226 } 227 228 static u32 airoha_fe_get_pse_all_rsv(struct airoha_eth *eth) 229 { 230 u32 val = airoha_fe_rr(eth, REG_FE_PSE_BUF_SET); 231 232 return FIELD_GET(PSE_ALLRSV_MASK, val); 233 } 234 235 static int airoha_fe_set_pse_oq_rsv(struct airoha_eth *eth, 236 u32 port, u32 queue, u32 val) 237 { 238 u32 orig_val = airoha_fe_get_pse_queue_rsv_pages(eth, port, queue); 239 u32 tmp, all_rsv, fq_limit; 240 241 airoha_fe_set_pse_queue_rsv_pages(eth, port, queue, val); 242 243 /* modify all rsv */ 244 all_rsv = airoha_fe_get_pse_all_rsv(eth); 245 all_rsv += (val - orig_val); 246 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK, 247 FIELD_PREP(PSE_ALLRSV_MASK, all_rsv)); 248 249 /* modify hthd */ 250 tmp = airoha_fe_rr(eth, PSE_FQ_CFG); 251 fq_limit = FIELD_GET(PSE_FQ_LIMIT_MASK, tmp); 252 tmp = fq_limit - all_rsv - 0x20; 253 airoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD, 254 PSE_SHARE_USED_HTHD_MASK, 255 FIELD_PREP(PSE_SHARE_USED_HTHD_MASK, tmp)); 256 257 tmp = fq_limit - all_rsv - 0x100; 258 airoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD, 259 PSE_SHARE_USED_MTHD_MASK, 260 FIELD_PREP(PSE_SHARE_USED_MTHD_MASK, tmp)); 261 tmp = (3 * tmp) >> 2; 262 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, 263 PSE_SHARE_USED_LTHD_MASK, 264 FIELD_PREP(PSE_SHARE_USED_LTHD_MASK, tmp)); 265 266 return 0; 267 } 268 269 static void airoha_fe_pse_ports_init(struct airoha_eth *eth) 270 { 271 const u32 pse_port_num_queues[] = { 272 [FE_PSE_PORT_CDM1] = 6, 273 [FE_PSE_PORT_GDM1] = 6, 274 [FE_PSE_PORT_GDM2] = 32, 275 [FE_PSE_PORT_GDM3] = 6, 276 [FE_PSE_PORT_PPE1] = 4, 277 [FE_PSE_PORT_CDM2] = 6, 278 [FE_PSE_PORT_CDM3] = 8, 279 [FE_PSE_PORT_CDM4] = 10, 280 [FE_PSE_PORT_PPE2] = 4, 281 [FE_PSE_PORT_GDM4] = 2, 282 [FE_PSE_PORT_CDM5] = 2, 283 }; 284 int q; 285 286 if (airoha_ppe_is_enabled(eth, 1)) { 287 u32 all_rsv; 288 289 /* hw misses PPE2 oq rsv */ 290 all_rsv = airoha_fe_get_pse_all_rsv(eth); 291 all_rsv += PSE_RSV_PAGES * 292 pse_port_num_queues[FE_PSE_PORT_PPE2]; 293 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK, 294 FIELD_PREP(PSE_ALLRSV_MASK, all_rsv)); 295 } 296 297 /* CMD1 */ 298 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM1]; q++) 299 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM1, q, 300 PSE_QUEUE_RSV_PAGES); 301 /* GMD1 */ 302 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM1]; q++) 303 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM1, q, 304 PSE_QUEUE_RSV_PAGES); 305 /* GMD2 */ 306 for (q = 6; q < pse_port_num_queues[FE_PSE_PORT_GDM2]; q++) 307 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM2, q, 0); 308 /* GMD3 */ 309 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM3]; q++) 310 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM3, q, 311 PSE_QUEUE_RSV_PAGES); 312 /* PPE1 */ 313 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_PPE1]; q++) { 314 if (q < pse_port_num_queues[FE_PSE_PORT_PPE1]) 315 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 316 PSE_QUEUE_RSV_PAGES); 317 else 318 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 0); 319 } 320 /* CDM2 */ 321 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM2]; q++) 322 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM2, q, 323 PSE_QUEUE_RSV_PAGES); 324 /* CDM3 */ 325 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM3] - 1; q++) 326 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM3, q, 0); 327 /* CDM4 */ 328 for (q = 4; q < pse_port_num_queues[FE_PSE_PORT_CDM4]; q++) 329 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM4, q, 330 PSE_QUEUE_RSV_PAGES); 331 if (airoha_ppe_is_enabled(eth, 1)) { 332 /* PPE2 */ 333 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_PPE2]; q++) { 334 if (q < pse_port_num_queues[FE_PSE_PORT_PPE2] / 2) 335 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2, 336 q, 337 PSE_QUEUE_RSV_PAGES); 338 else 339 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2, 340 q, 0); 341 } 342 } 343 /* GMD4 */ 344 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM4]; q++) 345 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM4, q, 346 PSE_QUEUE_RSV_PAGES); 347 /* CDM5 */ 348 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM5]; q++) 349 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM5, q, 350 PSE_QUEUE_RSV_PAGES); 351 } 352 353 static int airoha_fe_mc_vlan_clear(struct airoha_eth *eth) 354 { 355 int i; 356 357 for (i = 0; i < AIROHA_FE_MC_MAX_VLAN_TABLE; i++) { 358 int err, j; 359 u32 val; 360 361 airoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0); 362 363 val = FIELD_PREP(MC_VLAN_CFG_TABLE_ID_MASK, i) | 364 MC_VLAN_CFG_TABLE_SEL_MASK | MC_VLAN_CFG_RW_MASK; 365 airoha_fe_wr(eth, REG_MC_VLAN_CFG, val); 366 err = read_poll_timeout(airoha_fe_rr, val, 367 val & MC_VLAN_CFG_CMD_DONE_MASK, 368 USEC_PER_MSEC, 5 * USEC_PER_MSEC, 369 false, eth, REG_MC_VLAN_CFG); 370 if (err) 371 return err; 372 373 for (j = 0; j < AIROHA_FE_MC_MAX_VLAN_PORT; j++) { 374 airoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0); 375 376 val = FIELD_PREP(MC_VLAN_CFG_TABLE_ID_MASK, i) | 377 FIELD_PREP(MC_VLAN_CFG_PORT_ID_MASK, j) | 378 MC_VLAN_CFG_RW_MASK; 379 airoha_fe_wr(eth, REG_MC_VLAN_CFG, val); 380 err = read_poll_timeout(airoha_fe_rr, val, 381 val & MC_VLAN_CFG_CMD_DONE_MASK, 382 USEC_PER_MSEC, 383 5 * USEC_PER_MSEC, false, eth, 384 REG_MC_VLAN_CFG); 385 if (err) 386 return err; 387 } 388 } 389 390 return 0; 391 } 392 393 static void airoha_fe_crsn_qsel_init(struct airoha_eth *eth) 394 { 395 /* CDM1_CRSN_QSEL */ 396 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_22 >> 2), 397 CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 398 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 399 CDM_CRSN_QSEL_Q1)); 400 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_08 >> 2), 401 CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 402 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 403 CDM_CRSN_QSEL_Q1)); 404 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_21 >> 2), 405 CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 406 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 407 CDM_CRSN_QSEL_Q1)); 408 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_24 >> 2), 409 CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 410 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 411 CDM_CRSN_QSEL_Q6)); 412 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_25 >> 2), 413 CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 414 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 415 CDM_CRSN_QSEL_Q1)); 416 /* CDM2_CRSN_QSEL */ 417 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_08 >> 2), 418 CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 419 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 420 CDM_CRSN_QSEL_Q1)); 421 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_21 >> 2), 422 CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 423 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 424 CDM_CRSN_QSEL_Q1)); 425 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_22 >> 2), 426 CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 427 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 428 CDM_CRSN_QSEL_Q1)); 429 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_24 >> 2), 430 CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 431 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 432 CDM_CRSN_QSEL_Q6)); 433 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_25 >> 2), 434 CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 435 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 436 CDM_CRSN_QSEL_Q1)); 437 } 438 439 static int airoha_fe_init(struct airoha_eth *eth) 440 { 441 airoha_fe_maccr_init(eth); 442 443 /* PSE IQ reserve */ 444 airoha_fe_rmw(eth, REG_PSE_IQ_REV1, PSE_IQ_RES1_P2_MASK, 445 FIELD_PREP(PSE_IQ_RES1_P2_MASK, 0x10)); 446 airoha_fe_rmw(eth, REG_PSE_IQ_REV2, 447 PSE_IQ_RES2_P5_MASK | PSE_IQ_RES2_P4_MASK, 448 FIELD_PREP(PSE_IQ_RES2_P5_MASK, 0x40) | 449 FIELD_PREP(PSE_IQ_RES2_P4_MASK, 0x34)); 450 451 /* enable FE copy engine for KA/DPI */ 452 airoha_fe_wr(eth, REG_FE_PCE_CFG, PCE_DPI_EN_MASK | PCE_KA_EN_MASK); 453 /* set vip queue selection to ring 1 */ 454 airoha_fe_rmw(eth, REG_CDM_FWD_CFG(1), CDM_VIP_QSEL_MASK, 455 FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4)); 456 airoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_VIP_QSEL_MASK, 457 FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4)); 458 /* set GDM4 source interface offset to 8 */ 459 airoha_fe_rmw(eth, REG_GDM_SRC_PORT_SET(4), 460 GDM_SPORT_OFF2_MASK | 461 GDM_SPORT_OFF1_MASK | 462 GDM_SPORT_OFF0_MASK, 463 FIELD_PREP(GDM_SPORT_OFF2_MASK, 8) | 464 FIELD_PREP(GDM_SPORT_OFF1_MASK, 8) | 465 FIELD_PREP(GDM_SPORT_OFF0_MASK, 8)); 466 467 /* set PSE Page as 128B */ 468 airoha_fe_rmw(eth, REG_FE_DMA_GLO_CFG, 469 FE_DMA_GLO_L2_SPACE_MASK | FE_DMA_GLO_PG_SZ_MASK, 470 FIELD_PREP(FE_DMA_GLO_L2_SPACE_MASK, 2) | 471 FE_DMA_GLO_PG_SZ_MASK); 472 airoha_fe_wr(eth, REG_FE_RST_GLO_CFG, 473 FE_RST_CORE_MASK | FE_RST_GDM3_MBI_ARB_MASK | 474 FE_RST_GDM4_MBI_ARB_MASK); 475 usleep_range(1000, 2000); 476 477 /* connect RxRing1 and RxRing15 to PSE Port0 OQ-1 478 * connect other rings to PSE Port0 OQ-0 479 */ 480 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP0, BIT(4)); 481 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP1, BIT(28)); 482 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP2, BIT(4)); 483 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP3, BIT(28)); 484 485 airoha_fe_vip_setup(eth); 486 airoha_fe_pse_ports_init(eth); 487 488 airoha_fe_set(eth, REG_GDM_MISC_CFG, 489 GDM2_RDM_ACK_WAIT_PREF_MASK | 490 GDM2_CHN_VLD_MODE_MASK); 491 airoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_OAM_QSEL_MASK, 492 FIELD_PREP(CDM_OAM_QSEL_MASK, 15)); 493 494 /* init fragment and assemble Force Port */ 495 /* NPU Core-3, NPU Bridge Channel-3 */ 496 airoha_fe_rmw(eth, REG_IP_FRAG_FP, 497 IP_FRAGMENT_PORT_MASK | IP_FRAGMENT_NBQ_MASK, 498 FIELD_PREP(IP_FRAGMENT_PORT_MASK, 6) | 499 FIELD_PREP(IP_FRAGMENT_NBQ_MASK, 3)); 500 /* QDMA LAN, RX Ring-22 */ 501 airoha_fe_rmw(eth, REG_IP_FRAG_FP, 502 IP_ASSEMBLE_PORT_MASK | IP_ASSEMBLE_NBQ_MASK, 503 FIELD_PREP(IP_ASSEMBLE_PORT_MASK, 0) | 504 FIELD_PREP(IP_ASSEMBLE_NBQ_MASK, 22)); 505 506 airoha_fe_set(eth, REG_GDM_FWD_CFG(AIROHA_GDM3_IDX), GDM_PAD_EN_MASK); 507 airoha_fe_set(eth, REG_GDM_FWD_CFG(AIROHA_GDM4_IDX), GDM_PAD_EN_MASK); 508 509 airoha_fe_crsn_qsel_init(eth); 510 511 airoha_fe_clear(eth, REG_FE_CPORT_CFG, FE_CPORT_QUEUE_XFC_MASK); 512 airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PORT_XFC_MASK); 513 514 /* default aging mode for mbi unlock issue */ 515 airoha_fe_rmw(eth, REG_GDM_CHN_RLS(2), 516 MBI_RX_AGE_SEL_MASK | MBI_TX_AGE_SEL_MASK, 517 FIELD_PREP(MBI_RX_AGE_SEL_MASK, 3) | 518 FIELD_PREP(MBI_TX_AGE_SEL_MASK, 3)); 519 520 /* disable IFC by default */ 521 airoha_fe_clear(eth, REG_FE_CSR_IFC_CFG, FE_IFC_EN_MASK); 522 523 /* enable 1:N vlan action, init vlan table */ 524 airoha_fe_set(eth, REG_MC_VLAN_EN, MC_VLAN_EN_MASK); 525 526 return airoha_fe_mc_vlan_clear(eth); 527 } 528 529 static int airoha_qdma_fill_rx_queue(struct airoha_queue *q) 530 { 531 struct airoha_qdma *qdma = q->qdma; 532 int qid = q - &qdma->q_rx[0]; 533 int nframes = 0; 534 535 while (q->queued < q->ndesc - 1) { 536 struct airoha_queue_entry *e = &q->entry[q->head]; 537 struct airoha_qdma_desc *desc = &q->desc[q->head]; 538 struct page *page; 539 int offset; 540 u32 val; 541 542 page = page_pool_dev_alloc_frag(q->page_pool, &offset, 543 q->buf_size); 544 if (!page) 545 break; 546 547 q->head = (q->head + 1) % q->ndesc; 548 q->queued++; 549 nframes++; 550 551 e->buf = page_address(page) + offset; 552 e->dma_addr = page_pool_get_dma_addr(page) + offset; 553 e->dma_len = SKB_WITH_OVERHEAD(q->buf_size); 554 555 val = FIELD_PREP(QDMA_DESC_LEN_MASK, e->dma_len); 556 WRITE_ONCE(desc->ctrl, cpu_to_le32(val)); 557 WRITE_ONCE(desc->addr, cpu_to_le32(e->dma_addr)); 558 val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, q->head); 559 WRITE_ONCE(desc->data, cpu_to_le32(val)); 560 WRITE_ONCE(desc->msg0, 0); 561 WRITE_ONCE(desc->msg1, 0); 562 WRITE_ONCE(desc->msg2, 0); 563 WRITE_ONCE(desc->msg3, 0); 564 } 565 566 if (nframes) 567 airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), 568 RX_RING_CPU_IDX_MASK, 569 FIELD_PREP(RX_RING_CPU_IDX_MASK, q->head)); 570 571 return nframes; 572 } 573 574 static int airoha_qdma_get_gdm_port(struct airoha_eth *eth, 575 struct airoha_qdma_desc *desc) 576 { 577 u32 port, sport, msg1 = le32_to_cpu(READ_ONCE(desc->msg1)); 578 579 sport = FIELD_GET(QDMA_ETH_RXMSG_SPORT_MASK, msg1); 580 switch (sport) { 581 case 0x10 ... 0x14: 582 port = 0; 583 break; 584 case 0x2 ... 0x4: 585 port = sport - 1; 586 break; 587 default: 588 return -EINVAL; 589 } 590 591 return port >= ARRAY_SIZE(eth->ports) ? -EINVAL : port; 592 } 593 594 static int airoha_qdma_rx_process(struct airoha_queue *q, int budget) 595 { 596 enum dma_data_direction dir = page_pool_get_dma_dir(q->page_pool); 597 struct airoha_qdma *qdma = q->qdma; 598 struct airoha_eth *eth = qdma->eth; 599 int qid = q - &qdma->q_rx[0]; 600 int done = 0; 601 602 while (done < budget) { 603 struct airoha_queue_entry *e = &q->entry[q->tail]; 604 struct airoha_qdma_desc *desc = &q->desc[q->tail]; 605 u32 hash, reason, msg1, desc_ctrl; 606 struct airoha_gdm_port *port; 607 int data_len, len, p; 608 struct page *page; 609 610 desc_ctrl = le32_to_cpu(READ_ONCE(desc->ctrl)); 611 if (!(desc_ctrl & QDMA_DESC_DONE_MASK)) 612 break; 613 614 dma_rmb(); 615 616 q->tail = (q->tail + 1) % q->ndesc; 617 q->queued--; 618 619 dma_sync_single_for_cpu(eth->dev, e->dma_addr, 620 SKB_WITH_OVERHEAD(q->buf_size), dir); 621 622 page = virt_to_head_page(e->buf); 623 len = FIELD_GET(QDMA_DESC_LEN_MASK, desc_ctrl); 624 data_len = q->skb ? q->buf_size 625 : SKB_WITH_OVERHEAD(q->buf_size); 626 if (!len || data_len < len) 627 goto free_frag; 628 629 p = airoha_qdma_get_gdm_port(eth, desc); 630 if (p < 0 || !eth->ports[p]) 631 goto free_frag; 632 633 port = eth->ports[p]; 634 if (!q->skb) { /* first buffer */ 635 q->skb = napi_build_skb(e->buf, q->buf_size); 636 if (!q->skb) 637 goto free_frag; 638 639 __skb_put(q->skb, len); 640 skb_mark_for_recycle(q->skb); 641 q->skb->dev = port->dev; 642 q->skb->protocol = eth_type_trans(q->skb, port->dev); 643 q->skb->ip_summed = CHECKSUM_UNNECESSARY; 644 skb_record_rx_queue(q->skb, qid); 645 } else { /* scattered frame */ 646 struct skb_shared_info *shinfo = skb_shinfo(q->skb); 647 int nr_frags = shinfo->nr_frags; 648 649 if (nr_frags >= ARRAY_SIZE(shinfo->frags)) 650 goto free_frag; 651 652 skb_add_rx_frag(q->skb, nr_frags, page, 653 e->buf - page_address(page), len, 654 q->buf_size); 655 } 656 657 if (FIELD_GET(QDMA_DESC_MORE_MASK, desc_ctrl)) 658 continue; 659 660 if (netdev_uses_dsa(port->dev)) { 661 /* PPE module requires untagged packets to work 662 * properly and it provides DSA port index via the 663 * DMA descriptor. Report DSA tag to the DSA stack 664 * via skb dst info. 665 */ 666 u32 msg0 = le32_to_cpu(READ_ONCE(desc->msg0)); 667 u32 sptag = FIELD_GET(QDMA_ETH_RXMSG_SPTAG, msg0); 668 669 if (sptag < ARRAY_SIZE(port->dsa_meta) && 670 port->dsa_meta[sptag]) 671 skb_dst_set_noref(q->skb, 672 &port->dsa_meta[sptag]->dst); 673 } 674 675 msg1 = le32_to_cpu(READ_ONCE(desc->msg1)); 676 hash = FIELD_GET(AIROHA_RXD4_FOE_ENTRY, msg1); 677 if (hash != AIROHA_RXD4_FOE_ENTRY) 678 skb_set_hash(q->skb, jhash_1word(hash, 0), 679 PKT_HASH_TYPE_L4); 680 681 reason = FIELD_GET(AIROHA_RXD4_PPE_CPU_REASON, msg1); 682 if (reason == PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 683 airoha_ppe_check_skb(ð->ppe->dev, q->skb, hash, 684 false); 685 686 done++; 687 napi_gro_receive(&q->napi, q->skb); 688 q->skb = NULL; 689 continue; 690 free_frag: 691 if (q->skb) { 692 dev_kfree_skb(q->skb); 693 q->skb = NULL; 694 } 695 page_pool_put_full_page(q->page_pool, page, true); 696 } 697 airoha_qdma_fill_rx_queue(q); 698 699 return done; 700 } 701 702 static int airoha_qdma_rx_napi_poll(struct napi_struct *napi, int budget) 703 { 704 struct airoha_queue *q = container_of(napi, struct airoha_queue, napi); 705 int cur, done = 0; 706 707 do { 708 cur = airoha_qdma_rx_process(q, budget - done); 709 done += cur; 710 } while (cur && done < budget); 711 712 if (done < budget && napi_complete(napi)) { 713 struct airoha_qdma *qdma = q->qdma; 714 int i, qid = q - &qdma->q_rx[0]; 715 int intr_reg = qid < RX_DONE_HIGH_OFFSET ? QDMA_INT_REG_IDX1 716 : QDMA_INT_REG_IDX2; 717 718 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 719 if (!(BIT(qid) & RX_IRQ_BANK_PIN_MASK(i))) 720 continue; 721 722 airoha_qdma_irq_enable(&qdma->irq_banks[i], intr_reg, 723 BIT(qid % RX_DONE_HIGH_OFFSET)); 724 } 725 } 726 727 return done; 728 } 729 730 static int airoha_qdma_init_rx_queue(struct airoha_queue *q, 731 struct airoha_qdma *qdma, int ndesc) 732 { 733 const struct page_pool_params pp_params = { 734 .order = 0, 735 .pool_size = 256, 736 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 737 .dma_dir = DMA_FROM_DEVICE, 738 .max_len = PAGE_SIZE, 739 .nid = NUMA_NO_NODE, 740 .dev = qdma->eth->dev, 741 .napi = &q->napi, 742 }; 743 struct airoha_eth *eth = qdma->eth; 744 int qid = q - &qdma->q_rx[0], thr; 745 dma_addr_t dma_addr; 746 747 q->buf_size = PAGE_SIZE / 2; 748 q->qdma = qdma; 749 750 q->entry = devm_kzalloc(eth->dev, ndesc * sizeof(*q->entry), 751 GFP_KERNEL); 752 if (!q->entry) 753 return -ENOMEM; 754 755 q->desc = dmam_alloc_coherent(eth->dev, ndesc * sizeof(*q->desc), 756 &dma_addr, GFP_KERNEL); 757 if (!q->desc) 758 return -ENOMEM; 759 760 q->page_pool = page_pool_create(&pp_params); 761 if (IS_ERR(q->page_pool)) { 762 int err = PTR_ERR(q->page_pool); 763 764 q->page_pool = NULL; 765 return err; 766 } 767 768 q->ndesc = ndesc; 769 netif_napi_add(eth->napi_dev, &q->napi, airoha_qdma_rx_napi_poll); 770 771 airoha_qdma_wr(qdma, REG_RX_RING_BASE(qid), dma_addr); 772 airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), 773 RX_RING_SIZE_MASK, 774 FIELD_PREP(RX_RING_SIZE_MASK, ndesc)); 775 776 thr = clamp(ndesc >> 3, 1, 32); 777 airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), RX_RING_THR_MASK, 778 FIELD_PREP(RX_RING_THR_MASK, thr)); 779 airoha_qdma_rmw(qdma, REG_RX_DMA_IDX(qid), RX_RING_DMA_IDX_MASK, 780 FIELD_PREP(RX_RING_DMA_IDX_MASK, q->head)); 781 airoha_qdma_set(qdma, REG_RX_SCATTER_CFG(qid), RX_RING_SG_EN_MASK); 782 783 airoha_qdma_fill_rx_queue(q); 784 785 return 0; 786 } 787 788 static void airoha_qdma_cleanup_rx_queue(struct airoha_queue *q) 789 { 790 struct airoha_qdma *qdma = q->qdma; 791 struct airoha_eth *eth = qdma->eth; 792 int qid = q - &qdma->q_rx[0]; 793 794 while (q->queued) { 795 struct airoha_queue_entry *e = &q->entry[q->tail]; 796 struct airoha_qdma_desc *desc = &q->desc[q->tail]; 797 struct page *page = virt_to_head_page(e->buf); 798 799 dma_sync_single_for_cpu(eth->dev, e->dma_addr, e->dma_len, 800 page_pool_get_dma_dir(q->page_pool)); 801 page_pool_put_full_page(q->page_pool, page, false); 802 /* Reset DMA descriptor */ 803 WRITE_ONCE(desc->ctrl, 0); 804 WRITE_ONCE(desc->addr, 0); 805 WRITE_ONCE(desc->data, 0); 806 WRITE_ONCE(desc->msg0, 0); 807 WRITE_ONCE(desc->msg1, 0); 808 WRITE_ONCE(desc->msg2, 0); 809 WRITE_ONCE(desc->msg3, 0); 810 811 q->tail = (q->tail + 1) % q->ndesc; 812 q->queued--; 813 } 814 815 q->head = q->tail; 816 /* Set RX_DMA_IDX to RX_CPU_IDX to notify the hw the QDMA RX ring is 817 * empty. 818 */ 819 airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), RX_RING_CPU_IDX_MASK, 820 FIELD_PREP(RX_RING_CPU_IDX_MASK, q->head)); 821 airoha_qdma_rmw(qdma, REG_RX_DMA_IDX(qid), RX_RING_DMA_IDX_MASK, 822 FIELD_PREP(RX_RING_DMA_IDX_MASK, q->tail)); 823 } 824 825 static int airoha_qdma_init_rx(struct airoha_qdma *qdma) 826 { 827 int i; 828 829 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 830 int err; 831 832 if (!(RX_DONE_INT_MASK & BIT(i))) { 833 /* rx-queue not binded to irq */ 834 continue; 835 } 836 837 err = airoha_qdma_init_rx_queue(&qdma->q_rx[i], qdma, 838 RX_DSCP_NUM(i)); 839 if (err) 840 return err; 841 } 842 843 return 0; 844 } 845 846 static void airoha_qdma_wake_netdev_txqs(struct airoha_queue *q) 847 { 848 struct airoha_qdma *qdma = q->qdma; 849 struct airoha_eth *eth = qdma->eth; 850 int i, qid = q - &qdma->q_tx[0]; 851 852 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 853 struct airoha_gdm_port *port = eth->ports[i]; 854 int j; 855 856 if (!port) 857 continue; 858 859 if (port->qdma != qdma) 860 continue; 861 862 for (j = 0; j < port->dev->num_tx_queues; j++) { 863 if (airoha_qdma_get_txq(qdma, j) != qid) 864 continue; 865 866 netif_wake_subqueue(port->dev, j); 867 } 868 } 869 q->txq_stopped = false; 870 } 871 872 static int airoha_qdma_tx_napi_poll(struct napi_struct *napi, int budget) 873 { 874 struct airoha_tx_irq_queue *irq_q; 875 int id, done = 0, irq_queued; 876 struct airoha_qdma *qdma; 877 struct airoha_eth *eth; 878 u32 status, head; 879 880 irq_q = container_of(napi, struct airoha_tx_irq_queue, napi); 881 qdma = irq_q->qdma; 882 id = irq_q - &qdma->q_tx_irq[0]; 883 eth = qdma->eth; 884 885 status = airoha_qdma_rr(qdma, REG_IRQ_STATUS(id)); 886 head = FIELD_GET(IRQ_HEAD_IDX_MASK, status); 887 head = head % irq_q->size; 888 irq_queued = FIELD_GET(IRQ_ENTRY_LEN_MASK, status); 889 890 while (irq_queued > 0 && done < budget) { 891 u32 qid, val = irq_q->q[head]; 892 struct airoha_qdma_desc *desc; 893 struct airoha_queue_entry *e; 894 struct airoha_queue *q; 895 u32 index, desc_ctrl; 896 struct sk_buff *skb; 897 898 if (val == 0xff) 899 break; 900 901 irq_q->q[head] = 0xff; /* mark as done */ 902 head = (head + 1) % irq_q->size; 903 irq_queued--; 904 done++; 905 906 qid = FIELD_GET(IRQ_RING_IDX_MASK, val); 907 if (qid >= ARRAY_SIZE(qdma->q_tx)) 908 continue; 909 910 q = &qdma->q_tx[qid]; 911 if (!q->ndesc) 912 continue; 913 914 index = FIELD_GET(IRQ_DESC_IDX_MASK, val); 915 if (index >= q->ndesc) 916 continue; 917 918 spin_lock_bh(&q->lock); 919 920 if (!q->queued) 921 goto unlock; 922 923 desc = &q->desc[index]; 924 desc_ctrl = le32_to_cpu(desc->ctrl); 925 926 if (!(desc_ctrl & QDMA_DESC_DONE_MASK) && 927 !(desc_ctrl & QDMA_DESC_DROP_MASK)) 928 goto unlock; 929 930 e = &q->entry[index]; 931 skb = e->skb; 932 933 dma_unmap_single(eth->dev, e->dma_addr, e->dma_len, 934 DMA_TO_DEVICE); 935 e->dma_addr = 0; 936 list_add_tail(&e->list, &q->tx_list); 937 938 WRITE_ONCE(desc->msg0, 0); 939 WRITE_ONCE(desc->msg1, 0); 940 q->queued--; 941 942 if (skb) { 943 struct netdev_queue *txq; 944 945 txq = skb_get_tx_queue(skb->dev, skb); 946 netdev_tx_completed_queue(txq, 1, skb->len); 947 dev_kfree_skb_any(skb); 948 } 949 950 if (q->txq_stopped && q->ndesc - q->queued >= q->free_thr) { 951 /* Since multiple net_device TX queues can share the 952 * same hw QDMA TX queue, there is no guarantee we have 953 * inflight packets queued in hw belonging to a 954 * net_device TX queue stopped in the xmit path. 955 * In order to avoid any potential net_device TX queue 956 * stall, we need to wake all the net_device TX queues 957 * feeding the same hw QDMA TX queue. 958 */ 959 airoha_qdma_wake_netdev_txqs(q); 960 } 961 962 unlock: 963 spin_unlock_bh(&q->lock); 964 } 965 966 if (done) { 967 int i, len = done >> 7; 968 969 for (i = 0; i < len; i++) 970 airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(id), 971 IRQ_CLEAR_LEN_MASK, 0x80); 972 airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(id), 973 IRQ_CLEAR_LEN_MASK, (done & 0x7f)); 974 } 975 976 if (done < budget && napi_complete(napi)) 977 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0, 978 TX_DONE_INT_MASK(id)); 979 980 return done; 981 } 982 983 static int airoha_qdma_init_tx_queue(struct airoha_queue *q, 984 struct airoha_qdma *qdma, int size) 985 { 986 struct airoha_eth *eth = qdma->eth; 987 int i, qid = q - &qdma->q_tx[0]; 988 dma_addr_t dma_addr; 989 990 spin_lock_init(&q->lock); 991 q->qdma = qdma; 992 q->free_thr = 1 + MAX_SKB_FRAGS; 993 INIT_LIST_HEAD(&q->tx_list); 994 995 q->entry = devm_kzalloc(eth->dev, size * sizeof(*q->entry), 996 GFP_KERNEL); 997 if (!q->entry) 998 return -ENOMEM; 999 1000 q->desc = dmam_alloc_coherent(eth->dev, size * sizeof(*q->desc), 1001 &dma_addr, GFP_KERNEL); 1002 if (!q->desc) 1003 return -ENOMEM; 1004 1005 for (i = 0; i < size; i++) { 1006 u32 val = FIELD_PREP(QDMA_DESC_DONE_MASK, 1); 1007 1008 list_add_tail(&q->entry[i].list, &q->tx_list); 1009 WRITE_ONCE(q->desc[i].ctrl, cpu_to_le32(val)); 1010 } 1011 q->ndesc = size; 1012 1013 /* xmit ring drop default setting */ 1014 airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(qid), 1015 TX_RING_IRQ_BLOCKING_TX_DROP_EN_MASK); 1016 1017 airoha_qdma_wr(qdma, REG_TX_RING_BASE(qid), dma_addr); 1018 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK, 1019 FIELD_PREP(TX_RING_CPU_IDX_MASK, 0)); 1020 airoha_qdma_rmw(qdma, REG_TX_DMA_IDX(qid), TX_RING_DMA_IDX_MASK, 1021 FIELD_PREP(TX_RING_DMA_IDX_MASK, 0)); 1022 1023 return 0; 1024 } 1025 1026 static int airoha_qdma_tx_irq_init(struct airoha_tx_irq_queue *irq_q, 1027 struct airoha_qdma *qdma, int size) 1028 { 1029 int id = irq_q - &qdma->q_tx_irq[0]; 1030 struct airoha_eth *eth = qdma->eth; 1031 dma_addr_t dma_addr; 1032 1033 irq_q->q = dmam_alloc_coherent(eth->dev, size * sizeof(u32), 1034 &dma_addr, GFP_KERNEL); 1035 if (!irq_q->q) 1036 return -ENOMEM; 1037 1038 memset(irq_q->q, 0xff, size * sizeof(u32)); 1039 irq_q->size = size; 1040 irq_q->qdma = qdma; 1041 1042 netif_napi_add_tx(eth->napi_dev, &irq_q->napi, 1043 airoha_qdma_tx_napi_poll); 1044 1045 airoha_qdma_wr(qdma, REG_TX_IRQ_BASE(id), dma_addr); 1046 airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_DEPTH_MASK, 1047 FIELD_PREP(TX_IRQ_DEPTH_MASK, size)); 1048 airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_THR_MASK, 1049 FIELD_PREP(TX_IRQ_THR_MASK, 1)); 1050 1051 return 0; 1052 } 1053 1054 static int airoha_qdma_init_tx(struct airoha_qdma *qdma) 1055 { 1056 int i, err; 1057 1058 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) { 1059 err = airoha_qdma_tx_irq_init(&qdma->q_tx_irq[i], qdma, 1060 IRQ_QUEUE_LEN(i)); 1061 if (err) 1062 return err; 1063 } 1064 1065 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1066 err = airoha_qdma_init_tx_queue(&qdma->q_tx[i], qdma, 1067 TX_DSCP_NUM); 1068 if (err) 1069 return err; 1070 } 1071 1072 return 0; 1073 } 1074 1075 static void airoha_qdma_cleanup_tx_queue(struct airoha_queue *q) 1076 { 1077 struct airoha_qdma *qdma = q->qdma; 1078 struct airoha_eth *eth = qdma->eth; 1079 int i, qid = q - &qdma->q_tx[0]; 1080 u16 index = 0; 1081 1082 spin_lock_bh(&q->lock); 1083 for (i = 0; i < q->ndesc; i++) { 1084 struct airoha_queue_entry *e = &q->entry[i]; 1085 struct airoha_qdma_desc *desc = &q->desc[i]; 1086 1087 if (!e->dma_addr) 1088 continue; 1089 1090 dma_unmap_single(eth->dev, e->dma_addr, e->dma_len, 1091 DMA_TO_DEVICE); 1092 dev_kfree_skb_any(e->skb); 1093 e->dma_addr = 0; 1094 e->skb = NULL; 1095 list_add_tail(&e->list, &q->tx_list); 1096 1097 /* Reset DMA descriptor */ 1098 WRITE_ONCE(desc->ctrl, 0); 1099 WRITE_ONCE(desc->addr, 0); 1100 WRITE_ONCE(desc->data, 0); 1101 WRITE_ONCE(desc->msg0, 0); 1102 WRITE_ONCE(desc->msg1, 0); 1103 WRITE_ONCE(desc->msg2, 0); 1104 1105 q->queued--; 1106 } 1107 1108 if (!list_empty(&q->tx_list)) { 1109 struct airoha_queue_entry *e; 1110 1111 e = list_first_entry(&q->tx_list, struct airoha_queue_entry, 1112 list); 1113 index = e - q->entry; 1114 } 1115 /* Set TX_DMA_IDX to TX_CPU_IDX to notify the hw the QDMA TX ring is 1116 * empty. 1117 */ 1118 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK, 1119 FIELD_PREP(TX_RING_CPU_IDX_MASK, index)); 1120 airoha_qdma_rmw(qdma, REG_TX_DMA_IDX(qid), TX_RING_DMA_IDX_MASK, 1121 FIELD_PREP(TX_RING_DMA_IDX_MASK, index)); 1122 1123 spin_unlock_bh(&q->lock); 1124 } 1125 1126 static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma) 1127 { 1128 int size, index, num_desc = HW_DSCP_NUM; 1129 struct airoha_eth *eth = qdma->eth; 1130 int id = qdma - ð->qdma[0]; 1131 u32 status, buf_size; 1132 dma_addr_t dma_addr; 1133 const char *name; 1134 1135 name = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d-buf", id); 1136 if (!name) 1137 return -ENOMEM; 1138 1139 buf_size = id ? AIROHA_MAX_PACKET_SIZE / 2 : AIROHA_MAX_PACKET_SIZE; 1140 index = of_property_match_string(eth->dev->of_node, 1141 "memory-region-names", name); 1142 if (index >= 0) { 1143 struct reserved_mem *rmem; 1144 struct device_node *np; 1145 1146 /* Consume reserved memory for hw forwarding buffers queue if 1147 * available in the DTS 1148 */ 1149 np = of_parse_phandle(eth->dev->of_node, "memory-region", 1150 index); 1151 if (!np) 1152 return -ENODEV; 1153 1154 rmem = of_reserved_mem_lookup(np); 1155 of_node_put(np); 1156 if (!rmem) 1157 return -ENODEV; 1158 1159 dma_addr = rmem->base; 1160 /* Compute the number of hw descriptors according to the 1161 * reserved memory size and the payload buffer size 1162 */ 1163 num_desc = div_u64(rmem->size, buf_size); 1164 } else { 1165 size = buf_size * num_desc; 1166 if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, 1167 GFP_KERNEL)) 1168 return -ENOMEM; 1169 } 1170 1171 airoha_qdma_wr(qdma, REG_FWD_BUF_BASE, dma_addr); 1172 1173 size = num_desc * sizeof(struct airoha_qdma_fwd_desc); 1174 if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, GFP_KERNEL)) 1175 return -ENOMEM; 1176 1177 airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr); 1178 /* QDMA0: 2KB. QDMA1: 1KB */ 1179 airoha_qdma_rmw(qdma, REG_HW_FWD_DSCP_CFG, 1180 HW_FWD_DSCP_PAYLOAD_SIZE_MASK, 1181 FIELD_PREP(HW_FWD_DSCP_PAYLOAD_SIZE_MASK, !!id)); 1182 airoha_qdma_rmw(qdma, REG_FWD_DSCP_LOW_THR, FWD_DSCP_LOW_THR_MASK, 1183 FIELD_PREP(FWD_DSCP_LOW_THR_MASK, 128)); 1184 airoha_qdma_rmw(qdma, REG_LMGR_INIT_CFG, 1185 LMGR_INIT_START | LMGR_SRAM_MODE_MASK | 1186 HW_FWD_DESC_NUM_MASK, 1187 FIELD_PREP(HW_FWD_DESC_NUM_MASK, num_desc) | 1188 LMGR_INIT_START | LMGR_SRAM_MODE_MASK); 1189 1190 return read_poll_timeout(airoha_qdma_rr, status, 1191 !(status & LMGR_INIT_START), USEC_PER_MSEC, 1192 30 * USEC_PER_MSEC, true, qdma, 1193 REG_LMGR_INIT_CFG); 1194 } 1195 1196 static void airoha_qdma_init_qos(struct airoha_qdma *qdma) 1197 { 1198 airoha_qdma_clear(qdma, REG_TXWRR_MODE_CFG, TWRR_WEIGHT_SCALE_MASK); 1199 airoha_qdma_set(qdma, REG_TXWRR_MODE_CFG, TWRR_WEIGHT_BASE_MASK); 1200 1201 airoha_qdma_clear(qdma, REG_PSE_BUF_USAGE_CFG, 1202 PSE_BUF_ESTIMATE_EN_MASK); 1203 1204 airoha_qdma_set(qdma, REG_EGRESS_RATE_METER_CFG, 1205 EGRESS_RATE_METER_EN_MASK | 1206 EGRESS_RATE_METER_EQ_RATE_EN_MASK); 1207 /* 2047us x 31 = 63.457ms */ 1208 airoha_qdma_rmw(qdma, REG_EGRESS_RATE_METER_CFG, 1209 EGRESS_RATE_METER_WINDOW_SZ_MASK, 1210 FIELD_PREP(EGRESS_RATE_METER_WINDOW_SZ_MASK, 0x1f)); 1211 airoha_qdma_rmw(qdma, REG_EGRESS_RATE_METER_CFG, 1212 EGRESS_RATE_METER_TIMESLICE_MASK, 1213 FIELD_PREP(EGRESS_RATE_METER_TIMESLICE_MASK, 0x7ff)); 1214 1215 /* ratelimit init */ 1216 airoha_qdma_set(qdma, REG_GLB_TRTCM_CFG, GLB_TRTCM_EN_MASK); 1217 /* fast-tick 25us */ 1218 airoha_qdma_rmw(qdma, REG_GLB_TRTCM_CFG, GLB_FAST_TICK_MASK, 1219 FIELD_PREP(GLB_FAST_TICK_MASK, 25)); 1220 airoha_qdma_rmw(qdma, REG_GLB_TRTCM_CFG, GLB_SLOW_TICK_RATIO_MASK, 1221 FIELD_PREP(GLB_SLOW_TICK_RATIO_MASK, 40)); 1222 1223 airoha_qdma_set(qdma, REG_EGRESS_TRTCM_CFG, EGRESS_TRTCM_EN_MASK); 1224 airoha_qdma_rmw(qdma, REG_EGRESS_TRTCM_CFG, EGRESS_FAST_TICK_MASK, 1225 FIELD_PREP(EGRESS_FAST_TICK_MASK, 25)); 1226 airoha_qdma_rmw(qdma, REG_EGRESS_TRTCM_CFG, 1227 EGRESS_SLOW_TICK_RATIO_MASK, 1228 FIELD_PREP(EGRESS_SLOW_TICK_RATIO_MASK, 40)); 1229 1230 airoha_qdma_set(qdma, REG_INGRESS_TRTCM_CFG, INGRESS_TRTCM_EN_MASK); 1231 airoha_qdma_clear(qdma, REG_INGRESS_TRTCM_CFG, 1232 INGRESS_TRTCM_MODE_MASK); 1233 airoha_qdma_rmw(qdma, REG_INGRESS_TRTCM_CFG, INGRESS_FAST_TICK_MASK, 1234 FIELD_PREP(INGRESS_FAST_TICK_MASK, 125)); 1235 airoha_qdma_rmw(qdma, REG_INGRESS_TRTCM_CFG, 1236 INGRESS_SLOW_TICK_RATIO_MASK, 1237 FIELD_PREP(INGRESS_SLOW_TICK_RATIO_MASK, 8)); 1238 1239 airoha_qdma_set(qdma, REG_SLA_TRTCM_CFG, SLA_TRTCM_EN_MASK); 1240 airoha_qdma_rmw(qdma, REG_SLA_TRTCM_CFG, SLA_FAST_TICK_MASK, 1241 FIELD_PREP(SLA_FAST_TICK_MASK, 25)); 1242 airoha_qdma_rmw(qdma, REG_SLA_TRTCM_CFG, SLA_SLOW_TICK_RATIO_MASK, 1243 FIELD_PREP(SLA_SLOW_TICK_RATIO_MASK, 40)); 1244 } 1245 1246 static void airoha_qdma_init_qos_stats(struct airoha_qdma *qdma) 1247 { 1248 int i; 1249 1250 for (i = 0; i < AIROHA_NUM_QOS_CHANNELS; i++) { 1251 /* Tx-cpu transferred count */ 1252 airoha_qdma_wr(qdma, REG_CNTR_VAL(i << 1), 0); 1253 airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1), 1254 CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK | 1255 CNTR_ALL_DSCP_RING_EN_MASK | 1256 FIELD_PREP(CNTR_CHAN_MASK, i)); 1257 /* Tx-fwd transferred count */ 1258 airoha_qdma_wr(qdma, REG_CNTR_VAL((i << 1) + 1), 0); 1259 airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1), 1260 CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK | 1261 CNTR_ALL_DSCP_RING_EN_MASK | 1262 FIELD_PREP(CNTR_SRC_MASK, 1) | 1263 FIELD_PREP(CNTR_CHAN_MASK, i)); 1264 } 1265 } 1266 1267 static int airoha_qdma_hw_init(struct airoha_qdma *qdma) 1268 { 1269 int i; 1270 1271 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 1272 /* clear pending irqs */ 1273 airoha_qdma_wr(qdma, REG_INT_STATUS(i), 0xffffffff); 1274 /* setup rx irqs */ 1275 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX0, 1276 INT_RX0_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1277 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX1, 1278 INT_RX1_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1279 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX2, 1280 INT_RX2_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1281 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX3, 1282 INT_RX3_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1283 } 1284 /* setup tx irqs */ 1285 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0, 1286 TX_COHERENT_LOW_INT_MASK | INT_TX_MASK); 1287 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX4, 1288 TX_COHERENT_HIGH_INT_MASK); 1289 1290 /* setup irq binding */ 1291 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1292 if (!qdma->q_tx[i].ndesc) 1293 continue; 1294 1295 if (TX_RING_IRQ_BLOCKING_MAP_MASK & BIT(i)) 1296 airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(i), 1297 TX_RING_IRQ_BLOCKING_CFG_MASK); 1298 else 1299 airoha_qdma_clear(qdma, REG_TX_RING_BLOCKING(i), 1300 TX_RING_IRQ_BLOCKING_CFG_MASK); 1301 } 1302 1303 airoha_qdma_wr(qdma, REG_QDMA_GLOBAL_CFG, 1304 FIELD_PREP(GLOBAL_CFG_DMA_PREFERENCE_MASK, 3) | 1305 GLOBAL_CFG_CPU_TXR_RR_MASK | 1306 GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK | 1307 GLOBAL_CFG_MULTICAST_MODIFY_FP_MASK | 1308 GLOBAL_CFG_MULTICAST_EN_MASK | 1309 GLOBAL_CFG_IRQ0_EN_MASK | GLOBAL_CFG_IRQ1_EN_MASK | 1310 GLOBAL_CFG_TX_WB_DONE_MASK | 1311 FIELD_PREP(GLOBAL_CFG_MAX_ISSUE_NUM_MASK, 2)); 1312 1313 airoha_qdma_init_qos(qdma); 1314 1315 /* disable qdma rx delay interrupt */ 1316 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1317 if (!qdma->q_rx[i].ndesc) 1318 continue; 1319 1320 airoha_qdma_clear(qdma, REG_RX_DELAY_INT_IDX(i), 1321 RX_DELAY_INT_MASK); 1322 } 1323 1324 airoha_qdma_set(qdma, REG_TXQ_CNGST_CFG, 1325 TXQ_CNGST_DROP_EN | TXQ_CNGST_DEI_DROP_EN); 1326 airoha_qdma_init_qos_stats(qdma); 1327 1328 return 0; 1329 } 1330 1331 static irqreturn_t airoha_irq_handler(int irq, void *dev_instance) 1332 { 1333 struct airoha_irq_bank *irq_bank = dev_instance; 1334 struct airoha_qdma *qdma = irq_bank->qdma; 1335 u32 rx_intr_mask = 0, rx_intr1, rx_intr2; 1336 u32 intr[ARRAY_SIZE(irq_bank->irqmask)]; 1337 int i; 1338 1339 for (i = 0; i < ARRAY_SIZE(intr); i++) { 1340 intr[i] = airoha_qdma_rr(qdma, REG_INT_STATUS(i)); 1341 intr[i] &= irq_bank->irqmask[i]; 1342 airoha_qdma_wr(qdma, REG_INT_STATUS(i), intr[i]); 1343 } 1344 1345 if (!test_bit(DEV_STATE_INITIALIZED, &qdma->eth->state)) 1346 return IRQ_NONE; 1347 1348 rx_intr1 = intr[1] & RX_DONE_LOW_INT_MASK; 1349 if (rx_intr1) { 1350 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX1, rx_intr1); 1351 rx_intr_mask |= rx_intr1; 1352 } 1353 1354 rx_intr2 = intr[2] & RX_DONE_HIGH_INT_MASK; 1355 if (rx_intr2) { 1356 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX2, rx_intr2); 1357 rx_intr_mask |= (rx_intr2 << 16); 1358 } 1359 1360 for (i = 0; rx_intr_mask && i < ARRAY_SIZE(qdma->q_rx); i++) { 1361 if (!qdma->q_rx[i].ndesc) 1362 continue; 1363 1364 if (rx_intr_mask & BIT(i)) 1365 napi_schedule(&qdma->q_rx[i].napi); 1366 } 1367 1368 if (intr[0] & INT_TX_MASK) { 1369 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) { 1370 if (!(intr[0] & TX_DONE_INT_MASK(i))) 1371 continue; 1372 1373 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX0, 1374 TX_DONE_INT_MASK(i)); 1375 napi_schedule(&qdma->q_tx_irq[i].napi); 1376 } 1377 } 1378 1379 return IRQ_HANDLED; 1380 } 1381 1382 static int airoha_qdma_init_irq_banks(struct platform_device *pdev, 1383 struct airoha_qdma *qdma) 1384 { 1385 struct airoha_eth *eth = qdma->eth; 1386 int i, id = qdma - ð->qdma[0]; 1387 1388 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 1389 struct airoha_irq_bank *irq_bank = &qdma->irq_banks[i]; 1390 int err, irq_index = 4 * id + i; 1391 const char *name; 1392 1393 spin_lock_init(&irq_bank->irq_lock); 1394 irq_bank->qdma = qdma; 1395 1396 irq_bank->irq = platform_get_irq(pdev, irq_index); 1397 if (irq_bank->irq < 0) 1398 return irq_bank->irq; 1399 1400 name = devm_kasprintf(eth->dev, GFP_KERNEL, 1401 KBUILD_MODNAME ".%d", irq_index); 1402 if (!name) 1403 return -ENOMEM; 1404 1405 err = devm_request_irq(eth->dev, irq_bank->irq, 1406 airoha_irq_handler, IRQF_SHARED, name, 1407 irq_bank); 1408 if (err) 1409 return err; 1410 } 1411 1412 return 0; 1413 } 1414 1415 static int airoha_qdma_init(struct platform_device *pdev, 1416 struct airoha_eth *eth, 1417 struct airoha_qdma *qdma) 1418 { 1419 int err, id = qdma - ð->qdma[0]; 1420 const char *res; 1421 1422 qdma->eth = eth; 1423 res = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d", id); 1424 if (!res) 1425 return -ENOMEM; 1426 1427 qdma->regs = devm_platform_ioremap_resource_byname(pdev, res); 1428 if (IS_ERR(qdma->regs)) 1429 return dev_err_probe(eth->dev, PTR_ERR(qdma->regs), 1430 "failed to iomap qdma%d regs\n", id); 1431 1432 err = airoha_qdma_init_irq_banks(pdev, qdma); 1433 if (err) 1434 return err; 1435 1436 err = airoha_qdma_init_rx(qdma); 1437 if (err) 1438 return err; 1439 1440 err = airoha_qdma_init_tx(qdma); 1441 if (err) 1442 return err; 1443 1444 err = airoha_qdma_init_hfwd_queues(qdma); 1445 if (err) 1446 return err; 1447 1448 return airoha_qdma_hw_init(qdma); 1449 } 1450 1451 static void airoha_qdma_cleanup(struct airoha_qdma *qdma) 1452 { 1453 int i; 1454 1455 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1456 if (!qdma->q_rx[i].ndesc) 1457 continue; 1458 1459 netif_napi_del(&qdma->q_rx[i].napi); 1460 airoha_qdma_cleanup_rx_queue(&qdma->q_rx[i]); 1461 if (qdma->q_rx[i].page_pool) { 1462 page_pool_destroy(qdma->q_rx[i].page_pool); 1463 qdma->q_rx[i].page_pool = NULL; 1464 } 1465 } 1466 1467 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) { 1468 if (!qdma->q_tx_irq[i].size) 1469 continue; 1470 1471 netif_napi_del(&qdma->q_tx_irq[i].napi); 1472 } 1473 1474 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1475 if (!qdma->q_tx[i].ndesc) 1476 continue; 1477 1478 airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]); 1479 } 1480 } 1481 1482 static int airoha_hw_init(struct platform_device *pdev, 1483 struct airoha_eth *eth) 1484 { 1485 int err, i; 1486 1487 /* disable xsi */ 1488 err = reset_control_bulk_assert(eth->soc->num_xsi_rsts, eth->xsi_rsts); 1489 if (err) 1490 return err; 1491 1492 err = reset_control_bulk_assert(ARRAY_SIZE(eth->rsts), eth->rsts); 1493 if (err) 1494 return err; 1495 1496 msleep(20); 1497 err = reset_control_bulk_deassert(ARRAY_SIZE(eth->rsts), eth->rsts); 1498 if (err) 1499 return err; 1500 1501 msleep(20); 1502 err = airoha_fe_init(eth); 1503 if (err) 1504 return err; 1505 1506 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) { 1507 err = airoha_qdma_init(pdev, eth, ð->qdma[i]); 1508 if (err) 1509 goto error; 1510 } 1511 1512 err = airoha_ppe_init(eth); 1513 if (err) 1514 goto error; 1515 1516 set_bit(DEV_STATE_INITIALIZED, ð->state); 1517 1518 return 0; 1519 error: 1520 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 1521 airoha_qdma_cleanup(ð->qdma[i]); 1522 1523 return err; 1524 } 1525 1526 static void airoha_hw_cleanup(struct airoha_eth *eth) 1527 { 1528 int i; 1529 1530 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 1531 airoha_qdma_cleanup(ð->qdma[i]); 1532 airoha_ppe_deinit(eth); 1533 } 1534 1535 static void airoha_qdma_start_napi(struct airoha_qdma *qdma) 1536 { 1537 int i; 1538 1539 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) 1540 napi_enable(&qdma->q_tx_irq[i].napi); 1541 1542 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1543 if (!qdma->q_rx[i].ndesc) 1544 continue; 1545 1546 napi_enable(&qdma->q_rx[i].napi); 1547 } 1548 } 1549 1550 static void airoha_qdma_stop_napi(struct airoha_qdma *qdma) 1551 { 1552 int i; 1553 1554 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) 1555 napi_disable(&qdma->q_tx_irq[i].napi); 1556 1557 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1558 if (!qdma->q_rx[i].ndesc) 1559 continue; 1560 1561 napi_disable(&qdma->q_rx[i].napi); 1562 } 1563 } 1564 1565 static void airoha_update_hw_stats(struct airoha_gdm_port *port) 1566 { 1567 struct airoha_eth *eth = port->qdma->eth; 1568 u32 val, i = 0; 1569 1570 spin_lock(&port->stats.lock); 1571 u64_stats_update_begin(&port->stats.syncp); 1572 1573 /* TX */ 1574 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_PKT_CNT_H(port->id)); 1575 port->stats.tx_ok_pkts += ((u64)val << 32); 1576 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_PKT_CNT_L(port->id)); 1577 port->stats.tx_ok_pkts += val; 1578 1579 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_BYTE_CNT_H(port->id)); 1580 port->stats.tx_ok_bytes += ((u64)val << 32); 1581 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_BYTE_CNT_L(port->id)); 1582 port->stats.tx_ok_bytes += val; 1583 1584 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_DROP_CNT(port->id)); 1585 port->stats.tx_drops += val; 1586 1587 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_BC_CNT(port->id)); 1588 port->stats.tx_broadcast += val; 1589 1590 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_MC_CNT(port->id)); 1591 port->stats.tx_multicast += val; 1592 1593 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_RUNT_CNT(port->id)); 1594 port->stats.tx_len[i] += val; 1595 1596 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_E64_CNT_H(port->id)); 1597 port->stats.tx_len[i] += ((u64)val << 32); 1598 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_E64_CNT_L(port->id)); 1599 port->stats.tx_len[i++] += val; 1600 1601 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L64_CNT_H(port->id)); 1602 port->stats.tx_len[i] += ((u64)val << 32); 1603 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L64_CNT_L(port->id)); 1604 port->stats.tx_len[i++] += val; 1605 1606 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L127_CNT_H(port->id)); 1607 port->stats.tx_len[i] += ((u64)val << 32); 1608 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L127_CNT_L(port->id)); 1609 port->stats.tx_len[i++] += val; 1610 1611 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L255_CNT_H(port->id)); 1612 port->stats.tx_len[i] += ((u64)val << 32); 1613 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L255_CNT_L(port->id)); 1614 port->stats.tx_len[i++] += val; 1615 1616 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L511_CNT_H(port->id)); 1617 port->stats.tx_len[i] += ((u64)val << 32); 1618 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L511_CNT_L(port->id)); 1619 port->stats.tx_len[i++] += val; 1620 1621 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L1023_CNT_H(port->id)); 1622 port->stats.tx_len[i] += ((u64)val << 32); 1623 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L1023_CNT_L(port->id)); 1624 port->stats.tx_len[i++] += val; 1625 1626 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_LONG_CNT(port->id)); 1627 port->stats.tx_len[i++] += val; 1628 1629 /* RX */ 1630 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_PKT_CNT_H(port->id)); 1631 port->stats.rx_ok_pkts += ((u64)val << 32); 1632 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_PKT_CNT_L(port->id)); 1633 port->stats.rx_ok_pkts += val; 1634 1635 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_BYTE_CNT_H(port->id)); 1636 port->stats.rx_ok_bytes += ((u64)val << 32); 1637 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_BYTE_CNT_L(port->id)); 1638 port->stats.rx_ok_bytes += val; 1639 1640 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_DROP_CNT(port->id)); 1641 port->stats.rx_drops += val; 1642 1643 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_BC_CNT(port->id)); 1644 port->stats.rx_broadcast += val; 1645 1646 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_MC_CNT(port->id)); 1647 port->stats.rx_multicast += val; 1648 1649 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ERROR_DROP_CNT(port->id)); 1650 port->stats.rx_errors += val; 1651 1652 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_CRC_ERR_CNT(port->id)); 1653 port->stats.rx_crc_error += val; 1654 1655 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OVERFLOW_DROP_CNT(port->id)); 1656 port->stats.rx_over_errors += val; 1657 1658 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_FRAG_CNT(port->id)); 1659 port->stats.rx_fragment += val; 1660 1661 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_JABBER_CNT(port->id)); 1662 port->stats.rx_jabber += val; 1663 1664 i = 0; 1665 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_RUNT_CNT(port->id)); 1666 port->stats.rx_len[i] += val; 1667 1668 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_E64_CNT_H(port->id)); 1669 port->stats.rx_len[i] += ((u64)val << 32); 1670 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_E64_CNT_L(port->id)); 1671 port->stats.rx_len[i++] += val; 1672 1673 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L64_CNT_H(port->id)); 1674 port->stats.rx_len[i] += ((u64)val << 32); 1675 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L64_CNT_L(port->id)); 1676 port->stats.rx_len[i++] += val; 1677 1678 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L127_CNT_H(port->id)); 1679 port->stats.rx_len[i] += ((u64)val << 32); 1680 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L127_CNT_L(port->id)); 1681 port->stats.rx_len[i++] += val; 1682 1683 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L255_CNT_H(port->id)); 1684 port->stats.rx_len[i] += ((u64)val << 32); 1685 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L255_CNT_L(port->id)); 1686 port->stats.rx_len[i++] += val; 1687 1688 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L511_CNT_H(port->id)); 1689 port->stats.rx_len[i] += ((u64)val << 32); 1690 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L511_CNT_L(port->id)); 1691 port->stats.rx_len[i++] += val; 1692 1693 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L1023_CNT_H(port->id)); 1694 port->stats.rx_len[i] += ((u64)val << 32); 1695 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L1023_CNT_L(port->id)); 1696 port->stats.rx_len[i++] += val; 1697 1698 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_LONG_CNT(port->id)); 1699 port->stats.rx_len[i++] += val; 1700 1701 /* reset mib counters */ 1702 airoha_fe_set(eth, REG_FE_GDM_MIB_CLEAR(port->id), 1703 FE_GDM_MIB_RX_CLEAR_MASK | FE_GDM_MIB_TX_CLEAR_MASK); 1704 1705 u64_stats_update_end(&port->stats.syncp); 1706 spin_unlock(&port->stats.lock); 1707 } 1708 1709 static int airoha_dev_open(struct net_device *dev) 1710 { 1711 int err, len = ETH_HLEN + dev->mtu + ETH_FCS_LEN; 1712 struct airoha_gdm_port *port = netdev_priv(dev); 1713 struct airoha_qdma *qdma = port->qdma; 1714 u32 pse_port = FE_PSE_PORT_PPE1; 1715 1716 netif_tx_start_all_queues(dev); 1717 err = airoha_set_vip_for_gdm_port(port, true); 1718 if (err) 1719 return err; 1720 1721 if (netdev_uses_dsa(dev)) 1722 airoha_fe_set(qdma->eth, REG_GDM_INGRESS_CFG(port->id), 1723 GDM_STAG_EN_MASK); 1724 else 1725 airoha_fe_clear(qdma->eth, REG_GDM_INGRESS_CFG(port->id), 1726 GDM_STAG_EN_MASK); 1727 1728 airoha_fe_rmw(qdma->eth, REG_GDM_LEN_CFG(port->id), 1729 GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK, 1730 FIELD_PREP(GDM_SHORT_LEN_MASK, 60) | 1731 FIELD_PREP(GDM_LONG_LEN_MASK, len)); 1732 1733 airoha_qdma_set(qdma, REG_QDMA_GLOBAL_CFG, 1734 GLOBAL_CFG_TX_DMA_EN_MASK | 1735 GLOBAL_CFG_RX_DMA_EN_MASK); 1736 atomic_inc(&qdma->users); 1737 1738 if (port->id == AIROHA_GDM2_IDX && 1739 airoha_ppe_is_enabled(qdma->eth, 1)) { 1740 /* For PPE2 always use secondary cpu port. */ 1741 pse_port = FE_PSE_PORT_PPE2; 1742 } 1743 airoha_set_gdm_port_fwd_cfg(qdma->eth, REG_GDM_FWD_CFG(port->id), 1744 pse_port); 1745 1746 return 0; 1747 } 1748 1749 static int airoha_dev_stop(struct net_device *dev) 1750 { 1751 struct airoha_gdm_port *port = netdev_priv(dev); 1752 struct airoha_qdma *qdma = port->qdma; 1753 int i; 1754 1755 netif_tx_disable(dev); 1756 airoha_set_vip_for_gdm_port(port, false); 1757 for (i = 0; i < dev->num_tx_queues; i++) 1758 netdev_tx_reset_subqueue(dev, i); 1759 1760 airoha_set_gdm_port_fwd_cfg(qdma->eth, REG_GDM_FWD_CFG(port->id), 1761 FE_PSE_PORT_DROP); 1762 1763 if (atomic_dec_and_test(&qdma->users)) { 1764 airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG, 1765 GLOBAL_CFG_TX_DMA_EN_MASK | 1766 GLOBAL_CFG_RX_DMA_EN_MASK); 1767 1768 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1769 if (!qdma->q_tx[i].ndesc) 1770 continue; 1771 1772 airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]); 1773 } 1774 } 1775 1776 return 0; 1777 } 1778 1779 static int airoha_dev_set_macaddr(struct net_device *dev, void *p) 1780 { 1781 struct airoha_gdm_port *port = netdev_priv(dev); 1782 int err; 1783 1784 err = eth_mac_addr(dev, p); 1785 if (err) 1786 return err; 1787 1788 airoha_set_macaddr(port, dev->dev_addr); 1789 1790 return 0; 1791 } 1792 1793 static int airoha_set_gdm2_loopback(struct airoha_gdm_port *port) 1794 { 1795 struct airoha_eth *eth = port->qdma->eth; 1796 u32 val, pse_port, chan; 1797 int i, src_port; 1798 1799 airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(AIROHA_GDM2_IDX), 1800 FE_PSE_PORT_DROP); 1801 airoha_fe_clear(eth, REG_GDM_FWD_CFG(AIROHA_GDM2_IDX), 1802 GDM_STRIP_CRC_MASK); 1803 1804 /* Enable GDM2 loopback */ 1805 airoha_fe_wr(eth, REG_GDM_TXCHN_EN(AIROHA_GDM2_IDX), 0xffffffff); 1806 airoha_fe_wr(eth, REG_GDM_RXCHN_EN(AIROHA_GDM2_IDX), 0xffff); 1807 1808 chan = port->id == AIROHA_GDM3_IDX ? airoha_is_7581(eth) ? 4 : 3 : 0; 1809 airoha_fe_rmw(eth, REG_GDM_LPBK_CFG(AIROHA_GDM2_IDX), 1810 LPBK_CHAN_MASK | LPBK_MODE_MASK | LPBK_EN_MASK, 1811 FIELD_PREP(LPBK_CHAN_MASK, chan) | 1812 LBK_GAP_MODE_MASK | LBK_LEN_MODE_MASK | 1813 LBK_CHAN_MODE_MASK | LPBK_EN_MASK); 1814 airoha_fe_rmw(eth, REG_GDM_LEN_CFG(AIROHA_GDM2_IDX), 1815 GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK, 1816 FIELD_PREP(GDM_SHORT_LEN_MASK, 60) | 1817 FIELD_PREP(GDM_LONG_LEN_MASK, AIROHA_MAX_MTU)); 1818 /* Forward the traffic to the proper GDM port */ 1819 pse_port = port->id == AIROHA_GDM3_IDX ? FE_PSE_PORT_GDM3 1820 : FE_PSE_PORT_GDM4; 1821 airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(AIROHA_GDM2_IDX), 1822 pse_port); 1823 1824 /* Disable VIP and IFC for GDM2 */ 1825 airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, BIT(AIROHA_GDM2_IDX)); 1826 airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, BIT(AIROHA_GDM2_IDX)); 1827 1828 src_port = eth->soc->ops.get_src_port_id(port, port->nbq); 1829 if (src_port < 0) 1830 return src_port; 1831 1832 airoha_fe_rmw(eth, REG_FE_WAN_PORT, 1833 WAN1_EN_MASK | WAN1_MASK | WAN0_MASK, 1834 FIELD_PREP(WAN0_MASK, src_port)); 1835 val = src_port & SP_CPORT_DFT_MASK; 1836 airoha_fe_rmw(eth, 1837 REG_SP_DFT_CPORT(src_port >> fls(SP_CPORT_DFT_MASK)), 1838 SP_CPORT_MASK(val), 1839 __field_prep(SP_CPORT_MASK(val), FE_PSE_PORT_CDM2)); 1840 1841 for (i = 0; i < eth->soc->num_ppe; i++) 1842 airoha_ppe_set_cpu_port(port, i, AIROHA_GDM2_IDX); 1843 1844 if (port->id == AIROHA_GDM4_IDX && airoha_is_7581(eth)) { 1845 u32 mask = FC_ID_OF_SRC_PORT_MASK(port->nbq); 1846 1847 airoha_fe_rmw(eth, REG_SRC_PORT_FC_MAP6, mask, 1848 __field_prep(mask, AIROHA_GDM2_IDX)); 1849 } 1850 1851 return 0; 1852 } 1853 1854 static int airoha_dev_init(struct net_device *dev) 1855 { 1856 struct airoha_gdm_port *port = netdev_priv(dev); 1857 struct airoha_eth *eth = port->eth; 1858 int i; 1859 1860 /* QDMA0 is used for lan ports while QDMA1 is used for WAN ports */ 1861 port->qdma = ð->qdma[!airoha_is_lan_gdm_port(port)]; 1862 port->dev->irq = port->qdma->irq_banks[0].irq; 1863 airoha_set_macaddr(port, dev->dev_addr); 1864 1865 switch (port->id) { 1866 case AIROHA_GDM3_IDX: 1867 case AIROHA_GDM4_IDX: 1868 /* If GDM2 is active we can't enable loopback */ 1869 if (!eth->ports[1]) { 1870 int err; 1871 1872 err = airoha_set_gdm2_loopback(port); 1873 if (err) 1874 return err; 1875 } 1876 break; 1877 default: 1878 break; 1879 } 1880 1881 for (i = 0; i < eth->soc->num_ppe; i++) 1882 airoha_ppe_set_cpu_port(port, i, 1883 airoha_get_fe_port(port)); 1884 1885 return 0; 1886 } 1887 1888 static void airoha_dev_get_stats64(struct net_device *dev, 1889 struct rtnl_link_stats64 *storage) 1890 { 1891 struct airoha_gdm_port *port = netdev_priv(dev); 1892 unsigned int start; 1893 1894 airoha_update_hw_stats(port); 1895 do { 1896 start = u64_stats_fetch_begin(&port->stats.syncp); 1897 storage->rx_packets = port->stats.rx_ok_pkts; 1898 storage->tx_packets = port->stats.tx_ok_pkts; 1899 storage->rx_bytes = port->stats.rx_ok_bytes; 1900 storage->tx_bytes = port->stats.tx_ok_bytes; 1901 storage->multicast = port->stats.rx_multicast; 1902 storage->rx_errors = port->stats.rx_errors; 1903 storage->rx_dropped = port->stats.rx_drops; 1904 storage->tx_dropped = port->stats.tx_drops; 1905 storage->rx_crc_errors = port->stats.rx_crc_error; 1906 storage->rx_over_errors = port->stats.rx_over_errors; 1907 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 1908 } 1909 1910 static int airoha_dev_change_mtu(struct net_device *dev, int mtu) 1911 { 1912 struct airoha_gdm_port *port = netdev_priv(dev); 1913 struct airoha_eth *eth = port->qdma->eth; 1914 u32 len = ETH_HLEN + mtu + ETH_FCS_LEN; 1915 1916 airoha_fe_rmw(eth, REG_GDM_LEN_CFG(port->id), 1917 GDM_LONG_LEN_MASK, 1918 FIELD_PREP(GDM_LONG_LEN_MASK, len)); 1919 WRITE_ONCE(dev->mtu, mtu); 1920 1921 return 0; 1922 } 1923 1924 static u16 airoha_dev_select_queue(struct net_device *dev, struct sk_buff *skb, 1925 struct net_device *sb_dev) 1926 { 1927 struct airoha_gdm_port *port = netdev_priv(dev); 1928 int queue, channel; 1929 1930 /* For dsa device select QoS channel according to the dsa user port 1931 * index, rely on port id otherwise. Select QoS queue based on the 1932 * skb priority. 1933 */ 1934 channel = netdev_uses_dsa(dev) ? skb_get_queue_mapping(skb) : port->id; 1935 channel = channel % AIROHA_NUM_QOS_CHANNELS; 1936 queue = (skb->priority - 1) % AIROHA_NUM_QOS_QUEUES; /* QoS queue */ 1937 queue = channel * AIROHA_NUM_QOS_QUEUES + queue; 1938 1939 return queue < dev->num_tx_queues ? queue : 0; 1940 } 1941 1942 static u32 airoha_get_dsa_tag(struct sk_buff *skb, struct net_device *dev) 1943 { 1944 #if IS_ENABLED(CONFIG_NET_DSA) 1945 struct ethhdr *ehdr; 1946 u8 xmit_tpid; 1947 u16 tag; 1948 1949 if (!netdev_uses_dsa(dev)) 1950 return 0; 1951 1952 if (dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK) 1953 return 0; 1954 1955 if (skb_cow_head(skb, 0)) 1956 return 0; 1957 1958 ehdr = (struct ethhdr *)skb->data; 1959 tag = be16_to_cpu(ehdr->h_proto); 1960 xmit_tpid = tag >> 8; 1961 1962 switch (xmit_tpid) { 1963 case MTK_HDR_XMIT_TAGGED_TPID_8100: 1964 ehdr->h_proto = cpu_to_be16(ETH_P_8021Q); 1965 tag &= ~(MTK_HDR_XMIT_TAGGED_TPID_8100 << 8); 1966 break; 1967 case MTK_HDR_XMIT_TAGGED_TPID_88A8: 1968 ehdr->h_proto = cpu_to_be16(ETH_P_8021AD); 1969 tag &= ~(MTK_HDR_XMIT_TAGGED_TPID_88A8 << 8); 1970 break; 1971 default: 1972 /* PPE module requires untagged DSA packets to work properly, 1973 * so move DSA tag to DMA descriptor. 1974 */ 1975 memmove(skb->data + MTK_HDR_LEN, skb->data, 2 * ETH_ALEN); 1976 __skb_pull(skb, MTK_HDR_LEN); 1977 break; 1978 } 1979 1980 return tag; 1981 #else 1982 return 0; 1983 #endif 1984 } 1985 1986 int airoha_get_fe_port(struct airoha_gdm_port *port) 1987 { 1988 struct airoha_qdma *qdma = port->qdma; 1989 struct airoha_eth *eth = qdma->eth; 1990 1991 switch (eth->soc->version) { 1992 case 0x7583: 1993 return port->id == AIROHA_GDM3_IDX ? FE_PSE_PORT_GDM3 1994 : port->id; 1995 case 0x7581: 1996 default: 1997 return port->id == AIROHA_GDM4_IDX ? FE_PSE_PORT_GDM4 1998 : port->id; 1999 } 2000 } 2001 2002 static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb, 2003 struct net_device *dev) 2004 { 2005 struct airoha_gdm_port *port = netdev_priv(dev); 2006 struct airoha_qdma *qdma = port->qdma; 2007 u32 nr_frags, tag, msg0, msg1, len; 2008 struct airoha_queue_entry *e; 2009 struct netdev_queue *txq; 2010 struct airoha_queue *q; 2011 LIST_HEAD(tx_list); 2012 int i = 0, qid; 2013 void *data; 2014 u16 index; 2015 u8 fport; 2016 2017 qid = airoha_qdma_get_txq(qdma, skb_get_queue_mapping(skb)); 2018 tag = airoha_get_dsa_tag(skb, dev); 2019 2020 msg0 = FIELD_PREP(QDMA_ETH_TXMSG_CHAN_MASK, 2021 qid / AIROHA_NUM_QOS_QUEUES) | 2022 FIELD_PREP(QDMA_ETH_TXMSG_QUEUE_MASK, 2023 qid % AIROHA_NUM_QOS_QUEUES) | 2024 FIELD_PREP(QDMA_ETH_TXMSG_SP_TAG_MASK, tag); 2025 if (skb->ip_summed == CHECKSUM_PARTIAL) 2026 msg0 |= FIELD_PREP(QDMA_ETH_TXMSG_TCO_MASK, 1) | 2027 FIELD_PREP(QDMA_ETH_TXMSG_UCO_MASK, 1) | 2028 FIELD_PREP(QDMA_ETH_TXMSG_ICO_MASK, 1); 2029 2030 /* TSO: fill MSS info in tcp checksum field */ 2031 if (skb_is_gso(skb)) { 2032 if (skb_cow_head(skb, 0)) 2033 goto error; 2034 2035 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | 2036 SKB_GSO_TCPV6)) { 2037 __be16 csum = cpu_to_be16(skb_shinfo(skb)->gso_size); 2038 2039 tcp_hdr(skb)->check = (__force __sum16)csum; 2040 msg0 |= FIELD_PREP(QDMA_ETH_TXMSG_TSO_MASK, 1); 2041 } 2042 } 2043 2044 fport = airoha_get_fe_port(port); 2045 msg1 = FIELD_PREP(QDMA_ETH_TXMSG_FPORT_MASK, fport) | 2046 FIELD_PREP(QDMA_ETH_TXMSG_METER_MASK, 0x7f); 2047 2048 q = &qdma->q_tx[qid]; 2049 if (WARN_ON_ONCE(!q->ndesc)) 2050 goto error; 2051 2052 spin_lock_bh(&q->lock); 2053 2054 txq = skb_get_tx_queue(dev, skb); 2055 nr_frags = 1 + skb_shinfo(skb)->nr_frags; 2056 2057 if (q->queued + nr_frags >= q->ndesc) { 2058 /* not enough space in the queue */ 2059 netif_tx_stop_queue(txq); 2060 q->txq_stopped = true; 2061 spin_unlock_bh(&q->lock); 2062 return NETDEV_TX_BUSY; 2063 } 2064 2065 len = skb_headlen(skb); 2066 data = skb->data; 2067 2068 e = list_first_entry(&q->tx_list, struct airoha_queue_entry, 2069 list); 2070 index = e - q->entry; 2071 2072 while (true) { 2073 struct airoha_qdma_desc *desc = &q->desc[index]; 2074 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2075 dma_addr_t addr; 2076 u32 val; 2077 2078 addr = dma_map_single(dev->dev.parent, data, len, 2079 DMA_TO_DEVICE); 2080 if (unlikely(dma_mapping_error(dev->dev.parent, addr))) 2081 goto error_unmap; 2082 2083 list_move_tail(&e->list, &tx_list); 2084 e->skb = i == nr_frags - 1 ? skb : NULL; 2085 e->dma_addr = addr; 2086 e->dma_len = len; 2087 2088 e = list_first_entry(&q->tx_list, struct airoha_queue_entry, 2089 list); 2090 index = e - q->entry; 2091 2092 val = FIELD_PREP(QDMA_DESC_LEN_MASK, len); 2093 if (i < nr_frags - 1) 2094 val |= FIELD_PREP(QDMA_DESC_MORE_MASK, 1); 2095 WRITE_ONCE(desc->ctrl, cpu_to_le32(val)); 2096 WRITE_ONCE(desc->addr, cpu_to_le32(addr)); 2097 val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, index); 2098 WRITE_ONCE(desc->data, cpu_to_le32(val)); 2099 WRITE_ONCE(desc->msg0, cpu_to_le32(msg0)); 2100 WRITE_ONCE(desc->msg1, cpu_to_le32(msg1)); 2101 WRITE_ONCE(desc->msg2, cpu_to_le32(0xffff)); 2102 2103 if (++i == nr_frags) 2104 break; 2105 2106 data = skb_frag_address(frag); 2107 len = skb_frag_size(frag); 2108 } 2109 q->queued += i; 2110 2111 skb_tx_timestamp(skb); 2112 netdev_tx_sent_queue(txq, skb->len); 2113 if (q->ndesc - q->queued < q->free_thr) { 2114 netif_tx_stop_queue(txq); 2115 q->txq_stopped = true; 2116 } 2117 2118 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) 2119 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), 2120 TX_RING_CPU_IDX_MASK, 2121 FIELD_PREP(TX_RING_CPU_IDX_MASK, index)); 2122 2123 spin_unlock_bh(&q->lock); 2124 2125 return NETDEV_TX_OK; 2126 2127 error_unmap: 2128 list_for_each_entry(e, &tx_list, list) { 2129 dma_unmap_single(dev->dev.parent, e->dma_addr, e->dma_len, 2130 DMA_TO_DEVICE); 2131 e->dma_addr = 0; 2132 } 2133 list_splice(&tx_list, &q->tx_list); 2134 2135 spin_unlock_bh(&q->lock); 2136 error: 2137 dev_kfree_skb_any(skb); 2138 dev->stats.tx_dropped++; 2139 2140 return NETDEV_TX_OK; 2141 } 2142 2143 static void airoha_ethtool_get_drvinfo(struct net_device *dev, 2144 struct ethtool_drvinfo *info) 2145 { 2146 struct airoha_gdm_port *port = netdev_priv(dev); 2147 struct airoha_eth *eth = port->qdma->eth; 2148 2149 strscpy(info->driver, eth->dev->driver->name, sizeof(info->driver)); 2150 strscpy(info->bus_info, dev_name(eth->dev), sizeof(info->bus_info)); 2151 } 2152 2153 static void airoha_ethtool_get_mac_stats(struct net_device *dev, 2154 struct ethtool_eth_mac_stats *stats) 2155 { 2156 struct airoha_gdm_port *port = netdev_priv(dev); 2157 unsigned int start; 2158 2159 airoha_update_hw_stats(port); 2160 do { 2161 start = u64_stats_fetch_begin(&port->stats.syncp); 2162 stats->FramesTransmittedOK = port->stats.tx_ok_pkts; 2163 stats->OctetsTransmittedOK = port->stats.tx_ok_bytes; 2164 stats->MulticastFramesXmittedOK = port->stats.tx_multicast; 2165 stats->BroadcastFramesXmittedOK = port->stats.tx_broadcast; 2166 stats->FramesReceivedOK = port->stats.rx_ok_pkts; 2167 stats->OctetsReceivedOK = port->stats.rx_ok_bytes; 2168 stats->BroadcastFramesReceivedOK = port->stats.rx_broadcast; 2169 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 2170 } 2171 2172 static const struct ethtool_rmon_hist_range airoha_ethtool_rmon_ranges[] = { 2173 { 0, 64 }, 2174 { 65, 127 }, 2175 { 128, 255 }, 2176 { 256, 511 }, 2177 { 512, 1023 }, 2178 { 1024, 1518 }, 2179 { 1519, 10239 }, 2180 {}, 2181 }; 2182 2183 static void 2184 airoha_ethtool_get_rmon_stats(struct net_device *dev, 2185 struct ethtool_rmon_stats *stats, 2186 const struct ethtool_rmon_hist_range **ranges) 2187 { 2188 struct airoha_gdm_port *port = netdev_priv(dev); 2189 struct airoha_hw_stats *hw_stats = &port->stats; 2190 unsigned int start; 2191 2192 BUILD_BUG_ON(ARRAY_SIZE(airoha_ethtool_rmon_ranges) != 2193 ARRAY_SIZE(hw_stats->tx_len) + 1); 2194 BUILD_BUG_ON(ARRAY_SIZE(airoha_ethtool_rmon_ranges) != 2195 ARRAY_SIZE(hw_stats->rx_len) + 1); 2196 2197 *ranges = airoha_ethtool_rmon_ranges; 2198 airoha_update_hw_stats(port); 2199 do { 2200 int i; 2201 2202 start = u64_stats_fetch_begin(&port->stats.syncp); 2203 stats->fragments = hw_stats->rx_fragment; 2204 stats->jabbers = hw_stats->rx_jabber; 2205 for (i = 0; i < ARRAY_SIZE(airoha_ethtool_rmon_ranges) - 1; 2206 i++) { 2207 stats->hist[i] = hw_stats->rx_len[i]; 2208 stats->hist_tx[i] = hw_stats->tx_len[i]; 2209 } 2210 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 2211 } 2212 2213 static int airoha_qdma_set_chan_tx_sched(struct net_device *dev, 2214 int channel, enum tx_sched_mode mode, 2215 const u16 *weights, u8 n_weights) 2216 { 2217 struct airoha_gdm_port *port = netdev_priv(dev); 2218 int i; 2219 2220 for (i = 0; i < AIROHA_NUM_TX_RING; i++) 2221 airoha_qdma_clear(port->qdma, REG_QUEUE_CLOSE_CFG(channel), 2222 TXQ_DISABLE_CHAN_QUEUE_MASK(channel, i)); 2223 2224 for (i = 0; i < n_weights; i++) { 2225 u32 status; 2226 int err; 2227 2228 airoha_qdma_wr(port->qdma, REG_TXWRR_WEIGHT_CFG, 2229 TWRR_RW_CMD_MASK | 2230 FIELD_PREP(TWRR_CHAN_IDX_MASK, channel) | 2231 FIELD_PREP(TWRR_QUEUE_IDX_MASK, i) | 2232 FIELD_PREP(TWRR_VALUE_MASK, weights[i])); 2233 err = read_poll_timeout(airoha_qdma_rr, status, 2234 status & TWRR_RW_CMD_DONE, 2235 USEC_PER_MSEC, 10 * USEC_PER_MSEC, 2236 true, port->qdma, 2237 REG_TXWRR_WEIGHT_CFG); 2238 if (err) 2239 return err; 2240 } 2241 2242 airoha_qdma_rmw(port->qdma, REG_CHAN_QOS_MODE(channel >> 3), 2243 CHAN_QOS_MODE_MASK(channel), 2244 __field_prep(CHAN_QOS_MODE_MASK(channel), mode)); 2245 2246 return 0; 2247 } 2248 2249 static int airoha_qdma_set_tx_prio_sched(struct net_device *dev, int channel) 2250 { 2251 static const u16 w[AIROHA_NUM_QOS_QUEUES] = {}; 2252 2253 return airoha_qdma_set_chan_tx_sched(dev, channel, TC_SCH_SP, w, 2254 ARRAY_SIZE(w)); 2255 } 2256 2257 static int airoha_qdma_set_tx_ets_sched(struct net_device *dev, int channel, 2258 struct tc_ets_qopt_offload *opt) 2259 { 2260 struct tc_ets_qopt_offload_replace_params *p = &opt->replace_params; 2261 enum tx_sched_mode mode = TC_SCH_SP; 2262 u16 w[AIROHA_NUM_QOS_QUEUES] = {}; 2263 int i, nstrict = 0; 2264 2265 if (p->bands > AIROHA_NUM_QOS_QUEUES) 2266 return -EINVAL; 2267 2268 for (i = 0; i < p->bands; i++) { 2269 if (!p->quanta[i]) 2270 nstrict++; 2271 } 2272 2273 /* this configuration is not supported by the hw */ 2274 if (nstrict == AIROHA_NUM_QOS_QUEUES - 1) 2275 return -EINVAL; 2276 2277 /* EN7581 SoC supports fixed QoS band priority where WRR queues have 2278 * lowest priorities with respect to SP ones. 2279 * e.g: WRR0, WRR1, .., WRRm, SP0, SP1, .., SPn 2280 */ 2281 for (i = 0; i < nstrict; i++) { 2282 if (p->priomap[p->bands - i - 1] != i) 2283 return -EINVAL; 2284 } 2285 2286 for (i = 0; i < p->bands - nstrict; i++) { 2287 if (p->priomap[i] != nstrict + i) 2288 return -EINVAL; 2289 2290 w[i] = p->weights[nstrict + i]; 2291 } 2292 2293 if (!nstrict) 2294 mode = TC_SCH_WRR8; 2295 else if (nstrict < AIROHA_NUM_QOS_QUEUES - 1) 2296 mode = nstrict + 1; 2297 2298 return airoha_qdma_set_chan_tx_sched(dev, channel, mode, w, 2299 ARRAY_SIZE(w)); 2300 } 2301 2302 static int airoha_qdma_get_tx_ets_stats(struct net_device *dev, int channel, 2303 struct tc_ets_qopt_offload *opt) 2304 { 2305 struct airoha_gdm_port *port = netdev_priv(dev); 2306 u64 cpu_tx_packets = airoha_qdma_rr(port->qdma, 2307 REG_CNTR_VAL(channel << 1)); 2308 u64 fwd_tx_packets = airoha_qdma_rr(port->qdma, 2309 REG_CNTR_VAL((channel << 1) + 1)); 2310 u64 tx_packets = (cpu_tx_packets - port->cpu_tx_packets) + 2311 (fwd_tx_packets - port->fwd_tx_packets); 2312 2313 _bstats_update(opt->stats.bstats, 0, tx_packets); 2314 2315 port->cpu_tx_packets = cpu_tx_packets; 2316 port->fwd_tx_packets = fwd_tx_packets; 2317 2318 return 0; 2319 } 2320 2321 static int airoha_tc_setup_qdisc_ets(struct net_device *dev, 2322 struct tc_ets_qopt_offload *opt) 2323 { 2324 int channel; 2325 2326 if (opt->parent == TC_H_ROOT) 2327 return -EINVAL; 2328 2329 channel = TC_H_MAJ(opt->handle) >> 16; 2330 channel = channel % AIROHA_NUM_QOS_CHANNELS; 2331 2332 switch (opt->command) { 2333 case TC_ETS_REPLACE: 2334 return airoha_qdma_set_tx_ets_sched(dev, channel, opt); 2335 case TC_ETS_DESTROY: 2336 /* PRIO is default qdisc scheduler */ 2337 return airoha_qdma_set_tx_prio_sched(dev, channel); 2338 case TC_ETS_STATS: 2339 return airoha_qdma_get_tx_ets_stats(dev, channel, opt); 2340 default: 2341 return -EOPNOTSUPP; 2342 } 2343 } 2344 2345 static int airoha_qdma_get_rl_param(struct airoha_qdma *qdma, int queue_id, 2346 u32 addr, enum trtcm_param_type param, 2347 u32 *val_low, u32 *val_high) 2348 { 2349 u32 idx = QDMA_METER_IDX(queue_id), group = QDMA_METER_GROUP(queue_id); 2350 u32 val, config = FIELD_PREP(RATE_LIMIT_PARAM_TYPE_MASK, param) | 2351 FIELD_PREP(RATE_LIMIT_METER_GROUP_MASK, group) | 2352 FIELD_PREP(RATE_LIMIT_PARAM_INDEX_MASK, idx); 2353 2354 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2355 if (read_poll_timeout(airoha_qdma_rr, val, 2356 val & RATE_LIMIT_PARAM_RW_DONE_MASK, 2357 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, qdma, 2358 REG_TRTCM_CFG_PARAM(addr))) 2359 return -ETIMEDOUT; 2360 2361 *val_low = airoha_qdma_rr(qdma, REG_TRTCM_DATA_LOW(addr)); 2362 if (val_high) 2363 *val_high = airoha_qdma_rr(qdma, REG_TRTCM_DATA_HIGH(addr)); 2364 2365 return 0; 2366 } 2367 2368 static int airoha_qdma_set_rl_param(struct airoha_qdma *qdma, int queue_id, 2369 u32 addr, enum trtcm_param_type param, 2370 u32 val) 2371 { 2372 u32 idx = QDMA_METER_IDX(queue_id), group = QDMA_METER_GROUP(queue_id); 2373 u32 config = RATE_LIMIT_PARAM_RW_MASK | 2374 FIELD_PREP(RATE_LIMIT_PARAM_TYPE_MASK, param) | 2375 FIELD_PREP(RATE_LIMIT_METER_GROUP_MASK, group) | 2376 FIELD_PREP(RATE_LIMIT_PARAM_INDEX_MASK, idx); 2377 2378 airoha_qdma_wr(qdma, REG_TRTCM_DATA_LOW(addr), val); 2379 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2380 2381 return read_poll_timeout(airoha_qdma_rr, val, 2382 val & RATE_LIMIT_PARAM_RW_DONE_MASK, 2383 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2384 qdma, REG_TRTCM_CFG_PARAM(addr)); 2385 } 2386 2387 static int airoha_qdma_set_rl_config(struct airoha_qdma *qdma, int queue_id, 2388 u32 addr, bool enable, u32 enable_mask) 2389 { 2390 u32 val; 2391 int err; 2392 2393 err = airoha_qdma_get_rl_param(qdma, queue_id, addr, TRTCM_MISC_MODE, 2394 &val, NULL); 2395 if (err) 2396 return err; 2397 2398 val = enable ? val | enable_mask : val & ~enable_mask; 2399 2400 return airoha_qdma_set_rl_param(qdma, queue_id, addr, TRTCM_MISC_MODE, 2401 val); 2402 } 2403 2404 static int airoha_qdma_set_rl_token_bucket(struct airoha_qdma *qdma, 2405 int queue_id, u32 rate_val, 2406 u32 bucket_size) 2407 { 2408 u32 val, config, tick, unit, rate, rate_frac; 2409 int err; 2410 2411 err = airoha_qdma_get_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2412 TRTCM_MISC_MODE, &config, NULL); 2413 if (err) 2414 return err; 2415 2416 val = airoha_qdma_rr(qdma, REG_INGRESS_TRTCM_CFG); 2417 tick = FIELD_GET(INGRESS_FAST_TICK_MASK, val); 2418 if (config & TRTCM_TICK_SEL) 2419 tick *= FIELD_GET(INGRESS_SLOW_TICK_RATIO_MASK, val); 2420 if (!tick) 2421 return -EINVAL; 2422 2423 unit = (config & TRTCM_PKT_MODE) ? 1000000 / tick : 8000 / tick; 2424 if (!unit) 2425 return -EINVAL; 2426 2427 rate = rate_val / unit; 2428 rate_frac = rate_val % unit; 2429 rate_frac = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate_frac) / unit; 2430 rate = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate) | 2431 FIELD_PREP(TRTCM_TOKEN_RATE_FRACTION_MASK, rate_frac); 2432 2433 err = airoha_qdma_set_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2434 TRTCM_TOKEN_RATE_MODE, rate); 2435 if (err) 2436 return err; 2437 2438 val = bucket_size; 2439 if (!(config & TRTCM_PKT_MODE)) 2440 val = max_t(u32, val, MIN_TOKEN_SIZE); 2441 val = min_t(u32, __fls(val), MAX_TOKEN_SIZE_OFFSET); 2442 2443 return airoha_qdma_set_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2444 TRTCM_BUCKETSIZE_SHIFT_MODE, val); 2445 } 2446 2447 static int airoha_qdma_init_rl_config(struct airoha_qdma *qdma, int queue_id, 2448 bool enable, enum trtcm_unit_type unit) 2449 { 2450 bool tick_sel = queue_id == 0 || queue_id == 2 || queue_id == 8; 2451 enum trtcm_param mode = TRTCM_METER_MODE; 2452 int err; 2453 2454 mode |= unit == TRTCM_PACKET_UNIT ? TRTCM_PKT_MODE : 0; 2455 err = airoha_qdma_set_rl_config(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2456 enable, mode); 2457 if (err) 2458 return err; 2459 2460 return airoha_qdma_set_rl_config(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2461 tick_sel, TRTCM_TICK_SEL); 2462 } 2463 2464 static int airoha_qdma_get_trtcm_param(struct airoha_qdma *qdma, int channel, 2465 u32 addr, enum trtcm_param_type param, 2466 enum trtcm_mode_type mode, 2467 u32 *val_low, u32 *val_high) 2468 { 2469 u32 idx = QDMA_METER_IDX(channel), group = QDMA_METER_GROUP(channel); 2470 u32 val, config = FIELD_PREP(TRTCM_PARAM_TYPE_MASK, param) | 2471 FIELD_PREP(TRTCM_METER_GROUP_MASK, group) | 2472 FIELD_PREP(TRTCM_PARAM_INDEX_MASK, idx) | 2473 FIELD_PREP(TRTCM_PARAM_RATE_TYPE_MASK, mode); 2474 2475 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2476 if (read_poll_timeout(airoha_qdma_rr, val, 2477 val & TRTCM_PARAM_RW_DONE_MASK, 2478 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2479 qdma, REG_TRTCM_CFG_PARAM(addr))) 2480 return -ETIMEDOUT; 2481 2482 *val_low = airoha_qdma_rr(qdma, REG_TRTCM_DATA_LOW(addr)); 2483 if (val_high) 2484 *val_high = airoha_qdma_rr(qdma, REG_TRTCM_DATA_HIGH(addr)); 2485 2486 return 0; 2487 } 2488 2489 static int airoha_qdma_set_trtcm_param(struct airoha_qdma *qdma, int channel, 2490 u32 addr, enum trtcm_param_type param, 2491 enum trtcm_mode_type mode, u32 val) 2492 { 2493 u32 idx = QDMA_METER_IDX(channel), group = QDMA_METER_GROUP(channel); 2494 u32 config = TRTCM_PARAM_RW_MASK | 2495 FIELD_PREP(TRTCM_PARAM_TYPE_MASK, param) | 2496 FIELD_PREP(TRTCM_METER_GROUP_MASK, group) | 2497 FIELD_PREP(TRTCM_PARAM_INDEX_MASK, idx) | 2498 FIELD_PREP(TRTCM_PARAM_RATE_TYPE_MASK, mode); 2499 2500 airoha_qdma_wr(qdma, REG_TRTCM_DATA_LOW(addr), val); 2501 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2502 2503 return read_poll_timeout(airoha_qdma_rr, val, 2504 val & TRTCM_PARAM_RW_DONE_MASK, 2505 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2506 qdma, REG_TRTCM_CFG_PARAM(addr)); 2507 } 2508 2509 static int airoha_qdma_set_trtcm_config(struct airoha_qdma *qdma, int channel, 2510 u32 addr, enum trtcm_mode_type mode, 2511 bool enable, u32 enable_mask) 2512 { 2513 u32 val; 2514 2515 if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2516 mode, &val, NULL)) 2517 return -EINVAL; 2518 2519 val = enable ? val | enable_mask : val & ~enable_mask; 2520 2521 return airoha_qdma_set_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2522 mode, val); 2523 } 2524 2525 static int airoha_qdma_set_trtcm_token_bucket(struct airoha_qdma *qdma, 2526 int channel, u32 addr, 2527 enum trtcm_mode_type mode, 2528 u32 rate_val, u32 bucket_size) 2529 { 2530 u32 val, config, tick, unit, rate, rate_frac; 2531 int err; 2532 2533 if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2534 mode, &config, NULL)) 2535 return -EINVAL; 2536 2537 val = airoha_qdma_rr(qdma, addr); 2538 tick = FIELD_GET(INGRESS_FAST_TICK_MASK, val); 2539 if (config & TRTCM_TICK_SEL) 2540 tick *= FIELD_GET(INGRESS_SLOW_TICK_RATIO_MASK, val); 2541 if (!tick) 2542 return -EINVAL; 2543 2544 unit = (config & TRTCM_PKT_MODE) ? 1000000 / tick : 8000 / tick; 2545 if (!unit) 2546 return -EINVAL; 2547 2548 rate = rate_val / unit; 2549 rate_frac = rate_val % unit; 2550 rate_frac = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate_frac) / unit; 2551 rate = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate) | 2552 FIELD_PREP(TRTCM_TOKEN_RATE_FRACTION_MASK, rate_frac); 2553 2554 err = airoha_qdma_set_trtcm_param(qdma, channel, addr, 2555 TRTCM_TOKEN_RATE_MODE, mode, rate); 2556 if (err) 2557 return err; 2558 2559 val = max_t(u32, bucket_size, MIN_TOKEN_SIZE); 2560 val = min_t(u32, __fls(val), MAX_TOKEN_SIZE_OFFSET); 2561 2562 return airoha_qdma_set_trtcm_param(qdma, channel, addr, 2563 TRTCM_BUCKETSIZE_SHIFT_MODE, 2564 mode, val); 2565 } 2566 2567 static int airoha_qdma_set_tx_rate_limit(struct net_device *dev, 2568 int channel, u32 rate, 2569 u32 bucket_size) 2570 { 2571 struct airoha_gdm_port *port = netdev_priv(dev); 2572 int i, err; 2573 2574 for (i = 0; i <= TRTCM_PEAK_MODE; i++) { 2575 err = airoha_qdma_set_trtcm_config(port->qdma, channel, 2576 REG_EGRESS_TRTCM_CFG, i, 2577 !!rate, TRTCM_METER_MODE); 2578 if (err) 2579 return err; 2580 2581 err = airoha_qdma_set_trtcm_token_bucket(port->qdma, channel, 2582 REG_EGRESS_TRTCM_CFG, 2583 i, rate, bucket_size); 2584 if (err) 2585 return err; 2586 } 2587 2588 return 0; 2589 } 2590 2591 static int airoha_tc_htb_alloc_leaf_queue(struct net_device *dev, 2592 struct tc_htb_qopt_offload *opt) 2593 { 2594 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2595 u32 rate = div_u64(opt->rate, 1000) << 3; /* kbps */ 2596 int err, num_tx_queues = dev->real_num_tx_queues; 2597 struct airoha_gdm_port *port = netdev_priv(dev); 2598 2599 if (opt->parent_classid != TC_HTB_CLASSID_ROOT) { 2600 NL_SET_ERR_MSG_MOD(opt->extack, "invalid parent classid"); 2601 return -EINVAL; 2602 } 2603 2604 err = airoha_qdma_set_tx_rate_limit(dev, channel, rate, opt->quantum); 2605 if (err) { 2606 NL_SET_ERR_MSG_MOD(opt->extack, 2607 "failed configuring htb offload"); 2608 return err; 2609 } 2610 2611 if (opt->command == TC_HTB_NODE_MODIFY) 2612 return 0; 2613 2614 err = netif_set_real_num_tx_queues(dev, num_tx_queues + 1); 2615 if (err) { 2616 airoha_qdma_set_tx_rate_limit(dev, channel, 0, opt->quantum); 2617 NL_SET_ERR_MSG_MOD(opt->extack, 2618 "failed setting real_num_tx_queues"); 2619 return err; 2620 } 2621 2622 set_bit(channel, port->qos_sq_bmap); 2623 opt->qid = AIROHA_NUM_TX_RING + channel; 2624 2625 return 0; 2626 } 2627 2628 static int airoha_qdma_set_rx_meter(struct airoha_gdm_port *port, 2629 u32 rate, u32 bucket_size, 2630 enum trtcm_unit_type unit_type) 2631 { 2632 struct airoha_qdma *qdma = port->qdma; 2633 int i; 2634 2635 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 2636 int err; 2637 2638 if (!qdma->q_rx[i].ndesc) 2639 continue; 2640 2641 err = airoha_qdma_init_rl_config(qdma, i, !!rate, unit_type); 2642 if (err) 2643 return err; 2644 2645 err = airoha_qdma_set_rl_token_bucket(qdma, i, rate, 2646 bucket_size); 2647 if (err) 2648 return err; 2649 } 2650 2651 return 0; 2652 } 2653 2654 static int airoha_tc_matchall_act_validate(struct tc_cls_matchall_offload *f) 2655 { 2656 const struct flow_action *actions = &f->rule->action; 2657 const struct flow_action_entry *act; 2658 2659 if (!flow_action_has_entries(actions)) { 2660 NL_SET_ERR_MSG_MOD(f->common.extack, 2661 "filter run with no actions"); 2662 return -EINVAL; 2663 } 2664 2665 if (!flow_offload_has_one_action(actions)) { 2666 NL_SET_ERR_MSG_MOD(f->common.extack, 2667 "only once action per filter is supported"); 2668 return -EOPNOTSUPP; 2669 } 2670 2671 act = &actions->entries[0]; 2672 if (act->id != FLOW_ACTION_POLICE) { 2673 NL_SET_ERR_MSG_MOD(f->common.extack, "unsupported action"); 2674 return -EOPNOTSUPP; 2675 } 2676 2677 if (act->police.exceed.act_id != FLOW_ACTION_DROP) { 2678 NL_SET_ERR_MSG_MOD(f->common.extack, 2679 "invalid exceed action id"); 2680 return -EOPNOTSUPP; 2681 } 2682 2683 if (act->police.notexceed.act_id != FLOW_ACTION_ACCEPT) { 2684 NL_SET_ERR_MSG_MOD(f->common.extack, 2685 "invalid notexceed action id"); 2686 return -EOPNOTSUPP; 2687 } 2688 2689 if (act->police.notexceed.act_id == FLOW_ACTION_ACCEPT && 2690 !flow_action_is_last_entry(actions, act)) { 2691 NL_SET_ERR_MSG_MOD(f->common.extack, 2692 "action accept must be last"); 2693 return -EOPNOTSUPP; 2694 } 2695 2696 if (act->police.peakrate_bytes_ps || act->police.avrate || 2697 act->police.overhead || act->police.mtu) { 2698 NL_SET_ERR_MSG_MOD(f->common.extack, 2699 "peakrate/avrate/overhead/mtu unsupported"); 2700 return -EOPNOTSUPP; 2701 } 2702 2703 return 0; 2704 } 2705 2706 static int airoha_dev_tc_matchall(struct net_device *dev, 2707 struct tc_cls_matchall_offload *f) 2708 { 2709 enum trtcm_unit_type unit_type = TRTCM_BYTE_UNIT; 2710 struct airoha_gdm_port *port = netdev_priv(dev); 2711 u32 rate = 0, bucket_size = 0; 2712 2713 switch (f->command) { 2714 case TC_CLSMATCHALL_REPLACE: { 2715 const struct flow_action_entry *act; 2716 int err; 2717 2718 err = airoha_tc_matchall_act_validate(f); 2719 if (err) 2720 return err; 2721 2722 act = &f->rule->action.entries[0]; 2723 if (act->police.rate_pkt_ps) { 2724 rate = act->police.rate_pkt_ps; 2725 bucket_size = act->police.burst_pkt; 2726 unit_type = TRTCM_PACKET_UNIT; 2727 } else { 2728 rate = div_u64(act->police.rate_bytes_ps, 1000); 2729 rate = rate << 3; /* Kbps */ 2730 bucket_size = act->police.burst; 2731 } 2732 fallthrough; 2733 } 2734 case TC_CLSMATCHALL_DESTROY: 2735 return airoha_qdma_set_rx_meter(port, rate, bucket_size, 2736 unit_type); 2737 default: 2738 return -EOPNOTSUPP; 2739 } 2740 } 2741 2742 static int airoha_dev_setup_tc_block_cb(enum tc_setup_type type, 2743 void *type_data, void *cb_priv) 2744 { 2745 struct net_device *dev = cb_priv; 2746 struct airoha_gdm_port *port = netdev_priv(dev); 2747 struct airoha_eth *eth = port->qdma->eth; 2748 2749 if (!tc_can_offload(dev)) 2750 return -EOPNOTSUPP; 2751 2752 switch (type) { 2753 case TC_SETUP_CLSFLOWER: 2754 return airoha_ppe_setup_tc_block_cb(ð->ppe->dev, type_data); 2755 case TC_SETUP_CLSMATCHALL: 2756 return airoha_dev_tc_matchall(dev, type_data); 2757 default: 2758 return -EOPNOTSUPP; 2759 } 2760 } 2761 2762 static int airoha_dev_setup_tc_block(struct net_device *dev, 2763 struct flow_block_offload *f) 2764 { 2765 flow_setup_cb_t *cb = airoha_dev_setup_tc_block_cb; 2766 static LIST_HEAD(block_cb_list); 2767 struct flow_block_cb *block_cb; 2768 2769 if (f->binder_type != FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 2770 return -EOPNOTSUPP; 2771 2772 f->driver_block_list = &block_cb_list; 2773 switch (f->command) { 2774 case FLOW_BLOCK_BIND: 2775 block_cb = flow_block_cb_lookup(f->block, cb, dev); 2776 if (block_cb) { 2777 flow_block_cb_incref(block_cb); 2778 return 0; 2779 } 2780 block_cb = flow_block_cb_alloc(cb, dev, dev, NULL); 2781 if (IS_ERR(block_cb)) 2782 return PTR_ERR(block_cb); 2783 2784 flow_block_cb_incref(block_cb); 2785 flow_block_cb_add(block_cb, f); 2786 list_add_tail(&block_cb->driver_list, &block_cb_list); 2787 return 0; 2788 case FLOW_BLOCK_UNBIND: 2789 block_cb = flow_block_cb_lookup(f->block, cb, dev); 2790 if (!block_cb) 2791 return -ENOENT; 2792 2793 if (!flow_block_cb_decref(block_cb)) { 2794 flow_block_cb_remove(block_cb, f); 2795 list_del(&block_cb->driver_list); 2796 } 2797 return 0; 2798 default: 2799 return -EOPNOTSUPP; 2800 } 2801 } 2802 2803 static void airoha_tc_remove_htb_queue(struct net_device *dev, int queue) 2804 { 2805 struct airoha_gdm_port *port = netdev_priv(dev); 2806 2807 netif_set_real_num_tx_queues(dev, dev->real_num_tx_queues - 1); 2808 airoha_qdma_set_tx_rate_limit(dev, queue + 1, 0, 0); 2809 clear_bit(queue, port->qos_sq_bmap); 2810 } 2811 2812 static int airoha_tc_htb_delete_leaf_queue(struct net_device *dev, 2813 struct tc_htb_qopt_offload *opt) 2814 { 2815 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2816 struct airoha_gdm_port *port = netdev_priv(dev); 2817 2818 if (!test_bit(channel, port->qos_sq_bmap)) { 2819 NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id"); 2820 return -EINVAL; 2821 } 2822 2823 airoha_tc_remove_htb_queue(dev, channel); 2824 2825 return 0; 2826 } 2827 2828 static int airoha_tc_htb_destroy(struct net_device *dev) 2829 { 2830 struct airoha_gdm_port *port = netdev_priv(dev); 2831 int q; 2832 2833 for_each_set_bit(q, port->qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS) 2834 airoha_tc_remove_htb_queue(dev, q); 2835 2836 return 0; 2837 } 2838 2839 static int airoha_tc_get_htb_get_leaf_queue(struct net_device *dev, 2840 struct tc_htb_qopt_offload *opt) 2841 { 2842 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2843 struct airoha_gdm_port *port = netdev_priv(dev); 2844 2845 if (!test_bit(channel, port->qos_sq_bmap)) { 2846 NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id"); 2847 return -EINVAL; 2848 } 2849 2850 opt->qid = AIROHA_NUM_TX_RING + channel; 2851 2852 return 0; 2853 } 2854 2855 static int airoha_tc_setup_qdisc_htb(struct net_device *dev, 2856 struct tc_htb_qopt_offload *opt) 2857 { 2858 switch (opt->command) { 2859 case TC_HTB_CREATE: 2860 break; 2861 case TC_HTB_DESTROY: 2862 return airoha_tc_htb_destroy(dev); 2863 case TC_HTB_NODE_MODIFY: 2864 case TC_HTB_LEAF_ALLOC_QUEUE: 2865 return airoha_tc_htb_alloc_leaf_queue(dev, opt); 2866 case TC_HTB_LEAF_DEL: 2867 case TC_HTB_LEAF_DEL_LAST: 2868 case TC_HTB_LEAF_DEL_LAST_FORCE: 2869 return airoha_tc_htb_delete_leaf_queue(dev, opt); 2870 case TC_HTB_LEAF_QUERY_QUEUE: 2871 return airoha_tc_get_htb_get_leaf_queue(dev, opt); 2872 default: 2873 return -EOPNOTSUPP; 2874 } 2875 2876 return 0; 2877 } 2878 2879 static int airoha_dev_tc_setup(struct net_device *dev, enum tc_setup_type type, 2880 void *type_data) 2881 { 2882 switch (type) { 2883 case TC_SETUP_QDISC_ETS: 2884 return airoha_tc_setup_qdisc_ets(dev, type_data); 2885 case TC_SETUP_QDISC_HTB: 2886 return airoha_tc_setup_qdisc_htb(dev, type_data); 2887 case TC_SETUP_BLOCK: 2888 case TC_SETUP_FT: 2889 return airoha_dev_setup_tc_block(dev, type_data); 2890 default: 2891 return -EOPNOTSUPP; 2892 } 2893 } 2894 2895 static const struct net_device_ops airoha_netdev_ops = { 2896 .ndo_init = airoha_dev_init, 2897 .ndo_open = airoha_dev_open, 2898 .ndo_stop = airoha_dev_stop, 2899 .ndo_change_mtu = airoha_dev_change_mtu, 2900 .ndo_select_queue = airoha_dev_select_queue, 2901 .ndo_start_xmit = airoha_dev_xmit, 2902 .ndo_get_stats64 = airoha_dev_get_stats64, 2903 .ndo_set_mac_address = airoha_dev_set_macaddr, 2904 .ndo_setup_tc = airoha_dev_tc_setup, 2905 }; 2906 2907 static const struct ethtool_ops airoha_ethtool_ops = { 2908 .get_drvinfo = airoha_ethtool_get_drvinfo, 2909 .get_eth_mac_stats = airoha_ethtool_get_mac_stats, 2910 .get_rmon_stats = airoha_ethtool_get_rmon_stats, 2911 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2912 .get_link = ethtool_op_get_link, 2913 }; 2914 2915 static int airoha_metadata_dst_alloc(struct airoha_gdm_port *port) 2916 { 2917 int i; 2918 2919 for (i = 0; i < ARRAY_SIZE(port->dsa_meta); i++) { 2920 struct metadata_dst *md_dst; 2921 2922 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, 2923 GFP_KERNEL); 2924 if (!md_dst) 2925 return -ENOMEM; 2926 2927 md_dst->u.port_info.port_id = i; 2928 port->dsa_meta[i] = md_dst; 2929 } 2930 2931 return 0; 2932 } 2933 2934 static void airoha_metadata_dst_free(struct airoha_gdm_port *port) 2935 { 2936 int i; 2937 2938 for (i = 0; i < ARRAY_SIZE(port->dsa_meta); i++) { 2939 if (!port->dsa_meta[i]) 2940 continue; 2941 2942 dst_release(&port->dsa_meta[i]->dst); 2943 } 2944 } 2945 2946 bool airoha_is_valid_gdm_port(struct airoha_eth *eth, 2947 struct airoha_gdm_port *port) 2948 { 2949 int i; 2950 2951 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 2952 if (eth->ports[i] == port) 2953 return true; 2954 } 2955 2956 return false; 2957 } 2958 2959 static int airoha_alloc_gdm_port(struct airoha_eth *eth, 2960 struct device_node *np) 2961 { 2962 const __be32 *id_ptr = of_get_property(np, "reg", NULL); 2963 struct airoha_gdm_port *port; 2964 struct net_device *dev; 2965 int err, p; 2966 u32 id; 2967 2968 if (!id_ptr) { 2969 dev_err(eth->dev, "missing gdm port id\n"); 2970 return -EINVAL; 2971 } 2972 2973 id = be32_to_cpup(id_ptr); 2974 p = id - 1; 2975 2976 if (!id || id > ARRAY_SIZE(eth->ports)) { 2977 dev_err(eth->dev, "invalid gdm port id: %d\n", id); 2978 return -EINVAL; 2979 } 2980 2981 if (eth->ports[p]) { 2982 dev_err(eth->dev, "duplicate gdm port id: %d\n", id); 2983 return -EINVAL; 2984 } 2985 2986 dev = devm_alloc_etherdev_mqs(eth->dev, sizeof(*port), 2987 AIROHA_NUM_NETDEV_TX_RINGS, 2988 AIROHA_NUM_RX_RING); 2989 if (!dev) { 2990 dev_err(eth->dev, "alloc_etherdev failed\n"); 2991 return -ENOMEM; 2992 } 2993 2994 dev->netdev_ops = &airoha_netdev_ops; 2995 dev->ethtool_ops = &airoha_ethtool_ops; 2996 dev->max_mtu = AIROHA_MAX_MTU; 2997 dev->watchdog_timeo = 5 * HZ; 2998 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 2999 NETIF_F_TSO6 | NETIF_F_IPV6_CSUM | 3000 NETIF_F_SG | NETIF_F_TSO | 3001 NETIF_F_HW_TC; 3002 dev->features |= dev->hw_features; 3003 dev->vlan_features = dev->hw_features; 3004 dev->dev.of_node = np; 3005 SET_NETDEV_DEV(dev, eth->dev); 3006 3007 /* reserve hw queues for HTB offloading */ 3008 err = netif_set_real_num_tx_queues(dev, AIROHA_NUM_TX_RING); 3009 if (err) 3010 return err; 3011 3012 err = of_get_ethdev_address(np, dev); 3013 if (err) { 3014 if (err == -EPROBE_DEFER) 3015 return err; 3016 3017 eth_hw_addr_random(dev); 3018 dev_info(eth->dev, "generated random MAC address %pM\n", 3019 dev->dev_addr); 3020 } 3021 3022 port = netdev_priv(dev); 3023 u64_stats_init(&port->stats.syncp); 3024 spin_lock_init(&port->stats.lock); 3025 port->eth = eth; 3026 port->dev = dev; 3027 port->id = id; 3028 /* XXX: Read nbq from DTS */ 3029 port->nbq = id == AIROHA_GDM3_IDX && airoha_is_7581(eth) ? 4 : 0; 3030 eth->ports[p] = port; 3031 3032 return airoha_metadata_dst_alloc(port); 3033 } 3034 3035 static int airoha_register_gdm_devices(struct airoha_eth *eth) 3036 { 3037 int i; 3038 3039 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 3040 struct airoha_gdm_port *port = eth->ports[i]; 3041 int err; 3042 3043 if (!port) 3044 continue; 3045 3046 err = register_netdev(port->dev); 3047 if (err) 3048 return err; 3049 } 3050 3051 set_bit(DEV_STATE_REGISTERED, ð->state); 3052 3053 return 0; 3054 } 3055 3056 static int airoha_probe(struct platform_device *pdev) 3057 { 3058 struct reset_control_bulk_data *xsi_rsts; 3059 struct device_node *np; 3060 struct airoha_eth *eth; 3061 int i, err; 3062 3063 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 3064 if (!eth) 3065 return -ENOMEM; 3066 3067 eth->soc = of_device_get_match_data(&pdev->dev); 3068 if (!eth->soc) 3069 return -EINVAL; 3070 3071 eth->dev = &pdev->dev; 3072 3073 err = dma_set_mask_and_coherent(eth->dev, DMA_BIT_MASK(32)); 3074 if (err) { 3075 dev_err(eth->dev, "failed configuring DMA mask\n"); 3076 return err; 3077 } 3078 3079 eth->fe_regs = devm_platform_ioremap_resource_byname(pdev, "fe"); 3080 if (IS_ERR(eth->fe_regs)) 3081 return dev_err_probe(eth->dev, PTR_ERR(eth->fe_regs), 3082 "failed to iomap fe regs\n"); 3083 3084 eth->rsts[0].id = "fe"; 3085 eth->rsts[1].id = "pdma"; 3086 eth->rsts[2].id = "qdma"; 3087 err = devm_reset_control_bulk_get_exclusive(eth->dev, 3088 ARRAY_SIZE(eth->rsts), 3089 eth->rsts); 3090 if (err) { 3091 dev_err(eth->dev, "failed to get bulk reset lines\n"); 3092 return err; 3093 } 3094 3095 xsi_rsts = devm_kcalloc(eth->dev, 3096 eth->soc->num_xsi_rsts, sizeof(*xsi_rsts), 3097 GFP_KERNEL); 3098 if (!xsi_rsts) 3099 return -ENOMEM; 3100 3101 eth->xsi_rsts = xsi_rsts; 3102 for (i = 0; i < eth->soc->num_xsi_rsts; i++) 3103 eth->xsi_rsts[i].id = eth->soc->xsi_rsts_names[i]; 3104 3105 err = devm_reset_control_bulk_get_exclusive(eth->dev, 3106 eth->soc->num_xsi_rsts, 3107 eth->xsi_rsts); 3108 if (err) { 3109 dev_err(eth->dev, "failed to get bulk xsi reset lines\n"); 3110 return err; 3111 } 3112 3113 eth->napi_dev = alloc_netdev_dummy(0); 3114 if (!eth->napi_dev) 3115 return -ENOMEM; 3116 3117 /* Enable threaded NAPI by default */ 3118 eth->napi_dev->threaded = true; 3119 strscpy(eth->napi_dev->name, "qdma_eth", sizeof(eth->napi_dev->name)); 3120 platform_set_drvdata(pdev, eth); 3121 3122 err = airoha_hw_init(pdev, eth); 3123 if (err) 3124 goto error_netdev_free; 3125 3126 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 3127 airoha_qdma_start_napi(ð->qdma[i]); 3128 3129 for_each_child_of_node(pdev->dev.of_node, np) { 3130 if (!of_device_is_compatible(np, "airoha,eth-mac")) 3131 continue; 3132 3133 if (!of_device_is_available(np)) 3134 continue; 3135 3136 err = airoha_alloc_gdm_port(eth, np); 3137 if (err) { 3138 of_node_put(np); 3139 goto error_napi_stop; 3140 } 3141 } 3142 3143 err = airoha_register_gdm_devices(eth); 3144 if (err) 3145 goto error_napi_stop; 3146 3147 return 0; 3148 3149 error_napi_stop: 3150 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 3151 airoha_qdma_stop_napi(ð->qdma[i]); 3152 3153 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 3154 struct airoha_gdm_port *port = eth->ports[i]; 3155 3156 if (!port) 3157 continue; 3158 3159 if (port->dev->reg_state == NETREG_REGISTERED) 3160 unregister_netdev(port->dev); 3161 airoha_metadata_dst_free(port); 3162 } 3163 airoha_hw_cleanup(eth); 3164 error_netdev_free: 3165 free_netdev(eth->napi_dev); 3166 platform_set_drvdata(pdev, NULL); 3167 3168 return err; 3169 } 3170 3171 static void airoha_remove(struct platform_device *pdev) 3172 { 3173 struct airoha_eth *eth = platform_get_drvdata(pdev); 3174 int i; 3175 3176 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 3177 airoha_qdma_stop_napi(ð->qdma[i]); 3178 3179 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 3180 struct airoha_gdm_port *port = eth->ports[i]; 3181 3182 if (!port) 3183 continue; 3184 3185 unregister_netdev(port->dev); 3186 airoha_metadata_dst_free(port); 3187 } 3188 airoha_hw_cleanup(eth); 3189 3190 free_netdev(eth->napi_dev); 3191 platform_set_drvdata(pdev, NULL); 3192 } 3193 3194 static const char * const en7581_xsi_rsts_names[] = { 3195 "xsi-mac", 3196 "hsi0-mac", 3197 "hsi1-mac", 3198 "hsi-mac", 3199 "xfp-mac", 3200 }; 3201 3202 static int airoha_en7581_get_src_port_id(struct airoha_gdm_port *port, int nbq) 3203 { 3204 switch (port->id) { 3205 case AIROHA_GDM3_IDX: 3206 /* 7581 SoC supports PCIe serdes on GDM3 port */ 3207 if (nbq == 4) 3208 return HSGMII_LAN_7581_PCIE0_SRCPORT; 3209 if (nbq == 5) 3210 return HSGMII_LAN_7581_PCIE1_SRCPORT; 3211 break; 3212 case AIROHA_GDM4_IDX: 3213 /* 7581 SoC supports eth and usb serdes on GDM4 port */ 3214 if (!nbq) 3215 return HSGMII_LAN_7581_ETH_SRCPORT; 3216 if (nbq == 1) 3217 return HSGMII_LAN_7581_USB_SRCPORT; 3218 break; 3219 default: 3220 break; 3221 } 3222 3223 return -EINVAL; 3224 } 3225 3226 static u32 airoha_en7581_get_vip_port(struct airoha_gdm_port *port, int nbq) 3227 { 3228 switch (port->id) { 3229 case AIROHA_GDM3_IDX: 3230 if (nbq == 4) 3231 return XSI_PCIE0_VIP_PORT_MASK; 3232 if (nbq == 5) 3233 return XSI_PCIE1_VIP_PORT_MASK; 3234 break; 3235 case AIROHA_GDM4_IDX: 3236 if (!nbq) 3237 return XSI_ETH_VIP_PORT_MASK; 3238 if (nbq == 1) 3239 return XSI_USB_VIP_PORT_MASK; 3240 break; 3241 default: 3242 break; 3243 } 3244 3245 return 0; 3246 } 3247 3248 static const char * const an7583_xsi_rsts_names[] = { 3249 "xsi-mac", 3250 "hsi0-mac", 3251 "hsi1-mac", 3252 "xfp-mac", 3253 }; 3254 3255 static int airoha_an7583_get_src_port_id(struct airoha_gdm_port *port, int nbq) 3256 { 3257 switch (port->id) { 3258 case AIROHA_GDM3_IDX: 3259 /* 7583 SoC supports eth serdes on GDM3 port */ 3260 if (!nbq) 3261 return HSGMII_LAN_7583_ETH_SRCPORT; 3262 break; 3263 case AIROHA_GDM4_IDX: 3264 /* 7583 SoC supports PCIe and USB serdes on GDM4 port */ 3265 if (!nbq) 3266 return HSGMII_LAN_7583_PCIE_SRCPORT; 3267 if (nbq == 1) 3268 return HSGMII_LAN_7583_USB_SRCPORT; 3269 break; 3270 default: 3271 break; 3272 } 3273 3274 return -EINVAL; 3275 } 3276 3277 static u32 airoha_an7583_get_vip_port(struct airoha_gdm_port *port, int nbq) 3278 { 3279 switch (port->id) { 3280 case AIROHA_GDM3_IDX: 3281 if (!nbq) 3282 return XSI_ETH_VIP_PORT_MASK; 3283 break; 3284 case AIROHA_GDM4_IDX: 3285 if (!nbq) 3286 return XSI_PCIE0_VIP_PORT_MASK; 3287 if (nbq == 1) 3288 return XSI_USB_VIP_PORT_MASK; 3289 break; 3290 default: 3291 break; 3292 } 3293 3294 return 0; 3295 } 3296 3297 static const struct airoha_eth_soc_data en7581_soc_data = { 3298 .version = 0x7581, 3299 .xsi_rsts_names = en7581_xsi_rsts_names, 3300 .num_xsi_rsts = ARRAY_SIZE(en7581_xsi_rsts_names), 3301 .num_ppe = 2, 3302 .ops = { 3303 .get_src_port_id = airoha_en7581_get_src_port_id, 3304 .get_vip_port = airoha_en7581_get_vip_port, 3305 }, 3306 }; 3307 3308 static const struct airoha_eth_soc_data an7583_soc_data = { 3309 .version = 0x7583, 3310 .xsi_rsts_names = an7583_xsi_rsts_names, 3311 .num_xsi_rsts = ARRAY_SIZE(an7583_xsi_rsts_names), 3312 .num_ppe = 1, 3313 .ops = { 3314 .get_src_port_id = airoha_an7583_get_src_port_id, 3315 .get_vip_port = airoha_an7583_get_vip_port, 3316 }, 3317 }; 3318 3319 static const struct of_device_id of_airoha_match[] = { 3320 { .compatible = "airoha,en7581-eth", .data = &en7581_soc_data }, 3321 { .compatible = "airoha,an7583-eth", .data = &an7583_soc_data }, 3322 { /* sentinel */ } 3323 }; 3324 MODULE_DEVICE_TABLE(of, of_airoha_match); 3325 3326 static struct platform_driver airoha_driver = { 3327 .probe = airoha_probe, 3328 .remove = airoha_remove, 3329 .driver = { 3330 .name = KBUILD_MODNAME, 3331 .of_match_table = of_airoha_match, 3332 }, 3333 }; 3334 module_platform_driver(airoha_driver); 3335 3336 MODULE_LICENSE("GPL"); 3337 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 3338 MODULE_DESCRIPTION("Ethernet driver for Airoha SoC"); 3339