1 // SPDX-License-Identifier: GPL-2.0-only
2 /* ALSA SoC TLV320AIC3X codec driver
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * Notes:
10 * The AIC3X is a driver for a low power stereo audio
11 * codecs aic31, aic32, aic33, aic3007.
12 *
13 * It supports full aic33 codec functionality.
14 * The compatibility with aic32, aic31 and aic3007 is as follows:
15 * aic32/aic3007 | aic31
16 * ---------------------------------------
17 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
18 * | IN1L -> LINE1L
19 * | IN1R -> LINE1R
20 * | IN2L -> LINE2L
21 * | IN2R -> LINE2R
22 * | MIC3L/R -> N/A
23 * truncated internal functionality in
24 * accordance with documentation
25 * ---------------------------------------
26 *
27 * Hence the machine layer should disable unsupported inputs/outputs by
28 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
29 */
30
31 #include <linux/module.h>
32 #include <linux/moduleparam.h>
33 #include <linux/init.h>
34 #include <linux/delay.h>
35 #include <linux/err.h>
36 #include <linux/pm.h>
37 #include <linux/i2c.h>
38 #include <linux/gpio/consumer.h>
39 #include <linux/regulator/consumer.h>
40 #include <linux/of.h>
41 #include <linux/slab.h>
42 #include <sound/core.h>
43 #include <sound/pcm.h>
44 #include <sound/pcm_params.h>
45 #include <sound/soc.h>
46 #include <sound/initval.h>
47 #include <sound/tlv.h>
48
49 #include "tlv320aic3x.h"
50
51 #define AIC3X_NUM_SUPPLIES 4
52 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
53 "IOVDD", /* I/O Voltage */
54 "DVDD", /* Digital Core Voltage */
55 "AVDD", /* Analog DAC Voltage */
56 "DRVDD", /* ADC Analog and Output Driver Voltage */
57 };
58
59 struct aic3x_priv;
60
61 struct aic3x_disable_nb {
62 struct notifier_block nb;
63 struct aic3x_priv *aic3x;
64 };
65
66 struct aic3x_setup_data {
67 unsigned int gpio_func[2];
68 };
69
70 /* codec private data */
71 struct aic3x_priv {
72 struct snd_soc_component *component;
73 struct regmap *regmap;
74 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
75 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
76 struct aic3x_setup_data *setup;
77 unsigned int sysclk;
78 unsigned int dai_fmt;
79 unsigned int tdm_delay;
80 unsigned int slot_width;
81 int master;
82 struct gpio_desc *gpio_reset;
83 bool shared_reset;
84 int power;
85 u16 model;
86
87 /* Selects the micbias voltage */
88 enum aic3x_micbias_voltage micbias_vg;
89 /* Output Common-Mode Voltage */
90 u8 ocmv;
91 };
92
93 static const struct reg_default aic3x_reg[] = {
94 { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x10 },
95 { 4, 0x04 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
96 { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x01 },
97 { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x80 },
98 { 16, 0x80 }, { 17, 0xff }, { 18, 0xff }, { 19, 0x78 },
99 { 20, 0x78 }, { 21, 0x78 }, { 22, 0x78 }, { 23, 0x78 },
100 { 24, 0x78 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0xfe },
101 { 28, 0x00 }, { 29, 0x00 }, { 30, 0xfe }, { 31, 0x00 },
102 { 32, 0x18 }, { 33, 0x18 }, { 34, 0x00 }, { 35, 0x00 },
103 { 36, 0x00 }, { 37, 0x00 }, { 38, 0x00 }, { 39, 0x00 },
104 { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x80 },
105 { 44, 0x80 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 },
106 { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x04 },
107 { 52, 0x00 }, { 53, 0x00 }, { 54, 0x00 }, { 55, 0x00 },
108 { 56, 0x00 }, { 57, 0x00 }, { 58, 0x04 }, { 59, 0x00 },
109 { 60, 0x00 }, { 61, 0x00 }, { 62, 0x00 }, { 63, 0x00 },
110 { 64, 0x00 }, { 65, 0x04 }, { 66, 0x00 }, { 67, 0x00 },
111 { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 },
112 { 72, 0x04 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 },
113 { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 },
114 { 80, 0x00 }, { 81, 0x00 }, { 82, 0x00 }, { 83, 0x00 },
115 { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 },
116 { 88, 0x00 }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 },
117 { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 },
118 { 96, 0x00 }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 },
119 { 100, 0x00 }, { 101, 0x00 }, { 102, 0x02 }, { 103, 0x00 },
120 { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 },
121 { 108, 0x00 }, { 109, 0x00 },
122 };
123
124 static const struct reg_sequence aic3007_class_d[] = {
125 /* Class-D speaker driver init; datasheet p. 46 */
126 { AIC3X_PAGE_SELECT, 0x0D },
127 { 0xD, 0x0D },
128 { 0x8, 0x5C },
129 { 0x8, 0x5D },
130 { 0x8, 0x5C },
131 { AIC3X_PAGE_SELECT, 0x00 },
132 };
133
aic3x_volatile_reg(struct device * dev,unsigned int reg)134 static bool aic3x_volatile_reg(struct device *dev, unsigned int reg)
135 {
136 switch (reg) {
137 case AIC3X_RESET:
138 return true;
139 default:
140 return false;
141 }
142 }
143
144 const struct regmap_config aic3x_regmap = {
145 .max_register = DAC_ICC_ADJ,
146 .reg_defaults = aic3x_reg,
147 .num_reg_defaults = ARRAY_SIZE(aic3x_reg),
148
149 .volatile_reg = aic3x_volatile_reg,
150
151 .cache_type = REGCACHE_RBTREE,
152 };
153 EXPORT_SYMBOL_GPL(aic3x_regmap);
154
155 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
156 SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \
157 snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x)
158
159 /*
160 * All input lines are connected when !0xf and disconnected with 0xf bit field,
161 * so we have to use specific dapm_put call for input mixer
162 */
snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)163 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
164 struct snd_ctl_elem_value *ucontrol)
165 {
166 struct snd_soc_component *component = snd_soc_dapm_kcontrol_to_component(kcontrol);
167 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
168 struct soc_mixer_control *mc =
169 (struct soc_mixer_control *)kcontrol->private_value;
170 unsigned int reg = mc->reg;
171 unsigned int shift = mc->shift;
172 int max = mc->max;
173 unsigned int mask = (1 << fls(max)) - 1;
174 unsigned int invert = mc->invert;
175 unsigned short val;
176 struct snd_soc_dapm_update update = {};
177 int connect, change;
178
179 val = (ucontrol->value.integer.value[0] & mask);
180
181 mask = 0xf;
182 if (val)
183 val = mask;
184
185 connect = !!val;
186
187 if (invert)
188 val = mask - val;
189
190 mask <<= shift;
191 val <<= shift;
192
193 change = snd_soc_component_test_bits(component, reg, mask, val);
194 if (change) {
195 update.kcontrol = kcontrol;
196 update.reg = reg;
197 update.mask = mask;
198 update.val = val;
199
200 snd_soc_dapm_mixer_update_power(dapm, kcontrol, connect,
201 &update);
202 }
203
204 return change;
205 }
206
207 /*
208 * mic bias power on/off share the same register bits with
209 * output voltage of mic bias. when power on mic bias, we
210 * need reclaim it to voltage value.
211 * 0x0 = Powered off
212 * 0x1 = MICBIAS output is powered to 2.0V,
213 * 0x2 = MICBIAS output is powered to 2.5V
214 * 0x3 = MICBIAS output is connected to AVDD
215 */
mic_bias_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)216 static int mic_bias_event(struct snd_soc_dapm_widget *w,
217 struct snd_kcontrol *kcontrol, int event)
218 {
219 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
220 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
221
222 switch (event) {
223 case SND_SOC_DAPM_POST_PMU:
224 /* change mic bias voltage to user defined */
225 snd_soc_component_update_bits(component, MICBIAS_CTRL,
226 MICBIAS_LEVEL_MASK,
227 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT);
228 break;
229
230 case SND_SOC_DAPM_PRE_PMD:
231 snd_soc_component_update_bits(component, MICBIAS_CTRL,
232 MICBIAS_LEVEL_MASK, 0);
233 break;
234 }
235 return 0;
236 }
237
238 static const char * const aic3x_left_dac_mux[] = {
239 "DAC_L1", "DAC_L3", "DAC_L2" };
240 static SOC_ENUM_SINGLE_DECL(aic3x_left_dac_enum, DAC_LINE_MUX, 6,
241 aic3x_left_dac_mux);
242
243 static const char * const aic3x_right_dac_mux[] = {
244 "DAC_R1", "DAC_R3", "DAC_R2" };
245 static SOC_ENUM_SINGLE_DECL(aic3x_right_dac_enum, DAC_LINE_MUX, 4,
246 aic3x_right_dac_mux);
247
248 static const char * const aic3x_left_hpcom_mux[] = {
249 "differential of HPLOUT", "constant VCM", "single-ended" };
250 static SOC_ENUM_SINGLE_DECL(aic3x_left_hpcom_enum, HPLCOM_CFG, 4,
251 aic3x_left_hpcom_mux);
252
253 static const char * const aic3x_right_hpcom_mux[] = {
254 "differential of HPROUT", "constant VCM", "single-ended",
255 "differential of HPLCOM", "external feedback" };
256 static SOC_ENUM_SINGLE_DECL(aic3x_right_hpcom_enum, HPRCOM_CFG, 3,
257 aic3x_right_hpcom_mux);
258
259 static const char * const aic3x_linein_mode_mux[] = {
260 "single-ended", "differential" };
261 static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_l_enum, LINE1L_2_LADC_CTRL, 7,
262 aic3x_linein_mode_mux);
263 static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_r_enum, LINE1L_2_RADC_CTRL, 7,
264 aic3x_linein_mode_mux);
265 static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_l_enum, LINE1R_2_LADC_CTRL, 7,
266 aic3x_linein_mode_mux);
267 static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_r_enum, LINE1R_2_RADC_CTRL, 7,
268 aic3x_linein_mode_mux);
269 static SOC_ENUM_SINGLE_DECL(aic3x_line2l_2_ldac_enum, LINE2L_2_LADC_CTRL, 7,
270 aic3x_linein_mode_mux);
271 static SOC_ENUM_SINGLE_DECL(aic3x_line2r_2_rdac_enum, LINE2R_2_RADC_CTRL, 7,
272 aic3x_linein_mode_mux);
273
274 static const char * const aic3x_adc_hpf[] = {
275 "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
276 static SOC_ENUM_DOUBLE_DECL(aic3x_adc_hpf_enum, AIC3X_CODEC_DFILT_CTRL, 6, 4,
277 aic3x_adc_hpf);
278
279 static const char * const aic3x_agc_level[] = {
280 "-5.5dB", "-8dB", "-10dB", "-12dB",
281 "-14dB", "-17dB", "-20dB", "-24dB" };
282 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_level_enum, LAGC_CTRL_A, 4,
283 aic3x_agc_level);
284 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_level_enum, RAGC_CTRL_A, 4,
285 aic3x_agc_level);
286
287 static const char * const aic3x_agc_attack[] = {
288 "8ms", "11ms", "16ms", "20ms" };
289 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_attack_enum, LAGC_CTRL_A, 2,
290 aic3x_agc_attack);
291 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_attack_enum, RAGC_CTRL_A, 2,
292 aic3x_agc_attack);
293
294 static const char * const aic3x_agc_decay[] = {
295 "100ms", "200ms", "400ms", "500ms" };
296 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_decay_enum, LAGC_CTRL_A, 0,
297 aic3x_agc_decay);
298 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_decay_enum, RAGC_CTRL_A, 0,
299 aic3x_agc_decay);
300
301 static const char * const aic3x_poweron_time[] = {
302 "0us", "10us", "100us", "1ms", "10ms", "50ms",
303 "100ms", "200ms", "400ms", "800ms", "2s", "4s" };
304 static SOC_ENUM_SINGLE_DECL(aic3x_poweron_time_enum, HPOUT_POP_REDUCTION, 4,
305 aic3x_poweron_time);
306
307 static const char * const aic3x_rampup_step[] = { "0ms", "1ms", "2ms", "4ms" };
308 static SOC_ENUM_SINGLE_DECL(aic3x_rampup_step_enum, HPOUT_POP_REDUCTION, 2,
309 aic3x_rampup_step);
310
311 /*
312 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
313 */
314 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
315 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
316 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
317 /*
318 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
319 * Step size is approximately 0.5 dB over most of the scale but increasing
320 * near the very low levels.
321 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
322 * but having increasing dB difference below that (and where it doesn't count
323 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
324 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
325 */
326 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
327
328 /* Output volumes. From 0 to 9 dB in 1 dB steps */
329 static const DECLARE_TLV_DB_SCALE(out_tlv, 0, 100, 0);
330
331 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
332 /* Output */
333 SOC_DOUBLE_R_TLV("PCM Playback Volume",
334 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
335
336 /*
337 * Output controls that map to output mixer switches. Note these are
338 * only for swapped L-to-R and R-to-L routes. See below stereo controls
339 * for direct L-to-L and R-to-R routes.
340 */
341 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
342 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
343 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
344 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
345
346 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
347 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
348 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
349 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
350
351 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
352 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
353 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
354 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
355
356 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
357 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
358 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
359 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
360
361 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
362 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
363 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
364 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
365
366 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
367 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
368 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
369 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
370
371 /* Stereo output controls for direct L-to-L and R-to-R routes */
372 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
373 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
374 0, 118, 1, output_stage_tlv),
375 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
376 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
377 0, 118, 1, output_stage_tlv),
378
379 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
380 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
381 0, 118, 1, output_stage_tlv),
382 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
383 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
384 0, 118, 1, output_stage_tlv),
385
386 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
387 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
388 0, 118, 1, output_stage_tlv),
389 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
390 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
391 0, 118, 1, output_stage_tlv),
392
393 /* Output pin controls */
394 SOC_DOUBLE_R_TLV("Line Playback Volume", LLOPM_CTRL, RLOPM_CTRL, 4,
395 9, 0, out_tlv),
396 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
397 0x01, 0),
398 SOC_DOUBLE_R_TLV("HP Playback Volume", HPLOUT_CTRL, HPROUT_CTRL, 4,
399 9, 0, out_tlv),
400 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
401 0x01, 0),
402 SOC_DOUBLE_R_TLV("HPCOM Playback Volume", HPLCOM_CTRL, HPRCOM_CTRL,
403 4, 9, 0, out_tlv),
404 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
405 0x01, 0),
406
407 /*
408 * Note: enable Automatic input Gain Controller with care. It can
409 * adjust PGA to max value when ADC is on and will never go back.
410 */
411 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
412 SOC_ENUM("Left AGC Target level", aic3x_lagc_level_enum),
413 SOC_ENUM("Right AGC Target level", aic3x_ragc_level_enum),
414 SOC_ENUM("Left AGC Attack time", aic3x_lagc_attack_enum),
415 SOC_ENUM("Right AGC Attack time", aic3x_ragc_attack_enum),
416 SOC_ENUM("Left AGC Decay time", aic3x_lagc_decay_enum),
417 SOC_ENUM("Right AGC Decay time", aic3x_ragc_decay_enum),
418
419 /* De-emphasis */
420 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0),
421
422 /* Input */
423 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
424 0, 119, 0, adc_tlv),
425 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
426
427 SOC_ENUM("ADC HPF Cut-off", aic3x_adc_hpf_enum),
428
429 /* Pop reduction */
430 SOC_ENUM("Output Driver Power-On time", aic3x_poweron_time_enum),
431 SOC_ENUM("Output Driver Ramp-up step", aic3x_rampup_step_enum),
432 };
433
434 /* For other than tlv320aic3104 */
435 static const struct snd_kcontrol_new aic3x_extra_snd_controls[] = {
436 /*
437 * Output controls that map to output mixer switches. Note these are
438 * only for swapped L-to-R and R-to-L routes. See below stereo controls
439 * for direct L-to-L and R-to-R routes.
440 */
441 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
442 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
443
444 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
445 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
446
447 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
448 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
449
450 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
451 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
452
453 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
454 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
455
456 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
457 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
458
459 /* Stereo output controls for direct L-to-L and R-to-R routes */
460 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
461 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
462 0, 118, 1, output_stage_tlv),
463
464 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
465 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
466 0, 118, 1, output_stage_tlv),
467
468 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
469 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
470 0, 118, 1, output_stage_tlv),
471 };
472
473 static const struct snd_kcontrol_new aic3x_mono_controls[] = {
474 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
475 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
476 0, 118, 1, output_stage_tlv),
477 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
478 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
479 0, 118, 1, output_stage_tlv),
480 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
481 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
482 0, 118, 1, output_stage_tlv),
483
484 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
485 SOC_SINGLE_TLV("Mono Playback Volume", MONOLOPM_CTRL, 4, 9, 0,
486 out_tlv),
487
488 };
489
490 /*
491 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
492 */
493 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
494
495 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
496 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
497
498 /* Left DAC Mux */
499 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
500 SOC_DAPM_ENUM("Route", aic3x_left_dac_enum);
501
502 /* Right DAC Mux */
503 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
504 SOC_DAPM_ENUM("Route", aic3x_right_dac_enum);
505
506 /* Left HPCOM Mux */
507 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
508 SOC_DAPM_ENUM("Route", aic3x_left_hpcom_enum);
509
510 /* Right HPCOM Mux */
511 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
512 SOC_DAPM_ENUM("Route", aic3x_right_hpcom_enum);
513
514 /* Left Line Mixer */
515 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
516 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
517 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
518 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
519 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
520 /* Not on tlv320aic3104 */
521 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
522 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
523 };
524
525 /* Right Line Mixer */
526 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
527 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
528 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
529 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
530 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
531 /* Not on tlv320aic3104 */
532 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
533 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
534 };
535
536 /* Mono Mixer */
537 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
538 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
539 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
540 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
541 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
542 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
543 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
544 };
545
546 /* Left HP Mixer */
547 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
548 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
549 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
550 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
551 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
552 /* Not on tlv320aic3104 */
553 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
554 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
555 };
556
557 /* Right HP Mixer */
558 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
559 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
560 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
561 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
562 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
563 /* Not on tlv320aic3104 */
564 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
565 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
566 };
567
568 /* Left HPCOM Mixer */
569 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
570 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
571 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
572 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
573 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
574 /* Not on tlv320aic3104 */
575 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
576 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
577 };
578
579 /* Right HPCOM Mixer */
580 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
581 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
582 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
583 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
584 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
585 /* Not on tlv320aic3104 */
586 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
587 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
588 };
589
590 /* Left PGA Mixer */
591 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
592 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
593 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
594 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
595 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
596 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
597 };
598
599 /* Right PGA Mixer */
600 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
601 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
602 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
603 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
604 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
605 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
606 };
607
608 /* Left PGA Mixer for tlv320aic3104 */
609 static const struct snd_kcontrol_new aic3104_left_pga_mixer_controls[] = {
610 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
611 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
612 SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
613 SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
614 };
615
616 /* Right PGA Mixer for tlv320aic3104 */
617 static const struct snd_kcontrol_new aic3104_right_pga_mixer_controls[] = {
618 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
619 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
620 SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
621 SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
622 };
623
624 /* Left Line1 Mux */
625 static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
626 SOC_DAPM_ENUM("Route", aic3x_line1l_2_l_enum);
627 static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
628 SOC_DAPM_ENUM("Route", aic3x_line1l_2_r_enum);
629
630 /* Right Line1 Mux */
631 static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
632 SOC_DAPM_ENUM("Route", aic3x_line1r_2_r_enum);
633 static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
634 SOC_DAPM_ENUM("Route", aic3x_line1r_2_l_enum);
635
636 /* Left Line2 Mux */
637 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
638 SOC_DAPM_ENUM("Route", aic3x_line2l_2_ldac_enum);
639
640 /* Right Line2 Mux */
641 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
642 SOC_DAPM_ENUM("Route", aic3x_line2r_2_rdac_enum);
643
644 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
645 /* Left DAC to Left Outputs */
646 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
647 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
648 &aic3x_left_dac_mux_controls),
649 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
650 &aic3x_left_hpcom_mux_controls),
651 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
652 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
653 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
654
655 /* Right DAC to Right Outputs */
656 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
657 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
658 &aic3x_right_dac_mux_controls),
659 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
660 &aic3x_right_hpcom_mux_controls),
661 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
662 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
663 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
664
665 /* Inputs to Left ADC */
666 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
667 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
668 &aic3x_left_line1l_mux_controls),
669 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
670 &aic3x_left_line1r_mux_controls),
671
672 /* Inputs to Right ADC */
673 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
674 LINE1R_2_RADC_CTRL, 2, 0),
675 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
676 &aic3x_right_line1l_mux_controls),
677 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
678 &aic3x_right_line1r_mux_controls),
679
680 /* Mic Bias */
681 SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0,
682 mic_bias_event,
683 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
684
685 SND_SOC_DAPM_OUTPUT("LLOUT"),
686 SND_SOC_DAPM_OUTPUT("RLOUT"),
687 SND_SOC_DAPM_OUTPUT("HPLOUT"),
688 SND_SOC_DAPM_OUTPUT("HPROUT"),
689 SND_SOC_DAPM_OUTPUT("HPLCOM"),
690 SND_SOC_DAPM_OUTPUT("HPRCOM"),
691
692 SND_SOC_DAPM_INPUT("LINE1L"),
693 SND_SOC_DAPM_INPUT("LINE1R"),
694
695 /*
696 * Virtual output pin to detection block inside codec. This can be
697 * used to keep codec bias on if gpio or detection features are needed.
698 * Force pin on or construct a path with an input jack and mic bias
699 * widgets.
700 */
701 SND_SOC_DAPM_OUTPUT("Detection"),
702 };
703
704 /* For other than tlv320aic3104 */
705 static const struct snd_soc_dapm_widget aic3x_extra_dapm_widgets[] = {
706 /* Inputs to Left ADC */
707 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
708 &aic3x_left_pga_mixer_controls[0],
709 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
710 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
711 &aic3x_left_line2_mux_controls),
712
713 /* Inputs to Right ADC */
714 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
715 &aic3x_right_pga_mixer_controls[0],
716 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
717 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
718 &aic3x_right_line2_mux_controls),
719
720 /*
721 * Not a real mic bias widget but similar function. This is for dynamic
722 * control of GPIO1 digital mic modulator clock output function when
723 * using digital mic.
724 */
725 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
726 AIC3X_GPIO1_REG, 4, 0xf,
727 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
728 AIC3X_GPIO1_FUNC_DISABLED),
729
730 /*
731 * Also similar function like mic bias. Selects digital mic with
732 * configurable oversampling rate instead of ADC converter.
733 */
734 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
735 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
736 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
737 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
738 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
739 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
740
741 /* Output mixers */
742 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
743 &aic3x_left_line_mixer_controls[0],
744 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
745 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
746 &aic3x_right_line_mixer_controls[0],
747 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
748 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
749 &aic3x_left_hp_mixer_controls[0],
750 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
751 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
752 &aic3x_right_hp_mixer_controls[0],
753 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
754 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
755 &aic3x_left_hpcom_mixer_controls[0],
756 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
757 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
758 &aic3x_right_hpcom_mixer_controls[0],
759 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
760
761 SND_SOC_DAPM_INPUT("MIC3L"),
762 SND_SOC_DAPM_INPUT("MIC3R"),
763 SND_SOC_DAPM_INPUT("LINE2L"),
764 SND_SOC_DAPM_INPUT("LINE2R"),
765 };
766
767 /* For tlv320aic3104 */
768 static const struct snd_soc_dapm_widget aic3104_extra_dapm_widgets[] = {
769 /* Inputs to Left ADC */
770 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
771 &aic3104_left_pga_mixer_controls[0],
772 ARRAY_SIZE(aic3104_left_pga_mixer_controls)),
773
774 /* Inputs to Right ADC */
775 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
776 &aic3104_right_pga_mixer_controls[0],
777 ARRAY_SIZE(aic3104_right_pga_mixer_controls)),
778
779 /* Output mixers */
780 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
781 &aic3x_left_line_mixer_controls[0],
782 ARRAY_SIZE(aic3x_left_line_mixer_controls) - 2),
783 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
784 &aic3x_right_line_mixer_controls[0],
785 ARRAY_SIZE(aic3x_right_line_mixer_controls) - 2),
786 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
787 &aic3x_left_hp_mixer_controls[0],
788 ARRAY_SIZE(aic3x_left_hp_mixer_controls) - 2),
789 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
790 &aic3x_right_hp_mixer_controls[0],
791 ARRAY_SIZE(aic3x_right_hp_mixer_controls) - 2),
792 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
793 &aic3x_left_hpcom_mixer_controls[0],
794 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls) - 2),
795 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
796 &aic3x_right_hpcom_mixer_controls[0],
797 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls) - 2),
798
799 SND_SOC_DAPM_INPUT("MIC2L"),
800 SND_SOC_DAPM_INPUT("MIC2R"),
801 };
802
803 static const struct snd_soc_dapm_widget aic3x_dapm_mono_widgets[] = {
804 /* Mono Output */
805 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
806
807 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
808 &aic3x_mono_mixer_controls[0],
809 ARRAY_SIZE(aic3x_mono_mixer_controls)),
810
811 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
812 };
813
814 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
815 /* Class-D outputs */
816 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
817 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
818
819 SND_SOC_DAPM_OUTPUT("SPOP"),
820 SND_SOC_DAPM_OUTPUT("SPOM"),
821 };
822
823 static const struct snd_soc_dapm_route intercon[] = {
824 /* Left Input */
825 {"Left Line1L Mux", "single-ended", "LINE1L"},
826 {"Left Line1L Mux", "differential", "LINE1L"},
827 {"Left Line1R Mux", "single-ended", "LINE1R"},
828 {"Left Line1R Mux", "differential", "LINE1R"},
829
830 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
831 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
832
833 {"Left ADC", NULL, "Left PGA Mixer"},
834
835 /* Right Input */
836 {"Right Line1R Mux", "single-ended", "LINE1R"},
837 {"Right Line1R Mux", "differential", "LINE1R"},
838 {"Right Line1L Mux", "single-ended", "LINE1L"},
839 {"Right Line1L Mux", "differential", "LINE1L"},
840
841 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
842 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
843
844 {"Right ADC", NULL, "Right PGA Mixer"},
845
846 /* Left DAC Output */
847 {"Left DAC Mux", "DAC_L1", "Left DAC"},
848 {"Left DAC Mux", "DAC_L2", "Left DAC"},
849 {"Left DAC Mux", "DAC_L3", "Left DAC"},
850
851 /* Right DAC Output */
852 {"Right DAC Mux", "DAC_R1", "Right DAC"},
853 {"Right DAC Mux", "DAC_R2", "Right DAC"},
854 {"Right DAC Mux", "DAC_R3", "Right DAC"},
855
856 /* Left Line Output */
857 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
858 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
859 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
860 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
861
862 {"Left Line Out", NULL, "Left Line Mixer"},
863 {"Left Line Out", NULL, "Left DAC Mux"},
864 {"LLOUT", NULL, "Left Line Out"},
865
866 /* Right Line Output */
867 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
868 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
869 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
870 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
871
872 {"Right Line Out", NULL, "Right Line Mixer"},
873 {"Right Line Out", NULL, "Right DAC Mux"},
874 {"RLOUT", NULL, "Right Line Out"},
875
876 /* Left HP Output */
877 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
878 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
879 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
880 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
881
882 {"Left HP Out", NULL, "Left HP Mixer"},
883 {"Left HP Out", NULL, "Left DAC Mux"},
884 {"HPLOUT", NULL, "Left HP Out"},
885
886 /* Right HP Output */
887 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
888 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
889 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
890 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
891
892 {"Right HP Out", NULL, "Right HP Mixer"},
893 {"Right HP Out", NULL, "Right DAC Mux"},
894 {"HPROUT", NULL, "Right HP Out"},
895
896 /* Left HPCOM Output */
897 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
898 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
899 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
900 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
901
902 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
903 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
904 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
905 {"Left HP Com", NULL, "Left HPCOM Mux"},
906 {"HPLCOM", NULL, "Left HP Com"},
907
908 /* Right HPCOM Output */
909 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
910 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
911 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
912 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
913
914 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
915 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
916 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
917 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
918 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
919 {"Right HP Com", NULL, "Right HPCOM Mux"},
920 {"HPRCOM", NULL, "Right HP Com"},
921 };
922
923 /* For other than tlv320aic3104 */
924 static const struct snd_soc_dapm_route intercon_extra[] = {
925 /* Left Input */
926 {"Left Line2L Mux", "single-ended", "LINE2L"},
927 {"Left Line2L Mux", "differential", "LINE2L"},
928
929 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
930 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
931 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
932
933 {"Left ADC", NULL, "GPIO1 dmic modclk"},
934
935 /* Right Input */
936 {"Right Line2R Mux", "single-ended", "LINE2R"},
937 {"Right Line2R Mux", "differential", "LINE2R"},
938
939 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
940 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
941 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
942
943 {"Right ADC", NULL, "GPIO1 dmic modclk"},
944
945 /*
946 * Logical path between digital mic enable and GPIO1 modulator clock
947 * output function
948 */
949 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
950 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
951 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
952
953 /* Left Line Output */
954 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
955 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
956
957 /* Right Line Output */
958 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
959 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
960
961 /* Left HP Output */
962 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
963 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
964
965 /* Right HP Output */
966 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
967 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
968
969 /* Left HPCOM Output */
970 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
971 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
972
973 /* Right HPCOM Output */
974 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
975 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
976 };
977
978 /* For tlv320aic3104 */
979 static const struct snd_soc_dapm_route intercon_extra_3104[] = {
980 /* Left Input */
981 {"Left PGA Mixer", "Mic2L Switch", "MIC2L"},
982 {"Left PGA Mixer", "Mic2R Switch", "MIC2R"},
983
984 /* Right Input */
985 {"Right PGA Mixer", "Mic2L Switch", "MIC2L"},
986 {"Right PGA Mixer", "Mic2R Switch", "MIC2R"},
987 };
988
989 static const struct snd_soc_dapm_route intercon_mono[] = {
990 /* Mono Output */
991 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
992 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
993 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
994 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
995 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
996 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
997 {"Mono Out", NULL, "Mono Mixer"},
998 {"MONO_LOUT", NULL, "Mono Out"},
999 };
1000
1001 static const struct snd_soc_dapm_route intercon_3007[] = {
1002 /* Class-D outputs */
1003 {"Left Class-D Out", NULL, "Left Line Out"},
1004 {"Right Class-D Out", NULL, "Left Line Out"},
1005 {"SPOP", NULL, "Left Class-D Out"},
1006 {"SPOM", NULL, "Right Class-D Out"},
1007 };
1008
aic3x_add_widgets(struct snd_soc_component * component)1009 static int aic3x_add_widgets(struct snd_soc_component *component)
1010 {
1011 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1012 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
1013
1014 switch (aic3x->model) {
1015 case AIC3X_MODEL_3X:
1016 case AIC3X_MODEL_33:
1017 case AIC3X_MODEL_3106:
1018 snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets,
1019 ARRAY_SIZE(aic3x_extra_dapm_widgets));
1020 snd_soc_dapm_add_routes(dapm, intercon_extra,
1021 ARRAY_SIZE(intercon_extra));
1022 snd_soc_dapm_new_controls(dapm, aic3x_dapm_mono_widgets,
1023 ARRAY_SIZE(aic3x_dapm_mono_widgets));
1024 snd_soc_dapm_add_routes(dapm, intercon_mono,
1025 ARRAY_SIZE(intercon_mono));
1026 break;
1027 case AIC3X_MODEL_3007:
1028 snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets,
1029 ARRAY_SIZE(aic3x_extra_dapm_widgets));
1030 snd_soc_dapm_add_routes(dapm, intercon_extra,
1031 ARRAY_SIZE(intercon_extra));
1032 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
1033 ARRAY_SIZE(aic3007_dapm_widgets));
1034 snd_soc_dapm_add_routes(dapm, intercon_3007,
1035 ARRAY_SIZE(intercon_3007));
1036 break;
1037 case AIC3X_MODEL_3104:
1038 snd_soc_dapm_new_controls(dapm, aic3104_extra_dapm_widgets,
1039 ARRAY_SIZE(aic3104_extra_dapm_widgets));
1040 snd_soc_dapm_add_routes(dapm, intercon_extra_3104,
1041 ARRAY_SIZE(intercon_extra_3104));
1042 break;
1043 }
1044
1045 return 0;
1046 }
1047
aic3x_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1048 static int aic3x_hw_params(struct snd_pcm_substream *substream,
1049 struct snd_pcm_hw_params *params,
1050 struct snd_soc_dai *dai)
1051 {
1052 static const u8 dual_rate_q[] = {4, 8, 9, 12, 16};
1053 struct snd_soc_component *component = dai->component;
1054 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1055 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
1056 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
1057 u16 d, pll_d = 1;
1058 bool dual_rate;
1059 int clk;
1060 int width = aic3x->slot_width;
1061
1062 if (!width)
1063 width = params_width(params);
1064
1065 /* select data word length */
1066 data = snd_soc_component_read(component, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
1067 switch (width) {
1068 case 16:
1069 break;
1070 case 20:
1071 data |= (0x01 << 4);
1072 break;
1073 case 24:
1074 data |= (0x02 << 4);
1075 break;
1076 case 32:
1077 data |= (0x03 << 4);
1078 break;
1079 }
1080 snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLB, data);
1081
1082 /* Fsref can be 44100 or 48000 */
1083 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
1084 dual_rate = params_rate(params) >= 64000;
1085
1086 /* Try to find a value for Q which allows us to bypass the PLL and
1087 * generate CODEC_CLK directly. */
1088 if (dual_rate) {
1089 for (int i = 0; i < ARRAY_SIZE(dual_rate_q); i++) {
1090 pll_q = dual_rate_q[i];
1091 if (aic3x->sysclk / (128 * pll_q) == fsref) {
1092 bypass_pll = 1;
1093 break;
1094 }
1095 }
1096 } else {
1097 for (pll_q = 2; pll_q < 18; pll_q++)
1098 if (aic3x->sysclk / (128 * pll_q) == fsref) {
1099 bypass_pll = 1;
1100 break;
1101 }
1102 }
1103
1104 if (bypass_pll) {
1105 pll_q &= 0xf;
1106 snd_soc_component_write(component, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
1107 snd_soc_component_write(component, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
1108 /* disable PLL if it is bypassed */
1109 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
1110
1111 } else {
1112 snd_soc_component_write(component, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
1113 /* enable PLL when it is used */
1114 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG,
1115 PLL_ENABLE, PLL_ENABLE);
1116 }
1117
1118 /* Route Left DAC to left channel input and
1119 * right DAC to right channel input */
1120 data = (LDAC2LCH | RDAC2RCH);
1121 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
1122 if (dual_rate)
1123 data |= DUAL_RATE_MODE;
1124 snd_soc_component_write(component, AIC3X_CODEC_DATAPATH_REG, data);
1125
1126 /* codec sample rate select */
1127 data = (fsref * 20) / params_rate(params);
1128 if (!dual_rate)
1129 data /= 2;
1130 data /= 5;
1131 data -= 2;
1132 data |= (data << 4);
1133 snd_soc_component_write(component, AIC3X_SAMPLE_RATE_SEL_REG, data);
1134
1135 if (bypass_pll)
1136 return 0;
1137
1138 /* Use PLL, compute appropriate setup for j, d, r and p, the closest
1139 * one wins the game. Try with d==0 first, next with d!=0.
1140 * Constraints for j are according to the datasheet.
1141 * The sysclk is divided by 1000 to prevent integer overflows.
1142 */
1143
1144 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
1145
1146 for (r = 1; r <= 16; r++)
1147 for (p = 1; p <= 8; p++) {
1148 for (j = 4; j <= 55; j++) {
1149 /* This is actually 1000*((j+(d/10000))*r)/p
1150 * The term had to be converted to get
1151 * rid of the division by 10000; d = 0 here
1152 */
1153 int tmp_clk = (1000 * j * r) / p;
1154
1155 /* Check whether this values get closer than
1156 * the best ones we had before
1157 */
1158 if (abs(codec_clk - tmp_clk) <
1159 abs(codec_clk - last_clk)) {
1160 pll_j = j; pll_d = 0;
1161 pll_r = r; pll_p = p;
1162 last_clk = tmp_clk;
1163 }
1164
1165 /* Early exit for exact matches */
1166 if (tmp_clk == codec_clk)
1167 goto found;
1168 }
1169 }
1170
1171 /* try with d != 0 */
1172 for (p = 1; p <= 8; p++) {
1173 j = codec_clk * p / 1000;
1174
1175 if (j < 4 || j > 11)
1176 continue;
1177
1178 /* do not use codec_clk here since we'd loose precision */
1179 d = ((2048 * p * fsref) - j * aic3x->sysclk)
1180 * 100 / (aic3x->sysclk/100);
1181
1182 clk = (10000 * j + d) / (10 * p);
1183
1184 /* check whether this values get closer than the best
1185 * ones we had before */
1186 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
1187 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
1188 last_clk = clk;
1189 }
1190
1191 /* Early exit for exact matches */
1192 if (clk == codec_clk)
1193 goto found;
1194 }
1195
1196 if (last_clk == 0) {
1197 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
1198 return -EINVAL;
1199 }
1200
1201 found:
1202 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p);
1203 snd_soc_component_write(component, AIC3X_OVRF_STATUS_AND_PLLR_REG,
1204 pll_r << PLLR_SHIFT);
1205 snd_soc_component_write(component, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
1206 snd_soc_component_write(component, AIC3X_PLL_PROGC_REG,
1207 (pll_d >> 6) << PLLD_MSB_SHIFT);
1208 snd_soc_component_write(component, AIC3X_PLL_PROGD_REG,
1209 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
1210
1211 return 0;
1212 }
1213
aic3x_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1214 static int aic3x_prepare(struct snd_pcm_substream *substream,
1215 struct snd_soc_dai *dai)
1216 {
1217 struct snd_soc_component *component = dai->component;
1218 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1219 int delay = 0;
1220 int width = aic3x->slot_width;
1221
1222 if (!width)
1223 width = substream->runtime->sample_bits;
1224
1225 /* TDM slot selection only valid in DSP_A/_B mode */
1226 if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_A)
1227 delay += (aic3x->tdm_delay*width + 1);
1228 else if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_B)
1229 delay += aic3x->tdm_delay*width;
1230
1231 /* Configure data delay */
1232 snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLC, delay);
1233
1234 return 0;
1235 }
1236
aic3x_mute(struct snd_soc_dai * dai,int mute,int direction)1237 static int aic3x_mute(struct snd_soc_dai *dai, int mute, int direction)
1238 {
1239 struct snd_soc_component *component = dai->component;
1240 u8 ldac_reg = snd_soc_component_read(component, LDAC_VOL) & ~MUTE_ON;
1241 u8 rdac_reg = snd_soc_component_read(component, RDAC_VOL) & ~MUTE_ON;
1242
1243 if (mute) {
1244 snd_soc_component_write(component, LDAC_VOL, ldac_reg | MUTE_ON);
1245 snd_soc_component_write(component, RDAC_VOL, rdac_reg | MUTE_ON);
1246 } else {
1247 snd_soc_component_write(component, LDAC_VOL, ldac_reg);
1248 snd_soc_component_write(component, RDAC_VOL, rdac_reg);
1249 }
1250
1251 return 0;
1252 }
1253
aic3x_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)1254 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1255 int clk_id, unsigned int freq, int dir)
1256 {
1257 struct snd_soc_component *component = codec_dai->component;
1258 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1259
1260 /* set clock on MCLK or GPIO2 or BCLK */
1261 snd_soc_component_update_bits(component, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,
1262 clk_id << PLLCLK_IN_SHIFT);
1263 snd_soc_component_update_bits(component, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,
1264 clk_id << CLKDIV_IN_SHIFT);
1265
1266 aic3x->sysclk = freq;
1267 return 0;
1268 }
1269
aic3x_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)1270 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
1271 unsigned int fmt)
1272 {
1273 struct snd_soc_component *component = codec_dai->component;
1274 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1275 u8 iface_areg, iface_breg;
1276
1277 iface_areg = snd_soc_component_read(component, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1278 iface_breg = snd_soc_component_read(component, AIC3X_ASD_INTF_CTRLB) & 0x3f;
1279
1280 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1281 case SND_SOC_DAIFMT_CBP_CFP:
1282 aic3x->master = 1;
1283 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1284 break;
1285 case SND_SOC_DAIFMT_CBC_CFC:
1286 aic3x->master = 0;
1287 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
1288 break;
1289 case SND_SOC_DAIFMT_CBP_CFC:
1290 aic3x->master = 1;
1291 iface_areg |= BIT_CLK_MASTER;
1292 iface_areg &= ~WORD_CLK_MASTER;
1293 break;
1294 case SND_SOC_DAIFMT_CBC_CFP:
1295 aic3x->master = 1;
1296 iface_areg |= WORD_CLK_MASTER;
1297 iface_areg &= ~BIT_CLK_MASTER;
1298 break;
1299 default:
1300 return -EINVAL;
1301 }
1302
1303 /*
1304 * match both interface format and signal polarities since they
1305 * are fixed
1306 */
1307 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1308 SND_SOC_DAIFMT_INV_MASK)) {
1309 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1310 break;
1311 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1312 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1313 iface_breg |= (0x01 << 6);
1314 break;
1315 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1316 iface_breg |= (0x02 << 6);
1317 break;
1318 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1319 iface_breg |= (0x03 << 6);
1320 break;
1321 default:
1322 return -EINVAL;
1323 }
1324
1325 aic3x->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
1326
1327 /* set iface */
1328 snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLA, iface_areg);
1329 snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLB, iface_breg);
1330
1331 return 0;
1332 }
1333
aic3x_set_dai_tdm_slot(struct snd_soc_dai * codec_dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)1334 static int aic3x_set_dai_tdm_slot(struct snd_soc_dai *codec_dai,
1335 unsigned int tx_mask, unsigned int rx_mask,
1336 int slots, int slot_width)
1337 {
1338 struct snd_soc_component *component = codec_dai->component;
1339 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1340 unsigned int lsb;
1341
1342 if (tx_mask != rx_mask) {
1343 dev_err(component->dev, "tx and rx masks must be symmetric\n");
1344 return -EINVAL;
1345 }
1346
1347 if (unlikely(!tx_mask)) {
1348 dev_err(component->dev, "tx and rx masks need to be non 0\n");
1349 return -EINVAL;
1350 }
1351
1352 /* TDM based on DSP mode requires slots to be adjacent */
1353 lsb = __ffs(tx_mask);
1354 if ((lsb + 1) != __fls(tx_mask)) {
1355 dev_err(component->dev, "Invalid mask, slots must be adjacent\n");
1356 return -EINVAL;
1357 }
1358
1359 switch (slot_width) {
1360 case 16:
1361 case 20:
1362 case 24:
1363 case 32:
1364 break;
1365 default:
1366 dev_err(component->dev, "Unsupported slot width %d\n", slot_width);
1367 return -EINVAL;
1368 }
1369
1370
1371 aic3x->tdm_delay = lsb;
1372 aic3x->slot_width = slot_width;
1373
1374 /* DOUT in high-impedance on inactive bit clocks */
1375 snd_soc_component_update_bits(component, AIC3X_ASD_INTF_CTRLA,
1376 DOUT_TRISTATE, DOUT_TRISTATE);
1377
1378 return 0;
1379 }
1380
aic3x_regulator_event(struct notifier_block * nb,unsigned long event,void * data)1381 static int aic3x_regulator_event(struct notifier_block *nb,
1382 unsigned long event, void *data)
1383 {
1384 struct aic3x_disable_nb *disable_nb =
1385 container_of(nb, struct aic3x_disable_nb, nb);
1386 struct aic3x_priv *aic3x = disable_nb->aic3x;
1387
1388 if (event & REGULATOR_EVENT_DISABLE) {
1389 /*
1390 * Put codec to reset and require cache sync as at least one
1391 * of the supplies was disabled
1392 */
1393 if (aic3x->gpio_reset)
1394 gpiod_set_value(aic3x->gpio_reset, 1);
1395 regcache_mark_dirty(aic3x->regmap);
1396 }
1397
1398 return 0;
1399 }
1400
aic3x_set_power(struct snd_soc_component * component,int power)1401 static int aic3x_set_power(struct snd_soc_component *component, int power)
1402 {
1403 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1404 unsigned int pll_c, pll_d;
1405 int ret;
1406
1407 if (power) {
1408 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1409 aic3x->supplies);
1410 if (ret)
1411 goto out;
1412 aic3x->power = 1;
1413
1414 if (aic3x->gpio_reset) {
1415 udelay(1);
1416 gpiod_set_value(aic3x->gpio_reset, 0);
1417 }
1418
1419 if (aic3x->model == AIC3X_MODEL_3007)
1420 regmap_multi_reg_write_bypassed(aic3x->regmap, aic3007_class_d,
1421 ARRAY_SIZE(aic3007_class_d));
1422
1423 /* Sync reg_cache with the hardware */
1424 regcache_cache_only(aic3x->regmap, false);
1425 regcache_sync(aic3x->regmap);
1426
1427 /* Rewrite paired PLL D registers in case cached sync skipped
1428 * writing one of them and thus caused other one also not
1429 * being written
1430 */
1431 pll_c = snd_soc_component_read(component, AIC3X_PLL_PROGC_REG);
1432 pll_d = snd_soc_component_read(component, AIC3X_PLL_PROGD_REG);
1433 if (pll_c == aic3x_reg[AIC3X_PLL_PROGC_REG].def ||
1434 pll_d == aic3x_reg[AIC3X_PLL_PROGD_REG].def) {
1435 snd_soc_component_write(component, AIC3X_PLL_PROGC_REG, pll_c);
1436 snd_soc_component_write(component, AIC3X_PLL_PROGD_REG, pll_d);
1437 }
1438
1439 /*
1440 * Delay is needed to reduce pop-noise after syncing back the
1441 * registers
1442 */
1443 mdelay(50);
1444 } else {
1445 /*
1446 * Do soft reset to this codec instance in order to clear
1447 * possible VDD leakage currents in case the supply regulators
1448 * remain on
1449 */
1450 snd_soc_component_write(component, AIC3X_RESET, SOFT_RESET);
1451 regcache_mark_dirty(aic3x->regmap);
1452 aic3x->power = 0;
1453 /* HW writes are needless when bias is off */
1454 regcache_cache_only(aic3x->regmap, true);
1455 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1456 aic3x->supplies);
1457 }
1458 out:
1459 return ret;
1460 }
1461
aic3x_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)1462 static int aic3x_set_bias_level(struct snd_soc_component *component,
1463 enum snd_soc_bias_level level)
1464 {
1465 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
1466 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1467
1468 switch (level) {
1469 case SND_SOC_BIAS_ON:
1470 break;
1471 case SND_SOC_BIAS_PREPARE:
1472 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_STANDBY &&
1473 aic3x->master) {
1474 /* enable pll */
1475 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG,
1476 PLL_ENABLE, PLL_ENABLE);
1477 }
1478 break;
1479 case SND_SOC_BIAS_STANDBY:
1480 if (!aic3x->power)
1481 aic3x_set_power(component, 1);
1482 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_PREPARE &&
1483 aic3x->master) {
1484 /* disable pll */
1485 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG,
1486 PLL_ENABLE, 0);
1487 }
1488 break;
1489 case SND_SOC_BIAS_OFF:
1490 if (aic3x->power)
1491 aic3x_set_power(component, 0);
1492 break;
1493 }
1494
1495 return 0;
1496 }
1497
1498 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1499 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1500 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
1501 SNDRV_PCM_FMTBIT_S32_LE)
1502
1503 static const struct snd_soc_dai_ops aic3x_dai_ops = {
1504 .hw_params = aic3x_hw_params,
1505 .prepare = aic3x_prepare,
1506 .mute_stream = aic3x_mute,
1507 .set_sysclk = aic3x_set_dai_sysclk,
1508 .set_fmt = aic3x_set_dai_fmt,
1509 .set_tdm_slot = aic3x_set_dai_tdm_slot,
1510 .no_capture_mute = 1,
1511 };
1512
1513 static struct snd_soc_dai_driver aic3x_dai = {
1514 .name = "tlv320aic3x-hifi",
1515 .playback = {
1516 .stream_name = "Playback",
1517 .channels_min = 2,
1518 .channels_max = 2,
1519 .rates = AIC3X_RATES,
1520 .formats = AIC3X_FORMATS,},
1521 .capture = {
1522 .stream_name = "Capture",
1523 .channels_min = 2,
1524 .channels_max = 2,
1525 .rates = AIC3X_RATES,
1526 .formats = AIC3X_FORMATS,},
1527 .ops = &aic3x_dai_ops,
1528 .symmetric_rate = 1,
1529 };
1530
aic3x_mono_init(struct snd_soc_component * component)1531 static void aic3x_mono_init(struct snd_soc_component *component)
1532 {
1533 /* DAC to Mono Line Out default volume and route to Output mixer */
1534 snd_soc_component_write(component, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1535 snd_soc_component_write(component, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1536
1537 /* unmute all outputs */
1538 snd_soc_component_update_bits(component, MONOLOPM_CTRL, UNMUTE, UNMUTE);
1539
1540 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1541 snd_soc_component_write(component, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1542 snd_soc_component_write(component, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1543
1544 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1545 snd_soc_component_write(component, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1546 snd_soc_component_write(component, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1547 }
1548
1549 /*
1550 * initialise the AIC3X driver
1551 * register the mixer and dsp interfaces with the kernel
1552 */
aic3x_init(struct snd_soc_component * component)1553 static int aic3x_init(struct snd_soc_component *component)
1554 {
1555 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1556
1557 snd_soc_component_write(component, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1558 snd_soc_component_write(component, AIC3X_RESET, SOFT_RESET);
1559
1560 /* DAC default volume and mute */
1561 snd_soc_component_write(component, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1562 snd_soc_component_write(component, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1563
1564 /* DAC to HP default volume and route to Output mixer */
1565 snd_soc_component_write(component, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1566 snd_soc_component_write(component, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1567 snd_soc_component_write(component, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1568 snd_soc_component_write(component, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1569 /* DAC to Line Out default volume and route to Output mixer */
1570 snd_soc_component_write(component, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1571 snd_soc_component_write(component, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1572
1573 /* unmute all outputs */
1574 snd_soc_component_update_bits(component, LLOPM_CTRL, UNMUTE, UNMUTE);
1575 snd_soc_component_update_bits(component, RLOPM_CTRL, UNMUTE, UNMUTE);
1576 snd_soc_component_update_bits(component, HPLOUT_CTRL, UNMUTE, UNMUTE);
1577 snd_soc_component_update_bits(component, HPROUT_CTRL, UNMUTE, UNMUTE);
1578 snd_soc_component_update_bits(component, HPLCOM_CTRL, UNMUTE, UNMUTE);
1579 snd_soc_component_update_bits(component, HPRCOM_CTRL, UNMUTE, UNMUTE);
1580
1581 /* ADC default volume and unmute */
1582 snd_soc_component_write(component, LADC_VOL, DEFAULT_GAIN);
1583 snd_soc_component_write(component, RADC_VOL, DEFAULT_GAIN);
1584 /* By default route Line1 to ADC PGA mixer */
1585 snd_soc_component_write(component, LINE1L_2_LADC_CTRL, 0x0);
1586 snd_soc_component_write(component, LINE1R_2_RADC_CTRL, 0x0);
1587
1588 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1589 snd_soc_component_write(component, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1590 snd_soc_component_write(component, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1591 snd_soc_component_write(component, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1592 snd_soc_component_write(component, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1593 /* PGA to Line Out default volume, disconnect from Output Mixer */
1594 snd_soc_component_write(component, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1595 snd_soc_component_write(component, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1596
1597 /* On tlv320aic3104, these registers are reserved and must not be written */
1598 if (aic3x->model != AIC3X_MODEL_3104) {
1599 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1600 snd_soc_component_write(component, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1601 snd_soc_component_write(component, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1602 snd_soc_component_write(component, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1603 snd_soc_component_write(component, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1604 /* Line2 Line Out default volume, disconnect from Output Mixer */
1605 snd_soc_component_write(component, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1606 snd_soc_component_write(component, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1607 }
1608
1609 switch (aic3x->model) {
1610 case AIC3X_MODEL_3X:
1611 case AIC3X_MODEL_33:
1612 case AIC3X_MODEL_3106:
1613 aic3x_mono_init(component);
1614 break;
1615 case AIC3X_MODEL_3007:
1616 snd_soc_component_write(component, CLASSD_CTRL, 0);
1617 break;
1618 }
1619
1620 /* Output common-mode voltage = 1.5 V */
1621 snd_soc_component_update_bits(component, HPOUT_SC, HPOUT_SC_OCMV_MASK,
1622 aic3x->ocmv << HPOUT_SC_OCMV_SHIFT);
1623
1624 return 0;
1625 }
1626
aic3x_component_probe(struct snd_soc_component * component)1627 static int aic3x_component_probe(struct snd_soc_component *component)
1628 {
1629 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1630 int ret, i;
1631
1632 aic3x->component = component;
1633
1634 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1635 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1636 aic3x->disable_nb[i].aic3x = aic3x;
1637 ret = devm_regulator_register_notifier(
1638 aic3x->supplies[i].consumer,
1639 &aic3x->disable_nb[i].nb);
1640 if (ret) {
1641 dev_err(component->dev,
1642 "Failed to request regulator notifier: %d\n",
1643 ret);
1644 return ret;
1645 }
1646 }
1647
1648 regcache_mark_dirty(aic3x->regmap);
1649 aic3x_init(component);
1650
1651 if (aic3x->setup) {
1652 if (aic3x->model != AIC3X_MODEL_3104) {
1653 /* setup GPIO functions */
1654 snd_soc_component_write(component, AIC3X_GPIO1_REG,
1655 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1656 snd_soc_component_write(component, AIC3X_GPIO2_REG,
1657 (aic3x->setup->gpio_func[1] & 0xf) << 4);
1658 } else {
1659 dev_warn(component->dev, "GPIO functionality is not supported on tlv320aic3104\n");
1660 }
1661 }
1662
1663 switch (aic3x->model) {
1664 case AIC3X_MODEL_3X:
1665 case AIC3X_MODEL_33:
1666 case AIC3X_MODEL_3106:
1667 snd_soc_add_component_controls(component, aic3x_extra_snd_controls,
1668 ARRAY_SIZE(aic3x_extra_snd_controls));
1669 snd_soc_add_component_controls(component, aic3x_mono_controls,
1670 ARRAY_SIZE(aic3x_mono_controls));
1671 break;
1672 case AIC3X_MODEL_3007:
1673 snd_soc_add_component_controls(component, aic3x_extra_snd_controls,
1674 ARRAY_SIZE(aic3x_extra_snd_controls));
1675 snd_soc_add_component_controls(component,
1676 &aic3x_classd_amp_gain_ctrl, 1);
1677 break;
1678 case AIC3X_MODEL_3104:
1679 break;
1680 }
1681
1682 /* set mic bias voltage */
1683 switch (aic3x->micbias_vg) {
1684 case AIC3X_MICBIAS_2_0V:
1685 case AIC3X_MICBIAS_2_5V:
1686 case AIC3X_MICBIAS_AVDDV:
1687 snd_soc_component_update_bits(component, MICBIAS_CTRL,
1688 MICBIAS_LEVEL_MASK,
1689 (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT);
1690 break;
1691 case AIC3X_MICBIAS_OFF:
1692 /*
1693 * noting to do. target won't enter here. This is just to avoid
1694 * compile time warning "warning: enumeration value
1695 * 'AIC3X_MICBIAS_OFF' not handled in switch"
1696 */
1697 break;
1698 }
1699
1700 aic3x_add_widgets(component);
1701
1702 return 0;
1703 }
1704
aic3x_of_xlate_dai_id(struct snd_soc_component * component,struct device_node * endpoint)1705 static int aic3x_of_xlate_dai_id(struct snd_soc_component *component,
1706 struct device_node *endpoint)
1707 {
1708 return 0;
1709 }
1710
1711 static const struct snd_soc_component_driver soc_component_dev_aic3x = {
1712 .set_bias_level = aic3x_set_bias_level,
1713 .of_xlate_dai_id = aic3x_of_xlate_dai_id,
1714 .probe = aic3x_component_probe,
1715 .controls = aic3x_snd_controls,
1716 .num_controls = ARRAY_SIZE(aic3x_snd_controls),
1717 .dapm_widgets = aic3x_dapm_widgets,
1718 .num_dapm_widgets = ARRAY_SIZE(aic3x_dapm_widgets),
1719 .dapm_routes = intercon,
1720 .num_dapm_routes = ARRAY_SIZE(intercon),
1721 .use_pmdown_time = 1,
1722 .endianness = 1,
1723 };
1724
aic3x_configure_ocmv(struct device * dev,struct aic3x_priv * aic3x)1725 static void aic3x_configure_ocmv(struct device *dev, struct aic3x_priv *aic3x)
1726 {
1727 struct device_node *np = dev->of_node;
1728 u32 value;
1729 int dvdd, avdd;
1730
1731 if (np && !of_property_read_u32(np, "ai3x-ocmv", &value)) {
1732 /* OCMV setting is forced by DT */
1733 if (value <= 3) {
1734 aic3x->ocmv = value;
1735 return;
1736 }
1737 }
1738
1739 dvdd = regulator_get_voltage(aic3x->supplies[1].consumer);
1740 avdd = regulator_get_voltage(aic3x->supplies[2].consumer);
1741
1742 if (avdd > 3600000 || dvdd > 1950000) {
1743 dev_warn(dev,
1744 "Too high supply voltage(s) AVDD: %d, DVDD: %d\n",
1745 avdd, dvdd);
1746 } else if (avdd == 3600000 && dvdd == 1950000) {
1747 aic3x->ocmv = HPOUT_SC_OCMV_1_8V;
1748 } else if (avdd > 3300000 && dvdd > 1800000) {
1749 aic3x->ocmv = HPOUT_SC_OCMV_1_65V;
1750 } else if (avdd > 3000000 && dvdd > 1650000) {
1751 aic3x->ocmv = HPOUT_SC_OCMV_1_5V;
1752 } else if (avdd >= 2700000 && dvdd >= 1525000) {
1753 aic3x->ocmv = HPOUT_SC_OCMV_1_35V;
1754 } else {
1755 dev_warn(dev,
1756 "Invalid supply voltage(s) AVDD: %d, DVDD: %d\n",
1757 avdd, dvdd);
1758 }
1759 }
1760
aic3x_probe(struct device * dev,struct regmap * regmap,kernel_ulong_t driver_data)1761 int aic3x_probe(struct device *dev, struct regmap *regmap, kernel_ulong_t driver_data)
1762 {
1763 struct aic3x_priv *aic3x;
1764 struct aic3x_setup_data *ai3x_setup;
1765 struct device_node *np = dev->of_node;
1766 int ret, i;
1767 u32 value;
1768
1769 aic3x = devm_kzalloc(dev, sizeof(struct aic3x_priv), GFP_KERNEL);
1770 if (!aic3x)
1771 return -ENOMEM;
1772
1773 aic3x->regmap = regmap;
1774 if (IS_ERR(aic3x->regmap)) {
1775 ret = PTR_ERR(aic3x->regmap);
1776 return ret;
1777 }
1778
1779 regcache_cache_only(aic3x->regmap, true);
1780
1781 dev_set_drvdata(dev, aic3x);
1782 if (np) {
1783 ai3x_setup = devm_kzalloc(dev, sizeof(*ai3x_setup), GFP_KERNEL);
1784 if (!ai3x_setup)
1785 return -ENOMEM;
1786
1787 if (of_property_read_u32_array(np, "ai3x-gpio-func",
1788 ai3x_setup->gpio_func, 2) >= 0) {
1789 aic3x->setup = ai3x_setup;
1790 }
1791
1792 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) {
1793 switch (value) {
1794 case 1 :
1795 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V;
1796 break;
1797 case 2 :
1798 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V;
1799 break;
1800 case 3 :
1801 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV;
1802 break;
1803 default :
1804 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1805 dev_err(dev, "Unsuitable MicBias voltage "
1806 "found in DT\n");
1807 }
1808 } else {
1809 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1810 }
1811 }
1812
1813 aic3x->model = driver_data;
1814
1815 aic3x->gpio_reset = devm_gpiod_get_optional(dev, "reset",
1816 GPIOD_OUT_HIGH);
1817 ret = PTR_ERR_OR_ZERO(aic3x->gpio_reset);
1818 if (ret) {
1819 if (ret != -EBUSY)
1820 return ret;
1821
1822 /*
1823 * Apparently there are setups where the codec is sharing
1824 * its reset line. Try to get it non-exclusively, although
1825 * the utility of this is unclear: how do we make sure that
1826 * resetting one chip will not disturb the others that share
1827 * the same line?
1828 */
1829 aic3x->gpio_reset = devm_gpiod_get(dev, "reset",
1830 GPIOD_ASIS | GPIOD_FLAGS_BIT_NONEXCLUSIVE);
1831 ret = PTR_ERR_OR_ZERO(aic3x->gpio_reset);
1832 if (ret)
1833 return ret;
1834
1835 aic3x->shared_reset = true;
1836 }
1837
1838 gpiod_set_consumer_name(aic3x->gpio_reset, "tlv320aic3x reset");
1839
1840 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1841 aic3x->supplies[i].supply = aic3x_supply_names[i];
1842
1843 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(aic3x->supplies),
1844 aic3x->supplies);
1845 if (ret)
1846 return dev_err_probe(dev, ret, "Failed to request supplies\n");
1847
1848 aic3x_configure_ocmv(dev, aic3x);
1849
1850 ret = devm_snd_soc_register_component(dev, &soc_component_dev_aic3x, &aic3x_dai, 1);
1851 if (ret)
1852 return ret;
1853
1854 return 0;
1855 }
1856 EXPORT_SYMBOL(aic3x_probe);
1857
aic3x_remove(struct device * dev)1858 void aic3x_remove(struct device *dev)
1859 {
1860 struct aic3x_priv *aic3x = dev_get_drvdata(dev);
1861
1862 /* Leave the codec in reset state */
1863 if (aic3x->gpio_reset && !aic3x->shared_reset)
1864 gpiod_set_value(aic3x->gpio_reset, 1);
1865 }
1866 EXPORT_SYMBOL(aic3x_remove);
1867
1868 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1869 MODULE_AUTHOR("Vladimir Barinov");
1870 MODULE_LICENSE("GPL");
1871