1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * libahci.c - Common AHCI SATA low-level routines 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2004-2005 Red Hat, Inc. 10 * 11 * libata documentation is available via 'make {ps|pdf}docs', 12 * as Documentation/driver-api/libata.rst 13 * 14 * AHCI hardware documentation: 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 17 */ 18 19 #include <linux/bitops.h> 20 #include <linux/kernel.h> 21 #include <linux/gfp.h> 22 #include <linux/module.h> 23 #include <linux/nospec.h> 24 #include <linux/blkdev.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/device.h> 29 #include <scsi/scsi_host.h> 30 #include <scsi/scsi_cmnd.h> 31 #include <linux/libata.h> 32 #include <linux/pci.h> 33 #include "ahci.h" 34 #include "libata.h" 35 36 static int ahci_skip_host_reset; 37 int ahci_ignore_sss; 38 EXPORT_SYMBOL_GPL(ahci_ignore_sss); 39 40 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); 41 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); 42 43 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); 44 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); 45 46 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 47 unsigned hints); 48 static ssize_t ahci_led_show(struct ata_port *ap, char *buf); 49 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 50 size_t size); 51 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 52 ssize_t size); 53 54 55 56 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 57 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 58 static void ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 59 static void ahci_qc_ncq_fill_rtf(struct ata_port *ap, u64 done_mask); 60 static int ahci_port_start(struct ata_port *ap); 61 static void ahci_port_stop(struct ata_port *ap); 62 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc); 63 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc); 64 static void ahci_freeze(struct ata_port *ap); 65 static void ahci_thaw(struct ata_port *ap); 66 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep); 67 static void ahci_enable_fbs(struct ata_port *ap); 68 static void ahci_disable_fbs(struct ata_port *ap); 69 static void ahci_pmp_attach(struct ata_port *ap); 70 static void ahci_pmp_detach(struct ata_port *ap); 71 static int ahci_softreset(struct ata_link *link, unsigned int *class, 72 unsigned long deadline); 73 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 74 unsigned long deadline); 75 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 76 unsigned long deadline); 77 static void ahci_postreset(struct ata_link *link, unsigned int *class); 78 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 79 static void ahci_dev_config(struct ata_device *dev); 80 #ifdef CONFIG_PM 81 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 82 #endif 83 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); 84 static ssize_t ahci_activity_store(struct ata_device *dev, 85 enum sw_activity val); 86 static void ahci_init_sw_activity(struct ata_link *link); 87 88 static ssize_t ahci_show_host_caps(struct device *dev, 89 struct device_attribute *attr, char *buf); 90 static ssize_t ahci_show_host_cap2(struct device *dev, 91 struct device_attribute *attr, char *buf); 92 static ssize_t ahci_show_host_version(struct device *dev, 93 struct device_attribute *attr, char *buf); 94 static ssize_t ahci_show_port_cmd(struct device *dev, 95 struct device_attribute *attr, char *buf); 96 static ssize_t ahci_read_em_buffer(struct device *dev, 97 struct device_attribute *attr, char *buf); 98 static ssize_t ahci_store_em_buffer(struct device *dev, 99 struct device_attribute *attr, 100 const char *buf, size_t size); 101 static ssize_t ahci_show_em_supported(struct device *dev, 102 struct device_attribute *attr, char *buf); 103 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance); 104 105 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); 106 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); 107 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); 108 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); 109 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO, 110 ahci_read_em_buffer, ahci_store_em_buffer); 111 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL); 112 113 static struct attribute *ahci_shost_attrs[] = { 114 &dev_attr_link_power_management_supported.attr, 115 &dev_attr_link_power_management_policy.attr, 116 &dev_attr_em_message_type.attr, 117 &dev_attr_em_message.attr, 118 &dev_attr_ahci_host_caps.attr, 119 &dev_attr_ahci_host_cap2.attr, 120 &dev_attr_ahci_host_version.attr, 121 &dev_attr_ahci_port_cmd.attr, 122 &dev_attr_em_buffer.attr, 123 &dev_attr_em_message_supported.attr, 124 NULL 125 }; 126 127 static const struct attribute_group ahci_shost_attr_group = { 128 .attrs = ahci_shost_attrs 129 }; 130 131 const struct attribute_group *ahci_shost_groups[] = { 132 &ahci_shost_attr_group, 133 NULL 134 }; 135 EXPORT_SYMBOL_GPL(ahci_shost_groups); 136 137 static struct attribute *ahci_sdev_attrs[] = { 138 &dev_attr_sw_activity.attr, 139 &dev_attr_unload_heads.attr, 140 &dev_attr_ncq_prio_supported.attr, 141 &dev_attr_ncq_prio_enable.attr, 142 NULL 143 }; 144 145 static const struct attribute_group ahci_sdev_attr_group = { 146 .attrs = ahci_sdev_attrs 147 }; 148 149 const struct attribute_group *ahci_sdev_groups[] = { 150 &ahci_sdev_attr_group, 151 NULL 152 }; 153 EXPORT_SYMBOL_GPL(ahci_sdev_groups); 154 155 struct ata_port_operations ahci_ops = { 156 .inherits = &sata_pmp_port_ops, 157 158 .qc_defer = ahci_pmp_qc_defer, 159 .qc_prep = ahci_qc_prep, 160 .qc_issue = ahci_qc_issue, 161 .qc_fill_rtf = ahci_qc_fill_rtf, 162 .qc_ncq_fill_rtf = ahci_qc_ncq_fill_rtf, 163 164 .freeze = ahci_freeze, 165 .thaw = ahci_thaw, 166 .reset.softreset = ahci_softreset, 167 .reset.hardreset = ahci_hardreset, 168 .reset.postreset = ahci_postreset, 169 .pmp_reset.softreset = ahci_softreset, 170 .error_handler = ahci_error_handler, 171 .post_internal_cmd = ahci_post_internal_cmd, 172 .dev_config = ahci_dev_config, 173 174 .scr_read = ahci_scr_read, 175 .scr_write = ahci_scr_write, 176 .pmp_attach = ahci_pmp_attach, 177 .pmp_detach = ahci_pmp_detach, 178 179 .set_lpm = ahci_set_lpm, 180 .em_show = ahci_led_show, 181 .em_store = ahci_led_store, 182 .sw_activity_show = ahci_activity_show, 183 .sw_activity_store = ahci_activity_store, 184 .transmit_led_message = ahci_transmit_led_message, 185 #ifdef CONFIG_PM 186 .port_suspend = ahci_port_suspend, 187 .port_resume = ahci_port_resume, 188 #endif 189 .port_start = ahci_port_start, 190 .port_stop = ahci_port_stop, 191 }; 192 EXPORT_SYMBOL_GPL(ahci_ops); 193 194 struct ata_port_operations ahci_pmp_retry_srst_ops = { 195 .inherits = &ahci_ops, 196 .reset.softreset = ahci_pmp_retry_softreset, 197 }; 198 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops); 199 200 static bool ahci_em_messages __read_mostly = true; 201 module_param(ahci_em_messages, bool, 0444); 202 /* add other LED protocol types when they become supported */ 203 MODULE_PARM_DESC(ahci_em_messages, 204 "AHCI Enclosure Management Message control (0 = off, 1 = on)"); 205 206 /* device sleep idle timeout in ms */ 207 static int devslp_idle_timeout __read_mostly = 1000; 208 module_param(devslp_idle_timeout, int, 0644); 209 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout"); 210 211 static void ahci_enable_ahci(void __iomem *mmio) 212 { 213 int i; 214 u32 tmp; 215 216 /* turn on AHCI_EN */ 217 tmp = readl(mmio + HOST_CTL); 218 if (tmp & HOST_AHCI_EN) 219 return; 220 221 /* Some controllers need AHCI_EN to be written multiple times. 222 * Try a few times before giving up. 223 */ 224 for (i = 0; i < 5; i++) { 225 tmp |= HOST_AHCI_EN; 226 writel(tmp, mmio + HOST_CTL); 227 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ 228 if (tmp & HOST_AHCI_EN) 229 return; 230 msleep(10); 231 } 232 233 WARN_ON(1); 234 } 235 236 /** 237 * ahci_rpm_get_port - Make sure the port is powered on 238 * @ap: Port to power on 239 * 240 * Whenever there is need to access the AHCI host registers outside of 241 * normal execution paths, call this function to make sure the host is 242 * actually powered on. 243 */ 244 static int ahci_rpm_get_port(struct ata_port *ap) 245 { 246 return pm_runtime_get_sync(ap->dev); 247 } 248 249 /** 250 * ahci_rpm_put_port - Undoes ahci_rpm_get_port() 251 * @ap: Port to power down 252 * 253 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host 254 * if it has no more active users. 255 */ 256 static void ahci_rpm_put_port(struct ata_port *ap) 257 { 258 pm_runtime_put(ap->dev); 259 } 260 261 static ssize_t ahci_show_host_caps(struct device *dev, 262 struct device_attribute *attr, char *buf) 263 { 264 struct Scsi_Host *shost = class_to_shost(dev); 265 struct ata_port *ap = ata_shost_to_port(shost); 266 struct ahci_host_priv *hpriv = ap->host->private_data; 267 268 return sprintf(buf, "%x\n", hpriv->cap); 269 } 270 271 static ssize_t ahci_show_host_cap2(struct device *dev, 272 struct device_attribute *attr, char *buf) 273 { 274 struct Scsi_Host *shost = class_to_shost(dev); 275 struct ata_port *ap = ata_shost_to_port(shost); 276 struct ahci_host_priv *hpriv = ap->host->private_data; 277 278 return sprintf(buf, "%x\n", hpriv->cap2); 279 } 280 281 static ssize_t ahci_show_host_version(struct device *dev, 282 struct device_attribute *attr, char *buf) 283 { 284 struct Scsi_Host *shost = class_to_shost(dev); 285 struct ata_port *ap = ata_shost_to_port(shost); 286 struct ahci_host_priv *hpriv = ap->host->private_data; 287 288 return sprintf(buf, "%x\n", hpriv->version); 289 } 290 291 static ssize_t ahci_show_port_cmd(struct device *dev, 292 struct device_attribute *attr, char *buf) 293 { 294 struct Scsi_Host *shost = class_to_shost(dev); 295 struct ata_port *ap = ata_shost_to_port(shost); 296 void __iomem *port_mmio = ahci_port_base(ap); 297 ssize_t ret; 298 299 ahci_rpm_get_port(ap); 300 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); 301 ahci_rpm_put_port(ap); 302 303 return ret; 304 } 305 306 static ssize_t ahci_read_em_buffer(struct device *dev, 307 struct device_attribute *attr, char *buf) 308 { 309 struct Scsi_Host *shost = class_to_shost(dev); 310 struct ata_port *ap = ata_shost_to_port(shost); 311 struct ahci_host_priv *hpriv = ap->host->private_data; 312 void __iomem *mmio = hpriv->mmio; 313 void __iomem *em_mmio = mmio + hpriv->em_loc; 314 u32 em_ctl, msg; 315 unsigned long flags; 316 size_t count; 317 int i; 318 319 ahci_rpm_get_port(ap); 320 spin_lock_irqsave(ap->lock, flags); 321 322 em_ctl = readl(mmio + HOST_EM_CTL); 323 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT || 324 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) { 325 spin_unlock_irqrestore(ap->lock, flags); 326 ahci_rpm_put_port(ap); 327 return -EINVAL; 328 } 329 330 if (!(em_ctl & EM_CTL_MR)) { 331 spin_unlock_irqrestore(ap->lock, flags); 332 ahci_rpm_put_port(ap); 333 return -EAGAIN; 334 } 335 336 if (!(em_ctl & EM_CTL_SMB)) 337 em_mmio += hpriv->em_buf_sz; 338 339 count = hpriv->em_buf_sz; 340 341 /* the count should not be larger than PAGE_SIZE */ 342 if (count > PAGE_SIZE) { 343 if (printk_ratelimit()) 344 ata_port_warn(ap, 345 "EM read buffer size too large: " 346 "buffer size %u, page size %lu\n", 347 hpriv->em_buf_sz, PAGE_SIZE); 348 count = PAGE_SIZE; 349 } 350 351 for (i = 0; i < count; i += 4) { 352 msg = readl(em_mmio + i); 353 buf[i] = msg & 0xff; 354 buf[i + 1] = (msg >> 8) & 0xff; 355 buf[i + 2] = (msg >> 16) & 0xff; 356 buf[i + 3] = (msg >> 24) & 0xff; 357 } 358 359 spin_unlock_irqrestore(ap->lock, flags); 360 ahci_rpm_put_port(ap); 361 362 return i; 363 } 364 365 static ssize_t ahci_store_em_buffer(struct device *dev, 366 struct device_attribute *attr, 367 const char *buf, size_t size) 368 { 369 struct Scsi_Host *shost = class_to_shost(dev); 370 struct ata_port *ap = ata_shost_to_port(shost); 371 struct ahci_host_priv *hpriv = ap->host->private_data; 372 void __iomem *mmio = hpriv->mmio; 373 void __iomem *em_mmio = mmio + hpriv->em_loc; 374 const unsigned char *msg_buf = buf; 375 u32 em_ctl, msg; 376 unsigned long flags; 377 int i; 378 379 /* check size validity */ 380 if (!(ap->flags & ATA_FLAG_EM) || 381 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) || 382 size % 4 || size > hpriv->em_buf_sz) 383 return -EINVAL; 384 385 ahci_rpm_get_port(ap); 386 spin_lock_irqsave(ap->lock, flags); 387 388 em_ctl = readl(mmio + HOST_EM_CTL); 389 if (em_ctl & EM_CTL_TM) { 390 spin_unlock_irqrestore(ap->lock, flags); 391 ahci_rpm_put_port(ap); 392 return -EBUSY; 393 } 394 395 for (i = 0; i < size; i += 4) { 396 msg = msg_buf[i] | msg_buf[i + 1] << 8 | 397 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24; 398 writel(msg, em_mmio + i); 399 } 400 401 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 402 403 spin_unlock_irqrestore(ap->lock, flags); 404 ahci_rpm_put_port(ap); 405 406 return size; 407 } 408 409 static ssize_t ahci_show_em_supported(struct device *dev, 410 struct device_attribute *attr, char *buf) 411 { 412 struct Scsi_Host *shost = class_to_shost(dev); 413 struct ata_port *ap = ata_shost_to_port(shost); 414 struct ahci_host_priv *hpriv = ap->host->private_data; 415 void __iomem *mmio = hpriv->mmio; 416 u32 em_ctl; 417 418 ahci_rpm_get_port(ap); 419 em_ctl = readl(mmio + HOST_EM_CTL); 420 ahci_rpm_put_port(ap); 421 422 return sprintf(buf, "%s%s%s%s\n", 423 em_ctl & EM_CTL_LED ? "led " : "", 424 em_ctl & EM_CTL_SAFTE ? "saf-te " : "", 425 em_ctl & EM_CTL_SES ? "ses-2 " : "", 426 em_ctl & EM_CTL_SGPIO ? "sgpio " : ""); 427 } 428 429 /** 430 * ahci_save_initial_config - Save and fixup initial config values 431 * @dev: target AHCI device 432 * @hpriv: host private area to store config values 433 * 434 * Some registers containing configuration info might be setup by 435 * BIOS and might be cleared on reset. This function saves the 436 * initial values of those registers into @hpriv such that they 437 * can be restored after controller reset. 438 * 439 * If inconsistent, config values are fixed up by this function. 440 * 441 * If it is not set already this function sets hpriv->start_engine to 442 * ahci_start_engine. 443 * 444 * LOCKING: 445 * None. 446 */ 447 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv) 448 { 449 void __iomem *mmio = hpriv->mmio; 450 void __iomem *port_mmio; 451 unsigned long port_map; 452 u32 cap, cap2, vers; 453 int i; 454 455 /* make sure AHCI mode is enabled before accessing CAP */ 456 ahci_enable_ahci(mmio); 457 458 /* 459 * Values prefixed with saved_ are written back to the HBA and ports 460 * registers after reset. Values without are used for driver operation. 461 */ 462 463 /* 464 * Override HW-init HBA capability fields with the platform-specific 465 * values. The rest of the HBA capabilities are defined as Read-only 466 * and can't be modified in CSR anyway. 467 */ 468 cap = readl(mmio + HOST_CAP); 469 if (hpriv->saved_cap) 470 cap = (cap & ~(HOST_CAP_SSS | HOST_CAP_MPS)) | hpriv->saved_cap; 471 hpriv->saved_cap = cap; 472 473 /* CAP2 register is only defined for AHCI 1.2 and later */ 474 vers = readl(mmio + HOST_VERSION); 475 if ((vers >> 16) > 1 || 476 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) 477 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); 478 else 479 hpriv->saved_cap2 = cap2 = 0; 480 481 /* some chips have errata preventing 64bit use */ 482 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { 483 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n"); 484 cap &= ~HOST_CAP_64; 485 } 486 487 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { 488 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n"); 489 cap &= ~HOST_CAP_NCQ; 490 } 491 492 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { 493 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n"); 494 cap |= HOST_CAP_NCQ; 495 } 496 497 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 498 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n"); 499 cap &= ~HOST_CAP_PMP; 500 } 501 502 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) { 503 dev_info(dev, 504 "controller can't do SNTF, turning off CAP_SNTF\n"); 505 cap &= ~HOST_CAP_SNTF; 506 } 507 508 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) { 509 dev_info(dev, 510 "controller can't do DEVSLP, turning off\n"); 511 cap2 &= ~HOST_CAP2_SDS; 512 cap2 &= ~HOST_CAP2_SADM; 513 } 514 515 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) { 516 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n"); 517 cap |= HOST_CAP_FBS; 518 } 519 520 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) { 521 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n"); 522 cap &= ~HOST_CAP_FBS; 523 } 524 525 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) { 526 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n"); 527 cap |= HOST_CAP_ALPM; 528 } 529 530 if ((cap & HOST_CAP_SXS) && (hpriv->flags & AHCI_HFLAG_NO_SXS)) { 531 dev_info(dev, "controller does not support SXS, disabling CAP_SXS\n"); 532 cap &= ~HOST_CAP_SXS; 533 } 534 535 /* Override the HBA ports mapping if the platform needs it */ 536 port_map = readl(mmio + HOST_PORTS_IMPL); 537 if (hpriv->saved_port_map && port_map != hpriv->saved_port_map) { 538 dev_info(dev, "forcing port_map 0x%lx -> 0x%x\n", 539 port_map, hpriv->saved_port_map); 540 port_map = hpriv->saved_port_map; 541 } else { 542 hpriv->saved_port_map = port_map; 543 } 544 545 /* mask_port_map not set means that all ports are available */ 546 if (hpriv->mask_port_map) { 547 dev_warn(dev, "masking port_map 0x%lx -> 0x%lx\n", 548 port_map, 549 port_map & hpriv->mask_port_map); 550 port_map &= hpriv->mask_port_map; 551 } 552 553 /* cross check port_map and cap.n_ports */ 554 if (port_map) { 555 int map_ports = hweight_long(port_map); 556 557 /* If PI has more ports than n_ports, whine, clear 558 * port_map and let it be generated from n_ports. 559 */ 560 if (map_ports > ahci_nr_ports(cap)) { 561 dev_warn(dev, 562 "implemented port map (0x%lx) contains more ports than nr_ports (%u), using nr_ports\n", 563 port_map, ahci_nr_ports(cap)); 564 port_map = 0; 565 } 566 } 567 568 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */ 569 if (!port_map && vers < 0x10300) { 570 port_map = (1 << ahci_nr_ports(cap)) - 1; 571 dev_warn(dev, "forcing PORTS_IMPL to 0x%lx\n", port_map); 572 573 /* write the fixed up value to the PI register */ 574 hpriv->saved_port_map = port_map; 575 } 576 577 /* 578 * Preserve the ports capabilities defined by the platform. Note there 579 * is no need in storing the rest of the P#.CMD fields since they are 580 * volatile. 581 */ 582 for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) { 583 if (hpriv->saved_port_cap[i]) 584 continue; 585 586 port_mmio = __ahci_port_base(hpriv, i); 587 hpriv->saved_port_cap[i] = 588 readl(port_mmio + PORT_CMD) & PORT_CMD_CAP; 589 } 590 591 /* record values to use during operation */ 592 hpriv->cap = cap; 593 hpriv->cap2 = cap2; 594 hpriv->version = vers; 595 hpriv->port_map = port_map; 596 597 if (!hpriv->start_engine) 598 hpriv->start_engine = ahci_start_engine; 599 600 if (!hpriv->stop_engine) 601 hpriv->stop_engine = ahci_stop_engine; 602 603 if (!hpriv->irq_handler) 604 hpriv->irq_handler = ahci_single_level_irq_intr; 605 } 606 EXPORT_SYMBOL_GPL(ahci_save_initial_config); 607 608 /** 609 * ahci_restore_initial_config - Restore initial config 610 * @host: target ATA host 611 * 612 * Restore initial config stored by ahci_save_initial_config(). 613 * 614 * LOCKING: 615 * None. 616 */ 617 static void ahci_restore_initial_config(struct ata_host *host) 618 { 619 struct ahci_host_priv *hpriv = host->private_data; 620 unsigned long port_map = hpriv->port_map; 621 void __iomem *mmio = hpriv->mmio; 622 void __iomem *port_mmio; 623 int i; 624 625 writel(hpriv->saved_cap, mmio + HOST_CAP); 626 if (hpriv->saved_cap2) 627 writel(hpriv->saved_cap2, mmio + HOST_CAP2); 628 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 629 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 630 631 for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) { 632 port_mmio = __ahci_port_base(hpriv, i); 633 writel(hpriv->saved_port_cap[i], port_mmio + PORT_CMD); 634 } 635 } 636 637 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) 638 { 639 static const int offset[] = { 640 [SCR_STATUS] = PORT_SCR_STAT, 641 [SCR_CONTROL] = PORT_SCR_CTL, 642 [SCR_ERROR] = PORT_SCR_ERR, 643 [SCR_ACTIVE] = PORT_SCR_ACT, 644 [SCR_NOTIFICATION] = PORT_SCR_NTF, 645 }; 646 struct ahci_host_priv *hpriv = ap->host->private_data; 647 648 if (sc_reg < ARRAY_SIZE(offset) && 649 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) 650 return offset[sc_reg]; 651 return 0; 652 } 653 654 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 655 { 656 void __iomem *port_mmio = ahci_port_base(link->ap); 657 int offset = ahci_scr_offset(link->ap, sc_reg); 658 659 if (offset) { 660 *val = readl(port_mmio + offset); 661 return 0; 662 } 663 return -EINVAL; 664 } 665 666 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 667 { 668 void __iomem *port_mmio = ahci_port_base(link->ap); 669 int offset = ahci_scr_offset(link->ap, sc_reg); 670 671 if (offset) { 672 writel(val, port_mmio + offset); 673 return 0; 674 } 675 return -EINVAL; 676 } 677 678 void ahci_start_engine(struct ata_port *ap) 679 { 680 void __iomem *port_mmio = ahci_port_base(ap); 681 u32 tmp; 682 683 /* start DMA */ 684 tmp = readl(port_mmio + PORT_CMD); 685 tmp |= PORT_CMD_START; 686 writel(tmp, port_mmio + PORT_CMD); 687 readl(port_mmio + PORT_CMD); /* flush */ 688 } 689 EXPORT_SYMBOL_GPL(ahci_start_engine); 690 691 int ahci_stop_engine(struct ata_port *ap) 692 { 693 void __iomem *port_mmio = ahci_port_base(ap); 694 struct ahci_host_priv *hpriv = ap->host->private_data; 695 u32 tmp; 696 697 /* 698 * On some controllers, stopping a port's DMA engine while the port 699 * is in ALPM state (partial or slumber) results in failures on 700 * subsequent DMA engine starts. For those controllers, put the 701 * port back in active state before stopping its DMA engine. 702 */ 703 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) && 704 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) && 705 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) { 706 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n"); 707 return -EIO; 708 } 709 710 tmp = readl(port_mmio + PORT_CMD); 711 712 /* check if the HBA is idle */ 713 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 714 return 0; 715 716 /* 717 * Don't try to issue commands but return with ENODEV if the 718 * AHCI controller not available anymore (e.g. due to PCIe hot 719 * unplugging). Otherwise a 500ms delay for each port is added. 720 */ 721 if (tmp == 0xffffffff) { 722 dev_err(ap->host->dev, "AHCI controller unavailable!\n"); 723 return -ENODEV; 724 } 725 726 /* setting HBA to idle */ 727 tmp &= ~PORT_CMD_START; 728 writel(tmp, port_mmio + PORT_CMD); 729 730 /* wait for engine to stop. This could be as long as 500 msec */ 731 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 732 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 733 if (tmp & PORT_CMD_LIST_ON) 734 return -EIO; 735 736 return 0; 737 } 738 EXPORT_SYMBOL_GPL(ahci_stop_engine); 739 740 void ahci_start_fis_rx(struct ata_port *ap) 741 { 742 void __iomem *port_mmio = ahci_port_base(ap); 743 struct ahci_host_priv *hpriv = ap->host->private_data; 744 struct ahci_port_priv *pp = ap->private_data; 745 u32 tmp; 746 747 /* set FIS registers */ 748 if (hpriv->cap & HOST_CAP_64) 749 writel((pp->cmd_slot_dma >> 16) >> 16, 750 port_mmio + PORT_LST_ADDR_HI); 751 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 752 753 if (hpriv->cap & HOST_CAP_64) 754 writel((pp->rx_fis_dma >> 16) >> 16, 755 port_mmio + PORT_FIS_ADDR_HI); 756 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 757 758 /* enable FIS reception */ 759 tmp = readl(port_mmio + PORT_CMD); 760 tmp |= PORT_CMD_FIS_RX; 761 writel(tmp, port_mmio + PORT_CMD); 762 763 /* flush */ 764 readl(port_mmio + PORT_CMD); 765 } 766 EXPORT_SYMBOL_GPL(ahci_start_fis_rx); 767 768 static int ahci_stop_fis_rx(struct ata_port *ap) 769 { 770 void __iomem *port_mmio = ahci_port_base(ap); 771 u32 tmp; 772 773 /* disable FIS reception */ 774 tmp = readl(port_mmio + PORT_CMD); 775 tmp &= ~PORT_CMD_FIS_RX; 776 writel(tmp, port_mmio + PORT_CMD); 777 778 /* wait for completion, spec says 500ms, give it 1000 */ 779 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 780 PORT_CMD_FIS_ON, 10, 1000); 781 if (tmp & PORT_CMD_FIS_ON) 782 return -EBUSY; 783 784 return 0; 785 } 786 787 static void ahci_power_up(struct ata_port *ap) 788 { 789 struct ahci_host_priv *hpriv = ap->host->private_data; 790 void __iomem *port_mmio = ahci_port_base(ap); 791 u32 cmd; 792 793 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 794 795 /* spin up device */ 796 if (hpriv->cap & HOST_CAP_SSS) { 797 cmd |= PORT_CMD_SPIN_UP; 798 writel(cmd, port_mmio + PORT_CMD); 799 } 800 801 /* wake up link */ 802 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 803 } 804 805 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 806 unsigned int hints) 807 { 808 struct ata_port *ap = link->ap; 809 struct ahci_host_priv *hpriv = ap->host->private_data; 810 struct ahci_port_priv *pp = ap->private_data; 811 void __iomem *port_mmio = ahci_port_base(ap); 812 813 if (policy != ATA_LPM_MAX_POWER) { 814 /* wakeup flag only applies to the max power policy */ 815 hints &= ~ATA_LPM_WAKE_ONLY; 816 817 /* 818 * Disable interrupts on Phy Ready. This keeps us from 819 * getting woken up due to spurious phy ready 820 * interrupts. 821 */ 822 pp->intr_mask &= ~PORT_IRQ_PHYRDY; 823 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 824 825 sata_link_scr_lpm(link, policy, false); 826 } 827 828 if (hpriv->cap & HOST_CAP_ALPM) { 829 u32 cmd = readl(port_mmio + PORT_CMD); 830 831 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) { 832 if (!(hints & ATA_LPM_WAKE_ONLY)) 833 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE); 834 cmd |= PORT_CMD_ICC_ACTIVE; 835 836 writel(cmd, port_mmio + PORT_CMD); 837 readl(port_mmio + PORT_CMD); 838 839 /* wait 10ms to be sure we've come out of LPM state */ 840 ata_msleep(ap, 10); 841 842 if (hints & ATA_LPM_WAKE_ONLY) 843 return 0; 844 } else { 845 cmd |= PORT_CMD_ALPE; 846 if (policy == ATA_LPM_MIN_POWER) 847 cmd |= PORT_CMD_ASP; 848 else if (policy == ATA_LPM_MIN_POWER_WITH_PARTIAL) 849 cmd &= ~PORT_CMD_ASP; 850 851 /* write out new cmd value */ 852 writel(cmd, port_mmio + PORT_CMD); 853 } 854 } 855 856 /* set aggressive device sleep */ 857 if ((hpriv->cap2 & HOST_CAP2_SDS) && 858 (hpriv->cap2 & HOST_CAP2_SADM) && 859 (link->device->flags & ATA_DFLAG_DEVSLP)) { 860 if (policy == ATA_LPM_MIN_POWER || 861 policy == ATA_LPM_MIN_POWER_WITH_PARTIAL) 862 ahci_set_aggressive_devslp(ap, true); 863 else 864 ahci_set_aggressive_devslp(ap, false); 865 } 866 867 if (policy == ATA_LPM_MAX_POWER) { 868 sata_link_scr_lpm(link, policy, false); 869 870 /* turn PHYRDY IRQ back on */ 871 pp->intr_mask |= PORT_IRQ_PHYRDY; 872 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 873 } 874 875 return 0; 876 } 877 878 #ifdef CONFIG_PM 879 static void ahci_power_down(struct ata_port *ap) 880 { 881 struct ahci_host_priv *hpriv = ap->host->private_data; 882 void __iomem *port_mmio = ahci_port_base(ap); 883 u32 cmd, scontrol; 884 885 if (!(hpriv->cap & HOST_CAP_SSS)) 886 return; 887 888 /* put device into listen mode, first set PxSCTL.DET to 0 */ 889 scontrol = readl(port_mmio + PORT_SCR_CTL); 890 scontrol &= ~0xf; 891 writel(scontrol, port_mmio + PORT_SCR_CTL); 892 893 /* then set PxCMD.SUD to 0 */ 894 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 895 cmd &= ~PORT_CMD_SPIN_UP; 896 writel(cmd, port_mmio + PORT_CMD); 897 } 898 #endif 899 900 static void ahci_start_port(struct ata_port *ap) 901 { 902 struct ahci_host_priv *hpriv = ap->host->private_data; 903 struct ahci_port_priv *pp = ap->private_data; 904 struct ata_link *link; 905 struct ahci_em_priv *emp; 906 ssize_t rc; 907 int i; 908 909 /* enable FIS reception */ 910 ahci_start_fis_rx(ap); 911 912 /* enable DMA */ 913 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE)) 914 hpriv->start_engine(ap); 915 916 /* turn on LEDs */ 917 if (ap->flags & ATA_FLAG_EM) { 918 ata_for_each_link(link, ap, EDGE) { 919 emp = &pp->em_priv[link->pmp]; 920 921 /* EM Transmit bit maybe busy during init */ 922 for (i = 0; i < EM_MAX_RETRY; i++) { 923 rc = ap->ops->transmit_led_message(ap, 924 emp->led_state, 925 4); 926 /* 927 * If busy, give a breather but do not 928 * release EH ownership by using msleep() 929 * instead of ata_msleep(). EM Transmit 930 * bit is busy for the whole host and 931 * releasing ownership will cause other 932 * ports to fail the same way. 933 */ 934 if (rc == -EBUSY) 935 msleep(1); 936 else 937 break; 938 } 939 } 940 } 941 942 if (ap->flags & ATA_FLAG_SW_ACTIVITY) 943 ata_for_each_link(link, ap, EDGE) 944 ahci_init_sw_activity(link); 945 946 } 947 948 static int ahci_deinit_port(struct ata_port *ap, const char **emsg) 949 { 950 int rc; 951 struct ahci_host_priv *hpriv = ap->host->private_data; 952 953 /* disable DMA */ 954 rc = hpriv->stop_engine(ap); 955 if (rc) { 956 *emsg = "failed to stop engine"; 957 return rc; 958 } 959 960 /* disable FIS reception */ 961 rc = ahci_stop_fis_rx(ap); 962 if (rc) { 963 *emsg = "failed stop FIS RX"; 964 return rc; 965 } 966 967 return 0; 968 } 969 970 int ahci_reset_controller(struct ata_host *host) 971 { 972 struct ahci_host_priv *hpriv = host->private_data; 973 void __iomem *mmio = hpriv->mmio; 974 u32 tmp; 975 976 /* 977 * We must be in AHCI mode, before using anything AHCI-specific, such 978 * as HOST_RESET. 979 */ 980 ahci_enable_ahci(mmio); 981 982 /* Global controller reset */ 983 if (ahci_skip_host_reset) { 984 dev_info(host->dev, "Skipping global host reset\n"); 985 return 0; 986 } 987 988 tmp = readl(mmio + HOST_CTL); 989 if (!(tmp & HOST_RESET)) { 990 writel(tmp | HOST_RESET, mmio + HOST_CTL); 991 readl(mmio + HOST_CTL); /* flush */ 992 } 993 994 /* 995 * To perform host reset, OS should set HOST_RESET and poll until this 996 * bit is read to be "0". Reset must complete within 1 second, or the 997 * hardware should be considered fried. 998 */ 999 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET, 1000 HOST_RESET, 10, 1000); 1001 if (tmp & HOST_RESET) { 1002 dev_err(host->dev, "Controller reset failed (0x%x)\n", 1003 tmp); 1004 return -EIO; 1005 } 1006 1007 /* Turn on AHCI mode */ 1008 ahci_enable_ahci(mmio); 1009 1010 /* Some registers might be cleared on reset. Restore initial values. */ 1011 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO)) 1012 ahci_restore_initial_config(host); 1013 1014 return 0; 1015 } 1016 EXPORT_SYMBOL_GPL(ahci_reset_controller); 1017 1018 static void ahci_sw_activity(struct ata_link *link) 1019 { 1020 struct ata_port *ap = link->ap; 1021 struct ahci_port_priv *pp = ap->private_data; 1022 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1023 1024 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) 1025 return; 1026 1027 emp->activity++; 1028 if (!timer_pending(&emp->timer)) 1029 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); 1030 } 1031 1032 static void ahci_sw_activity_blink(struct timer_list *t) 1033 { 1034 struct ahci_em_priv *emp = timer_container_of(emp, t, timer); 1035 struct ata_link *link = emp->link; 1036 struct ata_port *ap = link->ap; 1037 1038 unsigned long led_message = emp->led_state; 1039 u32 activity_led_state; 1040 unsigned long flags; 1041 1042 led_message &= EM_MSG_LED_VALUE; 1043 led_message |= ap->port_no | (link->pmp << 8); 1044 1045 /* check to see if we've had activity. If so, 1046 * toggle state of LED and reset timer. If not, 1047 * turn LED to desired idle state. 1048 */ 1049 spin_lock_irqsave(ap->lock, flags); 1050 if (emp->saved_activity != emp->activity) { 1051 emp->saved_activity = emp->activity; 1052 /* get the current LED state */ 1053 activity_led_state = led_message & EM_MSG_LED_VALUE_ON; 1054 1055 if (activity_led_state) 1056 activity_led_state = 0; 1057 else 1058 activity_led_state = 1; 1059 1060 /* clear old state */ 1061 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1062 1063 /* toggle state */ 1064 led_message |= (activity_led_state << 16); 1065 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); 1066 } else { 1067 /* switch to idle */ 1068 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1069 if (emp->blink_policy == BLINK_OFF) 1070 led_message |= (1 << 16); 1071 } 1072 spin_unlock_irqrestore(ap->lock, flags); 1073 ap->ops->transmit_led_message(ap, led_message, 4); 1074 } 1075 1076 static void ahci_init_sw_activity(struct ata_link *link) 1077 { 1078 struct ata_port *ap = link->ap; 1079 struct ahci_port_priv *pp = ap->private_data; 1080 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1081 1082 /* init activity stats, setup timer */ 1083 emp->saved_activity = emp->activity = 0; 1084 emp->link = link; 1085 timer_setup(&emp->timer, ahci_sw_activity_blink, 0); 1086 1087 /* check our blink policy and set flag for link if it's enabled */ 1088 if (emp->blink_policy) 1089 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1090 } 1091 1092 int ahci_reset_em(struct ata_host *host) 1093 { 1094 struct ahci_host_priv *hpriv = host->private_data; 1095 void __iomem *mmio = hpriv->mmio; 1096 u32 em_ctl; 1097 1098 em_ctl = readl(mmio + HOST_EM_CTL); 1099 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) 1100 return -EINVAL; 1101 1102 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); 1103 return 0; 1104 } 1105 EXPORT_SYMBOL_GPL(ahci_reset_em); 1106 1107 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 1108 ssize_t size) 1109 { 1110 struct ahci_host_priv *hpriv = ap->host->private_data; 1111 struct ahci_port_priv *pp = ap->private_data; 1112 void __iomem *mmio = hpriv->mmio; 1113 u32 em_ctl; 1114 u32 message[] = {0, 0}; 1115 unsigned long flags; 1116 int pmp; 1117 struct ahci_em_priv *emp; 1118 1119 /* get the slot number from the message */ 1120 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1121 if (pmp < EM_MAX_SLOTS) 1122 emp = &pp->em_priv[pmp]; 1123 else 1124 return -EINVAL; 1125 1126 ahci_rpm_get_port(ap); 1127 spin_lock_irqsave(ap->lock, flags); 1128 1129 /* 1130 * if we are still busy transmitting a previous message, 1131 * do not allow 1132 */ 1133 em_ctl = readl(mmio + HOST_EM_CTL); 1134 if (em_ctl & EM_CTL_TM) { 1135 spin_unlock_irqrestore(ap->lock, flags); 1136 ahci_rpm_put_port(ap); 1137 return -EBUSY; 1138 } 1139 1140 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) { 1141 /* 1142 * create message header - this is all zero except for 1143 * the message size, which is 4 bytes. 1144 */ 1145 message[0] |= (4 << 8); 1146 1147 /* ignore 0:4 of byte zero, fill in port info yourself */ 1148 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); 1149 1150 /* write message to EM_LOC */ 1151 writel(message[0], mmio + hpriv->em_loc); 1152 writel(message[1], mmio + hpriv->em_loc+4); 1153 1154 /* 1155 * tell hardware to transmit the message 1156 */ 1157 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 1158 } 1159 1160 /* save off new led state for port/slot */ 1161 emp->led_state = state; 1162 1163 spin_unlock_irqrestore(ap->lock, flags); 1164 ahci_rpm_put_port(ap); 1165 1166 return size; 1167 } 1168 1169 static ssize_t ahci_led_show(struct ata_port *ap, char *buf) 1170 { 1171 struct ahci_port_priv *pp = ap->private_data; 1172 struct ata_link *link; 1173 struct ahci_em_priv *emp; 1174 int rc = 0; 1175 1176 ata_for_each_link(link, ap, EDGE) { 1177 emp = &pp->em_priv[link->pmp]; 1178 rc += sprintf(buf, "%lx\n", emp->led_state); 1179 } 1180 return rc; 1181 } 1182 1183 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 1184 size_t size) 1185 { 1186 unsigned int state; 1187 int pmp; 1188 struct ahci_port_priv *pp = ap->private_data; 1189 struct ahci_em_priv *emp; 1190 1191 if (kstrtouint(buf, 0, &state) < 0) 1192 return -EINVAL; 1193 1194 /* get the slot number from the message */ 1195 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1196 if (pmp < EM_MAX_SLOTS) { 1197 pmp = array_index_nospec(pmp, EM_MAX_SLOTS); 1198 emp = &pp->em_priv[pmp]; 1199 } else { 1200 return -EINVAL; 1201 } 1202 1203 /* mask off the activity bits if we are in sw_activity 1204 * mode, user should turn off sw_activity before setting 1205 * activity led through em_message 1206 */ 1207 if (emp->blink_policy) 1208 state &= ~EM_MSG_LED_VALUE_ACTIVITY; 1209 1210 return ap->ops->transmit_led_message(ap, state, size); 1211 } 1212 1213 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) 1214 { 1215 struct ata_link *link = dev->link; 1216 struct ata_port *ap = link->ap; 1217 struct ahci_port_priv *pp = ap->private_data; 1218 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1219 u32 port_led_state = emp->led_state; 1220 1221 /* save the desired Activity LED behavior */ 1222 if (val == OFF) { 1223 /* clear LFLAG */ 1224 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); 1225 1226 /* set the LED to OFF */ 1227 port_led_state &= EM_MSG_LED_VALUE_OFF; 1228 port_led_state |= (ap->port_no | (link->pmp << 8)); 1229 ap->ops->transmit_led_message(ap, port_led_state, 4); 1230 } else { 1231 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1232 if (val == BLINK_OFF) { 1233 /* set LED to ON for idle */ 1234 port_led_state &= EM_MSG_LED_VALUE_OFF; 1235 port_led_state |= (ap->port_no | (link->pmp << 8)); 1236 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ 1237 ap->ops->transmit_led_message(ap, port_led_state, 4); 1238 } 1239 } 1240 emp->blink_policy = val; 1241 return 0; 1242 } 1243 1244 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) 1245 { 1246 struct ata_link *link = dev->link; 1247 struct ata_port *ap = link->ap; 1248 struct ahci_port_priv *pp = ap->private_data; 1249 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1250 1251 /* display the saved value of activity behavior for this 1252 * disk. 1253 */ 1254 return sprintf(buf, "%d\n", emp->blink_policy); 1255 } 1256 1257 static void ahci_port_clear_pending_irq(struct ata_port *ap) 1258 { 1259 struct ahci_host_priv *hpriv = ap->host->private_data; 1260 void __iomem *port_mmio = ahci_port_base(ap); 1261 u32 tmp; 1262 1263 /* clear SError */ 1264 tmp = readl(port_mmio + PORT_SCR_ERR); 1265 dev_dbg(ap->host->dev, "PORT_SCR_ERR 0x%x\n", tmp); 1266 writel(tmp, port_mmio + PORT_SCR_ERR); 1267 1268 /* clear port IRQ */ 1269 tmp = readl(port_mmio + PORT_IRQ_STAT); 1270 dev_dbg(ap->host->dev, "PORT_IRQ_STAT 0x%x\n", tmp); 1271 if (tmp) 1272 writel(tmp, port_mmio + PORT_IRQ_STAT); 1273 1274 writel(1 << ap->port_no, hpriv->mmio + HOST_IRQ_STAT); 1275 } 1276 1277 static void ahci_port_init(struct device *dev, struct ata_port *ap, 1278 int port_no, void __iomem *mmio, 1279 void __iomem *port_mmio) 1280 { 1281 const char *emsg = NULL; 1282 int rc; 1283 1284 /* make sure port is not active */ 1285 rc = ahci_deinit_port(ap, &emsg); 1286 if (rc) 1287 dev_warn(dev, "%s (%d)\n", emsg, rc); 1288 1289 ahci_port_clear_pending_irq(ap); 1290 } 1291 1292 void ahci_init_controller(struct ata_host *host) 1293 { 1294 struct ahci_host_priv *hpriv = host->private_data; 1295 void __iomem *mmio = hpriv->mmio; 1296 int i; 1297 void __iomem *port_mmio; 1298 u32 tmp; 1299 1300 for (i = 0; i < host->n_ports; i++) { 1301 struct ata_port *ap = host->ports[i]; 1302 1303 port_mmio = ahci_port_base(ap); 1304 if (ata_port_is_dummy(ap)) 1305 continue; 1306 1307 ahci_port_init(host->dev, ap, i, mmio, port_mmio); 1308 } 1309 1310 tmp = readl(mmio + HOST_CTL); 1311 dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp); 1312 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 1313 tmp = readl(mmio + HOST_CTL); 1314 dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp); 1315 } 1316 EXPORT_SYMBOL_GPL(ahci_init_controller); 1317 1318 static void ahci_dev_config(struct ata_device *dev) 1319 { 1320 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; 1321 1322 if ((dev->class == ATA_DEV_ATAPI) && 1323 (hpriv->flags & AHCI_HFLAG_ATAPI_DMA_QUIRK)) 1324 dev->quirks |= ATA_QUIRK_ATAPI_MOD16_DMA; 1325 1326 if (hpriv->flags & AHCI_HFLAG_SECT255) { 1327 dev->max_sectors = 255; 1328 ata_dev_info(dev, 1329 "SB600 AHCI: limiting to 255 sectors per cmd\n"); 1330 } 1331 } 1332 1333 unsigned int ahci_dev_classify(struct ata_port *ap) 1334 { 1335 void __iomem *port_mmio = ahci_port_base(ap); 1336 struct ata_taskfile tf; 1337 u32 tmp; 1338 1339 tmp = readl(port_mmio + PORT_SIG); 1340 tf.lbah = (tmp >> 24) & 0xff; 1341 tf.lbam = (tmp >> 16) & 0xff; 1342 tf.lbal = (tmp >> 8) & 0xff; 1343 tf.nsect = (tmp) & 0xff; 1344 1345 return ata_port_classify(ap, &tf); 1346 } 1347 EXPORT_SYMBOL_GPL(ahci_dev_classify); 1348 1349 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 1350 u32 opts) 1351 { 1352 dma_addr_t cmd_tbl_dma; 1353 1354 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 1355 1356 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 1357 pp->cmd_slot[tag].status = 0; 1358 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 1359 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 1360 } 1361 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot); 1362 1363 int ahci_kick_engine(struct ata_port *ap) 1364 { 1365 void __iomem *port_mmio = ahci_port_base(ap); 1366 struct ahci_host_priv *hpriv = ap->host->private_data; 1367 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1368 u32 tmp; 1369 int busy, rc; 1370 1371 /* stop engine */ 1372 rc = hpriv->stop_engine(ap); 1373 if (rc) 1374 goto out_restart; 1375 1376 /* need to do CLO? 1377 * always do CLO if PMP is attached (AHCI-1.3 9.2) 1378 */ 1379 busy = status & (ATA_BUSY | ATA_DRQ); 1380 if (!busy && !sata_pmp_attached(ap)) { 1381 rc = 0; 1382 goto out_restart; 1383 } 1384 1385 if (!(hpriv->cap & HOST_CAP_CLO)) { 1386 rc = -EOPNOTSUPP; 1387 goto out_restart; 1388 } 1389 1390 /* perform CLO */ 1391 tmp = readl(port_mmio + PORT_CMD); 1392 tmp |= PORT_CMD_CLO; 1393 writel(tmp, port_mmio + PORT_CMD); 1394 1395 rc = 0; 1396 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 1397 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 1398 if (tmp & PORT_CMD_CLO) 1399 rc = -EIO; 1400 1401 /* restart engine */ 1402 out_restart: 1403 hpriv->start_engine(ap); 1404 return rc; 1405 } 1406 EXPORT_SYMBOL_GPL(ahci_kick_engine); 1407 1408 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, 1409 struct ata_taskfile *tf, int is_cmd, u16 flags, 1410 unsigned int timeout_msec) 1411 { 1412 const u32 cmd_fis_len = 5; /* five dwords */ 1413 struct ahci_port_priv *pp = ap->private_data; 1414 void __iomem *port_mmio = ahci_port_base(ap); 1415 u8 *fis = pp->cmd_tbl; 1416 u32 tmp; 1417 1418 /* prep the command */ 1419 ata_tf_to_fis(tf, pmp, is_cmd, fis); 1420 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); 1421 1422 /* set port value for softreset of Port Multiplier */ 1423 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) { 1424 tmp = readl(port_mmio + PORT_FBS); 1425 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 1426 tmp |= pmp << PORT_FBS_DEV_OFFSET; 1427 writel(tmp, port_mmio + PORT_FBS); 1428 pp->fbs_last_dev = pmp; 1429 } 1430 1431 /* issue & wait */ 1432 writel(1, port_mmio + PORT_CMD_ISSUE); 1433 1434 if (timeout_msec) { 1435 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE, 1436 0x1, 0x1, 1, timeout_msec); 1437 if (tmp & 0x1) { 1438 ahci_kick_engine(ap); 1439 return -EBUSY; 1440 } 1441 } else 1442 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1443 1444 return 0; 1445 } 1446 1447 int ahci_do_softreset(struct ata_link *link, unsigned int *class, 1448 int pmp, unsigned long deadline, 1449 int (*check_ready)(struct ata_link *link)) 1450 { 1451 struct ata_port *ap = link->ap; 1452 struct ahci_host_priv *hpriv = ap->host->private_data; 1453 struct ahci_port_priv *pp = ap->private_data; 1454 const char *reason = NULL; 1455 unsigned long now; 1456 unsigned int msecs; 1457 struct ata_taskfile tf; 1458 bool fbs_disabled = false; 1459 int rc; 1460 1461 /* prepare for SRST (AHCI-1.1 10.4.1) */ 1462 rc = ahci_kick_engine(ap); 1463 if (rc && rc != -EOPNOTSUPP) 1464 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc); 1465 1466 /* 1467 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall 1468 * clear PxFBS.EN to '0' prior to issuing software reset to devices 1469 * that is attached to port multiplier. 1470 */ 1471 if (!ata_is_host_link(link) && pp->fbs_enabled) { 1472 ahci_disable_fbs(ap); 1473 fbs_disabled = true; 1474 } 1475 1476 ata_tf_init(link->device, &tf); 1477 1478 /* issue the first H2D Register FIS */ 1479 msecs = 0; 1480 now = jiffies; 1481 if (time_after(deadline, now)) 1482 msecs = jiffies_to_msecs(deadline - now); 1483 1484 tf.ctl |= ATA_SRST; 1485 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, 1486 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { 1487 rc = -EIO; 1488 reason = "1st FIS failed"; 1489 goto fail; 1490 } 1491 1492 /* spec says at least 5us, but be generous and sleep for 1ms */ 1493 ata_msleep(ap, 1); 1494 1495 /* issue the second H2D Register FIS */ 1496 tf.ctl &= ~ATA_SRST; 1497 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1498 1499 /* wait for link to become ready */ 1500 rc = ata_wait_after_reset(link, deadline, check_ready); 1501 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { 1502 /* 1503 * Workaround for cases where link online status can't 1504 * be trusted. Treat device readiness timeout as link 1505 * offline. 1506 */ 1507 ata_link_info(link, "device not ready, treating as offline\n"); 1508 *class = ATA_DEV_NONE; 1509 } else if (rc) { 1510 /* link occupied, -ENODEV too is an error */ 1511 reason = "device not ready"; 1512 goto fail; 1513 } else 1514 *class = ahci_dev_classify(ap); 1515 1516 /* re-enable FBS if disabled before */ 1517 if (fbs_disabled) 1518 ahci_enable_fbs(ap); 1519 1520 return 0; 1521 1522 fail: 1523 ata_link_err(link, "softreset failed (%s)\n", reason); 1524 return rc; 1525 } 1526 EXPORT_SYMBOL_GPL(ahci_do_softreset); 1527 1528 int ahci_check_ready(struct ata_link *link) 1529 { 1530 void __iomem *port_mmio = ahci_port_base(link->ap); 1531 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1532 1533 return ata_check_ready(status); 1534 } 1535 EXPORT_SYMBOL_GPL(ahci_check_ready); 1536 1537 static int ahci_softreset(struct ata_link *link, unsigned int *class, 1538 unsigned long deadline) 1539 { 1540 int pmp = sata_srst_pmp(link); 1541 1542 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 1543 } 1544 1545 static int ahci_bad_pmp_check_ready(struct ata_link *link) 1546 { 1547 void __iomem *port_mmio = ahci_port_base(link->ap); 1548 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1549 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT); 1550 1551 /* 1552 * There is no need to check TFDATA if BAD PMP is found due to HW bug, 1553 * which can save timeout delay. 1554 */ 1555 if (irq_status & PORT_IRQ_BAD_PMP) 1556 return -EIO; 1557 1558 return ata_check_ready(status); 1559 } 1560 1561 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 1562 unsigned long deadline) 1563 { 1564 struct ata_port *ap = link->ap; 1565 void __iomem *port_mmio = ahci_port_base(ap); 1566 int pmp = sata_srst_pmp(link); 1567 int rc; 1568 u32 irq_sts; 1569 1570 rc = ahci_do_softreset(link, class, pmp, deadline, 1571 ahci_bad_pmp_check_ready); 1572 1573 /* 1574 * Soft reset fails with IPMS set when PMP is enabled but 1575 * SATA HDD/ODD is connected to SATA port, do soft reset 1576 * again to port 0. 1577 */ 1578 if (rc == -EIO) { 1579 irq_sts = readl(port_mmio + PORT_IRQ_STAT); 1580 if (irq_sts & PORT_IRQ_BAD_PMP) { 1581 ata_link_warn(link, 1582 "applying PMP SRST workaround " 1583 "and retrying\n"); 1584 rc = ahci_do_softreset(link, class, 0, deadline, 1585 ahci_check_ready); 1586 } 1587 } 1588 1589 return rc; 1590 } 1591 1592 int ahci_do_hardreset(struct ata_link *link, unsigned int *class, 1593 unsigned long deadline, bool *online) 1594 { 1595 const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context); 1596 struct ata_port *ap = link->ap; 1597 struct ahci_port_priv *pp = ap->private_data; 1598 struct ahci_host_priv *hpriv = ap->host->private_data; 1599 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1600 struct ata_taskfile tf; 1601 int rc; 1602 1603 hpriv->stop_engine(ap); 1604 1605 /* clear D2H reception area to properly wait for D2H FIS */ 1606 ata_tf_init(link->device, &tf); 1607 tf.status = ATA_BUSY; 1608 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1609 1610 ahci_port_clear_pending_irq(ap); 1611 1612 rc = sata_link_hardreset(link, timing, deadline, online, 1613 ahci_check_ready); 1614 1615 hpriv->start_engine(ap); 1616 1617 if (*online) 1618 *class = ahci_dev_classify(ap); 1619 1620 return rc; 1621 } 1622 EXPORT_SYMBOL_GPL(ahci_do_hardreset); 1623 1624 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1625 unsigned long deadline) 1626 { 1627 bool online; 1628 1629 return ahci_do_hardreset(link, class, deadline, &online); 1630 } 1631 1632 static void ahci_postreset(struct ata_link *link, unsigned int *class) 1633 { 1634 struct ata_port *ap = link->ap; 1635 void __iomem *port_mmio = ahci_port_base(ap); 1636 u32 new_tmp, tmp; 1637 1638 ata_std_postreset(link, class); 1639 1640 /* Make sure port's ATAPI bit is set appropriately */ 1641 new_tmp = tmp = readl(port_mmio + PORT_CMD); 1642 if (*class == ATA_DEV_ATAPI) 1643 new_tmp |= PORT_CMD_ATAPI; 1644 else 1645 new_tmp &= ~PORT_CMD_ATAPI; 1646 if (new_tmp != tmp) { 1647 writel(new_tmp, port_mmio + PORT_CMD); 1648 readl(port_mmio + PORT_CMD); /* flush */ 1649 } 1650 } 1651 1652 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 1653 { 1654 struct scatterlist *sg; 1655 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 1656 unsigned int si; 1657 1658 /* 1659 * Next, the S/G list. 1660 */ 1661 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1662 dma_addr_t addr = sg_dma_address(sg); 1663 u32 sg_len = sg_dma_len(sg); 1664 1665 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 1666 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 1667 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); 1668 } 1669 1670 return si; 1671 } 1672 1673 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) 1674 { 1675 struct ata_port *ap = qc->ap; 1676 struct ahci_port_priv *pp = ap->private_data; 1677 1678 if (!sata_pmp_attached(ap) || pp->fbs_enabled) 1679 return ata_std_qc_defer(qc); 1680 else 1681 return sata_pmp_qc_defer_cmd_switch(qc); 1682 } 1683 1684 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc) 1685 { 1686 struct ata_port *ap = qc->ap; 1687 struct ahci_port_priv *pp = ap->private_data; 1688 int is_atapi = ata_is_atapi(qc->tf.protocol); 1689 void *cmd_tbl; 1690 u32 opts; 1691 const u32 cmd_fis_len = 5; /* five dwords */ 1692 unsigned int n_elem; 1693 1694 /* 1695 * Fill in command table information. First, the header, 1696 * a SATA Register - Host to Device command FIS. 1697 */ 1698 cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ; 1699 1700 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 1701 if (is_atapi) { 1702 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1703 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1704 } 1705 1706 n_elem = 0; 1707 if (qc->flags & ATA_QCFLAG_DMAMAP) 1708 n_elem = ahci_fill_sg(qc, cmd_tbl); 1709 1710 /* 1711 * Fill in command slot information. 1712 */ 1713 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); 1714 if (qc->tf.flags & ATA_TFLAG_WRITE) 1715 opts |= AHCI_CMD_WRITE; 1716 if (is_atapi) 1717 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1718 1719 ahci_fill_cmd_slot(pp, qc->hw_tag, opts); 1720 1721 return AC_ERR_OK; 1722 } 1723 1724 static void ahci_fbs_dec_intr(struct ata_port *ap) 1725 { 1726 struct ahci_port_priv *pp = ap->private_data; 1727 void __iomem *port_mmio = ahci_port_base(ap); 1728 u32 fbs = readl(port_mmio + PORT_FBS); 1729 int retries = 3; 1730 1731 BUG_ON(!pp->fbs_enabled); 1732 1733 /* time to wait for DEC is not specified by AHCI spec, 1734 * add a retry loop for safety. 1735 */ 1736 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); 1737 fbs = readl(port_mmio + PORT_FBS); 1738 while ((fbs & PORT_FBS_DEC) && retries--) { 1739 udelay(1); 1740 fbs = readl(port_mmio + PORT_FBS); 1741 } 1742 1743 if (fbs & PORT_FBS_DEC) 1744 dev_err(ap->host->dev, "failed to clear device error\n"); 1745 } 1746 1747 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1748 { 1749 struct ahci_host_priv *hpriv = ap->host->private_data; 1750 struct ahci_port_priv *pp = ap->private_data; 1751 struct ata_eh_info *host_ehi = &ap->link.eh_info; 1752 struct ata_link *link = NULL; 1753 struct ata_queued_cmd *active_qc; 1754 struct ata_eh_info *active_ehi; 1755 bool fbs_need_dec = false; 1756 u32 serror; 1757 1758 /* determine active link with error */ 1759 if (pp->fbs_enabled) { 1760 void __iomem *port_mmio = ahci_port_base(ap); 1761 u32 fbs = readl(port_mmio + PORT_FBS); 1762 int pmp = fbs >> PORT_FBS_DWE_OFFSET; 1763 1764 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) { 1765 link = &ap->pmp_link[pmp]; 1766 fbs_need_dec = true; 1767 } 1768 1769 } else 1770 ata_for_each_link(link, ap, EDGE) 1771 if (ata_link_active(link)) 1772 break; 1773 1774 if (!link) 1775 link = &ap->link; 1776 1777 active_qc = ata_qc_from_tag(ap, link->active_tag); 1778 active_ehi = &link->eh_info; 1779 1780 /* record irq stat */ 1781 ata_ehi_clear_desc(host_ehi); 1782 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); 1783 1784 /* AHCI needs SError cleared; otherwise, it might lock up */ 1785 ahci_scr_read(&ap->link, SCR_ERROR, &serror); 1786 ahci_scr_write(&ap->link, SCR_ERROR, serror); 1787 host_ehi->serror |= serror; 1788 1789 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1790 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) 1791 irq_stat &= ~PORT_IRQ_IF_ERR; 1792 1793 if (irq_stat & PORT_IRQ_TF_ERR) { 1794 /* If qc is active, charge it; otherwise, the active 1795 * link. There's no active qc on NCQ errors. It will 1796 * be determined by EH by reading log page 10h. 1797 */ 1798 if (active_qc) 1799 active_qc->err_mask |= AC_ERR_DEV; 1800 else 1801 active_ehi->err_mask |= AC_ERR_DEV; 1802 1803 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) 1804 host_ehi->serror &= ~SERR_INTERNAL; 1805 } 1806 1807 if (irq_stat & PORT_IRQ_UNK_FIS) { 1808 u32 *unk = pp->rx_fis + RX_FIS_UNK; 1809 1810 active_ehi->err_mask |= AC_ERR_HSM; 1811 active_ehi->action |= ATA_EH_RESET; 1812 ata_ehi_push_desc(active_ehi, 1813 "unknown FIS %08x %08x %08x %08x" , 1814 unk[0], unk[1], unk[2], unk[3]); 1815 } 1816 1817 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { 1818 active_ehi->err_mask |= AC_ERR_HSM; 1819 active_ehi->action |= ATA_EH_RESET; 1820 ata_ehi_push_desc(active_ehi, "incorrect PMP"); 1821 } 1822 1823 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 1824 host_ehi->err_mask |= AC_ERR_HOST_BUS; 1825 host_ehi->action |= ATA_EH_RESET; 1826 ata_ehi_push_desc(host_ehi, "host bus error"); 1827 } 1828 1829 if (irq_stat & PORT_IRQ_IF_ERR) { 1830 if (fbs_need_dec) 1831 active_ehi->err_mask |= AC_ERR_DEV; 1832 else { 1833 host_ehi->err_mask |= AC_ERR_ATA_BUS; 1834 host_ehi->action |= ATA_EH_RESET; 1835 } 1836 1837 ata_ehi_push_desc(host_ehi, "interface fatal error"); 1838 } 1839 1840 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 1841 ata_ehi_hotplugged(host_ehi); 1842 ata_ehi_push_desc(host_ehi, "%s", 1843 irq_stat & PORT_IRQ_CONNECT ? 1844 "connection status changed" : "PHY RDY changed"); 1845 } 1846 1847 /* okay, let's hand over to EH */ 1848 1849 if (irq_stat & PORT_IRQ_FREEZE) 1850 ata_port_freeze(ap); 1851 else if (fbs_need_dec) { 1852 ata_link_abort(link); 1853 ahci_fbs_dec_intr(ap); 1854 } else 1855 ata_port_abort(ap); 1856 } 1857 1858 static void ahci_qc_complete(struct ata_port *ap, void __iomem *port_mmio) 1859 { 1860 struct ata_eh_info *ehi = &ap->link.eh_info; 1861 struct ahci_port_priv *pp = ap->private_data; 1862 u32 qc_active = 0; 1863 int rc; 1864 1865 /* 1866 * pp->active_link is not reliable once FBS is enabled, both 1867 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because 1868 * NCQ and non-NCQ commands may be in flight at the same time. 1869 */ 1870 if (pp->fbs_enabled) { 1871 if (ap->qc_active) { 1872 qc_active = readl(port_mmio + PORT_SCR_ACT); 1873 qc_active |= readl(port_mmio + PORT_CMD_ISSUE); 1874 } 1875 } else { 1876 /* pp->active_link is valid iff any command is in flight */ 1877 if (ap->qc_active && pp->active_link->sactive) 1878 qc_active = readl(port_mmio + PORT_SCR_ACT); 1879 else 1880 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 1881 } 1882 1883 rc = ata_qc_complete_multiple(ap, qc_active); 1884 if (unlikely(rc < 0 && !(ap->pflags & ATA_PFLAG_RESETTING))) { 1885 ehi->err_mask |= AC_ERR_HSM; 1886 ehi->action |= ATA_EH_RESET; 1887 ata_port_freeze(ap); 1888 } 1889 } 1890 1891 static void ahci_handle_port_interrupt(struct ata_port *ap, 1892 void __iomem *port_mmio, u32 status) 1893 { 1894 struct ahci_port_priv *pp = ap->private_data; 1895 struct ahci_host_priv *hpriv = ap->host->private_data; 1896 1897 /* ignore BAD_PMP while resetting */ 1898 if (unlikely(ap->pflags & ATA_PFLAG_RESETTING)) 1899 status &= ~PORT_IRQ_BAD_PMP; 1900 1901 if (sata_lpm_ignore_phy_events(&ap->link)) { 1902 status &= ~PORT_IRQ_PHYRDY; 1903 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG); 1904 } 1905 1906 if (unlikely(status & PORT_IRQ_ERROR)) { 1907 /* 1908 * Before getting the error notification, we may have 1909 * received SDB FISes notifying successful completions. 1910 * Handle these first and then handle the error. 1911 */ 1912 ahci_qc_complete(ap, port_mmio); 1913 ahci_error_intr(ap, status); 1914 return; 1915 } 1916 1917 if (status & PORT_IRQ_SDB_FIS) { 1918 /* If SNotification is available, leave notification 1919 * handling to sata_async_notification(). If not, 1920 * emulate it by snooping SDB FIS RX area. 1921 * 1922 * Snooping FIS RX area is probably cheaper than 1923 * poking SNotification but some constrollers which 1924 * implement SNotification, ICH9 for example, don't 1925 * store AN SDB FIS into receive area. 1926 */ 1927 if (hpriv->cap & HOST_CAP_SNTF) 1928 sata_async_notification(ap); 1929 else { 1930 /* If the 'N' bit in word 0 of the FIS is set, 1931 * we just received asynchronous notification. 1932 * Tell libata about it. 1933 * 1934 * Lack of SNotification should not appear in 1935 * ahci 1.2, so the workaround is unnecessary 1936 * when FBS is enabled. 1937 */ 1938 if (pp->fbs_enabled) 1939 WARN_ON_ONCE(1); 1940 else { 1941 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 1942 u32 f0 = le32_to_cpu(f[0]); 1943 if (f0 & (1 << 15)) 1944 sata_async_notification(ap); 1945 } 1946 } 1947 } 1948 1949 /* Handle completed commands */ 1950 ahci_qc_complete(ap, port_mmio); 1951 } 1952 1953 static void ahci_port_intr(struct ata_port *ap) 1954 { 1955 void __iomem *port_mmio = ahci_port_base(ap); 1956 u32 status; 1957 1958 status = readl(port_mmio + PORT_IRQ_STAT); 1959 writel(status, port_mmio + PORT_IRQ_STAT); 1960 1961 ahci_handle_port_interrupt(ap, port_mmio, status); 1962 } 1963 1964 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance) 1965 { 1966 struct ata_port *ap = dev_instance; 1967 void __iomem *port_mmio = ahci_port_base(ap); 1968 u32 status; 1969 1970 status = readl(port_mmio + PORT_IRQ_STAT); 1971 writel(status, port_mmio + PORT_IRQ_STAT); 1972 1973 spin_lock(ap->lock); 1974 ahci_handle_port_interrupt(ap, port_mmio, status); 1975 spin_unlock(ap->lock); 1976 1977 return IRQ_HANDLED; 1978 } 1979 1980 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked) 1981 { 1982 unsigned int i, handled = 0; 1983 1984 for (i = 0; i < host->n_ports; i++) { 1985 struct ata_port *ap; 1986 1987 if (!(irq_masked & (1 << i))) 1988 continue; 1989 1990 ap = host->ports[i]; 1991 if (ap) { 1992 ahci_port_intr(ap); 1993 } else { 1994 if (ata_ratelimit()) 1995 dev_warn(host->dev, 1996 "interrupt on disabled port %u\n", i); 1997 } 1998 1999 handled = 1; 2000 } 2001 2002 return handled; 2003 } 2004 EXPORT_SYMBOL_GPL(ahci_handle_port_intr); 2005 2006 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance) 2007 { 2008 struct ata_host *host = dev_instance; 2009 struct ahci_host_priv *hpriv; 2010 unsigned int rc = 0; 2011 void __iomem *mmio; 2012 u32 irq_stat, irq_masked; 2013 2014 hpriv = host->private_data; 2015 mmio = hpriv->mmio; 2016 2017 /* sigh. 0xffffffff is a valid return from h/w */ 2018 irq_stat = readl(mmio + HOST_IRQ_STAT); 2019 if (!irq_stat) 2020 return IRQ_NONE; 2021 2022 irq_masked = irq_stat & hpriv->port_map; 2023 2024 spin_lock(&host->lock); 2025 2026 rc = ahci_handle_port_intr(host, irq_masked); 2027 2028 /* HOST_IRQ_STAT behaves as level triggered latch meaning that 2029 * it should be cleared after all the port events are cleared; 2030 * otherwise, it will raise a spurious interrupt after each 2031 * valid one. Please read section 10.6.2 of ahci 1.1 for more 2032 * information. 2033 * 2034 * Also, use the unmasked value to clear interrupt as spurious 2035 * pending event on a dummy port might cause screaming IRQ. 2036 */ 2037 writel(irq_stat, mmio + HOST_IRQ_STAT); 2038 2039 spin_unlock(&host->lock); 2040 2041 return IRQ_RETVAL(rc); 2042 } 2043 2044 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 2045 { 2046 struct ata_port *ap = qc->ap; 2047 void __iomem *port_mmio = ahci_port_base(ap); 2048 struct ahci_port_priv *pp = ap->private_data; 2049 2050 /* Keep track of the currently active link. It will be used 2051 * in completion path to determine whether NCQ phase is in 2052 * progress. 2053 */ 2054 pp->active_link = qc->dev->link; 2055 2056 if (ata_is_ncq(qc->tf.protocol)) 2057 writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT); 2058 2059 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) { 2060 u32 fbs = readl(port_mmio + PORT_FBS); 2061 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 2062 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; 2063 writel(fbs, port_mmio + PORT_FBS); 2064 pp->fbs_last_dev = qc->dev->link->pmp; 2065 } 2066 2067 writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE); 2068 2069 ahci_sw_activity(qc->dev->link); 2070 2071 return 0; 2072 } 2073 EXPORT_SYMBOL_GPL(ahci_qc_issue); 2074 2075 static void ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 2076 { 2077 struct ahci_port_priv *pp = qc->ap->private_data; 2078 u8 *rx_fis = pp->rx_fis; 2079 2080 if (pp->fbs_enabled) 2081 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; 2082 2083 /* 2084 * After a successful execution of an ATA PIO data-in command, 2085 * the device doesn't send D2H Reg FIS to update the TF and 2086 * the host should take TF and E_Status from the preceding PIO 2087 * Setup FIS. 2088 */ 2089 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && 2090 !(qc->flags & ATA_QCFLAG_EH)) { 2091 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); 2092 qc->result_tf.status = (rx_fis + RX_FIS_PIO_SETUP)[15]; 2093 return; 2094 } 2095 2096 /* 2097 * For NCQ commands, we never get a D2H FIS, so reading the D2H Register 2098 * FIS area of the Received FIS Structure (which contains a copy of the 2099 * last D2H FIS received) will contain an outdated status code. 2100 * For NCQ commands, we instead get a SDB FIS, so read the SDB FIS area 2101 * instead. However, the SDB FIS does not contain the LBA, so we can't 2102 * use the ata_tf_from_fis() helper. 2103 */ 2104 if (ata_is_ncq(qc->tf.protocol)) { 2105 const u8 *fis = rx_fis + RX_FIS_SDB; 2106 2107 /* 2108 * Successful NCQ commands have been filled already. 2109 * A failed NCQ command will read the status here. 2110 * (Note that a failed NCQ command will get a more specific 2111 * error when reading the NCQ Command Error log.) 2112 */ 2113 qc->result_tf.status = fis[2]; 2114 qc->result_tf.error = fis[3]; 2115 return; 2116 } 2117 2118 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); 2119 } 2120 2121 static void ahci_qc_ncq_fill_rtf(struct ata_port *ap, u64 done_mask) 2122 { 2123 struct ahci_port_priv *pp = ap->private_data; 2124 const u8 *fis; 2125 2126 /* No outstanding commands. */ 2127 if (!ap->qc_active) 2128 return; 2129 2130 /* 2131 * FBS not enabled, so read status and error once, since they are shared 2132 * for all QCs. 2133 */ 2134 if (!pp->fbs_enabled) { 2135 u8 status, error; 2136 2137 /* No outstanding NCQ commands. */ 2138 if (!pp->active_link->sactive) 2139 return; 2140 2141 fis = pp->rx_fis + RX_FIS_SDB; 2142 status = fis[2]; 2143 error = fis[3]; 2144 2145 while (done_mask) { 2146 struct ata_queued_cmd *qc; 2147 unsigned int tag = __ffs64(done_mask); 2148 2149 qc = ata_qc_from_tag(ap, tag); 2150 if (qc && ata_is_ncq(qc->tf.protocol)) { 2151 qc->result_tf.status = status; 2152 qc->result_tf.error = error; 2153 qc->result_tf.flags = qc->tf.flags; 2154 qc->flags |= ATA_QCFLAG_RTF_FILLED; 2155 } 2156 done_mask &= ~(1ULL << tag); 2157 } 2158 2159 return; 2160 } 2161 2162 /* 2163 * FBS enabled, so read the status and error for each QC, since the QCs 2164 * can belong to different PMP links. (Each PMP link has its own FIS 2165 * Receive Area.) 2166 */ 2167 while (done_mask) { 2168 struct ata_queued_cmd *qc; 2169 unsigned int tag = __ffs64(done_mask); 2170 2171 qc = ata_qc_from_tag(ap, tag); 2172 if (qc && ata_is_ncq(qc->tf.protocol)) { 2173 fis = pp->rx_fis; 2174 fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; 2175 fis += RX_FIS_SDB; 2176 qc->result_tf.status = fis[2]; 2177 qc->result_tf.error = fis[3]; 2178 qc->result_tf.flags = qc->tf.flags; 2179 qc->flags |= ATA_QCFLAG_RTF_FILLED; 2180 } 2181 done_mask &= ~(1ULL << tag); 2182 } 2183 } 2184 2185 static void ahci_freeze(struct ata_port *ap) 2186 { 2187 void __iomem *port_mmio = ahci_port_base(ap); 2188 2189 /* turn IRQ off */ 2190 writel(0, port_mmio + PORT_IRQ_MASK); 2191 } 2192 2193 static void ahci_thaw(struct ata_port *ap) 2194 { 2195 struct ahci_host_priv *hpriv = ap->host->private_data; 2196 void __iomem *mmio = hpriv->mmio; 2197 void __iomem *port_mmio = ahci_port_base(ap); 2198 u32 tmp; 2199 struct ahci_port_priv *pp = ap->private_data; 2200 2201 /* clear IRQ */ 2202 tmp = readl(port_mmio + PORT_IRQ_STAT); 2203 writel(tmp, port_mmio + PORT_IRQ_STAT); 2204 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 2205 2206 /* turn IRQ back on */ 2207 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2208 } 2209 2210 void ahci_error_handler(struct ata_port *ap) 2211 __must_hold(&ap->host->eh_mutex) 2212 { 2213 struct ahci_host_priv *hpriv = ap->host->private_data; 2214 2215 if (!ata_port_is_frozen(ap)) { 2216 /* restart engine */ 2217 hpriv->stop_engine(ap); 2218 hpriv->start_engine(ap); 2219 } 2220 2221 sata_pmp_error_handler(ap); 2222 2223 if (!ata_dev_enabled(ap->link.device)) 2224 hpriv->stop_engine(ap); 2225 } 2226 EXPORT_SYMBOL_GPL(ahci_error_handler); 2227 2228 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 2229 { 2230 struct ata_port *ap = qc->ap; 2231 2232 /* make DMA engine forget about the failed command */ 2233 if (qc->flags & ATA_QCFLAG_EH) 2234 ahci_kick_engine(ap); 2235 } 2236 2237 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep) 2238 { 2239 struct ahci_host_priv *hpriv = ap->host->private_data; 2240 void __iomem *port_mmio = ahci_port_base(ap); 2241 struct ata_device *dev = ap->link.device; 2242 u32 devslp, dm, dito, mdat, deto, dito_conf; 2243 int rc; 2244 unsigned int err_mask; 2245 2246 devslp = readl(port_mmio + PORT_DEVSLP); 2247 if (!(devslp & PORT_DEVSLP_DSP)) { 2248 dev_info(ap->host->dev, "port does not support device sleep\n"); 2249 return; 2250 } 2251 2252 /* disable device sleep */ 2253 if (!sleep) { 2254 if (devslp & PORT_DEVSLP_ADSE) { 2255 writel(devslp & ~PORT_DEVSLP_ADSE, 2256 port_mmio + PORT_DEVSLP); 2257 err_mask = ata_dev_set_feature(dev, 2258 SETFEATURES_SATA_DISABLE, 2259 SATA_DEVSLP); 2260 if (err_mask && err_mask != AC_ERR_DEV) 2261 ata_dev_warn(dev, "failed to disable DEVSLP\n"); 2262 } 2263 return; 2264 } 2265 2266 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET; 2267 dito = devslp_idle_timeout / (dm + 1); 2268 if (dito > 0x3ff) 2269 dito = 0x3ff; 2270 2271 dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF; 2272 2273 /* device sleep was already enabled and same dito */ 2274 if ((devslp & PORT_DEVSLP_ADSE) && (dito_conf == dito)) 2275 return; 2276 2277 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */ 2278 rc = hpriv->stop_engine(ap); 2279 if (rc) 2280 return; 2281 2282 /* Use the nominal value 10 ms if the read MDAT is zero, 2283 * the nominal value of DETO is 20 ms. 2284 */ 2285 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] & 2286 ATA_LOG_DEVSLP_VALID_MASK) { 2287 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] & 2288 ATA_LOG_DEVSLP_MDAT_MASK; 2289 if (!mdat) 2290 mdat = 10; 2291 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO]; 2292 if (!deto) 2293 deto = 20; 2294 } else { 2295 mdat = 10; 2296 deto = 20; 2297 } 2298 2299 /* Make dito, mdat, deto bits to 0s */ 2300 devslp &= ~GENMASK_ULL(24, 2); 2301 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) | 2302 (mdat << PORT_DEVSLP_MDAT_OFFSET) | 2303 (deto << PORT_DEVSLP_DETO_OFFSET) | 2304 PORT_DEVSLP_ADSE); 2305 writel(devslp, port_mmio + PORT_DEVSLP); 2306 2307 hpriv->start_engine(ap); 2308 2309 /* enable device sleep feature for the drive */ 2310 err_mask = ata_dev_set_feature(dev, 2311 SETFEATURES_SATA_ENABLE, 2312 SATA_DEVSLP); 2313 if (err_mask && err_mask != AC_ERR_DEV) 2314 ata_dev_warn(dev, "failed to enable DEVSLP\n"); 2315 } 2316 2317 static void ahci_enable_fbs(struct ata_port *ap) 2318 { 2319 struct ahci_host_priv *hpriv = ap->host->private_data; 2320 struct ahci_port_priv *pp = ap->private_data; 2321 void __iomem *port_mmio = ahci_port_base(ap); 2322 u32 fbs; 2323 int rc; 2324 2325 if (!pp->fbs_supported) 2326 return; 2327 2328 fbs = readl(port_mmio + PORT_FBS); 2329 if (fbs & PORT_FBS_EN) { 2330 pp->fbs_enabled = true; 2331 pp->fbs_last_dev = -1; /* initialization */ 2332 return; 2333 } 2334 2335 rc = hpriv->stop_engine(ap); 2336 if (rc) 2337 return; 2338 2339 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); 2340 fbs = readl(port_mmio + PORT_FBS); 2341 if (fbs & PORT_FBS_EN) { 2342 dev_info(ap->host->dev, "FBS is enabled\n"); 2343 pp->fbs_enabled = true; 2344 pp->fbs_last_dev = -1; /* initialization */ 2345 } else 2346 dev_err(ap->host->dev, "Failed to enable FBS\n"); 2347 2348 hpriv->start_engine(ap); 2349 } 2350 2351 static void ahci_disable_fbs(struct ata_port *ap) 2352 { 2353 struct ahci_host_priv *hpriv = ap->host->private_data; 2354 struct ahci_port_priv *pp = ap->private_data; 2355 void __iomem *port_mmio = ahci_port_base(ap); 2356 u32 fbs; 2357 int rc; 2358 2359 if (!pp->fbs_supported) 2360 return; 2361 2362 fbs = readl(port_mmio + PORT_FBS); 2363 if ((fbs & PORT_FBS_EN) == 0) { 2364 pp->fbs_enabled = false; 2365 return; 2366 } 2367 2368 rc = hpriv->stop_engine(ap); 2369 if (rc) 2370 return; 2371 2372 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); 2373 fbs = readl(port_mmio + PORT_FBS); 2374 if (fbs & PORT_FBS_EN) 2375 dev_err(ap->host->dev, "Failed to disable FBS\n"); 2376 else { 2377 dev_info(ap->host->dev, "FBS is disabled\n"); 2378 pp->fbs_enabled = false; 2379 } 2380 2381 hpriv->start_engine(ap); 2382 } 2383 2384 static void ahci_pmp_attach(struct ata_port *ap) 2385 { 2386 void __iomem *port_mmio = ahci_port_base(ap); 2387 struct ahci_port_priv *pp = ap->private_data; 2388 u32 cmd; 2389 2390 cmd = readl(port_mmio + PORT_CMD); 2391 cmd |= PORT_CMD_PMP; 2392 writel(cmd, port_mmio + PORT_CMD); 2393 2394 ahci_enable_fbs(ap); 2395 2396 pp->intr_mask |= PORT_IRQ_BAD_PMP; 2397 2398 /* 2399 * We must not change the port interrupt mask register if the 2400 * port is marked frozen, the value in pp->intr_mask will be 2401 * restored later when the port is thawed. 2402 * 2403 * Note that during initialization, the port is marked as 2404 * frozen since the irq handler is not yet registered. 2405 */ 2406 if (!ata_port_is_frozen(ap)) 2407 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2408 } 2409 2410 static void ahci_pmp_detach(struct ata_port *ap) 2411 { 2412 void __iomem *port_mmio = ahci_port_base(ap); 2413 struct ahci_port_priv *pp = ap->private_data; 2414 u32 cmd; 2415 2416 ahci_disable_fbs(ap); 2417 2418 cmd = readl(port_mmio + PORT_CMD); 2419 cmd &= ~PORT_CMD_PMP; 2420 writel(cmd, port_mmio + PORT_CMD); 2421 2422 pp->intr_mask &= ~PORT_IRQ_BAD_PMP; 2423 2424 /* see comment above in ahci_pmp_attach() */ 2425 if (!ata_port_is_frozen(ap)) 2426 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2427 } 2428 2429 int ahci_port_resume(struct ata_port *ap) 2430 { 2431 ahci_rpm_get_port(ap); 2432 2433 ahci_power_up(ap); 2434 ahci_start_port(ap); 2435 2436 if (sata_pmp_attached(ap)) 2437 ahci_pmp_attach(ap); 2438 else 2439 ahci_pmp_detach(ap); 2440 2441 return 0; 2442 } 2443 EXPORT_SYMBOL_GPL(ahci_port_resume); 2444 2445 #ifdef CONFIG_PM 2446 static void ahci_handle_s2idle(struct ata_port *ap) 2447 { 2448 void __iomem *port_mmio = ahci_port_base(ap); 2449 u32 devslp; 2450 2451 if (pm_suspend_via_firmware()) 2452 return; 2453 devslp = readl(port_mmio + PORT_DEVSLP); 2454 if ((devslp & PORT_DEVSLP_ADSE)) 2455 ata_msleep(ap, devslp_idle_timeout); 2456 } 2457 2458 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 2459 { 2460 const char *emsg = NULL; 2461 int rc; 2462 2463 rc = ahci_deinit_port(ap, &emsg); 2464 if (rc == 0) 2465 ahci_power_down(ap); 2466 else { 2467 ata_port_err(ap, "%s (%d)\n", emsg, rc); 2468 ata_port_freeze(ap); 2469 } 2470 2471 if (acpi_storage_d3(ap->host->dev)) 2472 ahci_handle_s2idle(ap); 2473 2474 ahci_rpm_put_port(ap); 2475 return rc; 2476 } 2477 #endif 2478 2479 static int ahci_port_start(struct ata_port *ap) 2480 { 2481 struct ahci_host_priv *hpriv = ap->host->private_data; 2482 struct device *dev = ap->host->dev; 2483 struct ahci_port_priv *pp; 2484 void *mem; 2485 dma_addr_t mem_dma; 2486 size_t dma_sz, rx_fis_sz; 2487 2488 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 2489 if (!pp) 2490 return -ENOMEM; 2491 2492 if (ap->host->n_ports > 1) { 2493 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL); 2494 if (!pp->irq_desc) { 2495 devm_kfree(dev, pp); 2496 return -ENOMEM; 2497 } 2498 snprintf(pp->irq_desc, 8, 2499 "%s%d", dev_driver_string(dev), ap->port_no); 2500 } 2501 2502 /* check FBS capability */ 2503 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { 2504 void __iomem *port_mmio = ahci_port_base(ap); 2505 u32 cmd = readl(port_mmio + PORT_CMD); 2506 if (cmd & PORT_CMD_FBSCP) 2507 pp->fbs_supported = true; 2508 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { 2509 dev_info(dev, "port %d can do FBS, forcing FBSCP\n", 2510 ap->port_no); 2511 pp->fbs_supported = true; 2512 } else 2513 dev_warn(dev, "port %d is not capable of FBS\n", 2514 ap->port_no); 2515 } 2516 2517 if (pp->fbs_supported) { 2518 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; 2519 rx_fis_sz = AHCI_RX_FIS_SZ * 16; 2520 } else { 2521 dma_sz = AHCI_PORT_PRIV_DMA_SZ; 2522 rx_fis_sz = AHCI_RX_FIS_SZ; 2523 } 2524 2525 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); 2526 if (!mem) 2527 return -ENOMEM; 2528 2529 /* 2530 * First item in chunk of DMA memory: 32-slot command table, 2531 * 32 bytes each in size 2532 */ 2533 pp->cmd_slot = mem; 2534 pp->cmd_slot_dma = mem_dma; 2535 2536 mem += AHCI_CMD_SLOT_SZ; 2537 mem_dma += AHCI_CMD_SLOT_SZ; 2538 2539 /* 2540 * Second item: Received-FIS area 2541 */ 2542 pp->rx_fis = mem; 2543 pp->rx_fis_dma = mem_dma; 2544 2545 mem += rx_fis_sz; 2546 mem_dma += rx_fis_sz; 2547 2548 /* 2549 * Third item: data area for storing a single command 2550 * and its scatter-gather table 2551 */ 2552 pp->cmd_tbl = mem; 2553 pp->cmd_tbl_dma = mem_dma; 2554 2555 /* 2556 * Save off initial list of interrupts to be enabled. 2557 * This could be changed later 2558 */ 2559 pp->intr_mask = DEF_PORT_IRQ; 2560 2561 /* 2562 * Switch to per-port locking in case each port has its own MSI vector. 2563 */ 2564 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { 2565 spin_lock_init(&pp->lock); 2566 ap->lock = &pp->lock; 2567 } 2568 2569 ap->private_data = pp; 2570 2571 /* engage engines, captain */ 2572 return ahci_port_resume(ap); 2573 } 2574 2575 static void ahci_port_stop(struct ata_port *ap) 2576 { 2577 const char *emsg = NULL; 2578 struct ahci_host_priv *hpriv = ap->host->private_data; 2579 void __iomem *host_mmio = hpriv->mmio; 2580 int rc; 2581 2582 /* de-initialize port */ 2583 rc = ahci_deinit_port(ap, &emsg); 2584 if (rc) 2585 ata_port_warn(ap, "%s (%d)\n", emsg, rc); 2586 2587 /* 2588 * Clear GHC.IS to prevent stuck INTx after disabling MSI and 2589 * re-enabling INTx. 2590 */ 2591 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT); 2592 2593 ahci_rpm_put_port(ap); 2594 } 2595 2596 void ahci_print_info(struct ata_host *host, const char *scc_s) 2597 { 2598 struct ahci_host_priv *hpriv = host->private_data; 2599 u32 vers, cap, cap2, impl, speed; 2600 const char *speed_s; 2601 2602 vers = hpriv->version; 2603 cap = hpriv->cap; 2604 cap2 = hpriv->cap2; 2605 impl = hpriv->port_map; 2606 2607 speed = (cap >> 20) & 0xf; 2608 if (speed == 1) 2609 speed_s = "1.5"; 2610 else if (speed == 2) 2611 speed_s = "3"; 2612 else if (speed == 3) 2613 speed_s = "6"; 2614 else 2615 speed_s = "?"; 2616 2617 dev_info(host->dev, 2618 "AHCI vers %02x%02x.%02x%02x, " 2619 "%u command slots, %s Gbps, %s mode\n" 2620 , 2621 2622 (vers >> 24) & 0xff, 2623 (vers >> 16) & 0xff, 2624 (vers >> 8) & 0xff, 2625 vers & 0xff, 2626 2627 ((cap >> 8) & 0x1f) + 1, 2628 speed_s, 2629 scc_s); 2630 2631 dev_info(host->dev, 2632 "%u/%u ports implemented (port mask 0x%x)\n" 2633 , 2634 2635 hweight32(impl), 2636 ahci_nr_ports(cap), 2637 impl); 2638 2639 dev_info(host->dev, 2640 "flags: " 2641 "%s%s%s%s%s%s%s" 2642 "%s%s%s%s%s%s%s" 2643 "%s%s%s%s%s%s%s" 2644 "%s%s\n" 2645 , 2646 2647 cap & HOST_CAP_64 ? "64bit " : "", 2648 cap & HOST_CAP_NCQ ? "ncq " : "", 2649 cap & HOST_CAP_SNTF ? "sntf " : "", 2650 cap & HOST_CAP_MPS ? "ilck " : "", 2651 cap & HOST_CAP_SSS ? "stag " : "", 2652 cap & HOST_CAP_ALPM ? "pm " : "", 2653 cap & HOST_CAP_LED ? "led " : "", 2654 cap & HOST_CAP_CLO ? "clo " : "", 2655 cap & HOST_CAP_ONLY ? "only " : "", 2656 cap & HOST_CAP_PMP ? "pmp " : "", 2657 cap & HOST_CAP_FBS ? "fbs " : "", 2658 cap & HOST_CAP_PIO_MULTI ? "pio " : "", 2659 cap & HOST_CAP_SSC ? "slum " : "", 2660 cap & HOST_CAP_PART ? "part " : "", 2661 cap & HOST_CAP_CCC ? "ccc " : "", 2662 cap & HOST_CAP_EMS ? "ems " : "", 2663 cap & HOST_CAP_SXS ? "sxs " : "", 2664 cap2 & HOST_CAP2_DESO ? "deso " : "", 2665 cap2 & HOST_CAP2_SADM ? "sadm " : "", 2666 cap2 & HOST_CAP2_SDS ? "sds " : "", 2667 cap2 & HOST_CAP2_APST ? "apst " : "", 2668 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", 2669 cap2 & HOST_CAP2_BOH ? "boh " : "" 2670 ); 2671 } 2672 EXPORT_SYMBOL_GPL(ahci_print_info); 2673 2674 void ahci_set_em_messages(struct ahci_host_priv *hpriv, 2675 struct ata_port_info *pi) 2676 { 2677 u8 messages; 2678 void __iomem *mmio = hpriv->mmio; 2679 u32 em_loc = readl(mmio + HOST_EM_LOC); 2680 u32 em_ctl = readl(mmio + HOST_EM_CTL); 2681 2682 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS)) 2683 return; 2684 2685 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; 2686 2687 if (messages) { 2688 /* store em_loc */ 2689 hpriv->em_loc = ((em_loc >> 16) * 4); 2690 hpriv->em_buf_sz = ((em_loc & 0xff) * 4); 2691 hpriv->em_msg_type = messages; 2692 pi->flags |= ATA_FLAG_EM; 2693 if (!(em_ctl & EM_CTL_ALHD)) 2694 pi->flags |= ATA_FLAG_SW_ACTIVITY; 2695 } 2696 } 2697 EXPORT_SYMBOL_GPL(ahci_set_em_messages); 2698 2699 static int ahci_host_activate_multi_irqs(struct ata_host *host, 2700 const struct scsi_host_template *sht) 2701 { 2702 struct ahci_host_priv *hpriv = host->private_data; 2703 int i, rc; 2704 2705 rc = ata_host_start(host); 2706 if (rc) 2707 return rc; 2708 /* 2709 * Requests IRQs according to AHCI-1.1 when multiple MSIs were 2710 * allocated. That is one MSI per port, starting from @irq. 2711 */ 2712 for (i = 0; i < host->n_ports; i++) { 2713 struct ahci_port_priv *pp = host->ports[i]->private_data; 2714 int irq = hpriv->get_irq_vector(host, i); 2715 2716 /* Do not receive interrupts sent by dummy ports */ 2717 if (!pp) { 2718 disable_irq(irq); 2719 continue; 2720 } 2721 2722 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard, 2723 0, pp->irq_desc, host->ports[i]); 2724 2725 if (rc) 2726 return rc; 2727 ata_port_desc_misc(host->ports[i], irq); 2728 } 2729 2730 return ata_host_register(host, sht); 2731 } 2732 2733 /** 2734 * ahci_host_activate - start AHCI host, request IRQs and register it 2735 * @host: target ATA host 2736 * @sht: scsi_host_template to use when registering the host 2737 * 2738 * LOCKING: 2739 * Inherited from calling layer (may sleep). 2740 * 2741 * RETURNS: 2742 * 0 on success, -errno otherwise. 2743 */ 2744 int ahci_host_activate(struct ata_host *host, const struct scsi_host_template *sht) 2745 { 2746 struct ahci_host_priv *hpriv = host->private_data; 2747 int irq = hpriv->irq; 2748 int rc; 2749 2750 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { 2751 if (hpriv->irq_handler && 2752 hpriv->irq_handler != ahci_single_level_irq_intr) 2753 dev_warn(host->dev, 2754 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n"); 2755 if (!hpriv->get_irq_vector) { 2756 dev_err(host->dev, 2757 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n"); 2758 return -EIO; 2759 } 2760 2761 rc = ahci_host_activate_multi_irqs(host, sht); 2762 } else { 2763 rc = ata_host_activate(host, irq, hpriv->irq_handler, 2764 IRQF_SHARED, sht); 2765 } 2766 2767 2768 return rc; 2769 } 2770 EXPORT_SYMBOL_GPL(ahci_host_activate); 2771 2772 MODULE_AUTHOR("Jeff Garzik"); 2773 MODULE_DESCRIPTION("Common AHCI SATA low-level routines"); 2774 MODULE_LICENSE("GPL"); 2775